/*\r
- FreeRTOS V7.5.3 - Copyright (C) 2013 Real Time Engineers Ltd.\r
- All rights reserved\r
-\r
- VISIT http://www.FreeRTOS.org TO ENSURE YOU ARE USING THE LATEST VERSION.\r
-\r
- ***************************************************************************\r
- * *\r
- * FreeRTOS provides completely free yet professionally developed, *\r
- * robust, strictly quality controlled, supported, and cross *\r
- * platform software that has become a de facto standard. *\r
- * *\r
- * Help yourself get started quickly and support the FreeRTOS *\r
- * project by purchasing a FreeRTOS tutorial book, reference *\r
- * manual, or both from: http://www.FreeRTOS.org/Documentation *\r
- * *\r
- * Thank you! *\r
- * *\r
- ***************************************************************************\r
-\r
- This file is part of the FreeRTOS distribution.\r
-\r
- FreeRTOS is free software; you can redistribute it and/or modify it under\r
- the terms of the GNU General Public License (version 2) as published by the\r
- Free Software Foundation >>!AND MODIFIED BY!<< the FreeRTOS exception.\r
-\r
- >>! NOTE: The modification to the GPL is included to allow you to distribute\r
- >>! a combined work that includes FreeRTOS without being obliged to provide\r
- >>! the source code for proprietary components outside of the FreeRTOS\r
- >>! kernel.\r
-\r
- FreeRTOS is distributed in the hope that it will be useful, but WITHOUT ANY\r
- WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS\r
- FOR A PARTICULAR PURPOSE. Full license text is available from the following\r
- link: http://www.freertos.org/a00114.html\r
-\r
- 1 tab == 4 spaces!\r
-\r
- ***************************************************************************\r
- * *\r
- * Having a problem? Start by reading the FAQ "My application does *\r
- * not run, what could be wrong?" *\r
- * *\r
- * http://www.FreeRTOS.org/FAQHelp.html *\r
- * *\r
- ***************************************************************************\r
-\r
- http://www.FreeRTOS.org - Documentation, books, training, latest versions,\r
- license and Real Time Engineers Ltd. contact details.\r
-\r
- http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products,\r
- including FreeRTOS+Trace - an indispensable productivity tool, a DOS\r
- compatible FAT file system, and our tiny thread aware UDP/IP stack.\r
-\r
- http://www.OpenRTOS.com - Real Time Engineers ltd license FreeRTOS to High\r
- Integrity Systems to sell under the OpenRTOS brand. Low cost OpenRTOS\r
- licenses offer ticketed support, indemnification and middleware.\r
-\r
- http://www.SafeRTOS.com - High Integrity Systems also provide a safety\r
- engineered and independently SIL3 certified version for use in safety and\r
- mission critical applications that require provable dependability.\r
-\r
- 1 tab == 4 spaces!\r
-*/\r
+ * FreeRTOS Kernel V10.0.0\r
+ * Copyright (C) 2017 Amazon.com, Inc. or its affiliates. All Rights Reserved.\r
+ *\r
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of\r
+ * this software and associated documentation files (the "Software"), to deal in\r
+ * the Software without restriction, including without limitation the rights to\r
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of\r
+ * the Software, and to permit persons to whom the Software is furnished to do so,\r
+ * subject to the following conditions:\r
+ *\r
+ * The above copyright notice and this permission notice shall be included in all\r
+ * copies or substantial portions of the Software. If you wish to use our Amazon\r
+ * FreeRTOS name, please do so in a fair use way that does not cause confusion.\r
+ *\r
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR\r
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS\r
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR\r
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER\r
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN\r
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.\r
+ *\r
+ * http://www.FreeRTOS.org\r
+ * http://aws.amazon.com/freertos\r
+ *\r
+ * 1 tab == 4 spaces!\r
+ */\r
\r
/*-----------------------------------------------------------\r
* Implementation of functions defined in portable.h for the ARM CM3 port.\r
\r
#ifndef configSYSTICK_CLOCK_HZ\r
#define configSYSTICK_CLOCK_HZ configCPU_CLOCK_HZ\r
+ /* Ensure the SysTick is clocked at the same frequency as the core. */\r
+ #define portNVIC_SYSTICK_CLK_BIT ( 1UL << 2UL )\r
+#else\r
+ /* The way the SysTick is clocked is not modified in case it is not the same\r
+ as the core. */\r
+ #define portNVIC_SYSTICK_CLK_BIT ( 0 )\r
#endif\r
\r
/* Constants required to manipulate the core. Registers first... */\r
-#define portNVIC_SYSTICK_CTRL_REG ( * ( ( volatile unsigned long * ) 0xe000e010 ) )\r
-#define portNVIC_SYSTICK_LOAD_REG ( * ( ( volatile unsigned long * ) 0xe000e014 ) )\r
-#define portNVIC_SYSTICK_CURRENT_VALUE_REG ( * ( ( volatile unsigned long * ) 0xe000e018 ) )\r
-#define portNVIC_SYSPRI2_REG ( * ( ( volatile unsigned long * ) 0xe000ed20 ) )\r
+#define portNVIC_SYSTICK_CTRL_REG ( * ( ( volatile uint32_t * ) 0xe000e010 ) )\r
+#define portNVIC_SYSTICK_LOAD_REG ( * ( ( volatile uint32_t * ) 0xe000e014 ) )\r
+#define portNVIC_SYSTICK_CURRENT_VALUE_REG ( * ( ( volatile uint32_t * ) 0xe000e018 ) )\r
+#define portNVIC_SYSPRI2_REG ( * ( ( volatile uint32_t * ) 0xe000ed20 ) )\r
/* ...then bits in the registers. */\r
-#define portNVIC_SYSTICK_CLK_BIT ( 1UL << 2UL )\r
#define portNVIC_SYSTICK_INT_BIT ( 1UL << 1UL )\r
#define portNVIC_SYSTICK_ENABLE_BIT ( 1UL << 0UL )\r
#define portNVIC_SYSTICK_COUNT_FLAG_BIT ( 1UL << 16UL )\r
#define portNVIC_PENDSVCLEAR_BIT ( 1UL << 27UL )\r
#define portNVIC_PEND_SYSTICK_CLEAR_BIT ( 1UL << 25UL )\r
\r
-#define portNVIC_PENDSV_PRI ( ( ( unsigned long ) configKERNEL_INTERRUPT_PRIORITY ) << 16UL )\r
-#define portNVIC_SYSTICK_PRI ( ( ( unsigned long ) configKERNEL_INTERRUPT_PRIORITY ) << 24UL )\r
+#define portNVIC_PENDSV_PRI ( ( ( uint32_t ) configKERNEL_INTERRUPT_PRIORITY ) << 16UL )\r
+#define portNVIC_SYSTICK_PRI ( ( ( uint32_t ) configKERNEL_INTERRUPT_PRIORITY ) << 24UL )\r
\r
/* Constants required to check the validity of an interrupt priority. */\r
#define portFIRST_USER_INTERRUPT_NUMBER ( 16 )\r
#define portNVIC_IP_REGISTERS_OFFSET_16 ( 0xE000E3F0 )\r
-#define portAIRCR_REG ( * ( ( volatile unsigned long * ) 0xE000ED0C ) )\r
-#define portMAX_8_BIT_VALUE ( ( unsigned char ) 0xff )\r
-#define portTOP_BIT_OF_BYTE ( ( unsigned char ) 0x80 )\r
-#define portMAX_PRIGROUP_BITS ( ( unsigned char ) 7 )\r
+#define portAIRCR_REG ( * ( ( volatile uint32_t * ) 0xE000ED0C ) )\r
+#define portMAX_8_BIT_VALUE ( ( uint8_t ) 0xff )\r
+#define portTOP_BIT_OF_BYTE ( ( uint8_t ) 0x80 )\r
+#define portMAX_PRIGROUP_BITS ( ( uint8_t ) 7 )\r
#define portPRIORITY_GROUP_MASK ( 0x07UL << 8UL )\r
#define portPRIGROUP_SHIFT ( 8UL )\r
\r
+/* Masks off all bits but the VECTACTIVE bits in the ICSR register. */\r
+#define portVECTACTIVE_MASK ( 0xFFUL )\r
+\r
/* Constants required to set up the initial stack. */\r
#define portINITIAL_XPSR ( 0x01000000UL )\r
\r
calculations. */\r
#define portMISSED_COUNTS_FACTOR ( 45UL )\r
\r
+/* For strict compliance with the Cortex-M spec the task start address should\r
+have bit-0 clear, as it is loaded into the PC on exit from an ISR. */\r
+#define portSTART_ADDRESS_MASK ( ( StackType_t ) 0xfffffffeUL )\r
+\r
/* Let the user override the pre-loading of the initial LR with the address of\r
-prvTaskExitError() in case is messes up unwinding of the stack in the\r
+prvTaskExitError() in case it messes up unwinding of the stack in the\r
debugger. */\r
#ifdef configTASK_RETURN_ADDRESS\r
#define portTASK_RETURN_ADDRESS configTASK_RETURN_ADDRESS\r
#define portTASK_RETURN_ADDRESS prvTaskExitError\r
#endif\r
\r
-/* Each task maintains its own interrupt status in the critical nesting\r
-variable. */\r
-static unsigned portBASE_TYPE uxCriticalNesting = 0xaaaaaaaa;\r
-\r
/*\r
* Setup the timer to generate the tick interrupts. The implementation in this\r
* file is weak to allow application writers to change the timer used to\r
\r
/*-----------------------------------------------------------*/\r
\r
+/* Each task maintains its own interrupt status in the critical nesting\r
+variable. */\r
+static UBaseType_t uxCriticalNesting = 0xaaaaaaaa;\r
+\r
/*\r
* The number of SysTick increments that make up one tick period.\r
*/\r
-#if configUSE_TICKLESS_IDLE == 1\r
- static unsigned long ulTimerCountsForOneTick = 0;\r
+#if( configUSE_TICKLESS_IDLE == 1 )\r
+ static uint32_t ulTimerCountsForOneTick = 0;\r
#endif /* configUSE_TICKLESS_IDLE */\r
\r
/*\r
* The maximum number of tick periods that can be suppressed is limited by the\r
* 24 bit resolution of the SysTick timer.\r
*/\r
-#if configUSE_TICKLESS_IDLE == 1\r
- static unsigned long xMaximumPossibleSuppressedTicks = 0;\r
+#if( configUSE_TICKLESS_IDLE == 1 )\r
+ static uint32_t xMaximumPossibleSuppressedTicks = 0;\r
#endif /* configUSE_TICKLESS_IDLE */\r
\r
/*\r
* Compensate for the CPU cycles that pass while the SysTick is stopped (low\r
* power functionality only.\r
*/\r
-#if configUSE_TICKLESS_IDLE == 1\r
- static unsigned long ulStoppedTimerCompensation = 0;\r
+#if( configUSE_TICKLESS_IDLE == 1 )\r
+ static uint32_t ulStoppedTimerCompensation = 0;\r
#endif /* configUSE_TICKLESS_IDLE */\r
\r
/*\r
* FreeRTOS API functions are not called from interrupts that have been assigned\r
* a priority above configMAX_SYSCALL_INTERRUPT_PRIORITY.\r
*/\r
-#if ( configASSERT_DEFINED == 1 )\r
- static unsigned char ucMaxSysCallPriority = 0;\r
- static unsigned long ulMaxPRIGROUPValue = 0;\r
- static const volatile unsigned char * const pcInterruptPriorityRegisters = ( const volatile unsigned char * const ) portNVIC_IP_REGISTERS_OFFSET_16;\r
+#if( configASSERT_DEFINED == 1 )\r
+ static uint8_t ucMaxSysCallPriority = 0;\r
+ static uint32_t ulMaxPRIGROUPValue = 0;\r
+ static const volatile uint8_t * const pcInterruptPriorityRegisters = ( const volatile uint8_t * const ) portNVIC_IP_REGISTERS_OFFSET_16;\r
#endif /* configASSERT_DEFINED */\r
\r
/*-----------------------------------------------------------*/\r
/*\r
* See header file for description.\r
*/\r
-portSTACK_TYPE *pxPortInitialiseStack( portSTACK_TYPE *pxTopOfStack, pdTASK_CODE pxCode, void *pvParameters )\r
+StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, TaskFunction_t pxCode, void *pvParameters )\r
{\r
/* Simulate the stack frame as it would be created by a context switch\r
interrupt. */\r
pxTopOfStack--; /* Offset added to account for the way the MCU uses the stack on entry/exit of interrupts. */\r
*pxTopOfStack = portINITIAL_XPSR; /* xPSR */\r
pxTopOfStack--;\r
- *pxTopOfStack = ( portSTACK_TYPE ) pxCode; /* PC */\r
+ *pxTopOfStack = ( ( StackType_t ) pxCode ) & portSTART_ADDRESS_MASK; /* PC */\r
pxTopOfStack--;\r
- *pxTopOfStack = ( portSTACK_TYPE ) portTASK_RETURN_ADDRESS; /* LR */\r
+ *pxTopOfStack = ( StackType_t ) portTASK_RETURN_ADDRESS; /* LR */\r
pxTopOfStack -= 5; /* R12, R3, R2 and R1. */\r
- *pxTopOfStack = ( portSTACK_TYPE ) pvParameters; /* R0 */\r
+ *pxTopOfStack = ( StackType_t ) pvParameters; /* R0 */\r
pxTopOfStack -= 8; /* R11, R10, R9, R8, R7, R6, R5 and R4. */\r
\r
return pxTopOfStack;\r
\r
static void prvTaskExitError( void )\r
{\r
+volatile uint32_t ulDummy = 0UL;\r
+\r
/* A function that implements a task must not exit or attempt to return to\r
its caller as there is nothing to return to. If a task wants to exit it\r
should instead call vTaskDelete( NULL ).\r
defined, then stop here so application writers can catch the error. */\r
configASSERT( uxCriticalNesting == ~0UL );\r
portDISABLE_INTERRUPTS();\r
- for( ;; );\r
+ while( ulDummy == 0 )\r
+ {\r
+ /* This file calls prvTaskExitError() after the scheduler has been\r
+ started to remove a compiler warning about the function being defined\r
+ but never called. ulDummy is used purely to quieten other warnings\r
+ about code appearing after this function is called - making ulDummy\r
+ volatile makes the compiler think the function could return and\r
+ therefore not output an 'unreachable code' warning for code that appears\r
+ after it. */\r
+ }\r
}\r
/*-----------------------------------------------------------*/\r
\r
" ldr r0, [r1] \n" /* The first item in pxCurrentTCB is the task top of stack. */\r
" ldmia r0!, {r4-r11} \n" /* Pop the registers that are not automatically saved on exception entry and the critical nesting count. */\r
" msr psp, r0 \n" /* Restore the task stack pointer. */\r
+ " isb \n"\r
" mov r0, #0 \n"\r
" msr basepri, r0 \n"\r
" orr r14, #0xd \n"\r
" bx r14 \n"\r
" \n"\r
- " .align 2 \n"\r
+ " .align 4 \n"\r
"pxCurrentTCBConst2: .word pxCurrentTCB \n"\r
);\r
}\r
" ldr r0, [r0] \n"\r
" msr msp, r0 \n" /* Set the msp back to the start of the stack. */\r
" cpsie i \n" /* Globally enable interrupts. */\r
+ " cpsie f \n"\r
+ " dsb \n"\r
+ " isb \n"\r
" svc 0 \n" /* System call to start first task. */\r
" nop \n"\r
);\r
/*\r
* See header file for description.\r
*/\r
-portBASE_TYPE xPortStartScheduler( void )\r
+BaseType_t xPortStartScheduler( void )\r
{\r
/* configMAX_SYSCALL_INTERRUPT_PRIORITY must not be set to 0.\r
See http://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html */\r
\r
#if( configASSERT_DEFINED == 1 )\r
{\r
- volatile unsigned long ulOriginalPriority;\r
- volatile char * const pcFirstUserPriorityRegister = ( volatile char * const ) ( portNVIC_IP_REGISTERS_OFFSET_16 + portFIRST_USER_INTERRUPT_NUMBER );\r
- volatile unsigned char ucMaxPriorityValue;\r
+ volatile uint32_t ulOriginalPriority;\r
+ volatile uint8_t * const pucFirstUserPriorityRegister = ( volatile uint8_t * const ) ( portNVIC_IP_REGISTERS_OFFSET_16 + portFIRST_USER_INTERRUPT_NUMBER );\r
+ volatile uint8_t ucMaxPriorityValue;\r
\r
/* Determine the maximum priority from which ISR safe FreeRTOS API\r
functions can be called. ISR safe functions are those that end in\r
ensure interrupt entry is as fast and simple as possible.\r
\r
Save the interrupt priority value that is about to be clobbered. */\r
- ulOriginalPriority = *pcFirstUserPriorityRegister;\r
+ ulOriginalPriority = *pucFirstUserPriorityRegister;\r
\r
/* Determine the number of priority bits available. First write to all\r
possible bits. */\r
- *pcFirstUserPriorityRegister = portMAX_8_BIT_VALUE;\r
+ *pucFirstUserPriorityRegister = portMAX_8_BIT_VALUE;\r
\r
/* Read the value back to see how many bits stuck. */\r
- ucMaxPriorityValue = *pcFirstUserPriorityRegister;\r
+ ucMaxPriorityValue = *pucFirstUserPriorityRegister;\r
\r
/* Use the same mask on the maximum system call priority. */\r
ucMaxSysCallPriority = configMAX_SYSCALL_INTERRUPT_PRIORITY & ucMaxPriorityValue;\r
while( ( ucMaxPriorityValue & portTOP_BIT_OF_BYTE ) == portTOP_BIT_OF_BYTE )\r
{\r
ulMaxPRIGROUPValue--;\r
- ucMaxPriorityValue <<= ( unsigned char ) 0x01;\r
+ ucMaxPriorityValue <<= ( uint8_t ) 0x01;\r
}\r
\r
+ #ifdef __NVIC_PRIO_BITS\r
+ {\r
+ /* Check the CMSIS configuration that defines the number of\r
+ priority bits matches the number of priority bits actually queried\r
+ from the hardware. */\r
+ configASSERT( ( portMAX_PRIGROUP_BITS - ulMaxPRIGROUPValue ) == __NVIC_PRIO_BITS );\r
+ }\r
+ #endif\r
+\r
+ #ifdef configPRIO_BITS\r
+ {\r
+ /* Check the FreeRTOS configuration that defines the number of\r
+ priority bits matches the number of priority bits actually queried\r
+ from the hardware. */\r
+ configASSERT( ( portMAX_PRIGROUP_BITS - ulMaxPRIGROUPValue ) == configPRIO_BITS );\r
+ }\r
+ #endif\r
+\r
/* Shift the priority group value back to its position within the AIRCR\r
register. */\r
ulMaxPRIGROUPValue <<= portPRIGROUP_SHIFT;\r
\r
/* Restore the clobbered interrupt priority register to its original\r
value. */\r
- *pcFirstUserPriorityRegister = ulOriginalPriority;\r
+ *pucFirstUserPriorityRegister = ulOriginalPriority;\r
}\r
#endif /* conifgASSERT_DEFINED */\r
\r
/* Should never get here as the tasks will now be executing! Call the task\r
exit error function to prevent compiler warnings about a static function\r
not being called in the case that the application writer overrides this\r
- functionality by defining configTASK_RETURN_ADDRESS. */\r
+ functionality by defining configTASK_RETURN_ADDRESS. Call\r
+ vTaskSwitchContext() so link time optimisation does not remove the\r
+ symbol. */\r
+ vTaskSwitchContext();\r
prvTaskExitError();\r
\r
/* Should not get here! */\r
\r
void vPortEndScheduler( void )\r
{\r
- /* It is unlikely that the CM3 port will require this function as there\r
- is nothing to return to. */\r
-}\r
-/*-----------------------------------------------------------*/\r
-\r
-void vPortYield( void )\r
-{\r
- /* Set a PendSV to request a context switch. */\r
- portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT;\r
-\r
- /* Barriers are normally not required but do ensure the code is completely\r
- within the specified behaviour for the architecture. */\r
- __asm volatile( "dsb" );\r
- __asm volatile( "isb" );\r
+ /* Not implemented in ports where there is nothing to return to.\r
+ Artificially force an assert. */\r
+ configASSERT( uxCriticalNesting == 1000UL );\r
}\r
/*-----------------------------------------------------------*/\r
\r
{\r
portDISABLE_INTERRUPTS();\r
uxCriticalNesting++;\r
- __asm volatile( "dsb" );\r
- __asm volatile( "isb" );\r
+\r
+ /* This is not the interrupt safe version of the enter critical function so\r
+ assert() if it is being called from an interrupt context. Only API\r
+ functions that end in "FromISR" can be used in an interrupt. Only assert if\r
+ the critical nesting count is 1 to protect against recursive calls if the\r
+ assert function also uses a critical section. */\r
+ if( uxCriticalNesting == 1 )\r
+ {\r
+ configASSERT( ( portNVIC_INT_CTRL_REG & portVECTACTIVE_MASK ) == 0 );\r
+ }\r
}\r
/*-----------------------------------------------------------*/\r
\r
void vPortExitCritical( void )\r
{\r
+ configASSERT( uxCriticalNesting );\r
uxCriticalNesting--;\r
if( uxCriticalNesting == 0 )\r
{\r
}\r
/*-----------------------------------------------------------*/\r
\r
-__attribute__(( naked )) unsigned long ulPortSetInterruptMask( void )\r
-{\r
- __asm volatile \\r
- ( \\r
- " mrs r0, basepri \n" \\r
- " mov r1, %0 \n" \\r
- " msr basepri, r1 \n" \\r
- " bx lr \n" \\r
- :: "i" ( configMAX_SYSCALL_INTERRUPT_PRIORITY ) : "r0", "r1" \\r
- );\r
-\r
- /* This return will not be reached but is necessary to prevent compiler\r
- warnings. */\r
- return 0;\r
-}\r
-/*-----------------------------------------------------------*/\r
-\r
-__attribute__(( naked )) void vPortClearInterruptMask( unsigned long ulNewMaskValue )\r
-{\r
- __asm volatile \\r
- ( \\r
- " msr basepri, r0 \n" \\r
- " bx lr \n" \\r
- :::"r0" \\r
- );\r
-\r
- /* Just to avoid compiler warnings. */\r
- ( void ) ulNewMaskValue;\r
-}\r
-/*-----------------------------------------------------------*/\r
-\r
void xPortPendSVHandler( void )\r
{\r
/* This is a naked function. */\r
__asm volatile\r
(\r
" mrs r0, psp \n"\r
+ " isb \n"\r
" \n"\r
" ldr r3, pxCurrentTCBConst \n" /* Get the location of the current TCB. */\r
" ldr r2, [r3] \n"\r
" mov r0, #0 \n"\r
" msr basepri, r0 \n"\r
" ldmia sp!, {r3, r14} \n"\r
- " \n" /* Restore the context, including the critical nesting count. */\r
+ " \n" /* Restore the context, including the critical nesting count. */\r
" ldr r1, [r3] \n"\r
" ldr r0, [r1] \n" /* The first item in pxCurrentTCB is the task top of stack. */\r
" ldmia r0!, {r4-r11} \n" /* Pop the registers. */\r
" msr psp, r0 \n"\r
+ " isb \n"\r
" bx r14 \n"\r
" \n"\r
- " .align 2 \n"\r
+ " .align 4 \n"\r
"pxCurrentTCBConst: .word pxCurrentTCB \n"\r
::"i"(configMAX_SYSCALL_INTERRUPT_PRIORITY)\r
);\r
executes all interrupts must be unmasked. There is therefore no need to\r
save and then restore the interrupt mask value as its value is already\r
known. */\r
- ( void ) portSET_INTERRUPT_MASK_FROM_ISR();\r
+ portDISABLE_INTERRUPTS();\r
{\r
/* Increment the RTOS tick. */\r
if( xTaskIncrementTick() != pdFALSE )\r
portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT;\r
}\r
}\r
- portCLEAR_INTERRUPT_MASK_FROM_ISR( 0 );\r
+ portENABLE_INTERRUPTS();\r
}\r
/*-----------------------------------------------------------*/\r
\r
-#if configUSE_TICKLESS_IDLE == 1\r
+#if( configUSE_TICKLESS_IDLE == 1 )\r
\r
- __attribute__((weak)) void vPortSuppressTicksAndSleep( portTickType xExpectedIdleTime )\r
+ __attribute__((weak)) void vPortSuppressTicksAndSleep( TickType_t xExpectedIdleTime )\r
{\r
- unsigned long ulReloadValue, ulCompleteTickPeriods, ulCompletedSysTickDecrements;\r
- portTickType xModifiableIdleTime;\r
+ uint32_t ulReloadValue, ulCompleteTickPeriods, ulCompletedSysTickDecrements;\r
+ TickType_t xModifiableIdleTime;\r
\r
/* Make sure the SysTick reload value does not overflow the counter. */\r
if( xExpectedIdleTime > xMaximumPossibleSuppressedTicks )\r
is accounted for as best it can be, but using the tickless mode will\r
inevitably result in some tiny drift of the time maintained by the\r
kernel with respect to calendar time. */\r
- portNVIC_SYSTICK_CTRL_REG = portNVIC_SYSTICK_CLK_BIT | portNVIC_SYSTICK_INT_BIT;\r
+ portNVIC_SYSTICK_CTRL_REG &= ~portNVIC_SYSTICK_ENABLE_BIT;\r
\r
/* Calculate the reload value required to wait xExpectedIdleTime\r
tick periods. -1 is used because this code will execute part way\r
\r
/* Enter a critical section but don't use the taskENTER_CRITICAL()\r
method as that will mask interrupts that should exit sleep mode. */\r
- __asm volatile( "cpsid i" );\r
+ __asm volatile( "cpsid i" ::: "memory" );\r
+ __asm volatile( "dsb" );\r
+ __asm volatile( "isb" );\r
\r
/* If a context switch is pending or a task is waiting for the scheduler\r
to be unsuspended then abandon the low power entry. */\r
portNVIC_SYSTICK_LOAD_REG = portNVIC_SYSTICK_CURRENT_VALUE_REG;\r
\r
/* Restart SysTick. */\r
- portNVIC_SYSTICK_CTRL_REG = portNVIC_SYSTICK_CLK_BIT | portNVIC_SYSTICK_INT_BIT | portNVIC_SYSTICK_ENABLE_BIT;\r
+ portNVIC_SYSTICK_CTRL_REG |= portNVIC_SYSTICK_ENABLE_BIT;\r
\r
/* Reset the reload register to the value required for normal tick\r
periods. */\r
\r
/* Re-enable interrupts - see comments above the cpsid instruction()\r
above. */\r
- __asm volatile( "cpsie i" );\r
+ __asm volatile( "cpsie i" ::: "memory" );\r
}\r
else\r
{\r
portNVIC_SYSTICK_CURRENT_VALUE_REG = 0UL;\r
\r
/* Restart SysTick. */\r
- portNVIC_SYSTICK_CTRL_REG = portNVIC_SYSTICK_CLK_BIT | portNVIC_SYSTICK_INT_BIT | portNVIC_SYSTICK_ENABLE_BIT;\r
+ portNVIC_SYSTICK_CTRL_REG |= portNVIC_SYSTICK_ENABLE_BIT;\r
\r
/* Sleep until something happens. configPRE_SLEEP_PROCESSING() can\r
set its parameter to 0 to indicate that its implementation contains\r
configPRE_SLEEP_PROCESSING( xModifiableIdleTime );\r
if( xModifiableIdleTime > 0 )\r
{\r
- __asm volatile( "dsb" );\r
+ __asm volatile( "dsb" ::: "memory" );\r
__asm volatile( "wfi" );\r
__asm volatile( "isb" );\r
}\r
configPOST_SLEEP_PROCESSING( xExpectedIdleTime );\r
\r
- /* Stop SysTick. Again, the time the SysTick is stopped for is\r
- accounted for as best it can be, but using the tickless mode will\r
- inevitably result in some tiny drift of the time maintained by the\r
- kernel with respect to calendar time. */\r
- portNVIC_SYSTICK_CTRL_REG = portNVIC_SYSTICK_CLK_BIT | portNVIC_SYSTICK_INT_BIT;\r
-\r
- /* Re-enable interrupts - see comments above the cpsid instruction()\r
- above. */\r
- __asm volatile( "cpsie i" );\r
-\r
+ /* Re-enable interrupts to allow the interrupt that brought the MCU\r
+ out of sleep mode to execute immediately. see comments above\r
+ __disable_interrupt() call above. */\r
+ __asm volatile( "cpsie i" ::: "memory" );\r
+ __asm volatile( "dsb" );\r
+ __asm volatile( "isb" );\r
+\r
+ /* Disable interrupts again because the clock is about to be stopped\r
+ and interrupts that execute while the clock is stopped will increase\r
+ any slippage between the time maintained by the RTOS and calendar\r
+ time. */\r
+ __asm volatile( "cpsid i" ::: "memory" );\r
+ __asm volatile( "dsb" );\r
+ __asm volatile( "isb" );\r
+\r
+ /* Disable the SysTick clock without reading the\r
+ portNVIC_SYSTICK_CTRL_REG register to ensure the\r
+ portNVIC_SYSTICK_COUNT_FLAG_BIT is not cleared if it is set. Again,\r
+ the time the SysTick is stopped for is accounted for as best it can\r
+ be, but using the tickless mode will inevitably result in some tiny\r
+ drift of the time maintained by the kernel with respect to calendar\r
+ time*/\r
+ portNVIC_SYSTICK_CTRL_REG = ( portNVIC_SYSTICK_CLK_BIT | portNVIC_SYSTICK_INT_BIT );\r
+\r
+ /* Determine if the SysTick clock has already counted to zero and\r
+ been set back to the current reload value (the reload back being\r
+ correct for the entire expected idle time) or if the SysTick is yet\r
+ to count to zero (in which case an interrupt other than the SysTick\r
+ must have brought the system out of sleep mode). */\r
if( ( portNVIC_SYSTICK_CTRL_REG & portNVIC_SYSTICK_COUNT_FLAG_BIT ) != 0 )\r
{\r
- unsigned long ulCalculatedLoadValue;\r
+ uint32_t ulCalculatedLoadValue;\r
\r
- /* The tick interrupt has already executed, and the SysTick\r
- count reloaded with ulReloadValue. Reset the\r
+ /* The tick interrupt is already pending, and the SysTick count\r
+ reloaded with ulReloadValue. Reset the\r
portNVIC_SYSTICK_LOAD_REG with whatever remains of this tick\r
period. */\r
ulCalculatedLoadValue = ( ulTimerCountsForOneTick - 1UL ) - ( ulReloadValue - portNVIC_SYSTICK_CURRENT_VALUE_REG );\r
\r
portNVIC_SYSTICK_LOAD_REG = ulCalculatedLoadValue;\r
\r
- /* The tick interrupt handler will already have pended the tick\r
- processing in the kernel. As the pending tick will be\r
- processed as soon as this function exits, the tick value\r
- maintained by the tick is stepped forward by one less than the\r
- time spent waiting. */\r
+ /* As the pending tick will be processed as soon as this\r
+ function exits, the tick value maintained by the tick is stepped\r
+ forward by one less than the time spent waiting. */\r
ulCompleteTickPeriods = xExpectedIdleTime - 1UL;\r
}\r
else\r
\r
/* The reload value is set to whatever fraction of a single tick\r
period remains. */\r
- portNVIC_SYSTICK_LOAD_REG = ( ( ulCompleteTickPeriods + 1 ) * ulTimerCountsForOneTick ) - ulCompletedSysTickDecrements;\r
+ portNVIC_SYSTICK_LOAD_REG = ( ( ulCompleteTickPeriods + 1UL ) * ulTimerCountsForOneTick ) - ulCompletedSysTickDecrements;\r
}\r
\r
/* Restart SysTick so it runs from portNVIC_SYSTICK_LOAD_REG\r
again, then set portNVIC_SYSTICK_LOAD_REG back to its standard\r
- value. The critical section is used to ensure the tick interrupt\r
- can only execute once in the case that the reload register is near\r
- zero. */\r
+ value. */\r
portNVIC_SYSTICK_CURRENT_VALUE_REG = 0UL;\r
- portENTER_CRITICAL();\r
- {\r
- portNVIC_SYSTICK_CTRL_REG = portNVIC_SYSTICK_CLK_BIT | portNVIC_SYSTICK_INT_BIT | portNVIC_SYSTICK_ENABLE_BIT;\r
- vTaskStepTick( ulCompleteTickPeriods );\r
- portNVIC_SYSTICK_LOAD_REG = ulTimerCountsForOneTick - 1UL;\r
- }\r
- portEXIT_CRITICAL();\r
+ portNVIC_SYSTICK_CTRL_REG |= portNVIC_SYSTICK_ENABLE_BIT;\r
+ vTaskStepTick( ulCompleteTickPeriods );\r
+ portNVIC_SYSTICK_LOAD_REG = ulTimerCountsForOneTick - 1UL;\r
+\r
+ /* Exit with interrpts enabled. */\r
+ __asm volatile( "cpsie i" ::: "memory" );\r
}\r
}\r
\r
-#endif /* #if configUSE_TICKLESS_IDLE */\r
+#endif /* configUSE_TICKLESS_IDLE */\r
/*-----------------------------------------------------------*/\r
\r
/*\r
__attribute__(( weak )) void vPortSetupTimerInterrupt( void )\r
{\r
/* Calculate the constants required to configure the tick interrupt. */\r
- #if configUSE_TICKLESS_IDLE == 1\r
+ #if( configUSE_TICKLESS_IDLE == 1 )\r
{\r
ulTimerCountsForOneTick = ( configSYSTICK_CLOCK_HZ / configTICK_RATE_HZ );\r
xMaximumPossibleSuppressedTicks = portMAX_24_BIT_NUMBER / ulTimerCountsForOneTick;\r
}\r
#endif /* configUSE_TICKLESS_IDLE */\r
\r
+ /* Stop and clear the SysTick. */\r
+ portNVIC_SYSTICK_CTRL_REG = 0UL;\r
+ portNVIC_SYSTICK_CURRENT_VALUE_REG = 0UL;\r
+\r
/* Configure SysTick to interrupt at the requested rate. */\r
- portNVIC_SYSTICK_LOAD_REG = ( configSYSTICK_CLOCK_HZ / configTICK_RATE_HZ ) - 1UL;;\r
- portNVIC_SYSTICK_CTRL_REG = portNVIC_SYSTICK_CLK_BIT | portNVIC_SYSTICK_INT_BIT | portNVIC_SYSTICK_ENABLE_BIT;\r
+ portNVIC_SYSTICK_LOAD_REG = ( configSYSTICK_CLOCK_HZ / configTICK_RATE_HZ ) - 1UL;\r
+ portNVIC_SYSTICK_CTRL_REG = ( portNVIC_SYSTICK_CLK_BIT | portNVIC_SYSTICK_INT_BIT | portNVIC_SYSTICK_ENABLE_BIT );\r
}\r
/*-----------------------------------------------------------*/\r
\r
\r
void vPortValidateInterruptPriority( void )\r
{\r
- unsigned long ulCurrentInterrupt;\r
- unsigned char ucCurrentPriority;\r
+ uint32_t ulCurrentInterrupt;\r
+ uint8_t ucCurrentPriority;\r
\r
/* Obtain the number of the currently executing interrupt. */\r
- __asm volatile( "mrs %0, ipsr" : "=r"( ulCurrentInterrupt ) );\r
+ __asm volatile( "mrs %0, ipsr" : "=r"( ulCurrentInterrupt ) :: "memory" );\r
\r
/* Is the interrupt number a user defined interrupt? */\r
if( ulCurrentInterrupt >= portFIRST_USER_INTERRUPT_NUMBER )\r
devices by calling NVIC_SetPriorityGrouping( 0 ); before starting the\r
scheduler. Note however that some vendor specific peripheral libraries\r
assume a non-zero priority group setting, in which cases using a value\r
- of zero will result in unpredicable behaviour. */\r
+ of zero will result in unpredictable behaviour. */\r
configASSERT( ( portAIRCR_REG & portPRIORITY_GROUP_MASK ) <= ulMaxPRIGROUPValue );\r
}\r
\r
projects / freertos / blobdiff