/*\r
- * FreeRTOS Kernel V10.2.0\r
+ * FreeRTOS Kernel V10.2.1\r
* Copyright (C) 2019 Amazon.com, Inc. or its affiliates. All Rights Reserved.\r
*\r
* Permission is hereby granted, free of charge, to any person obtaining a copy of\r
#include "portasm.h"\r
\r
#if( configENABLE_TRUSTZONE == 1 )\r
- /* Secure components includes. */\r
- #include "secure_context.h"\r
- #include "secure_init.h"\r
+ /* Secure components includes. */\r
+ #include "secure_context.h"\r
+ #include "secure_init.h"\r
#endif /* configENABLE_TRUSTZONE */\r
\r
#undef MPU_WRAPPERS_INCLUDED_FROM_API_FILE\r
+\r
+/**\r
+ * The FreeRTOS Cortex M33 port can be configured to run on the Secure Side only\r
+ * i.e. the processor boots as secure and never jumps to the non-secure side.\r
+ * The Trust Zone support in the port must be disabled in order to run FreeRTOS\r
+ * on the secure side. The following are the valid configuration seetings:\r
+ *\r
+ * 1. Run FreeRTOS on the Secure Side:\r
+ * configRUN_FREERTOS_SECURE_ONLY = 1 and configENABLE_TRUSTZONE = 0\r
+ *\r
+ * 2. Run FreeRTOS on the Non-Secure Side with Secure Side function call support:\r
+ * configRUN_FREERTOS_SECURE_ONLY = 0 and configENABLE_TRUSTZONE = 1\r
+ *\r
+ * 3. Run FreeRTOS on the Non-Secure Side only i.e. no Secure Side function call support:\r
+ * configRUN_FREERTOS_SECURE_ONLY = 0 and configENABLE_TRUSTZONE = 0\r
+ */\r
+#if( ( configRUN_FREERTOS_SECURE_ONLY == 1 ) && ( configENABLE_TRUSTZONE == 1 ) )\r
+ #error TrustZone needs to be disabled in order to run FreeRTOS on the Secure Side.\r
+#endif\r
/*-----------------------------------------------------------*/\r
\r
/**\r
* @brief Constants required to manipulate the NVIC.\r
*/\r
-#define portNVIC_SYSTICK_CTRL ( ( volatile uint32_t * ) 0xe000e010 )\r
-#define portNVIC_SYSTICK_LOAD ( ( volatile uint32_t * ) 0xe000e014 )\r
-#define portNVIC_SYSTICK_CURRENT_VALUE ( ( volatile uint32_t * ) 0xe000e018 )\r
-#define portNVIC_INT_CTRL ( ( volatile uint32_t * ) 0xe000ed04 )\r
-#define portNVIC_SYSPRI2 ( ( volatile uint32_t * ) 0xe000ed20 )\r
-#define portNVIC_SYSTICK_CLK ( 0x00000004 )\r
-#define portNVIC_SYSTICK_INT ( 0x00000002 )\r
-#define portNVIC_SYSTICK_ENABLE ( 0x00000001 )\r
-#define portNVIC_PENDSVSET ( 0x10000000 )\r
-#define portMIN_INTERRUPT_PRIORITY ( 255UL )\r
-#define portNVIC_PENDSV_PRI ( portMIN_INTERRUPT_PRIORITY << 16UL )\r
-#define portNVIC_SYSTICK_PRI ( portMIN_INTERRUPT_PRIORITY << 24UL )\r
+#define portNVIC_SYSTICK_CTRL ( ( volatile uint32_t * ) 0xe000e010 )\r
+#define portNVIC_SYSTICK_LOAD ( ( volatile uint32_t * ) 0xe000e014 )\r
+#define portNVIC_SYSTICK_CURRENT_VALUE ( ( volatile uint32_t * ) 0xe000e018 )\r
+#define portNVIC_INT_CTRL ( ( volatile uint32_t * ) 0xe000ed04 )\r
+#define portNVIC_SYSPRI2 ( ( volatile uint32_t * ) 0xe000ed20 )\r
+#define portNVIC_SYSTICK_CLK ( 0x00000004 )\r
+#define portNVIC_SYSTICK_INT ( 0x00000002 )\r
+#define portNVIC_SYSTICK_ENABLE ( 0x00000001 )\r
+#define portNVIC_PENDSVSET ( 0x10000000 )\r
+#define portMIN_INTERRUPT_PRIORITY ( 255UL )\r
+#define portNVIC_PENDSV_PRI ( portMIN_INTERRUPT_PRIORITY << 16UL )\r
+#define portNVIC_SYSTICK_PRI ( portMIN_INTERRUPT_PRIORITY << 24UL )\r
/*-----------------------------------------------------------*/\r
\r
/**\r
* @brief Constants required to manipulate the SCB.\r
*/\r
-#define portSCB_SYS_HANDLER_CTRL_STATE_REG ( * ( volatile uint32_t * ) 0xe000ed24 )\r
-#define portSCB_MEM_FAULT_ENABLE ( 1UL << 16UL )\r
+#define portSCB_SYS_HANDLER_CTRL_STATE_REG ( * ( volatile uint32_t * ) 0xe000ed24 )\r
+#define portSCB_MEM_FAULT_ENABLE ( 1UL << 16UL )\r
/*-----------------------------------------------------------*/\r
\r
/**\r
* @brief Constants required to manipulate the FPU.\r
*/\r
-#define portCPACR ( ( volatile uint32_t * ) 0xe000ed88 ) /* Coprocessor Access Control Register. */\r
-#define portCPACR_CP10_VALUE ( 3UL )\r
-#define portCPACR_CP11_VALUE portCPACR_CP10_VALUE\r
-#define portCPACR_CP10_POS ( 20UL )\r
-#define portCPACR_CP11_POS ( 22UL )\r
-\r
-#define portFPCCR ( ( volatile uint32_t * ) 0xe000ef34 ) /* Floating Point Context Control Register. */\r
-#define portFPCCR_ASPEN_POS ( 31UL )\r
-#define portFPCCR_ASPEN_MASK ( 1UL << portFPCCR_ASPEN_POS )\r
-#define portFPCCR_LSPEN_POS ( 30UL )\r
-#define portFPCCR_LSPEN_MASK ( 1UL << portFPCCR_LSPEN_POS )\r
+#define portCPACR ( ( volatile uint32_t * ) 0xe000ed88 ) /* Coprocessor Access Control Register. */\r
+#define portCPACR_CP10_VALUE ( 3UL )\r
+#define portCPACR_CP11_VALUE portCPACR_CP10_VALUE\r
+#define portCPACR_CP10_POS ( 20UL )\r
+#define portCPACR_CP11_POS ( 22UL )\r
+\r
+#define portFPCCR ( ( volatile uint32_t * ) 0xe000ef34 ) /* Floating Point Context Control Register. */\r
+#define portFPCCR_ASPEN_POS ( 31UL )\r
+#define portFPCCR_ASPEN_MASK ( 1UL << portFPCCR_ASPEN_POS )\r
+#define portFPCCR_LSPEN_POS ( 30UL )\r
+#define portFPCCR_LSPEN_MASK ( 1UL << portFPCCR_LSPEN_POS )\r
/*-----------------------------------------------------------*/\r
\r
/**\r
* @brief Constants required to manipulate the MPU.\r
*/\r
-#define portMPU_TYPE_REG ( * ( ( volatile uint32_t * ) 0xe000ed90 ) )\r
-#define portMPU_CTRL_REG ( * ( ( volatile uint32_t * ) 0xe000ed94 ) )\r
-#define portMPU_RNR_REG ( * ( ( volatile uint32_t * ) 0xe000ed98 ) )\r
+#define portMPU_TYPE_REG ( * ( ( volatile uint32_t * ) 0xe000ed90 ) )\r
+#define portMPU_CTRL_REG ( * ( ( volatile uint32_t * ) 0xe000ed94 ) )\r
+#define portMPU_RNR_REG ( * ( ( volatile uint32_t * ) 0xe000ed98 ) )\r
\r
-#define portMPU_RBAR_REG ( * ( ( volatile uint32_t * ) 0xe000ed9c ) )\r
-#define portMPU_RLAR_REG ( * ( ( volatile uint32_t * ) 0xe000eda0 ) )\r
+#define portMPU_RBAR_REG ( * ( ( volatile uint32_t * ) 0xe000ed9c ) )\r
+#define portMPU_RLAR_REG ( * ( ( volatile uint32_t * ) 0xe000eda0 ) )\r
\r
-#define portMPU_RBAR_A1_REG ( * ( ( volatile uint32_t * ) 0xe000eda4 ) )\r
-#define portMPU_RLAR_A1_REG ( * ( ( volatile uint32_t * ) 0xe000eda8 ) )\r
+#define portMPU_RBAR_A1_REG ( * ( ( volatile uint32_t * ) 0xe000eda4 ) )\r
+#define portMPU_RLAR_A1_REG ( * ( ( volatile uint32_t * ) 0xe000eda8 ) )\r
\r
-#define portMPU_RBAR_A2_REG ( * ( ( volatile uint32_t * ) 0xe000edac ) )\r
-#define portMPU_RLAR_A2_REG ( * ( ( volatile uint32_t * ) 0xe000edb0 ) )\r
+#define portMPU_RBAR_A2_REG ( * ( ( volatile uint32_t * ) 0xe000edac ) )\r
+#define portMPU_RLAR_A2_REG ( * ( ( volatile uint32_t * ) 0xe000edb0 ) )\r
\r
-#define portMPU_RBAR_A3_REG ( * ( ( volatile uint32_t * ) 0xe000edb4 ) )\r
-#define portMPU_RLAR_A3_REG ( * ( ( volatile uint32_t * ) 0xe000edb8 ) )\r
+#define portMPU_RBAR_A3_REG ( * ( ( volatile uint32_t * ) 0xe000edb4 ) )\r
+#define portMPU_RLAR_A3_REG ( * ( ( volatile uint32_t * ) 0xe000edb8 ) )\r
\r
-#define portMPU_MAIR0_REG ( * ( ( volatile uint32_t * ) 0xe000edc0 ) )\r
-#define portMPU_MAIR1_REG ( * ( ( volatile uint32_t * ) 0xe000edc4 ) )\r
+#define portMPU_MAIR0_REG ( * ( ( volatile uint32_t * ) 0xe000edc0 ) )\r
+#define portMPU_MAIR1_REG ( * ( ( volatile uint32_t * ) 0xe000edc4 ) )\r
\r
-#define portMPU_RBAR_ADDRESS_MASK ( 0xffffffe0 ) /* Must be 32-byte aligned. */\r
-#define portMPU_RLAR_ADDRESS_MASK ( 0xffffffe0 ) /* Must be 32-byte aligned. */\r
+#define portMPU_RBAR_ADDRESS_MASK ( 0xffffffe0 ) /* Must be 32-byte aligned. */\r
+#define portMPU_RLAR_ADDRESS_MASK ( 0xffffffe0 ) /* Must be 32-byte aligned. */\r
\r
-#define portMPU_MAIR_ATTR0_POS ( 0UL )\r
-#define portMPU_MAIR_ATTR0_MASK ( 0x000000ff )\r
+#define portMPU_MAIR_ATTR0_POS ( 0UL )\r
+#define portMPU_MAIR_ATTR0_MASK ( 0x000000ff )\r
\r
-#define portMPU_MAIR_ATTR1_POS ( 8UL )\r
-#define portMPU_MAIR_ATTR1_MASK ( 0x0000ff00 )\r
+#define portMPU_MAIR_ATTR1_POS ( 8UL )\r
+#define portMPU_MAIR_ATTR1_MASK ( 0x0000ff00 )\r
\r
-#define portMPU_MAIR_ATTR2_POS ( 16UL )\r
-#define portMPU_MAIR_ATTR2_MASK ( 0x00ff0000 )\r
+#define portMPU_MAIR_ATTR2_POS ( 16UL )\r
+#define portMPU_MAIR_ATTR2_MASK ( 0x00ff0000 )\r
\r
-#define portMPU_MAIR_ATTR3_POS ( 24UL )\r
-#define portMPU_MAIR_ATTR3_MASK ( 0xff000000 )\r
+#define portMPU_MAIR_ATTR3_POS ( 24UL )\r
+#define portMPU_MAIR_ATTR3_MASK ( 0xff000000 )\r
\r
-#define portMPU_MAIR_ATTR4_POS ( 0UL )\r
-#define portMPU_MAIR_ATTR4_MASK ( 0x000000ff )\r
+#define portMPU_MAIR_ATTR4_POS ( 0UL )\r
+#define portMPU_MAIR_ATTR4_MASK ( 0x000000ff )\r
\r
-#define portMPU_MAIR_ATTR5_POS ( 8UL )\r
-#define portMPU_MAIR_ATTR5_MASK ( 0x0000ff00 )\r
+#define portMPU_MAIR_ATTR5_POS ( 8UL )\r
+#define portMPU_MAIR_ATTR5_MASK ( 0x0000ff00 )\r
\r
-#define portMPU_MAIR_ATTR6_POS ( 16UL )\r
-#define portMPU_MAIR_ATTR6_MASK ( 0x00ff0000 )\r
+#define portMPU_MAIR_ATTR6_POS ( 16UL )\r
+#define portMPU_MAIR_ATTR6_MASK ( 0x00ff0000 )\r
\r
-#define portMPU_MAIR_ATTR7_POS ( 24UL )\r
-#define portMPU_MAIR_ATTR7_MASK ( 0xff000000 )\r
+#define portMPU_MAIR_ATTR7_POS ( 24UL )\r
+#define portMPU_MAIR_ATTR7_MASK ( 0xff000000 )\r
\r
-#define portMPU_RLAR_ATTR_INDEX0 ( 0UL << 1UL )\r
-#define portMPU_RLAR_ATTR_INDEX1 ( 1UL << 1UL )\r
-#define portMPU_RLAR_ATTR_INDEX2 ( 2UL << 1UL )\r
-#define portMPU_RLAR_ATTR_INDEX3 ( 3UL << 1UL )\r
-#define portMPU_RLAR_ATTR_INDEX4 ( 4UL << 1UL )\r
-#define portMPU_RLAR_ATTR_INDEX5 ( 5UL << 1UL )\r
-#define portMPU_RLAR_ATTR_INDEX6 ( 6UL << 1UL )\r
-#define portMPU_RLAR_ATTR_INDEX7 ( 7UL << 1UL )\r
+#define portMPU_RLAR_ATTR_INDEX0 ( 0UL << 1UL )\r
+#define portMPU_RLAR_ATTR_INDEX1 ( 1UL << 1UL )\r
+#define portMPU_RLAR_ATTR_INDEX2 ( 2UL << 1UL )\r
+#define portMPU_RLAR_ATTR_INDEX3 ( 3UL << 1UL )\r
+#define portMPU_RLAR_ATTR_INDEX4 ( 4UL << 1UL )\r
+#define portMPU_RLAR_ATTR_INDEX5 ( 5UL << 1UL )\r
+#define portMPU_RLAR_ATTR_INDEX6 ( 6UL << 1UL )\r
+#define portMPU_RLAR_ATTR_INDEX7 ( 7UL << 1UL )\r
\r
-#define portMPU_RLAR_REGION_ENABLE ( 1UL )\r
+#define portMPU_RLAR_REGION_ENABLE ( 1UL )\r
\r
/* Enable privileged access to unmapped region. */\r
-#define portMPU_PRIV_BACKGROUND_ENABLE ( 1UL << 2UL )\r
+#define portMPU_PRIV_BACKGROUND_ENABLE ( 1UL << 2UL )\r
\r
/* Enable MPU. */\r
-#define portMPU_ENABLE ( 1UL << 0UL )\r
+#define portMPU_ENABLE ( 1UL << 0UL )\r
\r
/* Expected value of the portMPU_TYPE register. */\r
-#define portEXPECTED_MPU_TYPE_VALUE ( 8UL << 8UL ) /* 8 regions, unified. */\r
+#define portEXPECTED_MPU_TYPE_VALUE ( 8UL << 8UL ) /* 8 regions, unified. */\r
/*-----------------------------------------------------------*/\r
\r
/**\r
* @brief Constants required to set up the initial stack.\r
*/\r
-#define portINITIAL_XPSR ( 0x01000000 )\r
-\r
-/**\r
- * @brief Initial EXC_RETURN value.\r
- *\r
- * FF FF FF BC\r
- * 1111 1111 1111 1111 1111 1111 1011 1100\r
- *\r
- * Bit[6] - 0 --> The exception was taken from the Non-Secure state.\r
- * Bit[5] - 1 --> Do not skip stacking of additional state context.\r
- * Bit[4] - 1 --> The PE did not allocate space on the stack for FP context.\r
- * Bit[3] - 1 --> Return to the Thread mode.\r
- * Bit[2] - 1 --> Restore registers from the process stack.\r
- * Bit[1] - 0 --> Reserved, 0.\r
- * Bit[0] - 0 --> The exception was taken to the Non-Secure state.\r
- */\r
-#define portINITIAL_EXC_RETURN ( 0xffffffbc )\r
+#define portINITIAL_XPSR ( 0x01000000 )\r
+\r
+#if( configRUN_FREERTOS_SECURE_ONLY == 1 )\r
+ /**\r
+ * @brief Initial EXC_RETURN value.\r
+ *\r
+ * FF FF FF FD\r
+ * 1111 1111 1111 1111 1111 1111 1111 1101\r
+ *\r
+ * Bit[6] - 1 --> The exception was taken from the Secure state.\r
+ * Bit[5] - 1 --> Do not skip stacking of additional state context.\r
+ * Bit[4] - 1 --> The PE did not allocate space on the stack for FP context.\r
+ * Bit[3] - 1 --> Return to the Thread mode.\r
+ * Bit[2] - 1 --> Restore registers from the process stack.\r
+ * Bit[1] - 0 --> Reserved, 0.\r
+ * Bit[0] - 1 --> The exception was taken to the Secure state.\r
+ */\r
+ #define portINITIAL_EXC_RETURN ( 0xfffffffd )\r
+#else\r
+ /**\r
+ * @brief Initial EXC_RETURN value.\r
+ *\r
+ * FF FF FF BC\r
+ * 1111 1111 1111 1111 1111 1111 1011 1100\r
+ *\r
+ * Bit[6] - 0 --> The exception was taken from the Non-Secure state.\r
+ * Bit[5] - 1 --> Do not skip stacking of additional state context.\r
+ * Bit[4] - 1 --> The PE did not allocate space on the stack for FP context.\r
+ * Bit[3] - 1 --> Return to the Thread mode.\r
+ * Bit[2] - 1 --> Restore registers from the process stack.\r
+ * Bit[1] - 0 --> Reserved, 0.\r
+ * Bit[0] - 0 --> The exception was taken to the Non-Secure state.\r
+ */\r
+ #define portINITIAL_EXC_RETURN ( 0xffffffbc )\r
+#endif /* configRUN_FREERTOS_SECURE_ONLY */\r
\r
/**\r
* @brief CONTROL register privileged bit mask.\r
* Bit[0] = 0 ==> The task is privileged.\r
* Bit[0] = 1 ==> The task is not privileged.\r
*/\r
-#define portCONTROL_PRIVILEGED_MASK ( 1UL << 0UL )\r
+#define portCONTROL_PRIVILEGED_MASK ( 1UL << 0UL )\r
\r
/**\r
* @brief Initial CONTROL register values.\r
*/\r
-#define portINITIAL_CONTROL_UNPRIVILEGED ( 0x3 )\r
-#define portINITIAL_CONTROL_PRIVILEGED ( 0x2 )\r
+#define portINITIAL_CONTROL_UNPRIVILEGED ( 0x3 )\r
+#define portINITIAL_CONTROL_PRIVILEGED ( 0x2 )\r
\r
/**\r
* @brief Let the user override the pre-loading of the initial LR with the\r
* in the debugger.\r
*/\r
#ifdef configTASK_RETURN_ADDRESS\r
- #define portTASK_RETURN_ADDRESS configTASK_RETURN_ADDRESS\r
+ #define portTASK_RETURN_ADDRESS configTASK_RETURN_ADDRESS\r
#else\r
- #define portTASK_RETURN_ADDRESS prvTaskExitError\r
+ #define portTASK_RETURN_ADDRESS prvTaskExitError\r
#endif\r
\r
/**\r
* @brief If portPRELOAD_REGISTERS then registers will be given an initial value\r
* when a task is created. This helps in debugging at the cost of code size.\r
*/\r
-#define portPRELOAD_REGISTERS 1\r
+#define portPRELOAD_REGISTERS 1\r
\r
/**\r
* @brief A task is created without a secure context, and must call\r
* portALLOCATE_SECURE_CONTEXT() to give itself a secure context before it makes\r
* any secure calls.\r
*/\r
-#define portNO_SECURE_CONTEXT 0\r
+#define portNO_SECURE_CONTEXT 0\r
/*-----------------------------------------------------------*/\r
\r
-/**\r
- * @brief Setup the timer to generate the tick interrupts.\r
- */\r
-static void prvSetupTimerInterrupt( void ) PRIVILEGED_FUNCTION;\r
-\r
/**\r
* @brief Used to catch tasks that attempt to return from their implementing\r
* function.\r
static void prvTaskExitError( void );\r
\r
#if( configENABLE_MPU == 1 )\r
- /**\r
- * @brief Setup the Memory Protection Unit (MPU).\r
- */\r
- static void prvSetupMPU( void ) PRIVILEGED_FUNCTION;\r
+ /**\r
+ * @brief Setup the Memory Protection Unit (MPU).\r
+ */\r
+ static void prvSetupMPU( void ) PRIVILEGED_FUNCTION;\r
#endif /* configENABLE_MPU */\r
\r
#if( configENABLE_FPU == 1 )\r
- /**\r
- * @brief Setup the Floating Point Unit (FPU).\r
- */\r
- static void prvSetupFPU( void ) PRIVILEGED_FUNCTION;\r
+ /**\r
+ * @brief Setup the Floating Point Unit (FPU).\r
+ */\r
+ static void prvSetupFPU( void ) PRIVILEGED_FUNCTION;\r
#endif /* configENABLE_FPU */\r
\r
+/**\r
+ * @brief Setup the timer to generate the tick interrupts.\r
+ *\r
+ * The implementation in this file is weak to allow application writers to\r
+ * change the timer used to generate the tick interrupt.\r
+ */\r
+void vPortSetupTimerInterrupt( void ) PRIVILEGED_FUNCTION;\r
+\r
+/**\r
+ * @brief Checks whether the current execution context is interrupt.\r
+ *\r
+ * @return pdTRUE if the current execution context is interrupt, pdFALSE\r
+ * otherwise.\r
+ */\r
+BaseType_t xPortIsInsideInterrupt( void );\r
+\r
/**\r
* @brief Yield the processor.\r
*/\r
/**\r
* @brief C part of SVC handler.\r
*/\r
-void vPortSVCHandler_C( uint32_t *pulCallerStackAddress ) PRIVILEGED_FUNCTION;\r
+portDONT_DISCARD void vPortSVCHandler_C( uint32_t *pulCallerStackAddress ) PRIVILEGED_FUNCTION;\r
/*-----------------------------------------------------------*/\r
\r
/**\r
static volatile uint32_t ulCriticalNesting = 0xaaaaaaaaUL;\r
\r
#if( configENABLE_TRUSTZONE == 1 )\r
- /**\r
- * @brief Saved as part of the task context to indicate which context the\r
- * task is using on the secure side.\r
- */\r
- volatile SecureContextHandle_t xSecureContext = portNO_SECURE_CONTEXT;\r
+ /**\r
+ * @brief Saved as part of the task context to indicate which context the\r
+ * task is using on the secure side.\r
+ */\r
+ portDONT_DISCARD volatile SecureContextHandle_t xSecureContext = portNO_SECURE_CONTEXT;\r
#endif /* configENABLE_TRUSTZONE */\r
/*-----------------------------------------------------------*/\r
\r
-static void prvSetupTimerInterrupt( void ) /* PRIVILEGED_FUNCTION */\r
+__attribute__(( weak )) void vPortSetupTimerInterrupt( void ) /* PRIVILEGED_FUNCTION */\r
{\r
- /* Stop and reset the SysTick. */\r
- *( portNVIC_SYSTICK_CTRL ) = 0UL;\r
- *( portNVIC_SYSTICK_CURRENT_VALUE ) = 0UL;\r
+ /* Stop and reset the SysTick. */\r
+ *( portNVIC_SYSTICK_CTRL ) = 0UL;\r
+ *( portNVIC_SYSTICK_CURRENT_VALUE ) = 0UL;\r
\r
- /* Configure SysTick to interrupt at the requested rate. */\r
- *( portNVIC_SYSTICK_LOAD ) = ( configCPU_CLOCK_HZ / configTICK_RATE_HZ ) - 1UL;\r
- *( portNVIC_SYSTICK_CTRL ) = portNVIC_SYSTICK_CLK | portNVIC_SYSTICK_INT | portNVIC_SYSTICK_ENABLE;\r
+ /* Configure SysTick to interrupt at the requested rate. */\r
+ *( portNVIC_SYSTICK_LOAD ) = ( configCPU_CLOCK_HZ / configTICK_RATE_HZ ) - 1UL;\r
+ *( portNVIC_SYSTICK_CTRL ) = portNVIC_SYSTICK_CLK | portNVIC_SYSTICK_INT | portNVIC_SYSTICK_ENABLE;\r
}\r
/*-----------------------------------------------------------*/\r
\r
{\r
volatile uint32_t ulDummy = 0UL;\r
\r
- /* A function that implements a task must not exit or attempt to return to\r
- * its caller as there is nothing to return to. If a task wants to exit it\r
- * should instead call vTaskDelete( NULL ). Artificially force an assert()\r
- * to be triggered if configASSERT() is defined, then stop here so\r
- * application writers can catch the error. */\r
- configASSERT( ulCriticalNesting == ~0UL );\r
- portDISABLE_INTERRUPTS();\r
-\r
- while( ulDummy == 0 )\r
- {\r
- /* This file calls prvTaskExitError() after the scheduler has been\r
- * started to remove a compiler warning about the function being\r
- * defined but never called. ulDummy is used purely to quieten other\r
- * warnings about code appearing after this function is called - making\r
- * ulDummy volatile makes the compiler think the function could return\r
- * and therefore not output an 'unreachable code' warning for code that\r
- * appears after it. */\r
- }\r
+ /* A function that implements a task must not exit or attempt to return to\r
+ * its caller as there is nothing to return to. If a task wants to exit it\r
+ * should instead call vTaskDelete( NULL ). Artificially force an assert()\r
+ * to be triggered if configASSERT() is defined, then stop here so\r
+ * application writers can catch the error. */\r
+ configASSERT( ulCriticalNesting == ~0UL );\r
+ portDISABLE_INTERRUPTS();\r
+\r
+ while( ulDummy == 0 )\r
+ {\r
+ /* This file calls prvTaskExitError() after the scheduler has been\r
+ * started to remove a compiler warning about the function being\r
+ * defined but never called. ulDummy is used purely to quieten other\r
+ * warnings about code appearing after this function is called - making\r
+ * ulDummy volatile makes the compiler think the function could return\r
+ * and therefore not output an 'unreachable code' warning for code that\r
+ * appears after it. */\r
+ }\r
}\r
/*-----------------------------------------------------------*/\r
\r
#if( configENABLE_MPU == 1 )\r
- static void prvSetupMPU( void ) /* PRIVILEGED_FUNCTION */\r
- {\r
- #if defined( __ARMCC_VERSION )\r
- /* Declaration when these variable are defined in code instead of being\r
- * exported from linker scripts. */\r
- extern uint32_t * __privileged_functions_start__;\r
- extern uint32_t * __privileged_functions_end__;\r
- extern uint32_t * __syscalls_flash_start__;\r
- extern uint32_t * __unprivileged_flash_end__;\r
- extern uint32_t * __privileged_sram_start__;\r
- extern uint32_t * __privileged_sram_end__;\r
- #else\r
- /* Declaration when these variable are exported from linker scripts. */\r
- extern uint32_t __privileged_functions_start__[];\r
- extern uint32_t __privileged_functions_end__[];\r
- extern uint32_t __syscalls_flash_start__[];\r
- extern uint32_t __unprivileged_flash_end__[];\r
- extern uint32_t __privileged_sram_start__[];\r
- extern uint32_t __privileged_sram_end__[];\r
- #endif /* defined( __ARMCC_VERSION ) */\r
-\r
- /* Check that the MPU is present. */\r
- if( portMPU_TYPE_REG == portEXPECTED_MPU_TYPE_VALUE )\r
- {\r
- /* MAIR0 - Index 0. */\r
- portMPU_MAIR0_REG |= ( ( portMPU_NORMAL_MEMORY_BUFFERABLE_CACHEABLE << portMPU_MAIR_ATTR0_POS ) & portMPU_MAIR_ATTR0_MASK );\r
- /* MAIR0 - Index 1. */\r
- portMPU_MAIR0_REG |= ( ( portMPU_DEVICE_MEMORY_nGnRE << portMPU_MAIR_ATTR1_POS ) & portMPU_MAIR_ATTR1_MASK );\r
-\r
- /* Setup privileged flash as Read Only so that privileged tasks can\r
- * read it but not modify. */\r
- portMPU_RNR_REG = portPRIVILEGED_FLASH_REGION;\r
- portMPU_RBAR_REG = ( ( ( uint32_t ) __privileged_functions_start__ ) & portMPU_RBAR_ADDRESS_MASK ) |\r
- ( portMPU_REGION_NON_SHAREABLE ) |\r
- ( portMPU_REGION_PRIVILEGED_READ_ONLY );\r
- portMPU_RLAR_REG = ( ( ( uint32_t ) __privileged_functions_end__ ) & portMPU_RLAR_ADDRESS_MASK ) |\r
- ( portMPU_RLAR_ATTR_INDEX0 ) |\r
- ( portMPU_RLAR_REGION_ENABLE );\r
-\r
- /* Setup unprivileged flash and system calls flash as Read Only by\r
- * both privileged and unprivileged tasks. All tasks can read it but\r
- * no-one can modify. */\r
- portMPU_RNR_REG = portUNPRIVILEGED_FLASH_REGION;\r
- portMPU_RBAR_REG = ( ( ( uint32_t ) __syscalls_flash_start__ ) & portMPU_RBAR_ADDRESS_MASK ) |\r
- ( portMPU_REGION_NON_SHAREABLE ) |\r
- ( portMPU_REGION_READ_ONLY );\r
- portMPU_RLAR_REG = ( ( ( uint32_t ) __unprivileged_flash_end__ ) & portMPU_RLAR_ADDRESS_MASK ) |\r
- ( portMPU_RLAR_ATTR_INDEX0 ) |\r
- ( portMPU_RLAR_REGION_ENABLE );\r
-\r
- /* Setup RAM containing kernel data for privileged access only. */\r
- portMPU_RNR_REG = portPRIVILEGED_RAM_REGION;\r
- portMPU_RBAR_REG = ( ( ( uint32_t ) __privileged_sram_start__ ) & portMPU_RBAR_ADDRESS_MASK ) |\r
- ( portMPU_REGION_NON_SHAREABLE ) |\r
- ( portMPU_REGION_PRIVILEGED_READ_WRITE ) |\r
- ( portMPU_REGION_EXECUTE_NEVER );\r
- portMPU_RLAR_REG = ( ( ( uint32_t ) __privileged_sram_end__ ) & portMPU_RLAR_ADDRESS_MASK ) |\r
- ( portMPU_RLAR_ATTR_INDEX0 ) |\r
- ( portMPU_RLAR_REGION_ENABLE );\r
-\r
- /* By default allow everything to access the general peripherals.\r
- * The system peripherals and registers are protected. */\r
- portMPU_RNR_REG = portUNPRIVILEGED_DEVICE_REGION;\r
- portMPU_RBAR_REG = ( ( ( uint32_t ) portDEVICE_REGION_START_ADDRESS ) & portMPU_RBAR_ADDRESS_MASK ) |\r
- ( portMPU_REGION_NON_SHAREABLE ) |\r
- ( portMPU_REGION_READ_WRITE ) |\r
- ( portMPU_REGION_EXECUTE_NEVER );\r
- portMPU_RLAR_REG = ( ( ( uint32_t ) portDEVICE_REGION_END_ADDRESS ) & portMPU_RLAR_ADDRESS_MASK ) |\r
- ( portMPU_RLAR_ATTR_INDEX1 ) |\r
- ( portMPU_RLAR_REGION_ENABLE );\r
-\r
- /* Enable mem fault. */\r
- portSCB_SYS_HANDLER_CTRL_STATE_REG |= portSCB_MEM_FAULT_ENABLE;\r
-\r
- /* Enable MPU with privileged background access i.e. unmapped\r
- * regions have privileged access. */\r
- portMPU_CTRL_REG |= ( portMPU_PRIV_BACKGROUND_ENABLE | portMPU_ENABLE );\r
- }\r
- }\r
+ static void prvSetupMPU( void ) /* PRIVILEGED_FUNCTION */\r
+ {\r
+ #if defined( __ARMCC_VERSION )\r
+ /* Declaration when these variable are defined in code instead of being\r
+ * exported from linker scripts. */\r
+ extern uint32_t * __privileged_functions_start__;\r
+ extern uint32_t * __privileged_functions_end__;\r
+ extern uint32_t * __syscalls_flash_start__;\r
+ extern uint32_t * __syscalls_flash_end__;\r
+ extern uint32_t * __unprivileged_flash_start__;\r
+ extern uint32_t * __unprivileged_flash_end__;\r
+ extern uint32_t * __privileged_sram_start__;\r
+ extern uint32_t * __privileged_sram_end__;\r
+ #else\r
+ /* Declaration when these variable are exported from linker scripts. */\r
+ extern uint32_t __privileged_functions_start__[];\r
+ extern uint32_t __privileged_functions_end__[];\r
+ extern uint32_t __syscalls_flash_start__[];\r
+ extern uint32_t __syscalls_flash_end__[];\r
+ extern uint32_t __unprivileged_flash_start__[];\r
+ extern uint32_t __unprivileged_flash_end__[];\r
+ extern uint32_t __privileged_sram_start__[];\r
+ extern uint32_t __privileged_sram_end__[];\r
+ #endif /* defined( __ARMCC_VERSION ) */\r
+\r
+ /* Check that the MPU is present. */\r
+ if( portMPU_TYPE_REG == portEXPECTED_MPU_TYPE_VALUE )\r
+ {\r
+ /* MAIR0 - Index 0. */\r
+ portMPU_MAIR0_REG |= ( ( portMPU_NORMAL_MEMORY_BUFFERABLE_CACHEABLE << portMPU_MAIR_ATTR0_POS ) & portMPU_MAIR_ATTR0_MASK );\r
+ /* MAIR0 - Index 1. */\r
+ portMPU_MAIR0_REG |= ( ( portMPU_DEVICE_MEMORY_nGnRE << portMPU_MAIR_ATTR1_POS ) & portMPU_MAIR_ATTR1_MASK );\r
+\r
+ /* Setup privileged flash as Read Only so that privileged tasks can\r
+ * read it but not modify. */\r
+ portMPU_RNR_REG = portPRIVILEGED_FLASH_REGION;\r
+ portMPU_RBAR_REG = ( ( ( uint32_t ) __privileged_functions_start__ ) & portMPU_RBAR_ADDRESS_MASK ) |\r
+ ( portMPU_REGION_NON_SHAREABLE ) |\r
+ ( portMPU_REGION_PRIVILEGED_READ_ONLY );\r
+ portMPU_RLAR_REG = ( ( ( uint32_t ) __privileged_functions_end__ ) & portMPU_RLAR_ADDRESS_MASK ) |\r
+ ( portMPU_RLAR_ATTR_INDEX0 ) |\r
+ ( portMPU_RLAR_REGION_ENABLE );\r
+\r
+ /* Setup unprivileged flash as Read Only by both privileged and\r
+ * unprivileged tasks. All tasks can read it but no-one can modify. */\r
+ portMPU_RNR_REG = portUNPRIVILEGED_FLASH_REGION;\r
+ portMPU_RBAR_REG = ( ( ( uint32_t ) __unprivileged_flash_start__ ) & portMPU_RBAR_ADDRESS_MASK ) |\r
+ ( portMPU_REGION_NON_SHAREABLE ) |\r
+ ( portMPU_REGION_READ_ONLY );\r
+ portMPU_RLAR_REG = ( ( ( uint32_t ) __unprivileged_flash_end__ ) & portMPU_RLAR_ADDRESS_MASK ) |\r
+ ( portMPU_RLAR_ATTR_INDEX0 ) |\r
+ ( portMPU_RLAR_REGION_ENABLE );\r
+\r
+ /* Setup unprivileged syscalls flash as Read Only by both privileged\r
+ * and unprivileged tasks. All tasks can read it but no-one can modify. */\r
+ portMPU_RNR_REG = portUNPRIVILEGED_SYSCALLS_REGION;\r
+ portMPU_RBAR_REG = ( ( ( uint32_t ) __syscalls_flash_start__ ) & portMPU_RBAR_ADDRESS_MASK ) |\r
+ ( portMPU_REGION_NON_SHAREABLE ) |\r
+ ( portMPU_REGION_READ_ONLY );\r
+ portMPU_RLAR_REG = ( ( ( uint32_t ) __syscalls_flash_end__ ) & portMPU_RLAR_ADDRESS_MASK ) |\r
+ ( portMPU_RLAR_ATTR_INDEX0 ) |\r
+ ( portMPU_RLAR_REGION_ENABLE );\r
+\r
+ /* Setup RAM containing kernel data for privileged access only. */\r
+ portMPU_RNR_REG = portPRIVILEGED_RAM_REGION;\r
+ portMPU_RBAR_REG = ( ( ( uint32_t ) __privileged_sram_start__ ) & portMPU_RBAR_ADDRESS_MASK ) |\r
+ ( portMPU_REGION_NON_SHAREABLE ) |\r
+ ( portMPU_REGION_PRIVILEGED_READ_WRITE ) |\r
+ ( portMPU_REGION_EXECUTE_NEVER );\r
+ portMPU_RLAR_REG = ( ( ( uint32_t ) __privileged_sram_end__ ) & portMPU_RLAR_ADDRESS_MASK ) |\r
+ ( portMPU_RLAR_ATTR_INDEX0 ) |\r
+ ( portMPU_RLAR_REGION_ENABLE );\r
+\r
+ /* Enable mem fault. */\r
+ portSCB_SYS_HANDLER_CTRL_STATE_REG |= portSCB_MEM_FAULT_ENABLE;\r
+\r
+ /* Enable MPU with privileged background access i.e. unmapped\r
+ * regions have privileged access. */\r
+ portMPU_CTRL_REG |= ( portMPU_PRIV_BACKGROUND_ENABLE | portMPU_ENABLE );\r
+ }\r
+ }\r
#endif /* configENABLE_MPU */\r
/*-----------------------------------------------------------*/\r
\r
#if( configENABLE_FPU == 1 )\r
- static void prvSetupFPU( void ) /* PRIVILEGED_FUNCTION */\r
- {\r
- #if( configENABLE_TRUSTZONE == 1 )\r
- {\r
- /* Enable non-secure access to the FPU. */\r
- SecureInit_EnableNSFPUAccess();\r
- }\r
- #endif /* configENABLE_TRUSTZONE */\r
-\r
- /* CP10 = 11 ==> Full access to FPU i.e. both privileged and\r
- * unprivileged code should be able to access FPU. CP11 should be\r
- * programmed to the same value as CP10. */\r
- *( portCPACR ) |= ( ( portCPACR_CP10_VALUE << portCPACR_CP10_POS ) |\r
- ( portCPACR_CP11_VALUE << portCPACR_CP11_POS )\r
- );\r
-\r
- /* ASPEN = 1 ==> Hardware should automatically preserve floating point\r
- * context on exception entry and restore on exception return.\r
- * LSPEN = 1 ==> Enable lazy context save of FP state. */\r
- *( portFPCCR ) |= ( portFPCCR_ASPEN_MASK | portFPCCR_LSPEN_MASK );\r
- }\r
+ static void prvSetupFPU( void ) /* PRIVILEGED_FUNCTION */\r
+ {\r
+ #if( configENABLE_TRUSTZONE == 1 )\r
+ {\r
+ /* Enable non-secure access to the FPU. */\r
+ SecureInit_EnableNSFPUAccess();\r
+ }\r
+ #endif /* configENABLE_TRUSTZONE */\r
+\r
+ /* CP10 = 11 ==> Full access to FPU i.e. both privileged and\r
+ * unprivileged code should be able to access FPU. CP11 should be\r
+ * programmed to the same value as CP10. */\r
+ *( portCPACR ) |= ( ( portCPACR_CP10_VALUE << portCPACR_CP10_POS ) |\r
+ ( portCPACR_CP11_VALUE << portCPACR_CP11_POS )\r
+ );\r
+\r
+ /* ASPEN = 1 ==> Hardware should automatically preserve floating point\r
+ * context on exception entry and restore on exception return.\r
+ * LSPEN = 1 ==> Enable lazy context save of FP state. */\r
+ *( portFPCCR ) |= ( portFPCCR_ASPEN_MASK | portFPCCR_LSPEN_MASK );\r
+ }\r
#endif /* configENABLE_FPU */\r
/*-----------------------------------------------------------*/\r
\r
void vPortYield( void ) /* PRIVILEGED_FUNCTION */\r
{\r
- /* Set a PendSV to request a context switch. */\r
- *( portNVIC_INT_CTRL ) = portNVIC_PENDSVSET;\r
+ /* Set a PendSV to request a context switch. */\r
+ *( portNVIC_INT_CTRL ) = portNVIC_PENDSVSET;\r
\r
- /* Barriers are normally not required but do ensure the code is\r
- * completely within the specified behaviour for the architecture. */\r
- __asm volatile( "dsb" ::: "memory" );\r
- __asm volatile( "isb" );\r
+ /* Barriers are normally not required but do ensure the code is\r
+ * completely within the specified behaviour for the architecture. */\r
+ __asm volatile( "dsb" ::: "memory" );\r
+ __asm volatile( "isb" );\r
}\r
/*-----------------------------------------------------------*/\r
\r
void vPortEnterCritical( void ) /* PRIVILEGED_FUNCTION */\r
{\r
- portDISABLE_INTERRUPTS();\r
- ulCriticalNesting++;\r
+ portDISABLE_INTERRUPTS();\r
+ ulCriticalNesting++;\r
\r
- /* Barriers are normally not required but do ensure the code is\r
- * completely within the specified behaviour for the architecture. */\r
- __asm volatile( "dsb" ::: "memory" );\r
- __asm volatile( "isb" );\r
+ /* Barriers are normally not required but do ensure the code is\r
+ * completely within the specified behaviour for the architecture. */\r
+ __asm volatile( "dsb" ::: "memory" );\r
+ __asm volatile( "isb" );\r
}\r
/*-----------------------------------------------------------*/\r
\r
void vPortExitCritical( void ) /* PRIVILEGED_FUNCTION */\r
{\r
- configASSERT( ulCriticalNesting );\r
- ulCriticalNesting--;\r
+ configASSERT( ulCriticalNesting );\r
+ ulCriticalNesting--;\r
\r
- if( ulCriticalNesting == 0 )\r
- {\r
- portENABLE_INTERRUPTS();\r
- }\r
+ if( ulCriticalNesting == 0 )\r
+ {\r
+ portENABLE_INTERRUPTS();\r
+ }\r
}\r
/*-----------------------------------------------------------*/\r
\r
{\r
uint32_t ulPreviousMask;\r
\r
- ulPreviousMask = portSET_INTERRUPT_MASK_FROM_ISR();\r
- {\r
- /* Increment the RTOS tick. */\r
- if( xTaskIncrementTick() != pdFALSE )\r
- {\r
- /* Pend a context switch. */\r
- *( portNVIC_INT_CTRL ) = portNVIC_PENDSVSET;\r
- }\r
- }\r
- portCLEAR_INTERRUPT_MASK_FROM_ISR( ulPreviousMask );\r
+ ulPreviousMask = portSET_INTERRUPT_MASK_FROM_ISR();\r
+ {\r
+ /* Increment the RTOS tick. */\r
+ if( xTaskIncrementTick() != pdFALSE )\r
+ {\r
+ /* Pend a context switch. */\r
+ *( portNVIC_INT_CTRL ) = portNVIC_PENDSVSET;\r
+ }\r
+ }\r
+ portCLEAR_INTERRUPT_MASK_FROM_ISR( ulPreviousMask );\r
}\r
/*-----------------------------------------------------------*/\r
\r
-void vPortSVCHandler_C( uint32_t *pulCallerStackAddress ) /* PRIVILEGED_FUNCTION */\r
+void vPortSVCHandler_C( uint32_t *pulCallerStackAddress ) /* PRIVILEGED_FUNCTION portDONT_DISCARD */\r
{\r
#if( configENABLE_MPU == 1 )\r
- #if defined( __ARMCC_VERSION )\r
- /* Declaration when these variable are defined in code instead of being\r
- * exported from linker scripts. */\r
- extern uint32_t * __syscalls_flash_start__;\r
- extern uint32_t * __syscalls_flash_end__;\r
- #else\r
- /* Declaration when these variable are exported from linker scripts. */\r
- extern uint32_t __syscalls_flash_start__[];\r
- extern uint32_t __syscalls_flash_end__[];\r
- #endif /* defined( __ARMCC_VERSION ) */\r
+ #if defined( __ARMCC_VERSION )\r
+ /* Declaration when these variable are defined in code instead of being\r
+ * exported from linker scripts. */\r
+ extern uint32_t * __syscalls_flash_start__;\r
+ extern uint32_t * __syscalls_flash_end__;\r
+ #else\r
+ /* Declaration when these variable are exported from linker scripts. */\r
+ extern uint32_t __syscalls_flash_start__[];\r
+ extern uint32_t __syscalls_flash_end__[];\r
+ #endif /* defined( __ARMCC_VERSION ) */\r
#endif /* configENABLE_MPU */\r
\r
uint32_t ulPC;\r
\r
#if( configENABLE_TRUSTZONE == 1 )\r
- uint32_t ulR0;\r
- #if( configENABLE_MPU == 1 )\r
- uint32_t ulControl, ulIsTaskPrivileged;\r
- #endif /* configENABLE_MPU */\r
+ uint32_t ulR0;\r
+ #if( configENABLE_MPU == 1 )\r
+ uint32_t ulControl, ulIsTaskPrivileged;\r
+ #endif /* configENABLE_MPU */\r
#endif /* configENABLE_TRUSTZONE */\r
uint8_t ucSVCNumber;\r
\r
- /* Register are stored on the stack in the following order - R0, R1, R2, R3,\r
- * R12, LR, PC, xPSR. */\r
- ulPC = pulCallerStackAddress[ 6 ];\r
- ucSVCNumber = ( ( uint8_t *) ulPC )[ -2 ];\r
-\r
- switch( ucSVCNumber )\r
- {\r
- #if( configENABLE_TRUSTZONE == 1 )\r
- case portSVC_ALLOCATE_SECURE_CONTEXT:\r
- {\r
- /* R0 contains the stack size passed as parameter to the\r
- * vPortAllocateSecureContext function. */\r
- ulR0 = pulCallerStackAddress[ 0 ];\r
-\r
- #if( configENABLE_MPU == 1 )\r
- {\r
- /* Read the CONTROL register value. */\r
- __asm volatile ( "mrs %0, control" : "=r" ( ulControl ) );\r
-\r
- /* The task that raised the SVC is privileged if Bit[0]\r
- * in the CONTROL register is 0. */\r
- ulIsTaskPrivileged = ( ( ulControl & portCONTROL_PRIVILEGED_MASK ) == 0 );\r
-\r
- /* Allocate and load a context for the secure task. */\r
- xSecureContext = SecureContext_AllocateContext( ulR0, ulIsTaskPrivileged );\r
- }\r
- #else\r
- {\r
- /* Allocate and load a context for the secure task. */\r
- xSecureContext = SecureContext_AllocateContext( ulR0 );\r
- }\r
- #endif /* configENABLE_MPU */\r
-\r
- configASSERT( xSecureContext != NULL );\r
- SecureContext_LoadContext( xSecureContext );\r
- }\r
- break;\r
-\r
- case portSVC_FREE_SECURE_CONTEXT:\r
- {\r
- /* R0 contains the secure context handle to be freed. */\r
- ulR0 = pulCallerStackAddress[ 0 ];\r
-\r
- /* Free the secure context. */\r
- SecureContext_FreeContext( ( SecureContextHandle_t ) ulR0 );\r
- }\r
- break;\r
- #endif /* configENABLE_TRUSTZONE */\r
-\r
- case portSVC_START_SCHEDULER:\r
- {\r
- #if( configENABLE_TRUSTZONE == 1 )\r
- {\r
- /* De-prioritize the non-secure exceptions so that the\r
- * non-secure pendSV runs at the lowest priority. */\r
- SecureInit_DePrioritizeNSExceptions();\r
-\r
- /* Initialize the secure context management system. */\r
- SecureContext_Init();\r
- }\r
- #endif /* configENABLE_TRUSTZONE */\r
-\r
- #if( configENABLE_FPU == 1 )\r
- {\r
- /* Setup the Floating Point Unit (FPU). */\r
- prvSetupFPU();\r
- }\r
- #endif /* configENABLE_FPU */\r
-\r
- /* Setup the context of the first task so that the first task starts\r
- * executing. */\r
- vRestoreContextOfFirstTask();\r
- }\r
- break;\r
-\r
- #if( configENABLE_MPU == 1 )\r
- case portSVC_RAISE_PRIVILEGE:\r
- {\r
- /* Only raise the privilege, if the svc was raised from any of\r
- * the system calls. */\r
- if( ulPC >= ( uint32_t ) __syscalls_flash_start__ &&\r
- ulPC <= ( uint32_t ) __syscalls_flash_end__ )\r
- {\r
- vRaisePrivilege();\r
- }\r
- }\r
- break;\r
- #endif /* configENABLE_MPU */\r
-\r
- default:\r
- {\r
- /* Incorrect SVC call. */\r
- configASSERT( pdFALSE );\r
- }\r
- }\r
+ /* Register are stored on the stack in the following order - R0, R1, R2, R3,\r
+ * R12, LR, PC, xPSR. */\r
+ ulPC = pulCallerStackAddress[ 6 ];\r
+ ucSVCNumber = ( ( uint8_t *) ulPC )[ -2 ];\r
+\r
+ switch( ucSVCNumber )\r
+ {\r
+ #if( configENABLE_TRUSTZONE == 1 )\r
+ case portSVC_ALLOCATE_SECURE_CONTEXT:\r
+ {\r
+ /* R0 contains the stack size passed as parameter to the\r
+ * vPortAllocateSecureContext function. */\r
+ ulR0 = pulCallerStackAddress[ 0 ];\r
+\r
+ #if( configENABLE_MPU == 1 )\r
+ {\r
+ /* Read the CONTROL register value. */\r
+ __asm volatile ( "mrs %0, control" : "=r" ( ulControl ) );\r
+\r
+ /* The task that raised the SVC is privileged if Bit[0]\r
+ * in the CONTROL register is 0. */\r
+ ulIsTaskPrivileged = ( ( ulControl & portCONTROL_PRIVILEGED_MASK ) == 0 );\r
+\r
+ /* Allocate and load a context for the secure task. */\r
+ xSecureContext = SecureContext_AllocateContext( ulR0, ulIsTaskPrivileged );\r
+ }\r
+ #else\r
+ {\r
+ /* Allocate and load a context for the secure task. */\r
+ xSecureContext = SecureContext_AllocateContext( ulR0 );\r
+ }\r
+ #endif /* configENABLE_MPU */\r
+\r
+ configASSERT( xSecureContext != NULL );\r
+ SecureContext_LoadContext( xSecureContext );\r
+ }\r
+ break;\r
+\r
+ case portSVC_FREE_SECURE_CONTEXT:\r
+ {\r
+ /* R0 contains the secure context handle to be freed. */\r
+ ulR0 = pulCallerStackAddress[ 0 ];\r
+\r
+ /* Free the secure context. */\r
+ SecureContext_FreeContext( ( SecureContextHandle_t ) ulR0 );\r
+ }\r
+ break;\r
+ #endif /* configENABLE_TRUSTZONE */\r
+\r
+ case portSVC_START_SCHEDULER:\r
+ {\r
+ #if( configENABLE_TRUSTZONE == 1 )\r
+ {\r
+ /* De-prioritize the non-secure exceptions so that the\r
+ * non-secure pendSV runs at the lowest priority. */\r
+ SecureInit_DePrioritizeNSExceptions();\r
+\r
+ /* Initialize the secure context management system. */\r
+ SecureContext_Init();\r
+ }\r
+ #endif /* configENABLE_TRUSTZONE */\r
+\r
+ #if( configENABLE_FPU == 1 )\r
+ {\r
+ /* Setup the Floating Point Unit (FPU). */\r
+ prvSetupFPU();\r
+ }\r
+ #endif /* configENABLE_FPU */\r
+\r
+ /* Setup the context of the first task so that the first task starts\r
+ * executing. */\r
+ vRestoreContextOfFirstTask();\r
+ }\r
+ break;\r
+\r
+ #if( configENABLE_MPU == 1 )\r
+ case portSVC_RAISE_PRIVILEGE:\r
+ {\r
+ /* Only raise the privilege, if the svc was raised from any of\r
+ * the system calls. */\r
+ if( ulPC >= ( uint32_t ) __syscalls_flash_start__ &&\r
+ ulPC <= ( uint32_t ) __syscalls_flash_end__ )\r
+ {\r
+ vRaisePrivilege();\r
+ }\r
+ }\r
+ break;\r
+ #endif /* configENABLE_MPU */\r
+\r
+ default:\r
+ {\r
+ /* Incorrect SVC call. */\r
+ configASSERT( pdFALSE );\r
+ }\r
+ }\r
}\r
/*-----------------------------------------------------------*/\r
\r
#if( configENABLE_MPU == 1 )\r
- StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, StackType_t *pxEndOfStack, TaskFunction_t pxCode, void *pvParameters, BaseType_t xRunPrivileged ) /* PRIVILEGED_FUNCTION */\r
+ StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, StackType_t *pxEndOfStack, TaskFunction_t pxCode, void *pvParameters, BaseType_t xRunPrivileged ) /* PRIVILEGED_FUNCTION */\r
#else\r
- StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, StackType_t *pxEndOfStack, TaskFunction_t pxCode, void *pvParameters ) /* PRIVILEGED_FUNCTION */\r
+ StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, StackType_t *pxEndOfStack, TaskFunction_t pxCode, void *pvParameters ) /* PRIVILEGED_FUNCTION */\r
#endif /* configENABLE_MPU */\r
{\r
- /* Simulate the stack frame as it would be created by a context switch\r
- * interrupt. */\r
- #if( portPRELOAD_REGISTERS == 0 )\r
- {\r
- pxTopOfStack--; /* Offset added to account for the way the MCU uses the stack on entry/exit of interrupts. */\r
- *pxTopOfStack = portINITIAL_XPSR; /* xPSR */\r
- pxTopOfStack--;\r
- *pxTopOfStack = ( StackType_t ) pxCode; /* PC */\r
- pxTopOfStack--;\r
- *pxTopOfStack = ( StackType_t ) portTASK_RETURN_ADDRESS; /* LR */\r
- pxTopOfStack -= 5; /* R12, R3, R2 and R1. */\r
- *pxTopOfStack = ( StackType_t ) pvParameters; /* R0 */\r
- pxTopOfStack -= 9; /* R11..R4, EXC_RETURN. */\r
- *pxTopOfStack = portINITIAL_EXC_RETURN;\r
-\r
- #if( configENABLE_MPU == 1 )\r
- {\r
- pxTopOfStack--;\r
- if( xRunPrivileged == pdTRUE )\r
- {\r
- *pxTopOfStack = portINITIAL_CONTROL_PRIVILEGED; /* Slot used to hold this task's CONTROL value. */\r
- }\r
- else\r
- {\r
- *pxTopOfStack = portINITIAL_CONTROL_UNPRIVILEGED; /* Slot used to hold this task's CONTROL value. */\r
- }\r
- }\r
- #endif /* configENABLE_MPU */\r
-\r
- pxTopOfStack--;\r
- *pxTopOfStack = ( StackType_t ) pxEndOfStack; /* Slot used to hold this task's PSPLIM value. */\r
-\r
- #if( configENABLE_TRUSTZONE == 1 )\r
- {\r
- pxTopOfStack--;\r
- *pxTopOfStack = portNO_SECURE_CONTEXT; /* Slot used to hold this task's xSecureContext value. */\r
- }\r
- #endif /* configENABLE_TRUSTZONE */\r
- }\r
- #else /* portPRELOAD_REGISTERS */\r
- {\r
- pxTopOfStack--; /* Offset added to account for the way the MCU uses the stack on entry/exit of interrupts. */\r
- *pxTopOfStack = portINITIAL_XPSR; /* xPSR */\r
- pxTopOfStack--;\r
- *pxTopOfStack = ( StackType_t ) pxCode; /* PC */\r
- pxTopOfStack--;\r
- *pxTopOfStack = ( StackType_t ) portTASK_RETURN_ADDRESS; /* LR */\r
- pxTopOfStack--;\r
- *pxTopOfStack = ( StackType_t ) 0x12121212UL; /* R12 */\r
- pxTopOfStack--;\r
- *pxTopOfStack = ( StackType_t ) 0x03030303UL; /* R3 */\r
- pxTopOfStack--;\r
- *pxTopOfStack = ( StackType_t ) 0x02020202UL; /* R2 */\r
- pxTopOfStack--;\r
- *pxTopOfStack = ( StackType_t ) 0x01010101UL; /* R1 */\r
- pxTopOfStack--;\r
- *pxTopOfStack = ( StackType_t ) pvParameters; /* R0 */\r
- pxTopOfStack--;\r
- *pxTopOfStack = ( StackType_t ) 0x11111111UL; /* R11 */\r
- pxTopOfStack--;\r
- *pxTopOfStack = ( StackType_t ) 0x10101010UL; /* R10 */\r
- pxTopOfStack--;\r
- *pxTopOfStack = ( StackType_t ) 0x09090909UL; /* R09 */\r
- pxTopOfStack--;\r
- *pxTopOfStack = ( StackType_t ) 0x08080808UL; /* R08 */\r
- pxTopOfStack--;\r
- *pxTopOfStack = ( StackType_t ) 0x07070707UL; /* R07 */\r
- pxTopOfStack--;\r
- *pxTopOfStack = ( StackType_t ) 0x06060606UL; /* R06 */\r
- pxTopOfStack--;\r
- *pxTopOfStack = ( StackType_t ) 0x05050505UL; /* R05 */\r
- pxTopOfStack--;\r
- *pxTopOfStack = ( StackType_t ) 0x04040404UL; /* R04 */\r
- pxTopOfStack--;\r
- *pxTopOfStack = portINITIAL_EXC_RETURN; /* EXC_RETURN */\r
-\r
- #if( configENABLE_MPU == 1 )\r
- {\r
- pxTopOfStack--;\r
- if( xRunPrivileged == pdTRUE )\r
- {\r
- *pxTopOfStack = portINITIAL_CONTROL_PRIVILEGED; /* Slot used to hold this task's CONTROL value. */\r
- }\r
- else\r
- {\r
- *pxTopOfStack = portINITIAL_CONTROL_UNPRIVILEGED; /* Slot used to hold this task's CONTROL value. */\r
- }\r
- }\r
- #endif /* configENABLE_MPU */\r
-\r
- pxTopOfStack--;\r
- *pxTopOfStack = ( StackType_t ) pxEndOfStack; /* Slot used to hold this task's PSPLIM value. */\r
-\r
- #if( configENABLE_TRUSTZONE == 1 )\r
- {\r
- pxTopOfStack--;\r
- *pxTopOfStack = portNO_SECURE_CONTEXT; /* Slot used to hold this task's xSecureContext value. */\r
- }\r
- #endif /* configENABLE_TRUSTZONE */\r
- }\r
- #endif /* portPRELOAD_REGISTERS */\r
-\r
- return pxTopOfStack;\r
+ /* Simulate the stack frame as it would be created by a context switch\r
+ * interrupt. */\r
+ #if( portPRELOAD_REGISTERS == 0 )\r
+ {\r
+ pxTopOfStack--; /* Offset added to account for the way the MCU uses the stack on entry/exit of interrupts. */\r
+ *pxTopOfStack = portINITIAL_XPSR; /* xPSR */\r
+ pxTopOfStack--;\r
+ *pxTopOfStack = ( StackType_t ) pxCode; /* PC */\r
+ pxTopOfStack--;\r
+ *pxTopOfStack = ( StackType_t ) portTASK_RETURN_ADDRESS; /* LR */\r
+ pxTopOfStack -= 5; /* R12, R3, R2 and R1. */\r
+ *pxTopOfStack = ( StackType_t ) pvParameters; /* R0 */\r
+ pxTopOfStack -= 9; /* R11..R4, EXC_RETURN. */\r
+ *pxTopOfStack = portINITIAL_EXC_RETURN;\r
+\r
+ #if( configENABLE_MPU == 1 )\r
+ {\r
+ pxTopOfStack--;\r
+ if( xRunPrivileged == pdTRUE )\r
+ {\r
+ *pxTopOfStack = portINITIAL_CONTROL_PRIVILEGED; /* Slot used to hold this task's CONTROL value. */\r
+ }\r
+ else\r
+ {\r
+ *pxTopOfStack = portINITIAL_CONTROL_UNPRIVILEGED; /* Slot used to hold this task's CONTROL value. */\r
+ }\r
+ }\r
+ #endif /* configENABLE_MPU */\r
+\r
+ pxTopOfStack--;\r
+ *pxTopOfStack = ( StackType_t ) pxEndOfStack; /* Slot used to hold this task's PSPLIM value. */\r
+\r
+ #if( configENABLE_TRUSTZONE == 1 )\r
+ {\r
+ pxTopOfStack--;\r
+ *pxTopOfStack = portNO_SECURE_CONTEXT; /* Slot used to hold this task's xSecureContext value. */\r
+ }\r
+ #endif /* configENABLE_TRUSTZONE */\r
+ }\r
+ #else /* portPRELOAD_REGISTERS */\r
+ {\r
+ pxTopOfStack--; /* Offset added to account for the way the MCU uses the stack on entry/exit of interrupts. */\r
+ *pxTopOfStack = portINITIAL_XPSR; /* xPSR */\r
+ pxTopOfStack--;\r
+ *pxTopOfStack = ( StackType_t ) pxCode; /* PC */\r
+ pxTopOfStack--;\r
+ *pxTopOfStack = ( StackType_t ) portTASK_RETURN_ADDRESS; /* LR */\r
+ pxTopOfStack--;\r
+ *pxTopOfStack = ( StackType_t ) 0x12121212UL; /* R12 */\r
+ pxTopOfStack--;\r
+ *pxTopOfStack = ( StackType_t ) 0x03030303UL; /* R3 */\r
+ pxTopOfStack--;\r
+ *pxTopOfStack = ( StackType_t ) 0x02020202UL; /* R2 */\r
+ pxTopOfStack--;\r
+ *pxTopOfStack = ( StackType_t ) 0x01010101UL; /* R1 */\r
+ pxTopOfStack--;\r
+ *pxTopOfStack = ( StackType_t ) pvParameters; /* R0 */\r
+ pxTopOfStack--;\r
+ *pxTopOfStack = ( StackType_t ) 0x11111111UL; /* R11 */\r
+ pxTopOfStack--;\r
+ *pxTopOfStack = ( StackType_t ) 0x10101010UL; /* R10 */\r
+ pxTopOfStack--;\r
+ *pxTopOfStack = ( StackType_t ) 0x09090909UL; /* R09 */\r
+ pxTopOfStack--;\r
+ *pxTopOfStack = ( StackType_t ) 0x08080808UL; /* R08 */\r
+ pxTopOfStack--;\r
+ *pxTopOfStack = ( StackType_t ) 0x07070707UL; /* R07 */\r
+ pxTopOfStack--;\r
+ *pxTopOfStack = ( StackType_t ) 0x06060606UL; /* R06 */\r
+ pxTopOfStack--;\r
+ *pxTopOfStack = ( StackType_t ) 0x05050505UL; /* R05 */\r
+ pxTopOfStack--;\r
+ *pxTopOfStack = ( StackType_t ) 0x04040404UL; /* R04 */\r
+ pxTopOfStack--;\r
+ *pxTopOfStack = portINITIAL_EXC_RETURN; /* EXC_RETURN */\r
+\r
+ #if( configENABLE_MPU == 1 )\r
+ {\r
+ pxTopOfStack--;\r
+ if( xRunPrivileged == pdTRUE )\r
+ {\r
+ *pxTopOfStack = portINITIAL_CONTROL_PRIVILEGED; /* Slot used to hold this task's CONTROL value. */\r
+ }\r
+ else\r
+ {\r
+ *pxTopOfStack = portINITIAL_CONTROL_UNPRIVILEGED; /* Slot used to hold this task's CONTROL value. */\r
+ }\r
+ }\r
+ #endif /* configENABLE_MPU */\r
+\r
+ pxTopOfStack--;\r
+ *pxTopOfStack = ( StackType_t ) pxEndOfStack; /* Slot used to hold this task's PSPLIM value. */\r
+\r
+ #if( configENABLE_TRUSTZONE == 1 )\r
+ {\r
+ pxTopOfStack--;\r
+ *pxTopOfStack = portNO_SECURE_CONTEXT; /* Slot used to hold this task's xSecureContext value. */\r
+ }\r
+ #endif /* configENABLE_TRUSTZONE */\r
+ }\r
+ #endif /* portPRELOAD_REGISTERS */\r
+\r
+ return pxTopOfStack;\r
}\r
/*-----------------------------------------------------------*/\r
\r
BaseType_t xPortStartScheduler( void ) /* PRIVILEGED_FUNCTION */\r
{\r
- /* Make PendSV, CallSV and SysTick the same priority as the kernel. */\r
- *( portNVIC_SYSPRI2 ) |= portNVIC_PENDSV_PRI;\r
- *( portNVIC_SYSPRI2 ) |= portNVIC_SYSTICK_PRI;\r
-\r
- #if( configENABLE_MPU == 1 )\r
- {\r
- /* Setup the Memory Protection Unit (MPU). */\r
- prvSetupMPU();\r
- }\r
- #endif /* configENABLE_MPU */\r
-\r
- /* Start the timer that generates the tick ISR. Interrupts are disabled\r
- * here already. */\r
- prvSetupTimerInterrupt();\r
-\r
- /* Initialize the critical nesting count ready for the first task. */\r
- ulCriticalNesting = 0;\r
-\r
- /* Start the first task. */\r
- vStartFirstTask();\r
-\r
- /* Should never get here as the tasks will now be executing. Call the task\r
- * exit error function to prevent compiler warnings about a static function\r
- * not being called in the case that the application writer overrides this\r
- * functionality by defining configTASK_RETURN_ADDRESS. Call\r
- * vTaskSwitchContext() so link time optimization does not remove the\r
- * symbol. */\r
- vTaskSwitchContext();\r
- prvTaskExitError();\r
-\r
- /* Should not get here. */\r
- return 0;\r
+ /* Make PendSV, CallSV and SysTick the same priority as the kernel. */\r
+ *( portNVIC_SYSPRI2 ) |= portNVIC_PENDSV_PRI;\r
+ *( portNVIC_SYSPRI2 ) |= portNVIC_SYSTICK_PRI;\r
+\r
+ #if( configENABLE_MPU == 1 )\r
+ {\r
+ /* Setup the Memory Protection Unit (MPU). */\r
+ prvSetupMPU();\r
+ }\r
+ #endif /* configENABLE_MPU */\r
+\r
+ /* Start the timer that generates the tick ISR. Interrupts are disabled\r
+ * here already. */\r
+ vPortSetupTimerInterrupt();\r
+\r
+ /* Initialize the critical nesting count ready for the first task. */\r
+ ulCriticalNesting = 0;\r
+\r
+ /* Start the first task. */\r
+ vStartFirstTask();\r
+\r
+ /* Should never get here as the tasks will now be executing. Call the task\r
+ * exit error function to prevent compiler warnings about a static function\r
+ * not being called in the case that the application writer overrides this\r
+ * functionality by defining configTASK_RETURN_ADDRESS. Call\r
+ * vTaskSwitchContext() so link time optimization does not remove the\r
+ * symbol. */\r
+ vTaskSwitchContext();\r
+ prvTaskExitError();\r
+\r
+ /* Should not get here. */\r
+ return 0;\r
}\r
/*-----------------------------------------------------------*/\r
\r
void vPortEndScheduler( void ) /* PRIVILEGED_FUNCTION */\r
{\r
- /* Not implemented in ports where there is nothing to return to.\r
- * Artificially force an assert. */\r
- configASSERT( ulCriticalNesting == 1000UL );\r
+ /* Not implemented in ports where there is nothing to return to.\r
+ * Artificially force an assert. */\r
+ configASSERT( ulCriticalNesting == 1000UL );\r
}\r
/*-----------------------------------------------------------*/\r
\r
#if( configENABLE_MPU == 1 )\r
- void vPortStoreTaskMPUSettings( xMPU_SETTINGS *xMPUSettings, const struct xMEMORY_REGION * const xRegions, StackType_t *pxBottomOfStack, uint32_t ulStackDepth )\r
- {\r
- uint32_t ulRegionStartAddress, ulRegionEndAddress, ulRegionNumber;\r
- int32_t lIndex = 0;\r
-\r
- /* Setup MAIR0. */\r
- xMPUSettings->ulMAIR0 = ( ( portMPU_NORMAL_MEMORY_BUFFERABLE_CACHEABLE << portMPU_MAIR_ATTR0_POS ) & portMPU_MAIR_ATTR0_MASK );\r
- xMPUSettings->ulMAIR0 |= ( ( portMPU_DEVICE_MEMORY_nGnRE << portMPU_MAIR_ATTR1_POS ) & portMPU_MAIR_ATTR1_MASK );\r
-\r
- /* This function is called automatically when the task is created - in\r
- * which case the stack region parameters will be valid. At all other\r
- * times the stack parameters will not be valid and it is assumed that\r
- * the stack region has already been configured. */\r
- if( ulStackDepth > 0 )\r
- {\r
- /* Define the region that allows access to the stack. */\r
- ulRegionStartAddress = ( ( uint32_t ) pxBottomOfStack ) & portMPU_RBAR_ADDRESS_MASK;\r
- ulRegionEndAddress = ( uint32_t ) pxBottomOfStack + ( ulStackDepth * ( uint32_t ) sizeof( StackType_t ) ) - 1;\r
- ulRegionEndAddress &= portMPU_RLAR_ADDRESS_MASK;\r
-\r
- xMPUSettings->xRegionsSettings[ 0 ].ulRBAR = ( ulRegionStartAddress ) |\r
- ( portMPU_REGION_NON_SHAREABLE ) |\r
- ( portMPU_REGION_READ_WRITE ) |\r
- ( portMPU_REGION_EXECUTE_NEVER );\r
-\r
- xMPUSettings->xRegionsSettings[ 0 ].ulRLAR = ( ulRegionEndAddress ) |\r
- ( portMPU_RLAR_ATTR_INDEX0 ) |\r
- ( portMPU_RLAR_REGION_ENABLE );\r
- }\r
-\r
- /* User supplied configurable regions. */\r
- for( ulRegionNumber = 1; ulRegionNumber <= portNUM_CONFIGURABLE_REGIONS; ulRegionNumber++ )\r
- {\r
- /* If xRegions is NULL i.e. the task has not specified any MPU\r
- * region, the else part ensures that all the configurable MPU\r
- * regions are invalidated. */\r
- if( ( xRegions != NULL ) && ( xRegions[ lIndex ].ulLengthInBytes > 0UL ) )\r
- {\r
- /* Translate the generic region definition contained in xRegions\r
- * into the ARMv8 specific MPU settings that are then stored in\r
- * xMPUSettings. */\r
- ulRegionStartAddress = ( ( uint32_t ) xRegions[ lIndex ].pvBaseAddress ) & portMPU_RBAR_ADDRESS_MASK;\r
- ulRegionEndAddress = ( uint32_t ) xRegions[ lIndex ].pvBaseAddress + xRegions[ lIndex ].ulLengthInBytes - 1;\r
- ulRegionEndAddress &= portMPU_RLAR_ADDRESS_MASK;\r
-\r
- /* Start address. */\r
- xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRBAR = ( ulRegionStartAddress ) |\r
- ( portMPU_REGION_NON_SHAREABLE );\r
-\r
- /* RO/RW. */\r
- if( ( xRegions[ lIndex ].ulParameters & tskMPU_REGION_READ_ONLY ) != 0 )\r
- {\r
- xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRBAR |= ( portMPU_REGION_READ_ONLY );\r
- }\r
- else\r
- {\r
- xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRBAR |= ( portMPU_REGION_READ_WRITE );\r
- }\r
-\r
- /* XN. */\r
- if( ( xRegions[ lIndex ].ulParameters & tskMPU_REGION_EXECUTE_NEVER ) != 0 )\r
- {\r
- xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRBAR |= ( portMPU_REGION_EXECUTE_NEVER );\r
- }\r
-\r
- /* End Address. */\r
- xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRLAR = ( ulRegionEndAddress ) |\r
- ( portMPU_RLAR_REGION_ENABLE );\r
-\r
- /* Normal memory/ Device memory. */\r
- if( ( xRegions[ lIndex ].ulParameters & tskMPU_REGION_DEVICE_MEMORY ) != 0 )\r
- {\r
- /* Attr1 in MAIR0 is configured as device memory. */\r
- xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRLAR |= portMPU_RLAR_ATTR_INDEX1;\r
- }\r
- else\r
- {\r
- /* Attr1 in MAIR0 is configured as normal memory. */\r
- xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRLAR |= portMPU_RLAR_ATTR_INDEX0;\r
- }\r
- }\r
- else\r
- {\r
- /* Invalidate the region. */\r
- xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRBAR = 0UL;\r
- xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRLAR = 0UL;\r
- }\r
-\r
- lIndex++;\r
- }\r
- }\r
+ void vPortStoreTaskMPUSettings( xMPU_SETTINGS *xMPUSettings, const struct xMEMORY_REGION * const xRegions, StackType_t *pxBottomOfStack, uint32_t ulStackDepth )\r
+ {\r
+ uint32_t ulRegionStartAddress, ulRegionEndAddress, ulRegionNumber;\r
+ int32_t lIndex = 0;\r
+\r
+ /* Setup MAIR0. */\r
+ xMPUSettings->ulMAIR0 = ( ( portMPU_NORMAL_MEMORY_BUFFERABLE_CACHEABLE << portMPU_MAIR_ATTR0_POS ) & portMPU_MAIR_ATTR0_MASK );\r
+ xMPUSettings->ulMAIR0 |= ( ( portMPU_DEVICE_MEMORY_nGnRE << portMPU_MAIR_ATTR1_POS ) & portMPU_MAIR_ATTR1_MASK );\r
+\r
+ /* This function is called automatically when the task is created - in\r
+ * which case the stack region parameters will be valid. At all other\r
+ * times the stack parameters will not be valid and it is assumed that\r
+ * the stack region has already been configured. */\r
+ if( ulStackDepth > 0 )\r
+ {\r
+ /* Define the region that allows access to the stack. */\r
+ ulRegionStartAddress = ( ( uint32_t ) pxBottomOfStack ) & portMPU_RBAR_ADDRESS_MASK;\r
+ ulRegionEndAddress = ( uint32_t ) pxBottomOfStack + ( ulStackDepth * ( uint32_t ) sizeof( StackType_t ) ) - 1;\r
+ ulRegionEndAddress &= portMPU_RLAR_ADDRESS_MASK;\r
+\r
+ xMPUSettings->xRegionsSettings[ 0 ].ulRBAR = ( ulRegionStartAddress ) |\r
+ ( portMPU_REGION_NON_SHAREABLE ) |\r
+ ( portMPU_REGION_READ_WRITE ) |\r
+ ( portMPU_REGION_EXECUTE_NEVER );\r
+\r
+ xMPUSettings->xRegionsSettings[ 0 ].ulRLAR = ( ulRegionEndAddress ) |\r
+ ( portMPU_RLAR_ATTR_INDEX0 ) |\r
+ ( portMPU_RLAR_REGION_ENABLE );\r
+ }\r
+\r
+ /* User supplied configurable regions. */\r
+ for( ulRegionNumber = 1; ulRegionNumber <= portNUM_CONFIGURABLE_REGIONS; ulRegionNumber++ )\r
+ {\r
+ /* If xRegions is NULL i.e. the task has not specified any MPU\r
+ * region, the else part ensures that all the configurable MPU\r
+ * regions are invalidated. */\r
+ if( ( xRegions != NULL ) && ( xRegions[ lIndex ].ulLengthInBytes > 0UL ) )\r
+ {\r
+ /* Translate the generic region definition contained in xRegions\r
+ * into the ARMv8 specific MPU settings that are then stored in\r
+ * xMPUSettings. */\r
+ ulRegionStartAddress = ( ( uint32_t ) xRegions[ lIndex ].pvBaseAddress ) & portMPU_RBAR_ADDRESS_MASK;\r
+ ulRegionEndAddress = ( uint32_t ) xRegions[ lIndex ].pvBaseAddress + xRegions[ lIndex ].ulLengthInBytes - 1;\r
+ ulRegionEndAddress &= portMPU_RLAR_ADDRESS_MASK;\r
+\r
+ /* Start address. */\r
+ xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRBAR = ( ulRegionStartAddress ) |\r
+ ( portMPU_REGION_NON_SHAREABLE );\r
+\r
+ /* RO/RW. */\r
+ if( ( xRegions[ lIndex ].ulParameters & tskMPU_REGION_READ_ONLY ) != 0 )\r
+ {\r
+ xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRBAR |= ( portMPU_REGION_READ_ONLY );\r
+ }\r
+ else\r
+ {\r
+ xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRBAR |= ( portMPU_REGION_READ_WRITE );\r
+ }\r
+\r
+ /* XN. */\r
+ if( ( xRegions[ lIndex ].ulParameters & tskMPU_REGION_EXECUTE_NEVER ) != 0 )\r
+ {\r
+ xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRBAR |= ( portMPU_REGION_EXECUTE_NEVER );\r
+ }\r
+\r
+ /* End Address. */\r
+ xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRLAR = ( ulRegionEndAddress ) |\r
+ ( portMPU_RLAR_REGION_ENABLE );\r
+\r
+ /* Normal memory/ Device memory. */\r
+ if( ( xRegions[ lIndex ].ulParameters & tskMPU_REGION_DEVICE_MEMORY ) != 0 )\r
+ {\r
+ /* Attr1 in MAIR0 is configured as device memory. */\r
+ xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRLAR |= portMPU_RLAR_ATTR_INDEX1;\r
+ }\r
+ else\r
+ {\r
+ /* Attr1 in MAIR0 is configured as normal memory. */\r
+ xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRLAR |= portMPU_RLAR_ATTR_INDEX0;\r
+ }\r
+ }\r
+ else\r
+ {\r
+ /* Invalidate the region. */\r
+ xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRBAR = 0UL;\r
+ xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRLAR = 0UL;\r
+ }\r
+\r
+ lIndex++;\r
+ }\r
+ }\r
#endif /* configENABLE_MPU */\r
/*-----------------------------------------------------------*/\r
+\r
+BaseType_t xPortIsInsideInterrupt( void )\r
+{\r
+uint32_t ulCurrentInterrupt;\r
+BaseType_t xReturn;\r
+\r
+ /* Obtain the number of the currently executing interrupt. Interrupt Program\r
+ * Status Register (IPSR) holds the exception number of the currently-executing\r
+ * exception or zero for Thread mode.*/\r
+ __asm volatile( "mrs %0, ipsr" : "=r"( ulCurrentInterrupt ) :: "memory" );\r
+\r
+ if( ulCurrentInterrupt == 0 )\r
+ {\r
+ xReturn = pdFALSE;\r
+ }\r
+ else\r
+ {\r
+ xReturn = pdTRUE;\r
+ }\r
+\r
+ return xReturn;\r
+}\r
+/*-----------------------------------------------------------*/
\ No newline at end of file
projects / freertos / blobdiff