/*\r
- * FreeRTOS Kernel V10.2.0\r
+ * FreeRTOS Kernel V10.2.1\r
* Copyright (C) 2019 Amazon.com, Inc. or its affiliates. All Rights Reserved.\r
*\r
* Permission is hereby granted, free of charge, to any person obtaining a copy of\r
/* Standard includes. */\r
#include <stdint.h>\r
\r
+/* Defining MPU_WRAPPERS_INCLUDED_FROM_API_FILE ensures that PRIVILEGED_FUNCTION\r
+ * is defined correctly and privileged functions are placed in correct sections. */\r
+#define MPU_WRAPPERS_INCLUDED_FROM_API_FILE\r
+\r
/* Portasm includes. */\r
#include "portasm.h"\r
\r
+/* MPU_WRAPPERS_INCLUDED_FROM_API_FILE is needed to be defined only for the\r
+ * header files. */\r
+#undef MPU_WRAPPERS_INCLUDED_FROM_API_FILE\r
+\r
void vRestoreContextOfFirstTask( void ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */\r
{\r
__asm volatile\r
" ldr r0, [r3] \n" /* Read top of stack from TCB - The first item in pxCurrentTCB is the task top of stack. */\r
" \n"\r
#if( configENABLE_MPU == 1 )\r
+ " dmb \n" /* Complete outstanding transfers before disabling MPU. */\r
+ " ldr r2, xMPUCTRLConst2 \n" /* r2 = 0xe000ed94 [Location of MPU_CTRL]. */\r
+ " ldr r4, [r2] \n" /* Read the value of MPU_CTRL. */\r
+ " bic r4, #1 \n" /* r4 = r4 & ~1 i.e. Clear the bit 0 in r4. */\r
+ " str r4, [r2] \n" /* Disable MPU. */\r
+ " \n"\r
" adds r3, #4 \n" /* r3 = r3 + 4. r3 now points to MAIR0 in TCB. */\r
" ldr r4, [r3] \n" /* r4 = *r3 i.e. r4 = MAIR0. */\r
" ldr r2, xMAIR0Const2 \n" /* r2 = 0xe000edc0 [Location of MAIR0]. */\r
" ldr r2, xRBARConst2 \n" /* r2 = 0xe000ed9c [Location of RBAR]. */\r
" ldmia r3!, {r4-r11} \n" /* Read 4 set of RBAR/RLAR registers from TCB. */\r
" stmia r2!, {r4-r11} \n" /* Write 4 set of RBAR/RLAR registers using alias registers. */\r
+ " \n"\r
+ " ldr r2, xMPUCTRLConst2 \n" /* r2 = 0xe000ed94 [Location of MPU_CTRL]. */\r
+ " ldr r4, [r2] \n" /* Read the value of MPU_CTRL. */\r
+ " orr r4, #1 \n" /* r4 = r4 | 1 i.e. Set the bit 0 in r4. */\r
+ " str r4, [r2] \n" /* Enable MPU. */\r
+ " dsb \n" /* Force memory writes before continuing. */\r
#endif /* configENABLE_MPU */\r
" \n"\r
#if( configENABLE_MPU == 1 )\r
"pxCurrentTCBConst2: .word pxCurrentTCB \n"\r
"xSecureContextConst2: .word xSecureContext \n"\r
#if( configENABLE_MPU == 1 )\r
+ "xMPUCTRLConst2: .word 0xe000ed94 \n"\r
"xMAIR0Const2: .word 0xe000edc0 \n"\r
"xRNRConst2: .word 0xe000ed98 \n"\r
"xRBARConst2: .word 0xe000ed9c \n"\r
" bx lr \n"\r
::: "memory"\r
);\r
-\r
-#if !defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)\r
- /* To avoid compiler warnings. The return statement will never be reached,\r
- * but some compilers warn if it is not included, while others won't compile\r
- * if it is. */\r
- return 0;\r
-#endif\r
}\r
/*-----------------------------------------------------------*/\r
\r
" bx lr \n"\r
::: "memory"\r
);\r
-\r
-#if !defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)\r
- /* Just to avoid compiler warning. ulMask is used from the asm code but\r
- * the compiler can't see that. Some compilers generate warnings without\r
- * the following line, while others generate warnings if the line is\r
- * included. */\r
- ( void ) ulMask;\r
-#endif\r
}\r
/*-----------------------------------------------------------*/\r
\r
" ldr r1, [r3] \n" /* The first item in pxCurrentTCB is the task top of stack. r1 now points to the top of stack. */\r
" \n"\r
#if( configENABLE_MPU == 1 )\r
+ " dmb \n" /* Complete outstanding transfers before disabling MPU. */\r
+ " ldr r2, xMPUCTRLConst \n" /* r2 = 0xe000ed94 [Location of MPU_CTRL]. */\r
+ " ldr r4, [r2] \n" /* Read the value of MPU_CTRL. */\r
+ " bic r4, #1 \n" /* r4 = r4 & ~1 i.e. Clear the bit 0 in r4. */\r
+ " str r4, [r2] \n" /* Disable MPU. */\r
+ " \n"\r
" adds r3, #4 \n" /* r3 = r3 + 4. r3 now points to MAIR0 in TCB. */\r
" ldr r4, [r3] \n" /* r4 = *r3 i.e. r4 = MAIR0. */\r
" ldr r2, xMAIR0Const \n" /* r2 = 0xe000edc0 [Location of MAIR0]. */\r
" ldr r2, xRBARConst \n" /* r2 = 0xe000ed9c [Location of RBAR]. */\r
" ldmia r3!, {r4-r11} \n" /* Read 4 sets of RBAR/RLAR registers from TCB. */\r
" stmia r2!, {r4-r11} \n" /* Write 4 set of RBAR/RLAR registers using alias registers. */\r
+ " \n"\r
+ " ldr r2, xMPUCTRLConst \n" /* r2 = 0xe000ed94 [Location of MPU_CTRL]. */\r
+ " ldr r4, [r2] \n" /* Read the value of MPU_CTRL. */\r
+ " orr r4, #1 \n" /* r4 = r4 | 1 i.e. Set the bit 0 in r4. */\r
+ " str r4, [r2] \n" /* Enable MPU. */\r
+ " dsb \n" /* Force memory writes before continuing. */\r
#endif /* configENABLE_MPU */\r
" \n"\r
#if( configENABLE_MPU == 1 )\r
"pxCurrentTCBConst: .word pxCurrentTCB \n"\r
"xSecureContextConst: .word xSecureContext \n"\r
#if( configENABLE_MPU == 1 )\r
+ "xMPUCTRLConst: .word 0xe000ed94 \n"\r
"xMAIR0Const: .word 0xe000edc0 \n"\r
"xRNRConst: .word 0xe000ed98 \n"\r
"xRBARConst: .word 0xe000ed9c \n"\r