/*\r
- * FreeRTOS Kernel V10.2.0\r
+ * FreeRTOS Kernel V10.2.1\r
* Copyright (C) 2019 Amazon.com, Inc. or its affiliates. All Rights Reserved.\r
*\r
* Permission is hereby granted, free of charge, to any person obtaining a copy of\r
/**\r
* Architecture specifics.\r
*/\r
+#define portARCH_NAME "Cortex-M33"\r
#define portSTACK_GROWTH ( -1 )\r
#define portTICK_PERIOD_MS ( ( TickType_t ) 1000 / configTICK_RATE_HZ )\r
#define portBYTE_ALIGNMENT 8\r
#define portFORCE_INLINE inline __attribute__(( always_inline ))\r
#endif\r
#define portHAS_STACK_OVERFLOW_CHECKING 1\r
+#define portDONT_DISCARD __attribute__(( used ))\r
/*-----------------------------------------------------------*/\r
\r
/**\r
* @brief Extern declarations.\r
*/\r
+extern BaseType_t xPortIsInsideInterrupt( void );\r
+\r
extern void vPortYield( void ) /* PRIVILEGED_FUNCTION */;\r
\r
extern void vPortEnterCritical( void ) /* PRIVILEGED_FUNCTION */;\r
extern void vPortExitCritical( void ) /* PRIVILEGED_FUNCTION */;\r
\r
-extern uint32_t ulSetInterruptMaskFromISR( void ) /* __attribute__(( naked )) PRIVILEGED_FUNCTION */;\r
-extern void vClearInterruptMaskFromISR( uint32_t ulMask ) /* __attribute__(( naked )) PRIVILEGED_FUNCTION */;\r
+extern uint32_t ulSetInterruptMask( void ) /* __attribute__(( naked )) PRIVILEGED_FUNCTION */;\r
+extern void vClearInterruptMask( uint32_t ulMask ) /* __attribute__(( naked )) PRIVILEGED_FUNCTION */;\r
\r
#if( configENABLE_TRUSTZONE == 1 )\r
- extern void vPortAllocateSecureContext( uint32_t ulSecureStackSize );\r
- extern void vPortFreeSecureContext( uint32_t *pulTCB ) /* PRIVILEGED_FUNCTION */;\r
+ extern void vPortAllocateSecureContext( uint32_t ulSecureStackSize ); /* __attribute__ (( naked )) */\r
+ extern void vPortFreeSecureContext( uint32_t *pulTCB ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */;\r
#endif /* configENABLE_TRUSTZONE */\r
\r
#if( configENABLE_MPU == 1 )\r
/* MPU regions. */\r
#define portPRIVILEGED_FLASH_REGION ( 0UL )\r
#define portUNPRIVILEGED_FLASH_REGION ( 1UL )\r
-#define portPRIVILEGED_RAM_REGION ( 2UL )\r
-#define portUNPRIVILEGED_DEVICE_REGION ( 3UL )\r
+#define portUNPRIVILEGED_SYSCALLS_REGION ( 2UL )\r
+#define portPRIVILEGED_RAM_REGION ( 3UL )\r
#define portSTACK_REGION ( 4UL )\r
#define portFIRST_CONFIGURABLE_REGION ( 5UL )\r
#define portLAST_CONFIGURABLE_REGION ( 7UL )\r
#define portNUM_CONFIGURABLE_REGIONS ( ( portLAST_CONFIGURABLE_REGION - portFIRST_CONFIGURABLE_REGION ) + 1 )\r
#define portTOTAL_NUM_REGIONS ( portNUM_CONFIGURABLE_REGIONS + 1 ) /* Plus one to make space for the stack region. */\r
\r
-/* Devices Region. */\r
-#define portDEVICE_REGION_START_ADDRESS ( 0x50000000 )\r
-#define portDEVICE_REGION_END_ADDRESS ( 0x5FFFFFFF )\r
-\r
/* Device memory attributes used in MPU_MAIR registers.\r
*\r
* 8-bit values encoded as follows:\r
/**\r
* @brief Critical section management.\r
*/\r
-#define portSET_INTERRUPT_MASK_FROM_ISR() ulSetInterruptMaskFromISR()\r
-#define portCLEAR_INTERRUPT_MASK_FROM_ISR(x) vClearInterruptMaskFromISR( x )\r
-#define portDISABLE_INTERRUPTS() __asm volatile ( " cpsid i " ::: "memory" )\r
-#define portENABLE_INTERRUPTS() __asm volatile ( " cpsie i " ::: "memory" )\r
+#define portSET_INTERRUPT_MASK_FROM_ISR() ulSetInterruptMask()\r
+#define portCLEAR_INTERRUPT_MASK_FROM_ISR(x) vClearInterruptMask( x )\r
+#define portDISABLE_INTERRUPTS() ulSetInterruptMask()\r
+#define portENABLE_INTERRUPTS() vClearInterruptMask( 0 )\r
#define portENTER_CRITICAL() vPortEnterCritical()\r
#define portEXIT_CRITICAL() vPortExitCritical()\r
/*-----------------------------------------------------------*/\r
#endif /* configENABLE_MPU */\r
/*-----------------------------------------------------------*/\r
\r
+/**\r
+ * @brief Barriers.\r
+ */\r
+#define portMEMORY_BARRIER() __asm volatile( "" ::: "memory" )\r
+/*-----------------------------------------------------------*/\r
+\r
#ifdef __cplusplus\r
}\r
#endif\r