/*\r
- FreeRTOS V7.5.1 - Copyright (C) 2013 Real Time Engineers Ltd.\r
-\r
- VISIT http://www.FreeRTOS.org TO ENSURE YOU ARE USING THE LATEST VERSION.\r
-\r
- ***************************************************************************\r
- * *\r
- * FreeRTOS provides completely free yet professionally developed, *\r
- * robust, strictly quality controlled, supported, and cross *\r
- * platform software that has become a de facto standard. *\r
- * *\r
- * Help yourself get started quickly and support the FreeRTOS *\r
- * project by purchasing a FreeRTOS tutorial book, reference *\r
- * manual, or both from: http://www.FreeRTOS.org/Documentation *\r
- * *\r
- * Thank you! *\r
- * *\r
- ***************************************************************************\r
-\r
- This file is part of the FreeRTOS distribution.\r
-\r
- FreeRTOS is free software; you can redistribute it and/or modify it under\r
- the terms of the GNU General Public License (version 2) as published by the\r
- Free Software Foundation >>!AND MODIFIED BY!<< the FreeRTOS exception.\r
-\r
- >>! NOTE: The modification to the GPL is included to allow you to distribute\r
- >>! a combined work that includes FreeRTOS without being obliged to provide\r
- >>! the source code for proprietary components outside of the FreeRTOS\r
- >>! kernel.\r
-\r
- FreeRTOS is distributed in the hope that it will be useful, but WITHOUT ANY\r
- WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS\r
- FOR A PARTICULAR PURPOSE. Full license text is available from the following\r
- link: http://www.freertos.org/a00114.html\r
-\r
- 1 tab == 4 spaces!\r
-\r
- ***************************************************************************\r
- * *\r
- * Having a problem? Start by reading the FAQ "My application does *\r
- * not run, what could be wrong?" *\r
- * *\r
- * http://www.FreeRTOS.org/FAQHelp.html *\r
- * *\r
- ***************************************************************************\r
-\r
- http://www.FreeRTOS.org - Documentation, books, training, latest versions,\r
- license and Real Time Engineers Ltd. contact details.\r
-\r
- http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products,\r
- including FreeRTOS+Trace - an indispensable productivity tool, a DOS\r
- compatible FAT file system, and our tiny thread aware UDP/IP stack.\r
-\r
- http://www.OpenRTOS.com - Real Time Engineers ltd license FreeRTOS to High\r
- Integrity Systems to sell under the OpenRTOS brand. Low cost OpenRTOS\r
- licenses offer ticketed support, indemnification and middleware.\r
-\r
- http://www.SafeRTOS.com - High Integrity Systems also provide a safety\r
- engineered and independently SIL3 certified version for use in safety and\r
- mission critical applications that require provable dependability.\r
-\r
- 1 tab == 4 spaces!\r
-*/\r
+ * FreeRTOS Kernel V10.2.1\r
+ * Copyright (C) 2019 Amazon.com, Inc. or its affiliates. All Rights Reserved.\r
+ *\r
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of\r
+ * this software and associated documentation files (the "Software"), to deal in\r
+ * the Software without restriction, including without limitation the rights to\r
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of\r
+ * the Software, and to permit persons to whom the Software is furnished to do so,\r
+ * subject to the following conditions:\r
+ *\r
+ * The above copyright notice and this permission notice shall be included in all\r
+ * copies or substantial portions of the Software.\r
+ *\r
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR\r
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS\r
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR\r
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER\r
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN\r
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.\r
+ *\r
+ * http://www.FreeRTOS.org\r
+ * http://aws.amazon.com/freertos\r
+ *\r
+ * 1 tab == 4 spaces!\r
+ */\r
\r
/*-----------------------------------------------------------\r
* Implementation of functions defined in portable.h for the ARM CM3 port.\r
*----------------------------------------------------------*/\r
\r
/* Defining MPU_WRAPPERS_INCLUDED_FROM_API_FILE prevents task.h from redefining\r
-all the API functions to use the MPU wrappers. That should only be done when\r
-task.h is included from an application file. */\r
+ * all the API functions to use the MPU wrappers. That should only be done when\r
+ * task.h is included from an application file. */\r
#define MPU_WRAPPERS_INCLUDED_FROM_API_FILE\r
\r
/* Scheduler includes. */\r
#include "FreeRTOS.h"\r
#include "task.h"\r
-#include "queue.h"\r
\r
#undef MPU_WRAPPERS_INCLUDED_FROM_API_FILE\r
\r
+#ifndef configSYSTICK_CLOCK_HZ\r
+ #define configSYSTICK_CLOCK_HZ configCPU_CLOCK_HZ\r
+ /* Ensure the SysTick is clocked at the same frequency as the core. */\r
+ #define portNVIC_SYSTICK_CLK ( 1UL << 2UL )\r
+#else\r
+ /* The way the SysTick is clocked is not modified in case it is not the same\r
+ * as the core. */\r
+ #define portNVIC_SYSTICK_CLK ( 0 )\r
+#endif\r
+\r
/* Constants required to access and manipulate the NVIC. */\r
-#define portNVIC_SYSTICK_CTRL ( ( volatile unsigned long * ) 0xe000e010 )\r
-#define portNVIC_SYSTICK_LOAD ( ( volatile unsigned long * ) 0xe000e014 )\r
-#define portNVIC_SYSPRI2 ( ( volatile unsigned long * ) 0xe000ed20 )\r
-#define portNVIC_SYSPRI1 ( ( volatile unsigned long * ) 0xe000ed1c )\r
-#define portNVIC_SYS_CTRL_STATE ( ( volatile unsigned long * ) 0xe000ed24 )\r
+#define portNVIC_SYSTICK_CTRL_REG ( * ( ( volatile uint32_t * ) 0xe000e010 ) )\r
+#define portNVIC_SYSTICK_LOAD_REG ( * ( ( volatile uint32_t * ) 0xe000e014 ) )\r
+#define portNVIC_SYSTICK_CURRENT_VALUE_REG ( * ( ( volatile uint32_t * ) 0xe000e018 ) )\r
+#define portNVIC_SYSPRI2_REG ( * ( ( volatile uint32_t * ) 0xe000ed20 ) )\r
+#define portNVIC_SYSPRI1_REG ( * ( ( volatile uint32_t * ) 0xe000ed1c ) )\r
+#define portNVIC_SYS_CTRL_STATE_REG ( * ( ( volatile uint32_t * ) 0xe000ed24 ) )\r
#define portNVIC_MEM_FAULT_ENABLE ( 1UL << 16UL )\r
\r
/* Constants required to access and manipulate the MPU. */\r
-#define portMPU_TYPE ( ( volatile unsigned long * ) 0xe000ed90 )\r
-#define portMPU_REGION_BASE_ADDRESS ( ( volatile unsigned long * ) 0xe000ed9C )\r
-#define portMPU_REGION_ATTRIBUTE ( ( volatile unsigned long * ) 0xe000edA0 )\r
-#define portMPU_CTRL ( ( volatile unsigned long * ) 0xe000ed94 )\r
+#define portMPU_TYPE_REG ( * ( ( volatile uint32_t * ) 0xe000ed90 ) )\r
+#define portMPU_REGION_BASE_ADDRESS_REG ( * ( ( volatile uint32_t * ) 0xe000ed9C ) )\r
+#define portMPU_REGION_ATTRIBUTE_REG ( * ( ( volatile uint32_t * ) 0xe000edA0 ) )\r
+#define portMPU_CTRL_REG ( * ( ( volatile uint32_t * ) 0xe000ed94 ) )\r
#define portEXPECTED_MPU_TYPE_VALUE ( 8UL << 8UL ) /* 8 regions, unified. */\r
#define portMPU_ENABLE ( 0x01UL )\r
#define portMPU_BACKGROUND_ENABLE ( 1UL << 2UL )\r
#define portPERIPHERALS_END_ADDRESS 0x5FFFFFFFUL\r
\r
/* Constants required to access and manipulate the SysTick. */\r
-#define portNVIC_SYSTICK_CLK ( 0x00000004UL )\r
#define portNVIC_SYSTICK_INT ( 0x00000002UL )\r
#define portNVIC_SYSTICK_ENABLE ( 0x00000001UL )\r
-#define portNVIC_PENDSV_PRI ( ( ( unsigned long ) configKERNEL_INTERRUPT_PRIORITY ) << 16UL )\r
-#define portNVIC_SYSTICK_PRI ( ( ( unsigned long ) configKERNEL_INTERRUPT_PRIORITY ) << 24UL )\r
-#define portNVIC_SVC_PRI ( ( ( unsigned long ) configKERNEL_INTERRUPT_PRIORITY ) << 24UL )\r
+#define portNVIC_PENDSV_PRI ( ( ( uint32_t ) configKERNEL_INTERRUPT_PRIORITY ) << 16UL )\r
+#define portNVIC_SYSTICK_PRI ( ( ( uint32_t ) configKERNEL_INTERRUPT_PRIORITY ) << 24UL )\r
+#define portNVIC_SVC_PRI ( ( ( uint32_t ) configMAX_SYSCALL_INTERRUPT_PRIORITY - 1UL ) << 24UL )\r
\r
/* Constants required to set up the initial stack. */\r
#define portINITIAL_XPSR ( 0x01000000 )\r
#define portINITIAL_CONTROL_IF_UNPRIVILEGED ( 0x03 )\r
#define portINITIAL_CONTROL_IF_PRIVILEGED ( 0x02 )\r
\r
+/* Constants required to check the validity of an interrupt priority. */\r
+#define portFIRST_USER_INTERRUPT_NUMBER ( 16 )\r
+#define portNVIC_IP_REGISTERS_OFFSET_16 ( 0xE000E3F0 )\r
+#define portAIRCR_REG ( * ( ( volatile uint32_t * ) 0xE000ED0C ) )\r
+#define portMAX_8_BIT_VALUE ( ( uint8_t ) 0xff )\r
+#define portTOP_BIT_OF_BYTE ( ( uint8_t ) 0x80 )\r
+#define portMAX_PRIGROUP_BITS ( ( uint8_t ) 7 )\r
+#define portPRIORITY_GROUP_MASK ( 0x07UL << 8UL )\r
+#define portPRIGROUP_SHIFT ( 8UL )\r
+\r
/* Offsets in the stack to the parameters when inside the SVC handler. */\r
#define portOFFSET_TO_PC ( 6 )\r
\r
-/* Set the privilege level to user mode if xRunningPrivileged is false. */\r
-#define portRESET_PRIVILEGE( xRunningPrivileged ) if( xRunningPrivileged != pdTRUE ) __asm volatile ( " mrs r0, control \n orr r0, #1 \n msr control, r0" :::"r0" )\r
-\r
-/* Each task maintains its own interrupt status in the critical nesting\r
-variable. Note this is not saved as part of the task context as context\r
-switches can only occur when uxCriticalNesting is zero. */\r
-static unsigned portBASE_TYPE uxCriticalNesting = 0xaaaaaaaa;\r
-\r
-/*\r
- * Setup the timer to generate the tick interrupts.\r
- */\r
-static void prvSetupTimerInterrupt( void ) PRIVILEGED_FUNCTION;\r
+/* For strict compliance with the Cortex-M spec the task start address should\r
+ * have bit-0 clear, as it is loaded into the PC on exit from an ISR. */\r
+#define portSTART_ADDRESS_MASK ( ( StackType_t ) 0xfffffffeUL )\r
+/*-----------------------------------------------------------*/\r
\r
/*\r
* Configure a number of standard MPU regions that are used by all tasks.\r
* into. The region size is returned as the value that should be programmed\r
* into the region attribute register for that region.\r
*/\r
-static unsigned long prvGetMPURegionSizeSetting( unsigned long ulActualSizeInBytes ) PRIVILEGED_FUNCTION;\r
+static uint32_t prvGetMPURegionSizeSetting( uint32_t ulActualSizeInBytes ) PRIVILEGED_FUNCTION;\r
\r
/*\r
- * Checks to see if being called from the context of an unprivileged task, and\r
- * if so raises the privilege level and returns false - otherwise does nothing\r
- * other than return true.\r
+ * Setup the timer to generate the tick interrupts. The implementation in this\r
+ * file is weak to allow application writers to change the timer used to\r
+ * generate the tick interrupt.\r
*/\r
-static portBASE_TYPE prvRaisePrivilege( void ) __attribute__(( naked ));\r
+void vPortSetupTimerInterrupt( void );\r
\r
/*\r
* Standard FreeRTOS exception handlers.\r
* C portion of the SVC handler. The SVC handler is split between an asm entry\r
* and a C wrapper for simplicity of coding and maintenance.\r
*/\r
-static void prvSVCHandler( unsigned long *pulRegisters ) __attribute__(( noinline )) PRIVILEGED_FUNCTION;\r
+static void prvSVCHandler( uint32_t *pulRegisters ) __attribute__(( noinline )) PRIVILEGED_FUNCTION;\r
\r
-/*\r
- * Prototypes for all the MPU wrappers.\r
+/**\r
+ * @brief Checks whether or not the processor is privileged.\r
+ *\r
+ * @return 1 if the processor is already privileged, 0 otherwise.\r
*/\r
-signed portBASE_TYPE MPU_xTaskGenericCreate( pdTASK_CODE pvTaskCode, const signed char * const pcName, unsigned short usStackDepth, void *pvParameters, unsigned portBASE_TYPE uxPriority, xTaskHandle *pxCreatedTask, portSTACK_TYPE *puxStackBuffer, const xMemoryRegion * const xRegions );\r
-void MPU_vTaskAllocateMPURegions( xTaskHandle xTask, const xMemoryRegion * const xRegions );\r
-void MPU_vTaskDelete( xTaskHandle pxTaskToDelete );\r
-void MPU_vTaskDelayUntil( portTickType * const pxPreviousWakeTime, portTickType xTimeIncrement );\r
-void MPU_vTaskDelay( portTickType xTicksToDelay );\r
-unsigned portBASE_TYPE MPU_uxTaskPriorityGet( xTaskHandle pxTask );\r
-void MPU_vTaskPrioritySet( xTaskHandle pxTask, unsigned portBASE_TYPE uxNewPriority );\r
-eTaskState MPU_eTaskGetState( xTaskHandle pxTask );\r
-void MPU_vTaskSuspend( xTaskHandle pxTaskToSuspend );\r
-signed portBASE_TYPE MPU_xTaskIsTaskSuspended( xTaskHandle xTask );\r
-void MPU_vTaskResume( xTaskHandle pxTaskToResume );\r
-void MPU_vTaskSuspendAll( void );\r
-signed portBASE_TYPE MPU_xTaskResumeAll( void );\r
-portTickType MPU_xTaskGetTickCount( void );\r
-unsigned portBASE_TYPE MPU_uxTaskGetNumberOfTasks( void );\r
-void MPU_vTaskList( signed char *pcWriteBuffer );\r
-void MPU_vTaskGetRunTimeStats( signed char *pcWriteBuffer );\r
-void MPU_vTaskSetApplicationTaskTag( xTaskHandle xTask, pdTASK_HOOK_CODE pxTagValue );\r
-pdTASK_HOOK_CODE MPU_xTaskGetApplicationTaskTag( xTaskHandle xTask );\r
-portBASE_TYPE MPU_xTaskCallApplicationTaskHook( xTaskHandle xTask, void *pvParameter );\r
-unsigned portBASE_TYPE MPU_uxTaskGetStackHighWaterMark( xTaskHandle xTask );\r
-xTaskHandle MPU_xTaskGetCurrentTaskHandle( void );\r
-portBASE_TYPE MPU_xTaskGetSchedulerState( void );\r
-xTaskHandle MPU_xTaskGetIdleTaskHandle( void );\r
-unsigned portBASE_TYPE MPU_uxTaskGetSystemState( xTaskStatusType *pxTaskStatusArray, unsigned portBASE_TYPE uxArraySize, unsigned long *pulTotalRunTime );\r
-xQueueHandle MPU_xQueueGenericCreate( unsigned portBASE_TYPE uxQueueLength, unsigned portBASE_TYPE uxItemSize, unsigned char ucQueueType );\r
-signed portBASE_TYPE MPU_xQueueGenericSend( xQueueHandle xQueue, const void * const pvItemToQueue, portTickType xTicksToWait, portBASE_TYPE xCopyPosition );\r
-portBASE_TYPE MPU_xQueueGenericReset( xQueueHandle pxQueue, portBASE_TYPE xNewQueue );\r
-unsigned portBASE_TYPE MPU_uxQueueMessagesWaiting( const xQueueHandle pxQueue );\r
-signed portBASE_TYPE MPU_xQueueGenericReceive( xQueueHandle pxQueue, void * const pvBuffer, portTickType xTicksToWait, portBASE_TYPE xJustPeeking );\r
-xQueueHandle MPU_xQueueCreateMutex( void );\r
-xQueueHandle MPU_xQueueCreateCountingSemaphore( unsigned portBASE_TYPE uxCountValue, unsigned portBASE_TYPE uxInitialCount );\r
-portBASE_TYPE MPU_xQueueTakeMutexRecursive( xQueueHandle xMutex, portTickType xBlockTime );\r
-portBASE_TYPE MPU_xQueueGiveMutexRecursive( xQueueHandle xMutex );\r
-signed portBASE_TYPE MPU_xQueueAltGenericSend( xQueueHandle pxQueue, const void * const pvItemToQueue, portTickType xTicksToWait, portBASE_TYPE xCopyPosition );\r
-signed portBASE_TYPE MPU_xQueueAltGenericReceive( xQueueHandle pxQueue, void * const pvBuffer, portTickType xTicksToWait, portBASE_TYPE xJustPeeking );\r
-void MPU_vQueueAddToRegistry( xQueueHandle xQueue, signed char *pcName );\r
-void MPU_vQueueDelete( xQueueHandle xQueue );\r
-void *MPU_pvPortMalloc( size_t xSize );\r
-void MPU_vPortFree( void *pv );\r
-void MPU_vPortInitialiseBlocks( void );\r
-size_t MPU_xPortGetFreeHeapSize( void );\r
-xQueueSetHandle MPU_xQueueCreateSet( unsigned portBASE_TYPE uxEventQueueLength );\r
-xQueueSetMemberHandle MPU_xQueueSelectFromSet( xQueueSetHandle xQueueSet, portTickType xBlockTimeTicks );\r
-portBASE_TYPE MPU_xQueueAddToSet( xQueueSetMemberHandle xQueueOrSemaphore, xQueueSetHandle xQueueSet );\r
-portBASE_TYPE MPU_xQueueRemoveFromSet( xQueueSetMemberHandle xQueueOrSemaphore, xQueueSetHandle xQueueSet );\r
-signed portBASE_TYPE MPU_xQueuePeekFromISR( xQueueHandle xQueue, void * const pvBuffer );\r
+BaseType_t xIsPrivileged( void ) __attribute__ (( naked ));\r
+\r
+/**\r
+ * @brief Lowers the privilege level by setting the bit 0 of the CONTROL\r
+ * register.\r
+ *\r
+ * Bit 0 of the CONTROL register defines the privilege level of Thread Mode.\r
+ * Bit[0] = 0 --> The processor is running privileged\r
+ * Bit[0] = 1 --> The processor is running unprivileged.\r
+ */\r
+void vResetPrivilege( void ) __attribute__ (( naked ));\r
+\r
+/**\r
+ * @brief Calls the port specific code to raise the privilege.\r
+ *\r
+ * @return pdFALSE if privilege was raised, pdTRUE otherwise.\r
+ */\r
+extern BaseType_t xPortRaisePrivilege( void );\r
+\r
+/**\r
+ * @brief If xRunningPrivileged is not pdTRUE, calls the port specific\r
+ * code to reset the privilege, otherwise does nothing.\r
+ */\r
+extern void vPortResetPrivilege( BaseType_t xRunningPrivileged );\r
+/*-----------------------------------------------------------*/\r
+\r
+/* Each task maintains its own interrupt status in the critical nesting\r
+ * variable. Note this is not saved as part of the task context as context\r
+ * switches can only occur when uxCriticalNesting is zero. */\r
+static UBaseType_t uxCriticalNesting = 0xaaaaaaaa;\r
\r
+/*\r
+ * Used by the portASSERT_IF_INTERRUPT_PRIORITY_INVALID() macro to ensure\r
+ * FreeRTOS API functions are not called from interrupts that have been assigned\r
+ * a priority above configMAX_SYSCALL_INTERRUPT_PRIORITY.\r
+ */\r
+#if ( configASSERT_DEFINED == 1 )\r
+ static uint8_t ucMaxSysCallPriority = 0;\r
+ static uint32_t ulMaxPRIGROUPValue = 0;\r
+ static const volatile uint8_t * const pcInterruptPriorityRegisters = ( const volatile uint8_t * const ) portNVIC_IP_REGISTERS_OFFSET_16;\r
+#endif /* configASSERT_DEFINED */\r
/*-----------------------------------------------------------*/\r
\r
/*\r
* See header file for description.\r
*/\r
-portSTACK_TYPE *pxPortInitialiseStack( portSTACK_TYPE *pxTopOfStack, pdTASK_CODE pxCode, void *pvParameters, portBASE_TYPE xRunPrivileged )\r
+StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, TaskFunction_t pxCode, void *pvParameters, BaseType_t xRunPrivileged )\r
{\r
/* Simulate the stack frame as it would be created by a context switch\r
- interrupt. */\r
+ * interrupt. */\r
pxTopOfStack--; /* Offset added to account for the way the MCU uses the stack on entry/exit of interrupts. */\r
*pxTopOfStack = portINITIAL_XPSR; /* xPSR */\r
pxTopOfStack--;\r
- *pxTopOfStack = ( portSTACK_TYPE ) pxCode; /* PC */\r
+ *pxTopOfStack = ( ( StackType_t ) pxCode ) & portSTART_ADDRESS_MASK; /* PC */\r
pxTopOfStack--;\r
*pxTopOfStack = 0; /* LR */\r
pxTopOfStack -= 5; /* R12, R3, R2 and R1. */\r
- *pxTopOfStack = ( portSTACK_TYPE ) pvParameters; /* R0 */\r
+ *pxTopOfStack = ( StackType_t ) pvParameters; /* R0 */\r
pxTopOfStack -= 9; /* R11, R10, R9, R8, R7, R6, R5 and R4. */\r
\r
if( xRunPrivileged == pdTRUE )\r
" mrs r0, psp \n"\r
#endif\r
" b %0 \n"\r
- ::"i"(prvSVCHandler):"r0"\r
+ ::"i"(prvSVCHandler):"r0", "memory"\r
);\r
}\r
/*-----------------------------------------------------------*/\r
\r
-static void prvSVCHandler( unsigned long *pulParam )\r
+static void prvSVCHandler( uint32_t *pulParam )\r
{\r
-unsigned char ucSVCNumber;\r
+uint8_t ucSVCNumber;\r
+uint32_t ulPC;\r
+#if( configENFORCE_SYSTEM_CALLS_FROM_KERNEL_ONLY == 1 )\r
+ #if defined( __ARMCC_VERSION )\r
+ /* Declaration when these variable are defined in code instead of being\r
+ * exported from linker scripts. */\r
+ extern uint32_t * __syscalls_flash_start__;\r
+ extern uint32_t * __syscalls_flash_end__;\r
+ #else\r
+ /* Declaration when these variable are exported from linker scripts. */\r
+ extern uint32_t __syscalls_flash_start__[];\r
+ extern uint32_t __syscalls_flash_end__[];\r
+ #endif /* #if defined( __ARMCC_VERSION ) */\r
+#endif /* #if( configENFORCE_SYSTEM_CALLS_FROM_KERNEL_ONLY == 1 ) */\r
+\r
+ /* The stack contains: r0, r1, r2, r3, r12, LR, PC and xPSR. The first\r
+ * argument (r0) is pulParam[ 0 ]. */\r
+ ulPC = pulParam[ portOFFSET_TO_PC ];\r
+ ucSVCNumber = ( ( uint8_t * ) ulPC )[ -2 ];\r
\r
- /* The stack contains: r0, r1, r2, r3, r12, r14, the return address and\r
- xPSR. The first argument (r0) is pulParam[ 0 ]. */\r
- ucSVCNumber = ( ( unsigned char * ) pulParam[ portOFFSET_TO_PC ] )[ -2 ];\r
switch( ucSVCNumber )\r
{\r
- case portSVC_START_SCHEDULER : *(portNVIC_SYSPRI1) |= portNVIC_SVC_PRI;\r
+ case portSVC_START_SCHEDULER : portNVIC_SYSPRI1_REG |= portNVIC_SVC_PRI;\r
prvRestoreContextOfFirstTask();\r
break;\r
\r
- case portSVC_YIELD : *(portNVIC_INT_CTRL) = portNVIC_PENDSVSET;\r
+ case portSVC_YIELD : portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT;\r
/* Barriers are normally not required\r
- but do ensure the code is completely\r
- within the specified behaviour for the\r
- architecture. */\r
- __asm volatile( "dsb" );\r
+ * but do ensure the code is completely\r
+ * within the specified behaviour for the\r
+ * architecture. */\r
+ __asm volatile( "dsb" ::: "memory" );\r
__asm volatile( "isb" );\r
\r
break;\r
\r
+\r
+ #if( configENFORCE_SYSTEM_CALLS_FROM_KERNEL_ONLY == 1 )\r
+ case portSVC_RAISE_PRIVILEGE : /* Only raise the privilege, if the\r
+ * svc was raised from any of the\r
+ * system calls. */\r
+ if( ulPC >= ( uint32_t ) __syscalls_flash_start__ &&\r
+ ulPC <= ( uint32_t ) __syscalls_flash_end__ )\r
+ {\r
+ __asm volatile\r
+ (\r
+ " mrs r1, control \n" /* Obtain current control value. */\r
+ " bic r1, #1 \n" /* Set privilege bit. */\r
+ " msr control, r1 \n" /* Write back new control value. */\r
+ ::: "r1", "memory"\r
+ );\r
+ }\r
+ break;\r
+ #else\r
case portSVC_RAISE_PRIVILEGE : __asm volatile\r
(\r
" mrs r1, control \n" /* Obtain current control value. */\r
" bic r1, #1 \n" /* Set privilege bit. */\r
" msr control, r1 \n" /* Write back new control value. */\r
- :::"r1"\r
+ ::: "r1", "memory"\r
);\r
break;\r
+ #endif /* #if( configENFORCE_SYSTEM_CALLS_FROM_KERNEL_ONLY == 1 ) */\r
\r
default : /* Unknown SVC call. */\r
break;\r
" ldr r1, [r3] \n"\r
" ldr r0, [r1] \n" /* The first item in the TCB is the task top of stack. */\r
" add r1, r1, #4 \n" /* Move onto the second item in the TCB... */\r
+ " \n"\r
+ " dmb \n" /* Complete outstanding transfers before disabling MPU. */\r
+ " ldr r2, =0xe000ed94 \n" /* MPU_CTRL register. */\r
+ " ldr r3, [r2] \n" /* Read the value of MPU_CTRL. */\r
+ " bic r3, #1 \n" /* r3 = r3 & ~1 i.e. Clear the bit 0 in r3. */\r
+ " str r3, [r2] \n" /* Disable MPU. */\r
+ " \n"\r
" ldr r2, =0xe000ed9c \n" /* Region Base Address register. */\r
" ldmia r1!, {r4-r11} \n" /* Read 4 sets of MPU registers. */\r
" stmia r2!, {r4-r11} \n" /* Write 4 sets of MPU registers. */\r
+ " \n"\r
+ " ldr r2, =0xe000ed94 \n" /* MPU_CTRL register. */\r
+ " ldr r3, [r2] \n" /* Read the value of MPU_CTRL. */\r
+ " orr r3, #1 \n" /* r3 = r3 | 1 i.e. Set the bit 0 in r3. */\r
+ " str r3, [r2] \n" /* Enable MPU. */\r
+ " dsb \n" /* Force memory writes before continuing. */\r
+ " \n"\r
" ldmia r0!, {r3, r4-r11} \n" /* Pop the registers that are not automatically saved on exception entry. */\r
" msr control, r3 \n"\r
" msr psp, r0 \n" /* Restore the task stack pointer. */\r
" ldr r14, =0xfffffffd \n" /* Load exec return code. */\r
" bx r14 \n"\r
" \n"\r
- " .align 2 \n"\r
+ " .align 4 \n"\r
"pxCurrentTCBConst2: .word pxCurrentTCB \n"\r
);\r
}\r
/*\r
* See header file for description.\r
*/\r
-portBASE_TYPE xPortStartScheduler( void )\r
+BaseType_t xPortStartScheduler( void )\r
{\r
/* configMAX_SYSCALL_INTERRUPT_PRIORITY must not be set to 0. See\r
- http://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html */\r
+ * http://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html */\r
configASSERT( ( configMAX_SYSCALL_INTERRUPT_PRIORITY ) );\r
\r
- /* Make PendSV and SysTick the same priority as the kernel. */\r
- *(portNVIC_SYSPRI2) |= portNVIC_PENDSV_PRI;\r
- *(portNVIC_SYSPRI2) |= portNVIC_SYSTICK_PRI;\r
+ #if( configASSERT_DEFINED == 1 )\r
+ {\r
+ volatile uint32_t ulOriginalPriority;\r
+ volatile uint8_t * const pucFirstUserPriorityRegister = ( volatile uint8_t * const ) ( portNVIC_IP_REGISTERS_OFFSET_16 + portFIRST_USER_INTERRUPT_NUMBER );\r
+ volatile uint8_t ucMaxPriorityValue;\r
+\r
+ /* Determine the maximum priority from which ISR safe FreeRTOS API\r
+ * functions can be called. ISR safe functions are those that end in\r
+ * "FromISR". FreeRTOS maintains separate thread and ISR API functions\r
+ * to ensure interrupt entry is as fast and simple as possible.\r
+\r
+ * Save the interrupt priority value that is about to be clobbered. */\r
+ ulOriginalPriority = *pucFirstUserPriorityRegister;\r
+\r
+ /* Determine the number of priority bits available. First write to all\r
+ * possible bits. */\r
+ *pucFirstUserPriorityRegister = portMAX_8_BIT_VALUE;\r
+\r
+ /* Read the value back to see how many bits stuck. */\r
+ ucMaxPriorityValue = *pucFirstUserPriorityRegister;\r
+\r
+ /* Use the same mask on the maximum system call priority. */\r
+ ucMaxSysCallPriority = configMAX_SYSCALL_INTERRUPT_PRIORITY & ucMaxPriorityValue;\r
+\r
+ /* Calculate the maximum acceptable priority group value for the number\r
+ * of bits read back. */\r
+ ulMaxPRIGROUPValue = portMAX_PRIGROUP_BITS;\r
+ while( ( ucMaxPriorityValue & portTOP_BIT_OF_BYTE ) == portTOP_BIT_OF_BYTE )\r
+ {\r
+ ulMaxPRIGROUPValue--;\r
+ ucMaxPriorityValue <<= ( uint8_t ) 0x01;\r
+ }\r
+\r
+ #ifdef __NVIC_PRIO_BITS\r
+ {\r
+ /* Check the CMSIS configuration that defines the number of\r
+ * priority bits matches the number of priority bits actually queried\r
+ * from the hardware. */\r
+ configASSERT( ( portMAX_PRIGROUP_BITS - ulMaxPRIGROUPValue ) == __NVIC_PRIO_BITS );\r
+ }\r
+ #endif\r
+\r
+ #ifdef configPRIO_BITS\r
+ {\r
+ /* Check the FreeRTOS configuration that defines the number of\r
+ * priority bits matches the number of priority bits actually queried\r
+ * from the hardware. */\r
+ configASSERT( ( portMAX_PRIGROUP_BITS - ulMaxPRIGROUPValue ) == configPRIO_BITS );\r
+ }\r
+ #endif\r
+\r
+ /* Shift the priority group value back to its position within the AIRCR\r
+ * register. */\r
+ ulMaxPRIGROUPValue <<= portPRIGROUP_SHIFT;\r
+ ulMaxPRIGROUPValue &= portPRIORITY_GROUP_MASK;\r
+\r
+ /* Restore the clobbered interrupt priority register to its original\r
+ * value. */\r
+ *pucFirstUserPriorityRegister = ulOriginalPriority;\r
+ }\r
+ #endif /* conifgASSERT_DEFINED */\r
+\r
+ /* Make PendSV and SysTick the same priority as the kernel, and the SVC\r
+ * handler higher priority so it can be used to exit a critical section (where\r
+ * lower priorities are masked). */\r
+ portNVIC_SYSPRI2_REG |= portNVIC_PENDSV_PRI;\r
+ portNVIC_SYSPRI2_REG |= portNVIC_SYSTICK_PRI;\r
\r
/* Configure the regions in the MPU that are common to all tasks. */\r
prvSetupMPU();\r
\r
/* Start the timer that generates the tick ISR. Interrupts are disabled\r
- here already. */\r
- prvSetupTimerInterrupt();\r
+ * here already. */\r
+ vPortSetupTimerInterrupt();\r
\r
/* Initialise the critical nesting count ready for the first task. */\r
uxCriticalNesting = 0;\r
\r
/* Start the first task. */\r
- __asm volatile( " svc %0 \n"\r
- :: "i" (portSVC_START_SCHEDULER) );\r
+ __asm volatile(\r
+ " ldr r0, =0xE000ED08 \n" /* Use the NVIC offset register to locate the stack. */\r
+ " ldr r0, [r0] \n"\r
+ " ldr r0, [r0] \n"\r
+ " msr msp, r0 \n" /* Set the msp back to the start of the stack. */\r
+ " cpsie i \n" /* Globally enable interrupts. */\r
+ " cpsie f \n"\r
+ " dsb \n"\r
+ " isb \n"\r
+ " svc %0 \n" /* System call to start first task. */\r
+ " nop \n"\r
+ :: "i" (portSVC_START_SCHEDULER) : "memory" );\r
\r
/* Should not get here! */\r
return 0;\r
\r
void vPortEndScheduler( void )\r
{\r
- /* It is unlikely that the CM3 port will require this function as there\r
- is nothing to return to. */\r
+ /* Not implemented in ports where there is nothing to return to.\r
+ * Artificially force an assert. */\r
+ configASSERT( uxCriticalNesting == 1000UL );\r
}\r
/*-----------------------------------------------------------*/\r
\r
void vPortEnterCritical( void )\r
{\r
-portBASE_TYPE xRunningPrivileged = prvRaisePrivilege();\r
+BaseType_t xRunningPrivileged = xPortRaisePrivilege();\r
\r
portDISABLE_INTERRUPTS();\r
uxCriticalNesting++;\r
\r
- portRESET_PRIVILEGE( xRunningPrivileged );\r
+ vPortResetPrivilege( xRunningPrivileged );\r
}\r
/*-----------------------------------------------------------*/\r
\r
void vPortExitCritical( void )\r
{\r
-portBASE_TYPE xRunningPrivileged = prvRaisePrivilege();\r
+BaseType_t xRunningPrivileged = xPortRaisePrivilege();\r
\r
+ configASSERT( uxCriticalNesting );\r
uxCriticalNesting--;\r
if( uxCriticalNesting == 0 )\r
{\r
portENABLE_INTERRUPTS();\r
}\r
- portRESET_PRIVILEGE( xRunningPrivileged );\r
+ vPortResetPrivilege( xRunningPrivileged );\r
}\r
/*-----------------------------------------------------------*/\r
\r
" stmdb sp!, {r3, r14} \n"\r
" mov r0, %0 \n"\r
" msr basepri, r0 \n"\r
+ " dsb \n"\r
+ " isb \n"\r
" bl vTaskSwitchContext \n"\r
" mov r0, #0 \n"\r
" msr basepri, r0 \n"\r
" ldr r1, [r3] \n"\r
" ldr r0, [r1] \n" /* The first item in the TCB is the task top of stack. */\r
" add r1, r1, #4 \n" /* Move onto the second item in the TCB... */\r
+ " \n"\r
+ " dmb \n" /* Complete outstanding transfers before disabling MPU. */\r
+ " ldr r2, =0xe000ed94 \n" /* MPU_CTRL register. */\r
+ " ldr r3, [r2] \n" /* Read the value of MPU_CTRL. */\r
+ " bic r3, #1 \n" /* r3 = r3 & ~1 i.e. Clear the bit 0 in r3. */\r
+ " str r3, [r2] \n" /* Disable MPU. */\r
+ " \n"\r
" ldr r2, =0xe000ed9c \n" /* Region Base Address register. */\r
" ldmia r1!, {r4-r11} \n" /* Read 4 sets of MPU registers. */\r
" stmia r2!, {r4-r11} \n" /* Write 4 sets of MPU registers. */\r
+ " \n"\r
+ " ldr r2, =0xe000ed94 \n" /* MPU_CTRL register. */\r
+ " ldr r3, [r2] \n" /* Read the value of MPU_CTRL. */\r
+ " orr r3, #1 \n" /* r3 = r3 | 1 i.e. Set the bit 0 in r3. */\r
+ " str r3, [r2] \n" /* Enable MPU. */\r
+ " dsb \n" /* Force memory writes before continuing. */\r
+ " \n"\r
" ldmia r0!, {r3, r4-r11} \n" /* Pop the registers that are not automatically saved on exception entry. */\r
" msr control, r3 \n"\r
" \n"\r
" msr psp, r0 \n"\r
" bx r14 \n"\r
" \n"\r
- " .align 2 \n"\r
+ " .align 4 \n"\r
"pxCurrentTCBConst: .word pxCurrentTCB \n"\r
::"i"(configMAX_SYSCALL_INTERRUPT_PRIORITY)\r
);\r
\r
void xPortSysTickHandler( void )\r
{\r
-unsigned long ulDummy;\r
+uint32_t ulDummy;\r
\r
ulDummy = portSET_INTERRUPT_MASK_FROM_ISR();\r
{\r
if( xTaskIncrementTick() != pdFALSE )\r
{\r
/* Pend a context switch. */\r
- *(portNVIC_INT_CTRL) = portNVIC_PENDSVSET;\r
+ portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT;\r
}\r
}\r
portCLEAR_INTERRUPT_MASK_FROM_ISR( ulDummy );\r
* Setup the systick timer to generate the tick interrupts at the required\r
* frequency.\r
*/\r
-static void prvSetupTimerInterrupt( void )\r
+__attribute__(( weak )) void vPortSetupTimerInterrupt( void )\r
{\r
+ /* Stop and clear the SysTick. */\r
+ portNVIC_SYSTICK_CTRL_REG = 0UL;\r
+ portNVIC_SYSTICK_CURRENT_VALUE_REG = 0UL;\r
+\r
/* Configure SysTick to interrupt at the requested rate. */\r
- *(portNVIC_SYSTICK_LOAD) = ( configCPU_CLOCK_HZ / configTICK_RATE_HZ ) - 1UL;\r
- *(portNVIC_SYSTICK_CTRL) = portNVIC_SYSTICK_CLK | portNVIC_SYSTICK_INT | portNVIC_SYSTICK_ENABLE;\r
+ portNVIC_SYSTICK_LOAD_REG = ( configSYSTICK_CLOCK_HZ / configTICK_RATE_HZ ) - 1UL;\r
+ portNVIC_SYSTICK_CTRL_REG = ( portNVIC_SYSTICK_CLK | portNVIC_SYSTICK_INT | portNVIC_SYSTICK_ENABLE );\r
}\r
/*-----------------------------------------------------------*/\r
\r
static void prvSetupMPU( void )\r
{\r
-extern unsigned long __privileged_functions_end__[];\r
-extern unsigned long __FLASH_segment_start__[];\r
-extern unsigned long __FLASH_segment_end__[];\r
-extern unsigned long __privileged_data_start__[];\r
-extern unsigned long __privileged_data_end__[];\r
+extern uint32_t __privileged_functions_end__[];\r
+extern uint32_t __FLASH_segment_start__[];\r
+extern uint32_t __FLASH_segment_end__[];\r
+extern uint32_t __privileged_data_start__[];\r
+extern uint32_t __privileged_data_end__[];\r
\r
/* Check the expected MPU is present. */\r
- if( *portMPU_TYPE == portEXPECTED_MPU_TYPE_VALUE )\r
+ if( portMPU_TYPE_REG == portEXPECTED_MPU_TYPE_VALUE )\r
{\r
/* First setup the entire flash for unprivileged read only access. */\r
- *portMPU_REGION_BASE_ADDRESS = ( ( unsigned long ) __FLASH_segment_start__ ) | /* Base address. */\r
- ( portMPU_REGION_VALID ) |\r
- ( portUNPRIVILEGED_FLASH_REGION );\r
+ portMPU_REGION_BASE_ADDRESS_REG = ( ( uint32_t ) __FLASH_segment_start__ ) | /* Base address. */\r
+ ( portMPU_REGION_VALID ) |\r
+ ( portUNPRIVILEGED_FLASH_REGION );\r
\r
- *portMPU_REGION_ATTRIBUTE = ( portMPU_REGION_READ_ONLY ) |\r
+ portMPU_REGION_ATTRIBUTE_REG = ( portMPU_REGION_READ_ONLY ) |\r
( portMPU_REGION_CACHEABLE_BUFFERABLE ) |\r
- ( prvGetMPURegionSizeSetting( ( unsigned long ) __FLASH_segment_end__ - ( unsigned long ) __FLASH_segment_start__ ) ) |\r
+ ( prvGetMPURegionSizeSetting( ( uint32_t ) __FLASH_segment_end__ - ( uint32_t ) __FLASH_segment_start__ ) ) |\r
( portMPU_REGION_ENABLE );\r
\r
/* Setup the first 16K for privileged only access (even though less\r
- than 10K is actually being used). This is where the kernel code is\r
- placed. */\r
- *portMPU_REGION_BASE_ADDRESS = ( ( unsigned long ) __FLASH_segment_start__ ) | /* Base address. */\r
- ( portMPU_REGION_VALID ) |\r
- ( portPRIVILEGED_FLASH_REGION );\r
+ * than 10K is actually being used). This is where the kernel code is\r
+ * placed. */\r
+ portMPU_REGION_BASE_ADDRESS_REG = ( ( uint32_t ) __FLASH_segment_start__ ) | /* Base address. */\r
+ ( portMPU_REGION_VALID ) |\r
+ ( portPRIVILEGED_FLASH_REGION );\r
\r
- *portMPU_REGION_ATTRIBUTE = ( portMPU_REGION_PRIVILEGED_READ_ONLY ) |\r
+ portMPU_REGION_ATTRIBUTE_REG = ( portMPU_REGION_PRIVILEGED_READ_ONLY ) |\r
( portMPU_REGION_CACHEABLE_BUFFERABLE ) |\r
- ( prvGetMPURegionSizeSetting( ( unsigned long ) __privileged_functions_end__ - ( unsigned long ) __FLASH_segment_start__ ) ) |\r
+ ( prvGetMPURegionSizeSetting( ( uint32_t ) __privileged_functions_end__ - ( uint32_t ) __FLASH_segment_start__ ) ) |\r
( portMPU_REGION_ENABLE );\r
\r
/* Setup the privileged data RAM region. This is where the kernel data\r
- is placed. */\r
- *portMPU_REGION_BASE_ADDRESS = ( ( unsigned long ) __privileged_data_start__ ) | /* Base address. */\r
- ( portMPU_REGION_VALID ) |\r
- ( portPRIVILEGED_RAM_REGION );\r
+ * is placed. */\r
+ portMPU_REGION_BASE_ADDRESS_REG = ( ( uint32_t ) __privileged_data_start__ ) | /* Base address. */\r
+ ( portMPU_REGION_VALID ) |\r
+ ( portPRIVILEGED_RAM_REGION );\r
\r
- *portMPU_REGION_ATTRIBUTE = ( portMPU_REGION_PRIVILEGED_READ_WRITE ) |\r
+ portMPU_REGION_ATTRIBUTE_REG = ( portMPU_REGION_PRIVILEGED_READ_WRITE ) |\r
( portMPU_REGION_CACHEABLE_BUFFERABLE ) |\r
- prvGetMPURegionSizeSetting( ( unsigned long ) __privileged_data_end__ - ( unsigned long ) __privileged_data_start__ ) |\r
+ prvGetMPURegionSizeSetting( ( uint32_t ) __privileged_data_end__ - ( uint32_t ) __privileged_data_start__ ) |\r
( portMPU_REGION_ENABLE );\r
\r
/* By default allow everything to access the general peripherals. The\r
- system peripherals and registers are protected. */\r
- *portMPU_REGION_BASE_ADDRESS = ( portPERIPHERALS_START_ADDRESS ) |\r
- ( portMPU_REGION_VALID ) |\r
- ( portGENERAL_PERIPHERALS_REGION );\r
+ * system peripherals and registers are protected. */\r
+ portMPU_REGION_BASE_ADDRESS_REG = ( portPERIPHERALS_START_ADDRESS ) |\r
+ ( portMPU_REGION_VALID ) |\r
+ ( portGENERAL_PERIPHERALS_REGION );\r
\r
- *portMPU_REGION_ATTRIBUTE = ( portMPU_REGION_READ_WRITE | portMPU_REGION_EXECUTE_NEVER ) |\r
+ portMPU_REGION_ATTRIBUTE_REG = ( portMPU_REGION_READ_WRITE | portMPU_REGION_EXECUTE_NEVER ) |\r
( prvGetMPURegionSizeSetting( portPERIPHERALS_END_ADDRESS - portPERIPHERALS_START_ADDRESS ) ) |\r
( portMPU_REGION_ENABLE );\r
\r
/* Enable the memory fault exception. */\r
- *portNVIC_SYS_CTRL_STATE |= portNVIC_MEM_FAULT_ENABLE;\r
+ portNVIC_SYS_CTRL_STATE_REG |= portNVIC_MEM_FAULT_ENABLE;\r
\r
/* Enable the MPU with the background region configured. */\r
- *portMPU_CTRL |= ( portMPU_ENABLE | portMPU_BACKGROUND_ENABLE );\r
+ portMPU_CTRL_REG |= ( portMPU_ENABLE | portMPU_BACKGROUND_ENABLE );\r
}\r
}\r
/*-----------------------------------------------------------*/\r
\r
-static unsigned long prvGetMPURegionSizeSetting( unsigned long ulActualSizeInBytes )\r
+static uint32_t prvGetMPURegionSizeSetting( uint32_t ulActualSizeInBytes )\r
{\r
-unsigned long ulRegionSize, ulReturnValue = 4;\r
+uint32_t ulRegionSize, ulReturnValue = 4;\r
\r
/* 32 is the smallest region size, 31 is the largest valid value for\r
- ulReturnValue. */\r
+ * ulReturnValue. */\r
for( ulRegionSize = 32UL; ulReturnValue < 31UL; ( ulRegionSize <<= 1UL ) )\r
{\r
if( ulActualSizeInBytes <= ulRegionSize )\r
}\r
\r
/* Shift the code by one before returning so it can be written directly\r
- into the the correct bit position of the attribute register. */\r
+ * into the the correct bit position of the attribute register. */\r
return ( ulReturnValue << 1UL );\r
}\r
/*-----------------------------------------------------------*/\r
\r
-static portBASE_TYPE prvRaisePrivilege( void )\r
+BaseType_t xIsPrivileged( void ) /* __attribute__ (( naked )) */\r
{\r
__asm volatile\r
(\r
- " mrs r0, control \n"\r
- " tst r0, #1 \n" /* Is the task running privileged? */\r
- " itte ne \n"\r
- " movne r0, #0 \n" /* CONTROL[0]!=0, return false. */\r
- " svcne %0 \n" /* Switch to privileged. */\r
- " moveq r0, #1 \n" /* CONTROL[0]==0, return true. */\r
- " bx lr \n"\r
- :: "i" (portSVC_RAISE_PRIVILEGE) : "r0"\r
+ " mrs r0, control \n" /* r0 = CONTROL. */\r
+ " tst r0, #1 \n" /* Perform r0 & 1 (bitwise AND) and update the conditions flag. */\r
+ " ite ne \n"\r
+ " movne r0, #0 \n" /* CONTROL[0]!=0. Return false to indicate that the processor is not privileged. */\r
+ " moveq r0, #1 \n" /* CONTROL[0]==0. Return true to indicate that the processor is privileged. */\r
+ " bx lr \n" /* Return. */\r
+ " \n"\r
+ " .align 4 \n"\r
+ ::: "r0", "memory"\r
);\r
+}\r
+/*-----------------------------------------------------------*/\r
\r
- return 0;\r
+void vResetPrivilege( void ) /* __attribute__ (( naked )) */\r
+{\r
+ __asm volatile\r
+ (\r
+ " mrs r0, control \n" /* r0 = CONTROL. */\r
+ " orr r0, #1 \n" /* r0 = r0 | 1. */\r
+ " msr control, r0 \n" /* CONTROL = r0. */\r
+ " bx lr \n" /* Return to the caller. */\r
+ :::"r0", "memory"\r
+ );\r
}\r
/*-----------------------------------------------------------*/\r
\r
-void vPortStoreTaskMPUSettings( xMPU_SETTINGS *xMPUSettings, const struct xMEMORY_REGION * const xRegions, portSTACK_TYPE *pxBottomOfStack, unsigned short usStackDepth )\r
+void vPortStoreTaskMPUSettings( xMPU_SETTINGS *xMPUSettings, const struct xMEMORY_REGION * const xRegions, StackType_t *pxBottomOfStack, uint32_t ulStackDepth )\r
{\r
-extern unsigned long __SRAM_segment_start__[];\r
-extern unsigned long __SRAM_segment_end__[];\r
-extern unsigned long __privileged_data_start__[];\r
-extern unsigned long __privileged_data_end__[];\r
-long lIndex;\r
-unsigned long ul;\r
+extern uint32_t __SRAM_segment_start__[];\r
+extern uint32_t __SRAM_segment_end__[];\r
+extern uint32_t __privileged_data_start__[];\r
+extern uint32_t __privileged_data_end__[];\r
+int32_t lIndex;\r
+uint32_t ul;\r
\r
if( xRegions == NULL )\r
{\r
/* No MPU regions are specified so allow access to all RAM. */\r
- xMPUSettings->xRegion[ 0 ].ulRegionBaseAddress =\r
- ( ( unsigned long ) __SRAM_segment_start__ ) | /* Base address. */\r
+ xMPUSettings->xRegion[ 0 ].ulRegionBaseAddress =\r
+ ( ( uint32_t ) __SRAM_segment_start__ ) | /* Base address. */\r
( portMPU_REGION_VALID ) |\r
( portSTACK_REGION );\r
\r
xMPUSettings->xRegion[ 0 ].ulRegionAttribute =\r
( portMPU_REGION_READ_WRITE ) |\r
( portMPU_REGION_CACHEABLE_BUFFERABLE ) |\r
- ( prvGetMPURegionSizeSetting( ( unsigned long ) __SRAM_segment_end__ - ( unsigned long ) __SRAM_segment_start__ ) ) |\r
+ ( prvGetMPURegionSizeSetting( ( uint32_t ) __SRAM_segment_end__ - ( uint32_t ) __SRAM_segment_start__ ) ) |\r
( portMPU_REGION_ENABLE );\r
\r
/* Re-instate the privileged only RAM region as xRegion[ 0 ] will have\r
- just removed the privileged only parameters. */\r
+ * just removed the privileged only parameters. */\r
xMPUSettings->xRegion[ 1 ].ulRegionBaseAddress =\r
- ( ( unsigned long ) __privileged_data_start__ ) | /* Base address. */\r
+ ( ( uint32_t ) __privileged_data_start__ ) | /* Base address. */\r
( portMPU_REGION_VALID ) |\r
( portSTACK_REGION + 1 );\r
\r
xMPUSettings->xRegion[ 1 ].ulRegionAttribute =\r
( portMPU_REGION_PRIVILEGED_READ_WRITE ) |\r
( portMPU_REGION_CACHEABLE_BUFFERABLE ) |\r
- prvGetMPURegionSizeSetting( ( unsigned long ) __privileged_data_end__ - ( unsigned long ) __privileged_data_start__ ) |\r
+ prvGetMPURegionSizeSetting( ( uint32_t ) __privileged_data_end__ - ( uint32_t ) __privileged_data_start__ ) |\r
( portMPU_REGION_ENABLE );\r
\r
/* Invalidate all other regions. */\r
else\r
{\r
/* This function is called automatically when the task is created - in\r
- which case the stack region parameters will be valid. At all other\r
- times the stack parameters will not be valid and it is assumed that the\r
- stack region has already been configured. */\r
- if( usStackDepth > 0 )\r
+ * which case the stack region parameters will be valid. At all other\r
+ * times the stack parameters will not be valid and it is assumed that the\r
+ * stack region has already been configured. */\r
+ if( ulStackDepth > 0 )\r
{\r
/* Define the region that allows access to the stack. */\r
xMPUSettings->xRegion[ 0 ].ulRegionBaseAddress =\r
- ( ( unsigned long ) pxBottomOfStack ) |\r
+ ( ( uint32_t ) pxBottomOfStack ) |\r
( portMPU_REGION_VALID ) |\r
( portSTACK_REGION ); /* Region number. */\r
\r
xMPUSettings->xRegion[ 0 ].ulRegionAttribute =\r
( portMPU_REGION_READ_WRITE ) | /* Read and write. */\r
- ( prvGetMPURegionSizeSetting( ( unsigned long ) usStackDepth * ( unsigned long ) sizeof( portSTACK_TYPE ) ) ) |\r
+ ( prvGetMPURegionSizeSetting( ulStackDepth * ( uint32_t ) sizeof( StackType_t ) ) ) |\r
( portMPU_REGION_CACHEABLE_BUFFERABLE ) |\r
( portMPU_REGION_ENABLE );\r
}\r
if( ( xRegions[ lIndex ] ).ulLengthInBytes > 0UL )\r
{\r
/* Translate the generic region definition contained in\r
- xRegions into the CM3 specific MPU settings that are then\r
- stored in xMPUSettings. */\r
+ * xRegions into the CM3 specific MPU settings that are then\r
+ * stored in xMPUSettings. */\r
xMPUSettings->xRegion[ ul ].ulRegionBaseAddress =\r
- ( ( unsigned long ) xRegions[ lIndex ].pvBaseAddress ) |\r
+ ( ( uint32_t ) xRegions[ lIndex ].pvBaseAddress ) |\r
( portMPU_REGION_VALID ) |\r
( portSTACK_REGION + ul ); /* Region number. */\r
\r
}\r
/*-----------------------------------------------------------*/\r
\r
-signed portBASE_TYPE MPU_xTaskGenericCreate( pdTASK_CODE pvTaskCode, const signed char * const pcName, unsigned short usStackDepth, void *pvParameters, unsigned portBASE_TYPE uxPriority, xTaskHandle *pxCreatedTask, portSTACK_TYPE *puxStackBuffer, const xMemoryRegion * const xRegions )\r
-{\r
-signed portBASE_TYPE xReturn;\r
-portBASE_TYPE xRunningPrivileged = prvRaisePrivilege();\r
-\r
- xReturn = xTaskGenericCreate( pvTaskCode, pcName, usStackDepth, pvParameters, uxPriority, pxCreatedTask, puxStackBuffer, xRegions );\r
- portRESET_PRIVILEGE( xRunningPrivileged );\r
- return xReturn;\r
-}\r
-/*-----------------------------------------------------------*/\r
-\r
-void MPU_vTaskAllocateMPURegions( xTaskHandle xTask, const xMemoryRegion * const xRegions )\r
-{\r
-portBASE_TYPE xRunningPrivileged = prvRaisePrivilege();\r
-\r
- vTaskAllocateMPURegions( xTask, xRegions );\r
- portRESET_PRIVILEGE( xRunningPrivileged );\r
-}\r
-/*-----------------------------------------------------------*/\r
-\r
-#if ( INCLUDE_vTaskDelete == 1 )\r
- void MPU_vTaskDelete( xTaskHandle pxTaskToDelete )\r
- {\r
- portBASE_TYPE xRunningPrivileged = prvRaisePrivilege();\r
-\r
- vTaskDelete( pxTaskToDelete );\r
- portRESET_PRIVILEGE( xRunningPrivileged );\r
- }\r
-#endif\r
-/*-----------------------------------------------------------*/\r
-\r
-#if ( INCLUDE_vTaskDelayUntil == 1 )\r
- void MPU_vTaskDelayUntil( portTickType * const pxPreviousWakeTime, portTickType xTimeIncrement )\r
- {\r
- portBASE_TYPE xRunningPrivileged = prvRaisePrivilege();\r
-\r
- vTaskDelayUntil( pxPreviousWakeTime, xTimeIncrement );\r
- portRESET_PRIVILEGE( xRunningPrivileged );\r
- }\r
-#endif\r
-/*-----------------------------------------------------------*/\r
-\r
-#if ( INCLUDE_vTaskDelay == 1 )\r
- void MPU_vTaskDelay( portTickType xTicksToDelay )\r
- {\r
- portBASE_TYPE xRunningPrivileged = prvRaisePrivilege();\r
-\r
- vTaskDelay( xTicksToDelay );\r
- portRESET_PRIVILEGE( xRunningPrivileged );\r
- }\r
-#endif\r
-/*-----------------------------------------------------------*/\r
-\r
-#if ( INCLUDE_uxTaskPriorityGet == 1 )\r
- unsigned portBASE_TYPE MPU_uxTaskPriorityGet( xTaskHandle pxTask )\r
- {\r
- unsigned portBASE_TYPE uxReturn;\r
- portBASE_TYPE xRunningPrivileged = prvRaisePrivilege();\r
-\r
- uxReturn = uxTaskPriorityGet( pxTask );\r
- portRESET_PRIVILEGE( xRunningPrivileged );\r
- return uxReturn;\r
- }\r
-#endif\r
-/*-----------------------------------------------------------*/\r
-\r
-#if ( INCLUDE_vTaskPrioritySet == 1 )\r
- void MPU_vTaskPrioritySet( xTaskHandle pxTask, unsigned portBASE_TYPE uxNewPriority )\r
- {\r
- portBASE_TYPE xRunningPrivileged = prvRaisePrivilege();\r
-\r
- vTaskPrioritySet( pxTask, uxNewPriority );\r
- portRESET_PRIVILEGE( xRunningPrivileged );\r
- }\r
-#endif\r
-/*-----------------------------------------------------------*/\r
-\r
-#if ( INCLUDE_eTaskGetState == 1 )\r
- eTaskState MPU_eTaskGetState( xTaskHandle pxTask )\r
- {\r
- portBASE_TYPE xRunningPrivileged = prvRaisePrivilege();\r
- eTaskState eReturn;\r
-\r
- eReturn = eTaskGetState( pxTask );\r
- portRESET_PRIVILEGE( xRunningPrivileged );\r
- return eReturn;\r
- }\r
-#endif\r
-/*-----------------------------------------------------------*/\r
-\r
-#if ( INCLUDE_xTaskGetIdleTaskHandle == 1 )\r
- xTaskHandle MPU_xTaskGetIdleTaskHandle( void )\r
- {\r
- xTaskHandle xReturn;\r
- portBASE_TYPE xRunningPrivileged = prvRaisePrivilege();\r
-\r
- xReturn = xTaskGetIdleTaskHandle();\r
- portRESET_PRIVILEGE( xRunningPrivileged );\r
- return eReturn;\r
- }\r
-#endif\r
-/*-----------------------------------------------------------*/\r
-\r
-#if ( INCLUDE_vTaskSuspend == 1 )\r
- void MPU_vTaskSuspend( xTaskHandle pxTaskToSuspend )\r
- {\r
- portBASE_TYPE xRunningPrivileged = prvRaisePrivilege();\r
-\r
- vTaskSuspend( pxTaskToSuspend );\r
- portRESET_PRIVILEGE( xRunningPrivileged );\r
- }\r
-#endif\r
-/*-----------------------------------------------------------*/\r
-\r
-#if ( INCLUDE_vTaskSuspend == 1 )\r
- signed portBASE_TYPE MPU_xTaskIsTaskSuspended( xTaskHandle xTask )\r
- {\r
- signed portBASE_TYPE xReturn;\r
- portBASE_TYPE xRunningPrivileged = prvRaisePrivilege();\r
-\r
- xReturn = xTaskIsTaskSuspended( xTask );\r
- portRESET_PRIVILEGE( xRunningPrivileged );\r
- return xReturn;\r
- }\r
-#endif\r
-/*-----------------------------------------------------------*/\r
-\r
-#if ( INCLUDE_vTaskSuspend == 1 )\r
- void MPU_vTaskResume( xTaskHandle pxTaskToResume )\r
- {\r
- portBASE_TYPE xRunningPrivileged = prvRaisePrivilege();\r
-\r
- vTaskResume( pxTaskToResume );\r
- portRESET_PRIVILEGE( xRunningPrivileged );\r
- }\r
-#endif\r
-/*-----------------------------------------------------------*/\r
-\r
-void MPU_vTaskSuspendAll( void )\r
-{\r
-portBASE_TYPE xRunningPrivileged = prvRaisePrivilege();\r
-\r
- vTaskSuspendAll();\r
- portRESET_PRIVILEGE( xRunningPrivileged );\r
-}\r
-/*-----------------------------------------------------------*/\r
-\r
-signed portBASE_TYPE MPU_xTaskResumeAll( void )\r
-{\r
-signed portBASE_TYPE xReturn;\r
-portBASE_TYPE xRunningPrivileged = prvRaisePrivilege();\r
-\r
- xReturn = xTaskResumeAll();\r
- portRESET_PRIVILEGE( xRunningPrivileged );\r
- return xReturn;\r
-}\r
-/*-----------------------------------------------------------*/\r
-\r
-portTickType MPU_xTaskGetTickCount( void )\r
-{\r
-portTickType xReturn;\r
-portBASE_TYPE xRunningPrivileged = prvRaisePrivilege();\r
-\r
- xReturn = xTaskGetTickCount();\r
- portRESET_PRIVILEGE( xRunningPrivileged );\r
- return xReturn;\r
-}\r
-/*-----------------------------------------------------------*/\r
-\r
-unsigned portBASE_TYPE MPU_uxTaskGetNumberOfTasks( void )\r
-{\r
-unsigned portBASE_TYPE uxReturn;\r
-portBASE_TYPE xRunningPrivileged = prvRaisePrivilege();\r
-\r
- uxReturn = uxTaskGetNumberOfTasks();\r
- portRESET_PRIVILEGE( xRunningPrivileged );\r
- return uxReturn;\r
-}\r
-/*-----------------------------------------------------------*/\r
-\r
-#if ( configUSE_TRACE_FACILITY == 1 )\r
- void MPU_vTaskList( signed char *pcWriteBuffer )\r
- {\r
- portBASE_TYPE xRunningPrivileged = prvRaisePrivilege();\r
-\r
- vTaskList( pcWriteBuffer );\r
- portRESET_PRIVILEGE( xRunningPrivileged );\r
- }\r
-#endif\r
-/*-----------------------------------------------------------*/\r
-\r
-#if ( configGENERATE_RUN_TIME_STATS == 1 )\r
- void MPU_vTaskGetRunTimeStats( signed char *pcWriteBuffer )\r
- {\r
- portBASE_TYPE xRunningPrivileged = prvRaisePrivilege();\r
-\r
- vTaskGetRunTimeStats( pcWriteBuffer );\r
- portRESET_PRIVILEGE( xRunningPrivileged );\r
- }\r
-#endif\r
-/*-----------------------------------------------------------*/\r
-\r
-#if ( configUSE_APPLICATION_TASK_TAG == 1 )\r
- void MPU_vTaskSetApplicationTaskTag( xTaskHandle xTask, pdTASK_HOOK_CODE pxTagValue )\r
- {\r
- portBASE_TYPE xRunningPrivileged = prvRaisePrivilege();\r
-\r
- vTaskSetApplicationTaskTag( xTask, pxTagValue );\r
- portRESET_PRIVILEGE( xRunningPrivileged );\r
- }\r
-#endif\r
-/*-----------------------------------------------------------*/\r
-\r
-#if ( configUSE_APPLICATION_TASK_TAG == 1 )\r
- pdTASK_HOOK_CODE MPU_xTaskGetApplicationTaskTag( xTaskHandle xTask )\r
- {\r
- pdTASK_HOOK_CODE xReturn;\r
- portBASE_TYPE xRunningPrivileged = prvRaisePrivilege();\r
-\r
- xReturn = xTaskGetApplicationTaskTag( xTask );\r
- portRESET_PRIVILEGE( xRunningPrivileged );\r
- return xReturn;\r
- }\r
-#endif\r
-/*-----------------------------------------------------------*/\r
-\r
-#if ( configUSE_APPLICATION_TASK_TAG == 1 )\r
- portBASE_TYPE MPU_xTaskCallApplicationTaskHook( xTaskHandle xTask, void *pvParameter )\r
- {\r
- portBASE_TYPE xReturn;\r
- portBASE_TYPE xRunningPrivileged = prvRaisePrivilege();\r
-\r
- xReturn = xTaskCallApplicationTaskHook( xTask, pvParameter );\r
- portRESET_PRIVILEGE( xRunningPrivileged );\r
- return xReturn;\r
- }\r
-#endif\r
-/*-----------------------------------------------------------*/\r
-\r
-#if ( configUSE_TRACE_FACILITY == 1 )\r
- unsigned portBASE_TYPE MPU_uxTaskGetSystemState( xTaskStatusType *pxTaskStatusArray, unsigned portBASE_TYPE uxArraySize, unsigned long *pulTotalRunTime )\r
- {\r
- unsigned portBASE_TYPE uxReturn;\r
- portBASE_TYPE xRunningPrivileged = prvRaisePrivilege();\r
-\r
- uxReturn = uxTaskGetSystemState( pxTaskStatusArray, uxArraySize, pulTotalRunTime );\r
- portRESET_PRIVILEGE( xRunningPrivileged );\r
- return xReturn;\r
- }\r
-#endif\r
-/*-----------------------------------------------------------*/\r
-\r
-#if ( INCLUDE_uxTaskGetStackHighWaterMark == 1 )\r
- unsigned portBASE_TYPE MPU_uxTaskGetStackHighWaterMark( xTaskHandle xTask )\r
- {\r
- unsigned portBASE_TYPE uxReturn;\r
- portBASE_TYPE xRunningPrivileged = prvRaisePrivilege();\r
-\r
- uxReturn = uxTaskGetStackHighWaterMark( xTask );\r
- portRESET_PRIVILEGE( xRunningPrivileged );\r
- return uxReturn;\r
- }\r
-#endif\r
-/*-----------------------------------------------------------*/\r
-\r
-#if ( INCLUDE_xTaskGetCurrentTaskHandle == 1 )\r
- xTaskHandle MPU_xTaskGetCurrentTaskHandle( void )\r
- {\r
- xTaskHandle xReturn;\r
- portBASE_TYPE xRunningPrivileged = prvRaisePrivilege();\r
-\r
- xReturn = xTaskGetCurrentTaskHandle();\r
- portRESET_PRIVILEGE( xRunningPrivileged );\r
- return xReturn;\r
- }\r
-#endif\r
-/*-----------------------------------------------------------*/\r
-\r
-#if ( INCLUDE_xTaskGetSchedulerState == 1 )\r
- portBASE_TYPE MPU_xTaskGetSchedulerState( void )\r
- {\r
- portBASE_TYPE xReturn;\r
- portBASE_TYPE xRunningPrivileged = prvRaisePrivilege();\r
-\r
- xReturn = xTaskGetSchedulerState();\r
- portRESET_PRIVILEGE( xRunningPrivileged );\r
- return xReturn;\r
- }\r
-#endif\r
-/*-----------------------------------------------------------*/\r
-\r
-xQueueHandle MPU_xQueueGenericCreate( unsigned portBASE_TYPE uxQueueLength, unsigned portBASE_TYPE uxItemSize, unsigned char ucQueueType )\r
-{\r
-xQueueHandle xReturn;\r
-portBASE_TYPE xRunningPrivileged = prvRaisePrivilege();\r
-\r
- xReturn = xQueueGenericCreate( uxQueueLength, uxItemSize, ucQueueType );\r
- portRESET_PRIVILEGE( xRunningPrivileged );\r
- return xReturn;\r
-}\r
-/*-----------------------------------------------------------*/\r
-\r
-portBASE_TYPE MPU_xQueueGenericReset( xQueueHandle pxQueue, portBASE_TYPE xNewQueue )\r
-{\r
-portBASE_TYPE xReturn;\r
-portBASE_TYPE xRunningPrivileged = prvRaisePrivilege();\r
-\r
- xReturn = xQueueGenericReset( pxQueue, xNewQueue );\r
- portRESET_PRIVILEGE( xRunningPrivileged );\r
- return xReturn;\r
-}\r
-/*-----------------------------------------------------------*/\r
-\r
-signed portBASE_TYPE MPU_xQueueGenericSend( xQueueHandle xQueue, const void * const pvItemToQueue, portTickType xTicksToWait, portBASE_TYPE xCopyPosition )\r
-{\r
-signed portBASE_TYPE xReturn;\r
-portBASE_TYPE xRunningPrivileged = prvRaisePrivilege();\r
-\r
- xReturn = xQueueGenericSend( xQueue, pvItemToQueue, xTicksToWait, xCopyPosition );\r
- portRESET_PRIVILEGE( xRunningPrivileged );\r
- return xReturn;\r
-}\r
-/*-----------------------------------------------------------*/\r
-\r
-unsigned portBASE_TYPE MPU_uxQueueMessagesWaiting( const xQueueHandle pxQueue )\r
-{\r
-portBASE_TYPE xRunningPrivileged = prvRaisePrivilege();\r
-unsigned portBASE_TYPE uxReturn;\r
-\r
- uxReturn = uxQueueMessagesWaiting( pxQueue );\r
- portRESET_PRIVILEGE( xRunningPrivileged );\r
- return uxReturn;\r
-}\r
-/*-----------------------------------------------------------*/\r
-\r
-signed portBASE_TYPE MPU_xQueueGenericReceive( xQueueHandle pxQueue, void * const pvBuffer, portTickType xTicksToWait, portBASE_TYPE xJustPeeking )\r
-{\r
-portBASE_TYPE xRunningPrivileged = prvRaisePrivilege();\r
-signed portBASE_TYPE xReturn;\r
-\r
- xReturn = xQueueGenericReceive( pxQueue, pvBuffer, xTicksToWait, xJustPeeking );\r
- portRESET_PRIVILEGE( xRunningPrivileged );\r
- return xReturn;\r
-}\r
-/*-----------------------------------------------------------*/\r
-\r
-signed portBASE_TYPE MPU_xQueuePeekFromISR( xQueueHandle pxQueue, void * const pvBuffer )\r
-{\r
-portBASE_TYPE xRunningPrivileged = prvRaisePrivilege();\r
-signed portBASE_TYPE xReturn;\r
-\r
- xReturn = xQueuePeekFromISR( pxQueue, pvBuffer );\r
- portRESET_PRIVILEGE( xRunningPrivileged );\r
- return xReturn;\r
-}\r
-/*-----------------------------------------------------------*/\r
+#if( configASSERT_DEFINED == 1 )\r
\r
-#if ( configUSE_MUTEXES == 1 )\r
- xQueueHandle MPU_xQueueCreateMutex( void )\r
+ void vPortValidateInterruptPriority( void )\r
{\r
- xQueueHandle xReturn;\r
- portBASE_TYPE xRunningPrivileged = prvRaisePrivilege();\r
+ uint32_t ulCurrentInterrupt;\r
+ uint8_t ucCurrentPriority;\r
\r
- xReturn = xQueueCreateMutex( queueQUEUE_TYPE_MUTEX );\r
- portRESET_PRIVILEGE( xRunningPrivileged );\r
- return xReturn;\r
- }\r
-#endif\r
-/*-----------------------------------------------------------*/\r
-\r
-#if configUSE_COUNTING_SEMAPHORES == 1\r
- xQueueHandle MPU_xQueueCreateCountingSemaphore( unsigned portBASE_TYPE uxCountValue, unsigned portBASE_TYPE uxInitialCount )\r
- {\r
- xQueueHandle xReturn;\r
- portBASE_TYPE xRunningPrivileged = prvRaisePrivilege();\r
-\r
- xReturn = xQueueCreateCountingSemaphore( uxCountValue, uxInitialCount );\r
- portRESET_PRIVILEGE( xRunningPrivileged );\r
- return xReturn;\r
- }\r
-#endif\r
-/*-----------------------------------------------------------*/\r
-\r
-#if ( configUSE_MUTEXES == 1 )\r
- portBASE_TYPE MPU_xQueueTakeMutexRecursive( xQueueHandle xMutex, portTickType xBlockTime )\r
- {\r
- portBASE_TYPE xReturn;\r
- portBASE_TYPE xRunningPrivileged = prvRaisePrivilege();\r
-\r
- xReturn = xQueueTakeMutexRecursive( xMutex, xBlockTime );\r
- portRESET_PRIVILEGE( xRunningPrivileged );\r
- return xReturn;\r
- }\r
-#endif\r
-/*-----------------------------------------------------------*/\r
-\r
-#if ( configUSE_MUTEXES == 1 )\r
- portBASE_TYPE MPU_xQueueGiveMutexRecursive( xQueueHandle xMutex )\r
- {\r
- portBASE_TYPE xReturn;\r
- portBASE_TYPE xRunningPrivileged = prvRaisePrivilege();\r
+ /* Obtain the number of the currently executing interrupt. */\r
+ __asm volatile( "mrs %0, ipsr" : "=r"( ulCurrentInterrupt ) :: "memory" );\r
\r
- xReturn = xQueueGiveMutexRecursive( xMutex );\r
- portRESET_PRIVILEGE( xRunningPrivileged );\r
- return xReturn;\r
- }\r
-#endif\r
-/*-----------------------------------------------------------*/\r
-\r
-#if ( configUSE_QUEUE_SETS == 1 )\r
- xQueueSetHandle MPU_xQueueCreateSet( unsigned portBASE_TYPE uxEventQueueLength )\r
- {\r
- xQueueSetHandle xReturn;\r
- portBASE_TYPE xRunningPrivileged = prvRaisePrivilege();\r
-\r
- xReturn = xQueueCreateSet( uxEventQueueLength );\r
- portRESET_PRIVILEGE( xRunningPrivileged );\r
- return xReturn;\r
- }\r
-#endif\r
-/*-----------------------------------------------------------*/\r
-\r
-#if ( configUSE_QUEUE_SETS == 1 )\r
- xQueueSetMemberHandle MPU_xQueueSelectFromSet( xQueueSetHandle xQueueSet, portTickType xBlockTimeTicks )\r
- {\r
- xQueueSetMemberHandle xReturn;\r
- portBASE_TYPE xRunningPrivileged = prvRaisePrivilege();\r
-\r
- xReturn = xQueueSelectFromSet( xQueueSet, xBlockTimeTicks );\r
- portRESET_PRIVILEGE( xRunningPrivileged );\r
- return xReturn;\r
- }\r
-#endif\r
-/*-----------------------------------------------------------*/\r
-\r
-#if ( configUSE_QUEUE_SETS == 1 )\r
- portBASE_TYPE MPU_xQueueAddToSet( xQueueSetMemberHandle xQueueOrSemaphore, xQueueSetHandle xQueueSet )\r
- {\r
- portBASE_TYPE xReturn;\r
- portBASE_TYPE xRunningPrivileged = prvRaisePrivilege();\r
-\r
- xReturn = xQueueAddToSet( xQueueOrSemaphore, xQueueSet );\r
- portRESET_PRIVILEGE( xRunningPrivileged );\r
- return xReturn;\r
- }\r
-#endif\r
-/*-----------------------------------------------------------*/\r
-\r
-#if ( configUSE_QUEUE_SETS == 1 )\r
- portBASE_TYPE MPU_xQueueRemoveFromSet( xQueueSetMemberHandle xQueueOrSemaphore, xQueueSetHandle xQueueSet )\r
- {\r
- portBASE_TYPE xReturn;\r
- portBASE_TYPE xRunningPrivileged = prvRaisePrivilege();\r
-\r
- xReturn = xQueueRemoveFromSet( xQueueOrSemaphore, xQueueSet );\r
- portRESET_PRIVILEGE( xRunningPrivileged );\r
- return xReturn;\r
- }\r
-#endif\r
-/*-----------------------------------------------------------*/\r
-\r
-#if configUSE_ALTERNATIVE_API == 1\r
- signed portBASE_TYPE MPU_xQueueAltGenericSend( xQueueHandle pxQueue, const void * const pvItemToQueue, portTickType xTicksToWait, portBASE_TYPE xCopyPosition )\r
- {\r
- signed portBASE_TYPE xReturn;\r
- portBASE_TYPE xRunningPrivileged = prvRaisePrivilege();\r
-\r
- xReturn = signed portBASE_TYPE xQueueAltGenericSend( pxQueue, pvItemToQueue, xTicksToWait, xCopyPosition );\r
- portRESET_PRIVILEGE( xRunningPrivileged );\r
- return xReturn;\r
- }\r
-#endif\r
-/*-----------------------------------------------------------*/\r
-\r
-#if configUSE_ALTERNATIVE_API == 1\r
- signed portBASE_TYPE MPU_xQueueAltGenericReceive( xQueueHandle pxQueue, void * const pvBuffer, portTickType xTicksToWait, portBASE_TYPE xJustPeeking )\r
- {\r
- signed portBASE_TYPE xReturn;\r
- portBASE_TYPE xRunningPrivileged = prvRaisePrivilege();\r
-\r
- xReturn = xQueueAltGenericReceive( pxQueue, pvBuffer, xTicksToWait, xJustPeeking );\r
- portRESET_PRIVILEGE( xRunningPrivileged );\r
- return xReturn;\r
- }\r
-#endif\r
-/*-----------------------------------------------------------*/\r
-\r
-#if configQUEUE_REGISTRY_SIZE > 0\r
- void MPU_vQueueAddToRegistry( xQueueHandle xQueue, signed char *pcName )\r
- {\r
- portBASE_TYPE xRunningPrivileged = prvRaisePrivilege();\r
+ /* Is the interrupt number a user defined interrupt? */\r
+ if( ulCurrentInterrupt >= portFIRST_USER_INTERRUPT_NUMBER )\r
+ {\r
+ /* Look up the interrupt's priority. */\r
+ ucCurrentPriority = pcInterruptPriorityRegisters[ ulCurrentInterrupt ];\r
+\r
+ /* The following assertion will fail if a service routine (ISR) for\r
+ * an interrupt that has been assigned a priority above\r
+ * configMAX_SYSCALL_INTERRUPT_PRIORITY calls an ISR safe FreeRTOS API\r
+ * function. ISR safe FreeRTOS API functions must *only* be called\r
+ * from interrupts that have been assigned a priority at or below\r
+ * configMAX_SYSCALL_INTERRUPT_PRIORITY.\r
+\r
+ * Numerically low interrupt priority numbers represent logically high\r
+ * interrupt priorities, therefore the priority of the interrupt must\r
+ * be set to a value equal to or numerically *higher* than\r
+ * configMAX_SYSCALL_INTERRUPT_PRIORITY.\r
+\r
+ * Interrupts that use the FreeRTOS API must not be left at their\r
+ * default priority of zero as that is the highest possible priority,\r
+ * which is guaranteed to be above configMAX_SYSCALL_INTERRUPT_PRIORITY,\r
+ * and therefore also guaranteed to be invalid.\r
+\r
+ * FreeRTOS maintains separate thread and ISR API functions to ensure\r
+ * interrupt entry is as fast and simple as possible.\r
+\r
+ * The following links provide detailed information:\r
+ * http://www.freertos.org/RTOS-Cortex-M3-M4.html\r
+ * http://www.freertos.org/FAQHelp.html */\r
+ configASSERT( ucCurrentPriority >= ucMaxSysCallPriority );\r
+ }\r
\r
- vQueueAddToRegistry( xQueue, pcName );\r
+ /* Priority grouping: The interrupt controller (NVIC) allows the bits\r
+ * that define each interrupt's priority to be split between bits that\r
+ * define the interrupt's pre-emption priority bits and bits that define\r
+ * the interrupt's sub-priority. For simplicity all bits must be defined\r
+ * to be pre-emption priority bits. The following assertion will fail if\r
+ * this is not the case (if some bits represent a sub-priority).\r
\r
- portRESET_PRIVILEGE( xRunningPrivileged );\r
+ * If the application only uses CMSIS libraries for interrupt\r
+ * configuration then the correct setting can be achieved on all Cortex-M\r
+ * devices by calling NVIC_SetPriorityGrouping( 0 ); before starting the\r
+ * scheduler. Note however that some vendor specific peripheral libraries\r
+ * assume a non-zero priority group setting, in which cases using a value\r
+ * of zero will result in unpredicable behaviour. */\r
+ configASSERT( ( portAIRCR_REG & portPRIORITY_GROUP_MASK ) <= ulMaxPRIGROUPValue );\r
}\r
-#endif\r
-/*-----------------------------------------------------------*/\r
-\r
-void MPU_vQueueDelete( xQueueHandle xQueue )\r
-{\r
-portBASE_TYPE xRunningPrivileged = prvRaisePrivilege();\r
-\r
- vQueueDelete( xQueue );\r
\r
- portRESET_PRIVILEGE( xRunningPrivileged );\r
-}\r
+#endif /* configASSERT_DEFINED */\r
/*-----------------------------------------------------------*/\r
-\r
-void *MPU_pvPortMalloc( size_t xSize )\r
-{\r
-void *pvReturn;\r
-portBASE_TYPE xRunningPrivileged = prvRaisePrivilege();\r
-\r
- pvReturn = pvPortMalloc( xSize );\r
-\r
- portRESET_PRIVILEGE( xRunningPrivileged );\r
-\r
- return pvReturn;\r
-}\r
-/*-----------------------------------------------------------*/\r
-\r
-void MPU_vPortFree( void *pv )\r
-{\r
-portBASE_TYPE xRunningPrivileged = prvRaisePrivilege();\r
-\r
- vPortFree( pv );\r
-\r
- portRESET_PRIVILEGE( xRunningPrivileged );\r
-}\r
-/*-----------------------------------------------------------*/\r
-\r
-void MPU_vPortInitialiseBlocks( void )\r
-{\r
-portBASE_TYPE xRunningPrivileged = prvRaisePrivilege();\r
-\r
- vPortInitialiseBlocks();\r
-\r
- portRESET_PRIVILEGE( xRunningPrivileged );\r
-}\r
-/*-----------------------------------------------------------*/\r
-\r
-size_t MPU_xPortGetFreeHeapSize( void )\r
-{\r
-size_t xReturn;\r
-portBASE_TYPE xRunningPrivileged = prvRaisePrivilege();\r
-\r
- xReturn = xPortGetFreeHeapSize();\r
-\r
- portRESET_PRIVILEGE( xRunningPrivileged );\r
-\r
- return xReturn;\r
-}\r
-\r
-/* Functions that the application writer wants to execute in privileged mode\r
-can be defined in application_defined_privileged_functions.h. The functions\r
-must take the same format as those above whereby the privilege state on exit\r
-equals the privilege state on entry. For example:\r
-\r
-void MPU_FunctionName( [parameters ] )\r
-{\r
-portBASE_TYPE xRunningPrivileged = prvRaisePrivilege();\r
-\r
- FunctionName( [parameters ] );\r
-\r
- portRESET_PRIVILEGE( xRunningPrivileged );\r
-}\r
-*/\r
-\r
-#if configINCLUDE_APPLICATION_DEFINED_PRIVILEGED_FUNCTIONS == 1\r
- #include "application_defined_privileged_functions.h"\r
-#endif\r
-\r
projects / freertos / blobdiff