/*\r
- FreeRTOS V7.5.0 - Copyright (C) 2013 Real Time Engineers Ltd.\r
+ FreeRTOS V7.6.0 - Copyright (C) 2013 Real Time Engineers Ltd.\r
+ All rights reserved\r
\r
VISIT http://www.FreeRTOS.org TO ENSURE YOU ARE USING THE LATEST VERSION.\r
\r
#define portNVIC_PENDSV_PRI ( ( ( unsigned long ) configKERNEL_INTERRUPT_PRIORITY ) << 16UL )\r
#define portNVIC_SYSTICK_PRI ( ( ( unsigned long ) configKERNEL_INTERRUPT_PRIORITY ) << 24UL )\r
\r
-/* Constants required to check the validity of an interrupt prority. */\r
+/* Constants required to check the validity of an interrupt priority. */\r
#define portFIRST_USER_INTERRUPT_NUMBER ( 16 )\r
#define portNVIC_IP_REGISTERS_OFFSET_16 ( 0xE000E3F0 )\r
#define portAIRCR_REG ( * ( ( volatile unsigned long * ) 0xE000ED0C ) )\r
+#define portMAX_8_BIT_VALUE ( ( unsigned char ) 0xff )\r
+#define portTOP_BIT_OF_BYTE ( ( unsigned char ) 0x80 )\r
+#define portMAX_PRIGROUP_BITS ( ( unsigned char ) 7 )\r
#define portPRIORITY_GROUP_MASK ( 0x07UL << 8UL )\r
+#define portPRIGROUP_SHIFT ( 8UL )\r
\r
/* Constants required to manipulate the VFP. */\r
#define portFPCCR ( ( volatile unsigned long * ) 0xe000ef34 ) /* Floating point context control register. */\r
calculations. */\r
#define portMISSED_COUNTS_FACTOR ( 45UL )\r
\r
+/* Let the user override the pre-loading of the initial LR with the address of\r
+prvTaskExitError() in case is messes up unwinding of the stack in the\r
+debugger. */\r
+#ifdef configTASK_RETURN_ADDRESS\r
+ #define portTASK_RETURN_ADDRESS configTASK_RETURN_ADDRESS\r
+#else\r
+ #define portTASK_RETURN_ADDRESS prvTaskExitError\r
+#endif\r
+\r
/* Each task maintains its own interrupt status in the critical nesting\r
variable. */\r
static unsigned portBASE_TYPE uxCriticalNesting = 0xaaaaaaaa;\r
*/\r
static void vPortEnableVFP( void ) __attribute__ (( naked ));\r
\r
+/*\r
+ * Used to catch tasks that attempt to return from their implementing function.\r
+ */\r
+static void prvTaskExitError( void );\r
+\r
/*-----------------------------------------------------------*/\r
\r
/*\r
#endif /* configUSE_TICKLESS_IDLE */\r
\r
/*\r
- * Used by the portASSERT_IF_INTERRUPT_PRIORITY_INVALID() macro to ensure \r
+ * Used by the portASSERT_IF_INTERRUPT_PRIORITY_INVALID() macro to ensure\r
* FreeRTOS API functions are not called from interrupts that have been assigned\r
* a priority above configMAX_SYSCALL_INTERRUPT_PRIORITY.\r
*/\r
#if ( configASSERT_DEFINED == 1 )\r
static unsigned char ucMaxSysCallPriority = 0;\r
+ static unsigned long ulMaxPRIGROUPValue = 0;\r
static const volatile unsigned char * const pcInterruptPriorityRegisters = ( const volatile unsigned char * const ) portNVIC_IP_REGISTERS_OFFSET_16;\r
#endif /* configASSERT_DEFINED */\r
\r
pxTopOfStack--;\r
*pxTopOfStack = ( portSTACK_TYPE ) pxCode; /* PC */\r
pxTopOfStack--;\r
- *pxTopOfStack = 0; /* LR */\r
+ *pxTopOfStack = ( portSTACK_TYPE ) portTASK_RETURN_ADDRESS; /* LR */\r
\r
/* Save code space by skipping register initialisation. */\r
pxTopOfStack -= 5; /* R12, R3, R2 and R1. */\r
}\r
/*-----------------------------------------------------------*/\r
\r
+static void prvTaskExitError( void )\r
+{\r
+ /* A function that implements a task must not exit or attempt to return to\r
+ its caller as there is nothing to return to. If a task wants to exit it\r
+ should instead call vTaskDelete( NULL ).\r
+\r
+ Artificially force an assert() to be triggered if configASSERT() is\r
+ defined, then stop here so application writers can catch the error. */\r
+ configASSERT( uxCriticalNesting == ~0UL );\r
+ portDISABLE_INTERRUPTS();\r
+ for( ;; );\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
void vPortSVCHandler( void )\r
{\r
__asm volatile (\r
{\r
volatile unsigned long ulOriginalPriority;\r
volatile char * const pcFirstUserPriorityRegister = ( volatile char * const ) ( portNVIC_IP_REGISTERS_OFFSET_16 + portFIRST_USER_INTERRUPT_NUMBER );\r
+ volatile unsigned char ucMaxPriorityValue;\r
\r
/* Determine the maximum priority from which ISR safe FreeRTOS API\r
functions can be called. ISR safe functions are those that end in\r
Save the interrupt priority value that is about to be clobbered. */\r
ulOriginalPriority = *pcFirstUserPriorityRegister;\r
\r
- /* Write the configMAX_SYSCALL_INTERRUPT_PRIORITY value to an interrupt\r
- priority register. */\r
- *pcFirstUserPriorityRegister = configMAX_SYSCALL_INTERRUPT_PRIORITY;\r
+ /* Determine the number of priority bits available. First write to all\r
+ possible bits. */\r
+ *pcFirstUserPriorityRegister = portMAX_8_BIT_VALUE;\r
+\r
+ /* Read the value back to see how many bits stuck. */\r
+ ucMaxPriorityValue = *pcFirstUserPriorityRegister;\r
\r
- /* Read back the written priority to obtain its value as seen by the\r
- hardware, which will only implement a subset of the priority bits. */\r
- ucMaxSysCallPriority = *pcFirstUserPriorityRegister;\r
+ /* Use the same mask on the maximum system call priority. */\r
+ ucMaxSysCallPriority = configMAX_SYSCALL_INTERRUPT_PRIORITY & ucMaxPriorityValue;\r
+\r
+ /* Calculate the maximum acceptable priority group value for the number\r
+ of bits read back. */\r
+ ulMaxPRIGROUPValue = portMAX_PRIGROUP_BITS;\r
+ while( ( ucMaxPriorityValue & portTOP_BIT_OF_BYTE ) == portTOP_BIT_OF_BYTE )\r
+ {\r
+ ulMaxPRIGROUPValue--;\r
+ ucMaxPriorityValue <<= ( unsigned char ) 0x01;\r
+ }\r
+\r
+ /* Shift the priority group value back to its position within the AIRCR\r
+ register. */\r
+ ulMaxPRIGROUPValue <<= portPRIGROUP_SHIFT;\r
+ ulMaxPRIGROUPValue &= portPRIORITY_GROUP_MASK;\r
\r
/* Restore the clobbered interrupt priority register to its original\r
value. */\r
/* Start the first task. */\r
prvPortStartFirstTask();\r
\r
+ /* Should never get here as the tasks will now be executing! Call the task\r
+ exit error function to prevent compiler warnings about a static function\r
+ not being called in the case that the application writer overrides this\r
+ functionality by defining configTASK_RETURN_ADDRESS. */\r
+ prvTaskExitError();\r
+\r
/* Should not get here! */\r
return 0;\r
}\r
(\r
" mrs r0, psp \n"\r
" \n"\r
- " ldr r3, pxCurrentTCBConst \n" /* Get the location of the current TCB. */\r
+ " ldr r3, pxCurrentTCBConst \n" /* Get the location of the current TCB. */\r
" ldr r2, [r3] \n"\r
" \n"\r
" tst r14, #0x10 \n" /* Is the task using the FPU context? If so, push high vfp registers. */\r
" \n"\r
" str r0, [r2] \n" /* Save the new top of stack into the first member of the TCB. */\r
" \n"\r
- " stmdb sp!, {r3, r14} \n"\r
+ " stmdb sp!, {r3} \n"\r
" mov r0, %0 \n"\r
" msr basepri, r0 \n"\r
" bl vTaskSwitchContext \n"\r
" mov r0, #0 \n"\r
" msr basepri, r0 \n"\r
- " ldmia sp!, {r3, r14} \n"\r
+ " ldmia sp!, {r3} \n"\r
" \n"\r
" ldr r1, [r3] \n" /* The first item in pxCurrentTCB is the task top of stack. */\r
" ldr r0, [r1] \n"\r
" vldmiaeq r0!, {s16-s31} \n"\r
" \n"\r
" msr psp, r0 \n"\r
+ " \n"\r
+ #ifdef WORKAROUND_PMU_CM001 /* XMC4000 specific errata workaround. */\r
+ #if WORKAROUND_PMU_CM001 == 1\r
+ " push { r14 } \n"\r
+ " pop { pc } \n"\r
+ #endif\r
+ #endif\r
+ " \n"\r
" bx r14 \n"\r
" \n"\r
" .align 2 \n"\r
to be unsuspended then abandon the low power entry. */\r
if( eTaskConfirmSleepModeStatus() == eAbortSleep )\r
{\r
+ /* Restart from whatever is left in the count register to complete\r
+ this tick period. */\r
+ portNVIC_SYSTICK_LOAD_REG = portNVIC_SYSTICK_CURRENT_VALUE_REG;\r
+\r
/* Restart SysTick. */\r
portNVIC_SYSTICK_CTRL_REG = portNVIC_SYSTICK_CLK_BIT | portNVIC_SYSTICK_INT_BIT | portNVIC_SYSTICK_ENABLE_BIT;\r
\r
+ /* Reset the reload register to the value required for normal tick\r
+ periods. */\r
+ portNVIC_SYSTICK_LOAD_REG = ulTimerCountsForOneTick - 1UL;\r
+\r
/* Re-enable interrupts - see comments above the cpsid instruction()\r
above. */\r
__asm volatile( "cpsie i" );\r
\r
if( ( portNVIC_SYSTICK_CTRL_REG & portNVIC_SYSTICK_COUNT_FLAG_BIT ) != 0 )\r
{\r
+ unsigned long ulCalculatedLoadValue;\r
+\r
/* The tick interrupt has already executed, and the SysTick\r
count reloaded with ulReloadValue. Reset the\r
portNVIC_SYSTICK_LOAD_REG with whatever remains of this tick\r
period. */\r
- portNVIC_SYSTICK_LOAD_REG = ( ulTimerCountsForOneTick - 1UL ) - ( ulReloadValue - portNVIC_SYSTICK_CURRENT_VALUE_REG );\r
+ ulCalculatedLoadValue = ( ulTimerCountsForOneTick - 1UL ) - ( ulReloadValue - portNVIC_SYSTICK_CURRENT_VALUE_REG );\r
+\r
+ /* Don't allow a tiny value, or values that have somehow\r
+ underflowed because the post sleep hook did something\r
+ that took too long. */\r
+ if( ( ulCalculatedLoadValue < ulStoppedTimerCompensation ) || ( ulCalculatedLoadValue > ulTimerCountsForOneTick ) )\r
+ {\r
+ ulCalculatedLoadValue = ( ulTimerCountsForOneTick - 1UL );\r
+ }\r
+\r
+ portNVIC_SYSTICK_LOAD_REG = ulCalculatedLoadValue;\r
\r
/* The tick interrupt handler will already have pended the tick\r
processing in the kernel. As the pending tick will be\r
\r
/* Restart SysTick so it runs from portNVIC_SYSTICK_LOAD_REG\r
again, then set portNVIC_SYSTICK_LOAD_REG back to its standard\r
- value. */\r
+ value. The critical section is used to ensure the tick interrupt\r
+ can only execute once in the case that the reload register is near\r
+ zero. */\r
portNVIC_SYSTICK_CURRENT_VALUE_REG = 0UL;\r
- portNVIC_SYSTICK_CTRL_REG = portNVIC_SYSTICK_CLK_BIT | portNVIC_SYSTICK_INT_BIT | portNVIC_SYSTICK_ENABLE_BIT;\r
-\r
- vTaskStepTick( ulCompleteTickPeriods );\r
-\r
- /* The counter must start by the time the reload value is reset. */\r
- configASSERT( portNVIC_SYSTICK_CURRENT_VALUE_REG );\r
- portNVIC_SYSTICK_LOAD_REG = ulTimerCountsForOneTick - 1UL;\r
+ portENTER_CRITICAL();\r
+ {\r
+ portNVIC_SYSTICK_CTRL_REG = portNVIC_SYSTICK_CLK_BIT | portNVIC_SYSTICK_INT_BIT | portNVIC_SYSTICK_ENABLE_BIT;\r
+ vTaskStepTick( ulCompleteTickPeriods );\r
+ portNVIC_SYSTICK_LOAD_REG = ulTimerCountsForOneTick - 1UL;\r
+ }\r
+ portEXIT_CRITICAL();\r
}\r
}\r
\r
/* Look up the interrupt's priority. */\r
ucCurrentPriority = pcInterruptPriorityRegisters[ ulCurrentInterrupt ];\r
\r
- /* The following assertion will fail if a service routine (ISR) for \r
+ /* The following assertion will fail if a service routine (ISR) for\r
an interrupt that has been assigned a priority above\r
configMAX_SYSCALL_INTERRUPT_PRIORITY calls an ISR safe FreeRTOS API\r
- function. ISR safe FreeRTOS API functions must *only* be called \r
+ function. ISR safe FreeRTOS API functions must *only* be called\r
from interrupts that have been assigned a priority at or below\r
configMAX_SYSCALL_INTERRUPT_PRIORITY.\r
- \r
+\r
Numerically low interrupt priority numbers represent logically high\r
- interrupt priorities, therefore the priority of the interrupt must \r
- be set to a value equal to or numerically *higher* than \r
+ interrupt priorities, therefore the priority of the interrupt must\r
+ be set to a value equal to or numerically *higher* than\r
configMAX_SYSCALL_INTERRUPT_PRIORITY.\r
- \r
+\r
Interrupts that use the FreeRTOS API must not be left at their\r
default priority of zero as that is the highest possible priority,\r
- which is guaranteed to be above configMAX_SYSCALL_INTERRUPT_PRIORITY, \r
- and therefore also guaranteed to be invalid. \r
- \r
- FreeRTOS maintains separate thread and ISR API functions to ensure \r
+ which is guaranteed to be above configMAX_SYSCALL_INTERRUPT_PRIORITY,\r
+ and therefore also guaranteed to be invalid.\r
+\r
+ FreeRTOS maintains separate thread and ISR API functions to ensure\r
interrupt entry is as fast and simple as possible.\r
- \r
+\r
The following links provide detailed information:\r
http://www.freertos.org/RTOS-Cortex-M3-M4.html\r
http://www.freertos.org/FAQHelp.html */\r
configASSERT( ucCurrentPriority >= ucMaxSysCallPriority );\r
}\r
\r
- /* Priority grouping: The interrupt controller (NVIC) allows the bits \r
- that define each interrupt's priority to be split between bits that \r
+ /* Priority grouping: The interrupt controller (NVIC) allows the bits\r
+ that define each interrupt's priority to be split between bits that\r
define the interrupt's pre-emption priority bits and bits that define\r
- the interrupt's sub-priority. For simplicity all bits must be defined \r
+ the interrupt's sub-priority. For simplicity all bits must be defined\r
to be pre-emption priority bits. The following assertion will fail if\r
- this is not the case (if some bits represent a sub-priority). \r
- \r
- If CMSIS libraries are being used then the correct setting can be \r
- achieved by calling NVIC_SetPriorityGrouping( 0 ); before starting the \r
- scheduler. */\r
- configASSERT( ( portAIRCR_REG & portPRIORITY_GROUP_MASK ) == 0 );\r
+ this is not the case (if some bits represent a sub-priority).\r
+\r
+ If the application only uses CMSIS libraries for interrupt\r
+ configuration then the correct setting can be achieved on all Cortex-M\r
+ devices by calling NVIC_SetPriorityGrouping( 0 ); before starting the\r
+ scheduler. Note however that some vendor specific peripheral libraries\r
+ assume a non-zero priority group setting, in which cases using a value\r
+ of zero will result in unpredicable behaviour. */\r
+ configASSERT( ( portAIRCR_REG & portPRIORITY_GROUP_MASK ) <= ulMaxPRIGROUPValue );\r
}\r
\r
#endif /* configASSERT_DEFINED */\r
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