/*\r
- FreeRTOS V7.5.0 - Copyright (C) 2013 Real Time Engineers Ltd.\r
-\r
- VISIT http://www.FreeRTOS.org TO ENSURE YOU ARE USING THE LATEST VERSION.\r
-\r
- ***************************************************************************\r
- * *\r
- * FreeRTOS provides completely free yet professionally developed, *\r
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- * *\r
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- * project by purchasing a FreeRTOS tutorial book, reference *\r
- * manual, or both from: http://www.FreeRTOS.org/Documentation *\r
- * *\r
- * Thank you! *\r
- * *\r
- ***************************************************************************\r
-\r
- This file is part of the FreeRTOS distribution.\r
-\r
- FreeRTOS is free software; you can redistribute it and/or modify it under\r
- the terms of the GNU General Public License (version 2) as published by the\r
- Free Software Foundation >>!AND MODIFIED BY!<< the FreeRTOS exception.\r
-\r
- >>! NOTE: The modification to the GPL is included to allow you to distribute\r
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- >>! kernel.\r
-\r
- FreeRTOS is distributed in the hope that it will be useful, but WITHOUT ANY\r
- WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS\r
- FOR A PARTICULAR PURPOSE. Full license text is available from the following\r
- link: http://www.freertos.org/a00114.html\r
-\r
- 1 tab == 4 spaces!\r
-\r
- ***************************************************************************\r
- * *\r
- * Having a problem? Start by reading the FAQ "My application does *\r
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- http://www.FreeRTOS.org - Documentation, books, training, latest versions,\r
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-\r
- http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products,\r
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- engineered and independently SIL3 certified version for use in safety and\r
- mission critical applications that require provable dependability.\r
-\r
- 1 tab == 4 spaces!\r
-*/\r
+ * FreeRTOS Kernel V10.3.0\r
+ * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved.\r
+ *\r
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of\r
+ * this software and associated documentation files (the "Software"), to deal in\r
+ * the Software without restriction, including without limitation the rights to\r
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+ * the Software, and to permit persons to whom the Software is furnished to do so,\r
+ * subject to the following conditions:\r
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+ * copies or substantial portions of the Software.\r
+ *\r
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR\r
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS\r
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+ * 1 tab == 4 spaces!\r
+ */\r
\r
/*-----------------------------------------------------------\r
* Implementation of functions defined in portable.h for the MicroBlaze port.\r
#include <xintc_i.h>\r
#include <xtmrctr.h>\r
\r
+#if( configSUPPORT_DYNAMIC_ALLOCATION == 0 )\r
+ #error configSUPPORT_DYNAMIC_ALLOCATION must be set to 1 to use this port.\r
+#endif\r
+\r
/* Tasks are started with interrupts enabled. */\r
-#define portINITIAL_MSR_STATE ( ( portSTACK_TYPE ) 0x02 )\r
+#define portINITIAL_MSR_STATE ( ( StackType_t ) 0x02 )\r
\r
/* Tasks are started with a critical section nesting of 0 - however prior\r
to the scheduler being commenced we don't want the critical nesting level\r
debugging. */\r
#define portISR_STACK_FILL_VALUE 0x55555555\r
\r
-/* Counts the nesting depth of calls to portENTER_CRITICAL(). Each task \r
+/* Counts the nesting depth of calls to portENTER_CRITICAL(). Each task\r
maintains it's own count, so this variable is saved as part of the task\r
context. */\r
-volatile unsigned portBASE_TYPE uxCriticalNesting = portINITIAL_NESTING_VALUE;\r
+volatile UBaseType_t uxCriticalNesting = portINITIAL_NESTING_VALUE;\r
\r
/* To limit the amount of stack required by each task, this port uses a\r
separate stack for interrupts. */\r
-unsigned long *pulISRStack;\r
+uint32_t *pulISRStack;\r
\r
/*-----------------------------------------------------------*/\r
\r
static void prvSetupTimerInterrupt( void );\r
/*-----------------------------------------------------------*/\r
\r
-/* \r
- * Initialise the stack of a task to look exactly as if a call to \r
+/*\r
+ * Initialise the stack of a task to look exactly as if a call to\r
* portSAVE_CONTEXT had been made.\r
- * \r
+ *\r
* See the header file portable.h.\r
*/\r
-portSTACK_TYPE *pxPortInitialiseStack( portSTACK_TYPE *pxTopOfStack, pdTASK_CODE pxCode, void *pvParameters )\r
+StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, TaskFunction_t pxCode, void *pvParameters )\r
{\r
extern void *_SDA2_BASE_, *_SDA_BASE_;\r
-const unsigned long ulR2 = ( unsigned long ) &_SDA2_BASE_;\r
-const unsigned long ulR13 = ( unsigned long ) &_SDA_BASE_;\r
+const uint32_t ulR2 = ( uint32_t ) &_SDA2_BASE_;\r
+const uint32_t ulR13 = ( uint32_t ) &_SDA_BASE_;\r
\r
- /* Place a few bytes of known values on the bottom of the stack. \r
+ /* Place a few bytes of known values on the bottom of the stack.\r
This is essential for the Microblaze port and these lines must\r
- not be omitted. The parameter value will overwrite the \r
+ not be omitted. The parameter value will overwrite the\r
0x22222222 value during the function prologue. */\r
- *pxTopOfStack = ( portSTACK_TYPE ) 0x11111111;\r
+ *pxTopOfStack = ( StackType_t ) 0x11111111;\r
pxTopOfStack--;\r
- *pxTopOfStack = ( portSTACK_TYPE ) 0x22222222;\r
+ *pxTopOfStack = ( StackType_t ) 0x22222222;\r
+ pxTopOfStack--;\r
+ *pxTopOfStack = ( StackType_t ) 0x33333333;\r
pxTopOfStack--;\r
- *pxTopOfStack = ( portSTACK_TYPE ) 0x33333333;\r
- pxTopOfStack--; \r
\r
/* First stack an initial value for the critical section nesting. This\r
is initialised to zero as tasks are started with interrupts enabled. */\r
- *pxTopOfStack = ( portSTACK_TYPE ) 0x00; /* R0. */\r
+ *pxTopOfStack = ( StackType_t ) 0x00; /* R0. */\r
\r
/* Place an initial value for all the general purpose registers. */\r
pxTopOfStack--;\r
- *pxTopOfStack = ( portSTACK_TYPE ) ulR2; /* R2 - small data area. */\r
+ *pxTopOfStack = ( StackType_t ) ulR2; /* R2 - small data area. */\r
pxTopOfStack--;\r
- *pxTopOfStack = ( portSTACK_TYPE ) 0x03; /* R3. */\r
+ *pxTopOfStack = ( StackType_t ) 0x03; /* R3. */\r
pxTopOfStack--;\r
- *pxTopOfStack = ( portSTACK_TYPE ) 0x04; /* R4. */\r
+ *pxTopOfStack = ( StackType_t ) 0x04; /* R4. */\r
pxTopOfStack--;\r
- *pxTopOfStack = ( portSTACK_TYPE ) pvParameters;/* R5 contains the function call parameters. */\r
+ *pxTopOfStack = ( StackType_t ) pvParameters;/* R5 contains the function call parameters. */\r
pxTopOfStack--;\r
- *pxTopOfStack = ( portSTACK_TYPE ) 0x06; /* R6. */\r
+ *pxTopOfStack = ( StackType_t ) 0x06; /* R6. */\r
pxTopOfStack--;\r
- *pxTopOfStack = ( portSTACK_TYPE ) 0x07; /* R7. */\r
+ *pxTopOfStack = ( StackType_t ) 0x07; /* R7. */\r
pxTopOfStack--;\r
- *pxTopOfStack = ( portSTACK_TYPE ) 0x08; /* R8. */\r
+ *pxTopOfStack = ( StackType_t ) 0x08; /* R8. */\r
pxTopOfStack--;\r
- *pxTopOfStack = ( portSTACK_TYPE ) 0x09; /* R9. */\r
+ *pxTopOfStack = ( StackType_t ) 0x09; /* R9. */\r
pxTopOfStack--;\r
- *pxTopOfStack = ( portSTACK_TYPE ) 0x0a; /* R10. */\r
+ *pxTopOfStack = ( StackType_t ) 0x0a; /* R10. */\r
pxTopOfStack--;\r
- *pxTopOfStack = ( portSTACK_TYPE ) 0x0b; /* R11. */\r
+ *pxTopOfStack = ( StackType_t ) 0x0b; /* R11. */\r
pxTopOfStack--;\r
- *pxTopOfStack = ( portSTACK_TYPE ) 0x0c; /* R12. */\r
+ *pxTopOfStack = ( StackType_t ) 0x0c; /* R12. */\r
pxTopOfStack--;\r
- *pxTopOfStack = ( portSTACK_TYPE ) ulR13; /* R13 - small data read write area. */\r
+ *pxTopOfStack = ( StackType_t ) ulR13; /* R13 - small data read write area. */\r
pxTopOfStack--;\r
- *pxTopOfStack = ( portSTACK_TYPE ) pxCode; /* R14. */\r
+ *pxTopOfStack = ( StackType_t ) pxCode; /* R14. */\r
pxTopOfStack--;\r
- *pxTopOfStack = ( portSTACK_TYPE ) 0x0f; /* R15. */\r
+ *pxTopOfStack = ( StackType_t ) 0x0f; /* R15. */\r
pxTopOfStack--;\r
- *pxTopOfStack = ( portSTACK_TYPE ) 0x10; /* R16. */\r
+ *pxTopOfStack = ( StackType_t ) 0x10; /* R16. */\r
pxTopOfStack--;\r
- *pxTopOfStack = ( portSTACK_TYPE ) 0x11; /* R17. */\r
+ *pxTopOfStack = ( StackType_t ) 0x11; /* R17. */\r
pxTopOfStack--;\r
- *pxTopOfStack = ( portSTACK_TYPE ) 0x12; /* R18. */\r
+ *pxTopOfStack = ( StackType_t ) 0x12; /* R18. */\r
pxTopOfStack--;\r
- *pxTopOfStack = ( portSTACK_TYPE ) 0x13; /* R19. */\r
+ *pxTopOfStack = ( StackType_t ) 0x13; /* R19. */\r
pxTopOfStack--;\r
- *pxTopOfStack = ( portSTACK_TYPE ) 0x14; /* R20. */\r
+ *pxTopOfStack = ( StackType_t ) 0x14; /* R20. */\r
pxTopOfStack--;\r
- *pxTopOfStack = ( portSTACK_TYPE ) 0x15; /* R21. */\r
+ *pxTopOfStack = ( StackType_t ) 0x15; /* R21. */\r
pxTopOfStack--;\r
- *pxTopOfStack = ( portSTACK_TYPE ) 0x16; /* R22. */\r
+ *pxTopOfStack = ( StackType_t ) 0x16; /* R22. */\r
pxTopOfStack--;\r
- *pxTopOfStack = ( portSTACK_TYPE ) 0x17; /* R23. */\r
+ *pxTopOfStack = ( StackType_t ) 0x17; /* R23. */\r
pxTopOfStack--;\r
- *pxTopOfStack = ( portSTACK_TYPE ) 0x18; /* R24. */\r
+ *pxTopOfStack = ( StackType_t ) 0x18; /* R24. */\r
pxTopOfStack--;\r
- *pxTopOfStack = ( portSTACK_TYPE ) 0x19; /* R25. */\r
+ *pxTopOfStack = ( StackType_t ) 0x19; /* R25. */\r
pxTopOfStack--;\r
- *pxTopOfStack = ( portSTACK_TYPE ) 0x1a; /* R26. */\r
+ *pxTopOfStack = ( StackType_t ) 0x1a; /* R26. */\r
pxTopOfStack--;\r
- *pxTopOfStack = ( portSTACK_TYPE ) 0x1b; /* R27. */\r
+ *pxTopOfStack = ( StackType_t ) 0x1b; /* R27. */\r
pxTopOfStack--;\r
- *pxTopOfStack = ( portSTACK_TYPE ) 0x1c; /* R28. */\r
+ *pxTopOfStack = ( StackType_t ) 0x1c; /* R28. */\r
pxTopOfStack--;\r
- *pxTopOfStack = ( portSTACK_TYPE ) 0x1d; /* R29. */\r
+ *pxTopOfStack = ( StackType_t ) 0x1d; /* R29. */\r
pxTopOfStack--;\r
- *pxTopOfStack = ( portSTACK_TYPE ) 0x1e; /* R30. */\r
+ *pxTopOfStack = ( StackType_t ) 0x1e; /* R30. */\r
pxTopOfStack--;\r
\r
/* The MSR is stacked between R30 and R31. */\r
*pxTopOfStack = portINITIAL_MSR_STATE;\r
pxTopOfStack--;\r
\r
- *pxTopOfStack = ( portSTACK_TYPE ) 0x1f; /* R31. */\r
+ *pxTopOfStack = ( StackType_t ) 0x1f; /* R31. */\r
pxTopOfStack--;\r
\r
/* Return a pointer to the top of the stack we have generated so this can\r
}\r
/*-----------------------------------------------------------*/\r
\r
-portBASE_TYPE xPortStartScheduler( void )\r
+BaseType_t xPortStartScheduler( void )\r
{\r
extern void ( __FreeRTOS_interrupt_Handler )( void );\r
extern void ( vStartFirstTask )( void );\r
prvSetupTimerInterrupt();\r
\r
/* Allocate the stack to be used by the interrupt handler. */\r
- pulISRStack = ( unsigned long * ) pvPortMalloc( configMINIMAL_STACK_SIZE * sizeof( portSTACK_TYPE ) );\r
+ pulISRStack = ( uint32_t * ) pvPortMalloc( configMINIMAL_STACK_SIZE * sizeof( StackType_t ) );\r
\r
/* Restore the context of the first task that is going to run. */\r
if( pulISRStack != NULL )\r
{\r
/* Fill the ISR stack with a known value to facilitate debugging. */\r
- memset( pulISRStack, portISR_STACK_FILL_VALUE, configMINIMAL_STACK_SIZE * sizeof( portSTACK_TYPE ) );\r
+ memset( pulISRStack, portISR_STACK_FILL_VALUE, configMINIMAL_STACK_SIZE * sizeof( StackType_t ) );\r
pulISRStack += ( configMINIMAL_STACK_SIZE - 1 );\r
\r
/* Kick off the first task. */\r
/*-----------------------------------------------------------*/\r
\r
/*\r
- * Manual context switch called by portYIELD or taskYIELD. \r
+ * Manual context switch called by portYIELD or taskYIELD.\r
*/\r
void vPortYield( void )\r
{\r
/*-----------------------------------------------------------*/\r
\r
/*\r
- * Hardware initialisation to generate the RTOS tick. \r
+ * Hardware initialisation to generate the RTOS tick.\r
*/\r
static void prvSetupTimerInterrupt( void )\r
{\r
XTmrCtr xTimer;\r
-const unsigned long ulCounterValue = configCPU_CLOCK_HZ / configTICK_RATE_HZ;\r
-unsigned portBASE_TYPE uxMask;\r
+const uint32_t ulCounterValue = configCPU_CLOCK_HZ / configTICK_RATE_HZ;\r
+UBaseType_t uxMask;\r
\r
/* The OPB timer1 is used to generate the tick. Use the provided library\r
functions to enable the timer and set the tick frequency. */\r
XTmrCtr_mSetLoadReg( XPAR_OPB_TIMER_1_BASEADDR, portCOUNTER_0, ulCounterValue );\r
XTmrCtr_mSetControlStatusReg( XPAR_OPB_TIMER_1_BASEADDR, portCOUNTER_0, XTC_CSR_LOAD_MASK | XTC_CSR_INT_OCCURED_MASK );\r
\r
- /* Set the timer interrupt enable bit while maintaining the other bit \r
+ /* Set the timer interrupt enable bit while maintaining the other bit\r
states. */\r
uxMask = XIntc_In32( ( XPAR_OPB_INTC_0_BASEADDR + XIN_IER_OFFSET ) );\r
uxMask |= XPAR_OPB_TIMER_1_INTERRUPT_MASK;\r
- XIntc_Out32( ( XPAR_OPB_INTC_0_BASEADDR + XIN_IER_OFFSET ), ( uxMask ) ); \r
- \r
+ XIntc_Out32( ( XPAR_OPB_INTC_0_BASEADDR + XIN_IER_OFFSET ), ( uxMask ) );\r
+\r
XTmrCtr_Start( &xTimer, XPAR_OPB_TIMER_1_DEVICE_ID );\r
XTmrCtr_mSetControlStatusReg(XPAR_OPB_TIMER_1_BASEADDR, portCOUNTER_0, XTC_CSR_ENABLE_TMR_MASK | XTC_CSR_ENABLE_INT_MASK | XTC_CSR_AUTO_RELOAD_MASK | XTC_CSR_DOWN_COUNT_MASK | XTC_CSR_INT_OCCURED_MASK );\r
XIntc_mAckIntr( XPAR_INTC_SINGLE_BASEADDR, 1 );\r
/*\r
* The interrupt handler placed in the interrupt vector when the scheduler is\r
* started. The task context has already been saved when this is called.\r
- * This handler determines the interrupt source and calls the relevant \r
+ * This handler determines the interrupt source and calls the relevant\r
* peripheral handler.\r
*/\r
void vTaskISRHandler( void )\r
{\r
-static unsigned long ulPending; \r
+static uint32_t ulPending;\r
\r
/* Which interrupts are pending? */\r
ulPending = XIntc_In32( ( XPAR_INTC_SINGLE_BASEADDR + XIN_IVR_OFFSET ) );\r
{\r
static XIntc_VectorTableEntry *pxTablePtr;\r
static XIntc_Config *pxConfig;\r
- static unsigned long ulInterruptMask;\r
+ static uint32_t ulInterruptMask;\r
\r
- ulInterruptMask = ( unsigned long ) 1 << ulPending;\r
+ ulInterruptMask = ( uint32_t ) 1 << ulPending;\r
\r
/* Get the configuration data using the device ID */\r
- pxConfig = &XIntc_ConfigTable[ ( unsigned long ) XPAR_INTC_SINGLE_DEVICE_ID ];\r
+ pxConfig = &XIntc_ConfigTable[ ( uint32_t ) XPAR_INTC_SINGLE_DEVICE_ID ];\r
\r
pxTablePtr = &( pxConfig->HandlerTable[ ulPending ] );\r
if( pxConfig->AckBeforeService & ( ulInterruptMask ) )\r
}\r
/*-----------------------------------------------------------*/\r
\r
-/* \r
+/*\r
* Handler for the timer interrupt.\r
*/\r
void vTickISR( void *pvBaseAddress )\r
{\r
-unsigned long ulCSR;\r
+uint32_t ulCSR;\r
\r
/* Increment the RTOS tick - this might cause a task to unblock. */\r
if( xTaskIncrementTick() != pdFALSE )\r
}\r
\r
/* Clear the timer interrupt */\r
- ulCSR = XTmrCtr_mGetControlStatusReg(XPAR_OPB_TIMER_1_BASEADDR, 0); \r
+ ulCSR = XTmrCtr_mGetControlStatusReg(XPAR_OPB_TIMER_1_BASEADDR, 0);\r
XTmrCtr_mSetControlStatusReg( XPAR_OPB_TIMER_1_BASEADDR, portCOUNTER_0, ulCSR );\r
}\r
/*-----------------------------------------------------------*/\r
projects / freertos / blobdiff