/*\r
- FreeRTOS V7.3.0 - Copyright (C) 2012 Real Time Engineers Ltd.\r
-\r
- FEATURES AND PORTS ARE ADDED TO FREERTOS ALL THE TIME. PLEASE VISIT \r
- http://www.FreeRTOS.org TO ENSURE YOU ARE USING THE LATEST VERSION.\r
-\r
- ***************************************************************************\r
- * *\r
- * FreeRTOS tutorial books are available in pdf and paperback. *\r
- * Complete, revised, and edited pdf reference manuals are also *\r
- * available. *\r
- * *\r
- * Purchasing FreeRTOS documentation will not only help you, by *\r
- * ensuring you get running as quickly as possible and with an *\r
- * in-depth knowledge of how to use FreeRTOS, it will also help *\r
- * the FreeRTOS project to continue with its mission of providing *\r
- * professional grade, cross platform, de facto standard solutions *\r
- * for microcontrollers - completely free of charge! *\r
- * *\r
- * >>> See http://www.FreeRTOS.org/Documentation for details. <<< *\r
- * *\r
- * Thank you for using FreeRTOS, and thank you for your support! *\r
- * *\r
- ***************************************************************************\r
+ FreeRTOS V8.2.1 - Copyright (C) 2015 Real Time Engineers Ltd.\r
+ All rights reserved\r
\r
+ VISIT http://www.FreeRTOS.org TO ENSURE YOU ARE USING THE LATEST VERSION.\r
\r
This file is part of the FreeRTOS distribution.\r
\r
FreeRTOS is free software; you can redistribute it and/or modify it under\r
the terms of the GNU General Public License (version 2) as published by the\r
- Free Software Foundation AND MODIFIED BY the FreeRTOS exception.\r
- >>>NOTE<<< The modification to the GPL is included to allow you to\r
- distribute a combined work that includes FreeRTOS without being obliged to\r
- provide the source code for proprietary components outside of the FreeRTOS\r
- kernel. FreeRTOS is distributed in the hope that it will be useful, but\r
- WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY\r
- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for\r
- more details. You should have received a copy of the GNU General Public\r
- License and the FreeRTOS license exception along with FreeRTOS; if not it\r
- can be viewed here: http://www.freertos.org/a00114.html and also obtained\r
- by writing to Richard Barry, contact details for whom are available on the\r
- FreeRTOS WEB site.\r
+ Free Software Foundation >>!AND MODIFIED BY!<< the FreeRTOS exception.\r
+\r
+ ***************************************************************************\r
+ >>! NOTE: The modification to the GPL is included to allow you to !<<\r
+ >>! distribute a combined work that includes FreeRTOS without being !<<\r
+ >>! obliged to provide the source code for proprietary components !<<\r
+ >>! outside of the FreeRTOS kernel. !<<\r
+ ***************************************************************************\r
+\r
+ FreeRTOS is distributed in the hope that it will be useful, but WITHOUT ANY\r
+ WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS\r
+ FOR A PARTICULAR PURPOSE. Full license text is available on the following\r
+ link: http://www.freertos.org/a00114.html\r
\r
- 1 tab == 4 spaces!\r
- \r
***************************************************************************\r
* *\r
- * Having a problem? Start by reading the FAQ "My application does *\r
- * not run, what could be wrong?" *\r
+ * FreeRTOS provides completely free yet professionally developed, *\r
+ * robust, strictly quality controlled, supported, and cross *\r
+ * platform software that is more than just the market leader, it *\r
+ * is the industry's de facto standard. *\r
* *\r
- * http://www.FreeRTOS.org/FAQHelp.html *\r
+ * Help yourself get started quickly while simultaneously helping *\r
+ * to support the FreeRTOS project by purchasing a FreeRTOS *\r
+ * tutorial book, reference manual, or both: *\r
+ * http://www.FreeRTOS.org/Documentation *\r
* *\r
***************************************************************************\r
\r
- \r
- http://www.FreeRTOS.org - Documentation, training, latest versions, license \r
- and contact details. \r
- \r
+ http://www.FreeRTOS.org/FAQHelp.html - Having a problem? Start by reading\r
+ the FAQ page "My application does not run, what could be wrong?". Have you\r
+ defined configASSERT()?\r
+\r
+ http://www.FreeRTOS.org/support - In return for receiving this top quality\r
+ embedded software for free we request you assist our global community by\r
+ participating in the support forum.\r
+\r
+ http://www.FreeRTOS.org/training - Investing in training allows your team to\r
+ be as productive as possible as early as possible. Now you can receive\r
+ FreeRTOS training directly from Richard Barry, CEO of Real Time Engineers\r
+ Ltd, and the world's leading authority on the world's leading RTOS.\r
+\r
http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products,\r
- including FreeRTOS+Trace - an indispensable productivity tool.\r
+ including FreeRTOS+Trace - an indispensable productivity tool, a DOS\r
+ compatible FAT file system, and our tiny thread aware UDP/IP stack.\r
+\r
+ http://www.FreeRTOS.org/labs - Where new FreeRTOS products go to incubate.\r
+ Come and try FreeRTOS+TCP, our new open source TCP/IP stack for FreeRTOS.\r
+\r
+ http://www.OpenRTOS.com - Real Time Engineers ltd. license FreeRTOS to High\r
+ Integrity Systems ltd. to sell under the OpenRTOS brand. Low cost OpenRTOS\r
+ licenses offer ticketed support, indemnification and commercial middleware.\r
+\r
+ http://www.SafeRTOS.com - High Integrity Systems also provide a safety\r
+ engineered and independently SIL3 certified version for use in safety and\r
+ mission critical applications that require provable dependability.\r
\r
- Real Time Engineers ltd license FreeRTOS to High Integrity Systems, who sell \r
- the code with commercial support, indemnification, and middleware, under \r
- the OpenRTOS brand: http://www.OpenRTOS.com. High Integrity Systems also\r
- provide a safety engineered and independently SIL3 certified version under \r
- the SafeRTOS brand: http://www.SafeRTOS.com.\r
+ 1 tab == 4 spaces!\r
*/\r
\r
/*-----------------------------------------------------------\r
#include <xtmrctr.h>\r
\r
/* Tasks are started with interrupts enabled. */\r
-#define portINITIAL_MSR_STATE ( ( portSTACK_TYPE ) 0x02 )\r
+#define portINITIAL_MSR_STATE ( ( StackType_t ) 0x02 )\r
\r
/* Tasks are started with a critical section nesting of 0 - however prior\r
to the scheduler being commenced we don't want the critical nesting level\r
/* Counts the nesting depth of calls to portENTER_CRITICAL(). Each task \r
maintains it's own count, so this variable is saved as part of the task\r
context. */\r
-volatile unsigned portBASE_TYPE uxCriticalNesting = portINITIAL_NESTING_VALUE;\r
+volatile UBaseType_t uxCriticalNesting = portINITIAL_NESTING_VALUE;\r
\r
/* To limit the amount of stack required by each task, this port uses a\r
separate stack for interrupts. */\r
-unsigned long *pulISRStack;\r
+uint32_t *pulISRStack;\r
\r
/*-----------------------------------------------------------*/\r
\r
* \r
* See the header file portable.h.\r
*/\r
-portSTACK_TYPE *pxPortInitialiseStack( portSTACK_TYPE *pxTopOfStack, pdTASK_CODE pxCode, void *pvParameters )\r
+StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, TaskFunction_t pxCode, void *pvParameters )\r
{\r
extern void *_SDA2_BASE_, *_SDA_BASE_;\r
-const unsigned long ulR2 = ( unsigned long ) &_SDA2_BASE_;\r
-const unsigned long ulR13 = ( unsigned long ) &_SDA_BASE_;\r
+const uint32_t ulR2 = ( uint32_t ) &_SDA2_BASE_;\r
+const uint32_t ulR13 = ( uint32_t ) &_SDA_BASE_;\r
\r
/* Place a few bytes of known values on the bottom of the stack. \r
This is essential for the Microblaze port and these lines must\r
not be omitted. The parameter value will overwrite the \r
0x22222222 value during the function prologue. */\r
- *pxTopOfStack = ( portSTACK_TYPE ) 0x11111111;\r
+ *pxTopOfStack = ( StackType_t ) 0x11111111;\r
pxTopOfStack--;\r
- *pxTopOfStack = ( portSTACK_TYPE ) 0x22222222;\r
+ *pxTopOfStack = ( StackType_t ) 0x22222222;\r
pxTopOfStack--;\r
- *pxTopOfStack = ( portSTACK_TYPE ) 0x33333333;\r
+ *pxTopOfStack = ( StackType_t ) 0x33333333;\r
pxTopOfStack--; \r
\r
/* First stack an initial value for the critical section nesting. This\r
is initialised to zero as tasks are started with interrupts enabled. */\r
- *pxTopOfStack = ( portSTACK_TYPE ) 0x00; /* R0. */\r
+ *pxTopOfStack = ( StackType_t ) 0x00; /* R0. */\r
\r
/* Place an initial value for all the general purpose registers. */\r
pxTopOfStack--;\r
- *pxTopOfStack = ( portSTACK_TYPE ) ulR2; /* R2 - small data area. */\r
+ *pxTopOfStack = ( StackType_t ) ulR2; /* R2 - small data area. */\r
pxTopOfStack--;\r
- *pxTopOfStack = ( portSTACK_TYPE ) 0x03; /* R3. */\r
+ *pxTopOfStack = ( StackType_t ) 0x03; /* R3. */\r
pxTopOfStack--;\r
- *pxTopOfStack = ( portSTACK_TYPE ) 0x04; /* R4. */\r
+ *pxTopOfStack = ( StackType_t ) 0x04; /* R4. */\r
pxTopOfStack--;\r
- *pxTopOfStack = ( portSTACK_TYPE ) pvParameters;/* R5 contains the function call parameters. */\r
+ *pxTopOfStack = ( StackType_t ) pvParameters;/* R5 contains the function call parameters. */\r
pxTopOfStack--;\r
- *pxTopOfStack = ( portSTACK_TYPE ) 0x06; /* R6. */\r
+ *pxTopOfStack = ( StackType_t ) 0x06; /* R6. */\r
pxTopOfStack--;\r
- *pxTopOfStack = ( portSTACK_TYPE ) 0x07; /* R7. */\r
+ *pxTopOfStack = ( StackType_t ) 0x07; /* R7. */\r
pxTopOfStack--;\r
- *pxTopOfStack = ( portSTACK_TYPE ) 0x08; /* R8. */\r
+ *pxTopOfStack = ( StackType_t ) 0x08; /* R8. */\r
pxTopOfStack--;\r
- *pxTopOfStack = ( portSTACK_TYPE ) 0x09; /* R9. */\r
+ *pxTopOfStack = ( StackType_t ) 0x09; /* R9. */\r
pxTopOfStack--;\r
- *pxTopOfStack = ( portSTACK_TYPE ) 0x0a; /* R10. */\r
+ *pxTopOfStack = ( StackType_t ) 0x0a; /* R10. */\r
pxTopOfStack--;\r
- *pxTopOfStack = ( portSTACK_TYPE ) 0x0b; /* R11. */\r
+ *pxTopOfStack = ( StackType_t ) 0x0b; /* R11. */\r
pxTopOfStack--;\r
- *pxTopOfStack = ( portSTACK_TYPE ) 0x0c; /* R12. */\r
+ *pxTopOfStack = ( StackType_t ) 0x0c; /* R12. */\r
pxTopOfStack--;\r
- *pxTopOfStack = ( portSTACK_TYPE ) ulR13; /* R13 - small data read write area. */\r
+ *pxTopOfStack = ( StackType_t ) ulR13; /* R13 - small data read write area. */\r
pxTopOfStack--;\r
- *pxTopOfStack = ( portSTACK_TYPE ) pxCode; /* R14. */\r
+ *pxTopOfStack = ( StackType_t ) pxCode; /* R14. */\r
pxTopOfStack--;\r
- *pxTopOfStack = ( portSTACK_TYPE ) 0x0f; /* R15. */\r
+ *pxTopOfStack = ( StackType_t ) 0x0f; /* R15. */\r
pxTopOfStack--;\r
- *pxTopOfStack = ( portSTACK_TYPE ) 0x10; /* R16. */\r
+ *pxTopOfStack = ( StackType_t ) 0x10; /* R16. */\r
pxTopOfStack--;\r
- *pxTopOfStack = ( portSTACK_TYPE ) 0x11; /* R17. */\r
+ *pxTopOfStack = ( StackType_t ) 0x11; /* R17. */\r
pxTopOfStack--;\r
- *pxTopOfStack = ( portSTACK_TYPE ) 0x12; /* R18. */\r
+ *pxTopOfStack = ( StackType_t ) 0x12; /* R18. */\r
pxTopOfStack--;\r
- *pxTopOfStack = ( portSTACK_TYPE ) 0x13; /* R19. */\r
+ *pxTopOfStack = ( StackType_t ) 0x13; /* R19. */\r
pxTopOfStack--;\r
- *pxTopOfStack = ( portSTACK_TYPE ) 0x14; /* R20. */\r
+ *pxTopOfStack = ( StackType_t ) 0x14; /* R20. */\r
pxTopOfStack--;\r
- *pxTopOfStack = ( portSTACK_TYPE ) 0x15; /* R21. */\r
+ *pxTopOfStack = ( StackType_t ) 0x15; /* R21. */\r
pxTopOfStack--;\r
- *pxTopOfStack = ( portSTACK_TYPE ) 0x16; /* R22. */\r
+ *pxTopOfStack = ( StackType_t ) 0x16; /* R22. */\r
pxTopOfStack--;\r
- *pxTopOfStack = ( portSTACK_TYPE ) 0x17; /* R23. */\r
+ *pxTopOfStack = ( StackType_t ) 0x17; /* R23. */\r
pxTopOfStack--;\r
- *pxTopOfStack = ( portSTACK_TYPE ) 0x18; /* R24. */\r
+ *pxTopOfStack = ( StackType_t ) 0x18; /* R24. */\r
pxTopOfStack--;\r
- *pxTopOfStack = ( portSTACK_TYPE ) 0x19; /* R25. */\r
+ *pxTopOfStack = ( StackType_t ) 0x19; /* R25. */\r
pxTopOfStack--;\r
- *pxTopOfStack = ( portSTACK_TYPE ) 0x1a; /* R26. */\r
+ *pxTopOfStack = ( StackType_t ) 0x1a; /* R26. */\r
pxTopOfStack--;\r
- *pxTopOfStack = ( portSTACK_TYPE ) 0x1b; /* R27. */\r
+ *pxTopOfStack = ( StackType_t ) 0x1b; /* R27. */\r
pxTopOfStack--;\r
- *pxTopOfStack = ( portSTACK_TYPE ) 0x1c; /* R28. */\r
+ *pxTopOfStack = ( StackType_t ) 0x1c; /* R28. */\r
pxTopOfStack--;\r
- *pxTopOfStack = ( portSTACK_TYPE ) 0x1d; /* R29. */\r
+ *pxTopOfStack = ( StackType_t ) 0x1d; /* R29. */\r
pxTopOfStack--;\r
- *pxTopOfStack = ( portSTACK_TYPE ) 0x1e; /* R30. */\r
+ *pxTopOfStack = ( StackType_t ) 0x1e; /* R30. */\r
pxTopOfStack--;\r
\r
/* The MSR is stacked between R30 and R31. */\r
*pxTopOfStack = portINITIAL_MSR_STATE;\r
pxTopOfStack--;\r
\r
- *pxTopOfStack = ( portSTACK_TYPE ) 0x1f; /* R31. */\r
+ *pxTopOfStack = ( StackType_t ) 0x1f; /* R31. */\r
pxTopOfStack--;\r
\r
/* Return a pointer to the top of the stack we have generated so this can\r
}\r
/*-----------------------------------------------------------*/\r
\r
-portBASE_TYPE xPortStartScheduler( void )\r
+BaseType_t xPortStartScheduler( void )\r
{\r
extern void ( __FreeRTOS_interrupt_Handler )( void );\r
extern void ( vStartFirstTask )( void );\r
prvSetupTimerInterrupt();\r
\r
/* Allocate the stack to be used by the interrupt handler. */\r
- pulISRStack = ( unsigned long * ) pvPortMalloc( configMINIMAL_STACK_SIZE * sizeof( portSTACK_TYPE ) );\r
+ pulISRStack = ( uint32_t * ) pvPortMalloc( configMINIMAL_STACK_SIZE * sizeof( StackType_t ) );\r
\r
/* Restore the context of the first task that is going to run. */\r
if( pulISRStack != NULL )\r
{\r
/* Fill the ISR stack with a known value to facilitate debugging. */\r
- memset( pulISRStack, portISR_STACK_FILL_VALUE, configMINIMAL_STACK_SIZE * sizeof( portSTACK_TYPE ) );\r
+ memset( pulISRStack, portISR_STACK_FILL_VALUE, configMINIMAL_STACK_SIZE * sizeof( StackType_t ) );\r
pulISRStack += ( configMINIMAL_STACK_SIZE - 1 );\r
\r
/* Kick off the first task. */\r
static void prvSetupTimerInterrupt( void )\r
{\r
XTmrCtr xTimer;\r
-const unsigned long ulCounterValue = configCPU_CLOCK_HZ / configTICK_RATE_HZ;\r
-unsigned portBASE_TYPE uxMask;\r
+const uint32_t ulCounterValue = configCPU_CLOCK_HZ / configTICK_RATE_HZ;\r
+UBaseType_t uxMask;\r
\r
/* The OPB timer1 is used to generate the tick. Use the provided library\r
functions to enable the timer and set the tick frequency. */\r
*/\r
void vTaskISRHandler( void )\r
{\r
-static unsigned long ulPending; \r
+static uint32_t ulPending; \r
\r
/* Which interrupts are pending? */\r
ulPending = XIntc_In32( ( XPAR_INTC_SINGLE_BASEADDR + XIN_IVR_OFFSET ) );\r
{\r
static XIntc_VectorTableEntry *pxTablePtr;\r
static XIntc_Config *pxConfig;\r
- static unsigned long ulInterruptMask;\r
+ static uint32_t ulInterruptMask;\r
\r
- ulInterruptMask = ( unsigned long ) 1 << ulPending;\r
+ ulInterruptMask = ( uint32_t ) 1 << ulPending;\r
\r
/* Get the configuration data using the device ID */\r
- pxConfig = &XIntc_ConfigTable[ ( unsigned long ) XPAR_INTC_SINGLE_DEVICE_ID ];\r
+ pxConfig = &XIntc_ConfigTable[ ( uint32_t ) XPAR_INTC_SINGLE_DEVICE_ID ];\r
\r
pxTablePtr = &( pxConfig->HandlerTable[ ulPending ] );\r
if( pxConfig->AckBeforeService & ( ulInterruptMask ) )\r
*/\r
void vTickISR( void *pvBaseAddress )\r
{\r
-unsigned long ulCSR;\r
+uint32_t ulCSR;\r
\r
/* Increment the RTOS tick - this might cause a task to unblock. */\r
- vTaskIncrementTick();\r
+ if( xTaskIncrementTick() != pdFALSE )\r
+ {\r
+ vTaskSwitchContext();\r
+ }\r
\r
/* Clear the timer interrupt */\r
ulCSR = XTmrCtr_mGetControlStatusReg(XPAR_OPB_TIMER_1_BASEADDR, 0); \r
XTmrCtr_mSetControlStatusReg( XPAR_OPB_TIMER_1_BASEADDR, portCOUNTER_0, ulCSR );\r
-\r
- /* If we are using the preemptive scheduler then we also need to determine\r
- if this tick should cause a context switch. */\r
- #if configUSE_PREEMPTION == 1\r
- vTaskSwitchContext();\r
- #endif\r
}\r
/*-----------------------------------------------------------*/\r
\r
projects / freertos / blobdiff