/*\r
- FreeRTOS V7.1.1 - Copyright (C) 2012 Real Time Engineers Ltd.\r
- \r
-\r
- ***************************************************************************\r
- * *\r
- * FreeRTOS tutorial books are available in pdf and paperback. *\r
- * Complete, revised, and edited pdf reference manuals are also *\r
- * available. *\r
- * *\r
- * Purchasing FreeRTOS documentation will not only help you, by *\r
- * ensuring you get running as quickly as possible and with an *\r
- * in-depth knowledge of how to use FreeRTOS, it will also help *\r
- * the FreeRTOS project to continue with its mission of providing *\r
- * professional grade, cross platform, de facto standard solutions *\r
- * for microcontrollers - completely free of charge! *\r
- * *\r
- * >>> See http://www.FreeRTOS.org/Documentation for details. <<< *\r
- * *\r
- * Thank you for using FreeRTOS, and thank you for your support! *\r
- * *\r
- ***************************************************************************\r
+ FreeRTOS V9.0.0rc2 - Copyright (C) 2016 Real Time Engineers Ltd.\r
+ All rights reserved\r
\r
+ VISIT http://www.FreeRTOS.org TO ENSURE YOU ARE USING THE LATEST VERSION.\r
\r
This file is part of the FreeRTOS distribution.\r
\r
FreeRTOS is free software; you can redistribute it and/or modify it under\r
the terms of the GNU General Public License (version 2) as published by the\r
- Free Software Foundation AND MODIFIED BY the FreeRTOS exception.\r
- >>>NOTE<<< The modification to the GPL is included to allow you to\r
- distribute a combined work that includes FreeRTOS without being obliged to\r
- provide the source code for proprietary components outside of the FreeRTOS\r
- kernel. FreeRTOS is distributed in the hope that it will be useful, but\r
- WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY\r
- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for\r
- more details. You should have received a copy of the GNU General Public\r
- License and the FreeRTOS license exception along with FreeRTOS; if not it\r
- can be viewed here: http://www.freertos.org/a00114.html and also obtained\r
- by writing to Richard Barry, contact details for whom are available on the\r
- FreeRTOS WEB site.\r
+ Free Software Foundation >>>> AND MODIFIED BY <<<< the FreeRTOS exception.\r
+\r
+ ***************************************************************************\r
+ >>! NOTE: The modification to the GPL is included to allow you to !<<\r
+ >>! distribute a combined work that includes FreeRTOS without being !<<\r
+ >>! obliged to provide the source code for proprietary components !<<\r
+ >>! outside of the FreeRTOS kernel. !<<\r
+ ***************************************************************************\r
+\r
+ FreeRTOS is distributed in the hope that it will be useful, but WITHOUT ANY\r
+ WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS\r
+ FOR A PARTICULAR PURPOSE. Full license text is available on the following\r
+ link: http://www.freertos.org/a00114.html\r
\r
- 1 tab == 4 spaces!\r
- \r
***************************************************************************\r
* *\r
- * Having a problem? Start by reading the FAQ "My application does *\r
- * not run, what could be wrong? *\r
+ * FreeRTOS provides completely free yet professionally developed, *\r
+ * robust, strictly quality controlled, supported, and cross *\r
+ * platform software that is more than just the market leader, it *\r
+ * is the industry's de facto standard. *\r
* *\r
- * http://www.FreeRTOS.org/FAQHelp.html *\r
+ * Help yourself get started quickly while simultaneously helping *\r
+ * to support the FreeRTOS project by purchasing a FreeRTOS *\r
+ * tutorial book, reference manual, or both: *\r
+ * http://www.FreeRTOS.org/Documentation *\r
* *\r
***************************************************************************\r
\r
- \r
- http://www.FreeRTOS.org - Documentation, training, latest information, \r
- license and contact details.\r
- \r
+ http://www.FreeRTOS.org/FAQHelp.html - Having a problem? Start by reading\r
+ the FAQ page "My application does not run, what could be wrong?". Have you\r
+ defined configASSERT()?\r
+\r
+ http://www.FreeRTOS.org/support - In return for receiving this top quality\r
+ embedded software for free we request you assist our global community by\r
+ participating in the support forum.\r
+\r
+ http://www.FreeRTOS.org/training - Investing in training allows your team to\r
+ be as productive as possible as early as possible. Now you can receive\r
+ FreeRTOS training directly from Richard Barry, CEO of Real Time Engineers\r
+ Ltd, and the world's leading authority on the world's leading RTOS.\r
+\r
http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products,\r
- including FreeRTOS+Trace - an indispensable productivity tool.\r
+ including FreeRTOS+Trace - an indispensable productivity tool, a DOS\r
+ compatible FAT file system, and our tiny thread aware UDP/IP stack.\r
+\r
+ http://www.FreeRTOS.org/labs - Where new FreeRTOS products go to incubate.\r
+ Come and try FreeRTOS+TCP, our new open source TCP/IP stack for FreeRTOS.\r
+\r
+ http://www.OpenRTOS.com - Real Time Engineers ltd. license FreeRTOS to High\r
+ Integrity Systems ltd. to sell under the OpenRTOS brand. Low cost OpenRTOS\r
+ licenses offer ticketed support, indemnification and commercial middleware.\r
\r
- Real Time Engineers ltd license FreeRTOS to High Integrity Systems, who sell \r
- the code with commercial support, indemnification, and middleware, under \r
- the OpenRTOS brand: http://www.OpenRTOS.com. High Integrity Systems also\r
- provide a safety engineered and independently SIL3 certified version under \r
- the SafeRTOS brand: http://www.SafeRTOS.com.\r
+ http://www.SafeRTOS.com - High Integrity Systems also provide a safety\r
+ engineered and independently SIL3 certified version for use in safety and\r
+ mission critical applications that require provable dependability.\r
+\r
+ 1 tab == 4 spaces!\r
*/\r
\r
/*-----------------------------------------------------------\r
#include <xil_exception.h>\r
#include <microblaze_exceptions_g.h>\r
\r
-/* Tasks are started with a critical section nesting of 0 - however, prior to \r
-the scheduler being commenced interrupts should not be enabled, so the critical \r
+/* Tasks are started with a critical section nesting of 0 - however, prior to\r
+the scheduler being commenced interrupts should not be enabled, so the critical\r
nesting variable is initialised to a non-zero value. */\r
#define portINITIAL_NESTING_VALUE ( 0xff )\r
\r
-/* The bit within the MSR register that enabled/disables interrupts. */\r
+/* The bit within the MSR register that enabled/disables interrupts and \r
+exceptions respectively. */\r
#define portMSR_IE ( 0x02U )\r
+#define portMSR_EE ( 0x100U )\r
\r
/* If the floating point unit is included in the MicroBlaze build, then the\r
FSR register is saved as part of the task context. portINITIAL_FSR is the value\r
/*\r
* Initialise the interrupt controller instance.\r
*/\r
-static long prvInitialiseInterruptController( void );\r
+static int32_t prvInitialiseInterruptController( void );\r
\r
-/* Ensure the interrupt controller instance variable is initialised before it is \r
- * used, and that the initialisation only happens once. \r
+/* Ensure the interrupt controller instance variable is initialised before it is\r
+ * used, and that the initialisation only happens once.\r
*/\r
-static long prvEnsureInterruptControllerIsInitialised( void );\r
+static int32_t prvEnsureInterruptControllerIsInitialised( void );\r
\r
/*-----------------------------------------------------------*/\r
\r
-/* Counts the nesting depth of calls to portENTER_CRITICAL(). Each task \r
+/* Counts the nesting depth of calls to portENTER_CRITICAL(). Each task\r
maintains its own count, so this variable is saved as part of the task\r
context. */\r
-volatile unsigned portBASE_TYPE uxCriticalNesting = portINITIAL_NESTING_VALUE;\r
+volatile UBaseType_t uxCriticalNesting = portINITIAL_NESTING_VALUE;\r
\r
/* This port uses a separate stack for interrupts. This prevents the stack of\r
every task needing to be large enough to hold an entire interrupt stack on top\r
of the task stack. */\r
-unsigned long *pulISRStack;\r
+uint32_t *pulISRStack;\r
\r
/* If an interrupt requests a context switch, then ulTaskSwitchRequested will\r
get set to 1. ulTaskSwitchRequested is inspected just before the main interrupt\r
handler exits. If, at that time, ulTaskSwitchRequested is set to 1, the kernel\r
will call vTaskSwitchContext() to ensure the task that runs immediately after\r
-the interrupt exists is the highest priority task that is able to run. This is \r
-an unusual mechanism, but is used for this port because a single interrupt can \r
+the interrupt exists is the highest priority task that is able to run. This is\r
+an unusual mechanism, but is used for this port because a single interrupt can\r
cause the servicing of multiple peripherals - and it is inefficient to call\r
vTaskSwitchContext() multiple times as each peripheral is serviced. */\r
-volatile unsigned long ulTaskSwitchRequested = 0UL;\r
+volatile uint32_t ulTaskSwitchRequested = 0UL;\r
\r
/* The instance of the interrupt controller used by this port. This is required\r
by the Xilinx library API functions. */\r
\r
/*-----------------------------------------------------------*/\r
\r
-/* \r
- * Initialise the stack of a task to look exactly as if a call to \r
+/*\r
+ * Initialise the stack of a task to look exactly as if a call to\r
* portSAVE_CONTEXT had been made.\r
- * \r
+ *\r
* See the portable.h header file.\r
*/\r
-portSTACK_TYPE *pxPortInitialiseStack( portSTACK_TYPE *pxTopOfStack, pdTASK_CODE pxCode, void *pvParameters )\r
+StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, TaskFunction_t pxCode, void *pvParameters )\r
{\r
extern void *_SDA2_BASE_, *_SDA_BASE_;\r
-const unsigned long ulR2 = ( unsigned long ) &_SDA2_BASE_;\r
-const unsigned long ulR13 = ( unsigned long ) &_SDA_BASE_;\r
+const uint32_t ulR2 = ( uint32_t ) &_SDA2_BASE_;\r
+const uint32_t ulR13 = ( uint32_t ) &_SDA_BASE_;\r
\r
- /* Place a few bytes of known values on the bottom of the stack. \r
+ /* Place a few bytes of known values on the bottom of the stack.\r
This is essential for the Microblaze port and these lines must\r
not be omitted. */\r
- *pxTopOfStack = ( portSTACK_TYPE ) 0x00000000;\r
+ *pxTopOfStack = ( StackType_t ) 0x00000000;\r
pxTopOfStack--;\r
- *pxTopOfStack = ( portSTACK_TYPE ) 0x00000000;\r
+ *pxTopOfStack = ( StackType_t ) 0x00000000;\r
pxTopOfStack--;\r
- *pxTopOfStack = ( portSTACK_TYPE ) 0x00000000;\r
+ *pxTopOfStack = ( StackType_t ) 0x00000000;\r
pxTopOfStack--;\r
\r
- #if XPAR_MICROBLAZE_0_USE_FPU == 1\r
+ #if( XPAR_MICROBLAZE_USE_FPU != 0 )\r
/* The FSR value placed in the initial task context is just 0. */\r
*pxTopOfStack = portINITIAL_FSR;\r
pxTopOfStack--;\r
disabled. Each task will enable interrupts automatically when it enters\r
the running state for the first time. */\r
*pxTopOfStack = mfmsr() & ~portMSR_IE;\r
+ \r
+ #if( MICROBLAZE_EXCEPTIONS_ENABLED == 1 )\r
+ {\r
+ /* Ensure exceptions are enabled for the task. */\r
+ *pxTopOfStack |= portMSR_EE;\r
+ }\r
+ #endif\r
+\r
pxTopOfStack--;\r
\r
/* First stack an initial value for the critical section nesting. This\r
is initialised to zero. */\r
- *pxTopOfStack = ( portSTACK_TYPE ) 0x00;\r
- \r
+ *pxTopOfStack = ( StackType_t ) 0x00;\r
+\r
/* R0 is always zero. */\r
/* R1 is the SP. */\r
\r
/* Place an initial value for all the general purpose registers. */\r
pxTopOfStack--;\r
- *pxTopOfStack = ( portSTACK_TYPE ) ulR2; /* R2 - read only small data area. */\r
+ *pxTopOfStack = ( StackType_t ) ulR2; /* R2 - read only small data area. */\r
pxTopOfStack--;\r
- *pxTopOfStack = ( portSTACK_TYPE ) 0x03; /* R3 - return values and temporaries. */\r
+ *pxTopOfStack = ( StackType_t ) 0x03; /* R3 - return values and temporaries. */\r
pxTopOfStack--;\r
- *pxTopOfStack = ( portSTACK_TYPE ) 0x04; /* R4 - return values and temporaries. */\r
+ *pxTopOfStack = ( StackType_t ) 0x04; /* R4 - return values and temporaries. */\r
pxTopOfStack--;\r
- *pxTopOfStack = ( portSTACK_TYPE ) pvParameters;/* R5 contains the function call parameters. */\r
+ *pxTopOfStack = ( StackType_t ) pvParameters;/* R5 contains the function call parameters. */\r
\r
#ifdef portPRE_LOAD_STACK_FOR_DEBUGGING\r
pxTopOfStack--;\r
- *pxTopOfStack = ( portSTACK_TYPE ) 0x06; /* R6 - other parameters and temporaries. Used as the return address from vPortTaskEntryPoint. */\r
+ *pxTopOfStack = ( StackType_t ) 0x06; /* R6 - other parameters and temporaries. Used as the return address from vPortTaskEntryPoint. */\r
pxTopOfStack--;\r
- *pxTopOfStack = ( portSTACK_TYPE ) 0x07; /* R7 - other parameters and temporaries. */\r
+ *pxTopOfStack = ( StackType_t ) 0x07; /* R7 - other parameters and temporaries. */\r
pxTopOfStack--;\r
- *pxTopOfStack = ( portSTACK_TYPE ) 0x08; /* R8 - other parameters and temporaries. */\r
+ *pxTopOfStack = ( StackType_t ) 0x08; /* R8 - other parameters and temporaries. */\r
pxTopOfStack--;\r
- *pxTopOfStack = ( portSTACK_TYPE ) 0x09; /* R9 - other parameters and temporaries. */\r
+ *pxTopOfStack = ( StackType_t ) 0x09; /* R9 - other parameters and temporaries. */\r
pxTopOfStack--;\r
- *pxTopOfStack = ( portSTACK_TYPE ) 0x0a; /* R10 - other parameters and temporaries. */\r
+ *pxTopOfStack = ( StackType_t ) 0x0a; /* R10 - other parameters and temporaries. */\r
pxTopOfStack--;\r
- *pxTopOfStack = ( portSTACK_TYPE ) 0x0b; /* R11 - temporaries. */\r
+ *pxTopOfStack = ( StackType_t ) 0x0b; /* R11 - temporaries. */\r
pxTopOfStack--;\r
- *pxTopOfStack = ( portSTACK_TYPE ) 0x0c; /* R12 - temporaries. */\r
+ *pxTopOfStack = ( StackType_t ) 0x0c; /* R12 - temporaries. */\r
pxTopOfStack--;\r
#else\r
pxTopOfStack-= 8;\r
#endif\r
- \r
- *pxTopOfStack = ( portSTACK_TYPE ) ulR13; /* R13 - read/write small data area. */\r
+\r
+ *pxTopOfStack = ( StackType_t ) ulR13; /* R13 - read/write small data area. */\r
pxTopOfStack--;\r
- *pxTopOfStack = ( portSTACK_TYPE ) pxCode; /* R14 - return address for interrupt. */\r
+ *pxTopOfStack = ( StackType_t ) pxCode; /* R14 - return address for interrupt. */\r
pxTopOfStack--;\r
- *pxTopOfStack = ( portSTACK_TYPE ) NULL; /* R15 - return address for subroutine. */\r
- \r
+ *pxTopOfStack = ( StackType_t ) NULL; /* R15 - return address for subroutine. */\r
+\r
#ifdef portPRE_LOAD_STACK_FOR_DEBUGGING\r
pxTopOfStack--;\r
- *pxTopOfStack = ( portSTACK_TYPE ) 0x10; /* R16 - return address for trap (debugger). */\r
+ *pxTopOfStack = ( StackType_t ) 0x10; /* R16 - return address for trap (debugger). */\r
pxTopOfStack--;\r
- *pxTopOfStack = ( portSTACK_TYPE ) 0x11; /* R17 - return address for exceptions, if configured. */\r
+ *pxTopOfStack = ( StackType_t ) 0x11; /* R17 - return address for exceptions, if configured. */\r
pxTopOfStack--;\r
- *pxTopOfStack = ( portSTACK_TYPE ) 0x12; /* R18 - reserved for assembler and compiler temporaries. */\r
+ *pxTopOfStack = ( StackType_t ) 0x12; /* R18 - reserved for assembler and compiler temporaries. */\r
pxTopOfStack--;\r
#else\r
pxTopOfStack -= 4;\r
#endif\r
- \r
- *pxTopOfStack = ( portSTACK_TYPE ) 0x00; /* R19 - must be saved across function calls. Callee-save. Seems to be interpreted as the frame pointer. */\r
- \r
- #ifdef portPRE_LOAD_STACK_FOR_DEBUGGING \r
+\r
+ *pxTopOfStack = ( StackType_t ) 0x00; /* R19 - must be saved across function calls. Callee-save. Seems to be interpreted as the frame pointer. */\r
+\r
+ #ifdef portPRE_LOAD_STACK_FOR_DEBUGGING\r
pxTopOfStack--;\r
- *pxTopOfStack = ( portSTACK_TYPE ) 0x14; /* R20 - reserved for storing a pointer to the Global Offset Table (GOT) in Position Independent Code (PIC). Non-volatile in non-PIC code. Must be saved across function calls. Callee-save. Not used by FreeRTOS. */\r
+ *pxTopOfStack = ( StackType_t ) 0x14; /* R20 - reserved for storing a pointer to the Global Offset Table (GOT) in Position Independent Code (PIC). Non-volatile in non-PIC code. Must be saved across function calls. Callee-save. Not used by FreeRTOS. */\r
pxTopOfStack--;\r
- *pxTopOfStack = ( portSTACK_TYPE ) 0x15; /* R21 - must be saved across function calls. Callee-save. */\r
+ *pxTopOfStack = ( StackType_t ) 0x15; /* R21 - must be saved across function calls. Callee-save. */\r
pxTopOfStack--;\r
- *pxTopOfStack = ( portSTACK_TYPE ) 0x16; /* R22 - must be saved across function calls. Callee-save. */\r
+ *pxTopOfStack = ( StackType_t ) 0x16; /* R22 - must be saved across function calls. Callee-save. */\r
pxTopOfStack--;\r
- *pxTopOfStack = ( portSTACK_TYPE ) 0x17; /* R23 - must be saved across function calls. Callee-save. */\r
+ *pxTopOfStack = ( StackType_t ) 0x17; /* R23 - must be saved across function calls. Callee-save. */\r
pxTopOfStack--;\r
- *pxTopOfStack = ( portSTACK_TYPE ) 0x18; /* R24 - must be saved across function calls. Callee-save. */\r
+ *pxTopOfStack = ( StackType_t ) 0x18; /* R24 - must be saved across function calls. Callee-save. */\r
pxTopOfStack--;\r
- *pxTopOfStack = ( portSTACK_TYPE ) 0x19; /* R25 - must be saved across function calls. Callee-save. */\r
+ *pxTopOfStack = ( StackType_t ) 0x19; /* R25 - must be saved across function calls. Callee-save. */\r
pxTopOfStack--;\r
- *pxTopOfStack = ( portSTACK_TYPE ) 0x1a; /* R26 - must be saved across function calls. Callee-save. */\r
+ *pxTopOfStack = ( StackType_t ) 0x1a; /* R26 - must be saved across function calls. Callee-save. */\r
pxTopOfStack--;\r
- *pxTopOfStack = ( portSTACK_TYPE ) 0x1b; /* R27 - must be saved across function calls. Callee-save. */\r
+ *pxTopOfStack = ( StackType_t ) 0x1b; /* R27 - must be saved across function calls. Callee-save. */\r
pxTopOfStack--;\r
- *pxTopOfStack = ( portSTACK_TYPE ) 0x1c; /* R28 - must be saved across function calls. Callee-save. */\r
+ *pxTopOfStack = ( StackType_t ) 0x1c; /* R28 - must be saved across function calls. Callee-save. */\r
pxTopOfStack--;\r
- *pxTopOfStack = ( portSTACK_TYPE ) 0x1d; /* R29 - must be saved across function calls. Callee-save. */\r
+ *pxTopOfStack = ( StackType_t ) 0x1d; /* R29 - must be saved across function calls. Callee-save. */\r
pxTopOfStack--;\r
- *pxTopOfStack = ( portSTACK_TYPE ) 0x1e; /* R30 - must be saved across function calls. Callee-save. */\r
+ *pxTopOfStack = ( StackType_t ) 0x1e; /* R30 - must be saved across function calls. Callee-save. */\r
pxTopOfStack--;\r
- *pxTopOfStack = ( portSTACK_TYPE ) 0x1f; /* R31 - must be saved across function calls. Callee-save. */\r
+ *pxTopOfStack = ( StackType_t ) 0x1f; /* R31 - must be saved across function calls. Callee-save. */\r
pxTopOfStack--;\r
#else\r
pxTopOfStack -= 13;\r
#endif\r
\r
- /* Return a pointer to the top of the stack that has been generated so this \r
+ /* Return a pointer to the top of the stack that has been generated so this\r
can be stored in the task control block for the task. */\r
return pxTopOfStack;\r
}\r
/*-----------------------------------------------------------*/\r
\r
-portBASE_TYPE xPortStartScheduler( void )\r
+BaseType_t xPortStartScheduler( void )\r
{\r
extern void ( vPortStartFirstTask )( void );\r
-extern unsigned long _stack[];\r
+extern uint32_t _stack[];\r
\r
/* Setup the hardware to generate the tick. Interrupts are disabled when\r
- this function is called. \r
- \r
+ this function is called.\r
+\r
This port uses an application defined callback function to install the tick\r
- interrupt handler because the kernel will run on lots of different \r
- MicroBlaze and FPGA configurations - not all of which will have the same \r
+ interrupt handler because the kernel will run on lots of different\r
+ MicroBlaze and FPGA configurations - not all of which will have the same\r
timer peripherals defined or available. An example definition of\r
vApplicationSetupTimerInterrupt() is provided in the official demo\r
application that accompanies this port. */\r
vApplicationSetupTimerInterrupt();\r
\r
/* Reuse the stack from main() as the stack for the interrupts/exceptions. */\r
- pulISRStack = ( unsigned long * ) _stack;\r
+ pulISRStack = ( uint32_t * ) _stack;\r
\r
/* Ensure there is enough space for the functions called from the interrupt\r
service routines to write back into the stack frame of the caller. */\r
\r
void vPortEndScheduler( void )\r
{\r
- /* Not implemented. */\r
+ /* Not implemented in ports where there is nothing to return to.\r
+ Artificially force an assert. */\r
+ configASSERT( uxCriticalNesting == 1000UL );\r
}\r
/*-----------------------------------------------------------*/\r
\r
/*\r
- * Manual context switch called by portYIELD or taskYIELD. \r
+ * Manual context switch called by portYIELD or taskYIELD.\r
*/\r
void vPortYield( void )\r
{\r
}\r
/*-----------------------------------------------------------*/\r
\r
-void vPortEnableInterrupt( unsigned char ucInterruptID )\r
+void vPortEnableInterrupt( uint8_t ucInterruptID )\r
{\r
-long lReturn;\r
+int32_t lReturn;\r
\r
/* An API function is provided to enable an interrupt in the interrupt\r
controller because the interrupt controller instance variable is private\r
{\r
XIntc_Enable( &xInterruptControllerInstance, ucInterruptID );\r
}\r
- \r
+\r
configASSERT( lReturn );\r
}\r
/*-----------------------------------------------------------*/\r
\r
-void vPortDisableInterrupt( unsigned char ucInterruptID )\r
+void vPortDisableInterrupt( uint8_t ucInterruptID )\r
{\r
-long lReturn;\r
+int32_t lReturn;\r
\r
/* An API function is provided to disable an interrupt in the interrupt\r
controller because the interrupt controller instance variable is private\r
to this file. */\r
lReturn = prvEnsureInterruptControllerIsInitialised();\r
- \r
+\r
if( lReturn == pdPASS )\r
{\r
XIntc_Disable( &xInterruptControllerInstance, ucInterruptID );\r
}\r
- \r
+\r
configASSERT( lReturn );\r
}\r
/*-----------------------------------------------------------*/\r
\r
-portBASE_TYPE xPortInstallInterruptHandler( unsigned char ucInterruptID, XInterruptHandler pxHandler, void *pvCallBackRef )\r
+BaseType_t xPortInstallInterruptHandler( uint8_t ucInterruptID, XInterruptHandler pxHandler, void *pvCallBackRef )\r
{\r
-long lReturn;\r
+int32_t lReturn;\r
\r
- /* An API function is provided to install an interrupt handler because the \r
+ /* An API function is provided to install an interrupt handler because the\r
interrupt controller instance variable is private to this file. */\r
\r
lReturn = prvEnsureInterruptControllerIsInitialised();\r
- \r
+\r
if( lReturn == pdPASS )\r
{\r
lReturn = XIntc_Connect( &xInterruptControllerInstance, ucInterruptID, pxHandler, pvCallBackRef );\r
{\r
lReturn = pdPASS;\r
}\r
- \r
+\r
configASSERT( lReturn == pdPASS );\r
\r
return lReturn;\r
}\r
/*-----------------------------------------------------------*/\r
\r
-static long prvEnsureInterruptControllerIsInitialised( void )\r
+static int32_t prvEnsureInterruptControllerIsInitialised( void )\r
{\r
-static long lInterruptControllerInitialised = pdFALSE;\r
-long lReturn;\r
+static int32_t lInterruptControllerInitialised = pdFALSE;\r
+int32_t lReturn;\r
\r
/* Ensure the interrupt controller instance variable is initialised before\r
it is used, and that the initialisation only happens once. */\r
if( lInterruptControllerInitialised != pdTRUE )\r
{\r
lReturn = prvInitialiseInterruptController();\r
- \r
+\r
if( lReturn == pdPASS )\r
{\r
lInterruptControllerInitialised = pdTRUE;\r
}\r
/*-----------------------------------------------------------*/\r
\r
-/* \r
+/*\r
* Handler for the timer interrupt. This is the handler that the application\r
* defined callback function vApplicationSetupTimerInterrupt() should install.\r
*/\r
( void ) pvUnused;\r
\r
/* This port uses an application defined callback function to clear the tick\r
- interrupt because the kernel will run on lots of different MicroBlaze and \r
- FPGA configurations - not all of which will have the same timer peripherals \r
+ interrupt because the kernel will run on lots of different MicroBlaze and\r
+ FPGA configurations - not all of which will have the same timer peripherals\r
defined or available. An example definition of\r
vApplicationClearTimerInterrupt() is provided in the official demo\r
- application that accompanies this port. */ \r
+ application that accompanies this port. */\r
vApplicationClearTimerInterrupt();\r
\r
/* Increment the RTOS tick - this might cause a task to unblock. */\r
- vTaskIncrementTick();\r
-\r
- /* If the preemptive scheduler is being used then a context switch should be\r
- requested in case incrementing the tick unblocked a task, or a time slice\r
- should cause another task to enter the Running state. */\r
- #if configUSE_PREEMPTION == 1\r
+ if( xTaskIncrementTick() != pdFALSE )\r
+ {\r
/* Force vTaskSwitchContext() to be called as the interrupt exits. */\r
ulTaskSwitchRequested = 1;\r
- #endif\r
+ }\r
}\r
/*-----------------------------------------------------------*/\r
\r
-static long prvInitialiseInterruptController( void )\r
+static int32_t prvInitialiseInterruptController( void )\r
{\r
-long lStatus;\r
+int32_t lStatus;\r
\r
lStatus = XIntc_Initialize( &xInterruptControllerInstance, configINTERRUPT_CONTROLLER_TO_USE );\r
\r
projects / freertos / blobdiff