/*\r
- FreeRTOS V7.6.0 - Copyright (C) 2013 Real Time Engineers Ltd. \r
+ FreeRTOS V8.1.2 - Copyright (C) 2014 Real Time Engineers Ltd.\r
All rights reserved\r
\r
VISIT http://www.FreeRTOS.org TO ENSURE YOU ARE USING THE LATEST VERSION.\r
the terms of the GNU General Public License (version 2) as published by the\r
Free Software Foundation >>!AND MODIFIED BY!<< the FreeRTOS exception.\r
\r
- >>! NOTE: The modification to the GPL is included to allow you to distribute\r
- >>! a combined work that includes FreeRTOS without being obliged to provide\r
- >>! the source code for proprietary components outside of the FreeRTOS\r
- >>! kernel.\r
+ >>! NOTE: The modification to the GPL is included to allow you to !<<\r
+ >>! distribute a combined work that includes FreeRTOS without being !<<\r
+ >>! obliged to provide the source code for proprietary components !<<\r
+ >>! outside of the FreeRTOS kernel. !<<\r
\r
FreeRTOS is distributed in the hope that it will be useful, but WITHOUT ANY\r
WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS\r
\r
/* Tasks should start with interrupts enabled and in Supervisor mode, therefore\r
PSW is set with U and I set, and PM and IPL clear. */\r
-#define portINITIAL_PSW ( ( portSTACK_TYPE ) 0x00030000 )\r
+#define portINITIAL_PSW ( ( StackType_t ) 0x00030000 )\r
\r
/* The peripheral clock is divided by this value before being supplying the\r
CMT. */\r
* instruction.\r
*/\r
#if configUSE_TICKLESS_IDLE == 1\r
- static void prvSleep( portTickType xExpectedIdleTime );\r
+ static void prvSleep( TickType_t xExpectedIdleTime );\r
#endif /* configUSE_TICKLESS_IDLE */\r
\r
/*-----------------------------------------------------------*/\r
extern void *pxCurrentTCB;\r
\r
/* Calculate how many clock increments make up a single tick period. */\r
-static const unsigned long ulMatchValueForOneTick = ( ( configPERIPHERAL_CLOCK_HZ / portCLOCK_DIVISOR ) / configTICK_RATE_HZ );\r
+static const uint32_t ulMatchValueForOneTick = ( ( configPERIPHERAL_CLOCK_HZ / portCLOCK_DIVISOR ) / configTICK_RATE_HZ );\r
\r
#if configUSE_TICKLESS_IDLE == 1\r
\r
basically how far into the future an interrupt can be generated. Set\r
during initialisation. This is the maximum possible value that the\r
compare match register can hold divided by ulMatchValueForOneTick. */\r
- static const portTickType xMaximumPossibleSuppressedTicks = USHRT_MAX / ( ( configPERIPHERAL_CLOCK_HZ / portCLOCK_DIVISOR ) / configTICK_RATE_HZ );\r
+ static const TickType_t xMaximumPossibleSuppressedTicks = USHRT_MAX / ( ( configPERIPHERAL_CLOCK_HZ / portCLOCK_DIVISOR ) / configTICK_RATE_HZ );\r
\r
/* Flag set from the tick interrupt to allow the sleep processing to know if\r
sleep mode was exited because of a tick interrupt, or an interrupt\r
compensate for the lost time. The large difference between the divided CMT\r
clock and the CPU clock means it is likely ulStoppedTimerCompensation will\r
equal zero - and be optimised away. */\r
- static const unsigned long ulStoppedTimerCompensation = 100UL / ( configCPU_CLOCK_HZ / ( configPERIPHERAL_CLOCK_HZ / portCLOCK_DIVISOR ) );\r
+ static const uint32_t ulStoppedTimerCompensation = 100UL / ( configCPU_CLOCK_HZ / ( configPERIPHERAL_CLOCK_HZ / portCLOCK_DIVISOR ) );\r
\r
#endif\r
\r
/*\r
* See header file for description.\r
*/\r
-portSTACK_TYPE *pxPortInitialiseStack( portSTACK_TYPE *pxTopOfStack, pdTASK_CODE pxCode, void *pvParameters )\r
+StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, TaskFunction_t pxCode, void *pvParameters )\r
{\r
/* Offset to end up on 8 byte boundary. */\r
pxTopOfStack--;\r
pxTopOfStack--;\r
*pxTopOfStack = portINITIAL_PSW;\r
pxTopOfStack--;\r
- *pxTopOfStack = ( portSTACK_TYPE ) pxCode;\r
+ *pxTopOfStack = ( StackType_t ) pxCode;\r
\r
/* When debugging it can be useful if every register is set to a known\r
value. Otherwise code space can be saved by just setting the registers\r
}\r
#endif\r
\r
- *pxTopOfStack = ( portSTACK_TYPE ) pvParameters; /* R1 */\r
+ *pxTopOfStack = ( StackType_t ) pvParameters; /* R1 */\r
pxTopOfStack--;\r
*pxTopOfStack = 0x12345678; /* Accumulator. */\r
pxTopOfStack--;\r
}\r
/*-----------------------------------------------------------*/\r
\r
-portBASE_TYPE xPortStartScheduler( void )\r
+BaseType_t xPortStartScheduler( void )\r
{\r
/* Use pxCurrentTCB just so it does not get optimised away. */\r
if( pxCurrentTCB != NULL )\r
\r
void vPortEndScheduler( void )\r
{\r
- /* Not implemented as there is nothing to return to. */\r
+ /* Not implemented in ports where there is nothing to return to.\r
+ Artificially force an assert. */\r
+ configASSERT( pxCurrentTCB == NULL );\r
}\r
/*-----------------------------------------------------------*/\r
\r
\r
/* If this is the first tick since exiting tickless mode then the CMT\r
compare match value needs resetting. */\r
- CMT0.CMCOR = ( unsigned short ) ulMatchValueForOneTick;\r
+ CMT0.CMCOR = ( uint16_t ) ulMatchValueForOneTick;\r
}\r
#endif\r
}\r
/*-----------------------------------------------------------*/\r
\r
-unsigned long ulPortGetIPL( void )\r
+uint32_t ulPortGetIPL( void )\r
{\r
__asm volatile\r
(\r
}\r
/*-----------------------------------------------------------*/\r
\r
-void vPortSetIPL( unsigned long ulNewIPL )\r
+void vPortSetIPL( uint32_t ulNewIPL )\r
{\r
__asm volatile\r
(\r
CMT0.CMCR.BIT.CMIE = 1;\r
\r
/* Set the compare match value. */\r
- CMT0.CMCOR = ( unsigned short ) ulMatchValueForOneTick;\r
+ CMT0.CMCOR = ( uint16_t ) ulMatchValueForOneTick;\r
\r
/* Divide the PCLK. */\r
#if portCLOCK_DIVISOR == 512\r
\r
#if configUSE_TICKLESS_IDLE == 1\r
\r
- static void prvSleep( portTickType xExpectedIdleTime )\r
+ static void prvSleep( TickType_t xExpectedIdleTime )\r
{\r
/* Allow the application to define some pre-sleep processing. */\r
configPRE_SLEEP_PROCESSING( xExpectedIdleTime );\r
\r
#if configUSE_TICKLESS_IDLE == 1\r
\r
- void vPortSuppressTicksAndSleep( portTickType xExpectedIdleTime )\r
+ void vPortSuppressTicksAndSleep( TickType_t xExpectedIdleTime )\r
{\r
- unsigned long ulMatchValue, ulCompleteTickPeriods, ulCurrentCount;\r
+ uint32_t ulMatchValue, ulCompleteTickPeriods, ulCurrentCount;\r
eSleepModeStatus eSleepAction;\r
\r
/* THIS FUNCTION IS CALLED WITH THE SCHEDULER SUSPENDED. */\r
\r
/* Adjust the match value to take into account that the current\r
time slice is already partially complete. */\r
- ulMatchValue -= ( unsigned long ) CMT0.CMCNT;\r
- CMT0.CMCOR = ( unsigned short ) ulMatchValue;\r
+ ulMatchValue -= ( uint32_t ) CMT0.CMCNT;\r
+ CMT0.CMCOR = ( uint16_t ) ulMatchValue;\r
\r
/* Restart the CMT to count up to the new match value. */\r
CMT0.CMCNT = 0;\r
/* Nothing to do here. */\r
}\r
\r
- ulCurrentCount = ( unsigned long ) CMT0.CMCNT;\r
+ ulCurrentCount = ( uint32_t ) CMT0.CMCNT;\r
\r
if( ulTickFlag != pdFALSE )\r
{\r
exited. Reset the match value with whatever remains of this\r
tick period. */\r
ulMatchValue = ulMatchValueForOneTick - ulCurrentCount;\r
- CMT0.CMCOR = ( unsigned short ) ulMatchValue;\r
+ CMT0.CMCOR = ( uint16_t ) ulMatchValue;\r
\r
/* The tick interrupt handler will already have pended the tick\r
processing in the kernel. As the pending tick will be\r
/* The match value is set to whatever fraction of a single tick\r
period remains. */\r
ulMatchValue = ulCurrentCount - ( ulCompleteTickPeriods * ulMatchValueForOneTick );\r
- CMT0.CMCOR = ( unsigned short ) ulMatchValue;\r
+ CMT0.CMCOR = ( uint16_t ) ulMatchValue;\r
}\r
\r
/* Restart the CMT so it runs up to the match value. The match value\r
projects / freertos / blobdiff