/*\r
- FreeRTOS V7.6.0 - Copyright (C) 2013 Real Time Engineers Ltd. \r
+ FreeRTOS V7.6.0 - Copyright (C) 2013 Real Time Engineers Ltd.\r
All rights reserved\r
\r
VISIT http://www.FreeRTOS.org TO ENSURE YOU ARE USING THE LATEST VERSION.\r
\r
/*-----------------------------------------------------------*/\r
\r
-/* Tasks should start with interrupts enabled and in Supervisor mode, therefore \r
+/* Tasks should start with interrupts enabled and in Supervisor mode, therefore\r
PSW is set with U and I set, and PM and IPL clear. */\r
#define portINITIAL_PSW ( ( portSTACK_TYPE ) 0x00030000 )\r
#define portINITIAL_FPSW ( ( portSTACK_TYPE ) 0x00000100 )\r
\r
/* These macros allow a critical section to be added around the call to\r
-xTaskIncrementTick(), which is only ever called from interrupts at the kernel \r
-priority - ie a known priority. Therefore these local macros are a slight \r
-optimisation compared to calling the global SET/CLEAR_INTERRUPT_MASK macros, \r
+xTaskIncrementTick(), which is only ever called from interrupts at the kernel\r
+priority - ie a known priority. Therefore these local macros are a slight\r
+optimisation compared to calling the global SET/CLEAR_INTERRUPT_MASK macros,\r
which would require the old IPL to be read first and stored in a local variable. */\r
#define portDISABLE_INTERRUPTS_FROM_KERNEL_ISR() __asm volatile ( "MVTIPL %0" ::"i"(configMAX_SYSCALL_INTERRUPT_PRIORITY) )\r
#define portENABLE_INTERRUPTS_FROM_KERNEL_ISR() __asm volatile ( "MVTIPL %0" ::"i"(configKERNEL_INTERRUPT_PRIORITY) )\r
\r
/*\r
* Function to start the first task executing - written in asm code as direct\r
- * access to registers is required. \r
+ * access to registers is required.\r
*/\r
static void prvStartFirstTask( void ) __attribute__((naked));\r
\r
\r
/*-----------------------------------------------------------*/\r
\r
-/* \r
- * See header file for description. \r
+/*\r
+ * See header file for description.\r
*/\r
portSTACK_TYPE *pxPortInitialiseStack( portSTACK_TYPE *pxTopOfStack, pdTASK_CODE pxCode, void *pvParameters )\r
{\r
/* R0 is not included as it is the stack pointer. */\r
- \r
+\r
*pxTopOfStack = 0x00;\r
pxTopOfStack--;\r
*pxTopOfStack = portINITIAL_PSW;\r
pxTopOfStack--;\r
*pxTopOfStack = ( portSTACK_TYPE ) pxCode;\r
- \r
+\r
/* When debugging it can be useful if every register is set to a known\r
value. Otherwise code space can be saved by just setting the registers\r
that need to be set. */\r
pxTopOfStack -= 15;\r
}\r
#endif\r
- \r
+\r
*pxTopOfStack = ( portSTACK_TYPE ) pvParameters; /* R1 */\r
- pxTopOfStack--; \r
+ pxTopOfStack--;\r
*pxTopOfStack = portINITIAL_FPSW;\r
pxTopOfStack--;\r
*pxTopOfStack = 0x12345678; /* Accumulator. */\r
if( pxCurrentTCB != NULL )\r
{\r
/* Call an application function to set up the timer that will generate the\r
- tick interrupt. This way the application can decide which peripheral to \r
+ tick interrupt. This way the application can decide which peripheral to\r
use. A demo application is provided to show a suitable example. */\r
vApplicationSetupTimerInterrupt();\r
\r
- /* Enable the software interrupt. */ \r
+ /* Enable the software interrupt. */\r
_IEN( _ICU_SWINT ) = 1;\r
- \r
+\r
/* Ensure the software interrupt is clear. */\r
_IR( _ICU_SWINT ) = 0;\r
- \r
+\r
/* Ensure the software interrupt is set to the kernel priority. */\r
_IPR( _ICU_SWINT ) = configKERNEL_INTERRUPT_PRIORITY;\r
\r
\r
void vPortEndScheduler( void )\r
{\r
- /* Not implemented as there is nothing to return to. */\r
+ /* Not implemented in ports where there is nothing to return to.\r
+ Artificially force an assert. */\r
+ configASSERT( pxCurrentTCB == NULL );\r
}\r
/*-----------------------------------------------------------*/\r
\r
static void prvStartFirstTask( void )\r
{\r
__asm volatile\r
- ( \r
+ (\r
/* When starting the scheduler there is nothing that needs moving to the\r
interrupt stack because the function is not called from an interrupt.\r
Just ensure the current stack is the user stack. */\r
"SETPSW U \n" \\r
\r
- /* Obtain the location of the stack associated with which ever task \r
+ /* Obtain the location of the stack associated with which ever task\r
pxCurrentTCB is currently pointing to. */\r
"MOV.L #_pxCurrentTCB, R15 \n" \\r
"MOV.L [R15], R15 \n" \\r
"MOV.L [R15], R0 \n" \\r
\r
- /* Restore the registers from the stack of the task pointed to by \r
+ /* Restore the registers from the stack of the task pointed to by\r
pxCurrentTCB. */\r
"POP R15 \n" \\r
- \r
+\r
/* Accumulator low 32 bits. */\r
"MVTACLO R15 \n" \\r
"POP R15 \n" \\r
- \r
+\r
/* Accumulator high 32 bits. */\r
"MVTACHI R15 \n" \\r
"POP R15 \n" \\r
- \r
+\r
/* Floating point status word. */\r
"MVTC R15, FPSW \n" \\r
- \r
+\r
/* R1 to R15 - R0 is not included as it is the SP. */\r
"POPM R1-R15 \n" \\r
- \r
+\r
/* This pops the remaining registers. */\r
"RTE \n" \\r
"NOP \n" \\r
"SETPSW I \n" \\r
\r
/* Move the data that was automatically pushed onto the interrupt stack when\r
- the interrupt occurred from the interrupt stack to the user stack. \r
- \r
+ the interrupt occurred from the interrupt stack to the user stack.\r
+\r
R15 is saved before it is clobbered. */\r
"PUSH.L R15 \n" \\r
- \r
+\r
/* Read the user stack pointer. */\r
"MVFC USP, R15 \n" \\r
- \r
+\r
/* Move the address down to the data being moved. */\r
"SUB #12, R15 \n" \\r
"MVTC R15, USP \n" \\r
- \r
+\r
/* Copy the data across, R15, then PC, then PSW. */\r
"MOV.L [ R0 ], [ R15 ] \n" \\r
"MOV.L 4[ R0 ], 4[ R15 ] \n" \\r
\r
/* Move the interrupt stack pointer to its new correct position. */\r
"ADD #12, R0 \n" \\r
- \r
+\r
/* All the rest of the registers are saved directly to the user stack. */\r
"SETPSW U \n" \\r
\r
/* Save the rest of the general registers (R15 has been saved already). */\r
"PUSHM R1-R14 \n" \\r
- \r
+\r
/* Save the FPSW and accumulator. */\r
"MVFC FPSW, R15 \n" \\r
"PUSH.L R15 \n" \\r
"MVFACHI R15 \n" \\r
"PUSH.L R15 \n" \\r
- \r
+\r
/* Middle word. */\r
"MVFACMI R15 \n" \\r
- \r
+\r
/* Shifted left as it is restored to the low order word. */\r
"SHLL #16, R15 \n" \\r
"PUSH.L R15 \n" \\r
"MOV.L #_pxCurrentTCB, R15 \n" \\r
"MOV.L [ R15 ], R15 \n" \\r
"MOV.L R0, [ R15 ] \n" \\r
- \r
+\r
/* Ensure the interrupt mask is set to the syscall priority while the kernel\r
structures are being accessed. */\r
"MVTIPL %0 \n" \\r
{\r
/* Re-enabled interrupts. */\r
__asm volatile( "SETPSW I" );\r
- \r
+\r
/* Increment the tick, and perform any processing the new tick value\r
necessitates. Ensure IPL is at the max syscall value first. */\r
portDISABLE_INTERRUPTS_FROM_KERNEL_ISR();\r
unsigned long ulPortGetIPL( void )\r
{\r
__asm volatile\r
- ( \r
+ (\r
"MVFC PSW, R1 \n" \\r
"SHLR #24, R1 \n" \\r
"RTS "\r
);\r
- \r
+\r
/* This will never get executed, but keeps the compiler from complaining. */\r
return 0;\r
}\r
void vPortSetIPL( unsigned long ulNewIPL )\r
{\r
__asm volatile\r
- ( \r
+ (\r
"PUSH R5 \n" \\r
"MVFC PSW, R5 \n" \\r
"SHLL #24, R1 \n" \\r
projects / freertos / blobdiff