/*\r
- FreeRTOS V7.3.0 - Copyright (C) 2012 Real Time Engineers Ltd.\r
-\r
- FEATURES AND PORTS ARE ADDED TO FREERTOS ALL THE TIME. PLEASE VISIT \r
- http://www.FreeRTOS.org TO ENSURE YOU ARE USING THE LATEST VERSION.\r
-\r
- ***************************************************************************\r
- * *\r
- * FreeRTOS tutorial books are available in pdf and paperback. *\r
- * Complete, revised, and edited pdf reference manuals are also *\r
- * available. *\r
- * *\r
- * Purchasing FreeRTOS documentation will not only help you, by *\r
- * ensuring you get running as quickly as possible and with an *\r
- * in-depth knowledge of how to use FreeRTOS, it will also help *\r
- * the FreeRTOS project to continue with its mission of providing *\r
- * professional grade, cross platform, de facto standard solutions *\r
- * for microcontrollers - completely free of charge! *\r
- * *\r
- * >>> See http://www.FreeRTOS.org/Documentation for details. <<< *\r
- * *\r
- * Thank you for using FreeRTOS, and thank you for your support! *\r
- * *\r
- ***************************************************************************\r
-\r
-\r
- This file is part of the FreeRTOS distribution.\r
-\r
- FreeRTOS is free software; you can redistribute it and/or modify it under\r
- the terms of the GNU General Public License (version 2) as published by the\r
- Free Software Foundation AND MODIFIED BY the FreeRTOS exception.\r
- >>>NOTE<<< The modification to the GPL is included to allow you to\r
- distribute a combined work that includes FreeRTOS without being obliged to\r
- provide the source code for proprietary components outside of the FreeRTOS\r
- kernel. FreeRTOS is distributed in the hope that it will be useful, but\r
- WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY\r
- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for\r
- more details. You should have received a copy of the GNU General Public\r
- License and the FreeRTOS license exception along with FreeRTOS; if not it\r
- can be viewed here: http://www.freertos.org/a00114.html and also obtained\r
- by writing to Richard Barry, contact details for whom are available on the\r
- FreeRTOS WEB site.\r
-\r
- 1 tab == 4 spaces!\r
- \r
- ***************************************************************************\r
- * *\r
- * Having a problem? Start by reading the FAQ "My application does *\r
- * not run, what could be wrong?" *\r
- * *\r
- * http://www.FreeRTOS.org/FAQHelp.html *\r
- * *\r
- ***************************************************************************\r
-\r
- \r
- http://www.FreeRTOS.org - Documentation, training, latest versions, license \r
- and contact details. \r
- \r
- http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products,\r
- including FreeRTOS+Trace - an indispensable productivity tool.\r
-\r
- Real Time Engineers ltd license FreeRTOS to High Integrity Systems, who sell \r
- the code with commercial support, indemnification, and middleware, under \r
- the OpenRTOS brand: http://www.OpenRTOS.com. High Integrity Systems also\r
- provide a safety engineered and independently SIL3 certified version under \r
- the SafeRTOS brand: http://www.SafeRTOS.com.\r
-*/\r
+ * FreeRTOS Kernel V10.2.1\r
+ * Copyright (C) 2019 Amazon.com, Inc. or its affiliates. All Rights Reserved.\r
+ *\r
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of\r
+ * this software and associated documentation files (the "Software"), to deal in\r
+ * the Software without restriction, including without limitation the rights to\r
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of\r
+ * the Software, and to permit persons to whom the Software is furnished to do so,\r
+ * subject to the following conditions:\r
+ *\r
+ * The above copyright notice and this permission notice shall be included in all\r
+ * copies or substantial portions of the Software.\r
+ *\r
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR\r
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS\r
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR\r
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER\r
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN\r
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.\r
+ *\r
+ * http://www.FreeRTOS.org\r
+ * http://aws.amazon.com/freertos\r
+ *\r
+ * 1 tab == 4 spaces!\r
+ */\r
\r
/*-----------------------------------------------------------\r
* Implementation of functions defined in portable.h for the SH2A port.\r
\r
/*-----------------------------------------------------------*/\r
\r
-/* Tasks should start with interrupts enabled and in Supervisor mode, therefore \r
+/* Tasks should start with interrupts enabled and in Supervisor mode, therefore\r
PSW is set with U and I set, and PM and IPL clear. */\r
-#define portINITIAL_PSW ( ( portSTACK_TYPE ) 0x00030000 )\r
-#define portINITIAL_FPSW ( ( portSTACK_TYPE ) 0x00000100 )\r
+#define portINITIAL_PSW ( ( StackType_t ) 0x00030000 )\r
+#define portINITIAL_FPSW ( ( StackType_t ) 0x00000100 )\r
\r
/* These macros allow a critical section to be added around the call to\r
-vTaskIncrementTick(), which is only ever called from interrupts at the kernel \r
-priority - ie a known priority. Therefore these local macros are a slight \r
-optimisation compared to calling the global SET/CLEAR_INTERRUPT_MASK macros, \r
+xTaskIncrementTick(), which is only ever called from interrupts at the kernel\r
+priority - ie a known priority. Therefore these local macros are a slight\r
+optimisation compared to calling the global SET/CLEAR_INTERRUPT_MASK macros,\r
which would require the old IPL to be read first and stored in a local variable. */\r
#define portDISABLE_INTERRUPTS_FROM_KERNEL_ISR() __asm volatile ( "MVTIPL %0" ::"i"(configMAX_SYSCALL_INTERRUPT_PRIORITY) )\r
#define portENABLE_INTERRUPTS_FROM_KERNEL_ISR() __asm volatile ( "MVTIPL %0" ::"i"(configKERNEL_INTERRUPT_PRIORITY) )\r
\r
/*\r
* Function to start the first task executing - written in asm code as direct\r
- * access to registers is required. \r
+ * access to registers is required.\r
*/\r
static void prvStartFirstTask( void ) __attribute__((naked));\r
\r
\r
/*-----------------------------------------------------------*/\r
\r
-/* \r
- * See header file for description. \r
+/*\r
+ * See header file for description.\r
*/\r
-portSTACK_TYPE *pxPortInitialiseStack( portSTACK_TYPE *pxTopOfStack, pdTASK_CODE pxCode, void *pvParameters )\r
+StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, TaskFunction_t pxCode, void *pvParameters )\r
{\r
/* R0 is not included as it is the stack pointer. */\r
- \r
+\r
*pxTopOfStack = 0x00;\r
pxTopOfStack--;\r
*pxTopOfStack = portINITIAL_PSW;\r
pxTopOfStack--;\r
- *pxTopOfStack = ( portSTACK_TYPE ) pxCode;\r
- \r
+ *pxTopOfStack = ( StackType_t ) pxCode;\r
+\r
/* When debugging it can be useful if every register is set to a known\r
value. Otherwise code space can be saved by just setting the registers\r
that need to be set. */\r
pxTopOfStack -= 15;\r
}\r
#endif\r
- \r
- *pxTopOfStack = ( portSTACK_TYPE ) pvParameters; /* R1 */\r
- pxTopOfStack--; \r
+\r
+ *pxTopOfStack = ( StackType_t ) pvParameters; /* R1 */\r
+ pxTopOfStack--;\r
*pxTopOfStack = portINITIAL_FPSW;\r
pxTopOfStack--;\r
*pxTopOfStack = 0x12345678; /* Accumulator. */\r
}\r
/*-----------------------------------------------------------*/\r
\r
-portBASE_TYPE xPortStartScheduler( void )\r
+BaseType_t xPortStartScheduler( void )\r
{\r
extern void vApplicationSetupTimerInterrupt( void );\r
\r
if( pxCurrentTCB != NULL )\r
{\r
/* Call an application function to set up the timer that will generate the\r
- tick interrupt. This way the application can decide which peripheral to \r
+ tick interrupt. This way the application can decide which peripheral to\r
use. A demo application is provided to show a suitable example. */\r
vApplicationSetupTimerInterrupt();\r
\r
- /* Enable the software interrupt. */ \r
+ /* Enable the software interrupt. */\r
_IEN( _ICU_SWINT ) = 1;\r
- \r
+\r
/* Ensure the software interrupt is clear. */\r
_IR( _ICU_SWINT ) = 0;\r
- \r
+\r
/* Ensure the software interrupt is set to the kernel priority. */\r
_IPR( _ICU_SWINT ) = configKERNEL_INTERRUPT_PRIORITY;\r
\r
\r
void vPortEndScheduler( void )\r
{\r
- /* Not implemented as there is nothing to return to. */\r
+ /* Not implemented in ports where there is nothing to return to.\r
+ Artificially force an assert. */\r
+ configASSERT( pxCurrentTCB == NULL );\r
}\r
/*-----------------------------------------------------------*/\r
\r
static void prvStartFirstTask( void )\r
{\r
__asm volatile\r
- ( \r
+ (\r
/* When starting the scheduler there is nothing that needs moving to the\r
interrupt stack because the function is not called from an interrupt.\r
Just ensure the current stack is the user stack. */\r
"SETPSW U \n" \\r
\r
- /* Obtain the location of the stack associated with which ever task \r
+ /* Obtain the location of the stack associated with which ever task\r
pxCurrentTCB is currently pointing to. */\r
"MOV.L #_pxCurrentTCB, R15 \n" \\r
"MOV.L [R15], R15 \n" \\r
"MOV.L [R15], R0 \n" \\r
\r
- /* Restore the registers from the stack of the task pointed to by \r
+ /* Restore the registers from the stack of the task pointed to by\r
pxCurrentTCB. */\r
"POP R15 \n" \\r
- \r
+\r
/* Accumulator low 32 bits. */\r
"MVTACLO R15 \n" \\r
"POP R15 \n" \\r
- \r
+\r
/* Accumulator high 32 bits. */\r
"MVTACHI R15 \n" \\r
"POP R15 \n" \\r
- \r
+\r
/* Floating point status word. */\r
"MVTC R15, FPSW \n" \\r
- \r
+\r
/* R1 to R15 - R0 is not included as it is the SP. */\r
"POPM R1-R15 \n" \\r
- \r
+\r
/* This pops the remaining registers. */\r
"RTE \n" \\r
"NOP \n" \\r
"SETPSW I \n" \\r
\r
/* Move the data that was automatically pushed onto the interrupt stack when\r
- the interrupt occurred from the interrupt stack to the user stack. \r
- \r
+ the interrupt occurred from the interrupt stack to the user stack.\r
+\r
R15 is saved before it is clobbered. */\r
"PUSH.L R15 \n" \\r
- \r
+\r
/* Read the user stack pointer. */\r
"MVFC USP, R15 \n" \\r
- \r
+\r
/* Move the address down to the data being moved. */\r
"SUB #12, R15 \n" \\r
"MVTC R15, USP \n" \\r
- \r
+\r
/* Copy the data across, R15, then PC, then PSW. */\r
"MOV.L [ R0 ], [ R15 ] \n" \\r
"MOV.L 4[ R0 ], 4[ R15 ] \n" \\r
\r
/* Move the interrupt stack pointer to its new correct position. */\r
"ADD #12, R0 \n" \\r
- \r
+\r
/* All the rest of the registers are saved directly to the user stack. */\r
"SETPSW U \n" \\r
\r
/* Save the rest of the general registers (R15 has been saved already). */\r
"PUSHM R1-R14 \n" \\r
- \r
+\r
/* Save the FPSW and accumulator. */\r
"MVFC FPSW, R15 \n" \\r
"PUSH.L R15 \n" \\r
"MVFACHI R15 \n" \\r
"PUSH.L R15 \n" \\r
- \r
+\r
/* Middle word. */\r
"MVFACMI R15 \n" \\r
- \r
+\r
/* Shifted left as it is restored to the low order word. */\r
"SHLL #16, R15 \n" \\r
"PUSH.L R15 \n" \\r
"MOV.L #_pxCurrentTCB, R15 \n" \\r
"MOV.L [ R15 ], R15 \n" \\r
"MOV.L R0, [ R15 ] \n" \\r
- \r
+\r
/* Ensure the interrupt mask is set to the syscall priority while the kernel\r
structures are being accessed. */\r
"MVTIPL %0 \n" \\r
{\r
/* Re-enabled interrupts. */\r
__asm volatile( "SETPSW I" );\r
- \r
+\r
/* Increment the tick, and perform any processing the new tick value\r
necessitates. Ensure IPL is at the max syscall value first. */\r
portDISABLE_INTERRUPTS_FROM_KERNEL_ISR();\r
{\r
- vTaskIncrementTick(); \r
+ if( xTaskIncrementTick() != pdFALSE )\r
+ {\r
+ taskYIELD();\r
+ }\r
}\r
portENABLE_INTERRUPTS_FROM_KERNEL_ISR();\r
- \r
- /* Only select a new task if the preemptive scheduler is being used. */\r
- #if( configUSE_PREEMPTION == 1 )\r
- taskYIELD();\r
- #endif\r
}\r
/*-----------------------------------------------------------*/\r
\r
-unsigned long ulPortGetIPL( void )\r
+uint32_t ulPortGetIPL( void )\r
{\r
__asm volatile\r
- ( \r
+ (\r
"MVFC PSW, R1 \n" \\r
"SHLR #24, R1 \n" \\r
"RTS "\r
);\r
- \r
+\r
/* This will never get executed, but keeps the compiler from complaining. */\r
return 0;\r
}\r
/*-----------------------------------------------------------*/\r
\r
-void vPortSetIPL( unsigned long ulNewIPL )\r
+void vPortSetIPL( uint32_t ulNewIPL )\r
{\r
__asm volatile\r
- ( \r
+ (\r
"PUSH R5 \n" \\r
"MVFC PSW, R5 \n" \\r
"SHLL #24, R1 \n" \\r
projects / freertos / blobdiff