]> git.sur5r.net Git - freertos/blobdiff - FreeRTOS/Source/portable/GCC/TriCore_1782/portmacro.h
Update version number ready for version 9 release candidate 1.
[freertos] / FreeRTOS / Source / portable / GCC / TriCore_1782 / portmacro.h
index 830002761e9b4aa36db8ef46521581dacfadf784..05909fd7fe1a38e3e1f995b7e49c3e913238b676 100644 (file)
@@ -1,75 +1,70 @@
 /*\r
-    FreeRTOS V7.4.0 - Copyright (C) 2013 Real Time Engineers Ltd.\r
-\r
-    FEATURES AND PORTS ARE ADDED TO FREERTOS ALL THE TIME.  PLEASE VISIT\r
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-\r
-    ***************************************************************************\r
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-     *                                                                       *\r
-    ***************************************************************************\r
+    FreeRTOS V9.0.0rc1 - Copyright (C) 2016 Real Time Engineers Ltd.\r
+    All rights reserved\r
 \r
+    VISIT http://www.FreeRTOS.org TO ENSURE YOU ARE USING THE LATEST VERSION.\r
 \r
     This file is part of the FreeRTOS distribution.\r
 \r
     FreeRTOS is free software; you can redistribute it and/or modify it under\r
     the terms of the GNU General Public License (version 2) as published by the\r
-    Free Software Foundation AND MODIFIED BY the FreeRTOS exception.\r
+    Free Software Foundation >>>> AND MODIFIED BY <<<< the FreeRTOS exception.\r
 \r
-    >>>>>>NOTE<<<<<< The modification to the GPL is included to allow you to\r
-    distribute a combined work that includes FreeRTOS without being obliged to\r
-    provide the source code for proprietary components outside of the FreeRTOS\r
-    kernel.\r
+    ***************************************************************************\r
+    >>!   NOTE: The modification to the GPL is included to allow you to     !<<\r
+    >>!   distribute a combined work that includes FreeRTOS without being   !<<\r
+    >>!   obliged to provide the source code for proprietary components     !<<\r
+    >>!   outside of the FreeRTOS kernel.                                   !<<\r
+    ***************************************************************************\r
 \r
     FreeRTOS is distributed in the hope that it will be useful, but WITHOUT ANY\r
     WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS\r
-    FOR A PARTICULAR PURPOSE.  See the GNU General Public License for more\r
-    details. You should have received a copy of the GNU General Public License\r
-    and the FreeRTOS license exception along with FreeRTOS; if not itcan be\r
-    viewed here: http://www.freertos.org/a00114.html and also obtained by\r
-    writing to Real Time Engineers Ltd., contact details for whom are available\r
-    on the FreeRTOS WEB site.\r
-\r
-    1 tab == 4 spaces!\r
+    FOR A PARTICULAR PURPOSE.  Full license text is available on the following\r
+    link: http://www.freertos.org/a00114.html\r
 \r
     ***************************************************************************\r
      *                                                                       *\r
-     *    Having a problem?  Start by reading the FAQ "My application does   *\r
-     *    not run, what could be wrong?"                                     *\r
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     ***************************************************************************\r
 \r
+    http://www.FreeRTOS.org/FAQHelp.html - Having a problem?  Start by reading\r
+    the FAQ page "My application does not run, what could be wrong?".  Have you\r
+    defined configASSERT()?\r
+\r
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+    participating in the support forum.\r
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-    http://www.FreeRTOS.org - Documentation, books, training, latest versions, \r
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-    engineered and independently SIL3 certified version for use in safety and \r
+    including FreeRTOS+Trace - an indispensable productivity tool, a DOS\r
+    compatible FAT file system, and our tiny thread aware UDP/IP stack.\r
+\r
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+\r
+    http://www.OpenRTOS.com - Real Time Engineers ltd. license FreeRTOS to High\r
+    Integrity Systems ltd. to sell under the OpenRTOS brand.  Low cost OpenRTOS\r
+    licenses offer ticketed support, indemnification and commercial middleware.\r
+\r
+    http://www.SafeRTOS.com - High Integrity Systems also provide a safety\r
+    engineered and independently SIL3 certified version for use in safety and\r
     mission critical applications that require provable dependability.\r
+\r
+    1 tab == 4 spaces!\r
 */\r
 \r
 #ifndef PORTMACRO_H\r
@@ -99,21 +94,29 @@ extern "C" {
 #define portDOUBLE             double\r
 #define portLONG               long\r
 #define portSHORT              short\r
-#define portSTACK_TYPE unsigned long\r
+#define portSTACK_TYPE uint32_t\r
 #define portBASE_TYPE  long\r
 \r
+typedef portSTACK_TYPE StackType_t;\r
+typedef long BaseType_t;\r
+typedef unsigned long UBaseType_t;\r
+\r
 #if( configUSE_16_BIT_TICKS == 1 )\r
-       typedef unsigned portSHORT portTickType;\r
-       #define portMAX_DELAY ( portTickType ) 0xffff\r
+       typedef uint16_t TickType_t;\r
+       #define portMAX_DELAY ( TickType_t ) 0xffff\r
 #else\r
-       typedef unsigned portLONG portTickType;\r
-       #define portMAX_DELAY ( portTickType ) 0xffffffff\r
+       typedef uint32_t TickType_t;\r
+       #define portMAX_DELAY ( TickType_t ) 0xffffffffUL\r
+\r
+       /* 32-bit tick type on a 32-bit architecture, so reads of the tick count do\r
+       not need to be guarded with a critical section. */\r
+       #define portTICK_TYPE_IS_ATOMIC 1\r
 #endif\r
 /*---------------------------------------------------------------------------*/\r
 \r
 /* Architecture specifics. */\r
 #define portSTACK_GROWTH                                                       ( -1 )\r
-#define portTICK_RATE_MS                                                       ( ( portTickType ) 1000 / configTICK_RATE_HZ )\r
+#define portTICK_PERIOD_MS                                                     ( ( TickType_t ) 1000 / configTICK_RATE_HZ )\r
 #define portBYTE_ALIGNMENT                                                     4\r
 #define portNOP()                                                                      __asm volatile( " nop " )\r
 #define portCRITICAL_NESTING_IN_TCB                                    1\r
@@ -122,7 +125,7 @@ extern "C" {
 \r
 /*---------------------------------------------------------------------------*/\r
 \r
-typedef struct MPU_SETTINGS { unsigned long ulNotUsed; } xMPU_SETTINGS;\r
+typedef struct MPU_SETTINGS { uint32_t ulNotUsed; } xMPU_SETTINGS;\r
 \r
 /* Define away the instruction from the Restore Context Macro. */\r
 #define portPRIVILEGE_BIT                                                      0x0UL\r
@@ -136,8 +139,8 @@ extern void vTaskExitCritical( void );
 /*---------------------------------------------------------------------------*/\r
 \r
 /* CSA Manipulation. */\r
-#define portCSA_TO_ADDRESS( pCSA )                     ( ( unsigned long * )( ( ( ( pCSA ) & 0x000F0000 ) << 12 ) | ( ( ( pCSA ) & 0x0000FFFF ) << 6 ) ) )\r
-#define portADDRESS_TO_CSA( pAddress )         ( ( unsigned long )( ( ( ( (unsigned long)( pAddress ) ) & 0xF0000000 ) >> 12 ) | ( ( ( unsigned long )( pAddress ) & 0x003FFFC0 ) >> 6 ) ) )\r
+#define portCSA_TO_ADDRESS( pCSA )                     ( ( uint32_t * )( ( ( ( pCSA ) & 0x000F0000 ) << 12 ) | ( ( ( pCSA ) & 0x0000FFFF ) << 6 ) ) )\r
+#define portADDRESS_TO_CSA( pAddress )         ( ( uint32_t )( ( ( ( (uint32_t)( pAddress ) ) & 0xF0000000 ) >> 12 ) | ( ( ( uint32_t )( pAddress ) & 0x003FFFC0 ) >> 6 ) ) )\r
 /*---------------------------------------------------------------------------*/\r
 \r
 #define portYIELD()                                                            _syscall( 0 )\r
@@ -150,7 +153,7 @@ extern void vTaskExitCritical( void );
 \r
 /* Set ICR.CCPN to configMAX_SYSCALL_INTERRUPT_PRIORITY. */\r
 #define portDISABLE_INTERRUPTS()       {                                                                                                                                                                                                       \\r
-                                                                               unsigned long ulICR;                                                                                                                                                    \\r
+                                                                               uint32_t ulICR;                                                                                                                                                 \\r
                                                                                _disable();                                                                                                                                                                             \\r
                                                                                ulICR = _mfcr( $ICR );          /* Get current ICR value. */                                                                            \\r
                                                                                ulICR &= ~portCCPN_MASK;        /* Clear down mask bits. */                                                                                     \\r
@@ -162,7 +165,7 @@ extern void vTaskExitCritical( void );
 \r
 /* Clear ICR.CCPN to allow all interrupt priorities. */\r
 #define portENABLE_INTERRUPTS()                {                                                                                                                                       \\r
-                                                                               unsigned long ulICR;                                                                                    \\r
+                                                                               uint32_t ulICR;                                                                                 \\r
                                                                                _disable();                                                                                                             \\r
                                                                                ulICR = _mfcr( $ICR );          /* Get current ICR value. */            \\r
                                                                                ulICR &= ~portCCPN_MASK;        /* Clear down mask bits. */                     \\r
@@ -173,7 +176,7 @@ extern void vTaskExitCritical( void );
 \r
 /* Set ICR.CCPN to uxSavedMaskValue. */\r
 #define portCLEAR_INTERRUPT_MASK_FROM_ISR( uxSavedMaskValue )  {                                                                                                                                                                               \\r
-                                                                                                                                       unsigned long ulICR;                                                                                                                            \\r
+                                                                                                                                       uint32_t ulICR;                                                                                                                         \\r
                                                                                                                                        _disable();                                                                                                                                                     \\r
                                                                                                                                        ulICR = _mfcr( $ICR );          /* Get current ICR value. */                                                    \\r
                                                                                                                                        ulICR &= ~portCCPN_MASK;        /* Clear down mask bits. */                                                             \\r
@@ -185,13 +188,9 @@ extern void vTaskExitCritical( void );
 \r
 \r
 /* Set ICR.CCPN to configMAX_SYSCALL_INTERRUPT_PRIORITY */\r
-extern unsigned long uxPortSetInterruptMaskFromISR( void );\r
+extern uint32_t uxPortSetInterruptMaskFromISR( void );\r
 #define portSET_INTERRUPT_MASK_FROM_ISR()      uxPortSetInterruptMaskFromISR()\r
 \r
-/* As this port holds a CSA address in pxTopOfStack, the assert that checks the\r
-pxTopOfStack alignment is removed. */\r
-#define portALIGNMENT_ASSERT_pxCurrentTCB ( void )\r
-\r
 /* Pend a priority 1 interrupt, which will take care of the context switch. */\r
 #define portYIELD_FROM_ISR( xHigherPriorityTaskWoken )                 if( xHigherPriorityTaskWoken != pdFALSE ) {     CPU_SRC0.bits.SETR = 1; _isync(); }\r
 \r
@@ -206,8 +205,8 @@ pxTopOfStack alignment is removed. */
  * Port specific clean up macro required to free the CSAs that were consumed by\r
  * a task that has since been deleted.\r
  */\r
-void vPortReclaimCSA( unsigned long *pxTCB );\r
-#define portCLEAN_UP_TCB( pxTCB )              vPortReclaimCSA( ( unsigned long * ) ( pxTCB ) )\r
+void vPortReclaimCSA( uint32_t *pxTCB );\r
+#define portCLEAN_UP_TCB( pxTCB )              vPortReclaimCSA( ( uint32_t * ) ( pxTCB ) )\r
 \r
 #ifdef __cplusplus\r
 }\r