/**\r
* Architecture specifics.\r
*/\r
-#define portARCH_NAME "Cortex-M33"\r
+#define portARCH_NAME "Cortex-M23"\r
#define portSTACK_GROWTH ( -1 )\r
#define portTICK_PERIOD_MS ( ( TickType_t ) 1000 / configTICK_RATE_HZ )\r
#define portBYTE_ALIGNMENT 8\r
#define portFORCE_INLINE inline __attribute__(( always_inline ))\r
#endif\r
#define portHAS_STACK_OVERFLOW_CHECKING 1\r
+#define portDONT_DISCARD __root\r
/*-----------------------------------------------------------*/\r
\r
/**\r
extern void vClearInterruptMaskFromISR( uint32_t ulMask ) /* __attribute__(( naked )) PRIVILEGED_FUNCTION */;\r
\r
#if( configENABLE_TRUSTZONE == 1 )\r
- extern void vPortAllocateSecureContext( uint32_t ulSecureStackSize );\r
- extern void vPortFreeSecureContext( uint32_t *pulTCB ) /* PRIVILEGED_FUNCTION */;\r
+ extern void vPortAllocateSecureContext( uint32_t ulSecureStackSize ); /* __attribute__ (( naked )) */\r
+ extern void vPortFreeSecureContext( uint32_t *pulTCB ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */;\r
#endif /* configENABLE_TRUSTZONE */\r
\r
#if( configENABLE_MPU == 1 )\r