Added Cortex-M optimised code to the IAR, GCC and Keil Cortex-M port layers.

[freertos] / FreeRTOS / Source / portable / IAR / ARM_CM3 / portmacro.h

diff --git a/FreeRTOS/Source/portable/IAR/ARM_CM3/portmacro.h b/FreeRTOS/Source/portable/IAR/ARM_CM3/portmacro.h
index 939b640b530d6379ac37d3f3208012089be0586a..1536a5e53054d7c31e7c2372404e883dce120612 100644 (file)
--- a/FreeRTOS/Source/portable/IAR/ARM_CM3/portmacro.h
+++ b/FreeRTOS/Source/portable/IAR/ARM_CM3/portmacro.h
@@ -40,7 +40,7 @@
     FreeRTOS WEB site.\r
 \r
     1 tab == 4 spaces!\r
-    \r
+\r
     ***************************************************************************\r
      *                                                                       *\r
      *    Having a problem?  Start by reading the FAQ "My application does   *\r
@@ -50,17 +50,17 @@
      *                                                                       *\r
     ***************************************************************************\r
 \r
-    \r
-    http://www.FreeRTOS.org - Documentation, training, latest information, \r
+\r
+    http://www.FreeRTOS.org - Documentation, training, latest information,\r
     license and contact details.\r
-    \r
+\r
     http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products,\r
     including FreeRTOS+Trace - an indispensable productivity tool.\r
 \r
-    Real Time Engineers ltd license FreeRTOS to High Integrity Systems, who sell \r
-    the code with commercial support, indemnification, and middleware, under \r
+    Real Time Engineers ltd license FreeRTOS to High Integrity Systems, who sell\r
+    the code with commercial support, indemnification, and middleware, under\r
     the OpenRTOS brand: http://www.OpenRTOS.com.  High Integrity Systems also\r
-    provide a safety engineered and independently SIL3 certified version under \r
+    provide a safety engineered and independently SIL3 certified version under\r
     the SafeRTOS brand: http://www.SafeRTOS.com.\r
 */\r
 \r
@@ -115,6 +115,24 @@ extern void vPortYieldFromISR( void );
 #define portEND_SWITCHING_ISR( xSwitchRequired ) if( xSwitchRequired ) vPortYieldFromISR()\r
 /*-----------------------------------------------------------*/\r
 \r
+#if configUSE_PORT_OPTIMISED_TASK_SELECTION == 1\r
+\r
+       /* Check the configuration. */\r
+       #if( configMAX_PRIORITIES >= 32 )\r
+               #error configUSE_PORT_OPTIMISED_TASK_SELECTION can only be set to 1 when configMAX_PRIORITIES is less than or equal to 32.  It is very rare that a system requires more than 10 to 15 difference priorities as tasks that share a priority will time slice.\r
+       #endif\r
+\r
+       /* Store/clear the ready priorities in a bit map. */\r
+       #define portRECORD_READY_PRIORITY( uxPriority, uxReadyPriorities ) ( uxReadyPriorities ) |= ( 1UL << ( uxPriority ) )\r
+       #define portRESET_READY_PRIORITY( uxPriority, uxReadyPriorities ) ( uxReadyPriorities ) &= ~( 1UL << ( uxPriority ) )\r
+\r
+       /*-----------------------------------------------------------*/\r
+\r
+       #include <intrinsics.h>\r
+       #define portGET_HIGHEST_PRIORITY( uxTopPriority, uxReadyPriorities ) uxTopPriority = ( 31 - __CLZ( ( uxReadyPriorities ) ) )\r
+\r
+#endif /* taskRECORD_READY_PRIORITY */\r
+\r
 \r
 /* Critical section management. */\r
 \r
@@ -128,7 +146,7 @@ extern void vPortClearInterruptMask( void );
 #define portENTER_CRITICAL()                                   vPortEnterCritical()\r
 #define portEXIT_CRITICAL()                                            vPortExitCritical()\r
 \r
-/* FAQ:  Setting BASEPRI to 0 is not a bug.  Please see \r
+/* FAQ:  Setting BASEPRI to 0 is not a bug.  Please see\r
 http://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html before disagreeing. */\r
 #define portSET_INTERRUPT_MASK_FROM_ISR()              0;vPortSetInterruptMask()\r
 #define portCLEAR_INTERRUPT_MASK_FROM_ISR(x)   vPortClearInterruptMask();(void)x\r