/*\r
- * FreeRTOS Kernel V10.2.0\r
+ * FreeRTOS Kernel V10.2.1\r
* Copyright (C) 2019 Amazon.com, Inc. or its affiliates. All Rights Reserved.\r
*\r
* Permission is hereby granted, free of charge, to any person obtaining a copy of\r
#define portNO_SECURE_CONTEXT 0\r
/*-----------------------------------------------------------*/\r
\r
-/**\r
- * @brief Setup the timer to generate the tick interrupts.\r
- */\r
-static void prvSetupTimerInterrupt( void ) PRIVILEGED_FUNCTION;\r
-\r
/**\r
* @brief Used to catch tasks that attempt to return from their implementing\r
* function.\r
static void prvSetupFPU( void ) PRIVILEGED_FUNCTION;\r
#endif /* configENABLE_FPU */\r
\r
+/**\r
+ * @brief Setup the timer to generate the tick interrupts.\r
+ *\r
+ * The implementation in this file is weak to allow application writers to\r
+ * change the timer used to generate the tick interrupt.\r
+ */\r
+void vPortSetupTimerInterrupt( void ) PRIVILEGED_FUNCTION;\r
+\r
+/**\r
+ * @brief Checks whether the current execution context is interrupt.\r
+ *\r
+ * @return pdTRUE if the current execution context is interrupt, pdFALSE\r
+ * otherwise.\r
+ */\r
+BaseType_t xPortIsInsideInterrupt( void );\r
+\r
/**\r
* @brief Yield the processor.\r
*/\r
/**\r
* @brief C part of SVC handler.\r
*/\r
-void vPortSVCHandler_C( uint32_t *pulCallerStackAddress ) PRIVILEGED_FUNCTION;\r
+portDONT_DISCARD void vPortSVCHandler_C( uint32_t *pulCallerStackAddress ) PRIVILEGED_FUNCTION;\r
/*-----------------------------------------------------------*/\r
\r
/**\r
* @brief Saved as part of the task context to indicate which context the\r
* task is using on the secure side.\r
*/\r
- volatile SecureContextHandle_t xSecureContext = portNO_SECURE_CONTEXT;\r
+ portDONT_DISCARD volatile SecureContextHandle_t xSecureContext = portNO_SECURE_CONTEXT;\r
#endif /* configENABLE_TRUSTZONE */\r
/*-----------------------------------------------------------*/\r
\r
-static void prvSetupTimerInterrupt( void ) /* PRIVILEGED_FUNCTION */\r
+__attribute__(( weak )) void vPortSetupTimerInterrupt( void ) /* PRIVILEGED_FUNCTION */\r
{\r
/* Stop and reset the SysTick. */\r
*( portNVIC_SYSTICK_CTRL ) = 0UL;\r
extern uint32_t * __privileged_functions_start__;\r
extern uint32_t * __privileged_functions_end__;\r
extern uint32_t * __syscalls_flash_start__;\r
+ extern uint32_t * __syscalls_flash_end__;\r
+ extern uint32_t * __unprivileged_flash_start__;\r
extern uint32_t * __unprivileged_flash_end__;\r
extern uint32_t * __privileged_sram_start__;\r
extern uint32_t * __privileged_sram_end__;\r
extern uint32_t __privileged_functions_start__[];\r
extern uint32_t __privileged_functions_end__[];\r
extern uint32_t __syscalls_flash_start__[];\r
+ extern uint32_t __syscalls_flash_end__[];\r
+ extern uint32_t __unprivileged_flash_start__[];\r
extern uint32_t __unprivileged_flash_end__[];\r
extern uint32_t __privileged_sram_start__[];\r
extern uint32_t __privileged_sram_end__[];\r
( portMPU_RLAR_ATTR_INDEX0 ) |\r
( portMPU_RLAR_REGION_ENABLE );\r
\r
- /* Setup unprivileged flash and system calls flash as Read Only by\r
- * both privileged and unprivileged tasks. All tasks can read it but\r
- * no-one can modify. */\r
+ /* Setup unprivileged flash as Read Only by both privileged and\r
+ * unprivileged tasks. All tasks can read it but no-one can modify. */\r
portMPU_RNR_REG = portUNPRIVILEGED_FLASH_REGION;\r
- portMPU_RBAR_REG = ( ( ( uint32_t ) __syscalls_flash_start__ ) & portMPU_RBAR_ADDRESS_MASK ) |\r
+ portMPU_RBAR_REG = ( ( ( uint32_t ) __unprivileged_flash_start__ ) & portMPU_RBAR_ADDRESS_MASK ) |\r
( portMPU_REGION_NON_SHAREABLE ) |\r
( portMPU_REGION_READ_ONLY );\r
portMPU_RLAR_REG = ( ( ( uint32_t ) __unprivileged_flash_end__ ) & portMPU_RLAR_ADDRESS_MASK ) |\r
( portMPU_RLAR_ATTR_INDEX0 ) |\r
( portMPU_RLAR_REGION_ENABLE );\r
\r
+ /* Setup unprivileged syscalls flash as Read Only by both privileged\r
+ * and unprivileged tasks. All tasks can read it but no-one can modify. */\r
+ portMPU_RNR_REG = portUNPRIVILEGED_SYSCALLS_REGION;\r
+ portMPU_RBAR_REG = ( ( ( uint32_t ) __syscalls_flash_start__ ) & portMPU_RBAR_ADDRESS_MASK ) |\r
+ ( portMPU_REGION_NON_SHAREABLE ) |\r
+ ( portMPU_REGION_READ_ONLY );\r
+ portMPU_RLAR_REG = ( ( ( uint32_t ) __syscalls_flash_end__ ) & portMPU_RLAR_ADDRESS_MASK ) |\r
+ ( portMPU_RLAR_ATTR_INDEX0 ) |\r
+ ( portMPU_RLAR_REGION_ENABLE );\r
+\r
/* Setup RAM containing kernel data for privileged access only. */\r
portMPU_RNR_REG = portPRIVILEGED_RAM_REGION;\r
portMPU_RBAR_REG = ( ( ( uint32_t ) __privileged_sram_start__ ) & portMPU_RBAR_ADDRESS_MASK ) |\r
( portMPU_RLAR_ATTR_INDEX0 ) |\r
( portMPU_RLAR_REGION_ENABLE );\r
\r
- /* By default allow everything to access the general peripherals.\r
- * The system peripherals and registers are protected. */\r
- portMPU_RNR_REG = portUNPRIVILEGED_DEVICE_REGION;\r
- portMPU_RBAR_REG = ( ( ( uint32_t ) portDEVICE_REGION_START_ADDRESS ) & portMPU_RBAR_ADDRESS_MASK ) |\r
- ( portMPU_REGION_NON_SHAREABLE ) |\r
- ( portMPU_REGION_READ_WRITE ) |\r
- ( portMPU_REGION_EXECUTE_NEVER );\r
- portMPU_RLAR_REG = ( ( ( uint32_t ) portDEVICE_REGION_END_ADDRESS ) & portMPU_RLAR_ADDRESS_MASK ) |\r
- ( portMPU_RLAR_ATTR_INDEX1 ) |\r
- ( portMPU_RLAR_REGION_ENABLE );\r
-\r
/* Enable mem fault. */\r
portSCB_SYS_HANDLER_CTRL_STATE_REG |= portSCB_MEM_FAULT_ENABLE;\r
\r
}\r
/*-----------------------------------------------------------*/\r
\r
-void vPortSVCHandler_C( uint32_t *pulCallerStackAddress ) /* PRIVILEGED_FUNCTION */\r
+void vPortSVCHandler_C( uint32_t *pulCallerStackAddress ) /* PRIVILEGED_FUNCTION portDONT_DISCARD */\r
{\r
#if( configENABLE_MPU == 1 )\r
#if defined( __ARMCC_VERSION )\r
\r
/* Start the timer that generates the tick ISR. Interrupts are disabled\r
* here already. */\r
- prvSetupTimerInterrupt();\r
+ vPortSetupTimerInterrupt();\r
\r
/* Initialize the critical nesting count ready for the first task. */\r
ulCriticalNesting = 0;\r
}\r
#endif /* configENABLE_MPU */\r
/*-----------------------------------------------------------*/\r
+\r
+BaseType_t xPortIsInsideInterrupt( void )\r
+{\r
+uint32_t ulCurrentInterrupt;\r
+BaseType_t xReturn;\r
+\r
+ /* Obtain the number of the currently executing interrupt. Interrupt Program\r
+ * Status Register (IPSR) holds the exception number of the currently-executing\r
+ * exception or zero for Thread mode.*/\r
+ __asm volatile( "mrs %0, ipsr" : "=r"( ulCurrentInterrupt ) :: "memory" );\r
+\r
+ if( ulCurrentInterrupt == 0 )\r
+ {\r
+ xReturn = pdFALSE;\r
+ }\r
+ else\r
+ {\r
+ xReturn = pdTRUE;\r
+ }\r
+\r
+ return xReturn;\r
+}\r
+/*-----------------------------------------------------------*/
\ No newline at end of file