Updates to CM4_MPU IAR port

[freertos] / FreeRTOS / Source / portable / IAR / ARM_CM4F_MPU / portasm.s

diff --git a/FreeRTOS/Source/portable/IAR/ARM_CM4F_MPU/portasm.s b/FreeRTOS/Source/portable/IAR/ARM_CM4F_MPU/portasm.s
index 7dcc6e2c3b99c8cfc79ff6a3de5d8c55c762642d..1c0db8da7a9def4ad751497e13a9e78b70a959a6 100644 (file)
--- a/FreeRTOS/Source/portable/IAR/ARM_CM4F_MPU/portasm.s
+++ b/FreeRTOS/Source/portable/IAR/ARM_CM4F_MPU/portasm.s
@@ -1,5 +1,5 @@
 /*\r
- * FreeRTOS Kernel V10.2.0\r
+ * FreeRTOS Kernel V10.2.1\r
  * Copyright (C) 2019 Amazon.com, Inc. or its affiliates.  All Rights Reserved.\r
  *\r
  * Permission is hereby granted, free of charge, to any person obtaining a copy of\r
@@ -78,12 +78,26 @@ xPortPendSVHandler:
        ldr r0, [r1]\r
        /* Move onto the second item in the TCB... */\r
        add r1, r1, #4\r
+\r
+       dmb                                     /* Complete outstanding transfers before disabling MPU. */\r
+       ldr r2, =0xe000ed94     /* MPU_CTRL register. */\r
+       ldr r3, [r2]            /* Read the value of MPU_CTRL. */\r
+       bic r3, r3, #1          /* r3 = r3 & ~1 i.e. Clear the bit 0 in r3. */\r
+       str r3, [r2]            /* Disable MPU. */\r
+\r
        /* Region Base Address register. */\r
        ldr r2, =0xe000ed9c\r
        /* Read 4 sets of MPU registers. */\r
        ldmia r1!, {r4-r11}\r
        /* Write 4 sets of MPU registers. */\r
        stmia r2!, {r4-r11}\r
+\r
+       ldr r2, =0xe000ed94     /* MPU_CTRL register. */\r
+       ldr r3, [r2]            /* Read the value of MPU_CTRL. */\r
+       orr r3, r3, #1          /* r3 = r3 | 1 i.e. Set the bit 0 in r3. */\r
+       str r3, [r2]            /* Enable MPU. */\r
+       dsb                                     /* Force memory writes before continuing. */\r
+\r
        /* Pop the registers that are not automatically saved on exception entry. */\r
        ldmia r0!, {r3-r11, r14}\r
        msr control, r3\r
@@ -151,12 +165,26 @@ vPortRestoreContextOfFirstTask:
        ldr r0, [r1]\r
        /* Move onto the second item in the TCB... */\r
        add r1, r1, #4\r
+\r
+       dmb                                     /* Complete outstanding transfers before disabling MPU. */\r
+       ldr r2, =0xe000ed94     /* MPU_CTRL register. */\r
+       ldr r3, [r2]            /* Read the value of MPU_CTRL. */\r
+       bic r3, r3, #1          /* r3 = r3 & ~1 i.e. Clear the bit 0 in r3. */\r
+       str r3, [r2]            /* Disable MPU. */\r
+\r
        /* Region Base Address register. */\r
        ldr r2, =0xe000ed9c\r
        /* Read 4 sets of MPU registers. */\r
        ldmia r1!, {r4-r11}\r
        /* Write 4 sets of MPU registers. */\r
        stmia r2!, {r4-r11}\r
+\r
+       ldr r2, =0xe000ed94     /* MPU_CTRL register. */\r
+       ldr r3, [r2]            /* Read the value of MPU_CTRL. */\r
+       orr r3, r3, #1          /* r3 = r3 | 1 i.e. Set the bit 0 in r3. */\r
+       str r3, [r2]            /* Enable MPU. */\r
+       dsb                                     /* Force memory writes before continuing. */\r
+\r
        /* Pop the registers that are not automatically saved on exception entry. */\r
        ldmia r0!, {r3-r11, r14}\r
        msr control, r3\r