/*\r
- * FreeRTOS Kernel V10.0.0\r
- * Copyright (C) 2017 Amazon.com, Inc. or its affiliates. All Rights Reserved.\r
+ * FreeRTOS Kernel V10.2.1\r
+ * Copyright (C) 2019 Amazon.com, Inc. or its affiliates. All Rights Reserved.\r
*\r
* Permission is hereby granted, free of charge, to any person obtaining a copy of\r
* this software and associated documentation files (the "Software"), to deal in\r
* subject to the following conditions:\r
*\r
* The above copyright notice and this permission notice shall be included in all\r
- * copies or substantial portions of the Software. If you wish to use our Amazon\r
- * FreeRTOS name, please do so in a fair use way that does not cause confusion.\r
+ * copies or substantial portions of the Software.\r
*\r
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR\r
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS\r
*\r
* 1 tab == 4 spaces!\r
*/\r
-\r
+/* Including FreeRTOSConfig.h here will cause build errors if the header file\r
+contains code not understood by the assembler - for example the 'extern' keyword.\r
+To avoid errors place any such code inside a #ifdef __ICCARM__/#endif block so\r
+the code is included in C files but excluded by the preprocessor in assembly\r
+files (__ICCARM__ is defined by the IAR C compiler but not by the IAR assembler. */\r
#include <FreeRTOSConfig.h>\r
\r
RSEG CODE:CODE(2)\r
PUBLIC vPortStartFirstTask\r
PUBLIC vPortEnableVFP\r
PUBLIC vPortRestoreContextOfFirstTask\r
- PUBLIC xPortRaisePrivilege\r
+ PUBLIC xIsPrivileged\r
+ PUBLIC vResetPrivilege\r
\r
/*-----------------------------------------------------------*/\r
\r
ldr r0, [r1]\r
/* Move onto the second item in the TCB... */\r
add r1, r1, #4\r
+\r
+ dmb /* Complete outstanding transfers before disabling MPU. */\r
+ ldr r2, =0xe000ed94 /* MPU_CTRL register. */\r
+ ldr r3, [r2] /* Read the value of MPU_CTRL. */\r
+ bic r3, r3, #1 /* r3 = r3 & ~1 i.e. Clear the bit 0 in r3. */\r
+ str r3, [r2] /* Disable MPU. */\r
+\r
/* Region Base Address register. */\r
ldr r2, =0xe000ed9c\r
/* Read 4 sets of MPU registers. */\r
ldmia r1!, {r4-r11}\r
/* Write 4 sets of MPU registers. */\r
stmia r2!, {r4-r11}\r
+\r
+ ldr r2, =0xe000ed94 /* MPU_CTRL register. */\r
+ ldr r3, [r2] /* Read the value of MPU_CTRL. */\r
+ orr r3, r3, #1 /* r3 = r3 | 1 i.e. Set the bit 0 in r3. */\r
+ str r3, [r2] /* Enable MPU. */\r
+ dsb /* Force memory writes before continuing. */\r
+\r
/* Pop the registers that are not automatically saved on exception entry. */\r
ldmia r0!, {r3-r11, r14}\r
msr control, r3\r
\r
/*-----------------------------------------------------------*/\r
\r
-vPortStartFirstTask\r
+vPortStartFirstTask:\r
/* Use the NVIC offset register to locate the stack. */\r
ldr r0, =0xE000ED08\r
ldr r0, [r0]\r
\r
/*-----------------------------------------------------------*/\r
\r
-vPortRestoreContextOfFirstTask\r
+vPortRestoreContextOfFirstTask:\r
/* Use the NVIC offset register to locate the stack. */\r
ldr r0, =0xE000ED08\r
ldr r0, [r0]\r
ldr r0, [r1]\r
/* Move onto the second item in the TCB... */\r
add r1, r1, #4\r
+\r
+ dmb /* Complete outstanding transfers before disabling MPU. */\r
+ ldr r2, =0xe000ed94 /* MPU_CTRL register. */\r
+ ldr r3, [r2] /* Read the value of MPU_CTRL. */\r
+ bic r3, r3, #1 /* r3 = r3 & ~1 i.e. Clear the bit 0 in r3. */\r
+ str r3, [r2] /* Disable MPU. */\r
+\r
/* Region Base Address register. */\r
ldr r2, =0xe000ed9c\r
/* Read 4 sets of MPU registers. */\r
ldmia r1!, {r4-r11}\r
/* Write 4 sets of MPU registers. */\r
stmia r2!, {r4-r11}\r
+\r
+ ldr r2, =0xe000ed94 /* MPU_CTRL register. */\r
+ ldr r3, [r2] /* Read the value of MPU_CTRL. */\r
+ orr r3, r3, #1 /* r3 = r3 | 1 i.e. Set the bit 0 in r3. */\r
+ str r3, [r2] /* Enable MPU. */\r
+ dsb /* Force memory writes before continuing. */\r
+\r
/* Pop the registers that are not automatically saved on exception entry. */\r
ldmia r0!, {r3-r11, r14}\r
msr control, r3\r
\r
/*-----------------------------------------------------------*/\r
\r
-vPortEnableVFP\r
+vPortEnableVFP:\r
/* The FPU enable bits are in the CPACR. */\r
ldr.w r0, =0xE000ED88\r
ldr r1, [r0]\r
\r
/*-----------------------------------------------------------*/\r
\r
-xPortRaisePrivilege\r
- mrs r0, control\r
- /* Is the task running privileged? */\r
- tst r0, #1\r
- itte ne\r
- /* CONTROL[0]!=0, return false. */\r
- movne r0, #0\r
- /* Switch to privileged. */\r
- svcne 2 /* 2 == portSVC_RAISE_PRIVILEGE */\r
- /* CONTROL[0]==0, return true. */\r
- moveq r0, #1\r
- bx lr\r
+xIsPrivileged:\r
+ mrs r0, control /* r0 = CONTROL. */\r
+ tst r0, #1 /* Perform r0 & 1 (bitwise AND) and update the conditions flag. */\r
+ ite ne\r
+ movne r0, #0 /* CONTROL[0]!=0. Return false to indicate that the processor is not privileged. */\r
+ moveq r0, #1 /* CONTROL[0]==0. Return true to indicate that the processor is privileged. */\r
+ bx lr /* Return. */\r
+/*-----------------------------------------------------------*/\r
\r
+vResetPrivilege:\r
+ mrs r0, control /* r0 = CONTROL. */\r
+ orr r0, r0, #1 /* r0 = r0 | 1. */\r
+ msr control, r0 /* CONTROL = r0. */\r
+ bx lr /* Return to the caller. */\r
+/*-----------------------------------------------------------*/\r
\r
END\r
-\r
projects / freertos / blobdiff