/*\r
- FreeRTOS V7.4.2 - Copyright (C) 2013 Real Time Engineers Ltd.\r
+ FreeRTOS V8.1.2 - Copyright (C) 2014 Real Time Engineers Ltd. \r
+ All rights reserved\r
\r
- FEATURES AND PORTS ARE ADDED TO FREERTOS ALL THE TIME. PLEASE VISIT\r
- http://www.FreeRTOS.org TO ENSURE YOU ARE USING THE LATEST VERSION.\r
+ VISIT http://www.FreeRTOS.org TO ENSURE YOU ARE USING THE LATEST VERSION.\r
\r
***************************************************************************\r
* *\r
- * FreeRTOS tutorial books are available in pdf and paperback. *\r
- * Complete, revised, and edited pdf reference manuals are also *\r
- * available. *\r
+ * FreeRTOS provides completely free yet professionally developed, *\r
+ * robust, strictly quality controlled, supported, and cross *\r
+ * platform software that has become a de facto standard. *\r
* *\r
- * Purchasing FreeRTOS documentation will not only help you, by *\r
- * ensuring you get running as quickly as possible and with an *\r
- * in-depth knowledge of how to use FreeRTOS, it will also help *\r
- * the FreeRTOS project to continue with its mission of providing *\r
- * professional grade, cross platform, de facto standard solutions *\r
- * for microcontrollers - completely free of charge! *\r
+ * Help yourself get started quickly and support the FreeRTOS *\r
+ * project by purchasing a FreeRTOS tutorial book, reference *\r
+ * manual, or both from: http://www.FreeRTOS.org/Documentation *\r
* *\r
- * >>> See http://www.FreeRTOS.org/Documentation for details. <<< *\r
- * *\r
- * Thank you for using FreeRTOS, and thank you for your support! *\r
+ * Thank you! *\r
* *\r
***************************************************************************\r
\r
-\r
This file is part of the FreeRTOS distribution.\r
\r
FreeRTOS is free software; you can redistribute it and/or modify it under\r
the terms of the GNU General Public License (version 2) as published by the\r
- Free Software Foundation AND MODIFIED BY the FreeRTOS exception.\r
+ Free Software Foundation >>!AND MODIFIED BY!<< the FreeRTOS exception.\r
\r
- >>>>>>NOTE<<<<<< The modification to the GPL is included to allow you to\r
- distribute a combined work that includes FreeRTOS without being obliged to\r
- provide the source code for proprietary components outside of the FreeRTOS\r
- kernel.\r
+ >>! NOTE: The modification to the GPL is included to allow you to !<<\r
+ >>! distribute a combined work that includes FreeRTOS without being !<<\r
+ >>! obliged to provide the source code for proprietary components !<<\r
+ >>! outside of the FreeRTOS kernel. !<<\r
\r
FreeRTOS is distributed in the hope that it will be useful, but WITHOUT ANY\r
WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS\r
- FOR A PARTICULAR PURPOSE. See the GNU General Public License for more\r
- details. You should have received a copy of the GNU General Public License\r
- and the FreeRTOS license exception along with FreeRTOS; if not it can be\r
- viewed here: http://www.freertos.org/a00114.html and also obtained by\r
- writing to Real Time Engineers Ltd., contact details for whom are available\r
- on the FreeRTOS WEB site.\r
+ FOR A PARTICULAR PURPOSE. Full license text is available from the following\r
+ link: http://www.freertos.org/a00114.html\r
\r
1 tab == 4 spaces!\r
\r
* *\r
***************************************************************************\r
\r
-\r
- http://www.FreeRTOS.org - Documentation, books, training, latest versions, \r
+ http://www.FreeRTOS.org - Documentation, books, training, latest versions,\r
license and Real Time Engineers Ltd. contact details.\r
\r
http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products,\r
- including FreeRTOS+Trace - an indispensable productivity tool, and our new\r
- fully thread aware and reentrant UDP/IP stack.\r
-\r
- http://www.OpenRTOS.com - Real Time Engineers ltd license FreeRTOS to High \r
- Integrity Systems, who sell the code with commercial support, \r
- indemnification and middleware, under the OpenRTOS brand.\r
- \r
- http://www.SafeRTOS.com - High Integrity Systems also provide a safety \r
- engineered and independently SIL3 certified version for use in safety and \r
+ including FreeRTOS+Trace - an indispensable productivity tool, a DOS\r
+ compatible FAT file system, and our tiny thread aware UDP/IP stack.\r
+\r
+ http://www.OpenRTOS.com - Real Time Engineers ltd license FreeRTOS to High\r
+ Integrity Systems to sell under the OpenRTOS brand. Low cost OpenRTOS\r
+ licenses offer ticketed support, indemnification and middleware.\r
+\r
+ http://www.SafeRTOS.com - High Integrity Systems also provide a safety\r
+ engineered and independently SIL3 certified version for use in safety and\r
mission critical applications that require provable dependability.\r
+\r
+ 1 tab == 4 spaces!\r
*/\r
\r
/*-----------------------------------------------------------\r
#include "task.h"\r
\r
/* Constants required to setup the tick ISR. */\r
-#define portENABLE_TIMER ( ( unsigned char ) 0x01 )\r
+#define portENABLE_TIMER ( ( uint8_t ) 0x01 )\r
#define portPRESCALE_VALUE 0x00\r
-#define portINTERRUPT_ON_MATCH ( ( unsigned long ) 0x01 )\r
-#define portRESET_COUNT_ON_MATCH ( ( unsigned long ) 0x02 )\r
+#define portINTERRUPT_ON_MATCH ( ( uint32_t ) 0x01 )\r
+#define portRESET_COUNT_ON_MATCH ( ( uint32_t ) 0x02 )\r
\r
/* Constants required to setup the initial stack. */\r
-#define portINITIAL_SPSR ( ( portSTACK_TYPE ) 0x1f ) /* System mode, ARM mode, interrupts enabled. */\r
-#define portTHUMB_MODE_BIT ( ( portSTACK_TYPE ) 0x20 )\r
-#define portINSTRUCTION_SIZE ( ( portSTACK_TYPE ) 4 )\r
+#define portINITIAL_SPSR ( ( StackType_t ) 0x1f ) /* System mode, ARM mode, interrupts enabled. */\r
+#define portTHUMB_MODE_BIT ( ( StackType_t ) 0x20 )\r
+#define portINSTRUCTION_SIZE ( ( StackType_t ) 4 )\r
\r
/* Constants required to setup the PIT. */\r
-#define portPIT_CLOCK_DIVISOR ( ( unsigned long ) 16 )\r
-#define portPIT_COUNTER_VALUE ( ( ( configCPU_CLOCK_HZ / portPIT_CLOCK_DIVISOR ) / 1000UL ) * portTICK_RATE_MS )\r
+#define portPIT_CLOCK_DIVISOR ( ( uint32_t ) 16 )\r
+#define portPIT_COUNTER_VALUE ( ( ( configCPU_CLOCK_HZ / portPIT_CLOCK_DIVISOR ) / 1000UL ) * portTICK_PERIOD_MS )\r
\r
/* Constants required to handle interrupts. */\r
-#define portTIMER_MATCH_ISR_BIT ( ( unsigned char ) 0x01 )\r
-#define portCLEAR_VIC_INTERRUPT ( ( unsigned long ) 0 )\r
+#define portTIMER_MATCH_ISR_BIT ( ( uint8_t ) 0x01 )\r
+#define portCLEAR_VIC_INTERRUPT ( ( uint32_t ) 0 )\r
\r
/* Constants required to handle critical sections. */\r
-#define portNO_CRITICAL_NESTING ( ( unsigned long ) 0 )\r
+#define portNO_CRITICAL_NESTING ( ( uint32_t ) 0 )\r
\r
\r
#define portINT_LEVEL_SENSITIVE 0\r
-#define portPIT_ENABLE ( ( unsigned short ) 0x1 << 24 )\r
-#define portPIT_INT_ENABLE ( ( unsigned short ) 0x1 << 25 )\r
+#define portPIT_ENABLE ( ( uint16_t ) 0x1 << 24 )\r
+#define portPIT_INT_ENABLE ( ( uint16_t ) 0x1 << 25 )\r
\r
/* Constants required to setup the VIC for the tick ISR. */\r
-#define portTIMER_VIC_CHANNEL ( ( unsigned long ) 0x0004 )\r
-#define portTIMER_VIC_CHANNEL_BIT ( ( unsigned long ) 0x0010 )\r
-#define portTIMER_VIC_ENABLE ( ( unsigned long ) 0x0020 )\r
+#define portTIMER_VIC_CHANNEL ( ( uint32_t ) 0x0004 )\r
+#define portTIMER_VIC_CHANNEL_BIT ( ( uint32_t ) 0x0010 )\r
+#define portTIMER_VIC_ENABLE ( ( uint32_t ) 0x0020 )\r
\r
/*-----------------------------------------------------------*/\r
\r
/* ulCriticalNesting will get set to zero when the first task starts. It\r
cannot be initialised to 0 as this will cause interrupts to be enabled\r
during the kernel initialisation process. */\r
-unsigned long ulCriticalNesting = ( unsigned long ) 9999;\r
+uint32_t ulCriticalNesting = ( uint32_t ) 9999;\r
\r
/*-----------------------------------------------------------*/\r
\r
*\r
* See header file for description.\r
*/\r
-portSTACK_TYPE *pxPortInitialiseStack( portSTACK_TYPE *pxTopOfStack, pdTASK_CODE pxCode, void *pvParameters )\r
+StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, TaskFunction_t pxCode, void *pvParameters )\r
{\r
-portSTACK_TYPE *pxOriginalTOS;\r
+StackType_t *pxOriginalTOS;\r
\r
pxOriginalTOS = pxTopOfStack;\r
\r
/* First on the stack is the return address - which in this case is the\r
start of the task. The offset is added to make the return address appear\r
as it would within an IRQ ISR. */\r
- *pxTopOfStack = ( portSTACK_TYPE ) pxCode + portINSTRUCTION_SIZE; \r
+ *pxTopOfStack = ( StackType_t ) pxCode + portINSTRUCTION_SIZE; \r
pxTopOfStack--;\r
\r
- *pxTopOfStack = ( portSTACK_TYPE ) 0xaaaaaaaa; /* R14 */\r
+ *pxTopOfStack = ( StackType_t ) 0xaaaaaaaa; /* R14 */\r
pxTopOfStack--; \r
- *pxTopOfStack = ( portSTACK_TYPE ) pxOriginalTOS; /* Stack used when task starts goes in R13. */\r
+ *pxTopOfStack = ( StackType_t ) pxOriginalTOS; /* Stack used when task starts goes in R13. */\r
pxTopOfStack--;\r
- *pxTopOfStack = ( portSTACK_TYPE ) 0x12121212; /* R12 */\r
+ *pxTopOfStack = ( StackType_t ) 0x12121212; /* R12 */\r
pxTopOfStack--; \r
- *pxTopOfStack = ( portSTACK_TYPE ) 0x11111111; /* R11 */\r
+ *pxTopOfStack = ( StackType_t ) 0x11111111; /* R11 */\r
pxTopOfStack--; \r
- *pxTopOfStack = ( portSTACK_TYPE ) 0x10101010; /* R10 */\r
+ *pxTopOfStack = ( StackType_t ) 0x10101010; /* R10 */\r
pxTopOfStack--; \r
- *pxTopOfStack = ( portSTACK_TYPE ) 0x09090909; /* R9 */\r
+ *pxTopOfStack = ( StackType_t ) 0x09090909; /* R9 */\r
pxTopOfStack--; \r
- *pxTopOfStack = ( portSTACK_TYPE ) 0x08080808; /* R8 */\r
+ *pxTopOfStack = ( StackType_t ) 0x08080808; /* R8 */\r
pxTopOfStack--; \r
- *pxTopOfStack = ( portSTACK_TYPE ) 0x07070707; /* R7 */\r
+ *pxTopOfStack = ( StackType_t ) 0x07070707; /* R7 */\r
pxTopOfStack--; \r
- *pxTopOfStack = ( portSTACK_TYPE ) 0x06060606; /* R6 */\r
+ *pxTopOfStack = ( StackType_t ) 0x06060606; /* R6 */\r
pxTopOfStack--; \r
- *pxTopOfStack = ( portSTACK_TYPE ) 0x05050505; /* R5 */\r
+ *pxTopOfStack = ( StackType_t ) 0x05050505; /* R5 */\r
pxTopOfStack--; \r
- *pxTopOfStack = ( portSTACK_TYPE ) 0x04040404; /* R4 */\r
+ *pxTopOfStack = ( StackType_t ) 0x04040404; /* R4 */\r
pxTopOfStack--; \r
- *pxTopOfStack = ( portSTACK_TYPE ) 0x03030303; /* R3 */\r
+ *pxTopOfStack = ( StackType_t ) 0x03030303; /* R3 */\r
pxTopOfStack--; \r
- *pxTopOfStack = ( portSTACK_TYPE ) 0x02020202; /* R2 */\r
+ *pxTopOfStack = ( StackType_t ) 0x02020202; /* R2 */\r
pxTopOfStack--; \r
- *pxTopOfStack = ( portSTACK_TYPE ) 0x01010101; /* R1 */\r
+ *pxTopOfStack = ( StackType_t ) 0x01010101; /* R1 */\r
pxTopOfStack--; \r
\r
/* When the task starts is will expect to find the function parameter in\r
R0. */\r
- *pxTopOfStack = ( portSTACK_TYPE ) pvParameters; /* R0 */\r
+ *pxTopOfStack = ( StackType_t ) pvParameters; /* R0 */\r
pxTopOfStack--;\r
\r
/* The status register is set for system mode, with interrupts enabled. */\r
- *pxTopOfStack = ( portSTACK_TYPE ) portINITIAL_SPSR;\r
+ *pxTopOfStack = ( StackType_t ) portINITIAL_SPSR;\r
\r
- if( ( ( unsigned long ) pxCode & 0x01UL ) != 0x00UL )\r
+ if( ( ( uint32_t ) pxCode & 0x01UL ) != 0x00UL )\r
{\r
/* We want the task to start in thumb mode. */\r
*pxTopOfStack |= portTHUMB_MODE_BIT;\r
}\r
/*-----------------------------------------------------------*/\r
\r
-portBASE_TYPE xPortStartScheduler( void )\r
+BaseType_t xPortStartScheduler( void )\r
{\r
extern void vPortStartFirstTask( void );\r
\r
/* Increment the tick count - which may wake some tasks but as the\r
preemptive scheduler is not being used any woken task is not given\r
processor time no matter what its priority. */\r
- vTaskIncrementTick();\r
+ xTaskIncrementTick();\r
\r
/* Ready for the next interrupt. */\r
T0IR = portTIMER_MATCH_ISR_BIT;\r
void vPortPreemptiveTick( void )\r
{\r
/* Increment the tick counter. */\r
- vTaskIncrementTick();\r
- \r
- /* The new tick value might unblock a task. Ensure the highest task that\r
- is ready to execute is the task that will execute when the tick ISR\r
- exits. */\r
- vTaskSwitchContext();\r
+ if( xTaskIncrementTick() != pdFALSE )\r
+ { \r
+ /* The new tick value might unblock a task. Ensure the highest task that\r
+ is ready to execute is the task that will execute when the tick ISR\r
+ exits. */\r
+ vTaskSwitchContext();\r
+ }\r
\r
/* Ready for the next interrupt. */\r
T0IR = portTIMER_MATCH_ISR_BIT;\r
\r
static void prvSetupTimerInterrupt( void )\r
{\r
-unsigned long ulCompareMatch;\r
+uint32_t ulCompareMatch;\r
\r
/* A 1ms tick does not require the use of the timer prescale. This is\r
defaulted to zero but can be used if necessary. */\r
{ \r
extern void ( vPortPreemptiveTickEntry )( void );\r
\r
- VICVectAddr0 = ( unsigned long ) vPortPreemptiveTickEntry;\r
+ VICVectAddr0 = ( uint32_t ) vPortPreemptiveTickEntry;\r
}\r
#else\r
{\r
extern void ( vNonPreemptiveTick )( void );\r
\r
- VICVectAddr0 = ( long ) vPortNonPreemptiveTick;\r
+ VICVectAddr0 = ( int32_t ) vPortNonPreemptiveTick;\r
}\r
#endif\r
\r
projects / freertos / blobdiff