/*\r
- FreeRTOS V8.1.2 - Copyright (C) 2014 Real Time Engineers Ltd.\r
+ FreeRTOS V9.0.0rc2 - Copyright (C) 2016 Real Time Engineers Ltd.\r
All rights reserved\r
\r
VISIT http://www.FreeRTOS.org TO ENSURE YOU ARE USING THE LATEST VERSION.\r
\r
- ***************************************************************************\r
- * *\r
- * FreeRTOS provides completely free yet professionally developed, *\r
- * robust, strictly quality controlled, supported, and cross *\r
- * platform software that has become a de facto standard. *\r
- * *\r
- * Help yourself get started quickly and support the FreeRTOS *\r
- * project by purchasing a FreeRTOS tutorial book, reference *\r
- * manual, or both from: http://www.FreeRTOS.org/Documentation *\r
- * *\r
- * Thank you! *\r
- * *\r
- ***************************************************************************\r
-\r
This file is part of the FreeRTOS distribution.\r
\r
FreeRTOS is free software; you can redistribute it and/or modify it under\r
the terms of the GNU General Public License (version 2) as published by the\r
- Free Software Foundation >>!AND MODIFIED BY!<< the FreeRTOS exception.\r
+ Free Software Foundation >>>> AND MODIFIED BY <<<< the FreeRTOS exception.\r
\r
+ ***************************************************************************\r
>>! NOTE: The modification to the GPL is included to allow you to !<<\r
>>! distribute a combined work that includes FreeRTOS without being !<<\r
>>! obliged to provide the source code for proprietary components !<<\r
>>! outside of the FreeRTOS kernel. !<<\r
+ ***************************************************************************\r
\r
FreeRTOS is distributed in the hope that it will be useful, but WITHOUT ANY\r
WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS\r
- FOR A PARTICULAR PURPOSE. Full license text is available from the following\r
+ FOR A PARTICULAR PURPOSE. Full license text is available on the following\r
link: http://www.freertos.org/a00114.html\r
\r
- 1 tab == 4 spaces!\r
-\r
***************************************************************************\r
* *\r
- * Having a problem? Start by reading the FAQ "My application does *\r
- * not run, what could be wrong?" *\r
+ * FreeRTOS provides completely free yet professionally developed, *\r
+ * robust, strictly quality controlled, supported, and cross *\r
+ * platform software that is more than just the market leader, it *\r
+ * is the industry's de facto standard. *\r
* *\r
- * http://www.FreeRTOS.org/FAQHelp.html *\r
+ * Help yourself get started quickly while simultaneously helping *\r
+ * to support the FreeRTOS project by purchasing a FreeRTOS *\r
+ * tutorial book, reference manual, or both: *\r
+ * http://www.FreeRTOS.org/Documentation *\r
* *\r
***************************************************************************\r
\r
- http://www.FreeRTOS.org - Documentation, books, training, latest versions,\r
- license and Real Time Engineers Ltd. contact details.\r
+ http://www.FreeRTOS.org/FAQHelp.html - Having a problem? Start by reading\r
+ the FAQ page "My application does not run, what could be wrong?". Have you\r
+ defined configASSERT()?\r
+\r
+ http://www.FreeRTOS.org/support - In return for receiving this top quality\r
+ embedded software for free we request you assist our global community by\r
+ participating in the support forum.\r
+\r
+ http://www.FreeRTOS.org/training - Investing in training allows your team to\r
+ be as productive as possible as early as possible. Now you can receive\r
+ FreeRTOS training directly from Richard Barry, CEO of Real Time Engineers\r
+ Ltd, and the world's leading authority on the world's leading RTOS.\r
\r
http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products,\r
including FreeRTOS+Trace - an indispensable productivity tool, a DOS\r
compatible FAT file system, and our tiny thread aware UDP/IP stack.\r
\r
- http://www.OpenRTOS.com - Real Time Engineers ltd license FreeRTOS to High\r
- Integrity Systems to sell under the OpenRTOS brand. Low cost OpenRTOS\r
- licenses offer ticketed support, indemnification and middleware.\r
+ http://www.FreeRTOS.org/labs - Where new FreeRTOS products go to incubate.\r
+ Come and try FreeRTOS+TCP, our new open source TCP/IP stack for FreeRTOS.\r
+\r
+ http://www.OpenRTOS.com - Real Time Engineers ltd. license FreeRTOS to High\r
+ Integrity Systems ltd. to sell under the OpenRTOS brand. Low cost OpenRTOS\r
+ licenses offer ticketed support, indemnification and commercial middleware.\r
\r
http://www.SafeRTOS.com - High Integrity Systems also provide a safety\r
engineered and independently SIL3 certified version for use in safety and\r
\r
#include "FreeRTOSConfig.h"\r
\r
-#define portCONTEXT_SIZE 160\r
-#define portEPC_STACK_LOCATION 152\r
-#define portSTATUS_STACK_LOCATION 156\r
+#define portCONTEXT_SIZE 160\r
+#define portEPC_STACK_LOCATION 152\r
+#define portSTATUS_STACK_LOCATION 156\r
+#define portFPCSR_STACK_LOCATION 0\r
+#define portTASK_HAS_FPU_STACK_LOCATION 0\r
+#define portFPU_CONTEXT_SIZE 264\r
+\r
+/******************************************************************/\r
+.macro portSAVE_FPU_REGS offset, base\r
+ /* Macro to assist with saving just the FPU registers to the\r
+ * specified address and base offset,\r
+ * offset is a constant, base is the base pointer register */\r
+\r
+ sdc1 $f31, \offset + 248(\base)\r
+ sdc1 $f30, \offset + 240(\base)\r
+ sdc1 $f29, \offset + 232(\base)\r
+ sdc1 $f28, \offset + 224(\base)\r
+ sdc1 $f27, \offset + 216(\base)\r
+ sdc1 $f26, \offset + 208(\base)\r
+ sdc1 $f25, \offset + 200(\base)\r
+ sdc1 $f24, \offset + 192(\base)\r
+ sdc1 $f23, \offset + 184(\base)\r
+ sdc1 $f22, \offset + 176(\base)\r
+ sdc1 $f21, \offset + 168(\base)\r
+ sdc1 $f20, \offset + 160(\base)\r
+ sdc1 $f19, \offset + 152(\base)\r
+ sdc1 $f18, \offset + 144(\base)\r
+ sdc1 $f17, \offset + 136(\base)\r
+ sdc1 $f16, \offset + 128(\base)\r
+ sdc1 $f15, \offset + 120(\base)\r
+ sdc1 $f14, \offset + 112(\base)\r
+ sdc1 $f13, \offset + 104(\base)\r
+ sdc1 $f12, \offset + 96(\base)\r
+ sdc1 $f11, \offset + 88(\base)\r
+ sdc1 $f10, \offset + 80(\base)\r
+ sdc1 $f9, \offset + 72(\base)\r
+ sdc1 $f8, \offset + 64(\base)\r
+ sdc1 $f7, \offset + 56(\base)\r
+ sdc1 $f6, \offset + 48(\base)\r
+ sdc1 $f5, \offset + 40(\base)\r
+ sdc1 $f4, \offset + 32(\base)\r
+ sdc1 $f3, \offset + 24(\base)\r
+ sdc1 $f2, \offset + 16(\base)\r
+ sdc1 $f1, \offset + 8(\base)\r
+ sdc1 $f0, \offset + 0(\base)\r
+\r
+ .endm\r
+\r
+/******************************************************************/\r
+.macro portLOAD_FPU_REGS offset, base\r
+ /* Macro to assist with loading just the FPU registers from the\r
+ * specified address and base offset, offset is a constant,\r
+ * base is the base pointer register */\r
+\r
+ ldc1 $f0, \offset + 0(\base)\r
+ ldc1 $f1, \offset + 8(\base)\r
+ ldc1 $f2, \offset + 16(\base)\r
+ ldc1 $f3, \offset + 24(\base)\r
+ ldc1 $f4, \offset + 32(\base)\r
+ ldc1 $f5, \offset + 40(\base)\r
+ ldc1 $f6, \offset + 48(\base)\r
+ ldc1 $f7, \offset + 56(\base)\r
+ ldc1 $f8, \offset + 64(\base)\r
+ ldc1 $f9, \offset + 72(\base)\r
+ ldc1 $f10, \offset + 80(\base)\r
+ ldc1 $f11, \offset + 88(\base)\r
+ ldc1 $f12, \offset + 96(\base)\r
+ ldc1 $f13, \offset + 104(\base)\r
+ ldc1 $f14, \offset + 112(\base)\r
+ ldc1 $f15, \offset + 120(\base)\r
+ ldc1 $f16, \offset + 128(\base)\r
+ ldc1 $f17, \offset + 136(\base)\r
+ ldc1 $f18, \offset + 144(\base)\r
+ ldc1 $f19, \offset + 152(\base)\r
+ ldc1 $f20, \offset + 160(\base)\r
+ ldc1 $f21, \offset + 168(\base)\r
+ ldc1 $f22, \offset + 176(\base)\r
+ ldc1 $f23, \offset + 184(\base)\r
+ ldc1 $f24, \offset + 192(\base)\r
+ ldc1 $f25, \offset + 200(\base)\r
+ ldc1 $f26, \offset + 208(\base)\r
+ ldc1 $f27, \offset + 216(\base)\r
+ ldc1 $f28, \offset + 224(\base)\r
+ ldc1 $f29, \offset + 232(\base)\r
+ ldc1 $f30, \offset + 240(\base)\r
+ ldc1 $f31, \offset + 248(\base)\r
+\r
+ .endm\r
\r
/******************************************************************/\r
.macro portSAVE_CONTEXT\r
captured. */\r
mfc0 k0, _CP0_CAUSE\r
addiu sp, sp, -portCONTEXT_SIZE\r
+\r
+ #if ( __mips_hard_float == 1 ) && ( configUSE_TASK_FPU_SUPPORT == 1 )\r
+ /* Test if we are already using the system stack. Only tasks may use the\r
+ FPU so if we are already in a nested interrupt then the FPU context does\r
+ not require saving. */\r
+ la k1, uxInterruptNesting\r
+ lw k1, 0(k1)\r
+ bne k1, zero, 2f\r
+ nop\r
+\r
+ /* Test if the current task needs the FPU context saving. */\r
+ la k1, ulTaskHasFPUContext\r
+ lw k1, 0(k1)\r
+ beq k1, zero, 1f\r
+ nop\r
+\r
+ /* Adjust the stack to account for the additional FPU context.*/\r
+ addiu sp, sp, -portFPU_CONTEXT_SIZE\r
+\r
+ 1:\r
+ /* Save the ulTaskHasFPUContext flag. */\r
+ sw k1, portTASK_HAS_FPU_STACK_LOCATION(sp)\r
+\r
+ 2:\r
+ #endif\r
+\r
mfc0 k1, _CP0_STATUS\r
\r
- /* Also save s6 and s5 so they can be used. Any nesting interrupts should\r
- maintain the values of these registers across the ISR. */\r
+ /* Also save s7, s6 and s5 so they can be used. Any nesting interrupts\r
+ should maintain the values of these registers across the ISR. */\r
+ sw s7, 48(sp)\r
sw s6, 44(sp)\r
sw s5, 40(sp)\r
sw k1, portSTATUS_STACK_LOCATION(sp)\r
mflo s6, $ac0\r
sw s6, 8(s5)\r
\r
+ /* Save the FPU context if the nesting count was zero. */\r
+ #if ( __mips_hard_float == 1 ) && ( configUSE_TASK_FPU_SUPPORT == 1 )\r
+ la s6, uxInterruptNesting\r
+ lw s6, 0(s6)\r
+ addiu s6, s6, -1\r
+ bne s6, zero, 1f\r
+ nop\r
+\r
+ /* Test if the current task needs the FPU context saving. */\r
+ lw s6, portTASK_HAS_FPU_STACK_LOCATION(s5)\r
+ beq s6, zero, 1f\r
+ nop\r
+\r
+ /* Save the FPU registers. */\r
+ portSAVE_FPU_REGS ( portCONTEXT_SIZE + 8 ), s5\r
+\r
+ /* Save the FPU status register */\r
+ cfc1 s6, $f31\r
+ sw s6, (portCONTEXT_SIZE + portFPCSR_STACK_LOCATION)(s5)\r
+\r
+ 1:\r
+ #endif\r
+\r
/* Update the task stack pointer value if nesting is zero. */\r
la s6, uxInterruptNesting\r
lw s6, (s6)\r
la s6, uxSavedTaskStackPointer\r
lw s5, (s6)\r
\r
+ #if ( __mips_hard_float == 1 ) && ( configUSE_TASK_FPU_SUPPORT == 1 )\r
+ /* Restore the FPU context if required. */\r
+ lw s6, portTASK_HAS_FPU_STACK_LOCATION(s5)\r
+ beq s6, zero, 1f\r
+ nop\r
+\r
+ /* Restore the FPU registers. */\r
+ portLOAD_FPU_REGS ( portCONTEXT_SIZE + 8 ), s5\r
+\r
+ /* Restore the FPU status register. */\r
+ lw s6, ( portCONTEXT_SIZE + portFPCSR_STACK_LOCATION )(s5)\r
+ ctc1 s6, $f31\r
+ #endif\r
+\r
+1:\r
+\r
/* Restore the context. */\r
-1: lw s6, 128(s5)\r
+ lw s6, 128(s5)\r
mthi s6, $ac1\r
lw s6, 124(s5)\r
mtlo s6, $ac1\r
lw s6, 144(s5)\r
mthi s6, $ac3\r
lw s6, 140(s5)\r
- mtlo s6, $ac3\r
+ mtlo s6, $ac3\r
\r
/* Restore DSPControl. */\r
lw s6, 148(s5)\r
\r
/* s6 is loaded as it was used as a scratch register and therefore saved\r
as part of the interrupt context. */\r
+ lw s7, 48(s5)\r
lw s6, 44(s5)\r
lw v0, 52(s5)\r
lw v1, 56(s5)\r
addiu k1, k1, -1\r
sw k1, 0(k0)\r
\r
- lw k0, portSTATUS_STACK_LOCATION(s5)\r
- lw k1, portEPC_STACK_LOCATION(s5)\r
+ #if ( __mips_hard_float == 1 ) && ( configUSE_TASK_FPU_SUPPORT == 1 )\r
+ /* If the nesting count is now zero then the FPU context may be restored. */\r
+ bne k1, zero, 1f\r
+ nop\r
+\r
+ /* Restore the value of ulTaskHasFPUContext */\r
+ la k0, ulTaskHasFPUContext\r
+ lw k1, 0(s5)\r
+ sw k1, 0(k0)\r
+\r
+ /* If the task does not have an FPU context then adjust the stack normally. */\r
+ beq k1, zero, 1f\r
+ nop\r
+\r
+ /* Restore the STATUS and EPC registers */\r
+ lw k0, portSTATUS_STACK_LOCATION(s5)\r
+ lw k1, portEPC_STACK_LOCATION(s5)\r
+\r
+ /* Leave the stack in its original state. First load sp from s5, then\r
+ restore s5 from the stack. */\r
+ add sp, zero, s5\r
+ lw s5, 40(sp)\r
+\r
+ /* Adjust the stack pointer to remove the FPU context */\r
+ addiu sp, sp, portFPU_CONTEXT_SIZE\r
+ beq zero, zero, 2f\r
+ nop\r
+\r
+ 1: /* Restore the STATUS and EPC registers */\r
+ lw k0, portSTATUS_STACK_LOCATION(s5)\r
+ lw k1, portEPC_STACK_LOCATION(s5)\r
+\r
+ /* Leave the stack in its original state. First load sp from s5, then\r
+ restore s5 from the stack. */\r
+ add sp, zero, s5\r
+ lw s5, 40(sp)\r
+\r
+ 2: /* Adjust the stack pointer */\r
+ addiu sp, sp, portCONTEXT_SIZE\r
+\r
+ #else\r
+\r
+ /* Restore the frame when there is no hardware FP support. */\r
+ lw k0, portSTATUS_STACK_LOCATION(s5)\r
+ lw k1, portEPC_STACK_LOCATION(s5)\r
+\r
+ /* Leave the stack in its original state. First load sp from s5, then\r
+ restore s5 from the stack. */\r
+ add sp, zero, s5\r
+ lw s5, 40(sp)\r
+\r
+ addiu sp, sp, portCONTEXT_SIZE\r
\r
- /* Leave the stack in its original state. First load sp from s5, then\r
- restore s5 from the stack. */\r
- add sp, zero, s5\r
- lw s5, 40(sp)\r
- addiu sp, sp, portCONTEXT_SIZE\r
+ #endif // ( __mips_hard_float == 1 ) && ( configUSE_TASK_FPU_SUPPORT == 1 )\r
\r
mtc0 k0, _CP0_STATUS\r
mtc0 k1, _CP0_EPC\r
projects / freertos / blobdiff