/*\r
- FreeRTOS V7.4.0 - Copyright (C) 2013 Real Time Engineers Ltd.\r
-\r
- FEATURES AND PORTS ARE ADDED TO FREERTOS ALL THE TIME. PLEASE VISIT\r
- http://www.FreeRTOS.org TO ENSURE YOU ARE USING THE LATEST VERSION.\r
-\r
- ***************************************************************************\r
- * *\r
- * FreeRTOS tutorial books are available in pdf and paperback. *\r
- * Complete, revised, and edited pdf reference manuals are also *\r
- * available. *\r
- * *\r
- * Purchasing FreeRTOS documentation will not only help you, by *\r
- * ensuring you get running as quickly as possible and with an *\r
- * in-depth knowledge of how to use FreeRTOS, it will also help *\r
- * the FreeRTOS project to continue with its mission of providing *\r
- * professional grade, cross platform, de facto standard solutions *\r
- * for microcontrollers - completely free of charge! *\r
- * *\r
- * >>> See http://www.FreeRTOS.org/Documentation for details. <<< *\r
- * *\r
- * Thank you for using FreeRTOS, and thank you for your support! *\r
- * *\r
- ***************************************************************************\r
-\r
-\r
- This file is part of the FreeRTOS distribution.\r
-\r
- FreeRTOS is free software; you can redistribute it and/or modify it under\r
- the terms of the GNU General Public License (version 2) as published by the\r
- Free Software Foundation AND MODIFIED BY the FreeRTOS exception.\r
-\r
- >>>>>>NOTE<<<<<< The modification to the GPL is included to allow you to\r
- distribute a combined work that includes FreeRTOS without being obliged to\r
- provide the source code for proprietary components outside of the FreeRTOS\r
- kernel.\r
-\r
- FreeRTOS is distributed in the hope that it will be useful, but WITHOUT ANY\r
- WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS\r
- FOR A PARTICULAR PURPOSE. See the GNU General Public License for more\r
- details. You should have received a copy of the GNU General Public License\r
- and the FreeRTOS license exception along with FreeRTOS; if not itcan be\r
- viewed here: http://www.freertos.org/a00114.html and also obtained by\r
- writing to Real Time Engineers Ltd., contact details for whom are available\r
- on the FreeRTOS WEB site.\r
-\r
- 1 tab == 4 spaces!\r
-\r
- ***************************************************************************\r
- * *\r
- * Having a problem? Start by reading the FAQ "My application does *\r
- * not run, what could be wrong?" *\r
- * *\r
- * http://www.FreeRTOS.org/FAQHelp.html *\r
- * *\r
- ***************************************************************************\r
-\r
-\r
- http://www.FreeRTOS.org - Documentation, books, training, latest versions, \r
- license and Real Time Engineers Ltd. contact details.\r
-\r
- http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products,\r
- including FreeRTOS+Trace - an indispensable productivity tool, and our new\r
- fully thread aware and reentrant UDP/IP stack.\r
-\r
- http://www.OpenRTOS.com - Real Time Engineers ltd license FreeRTOS to High \r
- Integrity Systems, who sell the code with commercial support, \r
- indemnification and middleware, under the OpenRTOS brand.\r
- \r
- http://www.SafeRTOS.com - High Integrity Systems also provide a safety \r
- engineered and independently SIL3 certified version for use in safety and \r
- mission critical applications that require provable dependability.\r
-*/\r
+ * FreeRTOS Kernel V10.2.1\r
+ * Copyright (C) 2019 Amazon.com, Inc. or its affiliates. All Rights Reserved.\r
+ *\r
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of\r
+ * this software and associated documentation files (the "Software"), to deal in\r
+ * the Software without restriction, including without limitation the rights to\r
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of\r
+ * the Software, and to permit persons to whom the Software is furnished to do so,\r
+ * subject to the following conditions:\r
+ *\r
+ * The above copyright notice and this permission notice shall be included in all\r
+ * copies or substantial portions of the Software.\r
+ *\r
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR\r
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS\r
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR\r
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER\r
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN\r
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.\r
+ *\r
+ * http://www.FreeRTOS.org\r
+ * http://aws.amazon.com/freertos\r
+ *\r
+ * 1 tab == 4 spaces!\r
+ */\r
\r
/*-----------------------------------------------------------\r
* Implementation of functions defined in portable.h for the ARM CM4F port.\r
\r
#ifndef configSYSTICK_CLOCK_HZ\r
#define configSYSTICK_CLOCK_HZ configCPU_CLOCK_HZ\r
+ /* Ensure the SysTick is clocked at the same frequency as the core. */\r
+ #define portNVIC_SYSTICK_CLK_BIT ( 1UL << 2UL )\r
+#else\r
+ /* The way the SysTick is clocked is not modified in case it is not the same\r
+ as the core. */\r
+ #define portNVIC_SYSTICK_CLK_BIT ( 0 )\r
#endif\r
\r
-/* The __weak attribute does not work as you might expect with the Keil tools\r
-so the configOVERRIDE_DEFAULT_TICK_CONFIGURATION constant must be set to 1 if\r
-the application writer wants to provide their own implementation of\r
-vPortSetupTimerInterrupt(). Ensure configOVERRIDE_DEFAULT_TICK_CONFIGURATION\r
-is defined. */\r
+/* Legacy macro for backward compatibility only. This macro used to be used to\r
+replace the function that configures the clock used to generate the tick\r
+interrupt (prvSetupTimerInterrupt()), but now the function is declared weak so\r
+the application writer can override it by simply defining a function of the\r
+same name (vApplicationSetupTickInterrupt()). */\r
#ifndef configOVERRIDE_DEFAULT_TICK_CONFIGURATION\r
#define configOVERRIDE_DEFAULT_TICK_CONFIGURATION 0\r
#endif\r
\r
/* Constants required to manipulate the core. Registers first... */\r
-#define portNVIC_SYSTICK_CTRL_REG ( * ( ( volatile unsigned long * ) 0xe000e010 ) )\r
-#define portNVIC_SYSTICK_LOAD_REG ( * ( ( volatile unsigned long * ) 0xe000e014 ) )\r
-#define portNVIC_SYSTICK_CURRENT_VALUE_REG ( * ( ( volatile unsigned long * ) 0xe000e018 ) )\r
-#define portNVIC_INT_CTRL_REG ( * ( ( volatile unsigned long * ) 0xe000ed04 ) )\r
-#define portNVIC_SYSPRI2_REG ( * ( ( volatile unsigned long * ) 0xe000ed20 ) )\r
+#define portNVIC_SYSTICK_CTRL_REG ( * ( ( volatile uint32_t * ) 0xe000e010 ) )\r
+#define portNVIC_SYSTICK_LOAD_REG ( * ( ( volatile uint32_t * ) 0xe000e014 ) )\r
+#define portNVIC_SYSTICK_CURRENT_VALUE_REG ( * ( ( volatile uint32_t * ) 0xe000e018 ) )\r
+#define portNVIC_SYSPRI2_REG ( * ( ( volatile uint32_t * ) 0xe000ed20 ) )\r
/* ...then bits in the registers. */\r
-#define portNVIC_SYSTICK_CLK_BIT ( 1UL << 2UL )\r
#define portNVIC_SYSTICK_INT_BIT ( 1UL << 1UL )\r
#define portNVIC_SYSTICK_ENABLE_BIT ( 1UL << 0UL )\r
#define portNVIC_SYSTICK_COUNT_FLAG_BIT ( 1UL << 16UL )\r
-#define portNVIC_PENDSVSET_BIT ( 1UL << 28UL )\r
#define portNVIC_PENDSVCLEAR_BIT ( 1UL << 27UL )\r
#define portNVIC_PEND_SYSTICK_CLEAR_BIT ( 1UL << 25UL )\r
\r
-#define portNVIC_PENDSV_PRI ( ( ( unsigned long ) configKERNEL_INTERRUPT_PRIORITY ) << 16 )\r
-#define portNVIC_SYSTICK_PRI ( ( ( unsigned long ) configKERNEL_INTERRUPT_PRIORITY ) << 24 )\r
+/* Constants used to detect a Cortex-M7 r0p1 core, which should use the ARM_CM7\r
+r0p1 port. */\r
+#define portCPUID ( * ( ( volatile uint32_t * ) 0xE000ed00 ) )\r
+#define portCORTEX_M7_r0p1_ID ( 0x410FC271UL )\r
+#define portCORTEX_M7_r0p0_ID ( 0x410FC270UL )\r
+\r
+#define portNVIC_PENDSV_PRI ( ( ( uint32_t ) configKERNEL_INTERRUPT_PRIORITY ) << 16UL )\r
+#define portNVIC_SYSTICK_PRI ( ( ( uint32_t ) configKERNEL_INTERRUPT_PRIORITY ) << 24UL )\r
+\r
+/* Constants required to check the validity of an interrupt priority. */\r
+#define portFIRST_USER_INTERRUPT_NUMBER ( 16 )\r
+#define portNVIC_IP_REGISTERS_OFFSET_16 ( 0xE000E3F0 )\r
+#define portAIRCR_REG ( * ( ( volatile uint32_t * ) 0xE000ED0C ) )\r
+#define portMAX_8_BIT_VALUE ( ( uint8_t ) 0xff )\r
+#define portTOP_BIT_OF_BYTE ( ( uint8_t ) 0x80 )\r
+#define portMAX_PRIGROUP_BITS ( ( uint8_t ) 7 )\r
+#define portPRIORITY_GROUP_MASK ( 0x07UL << 8UL )\r
+#define portPRIGROUP_SHIFT ( 8UL )\r
+\r
+/* Masks off all bits but the VECTACTIVE bits in the ICSR register. */\r
+#define portVECTACTIVE_MASK ( 0xFFUL )\r
\r
/* Constants required to manipulate the VFP. */\r
-#define portFPCCR ( ( volatile unsigned long * ) 0xe000ef34 ) /* Floating point context control register. */\r
+#define portFPCCR ( ( volatile uint32_t * ) 0xe000ef34 ) /* Floating point context control register. */\r
#define portASPEN_AND_LSPEN_BITS ( 0x3UL << 30UL )\r
\r
/* Constants required to set up the initial stack. */\r
#define portINITIAL_XPSR ( 0x01000000 )\r
-#define portINITIAL_EXEC_RETURN ( 0xfffffffd )\r
+#define portINITIAL_EXC_RETURN ( 0xfffffffd )\r
\r
-/* Each task maintains its own interrupt status in the critical nesting\r
-variable. */\r
-static unsigned portBASE_TYPE uxCriticalNesting = 0xaaaaaaaa;\r
+/* The systick is a 24-bit counter. */\r
+#define portMAX_24_BIT_NUMBER ( 0xffffffUL )\r
+\r
+/* A fiddle factor to estimate the number of SysTick counts that would have\r
+occurred while the SysTick counter is stopped during tickless idle\r
+calculations. */\r
+#define portMISSED_COUNTS_FACTOR ( 45UL )\r
+\r
+/* For strict compliance with the Cortex-M spec the task start address should\r
+have bit-0 clear, as it is loaded into the PC on exit from an ISR. */\r
+#define portSTART_ADDRESS_MASK ( ( StackType_t ) 0xfffffffeUL )\r
\r
/*\r
* Setup the timer to generate the tick interrupts. The implementation in this\r
* Functions defined in portasm.s to enable the VFP.\r
*/\r
static void prvEnableVFP( void );\r
+\r
+/*\r
+ * Used to catch tasks that attempt to return from their implementing function.\r
+ */\r
+static void prvTaskExitError( void );\r
+\r
/*-----------------------------------------------------------*/\r
\r
+/* Each task maintains its own interrupt status in the critical nesting\r
+variable. */\r
+static UBaseType_t uxCriticalNesting = 0xaaaaaaaa;\r
+\r
/*\r
* The number of SysTick increments that make up one tick period.\r
*/\r
-#if configUSE_TICKLESS_IDLE == 1\r
- static unsigned long ulTimerReloadValueForOneTick = 0;\r
-#endif\r
+#if( configUSE_TICKLESS_IDLE == 1 )\r
+ static uint32_t ulTimerCountsForOneTick = 0;\r
+#endif /* configUSE_TICKLESS_IDLE */\r
\r
/*\r
* The maximum number of tick periods that can be suppressed is limited by the\r
* 24 bit resolution of the SysTick timer.\r
*/\r
-#if configUSE_TICKLESS_IDLE == 1\r
- static unsigned long xMaximumPossibleSuppressedTicks = 0;\r
+#if( configUSE_TICKLESS_IDLE == 1 )\r
+ static uint32_t xMaximumPossibleSuppressedTicks = 0;\r
#endif /* configUSE_TICKLESS_IDLE */\r
\r
/*\r
* Compensate for the CPU cycles that pass while the SysTick is stopped (low\r
* power functionality only.\r
*/\r
-#if configUSE_TICKLESS_IDLE == 1\r
- static unsigned long ulStoppedTimerCompensation = 0;\r
+#if( configUSE_TICKLESS_IDLE == 1 )\r
+ static uint32_t ulStoppedTimerCompensation = 0;\r
#endif /* configUSE_TICKLESS_IDLE */\r
\r
+/*\r
+ * Used by the portASSERT_IF_INTERRUPT_PRIORITY_INVALID() macro to ensure\r
+ * FreeRTOS API functions are not called from interrupts that have been assigned\r
+ * a priority above configMAX_SYSCALL_INTERRUPT_PRIORITY.\r
+ */\r
+#if ( configASSERT_DEFINED == 1 )\r
+ static uint8_t ucMaxSysCallPriority = 0;\r
+ static uint32_t ulMaxPRIGROUPValue = 0;\r
+ static const volatile uint8_t * const pcInterruptPriorityRegisters = ( uint8_t * ) portNVIC_IP_REGISTERS_OFFSET_16;\r
+#endif /* configASSERT_DEFINED */\r
+\r
/*-----------------------------------------------------------*/\r
\r
/*\r
* See header file for description.\r
*/\r
-portSTACK_TYPE *pxPortInitialiseStack( portSTACK_TYPE *pxTopOfStack, pdTASK_CODE pxCode, void *pvParameters )\r
+StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, TaskFunction_t pxCode, void *pvParameters )\r
{\r
/* Simulate the stack frame as it would be created by a context switch\r
interrupt. */\r
\r
*pxTopOfStack = portINITIAL_XPSR; /* xPSR */\r
pxTopOfStack--;\r
- *pxTopOfStack = ( portSTACK_TYPE ) pxCode; /* PC */\r
+ *pxTopOfStack = ( ( StackType_t ) pxCode ) & portSTART_ADDRESS_MASK; /* PC */\r
pxTopOfStack--;\r
- *pxTopOfStack = 0; /* LR */\r
+ *pxTopOfStack = ( StackType_t ) prvTaskExitError; /* LR */\r
\r
/* Save code space by skipping register initialisation. */\r
pxTopOfStack -= 5; /* R12, R3, R2 and R1. */\r
- *pxTopOfStack = ( portSTACK_TYPE ) pvParameters; /* R0 */\r
+ *pxTopOfStack = ( StackType_t ) pvParameters; /* R0 */\r
\r
/* A save method is being used that requires each task to maintain its\r
own exec return value. */\r
pxTopOfStack--;\r
- *pxTopOfStack = portINITIAL_EXEC_RETURN;\r
+ *pxTopOfStack = portINITIAL_EXC_RETURN;\r
\r
pxTopOfStack -= 8; /* R11, R10, R9, R8, R7, R6, R5 and R4. */\r
\r
}\r
/*-----------------------------------------------------------*/\r
\r
+static void prvTaskExitError( void )\r
+{\r
+ /* A function that implements a task must not exit or attempt to return to\r
+ its caller as there is nothing to return to. If a task wants to exit it\r
+ should instead call vTaskDelete( NULL ).\r
+\r
+ Artificially force an assert() to be triggered if configASSERT() is\r
+ defined, then stop here so application writers can catch the error. */\r
+ configASSERT( uxCriticalNesting == ~0UL );\r
+ portDISABLE_INTERRUPTS();\r
+ for( ;; );\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
__asm void vPortSVCHandler( void )\r
{\r
PRESERVE8\r
/* Pop the core registers. */\r
ldmia r0!, {r4-r11, r14}\r
msr psp, r0\r
+ isb\r
mov r0, #0\r
msr basepri, r0\r
bx r14\r
ldr r0, [r0]\r
/* Set the msp back to the start of the stack. */\r
msr msp, r0\r
+ /* Clear the bit that indicates the FPU is in use in case the FPU was used\r
+ before the scheduler was started - which would otherwise result in the\r
+ unnecessary leaving of space in the SVC stack for lazy saving of FPU\r
+ registers. */\r
+ mov r0, #0\r
+ msr control, r0\r
/* Globally enable interrupts. */\r
cpsie i\r
+ cpsie f\r
+ dsb\r
+ isb\r
/* Call SVC to start the first task. */\r
svc 0\r
nop\r
+ nop\r
}\r
/*-----------------------------------------------------------*/\r
\r
/*\r
* See header file for description.\r
*/\r
-portBASE_TYPE xPortStartScheduler( void )\r
+BaseType_t xPortStartScheduler( void )\r
{\r
- /* Make PendSV, CallSV and SysTick the same priroity as the kernel. */\r
+ /* configMAX_SYSCALL_INTERRUPT_PRIORITY must not be set to 0.\r
+ See http://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html */\r
+ configASSERT( configMAX_SYSCALL_INTERRUPT_PRIORITY );\r
+\r
+ /* This port can be used on all revisions of the Cortex-M7 core other than\r
+ the r0p1 parts. r0p1 parts should use the port from the\r
+ /source/portable/GCC/ARM_CM7/r0p1 directory. */\r
+ configASSERT( portCPUID != portCORTEX_M7_r0p1_ID );\r
+ configASSERT( portCPUID != portCORTEX_M7_r0p0_ID );\r
+\r
+ #if( configASSERT_DEFINED == 1 )\r
+ {\r
+ volatile uint32_t ulOriginalPriority;\r
+ volatile uint8_t * const pucFirstUserPriorityRegister = ( uint8_t * ) ( portNVIC_IP_REGISTERS_OFFSET_16 + portFIRST_USER_INTERRUPT_NUMBER );\r
+ volatile uint8_t ucMaxPriorityValue;\r
+\r
+ /* Determine the maximum priority from which ISR safe FreeRTOS API\r
+ functions can be called. ISR safe functions are those that end in\r
+ "FromISR". FreeRTOS maintains separate thread and ISR API functions to\r
+ ensure interrupt entry is as fast and simple as possible.\r
+\r
+ Save the interrupt priority value that is about to be clobbered. */\r
+ ulOriginalPriority = *pucFirstUserPriorityRegister;\r
+\r
+ /* Determine the number of priority bits available. First write to all\r
+ possible bits. */\r
+ *pucFirstUserPriorityRegister = portMAX_8_BIT_VALUE;\r
+\r
+ /* Read the value back to see how many bits stuck. */\r
+ ucMaxPriorityValue = *pucFirstUserPriorityRegister;\r
+\r
+ /* The kernel interrupt priority should be set to the lowest\r
+ priority. */\r
+ configASSERT( ucMaxPriorityValue == ( configKERNEL_INTERRUPT_PRIORITY & ucMaxPriorityValue ) );\r
+\r
+ /* Use the same mask on the maximum system call priority. */\r
+ ucMaxSysCallPriority = configMAX_SYSCALL_INTERRUPT_PRIORITY & ucMaxPriorityValue;\r
+\r
+ /* Calculate the maximum acceptable priority group value for the number\r
+ of bits read back. */\r
+ ulMaxPRIGROUPValue = portMAX_PRIGROUP_BITS;\r
+ while( ( ucMaxPriorityValue & portTOP_BIT_OF_BYTE ) == portTOP_BIT_OF_BYTE )\r
+ {\r
+ ulMaxPRIGROUPValue--;\r
+ ucMaxPriorityValue <<= ( uint8_t ) 0x01;\r
+ }\r
+\r
+ #ifdef __NVIC_PRIO_BITS\r
+ {\r
+ /* Check the CMSIS configuration that defines the number of\r
+ priority bits matches the number of priority bits actually queried\r
+ from the hardware. */\r
+ configASSERT( ( portMAX_PRIGROUP_BITS - ulMaxPRIGROUPValue ) == __NVIC_PRIO_BITS );\r
+ }\r
+ #endif\r
+\r
+ #ifdef configPRIO_BITS\r
+ {\r
+ /* Check the FreeRTOS configuration that defines the number of\r
+ priority bits matches the number of priority bits actually queried\r
+ from the hardware. */\r
+ configASSERT( ( portMAX_PRIGROUP_BITS - ulMaxPRIGROUPValue ) == configPRIO_BITS );\r
+ }\r
+ #endif\r
+\r
+ /* Shift the priority group value back to its position within the AIRCR\r
+ register. */\r
+ ulMaxPRIGROUPValue <<= portPRIGROUP_SHIFT;\r
+ ulMaxPRIGROUPValue &= portPRIORITY_GROUP_MASK;\r
+\r
+ /* Restore the clobbered interrupt priority register to its original\r
+ value. */\r
+ *pucFirstUserPriorityRegister = ulOriginalPriority;\r
+ }\r
+ #endif /* conifgASSERT_DEFINED */\r
+\r
+ /* Make PendSV and SysTick the lowest priority interrupts. */\r
portNVIC_SYSPRI2_REG |= portNVIC_PENDSV_PRI;\r
portNVIC_SYSPRI2_REG |= portNVIC_SYSTICK_PRI;\r
\r
\r
void vPortEndScheduler( void )\r
{\r
- /* It is unlikely that the CM4F port will require this function as there\r
- is nothing to return to. */\r
-}\r
-/*-----------------------------------------------------------*/\r
-\r
-void vPortYieldFromISR( void )\r
-{\r
- /* Set a PendSV to request a context switch. */\r
- portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT;\r
+ /* Not implemented in ports where there is nothing to return to.\r
+ Artificially force an assert. */\r
+ configASSERT( uxCriticalNesting == 1000UL );\r
}\r
/*-----------------------------------------------------------*/\r
\r
{\r
portDISABLE_INTERRUPTS();\r
uxCriticalNesting++;\r
+\r
+ /* This is not the interrupt safe version of the enter critical function so\r
+ assert() if it is being called from an interrupt context. Only API\r
+ functions that end in "FromISR" can be used in an interrupt. Only assert if\r
+ the critical nesting count is 1 to protect against recursive calls if the\r
+ assert function also uses a critical section. */\r
+ if( uxCriticalNesting == 1 )\r
+ {\r
+ configASSERT( ( portNVIC_INT_CTRL_REG & portVECTACTIVE_MASK ) == 0 );\r
+ }\r
}\r
/*-----------------------------------------------------------*/\r
\r
void vPortExitCritical( void )\r
{\r
+ configASSERT( uxCriticalNesting );\r
uxCriticalNesting--;\r
if( uxCriticalNesting == 0 )\r
{\r
PRESERVE8\r
\r
mrs r0, psp\r
-\r
+ isb\r
/* Get the location of the current TCB. */\r
ldr r3, =pxCurrentTCB\r
ldr r2, [r3]\r
/* Save the new top of stack into the first member of the TCB. */\r
str r0, [r2]\r
\r
- stmdb sp!, {r3, r14}\r
+ stmdb sp!, {r0, r3}\r
mov r0, #configMAX_SYSCALL_INTERRUPT_PRIORITY\r
msr basepri, r0\r
+ dsb\r
+ isb\r
bl vTaskSwitchContext\r
mov r0, #0\r
msr basepri, r0\r
- ldmia sp!, {r3, r14}\r
+ ldmia sp!, {r0, r3}\r
\r
/* The first item in pxCurrentTCB is the task top of stack. */\r
ldr r1, [r3]\r
vldmiaeq r0!, {s16-s31}\r
\r
msr psp, r0\r
+ isb\r
+ #ifdef WORKAROUND_PMU_CM001 /* XMC4000 specific errata */\r
+ #if WORKAROUND_PMU_CM001 == 1\r
+ push { r14 }\r
+ pop { pc }\r
+ nop\r
+ #endif\r
+ #endif\r
+\r
bx r14\r
- nop\r
}\r
/*-----------------------------------------------------------*/\r
\r
void xPortSysTickHandler( void )\r
{\r
- #if configUSE_PREEMPTION == 1\r
- {\r
- /* If using preemption, also force a context switch. */\r
- portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT;\r
- }\r
- #endif\r
-\r
- /* Only reset the systick load register if configUSE_TICKLESS_IDLE is set to\r
- 1. If it is set to 0 tickless idle is not being used. If it is set to a\r
- value other than 0 or 1 then a timer other than the SysTick is being used\r
- to generate the tick interrupt. */\r
- #if configUSE_TICKLESS_IDLE == 1\r
- portNVIC_SYSTICK_LOAD_REG = ulTimerReloadValueForOneTick;\r
- #endif\r
-\r
- ( void ) portSET_INTERRUPT_MASK_FROM_ISR();\r
+ /* The SysTick runs at the lowest interrupt priority, so when this interrupt\r
+ executes all interrupts must be unmasked. There is therefore no need to\r
+ save and then restore the interrupt mask value as its value is already\r
+ known - therefore the slightly faster vPortRaiseBASEPRI() function is used\r
+ in place of portSET_INTERRUPT_MASK_FROM_ISR(). */\r
+ vPortRaiseBASEPRI();\r
{\r
- vTaskIncrementTick();\r
+ /* Increment the RTOS tick. */\r
+ if( xTaskIncrementTick() != pdFALSE )\r
+ {\r
+ /* A context switch is required. Context switching is performed in\r
+ the PendSV interrupt. Pend the PendSV interrupt. */\r
+ portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT;\r
+ }\r
}\r
- portCLEAR_INTERRUPT_MASK_FROM_ISR( 0 );\r
+ vPortClearBASEPRIFromISR();\r
}\r
/*-----------------------------------------------------------*/\r
\r
-#if configUSE_TICKLESS_IDLE == 1\r
+#if( configUSE_TICKLESS_IDLE == 1 )\r
\r
- __weak void vPortSuppressTicksAndSleep( portTickType xExpectedIdleTime )\r
+ __weak void vPortSuppressTicksAndSleep( TickType_t xExpectedIdleTime )\r
{\r
- unsigned long ulReloadValue, ulCompleteTickPeriods, ulCompletedSysTickIncrements;\r
- portTickType xModifiableIdleTime;\r
+ uint32_t ulReloadValue, ulCompleteTickPeriods, ulCompletedSysTickDecrements;\r
+ TickType_t xModifiableIdleTime;\r
\r
/* Make sure the SysTick reload value does not overflow the counter. */\r
if( xExpectedIdleTime > xMaximumPossibleSuppressedTicks )\r
xExpectedIdleTime = xMaximumPossibleSuppressedTicks;\r
}\r
\r
+ /* Stop the SysTick momentarily. The time the SysTick is stopped for\r
+ is accounted for as best it can be, but using the tickless mode will\r
+ inevitably result in some tiny drift of the time maintained by the\r
+ kernel with respect to calendar time. */\r
+ portNVIC_SYSTICK_CTRL_REG &= ~portNVIC_SYSTICK_ENABLE_BIT;\r
+\r
/* Calculate the reload value required to wait xExpectedIdleTime\r
tick periods. -1 is used because this code will execute part way\r
- through one of the tick periods, and the fraction of a tick period is\r
- accounted for later. */\r
- ulReloadValue = ( ulTimerReloadValueForOneTick * ( xExpectedIdleTime - 1UL ) );\r
+ through one of the tick periods. */\r
+ ulReloadValue = portNVIC_SYSTICK_CURRENT_VALUE_REG + ( ulTimerCountsForOneTick * ( xExpectedIdleTime - 1UL ) );\r
if( ulReloadValue > ulStoppedTimerCompensation )\r
{\r
ulReloadValue -= ulStoppedTimerCompensation;\r
}\r
\r
- /* Stop the SysTick momentarily. The time the SysTick is stopped for\r
- is accounted for as best it can be, but using the tickless mode will\r
- inevitably result in some tiny drift of the time maintained by the\r
- kernel with respect to calendar time. */\r
- portNVIC_SYSTICK_CTRL_REG = portNVIC_SYSTICK_CLK_BIT | portNVIC_SYSTICK_INT_BIT;\r
-\r
- /* Adjust the reload value to take into account that the current\r
- time slice is already partially complete. */\r
- ulReloadValue += ( portNVIC_SYSTICK_LOAD_REG - ( portNVIC_SYSTICK_LOAD_REG - portNVIC_SYSTICK_CURRENT_VALUE_REG ) );\r
-\r
/* Enter a critical section but don't use the taskENTER_CRITICAL()\r
method as that will mask interrupts that should exit sleep mode. */\r
__disable_irq();\r
- \r
+ __dsb( portSY_FULL_READ_WRITE );\r
+ __isb( portSY_FULL_READ_WRITE );\r
+\r
/* If a context switch is pending or a task is waiting for the scheduler\r
to be unsuspended then abandon the low power entry. */\r
if( eTaskConfirmSleepModeStatus() == eAbortSleep )\r
{\r
+ /* Restart from whatever is left in the count register to complete\r
+ this tick period. */\r
+ portNVIC_SYSTICK_LOAD_REG = portNVIC_SYSTICK_CURRENT_VALUE_REG;\r
+\r
/* Restart SysTick. */\r
- portNVIC_SYSTICK_CTRL_REG = portNVIC_SYSTICK_CLK_BIT | portNVIC_SYSTICK_INT_BIT | portNVIC_SYSTICK_ENABLE_BIT;\r
+ portNVIC_SYSTICK_CTRL_REG |= portNVIC_SYSTICK_ENABLE_BIT;\r
+\r
+ /* Reset the reload register to the value required for normal tick\r
+ periods. */\r
+ portNVIC_SYSTICK_LOAD_REG = ulTimerCountsForOneTick - 1UL;\r
\r
- /* Re-enable interrupts - see comments above __disable_irq() call \r
+ /* Re-enable interrupts - see comments above __disable_irq() call\r
above. */\r
__enable_irq();\r
}\r
portNVIC_SYSTICK_CURRENT_VALUE_REG = 0UL;\r
\r
/* Restart SysTick. */\r
- portNVIC_SYSTICK_CTRL_REG = portNVIC_SYSTICK_CLK_BIT | portNVIC_SYSTICK_INT_BIT | portNVIC_SYSTICK_ENABLE_BIT;\r
+ portNVIC_SYSTICK_CTRL_REG |= portNVIC_SYSTICK_ENABLE_BIT;\r
\r
/* Sleep until something happens. configPRE_SLEEP_PROCESSING() can\r
set its parameter to 0 to indicate that its implementation contains\r
configPRE_SLEEP_PROCESSING( xModifiableIdleTime );\r
if( xModifiableIdleTime > 0 )\r
{\r
+ __dsb( portSY_FULL_READ_WRITE );\r
__wfi();\r
+ __isb( portSY_FULL_READ_WRITE );\r
}\r
configPOST_SLEEP_PROCESSING( xExpectedIdleTime );\r
\r
- /* Stop SysTick. Again, the time the SysTick is stopped for is\r
- accounted for as best it can be, but using the tickless mode will\r
- inevitably result in some tiny drift of the time maintained by the\r
- kernel with respect to calendar time. */\r
- portNVIC_SYSTICK_CTRL_REG = portNVIC_SYSTICK_CLK_BIT | portNVIC_SYSTICK_INT_BIT;\r
-\r
- /* Re-enable interrupts - see comments above __disable_irq() call \r
- above. */\r
+ /* Re-enable interrupts to allow the interrupt that brought the MCU\r
+ out of sleep mode to execute immediately. see comments above\r
+ __disable_interrupt() call above. */\r
__enable_irq();\r
-\r
+ __dsb( portSY_FULL_READ_WRITE );\r
+ __isb( portSY_FULL_READ_WRITE );\r
+\r
+ /* Disable interrupts again because the clock is about to be stopped\r
+ and interrupts that execute while the clock is stopped will increase\r
+ any slippage between the time maintained by the RTOS and calendar\r
+ time. */\r
+ __disable_irq();\r
+ __dsb( portSY_FULL_READ_WRITE );\r
+ __isb( portSY_FULL_READ_WRITE );\r
+\r
+ /* Disable the SysTick clock without reading the\r
+ portNVIC_SYSTICK_CTRL_REG register to ensure the\r
+ portNVIC_SYSTICK_COUNT_FLAG_BIT is not cleared if it is set. Again,\r
+ the time the SysTick is stopped for is accounted for as best it can\r
+ be, but using the tickless mode will inevitably result in some tiny\r
+ drift of the time maintained by the kernel with respect to calendar\r
+ time*/\r
+ portNVIC_SYSTICK_CTRL_REG = ( portNVIC_SYSTICK_CLK_BIT | portNVIC_SYSTICK_INT_BIT );\r
+\r
+ /* Determine if the SysTick clock has already counted to zero and\r
+ been set back to the current reload value (the reload back being\r
+ correct for the entire expected idle time) or if the SysTick is yet\r
+ to count to zero (in which case an interrupt other than the SysTick\r
+ must have brought the system out of sleep mode). */\r
if( ( portNVIC_SYSTICK_CTRL_REG & portNVIC_SYSTICK_COUNT_FLAG_BIT ) != 0 )\r
{\r
- /* The tick interrupt has already executed, and the SysTick\r
- count reloaded with the portNVIC_SYSTICK_LOAD_REG value.\r
- Reset the portNVIC_SYSTICK_LOAD_REG with whatever remains of\r
- this tick period. */\r
- portNVIC_SYSTICK_LOAD_REG = ulTimerReloadValueForOneTick - ( ulReloadValue - portNVIC_SYSTICK_CURRENT_VALUE_REG );\r
-\r
- /* The tick interrupt handler will already have pended the tick\r
- processing in the kernel. As the pending tick will be\r
- processed as soon as this function exits, the tick value\r
- maintained by the tick is stepped forward by one less than the\r
- time spent waiting. */\r
+ uint32_t ulCalculatedLoadValue;\r
+\r
+ /* The tick interrupt is already pending, and the SysTick count\r
+ reloaded with ulReloadValue. Reset the\r
+ portNVIC_SYSTICK_LOAD_REG with whatever remains of this tick\r
+ period. */\r
+ ulCalculatedLoadValue = ( ulTimerCountsForOneTick - 1UL ) - ( ulReloadValue - portNVIC_SYSTICK_CURRENT_VALUE_REG );\r
+\r
+ /* Don't allow a tiny value, or values that have somehow\r
+ underflowed because the post sleep hook did something\r
+ that took too long. */\r
+ if( ( ulCalculatedLoadValue < ulStoppedTimerCompensation ) || ( ulCalculatedLoadValue > ulTimerCountsForOneTick ) )\r
+ {\r
+ ulCalculatedLoadValue = ( ulTimerCountsForOneTick - 1UL );\r
+ }\r
+\r
+ portNVIC_SYSTICK_LOAD_REG = ulCalculatedLoadValue;\r
+\r
+ /* As the pending tick will be processed as soon as this\r
+ function exits, the tick value maintained by the tick is stepped\r
+ forward by one less than the time spent waiting. */\r
ulCompleteTickPeriods = xExpectedIdleTime - 1UL;\r
}\r
else\r
{\r
/* Something other than the tick interrupt ended the sleep.\r
- Work out how long the sleep lasted. */\r
- ulCompletedSysTickIncrements = ( xExpectedIdleTime * ulTimerReloadValueForOneTick ) - portNVIC_SYSTICK_CURRENT_VALUE_REG;\r
+ Work out how long the sleep lasted rounded to complete tick\r
+ periods (not the ulReload value which accounted for part\r
+ ticks). */\r
+ ulCompletedSysTickDecrements = ( xExpectedIdleTime * ulTimerCountsForOneTick ) - portNVIC_SYSTICK_CURRENT_VALUE_REG;\r
\r
/* How many complete tick periods passed while the processor\r
was waiting? */\r
- ulCompleteTickPeriods = ulCompletedSysTickIncrements / ulTimerReloadValueForOneTick;\r
+ ulCompleteTickPeriods = ulCompletedSysTickDecrements / ulTimerCountsForOneTick;\r
\r
/* The reload value is set to whatever fraction of a single tick\r
period remains. */\r
- portNVIC_SYSTICK_LOAD_REG = ( ( ulCompleteTickPeriods + 1 ) * ulTimerReloadValueForOneTick ) - ulCompletedSysTickIncrements;\r
+ portNVIC_SYSTICK_LOAD_REG = ( ( ulCompleteTickPeriods + 1UL ) * ulTimerCountsForOneTick ) - ulCompletedSysTickDecrements;\r
}\r
\r
/* Restart SysTick so it runs from portNVIC_SYSTICK_LOAD_REG\r
again, then set portNVIC_SYSTICK_LOAD_REG back to its standard\r
value. */\r
portNVIC_SYSTICK_CURRENT_VALUE_REG = 0UL;\r
- portNVIC_SYSTICK_CTRL_REG = portNVIC_SYSTICK_CLK_BIT | portNVIC_SYSTICK_INT_BIT | portNVIC_SYSTICK_ENABLE_BIT;\r
-\r
+ portNVIC_SYSTICK_CTRL_REG |= portNVIC_SYSTICK_ENABLE_BIT;\r
vTaskStepTick( ulCompleteTickPeriods );\r
+ portNVIC_SYSTICK_LOAD_REG = ulTimerCountsForOneTick - 1UL;\r
+\r
+ /* Exit with interrupts enabled. */\r
+ __enable_irq();\r
}\r
}\r
\r
* Setup the SysTick timer to generate the tick interrupts at the required\r
* frequency.\r
*/\r
-#if configOVERRIDE_DEFAULT_TICK_CONFIGURATION == 0\r
+#if( configOVERRIDE_DEFAULT_TICK_CONFIGURATION == 0 )\r
\r
- void vPortSetupTimerInterrupt( void )\r
+ __weak void vPortSetupTimerInterrupt( void )\r
{\r
/* Calculate the constants required to configure the tick interrupt. */\r
- #if configUSE_TICKLESS_IDLE == 1\r
+ #if( configUSE_TICKLESS_IDLE == 1 )\r
{\r
- ulTimerReloadValueForOneTick = ( configSYSTICK_CLOCK_HZ / configTICK_RATE_HZ ) - 1UL;\r
- xMaximumPossibleSuppressedTicks = 0xffffffUL / ( ( configSYSTICK_CLOCK_HZ / configTICK_RATE_HZ ) - 1UL );\r
- ulStoppedTimerCompensation = 45UL / ( configCPU_CLOCK_HZ / configSYSTICK_CLOCK_HZ );\r
+ ulTimerCountsForOneTick = ( configSYSTICK_CLOCK_HZ / configTICK_RATE_HZ );\r
+ xMaximumPossibleSuppressedTicks = portMAX_24_BIT_NUMBER / ulTimerCountsForOneTick;\r
+ ulStoppedTimerCompensation = portMISSED_COUNTS_FACTOR / ( configCPU_CLOCK_HZ / configSYSTICK_CLOCK_HZ );\r
}\r
#endif /* configUSE_TICKLESS_IDLE */\r
\r
+ /* Stop and clear the SysTick. */\r
+ portNVIC_SYSTICK_CTRL_REG = 0UL;\r
+ portNVIC_SYSTICK_CURRENT_VALUE_REG = 0UL;\r
+\r
/* Configure SysTick to interrupt at the requested rate. */\r
- portNVIC_SYSTICK_LOAD_REG = ( configSYSTICK_CLOCK_HZ / configTICK_RATE_HZ ) - 1UL;;\r
- portNVIC_SYSTICK_CTRL_REG = portNVIC_SYSTICK_CLK_BIT | portNVIC_SYSTICK_INT_BIT | portNVIC_SYSTICK_ENABLE_BIT;\r
+ portNVIC_SYSTICK_LOAD_REG = ( configSYSTICK_CLOCK_HZ / configTICK_RATE_HZ ) - 1UL;\r
+ portNVIC_SYSTICK_CTRL_REG = ( portNVIC_SYSTICK_CLK_BIT | portNVIC_SYSTICK_INT_BIT | portNVIC_SYSTICK_ENABLE_BIT );\r
}\r
\r
#endif /* configOVERRIDE_DEFAULT_TICK_CONFIGURATION */\r
/*-----------------------------------------------------------*/\r
\r
-__asm unsigned long ulPortSetInterruptMask( void )\r
+__asm uint32_t vPortGetIPSR( void )\r
{\r
PRESERVE8\r
\r
- mrs r0, basepri\r
- mov r1, #configMAX_SYSCALL_INTERRUPT_PRIORITY\r
- msr basepri, r1\r
+ mrs r0, ipsr\r
bx r14\r
}\r
/*-----------------------------------------------------------*/\r
\r
-__asm void vPortClearInterruptMask( unsigned long ulNewMask )\r
-{\r
- PRESERVE8\r
+#if( configASSERT_DEFINED == 1 )\r
+\r
+ void vPortValidateInterruptPriority( void )\r
+ {\r
+ uint32_t ulCurrentInterrupt;\r
+ uint8_t ucCurrentPriority;\r
+\r
+ /* Obtain the number of the currently executing interrupt. */\r
+ ulCurrentInterrupt = vPortGetIPSR();\r
+\r
+ /* Is the interrupt number a user defined interrupt? */\r
+ if( ulCurrentInterrupt >= portFIRST_USER_INTERRUPT_NUMBER )\r
+ {\r
+ /* Look up the interrupt's priority. */\r
+ ucCurrentPriority = pcInterruptPriorityRegisters[ ulCurrentInterrupt ];\r
+\r
+ /* The following assertion will fail if a service routine (ISR) for\r
+ an interrupt that has been assigned a priority above\r
+ configMAX_SYSCALL_INTERRUPT_PRIORITY calls an ISR safe FreeRTOS API\r
+ function. ISR safe FreeRTOS API functions must *only* be called\r
+ from interrupts that have been assigned a priority at or below\r
+ configMAX_SYSCALL_INTERRUPT_PRIORITY.\r
+\r
+ Numerically low interrupt priority numbers represent logically high\r
+ interrupt priorities, therefore the priority of the interrupt must\r
+ be set to a value equal to or numerically *higher* than\r
+ configMAX_SYSCALL_INTERRUPT_PRIORITY.\r
+\r
+ Interrupts that use the FreeRTOS API must not be left at their\r
+ default priority of zero as that is the highest possible priority,\r
+ which is guaranteed to be above configMAX_SYSCALL_INTERRUPT_PRIORITY,\r
+ and therefore also guaranteed to be invalid.\r
+\r
+ FreeRTOS maintains separate thread and ISR API functions to ensure\r
+ interrupt entry is as fast and simple as possible.\r
+\r
+ The following links provide detailed information:\r
+ http://www.freertos.org/RTOS-Cortex-M3-M4.html\r
+ http://www.freertos.org/FAQHelp.html */\r
+ configASSERT( ucCurrentPriority >= ucMaxSysCallPriority );\r
+ }\r
+\r
+ /* Priority grouping: The interrupt controller (NVIC) allows the bits\r
+ that define each interrupt's priority to be split between bits that\r
+ define the interrupt's pre-emption priority bits and bits that define\r
+ the interrupt's sub-priority. For simplicity all bits must be defined\r
+ to be pre-emption priority bits. The following assertion will fail if\r
+ this is not the case (if some bits represent a sub-priority).\r
+\r
+ If the application only uses CMSIS libraries for interrupt\r
+ configuration then the correct setting can be achieved on all Cortex-M\r
+ devices by calling NVIC_SetPriorityGrouping( 0 ); before starting the\r
+ scheduler. Note however that some vendor specific peripheral libraries\r
+ assume a non-zero priority group setting, in which cases using a value\r
+ of zero will result in unpredictable behaviour. */\r
+ configASSERT( ( portAIRCR_REG & portPRIORITY_GROUP_MASK ) <= ulMaxPRIGROUPValue );\r
+ }\r
+\r
+#endif /* configASSERT_DEFINED */\r
+\r
\r
- msr basepri, r0\r
- bx r14\r
-}\r
projects / freertos / blobdiff