/*\r
- FreeRTOS V7.6.0 - Copyright (C) 2013 Real Time Engineers Ltd.\r
- All rights reserved\r
-\r
- VISIT http://www.FreeRTOS.org TO ENSURE YOU ARE USING THE LATEST VERSION.\r
-\r
- ***************************************************************************\r
- * *\r
- * FreeRTOS provides completely free yet professionally developed, *\r
- * robust, strictly quality controlled, supported, and cross *\r
- * platform software that has become a de facto standard. *\r
- * *\r
- * Help yourself get started quickly and support the FreeRTOS *\r
- * project by purchasing a FreeRTOS tutorial book, reference *\r
- * manual, or both from: http://www.FreeRTOS.org/Documentation *\r
- * *\r
- * Thank you! *\r
- * *\r
- ***************************************************************************\r
-\r
- This file is part of the FreeRTOS distribution.\r
-\r
- FreeRTOS is free software; you can redistribute it and/or modify it under\r
- the terms of the GNU General Public License (version 2) as published by the\r
- Free Software Foundation >>!AND MODIFIED BY!<< the FreeRTOS exception.\r
-\r
- >>! NOTE: The modification to the GPL is included to allow you to distribute\r
- >>! a combined work that includes FreeRTOS without being obliged to provide\r
- >>! the source code for proprietary components outside of the FreeRTOS\r
- >>! kernel.\r
-\r
- FreeRTOS is distributed in the hope that it will be useful, but WITHOUT ANY\r
- WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS\r
- FOR A PARTICULAR PURPOSE. Full license text is available from the following\r
- link: http://www.freertos.org/a00114.html\r
-\r
- 1 tab == 4 spaces!\r
-\r
- ***************************************************************************\r
- * *\r
- * Having a problem? Start by reading the FAQ "My application does *\r
- * not run, what could be wrong?" *\r
- * *\r
- * http://www.FreeRTOS.org/FAQHelp.html *\r
- * *\r
- ***************************************************************************\r
-\r
- http://www.FreeRTOS.org - Documentation, books, training, latest versions,\r
- license and Real Time Engineers Ltd. contact details.\r
-\r
- http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products,\r
- including FreeRTOS+Trace - an indispensable productivity tool, a DOS\r
- compatible FAT file system, and our tiny thread aware UDP/IP stack.\r
-\r
- http://www.OpenRTOS.com - Real Time Engineers ltd license FreeRTOS to High\r
- Integrity Systems to sell under the OpenRTOS brand. Low cost OpenRTOS\r
- licenses offer ticketed support, indemnification and middleware.\r
-\r
- http://www.SafeRTOS.com - High Integrity Systems also provide a safety\r
- engineered and independently SIL3 certified version for use in safety and\r
- mission critical applications that require provable dependability.\r
-\r
- 1 tab == 4 spaces!\r
-*/\r
+ * FreeRTOS Kernel V10.2.1\r
+ * Copyright (C) 2019 Amazon.com, Inc. or its affiliates. All Rights Reserved.\r
+ *\r
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of\r
+ * this software and associated documentation files (the "Software"), to deal in\r
+ * the Software without restriction, including without limitation the rights to\r
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of\r
+ * the Software, and to permit persons to whom the Software is furnished to do so,\r
+ * subject to the following conditions:\r
+ *\r
+ * The above copyright notice and this permission notice shall be included in all\r
+ * copies or substantial portions of the Software.\r
+ *\r
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR\r
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS\r
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR\r
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER\r
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN\r
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.\r
+ *\r
+ * http://www.FreeRTOS.org\r
+ * http://aws.amazon.com/freertos\r
+ *\r
+ * 1 tab == 4 spaces!\r
+ */\r
\r
/*-----------------------------------------------------------\r
* Implementation of functions defined in portable.h for the ARM CM4F port.\r
#define portNVIC_SYSTICK_CLK_BIT ( 0 )\r
#endif\r
\r
-/* The __weak attribute does not work as you might expect with the Keil tools\r
-so the configOVERRIDE_DEFAULT_TICK_CONFIGURATION constant must be set to 1 if\r
-the application writer wants to provide their own implementation of\r
-vPortSetupTimerInterrupt(). Ensure configOVERRIDE_DEFAULT_TICK_CONFIGURATION\r
-is defined. */\r
+/* Legacy macro for backward compatibility only. This macro used to be used to\r
+replace the function that configures the clock used to generate the tick\r
+interrupt (prvSetupTimerInterrupt()), but now the function is declared weak so\r
+the application writer can override it by simply defining a function of the\r
+same name (vApplicationSetupTickInterrupt()). */\r
#ifndef configOVERRIDE_DEFAULT_TICK_CONFIGURATION\r
#define configOVERRIDE_DEFAULT_TICK_CONFIGURATION 0\r
#endif\r
#define portNVIC_PENDSVCLEAR_BIT ( 1UL << 27UL )\r
#define portNVIC_PEND_SYSTICK_CLEAR_BIT ( 1UL << 25UL )\r
\r
+/* Constants used to detect a Cortex-M7 r0p1 core, which should use the ARM_CM7\r
+r0p1 port. */\r
+#define portCPUID ( * ( ( volatile uint32_t * ) 0xE000ed00 ) )\r
+#define portCORTEX_M7_r0p1_ID ( 0x410FC271UL )\r
+#define portCORTEX_M7_r0p0_ID ( 0x410FC270UL )\r
+\r
#define portNVIC_PENDSV_PRI ( ( ( uint32_t ) configKERNEL_INTERRUPT_PRIORITY ) << 16UL )\r
#define portNVIC_SYSTICK_PRI ( ( ( uint32_t ) configKERNEL_INTERRUPT_PRIORITY ) << 24UL )\r
\r
#define portPRIORITY_GROUP_MASK ( 0x07UL << 8UL )\r
#define portPRIGROUP_SHIFT ( 8UL )\r
\r
+/* Masks off all bits but the VECTACTIVE bits in the ICSR register. */\r
+#define portVECTACTIVE_MASK ( 0xFFUL )\r
+\r
/* Constants required to manipulate the VFP. */\r
#define portFPCCR ( ( volatile uint32_t * ) 0xe000ef34 ) /* Floating point context control register. */\r
#define portASPEN_AND_LSPEN_BITS ( 0x3UL << 30UL )\r
\r
/* Constants required to set up the initial stack. */\r
#define portINITIAL_XPSR ( 0x01000000 )\r
-#define portINITIAL_EXEC_RETURN ( 0xfffffffd )\r
-\r
-/* Constants used with memory barrier intrinsics. */\r
-#define portSY_FULL_READ_WRITE ( 15 )\r
+#define portINITIAL_EXC_RETURN ( 0xfffffffd )\r
\r
/* The systick is a 24-bit counter. */\r
-#define portMAX_24_BIT_NUMBER ( 0xffffffUL )\r
+#define portMAX_24_BIT_NUMBER ( 0xffffffUL )\r
\r
/* A fiddle factor to estimate the number of SysTick counts that would have\r
occurred while the SysTick counter is stopped during tickless idle\r
calculations. */\r
-#define portMISSED_COUNTS_FACTOR ( 45UL )\r
+#define portMISSED_COUNTS_FACTOR ( 45UL )\r
\r
-/* Each task maintains its own interrupt status in the critical nesting\r
-variable. */\r
-static UBaseType_t uxCriticalNesting = 0xaaaaaaaa;\r
+/* For strict compliance with the Cortex-M spec the task start address should\r
+have bit-0 clear, as it is loaded into the PC on exit from an ISR. */\r
+#define portSTART_ADDRESS_MASK ( ( StackType_t ) 0xfffffffeUL )\r
\r
/*\r
* Setup the timer to generate the tick interrupts. The implementation in this\r
\r
/*-----------------------------------------------------------*/\r
\r
+/* Each task maintains its own interrupt status in the critical nesting\r
+variable. */\r
+static UBaseType_t uxCriticalNesting = 0xaaaaaaaa;\r
+\r
/*\r
* The number of SysTick increments that make up one tick period.\r
*/\r
-#if configUSE_TICKLESS_IDLE == 1\r
+#if( configUSE_TICKLESS_IDLE == 1 )\r
static uint32_t ulTimerCountsForOneTick = 0;\r
#endif /* configUSE_TICKLESS_IDLE */\r
\r
* The maximum number of tick periods that can be suppressed is limited by the\r
* 24 bit resolution of the SysTick timer.\r
*/\r
-#if configUSE_TICKLESS_IDLE == 1\r
+#if( configUSE_TICKLESS_IDLE == 1 )\r
static uint32_t xMaximumPossibleSuppressedTicks = 0;\r
#endif /* configUSE_TICKLESS_IDLE */\r
\r
* Compensate for the CPU cycles that pass while the SysTick is stopped (low\r
* power functionality only.\r
*/\r
-#if configUSE_TICKLESS_IDLE == 1\r
+#if( configUSE_TICKLESS_IDLE == 1 )\r
static uint32_t ulStoppedTimerCompensation = 0;\r
#endif /* configUSE_TICKLESS_IDLE */\r
\r
/*\r
* See header file for description.\r
*/\r
-StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, pdTASK_CODE pxCode, void *pvParameters )\r
+StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, TaskFunction_t pxCode, void *pvParameters )\r
{\r
/* Simulate the stack frame as it would be created by a context switch\r
interrupt. */\r
\r
*pxTopOfStack = portINITIAL_XPSR; /* xPSR */\r
pxTopOfStack--;\r
- *pxTopOfStack = ( StackType_t ) pxCode; /* PC */\r
+ *pxTopOfStack = ( ( StackType_t ) pxCode ) & portSTART_ADDRESS_MASK; /* PC */\r
pxTopOfStack--;\r
*pxTopOfStack = ( StackType_t ) prvTaskExitError; /* LR */\r
\r
/* A save method is being used that requires each task to maintain its\r
own exec return value. */\r
pxTopOfStack--;\r
- *pxTopOfStack = portINITIAL_EXEC_RETURN;\r
+ *pxTopOfStack = portINITIAL_EXC_RETURN;\r
\r
pxTopOfStack -= 8; /* R11, R10, R9, R8, R7, R6, R5 and R4. */\r
\r
ldr r0, [r0]\r
/* Set the msp back to the start of the stack. */\r
msr msp, r0\r
+ /* Clear the bit that indicates the FPU is in use in case the FPU was used\r
+ before the scheduler was started - which would otherwise result in the\r
+ unnecessary leaving of space in the SVC stack for lazy saving of FPU\r
+ registers. */\r
+ mov r0, #0\r
+ msr control, r0\r
/* Globally enable interrupts. */\r
cpsie i\r
+ cpsie f\r
dsb\r
isb\r
/* Call SVC to start the first task. */\r
svc 0\r
nop\r
+ nop\r
}\r
/*-----------------------------------------------------------*/\r
\r
*/\r
BaseType_t xPortStartScheduler( void )\r
{\r
+ /* configMAX_SYSCALL_INTERRUPT_PRIORITY must not be set to 0.\r
+ See http://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html */\r
+ configASSERT( configMAX_SYSCALL_INTERRUPT_PRIORITY );\r
+\r
+ /* This port can be used on all revisions of the Cortex-M7 core other than\r
+ the r0p1 parts. r0p1 parts should use the port from the\r
+ /source/portable/GCC/ARM_CM7/r0p1 directory. */\r
+ configASSERT( portCPUID != portCORTEX_M7_r0p1_ID );\r
+ configASSERT( portCPUID != portCORTEX_M7_r0p0_ID );\r
+\r
#if( configASSERT_DEFINED == 1 )\r
{\r
volatile uint32_t ulOriginalPriority;\r
/* Read the value back to see how many bits stuck. */\r
ucMaxPriorityValue = *pucFirstUserPriorityRegister;\r
\r
+ /* The kernel interrupt priority should be set to the lowest\r
+ priority. */\r
+ configASSERT( ucMaxPriorityValue == ( configKERNEL_INTERRUPT_PRIORITY & ucMaxPriorityValue ) );\r
+\r
/* Use the same mask on the maximum system call priority. */\r
ucMaxSysCallPriority = configMAX_SYSCALL_INTERRUPT_PRIORITY & ucMaxPriorityValue;\r
\r
ucMaxPriorityValue <<= ( uint8_t ) 0x01;\r
}\r
\r
+ #ifdef __NVIC_PRIO_BITS\r
+ {\r
+ /* Check the CMSIS configuration that defines the number of\r
+ priority bits matches the number of priority bits actually queried\r
+ from the hardware. */\r
+ configASSERT( ( portMAX_PRIGROUP_BITS - ulMaxPRIGROUPValue ) == __NVIC_PRIO_BITS );\r
+ }\r
+ #endif\r
+\r
+ #ifdef configPRIO_BITS\r
+ {\r
+ /* Check the FreeRTOS configuration that defines the number of\r
+ priority bits matches the number of priority bits actually queried\r
+ from the hardware. */\r
+ configASSERT( ( portMAX_PRIGROUP_BITS - ulMaxPRIGROUPValue ) == configPRIO_BITS );\r
+ }\r
+ #endif\r
+\r
/* Shift the priority group value back to its position within the AIRCR\r
register. */\r
ulMaxPRIGROUPValue <<= portPRIGROUP_SHIFT;\r
}\r
/*-----------------------------------------------------------*/\r
\r
-void vPortYield( void )\r
-{\r
- /* Set a PendSV to request a context switch. */\r
- portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT;\r
-\r
- /* Barriers are normally not required but do ensure the code is completely\r
- within the specified behaviour for the architecture. */\r
- __dsb( portSY_FULL_READ_WRITE );\r
- __isb( portSY_FULL_READ_WRITE );\r
-}\r
-/*-----------------------------------------------------------*/\r
-\r
void vPortEnterCritical( void )\r
{\r
portDISABLE_INTERRUPTS();\r
uxCriticalNesting++;\r
- __dsb( portSY_FULL_READ_WRITE );\r
- __isb( portSY_FULL_READ_WRITE );\r
+\r
+ /* This is not the interrupt safe version of the enter critical function so\r
+ assert() if it is being called from an interrupt context. Only API\r
+ functions that end in "FromISR" can be used in an interrupt. Only assert if\r
+ the critical nesting count is 1 to protect against recursive calls if the\r
+ assert function also uses a critical section. */\r
+ if( uxCriticalNesting == 1 )\r
+ {\r
+ configASSERT( ( portNVIC_INT_CTRL_REG & portVECTACTIVE_MASK ) == 0 );\r
+ }\r
}\r
/*-----------------------------------------------------------*/\r
\r
/* Save the new top of stack into the first member of the TCB. */\r
str r0, [r2]\r
\r
- stmdb sp!, {r3}\r
+ stmdb sp!, {r0, r3}\r
mov r0, #configMAX_SYSCALL_INTERRUPT_PRIORITY\r
msr basepri, r0\r
+ dsb\r
+ isb\r
bl vTaskSwitchContext\r
mov r0, #0\r
msr basepri, r0\r
- ldmia sp!, {r3}\r
+ ldmia sp!, {r0, r3}\r
\r
/* The first item in pxCurrentTCB is the task top of stack. */\r
ldr r1, [r3]\r
#endif\r
\r
bx r14\r
- nop\r
}\r
/*-----------------------------------------------------------*/\r
\r
/* The SysTick runs at the lowest interrupt priority, so when this interrupt\r
executes all interrupts must be unmasked. There is therefore no need to\r
save and then restore the interrupt mask value as its value is already\r
- known. */\r
- ( void ) portSET_INTERRUPT_MASK_FROM_ISR();\r
+ known - therefore the slightly faster vPortRaiseBASEPRI() function is used\r
+ in place of portSET_INTERRUPT_MASK_FROM_ISR(). */\r
+ vPortRaiseBASEPRI();\r
{\r
/* Increment the RTOS tick. */\r
if( xTaskIncrementTick() != pdFALSE )\r
portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT;\r
}\r
}\r
- portCLEAR_INTERRUPT_MASK_FROM_ISR( 0 );\r
+ vPortClearBASEPRIFromISR();\r
}\r
/*-----------------------------------------------------------*/\r
\r
-#if configUSE_TICKLESS_IDLE == 1\r
+#if( configUSE_TICKLESS_IDLE == 1 )\r
\r
__weak void vPortSuppressTicksAndSleep( TickType_t xExpectedIdleTime )\r
{\r
- uint32_t ulReloadValue, ulCompleteTickPeriods, ulCompletedSysTickDecrements, ulSysTickCTRL;\r
+ uint32_t ulReloadValue, ulCompleteTickPeriods, ulCompletedSysTickDecrements;\r
TickType_t xModifiableIdleTime;\r
\r
/* Make sure the SysTick reload value does not overflow the counter. */\r
/* Enter a critical section but don't use the taskENTER_CRITICAL()\r
method as that will mask interrupts that should exit sleep mode. */\r
__disable_irq();\r
+ __dsb( portSY_FULL_READ_WRITE );\r
+ __isb( portSY_FULL_READ_WRITE );\r
\r
/* If a context switch is pending or a task is waiting for the scheduler\r
to be unsuspended then abandon the low power entry. */\r
}\r
configPOST_SLEEP_PROCESSING( xExpectedIdleTime );\r
\r
- /* Stop SysTick. Again, the time the SysTick is stopped for is\r
- accounted for as best it can be, but using the tickless mode will\r
- inevitably result in some tiny drift of the time maintained by the\r
- kernel with respect to calendar time. */\r
- ulSysTickCTRL = portNVIC_SYSTICK_CTRL_REG;\r
- portNVIC_SYSTICK_CTRL_REG = ( ulSysTickCTRL & ~portNVIC_SYSTICK_ENABLE_BIT );\r
-\r
- /* Re-enable interrupts - see comments above __disable_irq() call\r
- above. */\r
+ /* Re-enable interrupts to allow the interrupt that brought the MCU\r
+ out of sleep mode to execute immediately. see comments above\r
+ __disable_interrupt() call above. */\r
__enable_irq();\r
-\r
- if( ( ulSysTickCTRL & portNVIC_SYSTICK_COUNT_FLAG_BIT ) != 0 )\r
+ __dsb( portSY_FULL_READ_WRITE );\r
+ __isb( portSY_FULL_READ_WRITE );\r
+\r
+ /* Disable interrupts again because the clock is about to be stopped\r
+ and interrupts that execute while the clock is stopped will increase\r
+ any slippage between the time maintained by the RTOS and calendar\r
+ time. */\r
+ __disable_irq();\r
+ __dsb( portSY_FULL_READ_WRITE );\r
+ __isb( portSY_FULL_READ_WRITE );\r
+\r
+ /* Disable the SysTick clock without reading the\r
+ portNVIC_SYSTICK_CTRL_REG register to ensure the\r
+ portNVIC_SYSTICK_COUNT_FLAG_BIT is not cleared if it is set. Again,\r
+ the time the SysTick is stopped for is accounted for as best it can\r
+ be, but using the tickless mode will inevitably result in some tiny\r
+ drift of the time maintained by the kernel with respect to calendar\r
+ time*/\r
+ portNVIC_SYSTICK_CTRL_REG = ( portNVIC_SYSTICK_CLK_BIT | portNVIC_SYSTICK_INT_BIT );\r
+\r
+ /* Determine if the SysTick clock has already counted to zero and\r
+ been set back to the current reload value (the reload back being\r
+ correct for the entire expected idle time) or if the SysTick is yet\r
+ to count to zero (in which case an interrupt other than the SysTick\r
+ must have brought the system out of sleep mode). */\r
+ if( ( portNVIC_SYSTICK_CTRL_REG & portNVIC_SYSTICK_COUNT_FLAG_BIT ) != 0 )\r
{\r
uint32_t ulCalculatedLoadValue;\r
\r
- /* The tick interrupt has already executed, and the SysTick\r
- count reloaded with ulReloadValue. Reset the\r
+ /* The tick interrupt is already pending, and the SysTick count\r
+ reloaded with ulReloadValue. Reset the\r
portNVIC_SYSTICK_LOAD_REG with whatever remains of this tick\r
period. */\r
ulCalculatedLoadValue = ( ulTimerCountsForOneTick - 1UL ) - ( ulReloadValue - portNVIC_SYSTICK_CURRENT_VALUE_REG );\r
\r
portNVIC_SYSTICK_LOAD_REG = ulCalculatedLoadValue;\r
\r
- /* The tick interrupt handler will already have pended the tick\r
- processing in the kernel. As the pending tick will be\r
- processed as soon as this function exits, the tick value\r
- maintained by the tick is stepped forward by one less than the\r
- time spent waiting. */\r
+ /* As the pending tick will be processed as soon as this\r
+ function exits, the tick value maintained by the tick is stepped\r
+ forward by one less than the time spent waiting. */\r
ulCompleteTickPeriods = xExpectedIdleTime - 1UL;\r
}\r
else\r
\r
/* The reload value is set to whatever fraction of a single tick\r
period remains. */\r
- portNVIC_SYSTICK_LOAD_REG = ( ( ulCompleteTickPeriods + 1 ) * ulTimerCountsForOneTick ) - ulCompletedSysTickDecrements;\r
+ portNVIC_SYSTICK_LOAD_REG = ( ( ulCompleteTickPeriods + 1UL ) * ulTimerCountsForOneTick ) - ulCompletedSysTickDecrements;\r
}\r
\r
/* Restart SysTick so it runs from portNVIC_SYSTICK_LOAD_REG\r
again, then set portNVIC_SYSTICK_LOAD_REG back to its standard\r
- value. The critical section is used to ensure the tick interrupt\r
- can only execute once in the case that the reload register is near\r
- zero. */\r
+ value. */\r
portNVIC_SYSTICK_CURRENT_VALUE_REG = 0UL;\r
- portENTER_CRITICAL();\r
- {\r
- portNVIC_SYSTICK_CTRL_REG |= portNVIC_SYSTICK_ENABLE_BIT;\r
- vTaskStepTick( ulCompleteTickPeriods );\r
- portNVIC_SYSTICK_LOAD_REG = ulTimerCountsForOneTick - 1UL;\r
- }\r
- portEXIT_CRITICAL();\r
+ portNVIC_SYSTICK_CTRL_REG |= portNVIC_SYSTICK_ENABLE_BIT;\r
+ vTaskStepTick( ulCompleteTickPeriods );\r
+ portNVIC_SYSTICK_LOAD_REG = ulTimerCountsForOneTick - 1UL;\r
+\r
+ /* Exit with interrupts enabled. */\r
+ __enable_irq();\r
}\r
}\r
\r
* Setup the SysTick timer to generate the tick interrupts at the required\r
* frequency.\r
*/\r
-#if configOVERRIDE_DEFAULT_TICK_CONFIGURATION == 0\r
+#if( configOVERRIDE_DEFAULT_TICK_CONFIGURATION == 0 )\r
\r
- void vPortSetupTimerInterrupt( void )\r
+ __weak void vPortSetupTimerInterrupt( void )\r
{\r
/* Calculate the constants required to configure the tick interrupt. */\r
- #if configUSE_TICKLESS_IDLE == 1\r
+ #if( configUSE_TICKLESS_IDLE == 1 )\r
{\r
ulTimerCountsForOneTick = ( configSYSTICK_CLOCK_HZ / configTICK_RATE_HZ );\r
xMaximumPossibleSuppressedTicks = portMAX_24_BIT_NUMBER / ulTimerCountsForOneTick;\r
}\r
#endif /* configUSE_TICKLESS_IDLE */\r
\r
+ /* Stop and clear the SysTick. */\r
+ portNVIC_SYSTICK_CTRL_REG = 0UL;\r
+ portNVIC_SYSTICK_CURRENT_VALUE_REG = 0UL;\r
+\r
/* Configure SysTick to interrupt at the requested rate. */\r
- portNVIC_SYSTICK_LOAD_REG = ( configSYSTICK_CLOCK_HZ / configTICK_RATE_HZ ) - 1UL;;\r
+ portNVIC_SYSTICK_LOAD_REG = ( configSYSTICK_CLOCK_HZ / configTICK_RATE_HZ ) - 1UL;\r
portNVIC_SYSTICK_CTRL_REG = ( portNVIC_SYSTICK_CLK_BIT | portNVIC_SYSTICK_INT_BIT | portNVIC_SYSTICK_ENABLE_BIT );\r
}\r
\r
#endif /* configOVERRIDE_DEFAULT_TICK_CONFIGURATION */\r
/*-----------------------------------------------------------*/\r
\r
-__asm uint32_t ulPortSetInterruptMask( void )\r
-{\r
- PRESERVE8\r
-\r
- mrs r0, basepri\r
- mov r1, #configMAX_SYSCALL_INTERRUPT_PRIORITY\r
- msr basepri, r1\r
- bx r14\r
-}\r
-/*-----------------------------------------------------------*/\r
-\r
-__asm void vPortClearInterruptMask( uint32_t ulNewMask )\r
-{\r
- PRESERVE8\r
-\r
- msr basepri, r0\r
- bx r14\r
-}\r
-/*-----------------------------------------------------------*/\r
-\r
__asm uint32_t vPortGetIPSR( void )\r
{\r
PRESERVE8\r
devices by calling NVIC_SetPriorityGrouping( 0 ); before starting the\r
scheduler. Note however that some vendor specific peripheral libraries\r
assume a non-zero priority group setting, in which cases using a value\r
- of zero will result in unpredicable behaviour. */\r
+ of zero will result in unpredictable behaviour. */\r
configASSERT( ( portAIRCR_REG & portPRIORITY_GROUP_MASK ) <= ulMaxPRIGROUPValue );\r
}\r
\r
projects / freertos / blobdiff