/*\r
- FreeRTOS V7.3.0 - Copyright (C) 2012 Real Time Engineers Ltd.\r
+ FreeRTOS V7.4.2 - Copyright (C) 2013 Real Time Engineers Ltd.\r
\r
- FEATURES AND PORTS ARE ADDED TO FREERTOS ALL THE TIME. PLEASE VISIT \r
+ FEATURES AND PORTS ARE ADDED TO FREERTOS ALL THE TIME. PLEASE VISIT\r
http://www.FreeRTOS.org TO ENSURE YOU ARE USING THE LATEST VERSION.\r
\r
***************************************************************************\r
FreeRTOS is free software; you can redistribute it and/or modify it under\r
the terms of the GNU General Public License (version 2) as published by the\r
Free Software Foundation AND MODIFIED BY the FreeRTOS exception.\r
- >>>NOTE<<< The modification to the GPL is included to allow you to\r
+\r
+ >>>>>>NOTE<<<<<< The modification to the GPL is included to allow you to\r
distribute a combined work that includes FreeRTOS without being obliged to\r
provide the source code for proprietary components outside of the FreeRTOS\r
- kernel. FreeRTOS is distributed in the hope that it will be useful, but\r
- WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY\r
- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for\r
- more details. You should have received a copy of the GNU General Public\r
- License and the FreeRTOS license exception along with FreeRTOS; if not it\r
- can be viewed here: http://www.freertos.org/a00114.html and also obtained\r
- by writing to Richard Barry, contact details for whom are available on the\r
- FreeRTOS WEB site.\r
+ kernel.\r
+\r
+ FreeRTOS is distributed in the hope that it will be useful, but WITHOUT ANY\r
+ WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS\r
+ FOR A PARTICULAR PURPOSE. See the GNU General Public License for more\r
+ details. You should have received a copy of the GNU General Public License\r
+ and the FreeRTOS license exception along with FreeRTOS; if not it can be\r
+ viewed here: http://www.freertos.org/a00114.html and also obtained by\r
+ writing to Real Time Engineers Ltd., contact details for whom are available\r
+ on the FreeRTOS WEB site.\r
\r
1 tab == 4 spaces!\r
- \r
+\r
***************************************************************************\r
* *\r
* Having a problem? Start by reading the FAQ "My application does *\r
* *\r
***************************************************************************\r
\r
- \r
- http://www.FreeRTOS.org - Documentation, training, latest versions, license \r
- and contact details. \r
- \r
+\r
+ http://www.FreeRTOS.org - Documentation, books, training, latest versions,\r
+ license and Real Time Engineers Ltd. contact details.\r
+\r
http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products,\r
- including FreeRTOS+Trace - an indispensable productivity tool.\r
+ including FreeRTOS+Trace - an indispensable productivity tool, and our new\r
+ fully thread aware and reentrant UDP/IP stack.\r
\r
- Real Time Engineers ltd license FreeRTOS to High Integrity Systems, who sell \r
- the code with commercial support, indemnification, and middleware, under \r
- the OpenRTOS brand: http://www.OpenRTOS.com. High Integrity Systems also\r
- provide a safety engineered and independently SIL3 certified version under \r
- the SafeRTOS brand: http://www.SafeRTOS.com.\r
+ http://www.OpenRTOS.com - Real Time Engineers ltd license FreeRTOS to High\r
+ Integrity Systems, who sell the code with commercial support,\r
+ indemnification and middleware, under the OpenRTOS brand.\r
+\r
+ http://www.SafeRTOS.com - High Integrity Systems also provide a safety\r
+ engineered and independently SIL3 certified version for use in safety and\r
+ mission critical applications that require provable dependability.\r
*/\r
\r
/*-----------------------------------------------------------\r
\r
#ifndef configSYSTICK_CLOCK_HZ\r
#define configSYSTICK_CLOCK_HZ configCPU_CLOCK_HZ\r
- #if configUSE_TICKLESS_IDLE == 1\r
- static const unsigned long ulStoppedTimerCompensation = 45UL;\r
- #endif\r
-#else /* configSYSTICK_CLOCK_HZ */\r
- #if configUSE_TICKLESS_IDLE == 1\r
- /* Assumes the SysTick clock is slower than the CPU clock. */\r
- static const unsigned long ulStoppedTimerCompensation = 45UL / ( configCPU_CLOCK_HZ / configSYSTICK_CLOCK_HZ );\r
- #endif\r
-#endif /* configSYSTICK_CLOCK_HZ */\r
+#endif\r
+\r
+/* The __weak attribute does not work as you might expect with the Keil tools\r
+so the configOVERRIDE_DEFAULT_TICK_CONFIGURATION constant must be set to 1 if\r
+the application writer wants to provide their own implementation of\r
+vPortSetupTimerInterrupt(). Ensure configOVERRIDE_DEFAULT_TICK_CONFIGURATION\r
+is defined. */\r
+#ifndef configOVERRIDE_DEFAULT_TICK_CONFIGURATION\r
+ #define configOVERRIDE_DEFAULT_TICK_CONFIGURATION 0\r
+#endif\r
\r
/* Constants required to manipulate the core. Registers first... */\r
#define portNVIC_SYSTICK_CTRL_REG ( * ( ( volatile unsigned long * ) 0xe000e010 ) )\r
#define portNVIC_SYSTICK_LOAD_REG ( * ( ( volatile unsigned long * ) 0xe000e014 ) )\r
#define portNVIC_SYSTICK_CURRENT_VALUE_REG ( * ( ( volatile unsigned long * ) 0xe000e018 ) )\r
-#define portNVIC_INT_CTRL_REG ( * ( ( volatile unsigned long * ) 0xe000ed04 ) )\r
#define portNVIC_SYSPRI2_REG ( * ( ( volatile unsigned long * ) 0xe000ed20 ) )\r
/* ...then bits in the registers. */\r
#define portNVIC_SYSTICK_CLK_BIT ( 1UL << 2UL )\r
#define portNVIC_SYSTICK_INT_BIT ( 1UL << 1UL )\r
#define portNVIC_SYSTICK_ENABLE_BIT ( 1UL << 0UL )\r
#define portNVIC_SYSTICK_COUNT_FLAG_BIT ( 1UL << 16UL )\r
-#define portNVIC_PENDSVSET_BIT ( 1UL << 28UL )\r
#define portNVIC_PENDSVCLEAR_BIT ( 1UL << 27UL )\r
#define portNVIC_PEND_SYSTICK_CLEAR_BIT ( 1UL << 25UL )\r
\r
#define portINITIAL_XPSR ( 0x01000000 )\r
#define portINITIAL_EXEC_RETURN ( 0xfffffffd )\r
\r
+/* Constants used with memory barrier intrinsics. */\r
+#define portSY_FULL_READ_WRITE ( 15 )\r
+\r
/* Each task maintains its own interrupt status in the critical nesting\r
variable. */\r
static unsigned portBASE_TYPE uxCriticalNesting = 0xaaaaaaaa;\r
\r
/*\r
- * Setup the timer to generate the tick interrupts.\r
+ * Setup the timer to generate the tick interrupts. The implementation in this\r
+ * file is weak to allow application writers to change the timer used to\r
+ * generate the tick interrupt.\r
*/\r
-static void prvSetupTimerInterrupt( void );\r
+void vPortSetupTimerInterrupt( void );\r
\r
/*\r
* Exception handlers.\r
/*\r
* The number of SysTick increments that make up one tick period.\r
*/\r
-static unsigned long ulTimerReloadValueForOneTick = 0;\r
+#if configUSE_TICKLESS_IDLE == 1\r
+ static unsigned long ulTimerReloadValueForOneTick = 0;\r
+#endif\r
\r
/*\r
* The maximum number of tick periods that can be suppressed is limited by the\r
static unsigned long xMaximumPossibleSuppressedTicks = 0;\r
#endif /* configUSE_TICKLESS_IDLE */\r
\r
+/*\r
+ * Compensate for the CPU cycles that pass while the SysTick is stopped (low\r
+ * power functionality only.\r
+ */\r
+#if configUSE_TICKLESS_IDLE == 1\r
+ static unsigned long ulStoppedTimerCompensation = 0;\r
+#endif /* configUSE_TICKLESS_IDLE */\r
+\r
/*-----------------------------------------------------------*/\r
\r
/*\r
\r
/* Start the timer that generates the tick ISR. Interrupts are disabled\r
here already. */\r
- prvSetupTimerInterrupt();\r
+ vPortSetupTimerInterrupt();\r
\r
/* Initialise the critical nesting count ready for the first task. */\r
uxCriticalNesting = 0;\r
}\r
/*-----------------------------------------------------------*/\r
\r
-void vPortYieldFromISR( void )\r
+void vPortYield( void )\r
{\r
/* Set a PendSV to request a context switch. */\r
portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT;\r
+\r
+ /* Barriers are normally not required but do ensure the code is completely\r
+ within the specified behaviour for the architecture. */\r
+ __dsb( portSY_FULL_READ_WRITE );\r
+ __isb( portSY_FULL_READ_WRITE );\r
}\r
/*-----------------------------------------------------------*/\r
\r
{\r
portDISABLE_INTERRUPTS();\r
uxCriticalNesting++;\r
+ __dsb( portSY_FULL_READ_WRITE );\r
+ __isb( portSY_FULL_READ_WRITE );\r
}\r
/*-----------------------------------------------------------*/\r
\r
}\r
#endif\r
\r
+ /* Only reset the systick load register if configUSE_TICKLESS_IDLE is set to\r
+ 1. If it is set to 0 tickless idle is not being used. If it is set to a\r
+ value other than 0 or 1 then a timer other than the SysTick is being used\r
+ to generate the tick interrupt. */\r
#if configUSE_TICKLESS_IDLE == 1\r
portNVIC_SYSTICK_LOAD_REG = ulTimerReloadValueForOneTick;\r
#endif\r
__weak void vPortSuppressTicksAndSleep( portTickType xExpectedIdleTime )\r
{\r
unsigned long ulReloadValue, ulCompleteTickPeriods, ulCompletedSysTickIncrements;\r
+ portTickType xModifiableIdleTime;\r
\r
/* Make sure the SysTick reload value does not overflow the counter. */\r
if( xExpectedIdleTime > xMaximumPossibleSuppressedTicks )\r
kernel with respect to calendar time. */\r
portNVIC_SYSTICK_CTRL_REG = portNVIC_SYSTICK_CLK_BIT | portNVIC_SYSTICK_INT_BIT;\r
\r
- /* If a context switch is pending then abandon the low power entry as\r
- the context switch might have been pended by an external interrupt that\r
- requires processing. */\r
- if( ( portNVIC_INT_CTRL_REG & portNVIC_PENDSVSET_BIT ) != 0 )\r
+ /* Adjust the reload value to take into account that the current\r
+ time slice is already partially complete. */\r
+ ulReloadValue += ( portNVIC_SYSTICK_LOAD_REG - ( portNVIC_SYSTICK_LOAD_REG - portNVIC_SYSTICK_CURRENT_VALUE_REG ) );\r
+\r
+ /* Enter a critical section but don't use the taskENTER_CRITICAL()\r
+ method as that will mask interrupts that should exit sleep mode. */\r
+ __disable_irq();\r
+\r
+ /* If a context switch is pending or a task is waiting for the scheduler\r
+ to be unsuspended then abandon the low power entry. */\r
+ if( eTaskConfirmSleepModeStatus() == eAbortSleep )\r
{\r
/* Restart SysTick. */\r
portNVIC_SYSTICK_CTRL_REG = portNVIC_SYSTICK_CLK_BIT | portNVIC_SYSTICK_INT_BIT | portNVIC_SYSTICK_ENABLE_BIT;\r
+\r
+ /* Re-enable interrupts - see comments above __disable_irq() call\r
+ above. */\r
+ __enable_irq();\r
}\r
else\r
{\r
- /* Adjust the reload value to take into account that the current\r
- time slice is already partially complete. */\r
- ulReloadValue += ( portNVIC_SYSTICK_LOAD_REG - ( portNVIC_SYSTICK_LOAD_REG - portNVIC_SYSTICK_CURRENT_VALUE_REG ) );\r
+ /* Set the new reload value. */\r
portNVIC_SYSTICK_LOAD_REG = ulReloadValue;\r
\r
/* Clear the SysTick count flag and set the count value back to\r
/* Restart SysTick. */\r
portNVIC_SYSTICK_CTRL_REG = portNVIC_SYSTICK_CLK_BIT | portNVIC_SYSTICK_INT_BIT | portNVIC_SYSTICK_ENABLE_BIT;\r
\r
- /* Sleep until something happens. */\r
- portPRE_SLEEP_PROCESSING();\r
- __wfi();\r
- portPOST_SLEEP_PROCESSING();\r
+ /* Sleep until something happens. configPRE_SLEEP_PROCESSING() can\r
+ set its parameter to 0 to indicate that its implementation contains\r
+ its own wait for interrupt or wait for event instruction, and so wfi\r
+ should not be executed again. However, the original expected idle\r
+ time variable must remain unmodified, so a copy is taken. */\r
+ xModifiableIdleTime = xExpectedIdleTime;\r
+ configPRE_SLEEP_PROCESSING( xModifiableIdleTime );\r
+ if( xModifiableIdleTime > 0 )\r
+ {\r
+ __wfi();\r
+ __dsb( portSY_FULL_READ_WRITE );\r
+ __isb( portSY_FULL_READ_WRITE );\r
+ }\r
+ configPOST_SLEEP_PROCESSING( xExpectedIdleTime );\r
\r
/* Stop SysTick. Again, the time the SysTick is stopped for is\r
accounted for as best it can be, but using the tickless mode will\r
kernel with respect to calendar time. */\r
portNVIC_SYSTICK_CTRL_REG = portNVIC_SYSTICK_CLK_BIT | portNVIC_SYSTICK_INT_BIT;\r
\r
+ /* Re-enable interrupts - see comments above __disable_irq() call\r
+ above. */\r
+ __enable_irq();\r
+\r
if( ( portNVIC_SYSTICK_CTRL_REG & portNVIC_SYSTICK_COUNT_FLAG_BIT ) != 0 )\r
{\r
/* The tick interrupt has already executed, and the SysTick\r
/*-----------------------------------------------------------*/\r
\r
/*\r
- * Setup the systick timer to generate the tick interrupts at the required\r
+ * Setup the SysTick timer to generate the tick interrupts at the required\r
* frequency.\r
*/\r
-void prvSetupTimerInterrupt( void )\r
-{\r
- /* Calculate the constants required to configure the tick interrupt. */\r
- ulTimerReloadValueForOneTick = ( configSYSTICK_CLOCK_HZ / configTICK_RATE_HZ ) - 1UL;\r
- #if configUSE_TICKLESS_IDLE == 1\r
- xMaximumPossibleSuppressedTicks = 0xffffffUL / ( ( configSYSTICK_CLOCK_HZ / configTICK_RATE_HZ ) - 1UL );\r
- #endif /* configUSE_TICKLESS_IDLE */\r
+#if configOVERRIDE_DEFAULT_TICK_CONFIGURATION == 0\r
\r
- /* Configure SysTick to interrupt at the requested rate. */\r
- portNVIC_SYSTICK_LOAD_REG = ulTimerReloadValueForOneTick;\r
- portNVIC_SYSTICK_CTRL_REG = portNVIC_SYSTICK_CLK_BIT | portNVIC_SYSTICK_INT_BIT | portNVIC_SYSTICK_ENABLE_BIT;\r
-}\r
+ void vPortSetupTimerInterrupt( void )\r
+ {\r
+ /* Calculate the constants required to configure the tick interrupt. */\r
+ #if configUSE_TICKLESS_IDLE == 1\r
+ {\r
+ ulTimerReloadValueForOneTick = ( configSYSTICK_CLOCK_HZ / configTICK_RATE_HZ ) - 1UL;\r
+ xMaximumPossibleSuppressedTicks = 0xffffffUL / ( ( configSYSTICK_CLOCK_HZ / configTICK_RATE_HZ ) - 1UL );\r
+ ulStoppedTimerCompensation = 45UL / ( configCPU_CLOCK_HZ / configSYSTICK_CLOCK_HZ );\r
+ }\r
+ #endif /* configUSE_TICKLESS_IDLE */\r
+\r
+ /* Configure SysTick to interrupt at the requested rate. */\r
+ portNVIC_SYSTICK_LOAD_REG = ( configSYSTICK_CLOCK_HZ / configTICK_RATE_HZ ) - 1UL;;\r
+ portNVIC_SYSTICK_CTRL_REG = portNVIC_SYSTICK_CLK_BIT | portNVIC_SYSTICK_INT_BIT | portNVIC_SYSTICK_ENABLE_BIT;\r
+ }\r
+\r
+#endif /* configOVERRIDE_DEFAULT_TICK_CONFIGURATION */\r
/*-----------------------------------------------------------*/\r
\r
__asm unsigned long ulPortSetInterruptMask( void )\r
msr basepri, r1\r
bx r14\r
}\r
-\r
/*-----------------------------------------------------------*/\r
\r
__asm void vPortClearInterruptMask( unsigned long ulNewMask )\r
projects / freertos / blobdiff