/*\r
- FreeRTOS V7.2.0 - Copyright (C) 2012 Real Time Engineers Ltd.\r
- \r
+ FreeRTOS V7.4.2 - Copyright (C) 2013 Real Time Engineers Ltd.\r
+\r
+ FEATURES AND PORTS ARE ADDED TO FREERTOS ALL THE TIME. PLEASE VISIT\r
+ http://www.FreeRTOS.org TO ENSURE YOU ARE USING THE LATEST VERSION.\r
\r
***************************************************************************\r
* *\r
FreeRTOS is free software; you can redistribute it and/or modify it under\r
the terms of the GNU General Public License (version 2) as published by the\r
Free Software Foundation AND MODIFIED BY the FreeRTOS exception.\r
- >>>NOTE<<< The modification to the GPL is included to allow you to\r
+\r
+ >>>>>>NOTE<<<<<< The modification to the GPL is included to allow you to\r
distribute a combined work that includes FreeRTOS without being obliged to\r
provide the source code for proprietary components outside of the FreeRTOS\r
- kernel. FreeRTOS is distributed in the hope that it will be useful, but\r
- WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY\r
- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for\r
- more details. You should have received a copy of the GNU General Public\r
- License and the FreeRTOS license exception along with FreeRTOS; if not it\r
- can be viewed here: http://www.freertos.org/a00114.html and also obtained\r
- by writing to Richard Barry, contact details for whom are available on the\r
- FreeRTOS WEB site.\r
+ kernel.\r
+\r
+ FreeRTOS is distributed in the hope that it will be useful, but WITHOUT ANY\r
+ WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS\r
+ FOR A PARTICULAR PURPOSE. See the GNU General Public License for more\r
+ details. You should have received a copy of the GNU General Public License\r
+ and the FreeRTOS license exception along with FreeRTOS; if not it can be\r
+ viewed here: http://www.freertos.org/a00114.html and also obtained by\r
+ writing to Real Time Engineers Ltd., contact details for whom are available\r
+ on the FreeRTOS WEB site.\r
\r
1 tab == 4 spaces!\r
- \r
+\r
***************************************************************************\r
* *\r
* Having a problem? Start by reading the FAQ "My application does *\r
- * not run, what could be wrong? *\r
+ * not run, what could be wrong?" *\r
* *\r
* http://www.FreeRTOS.org/FAQHelp.html *\r
* *\r
***************************************************************************\r
\r
- \r
- http://www.FreeRTOS.org - Documentation, training, latest information, \r
- license and contact details.\r
- \r
+\r
+ http://www.FreeRTOS.org - Documentation, books, training, latest versions,\r
+ license and Real Time Engineers Ltd. contact details.\r
+\r
http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products,\r
- including FreeRTOS+Trace - an indispensable productivity tool.\r
+ including FreeRTOS+Trace - an indispensable productivity tool, and our new\r
+ fully thread aware and reentrant UDP/IP stack.\r
+\r
+ http://www.OpenRTOS.com - Real Time Engineers ltd license FreeRTOS to High\r
+ Integrity Systems, who sell the code with commercial support,\r
+ indemnification and middleware, under the OpenRTOS brand.\r
\r
- Real Time Engineers ltd license FreeRTOS to High Integrity Systems, who sell \r
- the code with commercial support, indemnification, and middleware, under \r
- the OpenRTOS brand: http://www.OpenRTOS.com. High Integrity Systems also\r
- provide a safety engineered and independently SIL3 certified version under \r
- the SafeRTOS brand: http://www.SafeRTOS.com.\r
+ http://www.SafeRTOS.com - High Integrity Systems also provide a safety\r
+ engineered and independently SIL3 certified version for use in safety and\r
+ mission critical applications that require provable dependability.\r
*/\r
\r
/*-----------------------------------------------------------\r
#include "FreeRTOS.h"\r
#include "task.h"\r
\r
-#ifndef __TARGET_FPU_VFP \r
+#ifndef __TARGET_FPU_VFP\r
#error This port can only be used when the project options are configured to enable hardware floating point support.\r
#endif\r
\r
#error configMAX_SYSCALL_INTERRUPT_PRIORITY must not be set to 0. See http://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html\r
#endif\r
\r
-/* Constants required to manipulate the NVIC. */\r
-#define portNVIC_SYSTICK_CTRL ( ( volatile unsigned long *) 0xe000e010 )\r
-#define portNVIC_SYSTICK_LOAD ( ( volatile unsigned long *) 0xe000e014 )\r
-#define portNVIC_INT_CTRL ( ( volatile unsigned long *) 0xe000ed04 )\r
-#define portNVIC_SYSPRI2 ( ( volatile unsigned long *) 0xe000ed20 )\r
-#define portNVIC_SYSTICK_CLK 0x00000004\r
-#define portNVIC_SYSTICK_INT 0x00000002\r
-#define portNVIC_SYSTICK_ENABLE 0x00000001\r
-#define portNVIC_PENDSVSET 0x10000000\r
-#define portNVIC_PENDSV_PRI ( ( ( unsigned long ) configKERNEL_INTERRUPT_PRIORITY ) << 16 )\r
-#define portNVIC_SYSTICK_PRI ( ( ( unsigned long ) configKERNEL_INTERRUPT_PRIORITY ) << 24 )\r
+#ifndef configSYSTICK_CLOCK_HZ\r
+ #define configSYSTICK_CLOCK_HZ configCPU_CLOCK_HZ\r
+#endif\r
+\r
+/* The __weak attribute does not work as you might expect with the Keil tools\r
+so the configOVERRIDE_DEFAULT_TICK_CONFIGURATION constant must be set to 1 if\r
+the application writer wants to provide their own implementation of\r
+vPortSetupTimerInterrupt(). Ensure configOVERRIDE_DEFAULT_TICK_CONFIGURATION\r
+is defined. */\r
+#ifndef configOVERRIDE_DEFAULT_TICK_CONFIGURATION\r
+ #define configOVERRIDE_DEFAULT_TICK_CONFIGURATION 0\r
+#endif\r
+\r
+/* Constants required to manipulate the core. Registers first... */\r
+#define portNVIC_SYSTICK_CTRL_REG ( * ( ( volatile unsigned long * ) 0xe000e010 ) )\r
+#define portNVIC_SYSTICK_LOAD_REG ( * ( ( volatile unsigned long * ) 0xe000e014 ) )\r
+#define portNVIC_SYSTICK_CURRENT_VALUE_REG ( * ( ( volatile unsigned long * ) 0xe000e018 ) )\r
+#define portNVIC_SYSPRI2_REG ( * ( ( volatile unsigned long * ) 0xe000ed20 ) )\r
+/* ...then bits in the registers. */\r
+#define portNVIC_SYSTICK_CLK_BIT ( 1UL << 2UL )\r
+#define portNVIC_SYSTICK_INT_BIT ( 1UL << 1UL )\r
+#define portNVIC_SYSTICK_ENABLE_BIT ( 1UL << 0UL )\r
+#define portNVIC_SYSTICK_COUNT_FLAG_BIT ( 1UL << 16UL )\r
+#define portNVIC_PENDSVCLEAR_BIT ( 1UL << 27UL )\r
+#define portNVIC_PEND_SYSTICK_CLEAR_BIT ( 1UL << 25UL )\r
+\r
+#define portNVIC_PENDSV_PRI ( ( ( unsigned long ) configKERNEL_INTERRUPT_PRIORITY ) << 16 )\r
+#define portNVIC_SYSTICK_PRI ( ( ( unsigned long ) configKERNEL_INTERRUPT_PRIORITY ) << 24 )\r
\r
/* Constants required to manipulate the VFP. */\r
#define portFPCCR ( ( volatile unsigned long * ) 0xe000ef34 ) /* Floating point context control register. */\r
#define portINITIAL_XPSR ( 0x01000000 )\r
#define portINITIAL_EXEC_RETURN ( 0xfffffffd )\r
\r
+/* Constants used with memory barrier intrinsics. */\r
+#define portSY_FULL_READ_WRITE ( 15 )\r
+\r
/* Each task maintains its own interrupt status in the critical nesting\r
variable. */\r
static unsigned portBASE_TYPE uxCriticalNesting = 0xaaaaaaaa;\r
\r
-/* \r
- * Setup the timer to generate the tick interrupts.\r
+/*\r
+ * Setup the timer to generate the tick interrupts. The implementation in this\r
+ * file is weak to allow application writers to change the timer used to\r
+ * generate the tick interrupt.\r
*/\r
-static void prvSetupTimerInterrupt( void );\r
+void vPortSetupTimerInterrupt( void );\r
\r
/*\r
* Exception handlers.\r
* Functions defined in portasm.s to enable the VFP.\r
*/\r
static void prvEnableVFP( void );\r
+/*-----------------------------------------------------------*/\r
+\r
+/*\r
+ * The number of SysTick increments that make up one tick period.\r
+ */\r
+#if configUSE_TICKLESS_IDLE == 1\r
+ static unsigned long ulTimerReloadValueForOneTick = 0;\r
+#endif\r
+\r
+/*\r
+ * The maximum number of tick periods that can be suppressed is limited by the\r
+ * 24 bit resolution of the SysTick timer.\r
+ */\r
+#if configUSE_TICKLESS_IDLE == 1\r
+ static unsigned long xMaximumPossibleSuppressedTicks = 0;\r
+#endif /* configUSE_TICKLESS_IDLE */\r
+\r
+/*\r
+ * Compensate for the CPU cycles that pass while the SysTick is stopped (low\r
+ * power functionality only.\r
+ */\r
+#if configUSE_TICKLESS_IDLE == 1\r
+ static unsigned long ulStoppedTimerCompensation = 0;\r
+#endif /* configUSE_TICKLESS_IDLE */\r
\r
/*-----------------------------------------------------------*/\r
\r
-/* \r
- * See header file for description. \r
+/*\r
+ * See header file for description.\r
*/\r
portSTACK_TYPE *pxPortInitialiseStack( portSTACK_TYPE *pxTopOfStack, pdTASK_CODE pxCode, void *pvParameters )\r
{\r
/* Simulate the stack frame as it would be created by a context switch\r
interrupt. */\r
- \r
+\r
/* Offset added to account for the way the MCU uses the stack on entry/exit\r
of interrupts, and to ensure alignment. */\r
pxTopOfStack--;\r
- \r
+\r
*pxTopOfStack = portINITIAL_XPSR; /* xPSR */\r
pxTopOfStack--;\r
*pxTopOfStack = ( portSTACK_TYPE ) pxCode; /* PC */\r
pxTopOfStack--;\r
*pxTopOfStack = 0; /* LR */\r
- \r
+\r
/* Save code space by skipping register initialisation. */\r
pxTopOfStack -= 5; /* R12, R3, R2 and R1. */\r
*pxTopOfStack = ( portSTACK_TYPE ) pvParameters; /* R0 */\r
*pxTopOfStack = portINITIAL_EXEC_RETURN;\r
\r
pxTopOfStack -= 8; /* R11, R10, R9, R8, R7, R6, R5 and R4. */\r
- \r
+\r
return pxTopOfStack;\r
}\r
/*-----------------------------------------------------------*/\r
ldmia r0!, {r4-r11, r14}\r
msr psp, r0\r
mov r0, #0\r
- msr basepri, r0 \r
+ msr basepri, r0\r
bx r14\r
}\r
/*-----------------------------------------------------------*/\r
__asm void prvEnableVFP( void )\r
{\r
PRESERVE8\r
- \r
+\r
/* The FPU enable bits are in the CPACR. */\r
ldr.w r0, =0xE000ED88\r
ldr r1, [r0]\r
- \r
+\r
/* Enable CP10 and CP11 coprocessors, then save back. */\r
orr r1, r1, #( 0xf << 20 )\r
str r1, [r0]\r
- bx r14 \r
+ bx r14\r
nop\r
}\r
/*-----------------------------------------------------------*/\r
\r
-/* \r
- * See header file for description. \r
+/*\r
+ * See header file for description.\r
*/\r
portBASE_TYPE xPortStartScheduler( void )\r
{\r
/* Make PendSV, CallSV and SysTick the same priroity as the kernel. */\r
- *(portNVIC_SYSPRI2) |= portNVIC_PENDSV_PRI;\r
- *(portNVIC_SYSPRI2) |= portNVIC_SYSTICK_PRI;\r
+ portNVIC_SYSPRI2_REG |= portNVIC_PENDSV_PRI;\r
+ portNVIC_SYSPRI2_REG |= portNVIC_SYSTICK_PRI;\r
\r
/* Start the timer that generates the tick ISR. Interrupts are disabled\r
here already. */\r
- prvSetupTimerInterrupt();\r
- \r
+ vPortSetupTimerInterrupt();\r
+\r
/* Initialise the critical nesting count ready for the first task. */\r
uxCriticalNesting = 0;\r
\r
/* Ensure the VFP is enabled - it should be anyway. */\r
prvEnableVFP();\r
- \r
+\r
/* Lazy save always. */\r
*( portFPCCR ) |= portASPEN_AND_LSPEN_BITS;\r
- \r
+\r
/* Start the first task. */\r
prvStartFirstTask();\r
\r
}\r
/*-----------------------------------------------------------*/\r
\r
-void vPortYieldFromISR( void )\r
+void vPortYield( void )\r
{\r
/* Set a PendSV to request a context switch. */\r
- *(portNVIC_INT_CTRL) = portNVIC_PENDSVSET;\r
+ portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT;\r
+\r
+ /* Barriers are normally not required but do ensure the code is completely\r
+ within the specified behaviour for the architecture. */\r
+ __dsb( portSY_FULL_READ_WRITE );\r
+ __isb( portSY_FULL_READ_WRITE );\r
}\r
/*-----------------------------------------------------------*/\r
\r
{\r
portDISABLE_INTERRUPTS();\r
uxCriticalNesting++;\r
+ __dsb( portSY_FULL_READ_WRITE );\r
+ __isb( portSY_FULL_READ_WRITE );\r
}\r
/*-----------------------------------------------------------*/\r
\r
\r
PRESERVE8\r
\r
- mrs r0, psp \r
- \r
+ mrs r0, psp\r
+\r
/* Get the location of the current TCB. */\r
- ldr r3, =pxCurrentTCB \r
- ldr r2, [r3] \r
+ ldr r3, =pxCurrentTCB\r
+ ldr r2, [r3]\r
\r
/* Is the task using the FPU context? If so, push high vfp registers. */\r
tst r14, #0x10\r
vstmdbeq r0!, {s16-s31}\r
\r
/* Save the core registers. */\r
- stmdb r0!, {r4-r11, r14} \r
- \r
+ stmdb r0!, {r4-r11, r14}\r
+\r
/* Save the new top of stack into the first member of the TCB. */\r
str r0, [r2]\r
- \r
+\r
stmdb sp!, {r3, r14}\r
mov r0, #configMAX_SYSCALL_INTERRUPT_PRIORITY\r
msr basepri, r0\r
- bl vTaskSwitchContext \r
+ bl vTaskSwitchContext\r
mov r0, #0\r
msr basepri, r0\r
ldmia sp!, {r3, r14}\r
\r
/* The first item in pxCurrentTCB is the task top of stack. */\r
- ldr r1, [r3] \r
+ ldr r1, [r3]\r
ldr r0, [r1]\r
- \r
+\r
/* Pop the core registers. */\r
ldmia r0!, {r4-r11, r14}\r
\r
- /* Is the task using the FPU context? If so, pop the high vfp registers \r
+ /* Is the task using the FPU context? If so, pop the high vfp registers\r
too. */\r
tst r14, #0x10\r
it eq\r
vldmiaeq r0!, {s16-s31}\r
- \r
- msr psp, r0 \r
- bx r14 \r
- nop \r
+\r
+ msr psp, r0\r
+ bx r14\r
+ nop\r
}\r
/*-----------------------------------------------------------*/\r
\r
void xPortSysTickHandler( void )\r
{\r
-unsigned long ulDummy;\r
-\r
- /* If using preemption, also force a context switch. */\r
#if configUSE_PREEMPTION == 1\r
- *(portNVIC_INT_CTRL) = portNVIC_PENDSVSET; \r
+ {\r
+ /* If using preemption, also force a context switch. */\r
+ portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT;\r
+ }\r
+ #endif\r
+\r
+ /* Only reset the systick load register if configUSE_TICKLESS_IDLE is set to\r
+ 1. If it is set to 0 tickless idle is not being used. If it is set to a\r
+ value other than 0 or 1 then a timer other than the SysTick is being used\r
+ to generate the tick interrupt. */\r
+ #if configUSE_TICKLESS_IDLE == 1\r
+ portNVIC_SYSTICK_LOAD_REG = ulTimerReloadValueForOneTick;\r
#endif\r
\r
- ulDummy = portSET_INTERRUPT_MASK_FROM_ISR();\r
+ ( void ) portSET_INTERRUPT_MASK_FROM_ISR();\r
{\r
vTaskIncrementTick();\r
}\r
- portCLEAR_INTERRUPT_MASK_FROM_ISR( ulDummy );\r
+ portCLEAR_INTERRUPT_MASK_FROM_ISR( 0 );\r
}\r
/*-----------------------------------------------------------*/\r
\r
+#if configUSE_TICKLESS_IDLE == 1\r
+\r
+ __weak void vPortSuppressTicksAndSleep( portTickType xExpectedIdleTime )\r
+ {\r
+ unsigned long ulReloadValue, ulCompleteTickPeriods, ulCompletedSysTickIncrements;\r
+ portTickType xModifiableIdleTime;\r
+\r
+ /* Make sure the SysTick reload value does not overflow the counter. */\r
+ if( xExpectedIdleTime > xMaximumPossibleSuppressedTicks )\r
+ {\r
+ xExpectedIdleTime = xMaximumPossibleSuppressedTicks;\r
+ }\r
+\r
+ /* Calculate the reload value required to wait xExpectedIdleTime\r
+ tick periods. -1 is used because this code will execute part way\r
+ through one of the tick periods, and the fraction of a tick period is\r
+ accounted for later. */\r
+ ulReloadValue = ( ulTimerReloadValueForOneTick * ( xExpectedIdleTime - 1UL ) );\r
+ if( ulReloadValue > ulStoppedTimerCompensation )\r
+ {\r
+ ulReloadValue -= ulStoppedTimerCompensation;\r
+ }\r
+\r
+ /* Stop the SysTick momentarily. The time the SysTick is stopped for\r
+ is accounted for as best it can be, but using the tickless mode will\r
+ inevitably result in some tiny drift of the time maintained by the\r
+ kernel with respect to calendar time. */\r
+ portNVIC_SYSTICK_CTRL_REG = portNVIC_SYSTICK_CLK_BIT | portNVIC_SYSTICK_INT_BIT;\r
+\r
+ /* Adjust the reload value to take into account that the current\r
+ time slice is already partially complete. */\r
+ ulReloadValue += ( portNVIC_SYSTICK_LOAD_REG - ( portNVIC_SYSTICK_LOAD_REG - portNVIC_SYSTICK_CURRENT_VALUE_REG ) );\r
+\r
+ /* Enter a critical section but don't use the taskENTER_CRITICAL()\r
+ method as that will mask interrupts that should exit sleep mode. */\r
+ __disable_irq();\r
+\r
+ /* If a context switch is pending or a task is waiting for the scheduler\r
+ to be unsuspended then abandon the low power entry. */\r
+ if( eTaskConfirmSleepModeStatus() == eAbortSleep )\r
+ {\r
+ /* Restart SysTick. */\r
+ portNVIC_SYSTICK_CTRL_REG = portNVIC_SYSTICK_CLK_BIT | portNVIC_SYSTICK_INT_BIT | portNVIC_SYSTICK_ENABLE_BIT;\r
+\r
+ /* Re-enable interrupts - see comments above __disable_irq() call\r
+ above. */\r
+ __enable_irq();\r
+ }\r
+ else\r
+ {\r
+ /* Set the new reload value. */\r
+ portNVIC_SYSTICK_LOAD_REG = ulReloadValue;\r
+\r
+ /* Clear the SysTick count flag and set the count value back to\r
+ zero. */\r
+ portNVIC_SYSTICK_CURRENT_VALUE_REG = 0UL;\r
+\r
+ /* Restart SysTick. */\r
+ portNVIC_SYSTICK_CTRL_REG = portNVIC_SYSTICK_CLK_BIT | portNVIC_SYSTICK_INT_BIT | portNVIC_SYSTICK_ENABLE_BIT;\r
+\r
+ /* Sleep until something happens. configPRE_SLEEP_PROCESSING() can\r
+ set its parameter to 0 to indicate that its implementation contains\r
+ its own wait for interrupt or wait for event instruction, and so wfi\r
+ should not be executed again. However, the original expected idle\r
+ time variable must remain unmodified, so a copy is taken. */\r
+ xModifiableIdleTime = xExpectedIdleTime;\r
+ configPRE_SLEEP_PROCESSING( xModifiableIdleTime );\r
+ if( xModifiableIdleTime > 0 )\r
+ {\r
+ __wfi();\r
+ __dsb( portSY_FULL_READ_WRITE );\r
+ __isb( portSY_FULL_READ_WRITE );\r
+ }\r
+ configPOST_SLEEP_PROCESSING( xExpectedIdleTime );\r
+\r
+ /* Stop SysTick. Again, the time the SysTick is stopped for is\r
+ accounted for as best it can be, but using the tickless mode will\r
+ inevitably result in some tiny drift of the time maintained by the\r
+ kernel with respect to calendar time. */\r
+ portNVIC_SYSTICK_CTRL_REG = portNVIC_SYSTICK_CLK_BIT | portNVIC_SYSTICK_INT_BIT;\r
+\r
+ /* Re-enable interrupts - see comments above __disable_irq() call\r
+ above. */\r
+ __enable_irq();\r
+\r
+ if( ( portNVIC_SYSTICK_CTRL_REG & portNVIC_SYSTICK_COUNT_FLAG_BIT ) != 0 )\r
+ {\r
+ /* The tick interrupt has already executed, and the SysTick\r
+ count reloaded with the portNVIC_SYSTICK_LOAD_REG value.\r
+ Reset the portNVIC_SYSTICK_LOAD_REG with whatever remains of\r
+ this tick period. */\r
+ portNVIC_SYSTICK_LOAD_REG = ulTimerReloadValueForOneTick - ( ulReloadValue - portNVIC_SYSTICK_CURRENT_VALUE_REG );\r
+\r
+ /* The tick interrupt handler will already have pended the tick\r
+ processing in the kernel. As the pending tick will be\r
+ processed as soon as this function exits, the tick value\r
+ maintained by the tick is stepped forward by one less than the\r
+ time spent waiting. */\r
+ ulCompleteTickPeriods = xExpectedIdleTime - 1UL;\r
+ }\r
+ else\r
+ {\r
+ /* Something other than the tick interrupt ended the sleep.\r
+ Work out how long the sleep lasted. */\r
+ ulCompletedSysTickIncrements = ( xExpectedIdleTime * ulTimerReloadValueForOneTick ) - portNVIC_SYSTICK_CURRENT_VALUE_REG;\r
+\r
+ /* How many complete tick periods passed while the processor\r
+ was waiting? */\r
+ ulCompleteTickPeriods = ulCompletedSysTickIncrements / ulTimerReloadValueForOneTick;\r
+\r
+ /* The reload value is set to whatever fraction of a single tick\r
+ period remains. */\r
+ portNVIC_SYSTICK_LOAD_REG = ( ( ulCompleteTickPeriods + 1 ) * ulTimerReloadValueForOneTick ) - ulCompletedSysTickIncrements;\r
+ }\r
+\r
+ /* Restart SysTick so it runs from portNVIC_SYSTICK_LOAD_REG\r
+ again, then set portNVIC_SYSTICK_LOAD_REG back to its standard\r
+ value. */\r
+ portNVIC_SYSTICK_CURRENT_VALUE_REG = 0UL;\r
+ portNVIC_SYSTICK_CTRL_REG = portNVIC_SYSTICK_CLK_BIT | portNVIC_SYSTICK_INT_BIT | portNVIC_SYSTICK_ENABLE_BIT;\r
+\r
+ vTaskStepTick( ulCompleteTickPeriods );\r
+ }\r
+ }\r
+\r
+#endif /* #if configUSE_TICKLESS_IDLE */\r
+\r
+/*-----------------------------------------------------------*/\r
+\r
/*\r
- * Setup the systick timer to generate the tick interrupts at the required\r
+ * Setup the SysTick timer to generate the tick interrupts at the required\r
* frequency.\r
*/\r
-void prvSetupTimerInterrupt( void )\r
-{\r
- /* Configure SysTick to interrupt at the requested rate. */\r
- *(portNVIC_SYSTICK_LOAD) = ( configCPU_CLOCK_HZ / configTICK_RATE_HZ ) - 1UL;\r
- *(portNVIC_SYSTICK_CTRL) = portNVIC_SYSTICK_CLK | portNVIC_SYSTICK_INT | portNVIC_SYSTICK_ENABLE;\r
-}\r
+#if configOVERRIDE_DEFAULT_TICK_CONFIGURATION == 0\r
+\r
+ void vPortSetupTimerInterrupt( void )\r
+ {\r
+ /* Calculate the constants required to configure the tick interrupt. */\r
+ #if configUSE_TICKLESS_IDLE == 1\r
+ {\r
+ ulTimerReloadValueForOneTick = ( configSYSTICK_CLOCK_HZ / configTICK_RATE_HZ ) - 1UL;\r
+ xMaximumPossibleSuppressedTicks = 0xffffffUL / ( ( configSYSTICK_CLOCK_HZ / configTICK_RATE_HZ ) - 1UL );\r
+ ulStoppedTimerCompensation = 45UL / ( configCPU_CLOCK_HZ / configSYSTICK_CLOCK_HZ );\r
+ }\r
+ #endif /* configUSE_TICKLESS_IDLE */\r
+\r
+ /* Configure SysTick to interrupt at the requested rate. */\r
+ portNVIC_SYSTICK_LOAD_REG = ( configSYSTICK_CLOCK_HZ / configTICK_RATE_HZ ) - 1UL;;\r
+ portNVIC_SYSTICK_CTRL_REG = portNVIC_SYSTICK_CLK_BIT | portNVIC_SYSTICK_INT_BIT | portNVIC_SYSTICK_ENABLE_BIT;\r
+ }\r
+\r
+#endif /* configOVERRIDE_DEFAULT_TICK_CONFIGURATION */\r
/*-----------------------------------------------------------*/\r
\r
-__asm void vPortSetInterruptMask( void )\r
+__asm unsigned long ulPortSetInterruptMask( void )\r
{\r
PRESERVE8\r
\r
- mov r0, #configMAX_SYSCALL_INTERRUPT_PRIORITY\r
- msr basepri, r0\r
+ mrs r0, basepri\r
+ mov r1, #configMAX_SYSCALL_INTERRUPT_PRIORITY\r
+ msr basepri, r1\r
bx r14\r
}\r
-\r
/*-----------------------------------------------------------*/\r
\r
-__asm void vPortClearInterruptMask( void )\r
+__asm void vPortClearInterruptMask( unsigned long ulNewMask )\r
{\r
PRESERVE8\r
\r
- /* FAQ: Setting BASEPRI to 0 is not a bug. Please see \r
- http://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html before disagreeing. */\r
- mov r0, #0\r
msr basepri, r0\r
bx r14\r
}\r
projects / freertos / blobdiff