/*\r
- FreeRTOS V7.2.0 - Copyright (C) 2012 Real Time Engineers Ltd.\r
- \r
-\r
- ***************************************************************************\r
- * *\r
- * FreeRTOS tutorial books are available in pdf and paperback. *\r
- * Complete, revised, and edited pdf reference manuals are also *\r
- * available. *\r
- * *\r
- * Purchasing FreeRTOS documentation will not only help you, by *\r
- * ensuring you get running as quickly as possible and with an *\r
- * in-depth knowledge of how to use FreeRTOS, it will also help *\r
- * the FreeRTOS project to continue with its mission of providing *\r
- * professional grade, cross platform, de facto standard solutions *\r
- * for microcontrollers - completely free of charge! *\r
- * *\r
- * >>> See http://www.FreeRTOS.org/Documentation for details. <<< *\r
- * *\r
- * Thank you for using FreeRTOS, and thank you for your support! *\r
- * *\r
- ***************************************************************************\r
-\r
-\r
- This file is part of the FreeRTOS distribution.\r
-\r
- FreeRTOS is free software; you can redistribute it and/or modify it under\r
- the terms of the GNU General Public License (version 2) as published by the\r
- Free Software Foundation AND MODIFIED BY the FreeRTOS exception.\r
- >>>NOTE<<< The modification to the GPL is included to allow you to\r
- distribute a combined work that includes FreeRTOS without being obliged to\r
- provide the source code for proprietary components outside of the FreeRTOS\r
- kernel. FreeRTOS is distributed in the hope that it will be useful, but\r
- WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY\r
- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for\r
- more details. You should have received a copy of the GNU General Public\r
- License and the FreeRTOS license exception along with FreeRTOS; if not it\r
- can be viewed here: http://www.freertos.org/a00114.html and also obtained\r
- by writing to Richard Barry, contact details for whom are available on the\r
- FreeRTOS WEB site.\r
-\r
- 1 tab == 4 spaces!\r
- \r
- ***************************************************************************\r
- * *\r
- * Having a problem? Start by reading the FAQ "My application does *\r
- * not run, what could be wrong? *\r
- * *\r
- * http://www.FreeRTOS.org/FAQHelp.html *\r
- * *\r
- ***************************************************************************\r
-\r
- \r
- http://www.FreeRTOS.org - Documentation, training, latest information, \r
- license and contact details.\r
- \r
- http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products,\r
- including FreeRTOS+Trace - an indispensable productivity tool.\r
-\r
- Real Time Engineers ltd license FreeRTOS to High Integrity Systems, who sell \r
- the code with commercial support, indemnification, and middleware, under \r
- the OpenRTOS brand: http://www.OpenRTOS.com. High Integrity Systems also\r
- provide a safety engineered and independently SIL3 certified version under \r
- the SafeRTOS brand: http://www.SafeRTOS.com.\r
-*/\r
+ * FreeRTOS Kernel V10.3.0\r
+ * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved.\r
+ *\r
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of\r
+ * this software and associated documentation files (the "Software"), to deal in\r
+ * the Software without restriction, including without limitation the rights to\r
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of\r
+ * the Software, and to permit persons to whom the Software is furnished to do so,\r
+ * subject to the following conditions:\r
+ *\r
+ * The above copyright notice and this permission notice shall be included in all\r
+ * copies or substantial portions of the Software.\r
+ *\r
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR\r
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS\r
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR\r
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER\r
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN\r
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.\r
+ *\r
+ * http://www.FreeRTOS.org\r
+ * http://aws.amazon.com/freertos\r
+ *\r
+ * 1 tab == 4 spaces!\r
+ */\r
\r
\r
#ifndef PORTMACRO_H\r
#endif\r
\r
/*-----------------------------------------------------------\r
- * Port specific definitions. \r
+ * Port specific definitions.\r
*\r
* The settings in this file configure FreeRTOS correctly for the\r
* given hardware and compiler.\r
#define portDOUBLE double\r
#define portLONG long\r
#define portSHORT short\r
-#define portSTACK_TYPE unsigned portLONG\r
+#define portSTACK_TYPE uint32_t\r
#define portBASE_TYPE long\r
\r
+typedef portSTACK_TYPE StackType_t;\r
+typedef long BaseType_t;\r
+typedef unsigned long UBaseType_t;\r
+\r
#if( configUSE_16_BIT_TICKS == 1 )\r
- typedef unsigned portSHORT portTickType;\r
- #define portMAX_DELAY ( portTickType ) 0xffff\r
+ typedef uint16_t TickType_t;\r
+ #define portMAX_DELAY ( TickType_t ) 0xffff\r
#else\r
- typedef unsigned portLONG portTickType;\r
- #define portMAX_DELAY ( portTickType ) 0xffffffff\r
+ typedef uint32_t TickType_t;\r
+ #define portMAX_DELAY ( TickType_t ) 0xffffffffUL\r
+\r
+ /* 32-bit tick type on a 32-bit architecture, so reads of the tick count do\r
+ not need to be guarded with a critical section. */\r
+ #define portTICK_TYPE_IS_ATOMIC 1\r
#endif\r
-/*-----------------------------------------------------------*/ \r
+/*-----------------------------------------------------------*/\r
\r
/* Architecture specifics. */\r
#define portSTACK_GROWTH ( -1 )\r
-#define portTICK_RATE_MS ( ( portTickType ) 1000 / configTICK_RATE_HZ ) \r
+#define portTICK_PERIOD_MS ( ( TickType_t ) 1000 / configTICK_RATE_HZ )\r
#define portBYTE_ALIGNMENT 8\r
-/*-----------------------------------------------------------*/ \r
+\r
+/* Constants used with memory barrier intrinsics. */\r
+#define portSY_FULL_READ_WRITE ( 15 )\r
+\r
+/*-----------------------------------------------------------*/\r
\r
/* Scheduler utilities. */\r
-extern void vPortYield( void );\r
-extern void vPortYieldFromISR( void );\r
-#define portYIELD() vPortYieldFromISR()\r
-#define portEND_SWITCHING_ISR( xSwitchRequired ) if( xSwitchRequired ) vPortYieldFromISR()\r
+#define portYIELD() \\r
+{ \\r
+ /* Set a PendSV to request a context switch. */ \\r
+ portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT; \\r
+ \\r
+ /* Barriers are normally not required but do ensure the code is completely \\r
+ within the specified behaviour for the architecture. */ \\r
+ __dsb( portSY_FULL_READ_WRITE ); \\r
+ __isb( portSY_FULL_READ_WRITE ); \\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+#define portNVIC_INT_CTRL_REG ( * ( ( volatile uint32_t * ) 0xe000ed04 ) )\r
+#define portNVIC_PENDSVSET_BIT ( 1UL << 28UL )\r
+#define portEND_SWITCHING_ISR( xSwitchRequired ) if( xSwitchRequired != pdFALSE ) portYIELD()\r
+#define portYIELD_FROM_ISR( x ) portEND_SWITCHING_ISR( x )\r
/*-----------------------------------------------------------*/\r
\r
/* Critical section management. */\r
-extern unsigned long ulPortSetInterruptMask( void );\r
-extern void vPortClearInterruptMask( unsigned long ulNewMask );\r
extern void vPortEnterCritical( void );\r
extern void vPortExitCritical( void );\r
\r
-#define portDISABLE_INTERRUPTS() ulPortSetInterruptMask()\r
-#define portENABLE_INTERRUPTS() vPortClearInterruptMask( 0 )\r
+#define portDISABLE_INTERRUPTS() vPortRaiseBASEPRI()\r
+#define portENABLE_INTERRUPTS() vPortSetBASEPRI( 0 )\r
#define portENTER_CRITICAL() vPortEnterCritical()\r
#define portEXIT_CRITICAL() vPortExitCritical()\r
-#define portSET_INTERRUPT_MASK_FROM_ISR() ulPortSetInterruptMask()\r
-#define portCLEAR_INTERRUPT_MASK_FROM_ISR(x) vPortClearInterruptMask(x)\r
-\r
-/*-----------------------------------------------------------*/\r
+#define portSET_INTERRUPT_MASK_FROM_ISR() ulPortRaiseBASEPRI()\r
+#define portCLEAR_INTERRUPT_MASK_FROM_ISR(x) vPortSetBASEPRI(x)\r
\r
-/* There are an uneven number of items on the initial stack, so \r
-portALIGNMENT_ASSERT_pxCurrentTCB() will trigger false positive asserts. */\r
-#define portALIGNMENT_ASSERT_pxCurrentTCB ( void )\r
/*-----------------------------------------------------------*/\r
\r
-/* Tickless/low power optimisations. */\r
-extern void vPortSuppressTicksAndSleep( portTickType xExpectedIdleTime );\r
-#define portSUPPRESS_TICKS_AND_SLEEP( xExpectedIdleTime ) vPortSuppressTicksAndSleep( xExpectedIdleTime )\r
+/* Tickless idle/low power functionality. */\r
+#ifndef portSUPPRESS_TICKS_AND_SLEEP\r
+ extern void vPortSuppressTicksAndSleep( TickType_t xExpectedIdleTime );\r
+ #define portSUPPRESS_TICKS_AND_SLEEP( xExpectedIdleTime ) vPortSuppressTicksAndSleep( xExpectedIdleTime )\r
+#endif\r
/*-----------------------------------------------------------*/\r
\r
/* Port specific optimisations. */\r
+#ifndef configUSE_PORT_OPTIMISED_TASK_SELECTION\r
+ #define configUSE_PORT_OPTIMISED_TASK_SELECTION 1\r
+#endif\r
+\r
#if configUSE_PORT_OPTIMISED_TASK_SELECTION == 1\r
\r
/* Check the configuration. */\r
\r
/*-----------------------------------------------------------*/\r
\r
- #define portGET_HIGHEST_PRIORITY( uxTopPriority, uxReadyPriorities ) uxTopPriority = ( 31 - __clz( ( uxReadyPriorities ) ) )\r
+ #define portGET_HIGHEST_PRIORITY( uxTopPriority, uxReadyPriorities ) uxTopPriority = ( 31UL - ( uint32_t ) __clz( ( uxReadyPriorities ) ) )\r
\r
#endif /* taskRECORD_READY_PRIORITY */\r
/*-----------------------------------------------------------*/\r
#define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void *pvParameters )\r
/*-----------------------------------------------------------*/\r
\r
+#ifdef configASSERT\r
+ void vPortValidateInterruptPriority( void );\r
+ #define portASSERT_IF_INTERRUPT_PRIORITY_INVALID() vPortValidateInterruptPriority()\r
+#endif\r
+\r
/* portNOP() is not required by this port. */\r
#define portNOP()\r
\r
+#define portINLINE __inline\r
+\r
+#ifndef portFORCE_INLINE\r
+ #define portFORCE_INLINE __forceinline\r
+#endif\r
+\r
+/*-----------------------------------------------------------*/\r
+\r
+static portFORCE_INLINE void vPortSetBASEPRI( uint32_t ulBASEPRI )\r
+{\r
+ __asm\r
+ {\r
+ /* Barrier instructions are not used as this function is only used to\r
+ lower the BASEPRI value. */\r
+ msr basepri, ulBASEPRI\r
+ }\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+static portFORCE_INLINE void vPortRaiseBASEPRI( void )\r
+{\r
+uint32_t ulNewBASEPRI = configMAX_SYSCALL_INTERRUPT_PRIORITY;\r
+\r
+ __asm\r
+ {\r
+ /* Set BASEPRI to the max syscall priority to effect a critical\r
+ section. */\r
+ msr basepri, ulNewBASEPRI\r
+ dsb\r
+ isb\r
+ }\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+static portFORCE_INLINE void vPortClearBASEPRIFromISR( void )\r
+{\r
+ __asm\r
+ {\r
+ /* Set BASEPRI to 0 so no interrupts are masked. This function is only\r
+ used to lower the mask in an interrupt, so memory barriers are not \r
+ used. */\r
+ msr basepri, #0\r
+ }\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+static portFORCE_INLINE uint32_t ulPortRaiseBASEPRI( void )\r
+{\r
+uint32_t ulReturn, ulNewBASEPRI = configMAX_SYSCALL_INTERRUPT_PRIORITY;\r
+\r
+ __asm\r
+ {\r
+ /* Set BASEPRI to the max syscall priority to effect a critical\r
+ section. */\r
+ mrs ulReturn, basepri\r
+ msr basepri, ulNewBASEPRI\r
+ dsb\r
+ isb\r
+ }\r
+\r
+ return ulReturn;\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+static portFORCE_INLINE BaseType_t xPortIsInsideInterrupt( void )\r
+{\r
+uint32_t ulCurrentInterrupt;\r
+BaseType_t xReturn;\r
+\r
+ /* Obtain the number of the currently executing interrupt. */\r
+ __asm\r
+ {\r
+ mrs ulCurrentInterrupt, ipsr\r
+ }\r
+\r
+ if( ulCurrentInterrupt == 0 )\r
+ {\r
+ xReturn = pdFALSE;\r
+ }\r
+ else\r
+ {\r
+ xReturn = pdTRUE;\r
+ }\r
+\r
+ return xReturn;\r
+}\r
+\r
+\r
#ifdef __cplusplus\r
}\r
#endif\r
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