X-Git-Url: https://git.sur5r.net/?p=freertos;a=blobdiff_plain;f=FreeRTOS%2FDemo%2FCORTEX_MPU_M33F_NXP_LPC55S69_MCUXpresso%2FNXP_Code%2Fdrivers%2Ffsl_reset.h;h=0139b15dc9b14ae38d8e95acf526e5c2d9c62b57;hp=f59f59e33c7d1ae0f0de7bfcd4637d71d7c96e55;hb=584c29e09cf7a95184b0e32718e8f711b781ffea;hpb=c5efd011e8c638d413ac395419119a451a0cb169 diff --git a/FreeRTOS/Demo/CORTEX_MPU_M33F_NXP_LPC55S69_MCUXpresso/NXP_Code/drivers/fsl_reset.h b/FreeRTOS/Demo/CORTEX_MPU_M33F_NXP_LPC55S69_MCUXpresso/NXP_Code/drivers/fsl_reset.h index f59f59e33..0139b15dc 100644 --- a/FreeRTOS/Demo/CORTEX_MPU_M33F_NXP_LPC55S69_MCUXpresso/NXP_Code/drivers/fsl_reset.h +++ b/FreeRTOS/Demo/CORTEX_MPU_M33F_NXP_LPC55S69_MCUXpresso/NXP_Code/drivers/fsl_reset.h @@ -1,6 +1,6 @@ /* * Copyright (c) 2016, Freescale Semiconductor, Inc. - * Copyright (c) 2016, NXP + * Copyright 2016, NXP * All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause @@ -26,8 +26,8 @@ /*! @name Driver version */ /*@{*/ -/*! @brief reset driver version 2.0.0. */ -#define FSL_RESET_DRIVER_VERSION (MAKE_VERSION(2, 0, 0)) +/*! @brief reset driver version 2.0.2. */ +#define FSL_RESET_DRIVER_VERSION (MAKE_VERSION(2, 0, 2)) /*@}*/ /*! @@ -37,78 +37,78 @@ */ typedef enum _SYSCON_RSTn { - kROM_RST_SHIFT_RSTn = 0 | 1U, /**< ROM reset control */ - kSRAM1_RST_SHIFT_RSTn = 0 | 3U, /**< SRAM1 reset control */ - kSRAM2_RST_SHIFT_RSTn = 0 | 4U, /**< SRAM2 reset control */ - kSRAM3_RST_SHIFT_RSTn = 0 | 5U, /**< SRAM3 reset control */ - kSRAM4_RST_SHIFT_RSTn = 0 | 6U, /**< SRAM4 reset control */ - kFLASH_RST_SHIFT_RSTn = 0 | 7U, /**< Flash controller reset control */ - kFMC_RST_SHIFT_RSTn = 0 | 8U, /**< Flash accelerator reset control */ - kSPIFI_RST_SHIFT_RSTn = 0 | 10U, /**< SPIFI reset control */ - kMUX0_RST_SHIFT_RSTn = 0 | 11U, /**< Input mux0 reset control */ - kIOCON_RST_SHIFT_RSTn = 0 | 13U, /**< IOCON reset control */ - kGPIO0_RST_SHIFT_RSTn = 0 | 14U, /**< GPIO0 reset control */ - kGPIO1_RST_SHIFT_RSTn = 0 | 15U, /**< GPIO1 reset control */ - kGPIO2_RST_SHIFT_RSTn = 0 | 16U, /**< GPIO2 reset control */ - kGPIO3_RST_SHIFT_RSTn = 0 | 17U, /**< GPIO3 reset control */ - kPINT_RST_SHIFT_RSTn = 0 | 18U, /**< Pin interrupt (PINT) reset control */ - kGINT_RST_SHIFT_RSTn = 0 | 19U, /**< Grouped interrupt (PINT) reset control. */ - kDMA0_RST_SHIFT_RSTn = 0 | 20U, /**< DMA reset control */ - kCRC_RST_SHIFT_RSTn = 0 | 21U, /**< CRC reset control */ - kWWDT_RST_SHIFT_RSTn = 0 | 22U, /**< Watchdog timer reset control */ - kRTC_RST_SHIFT_RSTn = 0 | 23U, /**< RTC reset control */ + kROM_RST_SHIFT_RSTn = 0 | 1U, /**< ROM reset control */ + kSRAM1_RST_SHIFT_RSTn = 0 | 3U, /**< SRAM1 reset control */ + kSRAM2_RST_SHIFT_RSTn = 0 | 4U, /**< SRAM2 reset control */ + kSRAM3_RST_SHIFT_RSTn = 0 | 5U, /**< SRAM3 reset control */ + kSRAM4_RST_SHIFT_RSTn = 0 | 6U, /**< SRAM4 reset control */ + kFLASH_RST_SHIFT_RSTn = 0 | 7U, /**< Flash controller reset control */ + kFMC_RST_SHIFT_RSTn = 0 | 8U, /**< Flash accelerator reset control */ + kSPIFI_RST_SHIFT_RSTn = 0 | 10U, /**< SPIFI reset control */ + kMUX0_RST_SHIFT_RSTn = 0 | 11U, /**< Input mux0 reset control */ + kIOCON_RST_SHIFT_RSTn = 0 | 13U, /**< IOCON reset control */ + kGPIO0_RST_SHIFT_RSTn = 0 | 14U, /**< GPIO0 reset control */ + kGPIO1_RST_SHIFT_RSTn = 0 | 15U, /**< GPIO1 reset control */ + kGPIO2_RST_SHIFT_RSTn = 0 | 16U, /**< GPIO2 reset control */ + kGPIO3_RST_SHIFT_RSTn = 0 | 17U, /**< GPIO3 reset control */ + kPINT_RST_SHIFT_RSTn = 0 | 18U, /**< Pin interrupt (PINT) reset control */ + kGINT_RST_SHIFT_RSTn = 0 | 19U, /**< Grouped interrupt (PINT) reset control. */ + kDMA0_RST_SHIFT_RSTn = 0 | 20U, /**< DMA reset control */ + kCRC_RST_SHIFT_RSTn = 0 | 21U, /**< CRC reset control */ + kWWDT_RST_SHIFT_RSTn = 0 | 22U, /**< Watchdog timer reset control */ + kRTC_RST_SHIFT_RSTn = 0 | 23U, /**< RTC reset control */ kMAILBOX_RST_SHIFT_RSTn = 0 | 26U, /**< Mailbox reset control */ - kADC0_RST_SHIFT_RSTn = 0 | 27U, /**< ADC0 reset control */ + kADC0_RST_SHIFT_RSTn = 0 | 27U, /**< ADC0 reset control */ - kMRT_RST_SHIFT_RSTn = 65536 | 0U, /**< Multi-rate timer (MRT) reset control */ - kOSTIMER0_RST_SHIFT_RSTn = 65536 | 1U, /**< OSTimer0 reset control */ - kSCT0_RST_SHIFT_RSTn = 65536 | 2U, /**< SCTimer/PWM 0 (SCT0) reset control */ - kSCTIPU_RST_SHIFT_RSTn = 65536 | 6U, /**< SCTIPU reset control */ - kUTICK_RST_SHIFT_RSTn = 65536 | 10U, /**< Micro-tick timer reset control */ - kFC0_RST_SHIFT_RSTn = 65536 | 11U, /**< Flexcomm Interface 0 reset control */ - kFC1_RST_SHIFT_RSTn = 65536 | 12U, /**< Flexcomm Interface 1 reset control */ - kFC2_RST_SHIFT_RSTn = 65536 | 13U, /**< Flexcomm Interface 2 reset control */ - kFC3_RST_SHIFT_RSTn = 65536 | 14U, /**< Flexcomm Interface 3 reset control */ - kFC4_RST_SHIFT_RSTn = 65536 | 15U, /**< Flexcomm Interface 4 reset control */ - kFC5_RST_SHIFT_RSTn = 65536 | 16U, /**< Flexcomm Interface 5 reset control */ - kFC6_RST_SHIFT_RSTn = 65536 | 17U, /**< Flexcomm Interface 6 reset control */ - kFC7_RST_SHIFT_RSTn = 65536 | 18U, /**< Flexcomm Interface 7 reset control */ - kCTIMER2_RST_SHIFT_RSTn = 65536 | 22U, /**< CTimer 2 reset control */ - kUSB0D_RST_SHIFT_RSTn = 65536 | 25U, /**< USB0 Device reset control */ - kCTIMER0_RST_SHIFT_RSTn = 65536 | 26U, /**< CTimer 0 reset control */ - kCTIMER1_RST_SHIFT_RSTn = 65536 | 27U, /**< CTimer 1 reset control */ - kPVT_RST_SHIFT_RSTn = 65536 | 28U, /**< PVT reset control */ - kEZHA_RST_SHIFT_RSTn = 65536 | 30U, /**< EZHA reset control */ - kEZHB_RST_SHIFT_RSTn = 65536 | 31U, /**< EZHB reset control */ + kMRT_RST_SHIFT_RSTn = 65536 | 0U, /**< Multi-rate timer (MRT) reset control */ + kOSTIMER0_RST_SHIFT_RSTn = 65536 | 1U, /**< OSTimer0 reset control */ + kSCT0_RST_SHIFT_RSTn = 65536 | 2U, /**< SCTimer/PWM 0 (SCT0) reset control */ + kSCTIPU_RST_SHIFT_RSTn = 65536 | 6U, /**< SCTIPU reset control */ + kUTICK_RST_SHIFT_RSTn = 65536 | 10U, /**< Micro-tick timer reset control */ + kFC0_RST_SHIFT_RSTn = 65536 | 11U, /**< Flexcomm Interface 0 reset control */ + kFC1_RST_SHIFT_RSTn = 65536 | 12U, /**< Flexcomm Interface 1 reset control */ + kFC2_RST_SHIFT_RSTn = 65536 | 13U, /**< Flexcomm Interface 2 reset control */ + kFC3_RST_SHIFT_RSTn = 65536 | 14U, /**< Flexcomm Interface 3 reset control */ + kFC4_RST_SHIFT_RSTn = 65536 | 15U, /**< Flexcomm Interface 4 reset control */ + kFC5_RST_SHIFT_RSTn = 65536 | 16U, /**< Flexcomm Interface 5 reset control */ + kFC6_RST_SHIFT_RSTn = 65536 | 17U, /**< Flexcomm Interface 6 reset control */ + kFC7_RST_SHIFT_RSTn = 65536 | 18U, /**< Flexcomm Interface 7 reset control */ + kCTIMER2_RST_SHIFT_RSTn = 65536 | 22U, /**< CTimer 2 reset control */ + kUSB0D_RST_SHIFT_RSTn = 65536 | 25U, /**< USB0 Device reset control */ + kCTIMER0_RST_SHIFT_RSTn = 65536 | 26U, /**< CTimer 0 reset control */ + kCTIMER1_RST_SHIFT_RSTn = 65536 | 27U, /**< CTimer 1 reset control */ + kPVT_RST_SHIFT_RSTn = 65536 | 28U, /**< PVT reset control */ + kEZHA_RST_SHIFT_RSTn = 65536 | 30U, /**< EZHA reset control */ + kEZHB_RST_SHIFT_RSTn = 65536 | 31U, /**< EZHB reset control */ - kDMA1_RST_SHIFT_RSTn = 131072 | 1U, /**< DMA1 reset control */ - kCMP_RST_SHIFT_RSTn = 131072 | 2U, /**< CMP reset control */ - kSDIO_RST_SHIFT_RSTn = 131072 | 3U, /**< SDIO reset control */ - kUSB1H_RST_SHIFT_RSTn = 131072 | 4U, /**< USBHS Host reset control */ - kUSB1D_RST_SHIFT_RSTn = 131072 | 5U, /**< USBHS Device reset control */ - kUSB1RAM_RST_SHIFT_RSTn = 131072 | 6U, /**< USB RAM reset control */ - kUSB1_RST_SHIFT_RSTn = 131072 | 7U, /**< USBHS reset control */ - kFREQME_RST_SHIFT_RSTn = 131072 | 8U, /**< FREQME reset control */ - kGPIO4_RST_SHIFT_RSTn = 131072 | 9U, /**< GPIO4 reset control */ - kGPIO5_RST_SHIFT_RSTn = 131072 | 10U, /**< GPIO5 reset control */ - kAES_RST_SHIFT_RSTn = 131072 | 11U, /**< AES reset control */ - kOTP_RST_SHIFT_RSTn = 131072 | 12U, /**< OTP reset control */ - kRNG_RST_SHIFT_RSTn = 131072 | 13U, /**< RNG reset control */ - kMUX1_RST_SHIFT_RSTn = 131072 | 14U, /**< Input mux1 reset control */ - kUSB0HMR_RST_SHIFT_RSTn = 131072 | 16U, /**< USB0HMR reset control */ - kUSB0HSL_RST_SHIFT_RSTn = 131072 | 17U, /**< USB0HSL reset control */ - kHASHCRYPT_RST_SHIFT_RSTn = 131072 | 18U, /**< HASHCRYPT reset control */ - kPOWERQUAD_RST_SHIFT_RSTn = 131072 | 19U, /**< PowerQuad reset control */ - kPLULUT_RST_SHIFT_RSTn = 131072 | 20U, /**< PLU LUT reset control */ - kCTIMER3_RST_SHIFT_RSTn = 131072 | 21U, /**< CTimer 3 reset control */ - kCTIMER4_RST_SHIFT_RSTn = 131072 | 22U, /**< CTimer 4 reset control */ - kPUF_RST_SHIFT_RSTn = 131072 | 23U, /**< PUF reset control */ - kCASPER_RST_SHIFT_RSTn = 131072 | 24U, /**< CASPER reset control */ - kCAP0_RST_SHIFT_RSTn = 131072 | 25U, /**< CASPER reset control */ - kOSTIMER1_RST_SHIFT_RSTn = 131072 | 26U, /**< OSTIMER1 reset control */ - kANALOGCTL_RST_SHIFT_RSTn = 131072 | 27U, /**< ANALOG_CTL reset control */ - kHSLSPI_RST_SHIFT_RSTn = 131072 | 28U, /**< HS LSPI reset control */ - kGPIOSEC_RST_SHIFT_RSTn = 131072 | 29U, /**< GPIO Secure reset control */ + kDMA1_RST_SHIFT_RSTn = 131072 | 1U, /**< DMA1 reset control */ + kCMP_RST_SHIFT_RSTn = 131072 | 2U, /**< CMP reset control */ + kSDIO_RST_SHIFT_RSTn = 131072 | 3U, /**< SDIO reset control */ + kUSB1H_RST_SHIFT_RSTn = 131072 | 4U, /**< USBHS Host reset control */ + kUSB1D_RST_SHIFT_RSTn = 131072 | 5U, /**< USBHS Device reset control */ + kUSB1RAM_RST_SHIFT_RSTn = 131072 | 6U, /**< USB RAM reset control */ + kUSB1_RST_SHIFT_RSTn = 131072 | 7U, /**< USBHS reset control */ + kFREQME_RST_SHIFT_RSTn = 131072 | 8U, /**< FREQME reset control */ + kGPIO4_RST_SHIFT_RSTn = 131072 | 9U, /**< GPIO4 reset control */ + kGPIO5_RST_SHIFT_RSTn = 131072 | 10U, /**< GPIO5 reset control */ + kAES_RST_SHIFT_RSTn = 131072 | 11U, /**< AES reset control */ + kOTP_RST_SHIFT_RSTn = 131072 | 12U, /**< OTP reset control */ + kRNG_RST_SHIFT_RSTn = 131072 | 13U, /**< RNG reset control */ + kMUX1_RST_SHIFT_RSTn = 131072 | 14U, /**< Input mux1 reset control */ + kUSB0HMR_RST_SHIFT_RSTn = 131072 | 16U, /**< USB0HMR reset control */ + kUSB0HSL_RST_SHIFT_RSTn = 131072 | 17U, /**< USB0HSL reset control */ + kHASHCRYPT_RST_SHIFT_RSTn = 131072 | 18U, /**< HASHCRYPT reset control */ + kPOWERQUAD_RST_SHIFT_RSTn = 131072 | 19U, /**< PowerQuad reset control */ + kPLULUT_RST_SHIFT_RSTn = 131072 | 20U, /**< PLU LUT reset control */ + kCTIMER3_RST_SHIFT_RSTn = 131072 | 21U, /**< CTimer 3 reset control */ + kCTIMER4_RST_SHIFT_RSTn = 131072 | 22U, /**< CTimer 4 reset control */ + kPUF_RST_SHIFT_RSTn = 131072 | 23U, /**< PUF reset control */ + kCASPER_RST_SHIFT_RSTn = 131072 | 24U, /**< CASPER reset control */ + kCAP0_RST_SHIFT_RSTn = 131072 | 25U, /**< CASPER reset control */ + kOSTIMER1_RST_SHIFT_RSTn = 131072 | 26U, /**< OSTIMER1 reset control */ + kANALOGCTL_RST_SHIFT_RSTn = 131072 | 27U, /**< ANALOG_CTL reset control */ + kHSLSPI_RST_SHIFT_RSTn = 131072 | 28U, /**< HS LSPI reset control */ + kGPIOSEC_RST_SHIFT_RSTn = 131072 | 29U, /**< GPIO Secure reset control */ kGPIOSECINT_RST_SHIFT_RSTn = 131072 | 30U, /**< GPIO Secure int reset control */ } SYSCON_RSTn_t; @@ -230,7 +230,7 @@ typedef enum _SYSCON_RSTn kPLULUT_RST_SHIFT_RSTn \ } /* Reset bits for PLU peripheral */ #define OSTIMER_RSTS \ - { \ + { \ kOSTIMER0_RST_SHIFT_RSTn \ } /* Reset bits for OSTIMER peripheral */ typedef SYSCON_RSTn_t reset_ip_name_t;