--- /dev/null
+/*\r
+ * FreeRTOS Kernel V10.2.1\r
+ * Copyright (C) 2019 Amazon.com, Inc. or its affiliates. All Rights Reserved.\r
+ *\r
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of\r
+ * this software and associated documentation files (the "Software"), to deal in\r
+ * the Software without restriction, including without limitation the rights to\r
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of\r
+ * the Software, and to permit persons to whom the Software is furnished to do so,\r
+ * subject to the following conditions:\r
+ *\r
+ * The above copyright notice and this permission notice shall be included in all\r
+ * copies or substantial portions of the Software.\r
+ *\r
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR\r
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS\r
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR\r
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER\r
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN\r
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.\r
+ *\r
+ * http://www.FreeRTOS.org\r
+ * http://aws.amazon.com/freertos\r
+ *\r
+ * 1 tab == 4 spaces!\r
+ */\r
+\r
+\r
+#ifndef FREERTOS_CONFIG_H\r
+#define FREERTOS_CONFIG_H\r
+\r
+#ifdef __cplusplus\r
+extern "C" {\r
+#endif\r
+\r
+/*-----------------------------------------------------------\r
+ * Application specific definitions.\r
+ *\r
+ * These definitions should be adjusted for your particular hardware and\r
+ * application requirements.\r
+ *\r
+ * THESE PARAMETERS ARE DESCRIBED WITHIN THE 'CONFIGURATION' SECTION OF THE\r
+ * FreeRTOS API DOCUMENTATION AVAILABLE ON THE FreeRTOS.org WEB SITE.\r
+ *\r
+ * See http://www.freertos.org/a00110.html\r
+ *----------------------------------------------------------*/\r
+\r
+/* The MPU version of port.c includes and excludes functions depending on the\r
+settings within this file. Therefore, to ensure all the functions in port.c\r
+build, this configuration file has all options turned on. */\r
+\r
+#define configUSE_PREEMPTION 1\r
+#define configTICK_RATE_HZ ( 1000 )\r
+#define configUSE_PORT_OPTIMISED_TASK_SELECTION 1\r
+#define configUSE_QUEUE_SETS 1\r
+#define configUSE_IDLE_HOOK 0\r
+#define configUSE_TICK_HOOK 0\r
+#define configCPU_CLOCK_HZ 48000000\r
+#define configMAX_PRIORITIES ( 5 )\r
+#define configMINIMAL_STACK_SIZE ( ( unsigned short ) 256 )\r
+#define configTOTAL_HEAP_SIZE ( ( size_t ) ( 16 * 1024 ) )\r
+#define configMAX_TASK_NAME_LEN ( 10 )\r
+#define configUSE_TRACE_FACILITY 1\r
+#define configUSE_16_BIT_TICKS 0\r
+#define configIDLE_SHOULD_YIELD 1\r
+#define configUSE_MUTEXES 1\r
+#define configQUEUE_REGISTRY_SIZE 5\r
+#define configCHECK_FOR_STACK_OVERFLOW 2\r
+#define configUSE_RECURSIVE_MUTEXES 1\r
+#define configUSE_MALLOC_FAILED_HOOK 1\r
+#define configUSE_APPLICATION_TASK_TAG 1\r
+#define configUSE_COUNTING_SEMAPHORES 1\r
+#define configUSE_TICKLESS_IDLE 0\r
+#define configNUM_THREAD_LOCAL_STORAGE_POINTERS 2\r
+\r
+/* This demo shows the MPU being used without any dynamic memory allocation. */\r
+#define configSUPPORT_STATIC_ALLOCATION 1\r
+#define configSUPPORT_DYNAMIC_ALLOCATION 1\r
+\r
+/* Run time stats gathering definitions. */\r
+#define configGENERATE_RUN_TIME_STATS 1\r
+#define portCONFIGURE_TIMER_FOR_RUN_TIME_STATS()\r
+#define portGET_RUN_TIME_COUNTER_VALUE() 0\r
+\r
+/* This demo makes use of one or more example stats formatting functions. These\r
+format the raw data provided by the uxTaskGetSystemState() function in to human\r
+readable ASCII form. See the notes in the implementation of vTaskList() within\r
+FreeRTOS/Source/tasks.c for limitations. */\r
+#define configUSE_STATS_FORMATTING_FUNCTIONS 0\r
+\r
+/* Co-routine definitions. */\r
+#define configUSE_CO_ROUTINES 0\r
+#define configMAX_CO_ROUTINE_PRIORITIES ( 2 )\r
+\r
+/* Software timer definitions. */\r
+#define configUSE_TIMERS 1\r
+#define configTIMER_TASK_PRIORITY ( 2 )\r
+#define configTIMER_QUEUE_LENGTH 5\r
+#define configTIMER_TASK_STACK_DEPTH ( configMINIMAL_STACK_SIZE )\r
+\r
+/* Set the following definitions to 1 to include the API function, or zero\r
+to exclude the API function. */\r
+#define INCLUDE_vTaskPrioritySet 1\r
+#define INCLUDE_uxTaskPriorityGet 1\r
+#define INCLUDE_vTaskDelete 1\r
+#define INCLUDE_vTaskCleanUpResources 1\r
+#define INCLUDE_vTaskSuspend 1\r
+#define INCLUDE_vTaskDelayUntil 1\r
+#define INCLUDE_vTaskDelay 1\r
+#define INCLUDE_eTaskGetState 1\r
+#define INCLUDE_xTimerPendFunctionCall 0\r
+#define INCLUDE_xSemaphoreGetMutexHolder 1\r
+#define INCLUDE_xTaskGetHandle 1\r
+#define INCLUDE_xTaskGetCurrentTaskHandle 1\r
+#define INCLUDE_xTaskGetIdleTaskHandle 1\r
+#define INCLUDE_xTaskAbortDelay 1\r
+#define INCLUDE_xTaskGetSchedulerState 1\r
+#define INCLUDE_xTaskGetIdleTaskHandle 1\r
+#define INCLUDE_uxTaskGetStackHighWaterMark 1\r
+\r
+/* Cortex-M specific definitions. */\r
+#ifdef __NVIC_PRIO_BITS\r
+ /* __BVIC_PRIO_BITS will be specified when CMSIS is being used. */\r
+ #define configPRIO_BITS __NVIC_PRIO_BITS\r
+#else\r
+ #define configPRIO_BITS 4 /* 15 priority levels */\r
+#endif\r
+\r
+/* The lowest interrupt priority that can be used in a call to a "set priority"\r
+function. */\r
+#define configLIBRARY_LOWEST_INTERRUPT_PRIORITY 0xf\r
+\r
+/* The highest interrupt priority that can be used by any interrupt service\r
+routine that makes calls to interrupt safe FreeRTOS API functions. DO NOT CALL\r
+INTERRUPT SAFE FREERTOS API FUNCTIONS FROM ANY INTERRUPT THAT HAS A HIGHER\r
+PRIORITY THAN THIS! (higher priorities are lower numeric values. */\r
+#define configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY 5\r
+\r
+/* Interrupt priorities used by the kernel port layer itself. These are generic\r
+to all Cortex-M ports, and do not rely on any particular library functions. */\r
+#define configKERNEL_INTERRUPT_PRIORITY ( configLIBRARY_LOWEST_INTERRUPT_PRIORITY << (8 - configPRIO_BITS) )\r
+/* !!!! configMAX_SYSCALL_INTERRUPT_PRIORITY must not be set to zero !!!!\r
+See http://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html. */\r
+#define configMAX_SYSCALL_INTERRUPT_PRIORITY ( configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY << (8 - configPRIO_BITS) )\r
+\r
+\r
+/* Definitions that map the FreeRTOS port interrupt handlers to their CMSIS\r
+standard names. */\r
+#define xPortPendSVHandler PendSV_Handler\r
+#define vPortSVCHandler SVC_Handler\r
+#define xPortSysTickHandler SysTick_Handler\r
+\r
+/* Normal assert() semantics without relying on the provision of an assert.h\r
+header file. */\r
+#define configASSERT( x ) if( ( x ) == 0 ) { portDISABLE_INTERRUPTS(); for( ;; ); }\r
+\r
+/* Ensure that system calls can only be made from kernel code. */\r
+#define configENFORCE_SYSTEM_CALLS_FROM_KERNEL_ONLY 1\r
+\r
+#ifdef __cplusplus\r
+}\r
+#endif\r
+\r
+#endif /* FREERTOS_CONFIG_H */\r
--- /dev/null
+/*\r
+ * FreeRTOS Kernel V10.2.1\r
+ * Copyright (C) 2019 Amazon.com, Inc. or its affiliates. All Rights Reserved.\r
+ *\r
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of\r
+ * this software and associated documentation files (the "Software"), to deal in\r
+ * the Software without restriction, including without limitation the rights to\r
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of\r
+ * the Software, and to permit persons to whom the Software is furnished to do so,\r
+ * subject to the following conditions:\r
+ *\r
+ * The above copyright notice and this permission notice shall be included in all\r
+ * copies or substantial portions of the Software.\r
+ *\r
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR\r
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS\r
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR\r
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER\r
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN\r
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.\r
+ *\r
+ * http://www.FreeRTOS.org\r
+ * http://aws.amazon.com/freertos\r
+ *\r
+ * 1 tab == 4 spaces!\r
+ */\r
+/* Scheduler includes. */\r
+#include "FreeRTOS.h"\r
+#include "task.h"\r
+\r
+/* App includes. */\r
+#include "app_main.h"\r
+\r
+/* Demo includes. */\r
+#include "mpu_demo.h"\r
+\r
+void app_main( void )\r
+{\r
+ /* Start the MPU demo. */\r
+ vStartMPUDemo();\r
+\r
+ /* Start the scheduler. */\r
+ vTaskStartScheduler();\r
+\r
+ /* Should not get here. */\r
+ for( ;; );\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+void vApplicationStackOverflowHook( TaskHandle_t pxTask, char *pcTaskName )\r
+{\r
+ /* If configCHECK_FOR_STACK_OVERFLOW is set to either 1 or 2 then this\r
+ function will automatically get called if a task overflows its stack. */\r
+ ( void ) pxTask;\r
+ ( void ) pcTaskName;\r
+ for( ;; );\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+void vApplicationMallocFailedHook( void )\r
+{\r
+ /* If configUSE_MALLOC_FAILED_HOOK is set to 1 then this function will\r
+ be called automatically if a call to pvPortMalloc() fails. pvPortMalloc()\r
+ is called automatically when a task, queue or semaphore is created. */\r
+ for( ;; );\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+/* configUSE_STATIC_ALLOCATION is set to 1, so the application must provide an\r
+implementation of vApplicationGetIdleTaskMemory() to provide the memory that is\r
+used by the Idle task. */\r
+void vApplicationGetIdleTaskMemory( StaticTask_t **ppxIdleTaskTCBBuffer, StackType_t **ppxIdleTaskStackBuffer, uint32_t *pulIdleTaskStackSize )\r
+{\r
+/* If the buffers to be provided to the Idle task are declared inside this\r
+function then they must be declared static - otherwise they will be allocated on\r
+the stack and so not exists after this function exits. */\r
+static StaticTask_t xIdleTaskTCB;\r
+static StackType_t uxIdleTaskStack[ configMINIMAL_STACK_SIZE ];\r
+\r
+ /* Pass out a pointer to the StaticTask_t structure in which the Idle task's\r
+ state will be stored. */\r
+ *ppxIdleTaskTCBBuffer = &xIdleTaskTCB;\r
+\r
+ /* Pass out the array that will be used as the Idle task's stack. */\r
+ *ppxIdleTaskStackBuffer = uxIdleTaskStack;\r
+\r
+ /* Pass out the size of the array pointed to by *ppxIdleTaskStackBuffer.\r
+ Note that, as the array is necessarily of type StackType_t,\r
+ configMINIMAL_STACK_SIZE is specified in words, not bytes. */\r
+ *pulIdleTaskStackSize = configMINIMAL_STACK_SIZE;\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+/* configUSE_STATIC_ALLOCATION and configUSE_TIMERS are both set to 1, so the\r
+application must provide an implementation of vApplicationGetTimerTaskMemory()\r
+to provide the memory that is used by the Timer service task. */\r
+void vApplicationGetTimerTaskMemory( StaticTask_t **ppxTimerTaskTCBBuffer, StackType_t **ppxTimerTaskStackBuffer, uint32_t *pulTimerTaskStackSize )\r
+{\r
+/* If the buffers to be provided to the Timer task are declared inside this\r
+function then they must be declared static - otherwise they will be allocated on\r
+the stack and so not exists after this function exits. */\r
+static StaticTask_t xTimerTaskTCB;\r
+static StackType_t uxTimerTaskStack[ configTIMER_TASK_STACK_DEPTH ];\r
+\r
+ /* Pass out a pointer to the StaticTask_t structure in which the Timer\r
+ task's state will be stored. */\r
+ *ppxTimerTaskTCBBuffer = &xTimerTaskTCB;\r
+\r
+ /* Pass out the array that will be used as the Timer task's stack. */\r
+ *ppxTimerTaskStackBuffer = uxTimerTaskStack;\r
+\r
+ /* Pass out the size of the array pointed to by *ppxTimerTaskStackBuffer.\r
+ Note that, as the array is necessarily of type StackType_t,\r
+ configMINIMAL_STACK_SIZE is specified in words, not bytes. */\r
+ *pulTimerTaskStackSize = configTIMER_TASK_STACK_DEPTH;\r
+}\r
+/*-----------------------------------------------------------*/\r
--- /dev/null
+/*\r
+ * FreeRTOS Kernel V10.2.1\r
+ * Copyright (C) 2019 Amazon.com, Inc. or its affiliates. All Rights Reserved.\r
+ *\r
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of\r
+ * this software and associated documentation files (the "Software"), to deal in\r
+ * the Software without restriction, including without limitation the rights to\r
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of\r
+ * the Software, and to permit persons to whom the Software is furnished to do so,\r
+ * subject to the following conditions:\r
+ *\r
+ * The above copyright notice and this permission notice shall be included in all\r
+ * copies or substantial portions of the Software.\r
+ *\r
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR\r
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS\r
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR\r
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER\r
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN\r
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.\r
+ *\r
+ * http://www.FreeRTOS.org\r
+ * http://aws.amazon.com/freertos\r
+ *\r
+ * 1 tab == 4 spaces!\r
+ */\r
+\r
+#ifndef __APP_MAIN_H__\r
+#define __APP_MAIN_H__\r
+\r
+/**\r
+ * @brief Main app entry point.\r
+ */\r
+void app_main( void );\r
+\r
+#endif /* __APP_MAIN_H__ */\r
--- /dev/null
+/*\r
+ * FreeRTOS Kernel V10.2.1\r
+ * Copyright (C) 2019 Amazon.com, Inc. or its affiliates. All Rights Reserved.\r
+ *\r
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of\r
+ * this software and associated documentation files (the "Software"), to deal in\r
+ * the Software without restriction, including without limitation the rights to\r
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of\r
+ * the Software, and to permit persons to whom the Software is furnished to do so,\r
+ * subject to the following conditions:\r
+ *\r
+ * The above copyright notice and this permission notice shall be included in all\r
+ * copies or substantial portions of the Software.\r
+ *\r
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR\r
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS\r
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR\r
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER\r
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN\r
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.\r
+ *\r
+ * http://www.FreeRTOS.org\r
+ * http://aws.amazon.com/freertos\r
+ *\r
+ * 1 tab == 4 spaces!\r
+ */\r
+\r
+/* FreeRTOS includes. */\r
+#include "FreeRTOS.h"\r
+#include "task.h"\r
+\r
+/** ARMv7 MPU Details:\r
+ *\r
+ * - ARMv7 MPU requires that the size of a MPU region is a power of 2.\r
+ * - Smallest supported region size is 32 bytes.\r
+ * - Start address of a region must be aligned to an integer multiple of the\r
+ * region size. For example, if the region size is 4 KB(0x1000), the starting\r
+ * address must be N x 0x1000, where N is an integer.\r
+ */\r
+\r
+/**\r
+ * @brief Size of the shared memory region.\r
+ */\r
+#define SHARED_MEMORY_SIZE 32\r
+\r
+/**\r
+ * @brief Memory region shared between two tasks.\r
+ */\r
+static uint8_t ucSharedMemory[ SHARED_MEMORY_SIZE ] __attribute__( ( aligned( SHARED_MEMORY_SIZE ) ) );\r
+\r
+/**\r
+ * @brief Memory region used to track Memory Fault intentionally caused by the\r
+ * RO Access task.\r
+ *\r
+ * RO Access task sets ucROTaskFaultTracker[ 0 ] to 1 before accessing illegal\r
+ * memory. Illegal memory access causes Memory Fault and the fault handler\r
+ * checks ucROTaskFaultTracker[ 0 ] to see if this is an expected fault. We\r
+ * recover gracefully from an expected fault by jumping to the next instruction.\r
+ *\r
+ * @note We are declaring a region of 32 bytes even though we need only one.\r
+ * The reason is that the smallest supported MPU region size is 32 bytes.\r
+ */\r
+static volatile uint8_t ucROTaskFaultTracker[ SHARED_MEMORY_SIZE ] __attribute__( ( aligned( SHARED_MEMORY_SIZE ) ) ) = { 0 };\r
+/*-----------------------------------------------------------*/\r
+\r
+/**\r
+ * @brief Implements the task which has Read Only access to the memory region\r
+ * ucSharedMemory.\r
+ *\r
+ * @param pvParameters[in] Parameters as passed during task creation.\r
+ */\r
+static void prvROAccessTask( void * pvParameters );\r
+\r
+/**\r
+ * @brief Implements the task which has Read Write access to the memory region\r
+ * ucSharedMemory.\r
+ *\r
+ * @param pvParameters[in] Parameters as passed during task creation.\r
+ */\r
+static void prvRWAccessTask( void * pvParameters );\r
+\r
+/*-----------------------------------------------------------*/\r
+\r
+static void prvROAccessTask( void * pvParameters )\r
+{\r
+uint8_t ucVal;\r
+\r
+ /* Unused parameters. */\r
+ ( void ) pvParameters;\r
+\r
+ for( ; ; )\r
+ {\r
+ /* This task has RO access to ucSharedMemory and therefore it can read\r
+ * it but cannot modify it. */\r
+ ucVal = ucSharedMemory[ 0 ];\r
+\r
+ /* Silent compiler warnings about unused variables. */\r
+ ( void ) ucVal;\r
+\r
+ /* Since this task has Read Only access to the ucSharedMemory region,\r
+ * writing to it results in Memory Fault. Set ucROTaskFaultTracker[ 0 ]\r
+ * to 1 to tell the Memory Fault Handler that this is an expected fault.\r
+ * The handler will recover from this fault gracefully by jumping to the\r
+ * next instruction. */\r
+ ucROTaskFaultTracker[ 0 ] = 1;\r
+\r
+ /* Illegal access to generate Memory Fault. */\r
+ ucSharedMemory[ 0 ] = 0;\r
+\r
+ /* Ensure that the above line did generate MemFault and the fault\r
+ * handler did clear the ucROTaskFaultTracker[ 0 ]. */\r
+ configASSERT( ucROTaskFaultTracker[ 0 ] == 0 );\r
+\r
+ #if( configENFORCE_SYSTEM_CALLS_FROM_KERNEL_ONLY == 1 )\r
+ {\r
+ /* Generate an SVC to raise the privilege. Since privilege\r
+ * escalation is only allowed from kernel code, this request must\r
+ * get rejected and the task must remain unprivileged. As a result,\r
+ * trying to write to ucSharedMemory will still result in Memory\r
+ * Fault. */\r
+ portRAISE_PRIVILEGE();\r
+\r
+ /* Set ucROTaskFaultTracker[ 0 ] to 1 to tell the Memory Fault\r
+ * Handler that this is an expected fault. The handler will then be\r
+ * able to recover from this fault gracefully by jumping to the\r
+ * next instruction.*/\r
+ ucROTaskFaultTracker[ 0 ] = 1;\r
+\r
+ /* The following must still result in Memory Fault since the task\r
+ * is still running unprivileged. */\r
+ ucSharedMemory[ 0 ] = 0;\r
+\r
+ /* Ensure that the above line did generate MemFault and the fault\r
+ * handler did clear the ucROTaskFaultTracker[ 0 ]. */\r
+ configASSERT( ucROTaskFaultTracker[ 0 ] == 0 );\r
+ }\r
+ #else\r
+ {\r
+ /* Generate an SVC to raise the privilege. Since\r
+ * configENFORCE_SYSTEM_CALLS_FROM_KERNEL_ONLY is not enabled, the\r
+ * task will be able to escalate privilege. */\r
+ portRAISE_PRIVILEGE();\r
+\r
+ /* At this point, the task is running privileged. The following\r
+ * access must not result in Memory Fault. If something goes\r
+ * wrong and we do get a fault, the execution will stop in fault\r
+ * handler as ucROTaskFaultTracker[ 0 ] is not set (i.e.\r
+ * un-expected fault). */\r
+ ucSharedMemory[ 0 ] = 0;\r
+\r
+ /* Lower down the privilege. */\r
+ portSWITCH_TO_USER_MODE();\r
+\r
+ /* Now the task is running unprivileged and therefore an attempt to\r
+ * write to ucSharedMemory will result in a Memory Fault. Set\r
+ * ucROTaskFaultTracker[ 0 ] to 1 to tell the Memory Fault Handler\r
+ * that this is an expected fault. The handler will then be able to\r
+ * recover from this fault gracefully by jumping to the next\r
+ * instruction.*/\r
+ ucROTaskFaultTracker[ 0 ] = 1;\r
+\r
+ /* The following must result in Memory Fault since the task is now\r
+ * running unprivileged. */\r
+ ucSharedMemory[ 0 ] = 0;\r
+\r
+ /* Ensure that the above line did generate MemFault and the fault\r
+ * handler did clear the ucROTaskFaultTracker[ 0 ]. */\r
+ configASSERT( ucROTaskFaultTracker[ 0 ] == 0 );\r
+ }\r
+ #endif /* #if( configENFORCE_SYSTEM_CALLS_FROM_KERNEL_ONLY == 1 ) */\r
+\r
+ /* Wait for a second. */\r
+ vTaskDelay( pdMS_TO_TICKS( 1000 ) );\r
+ }\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+static void prvRWAccessTask( void * pvParameters )\r
+{\r
+ /* Unused parameters. */\r
+ ( void ) pvParameters;\r
+\r
+ for( ; ; )\r
+ {\r
+ /* This task has RW access to ucSharedMemory and therefore can write to\r
+ * it. */\r
+ ucSharedMemory[ 0 ] = 0;\r
+\r
+ /* Wait for a second. */\r
+ vTaskDelay( pdMS_TO_TICKS( 1000 ) );\r
+ }\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+void vStartMPUDemo( void )\r
+{\r
+/**\r
+ * Since stack of a task is protected using MPU, it must satisfy MPU\r
+ * requirements as mentioned at the top of this file.\r
+ */\r
+static StackType_t xROAccessTaskStack[ configMINIMAL_STACK_SIZE ] __attribute__( ( aligned( configMINIMAL_STACK_SIZE * sizeof( StackType_t ) ) ) );\r
+static StackType_t xRWAccessTaskStack[ configMINIMAL_STACK_SIZE ] __attribute__( ( aligned( configMINIMAL_STACK_SIZE * sizeof( StackType_t ) ) ) );\r
+TaskParameters_t xROAccessTaskParameters =\r
+{\r
+ .pvTaskCode = prvROAccessTask,\r
+ .pcName = "ROAccess",\r
+ .usStackDepth = configMINIMAL_STACK_SIZE,\r
+ .pvParameters = NULL,\r
+ .uxPriority = tskIDLE_PRIORITY,\r
+ .puxStackBuffer = xROAccessTaskStack,\r
+ .xRegions = {\r
+ { ucSharedMemory, SHARED_MEMORY_SIZE, portMPU_REGION_PRIVILEGED_READ_WRITE_UNPRIV_READ_ONLY | portMPU_REGION_EXECUTE_NEVER },\r
+ { ( void * ) ucROTaskFaultTracker, SHARED_MEMORY_SIZE, portMPU_REGION_READ_WRITE | portMPU_REGION_EXECUTE_NEVER },\r
+ { 0, 0, 0 },\r
+ }\r
+};\r
+TaskParameters_t xRWAccessTaskParameters =\r
+{\r
+ .pvTaskCode = prvRWAccessTask,\r
+ .pcName = "RWAccess",\r
+ .usStackDepth = configMINIMAL_STACK_SIZE,\r
+ .pvParameters = NULL,\r
+ .uxPriority = tskIDLE_PRIORITY,\r
+ .puxStackBuffer = xRWAccessTaskStack,\r
+ .xRegions = {\r
+ { ucSharedMemory, SHARED_MEMORY_SIZE, portMPU_REGION_READ_WRITE | portMPU_REGION_EXECUTE_NEVER},\r
+ { 0, 0, 0 },\r
+ { 0, 0, 0 },\r
+ }\r
+};\r
+\r
+ /* Create an unprivileged task with RO access to ucSharedMemory. */\r
+ xTaskCreateRestricted( &( xROAccessTaskParameters ), NULL );\r
+\r
+ /* Create an unprivileged task with RW access to ucSharedMemory. */\r
+ xTaskCreateRestricted( &( xRWAccessTaskParameters ), NULL );\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+portDONT_DISCARD void vHandleMemoryFault( uint32_t * pulFaultStackAddress )\r
+{\r
+uint32_t ulPC;\r
+uint16_t usOffendingInstruction;\r
+\r
+ /* Is this an expected fault? */\r
+ if( ucROTaskFaultTracker[ 0 ] == 1 )\r
+ {\r
+ /* Read program counter. */\r
+ ulPC = pulFaultStackAddress[ 6 ];\r
+\r
+ /* Read the offending instruction. */\r
+ usOffendingInstruction = *( uint16_t * )ulPC;\r
+\r
+ /* From ARM docs:\r
+ * If the value of bits[15:11] of the halfword being decoded is one of\r
+ * the following, the halfword is the first halfword of a 32-bit\r
+ * instruction:\r
+ * - 0b11101.\r
+ * - 0b11110.\r
+ * - 0b11111.\r
+ * Otherwise, the halfword is a 16-bit instruction.\r
+ */\r
+\r
+ /* Extract bits[15:11] of the offending instruction. */\r
+ usOffendingInstruction = usOffendingInstruction & 0xF800;\r
+ usOffendingInstruction = ( usOffendingInstruction >> 11 );\r
+\r
+ /* Determine if the offending instruction is a 32-bit instruction or\r
+ * a 16-bit instruction. */\r
+ if( usOffendingInstruction == 0x001F ||\r
+ usOffendingInstruction == 0x001E ||\r
+ usOffendingInstruction == 0x001D )\r
+ {\r
+ /* Since the offending instruction is a 32-bit instruction,\r
+ * increment the program counter by 4 to move to the next\r
+ * instruction. */\r
+ ulPC += 4;\r
+ }\r
+ else\r
+ {\r
+ /* Since the offending instruction is a 16-bit instruction,\r
+ * increment the program counter by 2 to move to the next\r
+ * instruction. */\r
+ ulPC += 2;\r
+ }\r
+\r
+ /* Save the new program counter on the stack. */\r
+ pulFaultStackAddress[ 6 ] = ulPC;\r
+\r
+ /* Mark the fault as handled. */\r
+ ucROTaskFaultTracker[ 0 ] = 0;\r
+ }\r
+ else\r
+ {\r
+ /* This is an unexpected fault - loop forever. */\r
+ for( ; ; )\r
+ {\r
+ }\r
+ }\r
+}\r
+/*-----------------------------------------------------------*/\r
--- /dev/null
+/*\r
+ * FreeRTOS Kernel V10.2.1\r
+ * Copyright (C) 2019 Amazon.com, Inc. or its affiliates. All Rights Reserved.\r
+ *\r
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of\r
+ * this software and associated documentation files (the "Software"), to deal in\r
+ * the Software without restriction, including without limitation the rights to\r
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of\r
+ * the Software, and to permit persons to whom the Software is furnished to do so,\r
+ * subject to the following conditions:\r
+ *\r
+ * The above copyright notice and this permission notice shall be included in all\r
+ * copies or substantial portions of the Software.\r
+ *\r
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR\r
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS\r
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR\r
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER\r
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN\r
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.\r
+ *\r
+ * http://www.FreeRTOS.org\r
+ * http://aws.amazon.com/freertos\r
+ *\r
+ * 1 tab == 4 spaces!\r
+ */\r
+\r
+#ifndef __MPU_DEMO_H__\r
+#define __MPU_DEMO_H__\r
+\r
+/**\r
+ * @brief Creates all the tasks for MPU demo.\r
+ *\r
+ * The MPU demo creates 2 unprivileged tasks - One of which has Read Only access\r
+ * to a shared memory region while the other has Read Write access. The task\r
+ * with Read Only access then tries to write to the shared memory which results\r
+ * in a Memory fault. The fault handler examines that it is the fault generated\r
+ * by the task with Read Only access and if so, it recovers from the fault\r
+ * greacefully by moving the Program Counter to the next instruction to the one\r
+ * which generated the fault. If any other memory access violation occurs, the\r
+ * fault handler will get stuck in an inifinite loop.\r
+ */\r
+void vStartMPUDemo( void );\r
+\r
+#endif /* __MPU_DEMO_H__ */\r
--- /dev/null
+<?xml version="1.0" encoding="UTF-8" standalone="no"?>\r
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+ <builder buildPath="${workspace_loc:/FreeRTOSDemo}/Debug" id="com.st.stm32cube.ide.mcu.gnu.managedbuild.builder.43549526" keepEnvironmentInBuildfile="false" managedBuildOn="true" name="Gnu Make Builder" parallelBuildOn="true" parallelizationNumber="optimal" superClass="com.st.stm32cube.ide.mcu.gnu.managedbuild.builder"/>\r
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+ <listOptionValue builtIn="false" value="DEBUG"/>\r
+ </option>\r
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+ <listOptionValue builtIn="false" value=""${workspace_loc:/${ProjName}/ST_Code/Drivers/STM32L1xx_HAL_Driver/Inc/Legacy}""/>\r
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+ <listOptionValue builtIn="false" value=""${workspace_loc:/${ProjName}/Config}""/>\r
+ <listOptionValue builtIn="false" value=""${workspace_loc:/${ProjName}/Demo}""/>\r
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+ <additionalInput kind="additionalinputdependency" paths="$(USER_OBJS)"/>\r
+ <additionalInput kind="additionalinput" paths="$(LIBS)"/>\r
+ </inputType>\r
+ </tool>\r
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+ </tool>\r
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+ </toolChain>\r
+ </folderInfo>\r
+ </configuration>\r
+ </storageModule>\r
+ <storageModule moduleId="org.eclipse.cdt.core.externalSettings"/>\r
+ </cconfiguration>\r
+ </storageModule>\r
+ <storageModule moduleId="cdtBuildSystem" version="4.0.0">\r
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+ <autodiscovery enabled="true" problemReportingEnabled="true" selectedProfileId=""/>\r
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+ <autodiscovery enabled="false" problemReportingEnabled="true" selectedProfileId=""/>\r
+ </scannerConfigBuildInfo>\r
+ </storageModule>\r
+</cproject>\r
--- /dev/null
+<?xml version="1.0" encoding="UTF-8"?>\r
+<projectDescription>\r
+ <name>FreeRTOSDemo</name>\r
+ <comment></comment>\r
+ <projects>\r
+ </projects>\r
+ <buildSpec>\r
+ <buildCommand>\r
+ <name>org.eclipse.cdt.managedbuilder.core.genmakebuilder</name>\r
+ <triggers>clean,full,incremental,</triggers>\r
+ <arguments>\r
+ </arguments>\r
+ </buildCommand>\r
+ <buildCommand>\r
+ <name>org.eclipse.cdt.managedbuilder.core.ScannerConfigBuilder</name>\r
+ <triggers>full,incremental,</triggers>\r
+ <arguments>\r
+ </arguments>\r
+ </buildCommand>\r
+ </buildSpec>\r
+ <natures>\r
+ <nature>com.st.stm32cube.ide.mcu.MCUProjectNature</nature>\r
+ <nature>com.st.stm32cube.ide.mcu.MCUCubeProjectNature</nature>\r
+ <nature>org.eclipse.cdt.core.cnature</nature>\r
+ <nature>com.st.stm32cube.ide.mcu.MCUCubeIdeServicesRevAProjectNature</nature>\r
+ <nature>com.st.stm32cube.ide.mcu.MCUAdvancedStructureProjectNature</nature>\r
+ <nature>com.st.stm32cube.ide.mcu.MCUEndUserDisabledTrustZoneProjectNature</nature>\r
+ <nature>com.st.stm32cube.ide.mcu.MCUSingleCpuProjectNature</nature>\r
+ <nature>com.st.stm32cube.ide.mcu.MCURootProjectNature</nature>\r
+ <nature>org.eclipse.cdt.managedbuilder.core.managedBuildNature</nature>\r
+ <nature>org.eclipse.cdt.managedbuilder.core.ScannerConfigNature</nature>\r
+ </natures>\r
+ <linkedResources>\r
+ <link>\r
+ <name>Config</name>\r
+ <type>2</type>\r
+ <locationURI>PARENT-2-PROJECT_LOC/Config</locationURI>\r
+ </link>\r
+ <link>\r
+ <name>Demo</name>\r
+ <type>2</type>\r
+ <locationURI>PARENT-2-PROJECT_LOC/Demo</locationURI>\r
+ </link>\r
+ <link>\r
+ <name>FreeRTOS</name>\r
+ <type>2</type>\r
+ <locationURI>PARENT-4-PROJECT_LOC/Source</locationURI>\r
+ </link>\r
+ <link>\r
+ <name>ST_Code</name>\r
+ <type>2</type>\r
+ <locationURI>PARENT-2-PROJECT_LOC/ST_Code</locationURI>\r
+ </link>\r
+ </linkedResources>\r
+ <filteredResources>\r
+ <filter>\r
+ <id>1579730437023</id>\r
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+ <type>9</type>\r
+ <matcher>\r
+ <id>org.eclipse.ui.ide.multiFilter</id>\r
+ <arguments>1.0-name-matches-false-false-Common</arguments>\r
+ </matcher>\r
+ </filter>\r
+ <filter>\r
+ <id>1579730437029</id>\r
+ <name>FreeRTOS/portable</name>\r
+ <type>9</type>\r
+ <matcher>\r
+ <id>org.eclipse.ui.ide.multiFilter</id>\r
+ <arguments>1.0-name-matches-false-false-MemMang</arguments>\r
+ </matcher>\r
+ </filter>\r
+ <filter>\r
+ <id>1579730437034</id>\r
+ <name>FreeRTOS/portable</name>\r
+ <type>9</type>\r
+ <matcher>\r
+ <id>org.eclipse.ui.ide.multiFilter</id>\r
+ <arguments>1.0-name-matches-false-false-GCC</arguments>\r
+ </matcher>\r
+ </filter>\r
+ <filter>\r
+ <id>1579730469419</id>\r
+ <name>FreeRTOS/portable/GCC</name>\r
+ <type>9</type>\r
+ <matcher>\r
+ <id>org.eclipse.ui.ide.multiFilter</id>\r
+ <arguments>1.0-name-matches-false-false-ARM_CM3_MPU</arguments>\r
+ </matcher>\r
+ </filter>\r
+ <filter>\r
+ <id>1579730451568</id>\r
+ <name>FreeRTOS/portable/MemMang</name>\r
+ <type>5</type>\r
+ <matcher>\r
+ <id>org.eclipse.ui.ide.multiFilter</id>\r
+ <arguments>1.0-name-matches-false-false-heap_4.c</arguments>\r
+ </matcher>\r
+ </filter>\r
+ </filteredResources>\r
+</projectDescription>\r
--- /dev/null
+/*
+******************************************************************************
+**
+** File : LinkerScript.ld
+**
+** Author : Auto-generated by STM32CubeIDE
+**
+** Abstract : Linker script for NUCLEO-L152RE Board embedding STM32L152RETx Device from STM32L1 series
+** 512Kbytes FLASH
+** 80Kbytes RAM
+**
+** Set heap size, stack size and stack location according
+** to application requirements.
+**
+** Set memory bank area and size if external memory is used.
+**
+** Target : STMicroelectronics STM32
+**
+** Distribution: The file is distributed as is without any warranty
+** of any kind.
+**
+*****************************************************************************
+** @attention
+**
+** <h2><center>© COPYRIGHT(c) 2020 STMicroelectronics</center></h2>
+**
+** Redistribution and use in source and binary forms, with or without modification,
+** are permitted provided that the following conditions are met:
+** 1. Redistributions of source code must retain the above copyright notice,
+** this list of conditions and the following disclaimer.
+** 2. Redistributions in binary form must reproduce the above copyright notice,
+** this list of conditions and the following disclaimer in the documentation
+** and/or other materials provided with the distribution.
+** 3. Neither the name of STMicroelectronics nor the names of its contributors
+** may be used to endorse or promote products derived from this software
+** without specific prior written permission.
+**
+** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+** AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+** IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+** FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+** DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+** SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+** CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+** OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+** OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+**
+*****************************************************************************
+*/
+
+/* Entry Point. */
+ENTRY(Reset_Handler)
+
+/* Highest address of the user mode stack. */
+_estack = ORIGIN(RAM) + LENGTH(RAM); /* end of "RAM" Ram type memory. */
+
+_Min_Heap_Size = 0x200 ; /* Required amount of heap. */
+_Min_Stack_Size = 0x400 ; /* Required amount of stack. */
+
+/* Memories definition. */
+/* ARMv7M MPU requires that the base address of a MPU region must be aligned to
+ * an interger mutiple of the region size and the region size can only be a
+ * power of 2. We, therefore, are not using last 16K of RAM. */
+MEMORY
+{
+ RAM (xrw) : ORIGIN = 0x20000000, LENGTH = 64K
+ RAM_UNUSED (xrw) : ORIGIN = 0x20010000, LENGTH = 16K
+ FLASH (rx) : ORIGIN = 0x8000000, LENGTH = 512K
+}
+
+/* Initial 32K Flash is used to store kernel functions and
+ * initial 512 bytes of RAM is used to store kernel data. */
+__privileged_functions_region_size__ = 32K;
+__privileged_data_region_size__ = 512;
+
+__FLASH_segment_start__ = ORIGIN( FLASH );
+__FLASH_segment_end__ = __FLASH_segment_start__ + LENGTH( FLASH );
+
+__SRAM_segment_start__ = ORIGIN( RAM );
+__SRAM_segment_end__ = __SRAM_segment_start__ + LENGTH( RAM );
+
+__privileged_functions_start__ = __FLASH_segment_start__;
+__privileged_functions_end__ = __FLASH_segment_start__ + __privileged_functions_region_size__;
+
+__privileged_data_start__ = __SRAM_segment_start__;
+__privileged_data_end__ = __SRAM_segment_start__ + __privileged_data_region_size__;
+
+/* Sections. */
+SECTIONS
+{
+ /* The startup code and FreeRTOS kernel code are placed into privileged
+ * flash. */
+ .privileged_functions :
+ {
+ . = ALIGN(4);
+ KEEP(*(.isr_vector)) /* Startup code */
+ . = ALIGN(4);
+ *(privileged_functions)
+ . = ALIGN(4);
+ FILL(0xDEAD);
+ /* Ensure that un-privileged code is placed after the region reserved
+ * for privileged kernel code. */
+ /* Note that dot (.) actually refers to the byte offset from the start
+ * of the current section (.privileged_functions in this case). As a
+ * result, setting dot (.) to a value sets the size of the section. */
+ . = __privileged_functions_region_size__;
+ } >FLASH
+
+ /* The rest of the program code and other data into the remaining
+ * unprivileged flash. */
+ .text :
+ {
+ /* Place the FreeRTOS System Calls first in the unprivileged region. */
+ . = ALIGN(4);
+ __syscalls_flash_start__ = .;
+ *(freertos_system_calls)
+ __syscalls_flash_end__ = .;
+ . = ALIGN(4);
+ *(.text) /* .text sections (code). */
+ *(.text*) /* .text* sections (code). */
+ *(.glue_7) /* glue arm to thumb code. */
+ *(.glue_7t) /* glue thumb to arm code. */
+ *(.eh_frame)
+
+ KEEP (*(.init))
+ KEEP (*(.fini))
+
+ . = ALIGN(4);
+ _etext = .; /* define a global symbols at end of code. */
+ } >FLASH
+
+ /* Constant data into "FLASH" Rom type memory. */
+ .rodata :
+ {
+ . = ALIGN(4);
+ *(.rodata) /* .rodata sections (constants, strings, etc.). */
+ *(.rodata*) /* .rodata* sections (constants, strings, etc.). */
+ . = ALIGN(4);
+ } >FLASH
+
+ .ARM.extab :
+ {
+ . = ALIGN(4);
+ *(.ARM.extab* .gnu.linkonce.armextab.*)
+ . = ALIGN(4);
+ } >FLASH
+
+ .ARM :
+ {
+ . = ALIGN(4);
+ __exidx_start = .;
+ *(.ARM.exidx*)
+ __exidx_end = .;
+ . = ALIGN(4);
+ } >FLASH
+
+ .preinit_array :
+ {
+ . = ALIGN(4);
+ PROVIDE_HIDDEN (__preinit_array_start = .);
+ KEEP (*(.preinit_array*))
+ PROVIDE_HIDDEN (__preinit_array_end = .);
+ . = ALIGN(4);
+ } >FLASH
+
+ .init_array :
+ {
+ . = ALIGN(4);
+ PROVIDE_HIDDEN (__init_array_start = .);
+ KEEP (*(SORT(.init_array.*)))
+ KEEP (*(.init_array*))
+ PROVIDE_HIDDEN (__init_array_end = .);
+ . = ALIGN(4);
+ } >FLASH
+
+ .fini_array :
+ {
+ . = ALIGN(4);
+ PROVIDE_HIDDEN (__fini_array_start = .);
+ KEEP (*(SORT(.fini_array.*)))
+ KEEP (*(.fini_array*))
+ PROVIDE_HIDDEN (__fini_array_end = .);
+ . = ALIGN(4);
+ } >FLASH
+
+ /* Used by the startup to initialize data. */
+ _sidata = LOADADDR(.privileged_data);
+
+ /* FreeRTOS kernel data. */
+ .privileged_data :
+ {
+ . = ALIGN(4);
+ _sdata = .; /* Create a global symbol at data start. */
+ *(privileged_data)
+ . = ALIGN(4);
+ FILL(0xDEAD);
+ /* Ensure that un-privileged data is placed after the region reserved
+ * for privileged kernel data. */
+ /* Note that dot (.) actually refers to the byte offset from the start
+ * of the current section (.privileged_data in this case). As a result,
+ * setting dot (.) to a value sets the size of the section. */
+ . = __privileged_data_region_size__;
+ } >RAM AT> FLASH
+
+ /* Initialized data sections into "RAM" Ram type memory. */
+ .data :
+ {
+ . = ALIGN(4);
+ *(.data) /* .data sections. */
+ *(.data*) /* .data* sections. */
+
+ . = ALIGN(4);
+ _edata = .; /* define a global symbol at data end. */
+ } >RAM AT> FLASH
+
+ /* Uninitialized data section into "RAM" Ram type memory. */
+ . = ALIGN(4);
+ .bss :
+ {
+ /* This is used by the startup in order to initialize the .bss section. */
+ _sbss = .; /* define a global symbol at bss start. */
+ __bss_start__ = _sbss;
+ *(.bss)
+ *(.bss*)
+ *(COMMON)
+
+ . = ALIGN(4);
+ _ebss = .; /* define a global symbol at bss end. */
+ __bss_end__ = _ebss;
+ } >RAM
+
+ /* User_heap_stack section, used to check that there is enough "RAM" Ram
+ * type memory left. */
+ ._user_heap_stack :
+ {
+ . = ALIGN(8);
+ PROVIDE ( end = . );
+ PROVIDE ( _end = . );
+ . = . + _Min_Heap_Size;
+ . = . + _Min_Stack_Size;
+ . = ALIGN(8);
+ } >RAM
+
+ /* Remove information from the compiler libraries. */
+ /DISCARD/ :
+ {
+ libc.a ( * )
+ libm.a ( * )
+ libgcc.a ( * )
+ }
+
+ .ARM.attributes 0 : { *(.ARM.attributes) }
+}
--- /dev/null
+/*\r
+ * FreeRTOS Kernel V10.2.1\r
+ * Copyright (C) 2019 Amazon.com, Inc. or its affiliates. All Rights Reserved.\r
+ *\r
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of\r
+ * this software and associated documentation files (the "Software"), to deal in\r
+ * the Software without restriction, including without limitation the rights to\r
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of\r
+ * the Software, and to permit persons to whom the Software is furnished to do so,\r
+ * subject to the following conditions:\r
+ *\r
+ * The above copyright notice and this permission notice shall be included in all\r
+ * copies or substantial portions of the Software.\r
+ *\r
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR\r
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS\r
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR\r
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER\r
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN\r
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.\r
+ *\r
+ * http://www.FreeRTOS.org\r
+ * http://aws.amazon.com/freertos\r
+ *\r
+ * 1 tab == 4 spaces!\r
+ */\r
+\r
+/**\r
+ * @brief Mem fault handler.\r
+ */\r
+void MemManage_Handler( void ) __attribute__ (( naked ));\r
+/*-----------------------------------------------------------*/\r
+\r
+void MemManage_Handler( void )\r
+{\r
+ __asm volatile\r
+ (\r
+ " tst lr, #4 \n"\r
+ " ite eq \n"\r
+ " mrseq r0, msp \n"\r
+ " mrsne r0, psp \n"\r
+ " ldr r1, handler_address_const \n"\r
+ " bx r1 \n"\r
+ " \n"\r
+ " handler_address_const: .word vHandleMemoryFault \n"\r
+ );\r
+}\r
+/*-----------------------------------------------------------*/\r
--- /dev/null
+/**\r
+ ******************************************************************************\r
+ * @file startup_stm32l152xe.s\r
+ * @author MCD Application Team\r
+ * @brief STM32L152XE Devices vector table for GCC toolchain.\r
+ * This module performs:\r
+ * - Set the initial SP\r
+ * - Set the initial PC == Reset_Handler,\r
+ * - Set the vector table entries with the exceptions ISR address\r
+ * - Configure the clock system\r
+ * - Branches to main in the C library (which eventually\r
+ * calls main()).\r
+ * After Reset the Cortex-M3 processor is in Thread mode,\r
+ * priority is Privileged, and the Stack is set to Main.\r
+ ******************************************************************************\r
+ *\r
+ * @attention\r
+ *\r
+ * Copyright (c) 2017 STMicroelectronics. All rights reserved.\r
+ *\r
+ * This software component is licensed by ST under BSD 3-Clause license,\r
+ * the "License"; You may not use this file except in compliance with the \r
+ * License. You may obtain a copy of the License at:\r
+ * opensource.org/licenses/BSD-3-Clause\r
+ *\r
+ ******************************************************************************\r
+ */\r
+\r
+ .syntax unified\r
+ .cpu cortex-m3\r
+ .fpu softvfp\r
+ .thumb\r
+\r
+.global g_pfnVectors\r
+.global Default_Handler\r
+\r
+/* start address for the initialization values of the .data section.\r
+defined in linker script */\r
+.word _sidata\r
+/* start address for the .data section. defined in linker script */\r
+.word _sdata\r
+/* end address for the .data section. defined in linker script */\r
+.word _edata\r
+/* start address for the .bss section. defined in linker script */\r
+.word _sbss\r
+/* end address for the .bss section. defined in linker script */\r
+.word _ebss\r
+\r
+.equ BootRAM, 0xF108F85F\r
+/**\r
+ * @brief This is the code that gets called when the processor first\r
+ * starts execution following a reset event. Only the absolutely\r
+ * necessary set is performed, after which the application\r
+ * supplied main() routine is called.\r
+ * @param None\r
+ * @retval : None\r
+*/\r
+\r
+ .section .text.Reset_Handler\r
+ .weak Reset_Handler\r
+ .type Reset_Handler, %function\r
+Reset_Handler:\r
+\r
+/* Copy the data segment initializers from flash to SRAM */\r
+ movs r1, #0\r
+ b LoopCopyDataInit\r
+\r
+CopyDataInit:\r
+ ldr r3, =_sidata\r
+ ldr r3, [r3, r1]\r
+ str r3, [r0, r1]\r
+ adds r1, r1, #4\r
+\r
+LoopCopyDataInit:\r
+ ldr r0, =_sdata\r
+ ldr r3, =_edata\r
+ adds r2, r0, r1\r
+ cmp r2, r3\r
+ bcc CopyDataInit\r
+ ldr r2, =_sbss\r
+ b LoopFillZerobss\r
+/* Zero fill the bss segment. */\r
+FillZerobss:\r
+ movs r3, #0\r
+ str r3, [r2], #4\r
+\r
+LoopFillZerobss:\r
+ ldr r3, = _ebss\r
+ cmp r2, r3\r
+ bcc FillZerobss\r
+\r
+/* Call the clock system intitialization function.*/\r
+ bl SystemInit\r
+/* Call static constructors */\r
+ bl __libc_init_array\r
+/* Call the application's entry point.*/\r
+ bl main\r
+ bx lr\r
+.size Reset_Handler, .-Reset_Handler\r
+\r
+/**\r
+ * @brief This is the code that gets called when the processor receives an\r
+ * unexpected interrupt. This simply enters an infinite loop, preserving\r
+ * the system state for examination by a debugger.\r
+ *\r
+ * @param None\r
+ * @retval : None\r
+*/\r
+ .section .text.Default_Handler,"ax",%progbits\r
+Default_Handler:\r
+Infinite_Loop:\r
+ b Infinite_Loop\r
+ .size Default_Handler, .-Default_Handler\r
+/******************************************************************************\r
+*\r
+* The minimal vector table for a Cortex M3. Note that the proper constructs\r
+* must be placed on this to ensure that it ends up at physical address\r
+* 0x0000.0000.\r
+*\r
+******************************************************************************/\r
+ .section .isr_vector,"a",%progbits\r
+ .type g_pfnVectors, %object\r
+ .size g_pfnVectors, .-g_pfnVectors\r
+\r
+\r
+g_pfnVectors:\r
+ .word _estack\r
+ .word Reset_Handler\r
+ .word NMI_Handler\r
+ .word HardFault_Handler\r
+ .word MemManage_Handler\r
+ .word BusFault_Handler\r
+ .word UsageFault_Handler\r
+ .word 0\r
+ .word 0\r
+ .word 0\r
+ .word 0\r
+ .word SVC_Handler\r
+ .word DebugMon_Handler\r
+ .word 0\r
+ .word PendSV_Handler\r
+ .word SysTick_Handler\r
+ .word WWDG_IRQHandler\r
+ .word PVD_IRQHandler\r
+ .word TAMPER_STAMP_IRQHandler\r
+ .word RTC_WKUP_IRQHandler\r
+ .word FLASH_IRQHandler\r
+ .word RCC_IRQHandler\r
+ .word EXTI0_IRQHandler\r
+ .word EXTI1_IRQHandler\r
+ .word EXTI2_IRQHandler\r
+ .word EXTI3_IRQHandler\r
+ .word EXTI4_IRQHandler\r
+ .word DMA1_Channel1_IRQHandler\r
+ .word DMA1_Channel2_IRQHandler\r
+ .word DMA1_Channel3_IRQHandler\r
+ .word DMA1_Channel4_IRQHandler\r
+ .word DMA1_Channel5_IRQHandler\r
+ .word DMA1_Channel6_IRQHandler\r
+ .word DMA1_Channel7_IRQHandler\r
+ .word ADC1_IRQHandler\r
+ .word USB_HP_IRQHandler\r
+ .word USB_LP_IRQHandler\r
+ .word DAC_IRQHandler\r
+ .word COMP_IRQHandler\r
+ .word EXTI9_5_IRQHandler\r
+ .word LCD_IRQHandler \r
+ .word TIM9_IRQHandler\r
+ .word TIM10_IRQHandler\r
+ .word TIM11_IRQHandler\r
+ .word TIM2_IRQHandler\r
+ .word TIM3_IRQHandler\r
+ .word TIM4_IRQHandler\r
+ .word I2C1_EV_IRQHandler\r
+ .word I2C1_ER_IRQHandler\r
+ .word I2C2_EV_IRQHandler\r
+ .word I2C2_ER_IRQHandler\r
+ .word SPI1_IRQHandler\r
+ .word SPI2_IRQHandler\r
+ .word USART1_IRQHandler\r
+ .word USART2_IRQHandler\r
+ .word USART3_IRQHandler\r
+ .word EXTI15_10_IRQHandler\r
+ .word RTC_Alarm_IRQHandler\r
+ .word USB_FS_WKUP_IRQHandler\r
+ .word TIM6_IRQHandler\r
+ .word TIM7_IRQHandler\r
+ .word 0\r
+ .word TIM5_IRQHandler\r
+ .word SPI3_IRQHandler\r
+ .word UART4_IRQHandler\r
+ .word UART5_IRQHandler\r
+ .word DMA2_Channel1_IRQHandler\r
+ .word DMA2_Channel2_IRQHandler\r
+ .word DMA2_Channel3_IRQHandler\r
+ .word DMA2_Channel4_IRQHandler\r
+ .word DMA2_Channel5_IRQHandler\r
+ .word 0\r
+ .word COMP_ACQ_IRQHandler\r
+ .word 0\r
+ .word 0\r
+ .word 0\r
+ .word 0\r
+ .word 0\r
+ .word BootRAM /* @0x108. This is for boot in RAM mode for \r
+ STM32L152XE devices. */\r
+\r
+/*******************************************************************************\r
+*\r
+* Provide weak aliases for each Exception handler to the Default_Handler.\r
+* As they are weak aliases, any function with the same name will override\r
+* this definition.\r
+*\r
+*******************************************************************************/\r
+\r
+ .weak NMI_Handler\r
+ .thumb_set NMI_Handler,Default_Handler\r
+\r
+ .weak HardFault_Handler\r
+ .thumb_set HardFault_Handler,Default_Handler\r
+\r
+ .weak MemManage_Handler\r
+ .thumb_set MemManage_Handler,Default_Handler\r
+\r
+ .weak BusFault_Handler\r
+ .thumb_set BusFault_Handler,Default_Handler\r
+\r
+ .weak UsageFault_Handler\r
+ .thumb_set UsageFault_Handler,Default_Handler\r
+\r
+ .weak SVC_Handler\r
+ .thumb_set SVC_Handler,Default_Handler\r
+\r
+ .weak DebugMon_Handler\r
+ .thumb_set DebugMon_Handler,Default_Handler\r
+\r
+ .weak PendSV_Handler\r
+ .thumb_set PendSV_Handler,Default_Handler\r
+\r
+ .weak SysTick_Handler\r
+ .thumb_set SysTick_Handler,Default_Handler\r
+\r
+ .weak WWDG_IRQHandler\r
+ .thumb_set WWDG_IRQHandler,Default_Handler\r
+\r
+ .weak PVD_IRQHandler\r
+ .thumb_set PVD_IRQHandler,Default_Handler\r
+\r
+ .weak TAMPER_STAMP_IRQHandler\r
+ .thumb_set TAMPER_STAMP_IRQHandler,Default_Handler\r
+\r
+ .weak RTC_WKUP_IRQHandler\r
+ .thumb_set RTC_WKUP_IRQHandler,Default_Handler\r
+\r
+ .weak FLASH_IRQHandler\r
+ .thumb_set FLASH_IRQHandler,Default_Handler\r
+\r
+ .weak RCC_IRQHandler\r
+ .thumb_set RCC_IRQHandler,Default_Handler\r
+\r
+ .weak EXTI0_IRQHandler\r
+ .thumb_set EXTI0_IRQHandler,Default_Handler\r
+\r
+ .weak EXTI1_IRQHandler\r
+ .thumb_set EXTI1_IRQHandler,Default_Handler\r
+\r
+ .weak EXTI2_IRQHandler\r
+ .thumb_set EXTI2_IRQHandler,Default_Handler\r
+\r
+ .weak EXTI3_IRQHandler\r
+ .thumb_set EXTI3_IRQHandler,Default_Handler\r
+\r
+ .weak EXTI4_IRQHandler\r
+ .thumb_set EXTI4_IRQHandler,Default_Handler\r
+\r
+ .weak DMA1_Channel1_IRQHandler\r
+ .thumb_set DMA1_Channel1_IRQHandler,Default_Handler\r
+\r
+ .weak DMA1_Channel2_IRQHandler\r
+ .thumb_set DMA1_Channel2_IRQHandler,Default_Handler\r
+\r
+ .weak DMA1_Channel3_IRQHandler\r
+ .thumb_set DMA1_Channel3_IRQHandler,Default_Handler\r
+\r
+ .weak DMA1_Channel4_IRQHandler\r
+ .thumb_set DMA1_Channel4_IRQHandler,Default_Handler\r
+\r
+ .weak DMA1_Channel5_IRQHandler\r
+ .thumb_set DMA1_Channel5_IRQHandler,Default_Handler\r
+\r
+ .weak DMA1_Channel6_IRQHandler\r
+ .thumb_set DMA1_Channel6_IRQHandler,Default_Handler\r
+\r
+ .weak DMA1_Channel7_IRQHandler\r
+ .thumb_set DMA1_Channel7_IRQHandler,Default_Handler\r
+\r
+ .weak ADC1_IRQHandler\r
+ .thumb_set ADC1_IRQHandler,Default_Handler\r
+\r
+ .weak USB_HP_IRQHandler\r
+ .thumb_set USB_HP_IRQHandler,Default_Handler\r
+\r
+ .weak USB_LP_IRQHandler\r
+ .thumb_set USB_LP_IRQHandler,Default_Handler\r
+\r
+ .weak DAC_IRQHandler\r
+ .thumb_set DAC_IRQHandler,Default_Handler\r
+\r
+ .weak COMP_IRQHandler\r
+ .thumb_set COMP_IRQHandler,Default_Handler\r
+\r
+ .weak EXTI9_5_IRQHandler\r
+ .thumb_set EXTI9_5_IRQHandler,Default_Handler\r
+\r
+ .weak LCD_IRQHandler\r
+ .thumb_set LCD_IRQHandler,Default_Handler \r
+\r
+ .weak TIM9_IRQHandler\r
+ .thumb_set TIM9_IRQHandler,Default_Handler\r
+\r
+ .weak TIM10_IRQHandler\r
+ .thumb_set TIM10_IRQHandler,Default_Handler\r
+\r
+ .weak TIM11_IRQHandler\r
+ .thumb_set TIM11_IRQHandler,Default_Handler\r
+\r
+ .weak TIM2_IRQHandler\r
+ .thumb_set TIM2_IRQHandler,Default_Handler\r
+\r
+ .weak TIM3_IRQHandler\r
+ .thumb_set TIM3_IRQHandler,Default_Handler\r
+\r
+ .weak TIM4_IRQHandler\r
+ .thumb_set TIM4_IRQHandler,Default_Handler\r
+\r
+ .weak I2C1_EV_IRQHandler\r
+ .thumb_set I2C1_EV_IRQHandler,Default_Handler\r
+\r
+ .weak I2C1_ER_IRQHandler\r
+ .thumb_set I2C1_ER_IRQHandler,Default_Handler\r
+\r
+ .weak I2C2_EV_IRQHandler\r
+ .thumb_set I2C2_EV_IRQHandler,Default_Handler\r
+\r
+ .weak I2C2_ER_IRQHandler\r
+ .thumb_set I2C2_ER_IRQHandler,Default_Handler\r
+\r
+ .weak SPI1_IRQHandler\r
+ .thumb_set SPI1_IRQHandler,Default_Handler\r
+\r
+ .weak SPI2_IRQHandler\r
+ .thumb_set SPI2_IRQHandler,Default_Handler\r
+\r
+ .weak USART1_IRQHandler\r
+ .thumb_set USART1_IRQHandler,Default_Handler\r
+\r
+ .weak USART2_IRQHandler\r
+ .thumb_set USART2_IRQHandler,Default_Handler\r
+\r
+ .weak USART3_IRQHandler\r
+ .thumb_set USART3_IRQHandler,Default_Handler\r
+\r
+ .weak EXTI15_10_IRQHandler\r
+ .thumb_set EXTI15_10_IRQHandler,Default_Handler\r
+\r
+ .weak RTC_Alarm_IRQHandler\r
+ .thumb_set RTC_Alarm_IRQHandler,Default_Handler\r
+\r
+ .weak USB_FS_WKUP_IRQHandler\r
+ .thumb_set USB_FS_WKUP_IRQHandler,Default_Handler\r
+\r
+ .weak TIM6_IRQHandler\r
+ .thumb_set TIM6_IRQHandler,Default_Handler\r
+\r
+ .weak TIM7_IRQHandler\r
+ .thumb_set TIM7_IRQHandler,Default_Handler\r
+\r
+ .weak TIM5_IRQHandler\r
+ .thumb_set TIM5_IRQHandler,Default_Handler\r
+ \r
+ .weak SPI3_IRQHandler\r
+ .thumb_set SPI3_IRQHandler,Default_Handler\r
+\r
+ .weak UART4_IRQHandler\r
+ .thumb_set UART4_IRQHandler,Default_Handler\r
+\r
+ .weak UART5_IRQHandler\r
+ .thumb_set UART5_IRQHandler,Default_Handler\r
+ \r
+ .weak DMA2_Channel1_IRQHandler\r
+ .thumb_set DMA2_Channel1_IRQHandler,Default_Handler\r
+\r
+ .weak DMA2_Channel2_IRQHandler\r
+ .thumb_set DMA2_Channel2_IRQHandler,Default_Handler\r
+\r
+ .weak DMA2_Channel3_IRQHandler\r
+ .thumb_set DMA2_Channel3_IRQHandler,Default_Handler\r
+\r
+ .weak DMA2_Channel4_IRQHandler\r
+ .thumb_set DMA2_Channel4_IRQHandler,Default_Handler\r
+\r
+ .weak DMA2_Channel5_IRQHandler\r
+ .thumb_set DMA2_Channel5_IRQHandler,Default_Handler\r
+\r
+ .weak COMP_ACQ_IRQHandler\r
+ .thumb_set COMP_ACQ_IRQHandler,Default_Handler\r
+\r
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\r
+\r
--- /dev/null
+/**
+*****************************************************************************
+**
+** File : syscalls.c
+**
+** Author : Auto-generated by STM32CubeIDE
+**
+** Abstract : STM32CubeIDE Minimal System calls file
+**
+** For more information about which c-functions
+** need which of these lowlevel functions
+** please consult the Newlib libc-manual
+**
+** Environment : STM32CubeIDE MCU
+**
+** Distribution: The file is distributed as is, without any warranty
+** of any kind.
+**
+*****************************************************************************
+**
+** <h2><center>© COPYRIGHT(c) 2018 STMicroelectronics</center></h2>
+**
+** Redistribution and use in source and binary forms, with or without modification,
+** are permitted provided that the following conditions are met:
+** 1. Redistributions of source code must retain the above copyright notice,
+** this list of conditions and the following disclaimer.
+** 2. Redistributions in binary form must reproduce the above copyright notice,
+** this list of conditions and the following disclaimer in the documentation
+** and/or other materials provided with the distribution.
+** 3. Neither the name of STMicroelectronics nor the names of its contributors
+** may be used to endorse or promote products derived from this software
+** without specific prior written permission.
+**
+** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+** AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+** IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+** FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+** DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+** SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+** CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+** OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+** OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+**
+**
+*****************************************************************************
+*/
+
+/* Includes */
+#include <sys/stat.h>
+#include <stdlib.h>
+#include <errno.h>
+#include <stdio.h>
+#include <signal.h>
+#include <time.h>
+#include <sys/time.h>
+#include <sys/times.h>
+
+
+/* Variables */
+//#undef errno
+extern int errno;
+extern int __io_putchar(int ch) __attribute__((weak));
+extern int __io_getchar(void) __attribute__((weak));
+
+register char * stack_ptr asm("sp");
+
+char *__env[1] = { 0 };
+char **environ = __env;
+
+
+/* Functions */
+void initialise_monitor_handles()
+{
+}
+
+int _getpid(void)
+{
+ return 1;
+}
+
+int _kill(int pid, int sig)
+{
+ errno = EINVAL;
+ return -1;
+}
+
+void _exit (int status)
+{
+ _kill(status, -1);
+ while (1) {} /* Make sure we hang here */
+}
+
+__attribute__((weak)) int _read(int file, char *ptr, int len)
+{
+ int DataIdx;
+
+ for (DataIdx = 0; DataIdx < len; DataIdx++)
+ {
+ *ptr++ = __io_getchar();
+ }
+
+return len;
+}
+
+__attribute__((weak)) int _write(int file, char *ptr, int len)
+{
+ int DataIdx;
+
+ for (DataIdx = 0; DataIdx < len; DataIdx++)
+ {
+ __io_putchar(*ptr++);
+ }
+ return len;
+}
+
+int _close(int file)
+{
+ return -1;
+}
+
+
+int _fstat(int file, struct stat *st)
+{
+ st->st_mode = S_IFCHR;
+ return 0;
+}
+
+int _isatty(int file)
+{
+ return 1;
+}
+
+int _lseek(int file, int ptr, int dir)
+{
+ return 0;
+}
+
+int _open(char *path, int flags, ...)
+{
+ /* Pretend like we always fail */
+ return -1;
+}
+
+int _wait(int *status)
+{
+ errno = ECHILD;
+ return -1;
+}
+
+int _unlink(char *name)
+{
+ errno = ENOENT;
+ return -1;
+}
+
+int _times(struct tms *buf)
+{
+ return -1;
+}
+
+int _stat(char *file, struct stat *st)
+{
+ st->st_mode = S_IFCHR;
+ return 0;
+}
+
+int _link(char *old, char *new)
+{
+ errno = EMLINK;
+ return -1;
+}
+
+int _fork(void)
+{
+ errno = EAGAIN;
+ return -1;
+}
+
+int _execve(char *name, char **argv, char **env)
+{
+ errno = ENOMEM;
+ return -1;
+}
--- /dev/null
+/**
+*****************************************************************************
+**
+** File : sysmem.c
+**
+** Author : Auto-generated by STM32CubeIDE
+**
+** Abstract : STM32CubeIDE Minimal System Memory calls file
+**
+** For more information about which c-functions
+** need which of these lowlevel functions
+** please consult the Newlib libc-manual
+**
+** Environment : STM32CubeIDE MCU
+**
+** Distribution: The file is distributed as is, without any warranty
+** of any kind.
+**
+*****************************************************************************
+**
+** <h2><center>© COPYRIGHT(c) 2018 STMicroelectronics</center></h2>
+**
+** Redistribution and use in source and binary forms, with or without modification,
+** are permitted provided that the following conditions are met:
+** 1. Redistributions of source code must retain the above copyright notice,
+** this list of conditions and the following disclaimer.
+** 2. Redistributions in binary form must reproduce the above copyright notice,
+** this list of conditions and the following disclaimer in the documentation
+** and/or other materials provided with the distribution.
+** 3. Neither the name of STMicroelectronics nor the names of its contributors
+** may be used to endorse or promote products derived from this software
+** without specific prior written permission.
+**
+** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+** AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+** IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+** FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+** DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+** SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+** CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+** OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+** OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+**
+**
+*****************************************************************************
+*/
+
+/* Includes */
+#include <errno.h>
+#include <stdio.h>
+
+/* Variables */
+extern int errno;
+register char * stack_ptr asm("sp");
+
+/* Functions */
+
+/**
+ _sbrk
+ Increase program data space. Malloc and related functions depend on this
+**/
+caddr_t _sbrk(int incr)
+{
+ extern char end asm("end");
+ static char *heap_end;
+ char *prev_heap_end;
+
+ if (heap_end == 0)
+ heap_end = &end;
+
+ prev_heap_end = heap_end;
+ if (heap_end + incr > stack_ptr)
+ {
+ errno = ENOMEM;
+ return (caddr_t) -1;
+ }
+
+ heap_end += incr;
+
+ return (caddr_t) prev_heap_end;
+}
+
--- /dev/null
+/* USER CODE BEGIN Header */\r
+/**\r
+ ******************************************************************************\r
+ * @file : main.h\r
+ * @brief : Header for main.c file.\r
+ * This file contains the common defines of the application.\r
+ ******************************************************************************\r
+ * @attention\r
+ *\r
+ * <h2><center>© Copyright (c) 2020 STMicroelectronics.\r
+ * All rights reserved.</center></h2>\r
+ *\r
+ * This software component is licensed by ST under BSD 3-Clause license,\r
+ * the "License"; You may not use this file except in compliance with the\r
+ * License. You may obtain a copy of the License at:\r
+ * opensource.org/licenses/BSD-3-Clause\r
+ *\r
+ ******************************************************************************\r
+ */\r
+/* USER CODE END Header */\r
+\r
+/* Define to prevent recursive inclusion -------------------------------------*/\r
+#ifndef __MAIN_H\r
+#define __MAIN_H\r
+\r
+#ifdef __cplusplus\r
+extern "C" {\r
+#endif\r
+\r
+/* Includes ------------------------------------------------------------------*/\r
+#include "stm32l1xx_hal.h"\r
+\r
+/* Private includes ----------------------------------------------------------*/\r
+/* USER CODE BEGIN Includes */\r
+\r
+/* USER CODE END Includes */\r
+\r
+/* Exported types ------------------------------------------------------------*/\r
+/* USER CODE BEGIN ET */\r
+\r
+/* USER CODE END ET */\r
+\r
+/* Exported constants --------------------------------------------------------*/\r
+/* USER CODE BEGIN EC */\r
+\r
+/* USER CODE END EC */\r
+\r
+/* Exported macro ------------------------------------------------------------*/\r
+/* USER CODE BEGIN EM */\r
+\r
+/* USER CODE END EM */\r
+\r
+/* Exported functions prototypes ---------------------------------------------*/\r
+void Error_Handler(void);\r
+\r
+/* USER CODE BEGIN EFP */\r
+\r
+/* USER CODE END EFP */\r
+\r
+/* Private defines -----------------------------------------------------------*/\r
+#define B1_Pin GPIO_PIN_13\r
+#define B1_GPIO_Port GPIOC\r
+#define USART_TX_Pin GPIO_PIN_2\r
+#define USART_TX_GPIO_Port GPIOA\r
+#define USART_RX_Pin GPIO_PIN_3\r
+#define USART_RX_GPIO_Port GPIOA\r
+#define LD2_Pin GPIO_PIN_5\r
+#define LD2_GPIO_Port GPIOA\r
+#define TMS_Pin GPIO_PIN_13\r
+#define TMS_GPIO_Port GPIOA\r
+#define TCK_Pin GPIO_PIN_14\r
+#define TCK_GPIO_Port GPIOA\r
+#define SWO_Pin GPIO_PIN_3\r
+#define SWO_GPIO_Port GPIOB\r
+/* USER CODE BEGIN Private defines */\r
+\r
+/* USER CODE END Private defines */\r
+\r
+#ifdef __cplusplus\r
+}\r
+#endif\r
+\r
+#endif /* __MAIN_H */\r
+\r
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\r
--- /dev/null
+/**\r
+ ******************************************************************************\r
+ * @file stm32l1xx_hal_conf.h\r
+ * @brief HAL configuration file. \r
+ ******************************************************************************\r
+ * @attention\r
+ *\r
+ * <h2><center>© COPYRIGHT(c) 2020 STMicroelectronics</center></h2>\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without modification,\r
+ * are permitted provided that the following conditions are met:\r
+ * 1. Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the following disclaimer.\r
+ * 2. Redistributions in binary form must reproduce the above copyright notice,\r
+ * this list of conditions and the following disclaimer in the documentation\r
+ * and/or other materials provided with the distribution.\r
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors\r
+ * may be used to endorse or promote products derived from this software\r
+ * without specific prior written permission.\r
+ *\r
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"\r
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\r
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE\r
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE\r
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\r
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR\r
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER\r
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,\r
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\r
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r
+ *\r
+ ******************************************************************************\r
+ */ \r
+\r
+/* Define to prevent recursive inclusion -------------------------------------*/\r
+#ifndef __STM32L1xx_HAL_CONF_H\r
+#define __STM32L1xx_HAL_CONF_H\r
+\r
+#ifdef __cplusplus\r
+ extern "C" {\r
+#endif\r
+\r
+/* Exported types ------------------------------------------------------------*/\r
+/* Exported constants --------------------------------------------------------*/\r
+\r
+/* ########################## Module Selection ############################## */\r
+/**\r
+ * @brief This is the list of modules to be used in the HAL driver \r
+ */\r
+\r
+#define HAL_MODULE_ENABLED \r
+/*#define HAL_ADC_MODULE_ENABLED */\r
+/*#define HAL_CRYP_MODULE_ENABLED */\r
+/*#define HAL_COMP_MODULE_ENABLED */\r
+/*#define HAL_CRC_MODULE_ENABLED */\r
+/*#define HAL_CRYP_MODULE_ENABLED */\r
+/*#define HAL_DAC_MODULE_ENABLED */\r
+/*#define HAL_I2C_MODULE_ENABLED */\r
+/*#define HAL_I2S_MODULE_ENABLED */\r
+/*#define HAL_IRDA_MODULE_ENABLED */\r
+/*#define HAL_IWDG_MODULE_ENABLED */\r
+/*#define HAL_LCD_MODULE_ENABLED */\r
+/*#define HAL_NOR_MODULE_ENABLED */\r
+/*#define HAL_OPAMP_MODULE_ENABLED */\r
+/*#define HAL_PCD_MODULE_ENABLED */\r
+/*#define HAL_RTC_MODULE_ENABLED */\r
+/*#define HAL_SD_MODULE_ENABLED */\r
+/*#define HAL_SMARTCARD_MODULE_ENABLED */\r
+/*#define HAL_SPI_MODULE_ENABLED */\r
+/*#define HAL_SRAM_MODULE_ENABLED */\r
+#define HAL_TIM_MODULE_ENABLED\r
+#define HAL_UART_MODULE_ENABLED\r
+/*#define HAL_USART_MODULE_ENABLED */\r
+/*#define HAL_WWDG_MODULE_ENABLED */\r
+/*#define HAL_EXTI_MODULE_ENABLED */\r
+#define HAL_GPIO_MODULE_ENABLED\r
+#define HAL_DMA_MODULE_ENABLED\r
+#define HAL_RCC_MODULE_ENABLED\r
+#define HAL_FLASH_MODULE_ENABLED\r
+#define HAL_PWR_MODULE_ENABLED\r
+#define HAL_CORTEX_MODULE_ENABLED\r
+\r
+/* ########################## Oscillator Values adaptation ####################*/\r
+/**\r
+ * @brief Adjust the value of External High Speed oscillator (HSE) used in your application.\r
+ * This value is used by the RCC HAL module to compute the system frequency\r
+ * (when HSE is used as system clock source, directly or through the PLL). \r
+ */\r
+#if !defined (HSE_VALUE) \r
+ #define HSE_VALUE ((uint32_t)8000000) /*!< Value of the External oscillator in Hz */\r
+#endif /* HSE_VALUE */\r
+\r
+#if !defined (HSE_STARTUP_TIMEOUT)\r
+ #define HSE_STARTUP_TIMEOUT ((uint32_t)100) /*!< Time out for HSE start up, in ms */\r
+#endif /* HSE_STARTUP_TIMEOUT */\r
+\r
+/**\r
+ * @brief Internal Multiple Speed oscillator (MSI) default value.\r
+ * This value is the default MSI range value after Reset.\r
+ */\r
+#if !defined (MSI_VALUE)\r
+ #define MSI_VALUE ((uint32_t)16000000) /*!< Value of the Internal oscillator in Hz*/\r
+#endif /* MSI_VALUE */\r
+/**\r
+ * @brief Internal High Speed oscillator (HSI) value.\r
+ * This value is used by the RCC HAL module to compute the system frequency\r
+ * (when HSI is used as system clock source, directly or through the PLL). \r
+ */\r
+#if !defined (HSI_VALUE)\r
+ #define HSI_VALUE ((uint32_t)16000000) /*!< Value of the Internal oscillator in Hz*/\r
+#endif /* HSI_VALUE */\r
+\r
+/**\r
+ * @brief Internal Low Speed oscillator (LSI) value.\r
+ */\r
+#if !defined (LSI_VALUE) \r
+ #define LSI_VALUE (37000U) /*!< LSI Typical Value in Hz*/\r
+#endif /* LSI_VALUE */ /*!< Value of the Internal Low Speed oscillator in Hz\r
+ The real value may vary depending on the variations\r
+ in voltage and temperature.*/\r
+ \r
+/**\r
+ * @brief External Low Speed oscillator (LSE) value.\r
+ * This value is used by the UART, RTC HAL module to compute the system frequency\r
+ */\r
+#if !defined (LSE_VALUE)\r
+ #define LSE_VALUE ((uint32_t)32768) /*!< Value of the External oscillator in Hz*/\r
+#endif /* LSE_VALUE */\r
+\r
+#if !defined (LSE_STARTUP_TIMEOUT)\r
+ #define LSE_STARTUP_TIMEOUT ((uint32_t)5000) /*!< Time out for LSE start up, in ms */\r
+#endif /* HSE_STARTUP_TIMEOUT */\r
+\r
+/* Tip: To avoid modifying this file each time you need to use different HSE,\r
+ === you can define the HSE value in your toolchain compiler preprocessor. */\r
+\r
+/* ########################### System Configuration ######################### */\r
+/**\r
+ * @brief This is the HAL system configuration section\r
+ */ \r
+ \r
+#define VDD_VALUE ((uint32_t)3300) /*!< Value of VDD in mv */ \r
+#define TICK_INT_PRIORITY ((uint32_t)0) /*!< tick interrupt priority */ \r
+#define USE_RTOS 0 \r
+#define PREFETCH_ENABLE 0\r
+#define INSTRUCTION_CACHE_ENABLE 1\r
+#define DATA_CACHE_ENABLE 1\r
+\r
+/* ########################## Assert Selection ############################## */\r
+/**\r
+ * @brief Uncomment the line below to expanse the "assert_param" macro in the \r
+ * HAL drivers code\r
+ */\r
+/* #define USE_FULL_ASSERT 1U */\r
+\r
+/* ################## Register callback feature configuration ############### */\r
+/**\r
+ * @brief Set below the peripheral configuration to "1U" to add the support\r
+ * of HAL callback registration/deregistration feature for the HAL\r
+ * driver(s). This allows user application to provide specific callback\r
+ * functions thanks to HAL_PPP_RegisterCallback() rather than overwriting\r
+ * the default weak callback functions (see each stm32l0xx_hal_ppp.h file\r
+ * for possible callback identifiers defined in HAL_PPP_CallbackIDTypeDef\r
+ * for each PPP peripheral).\r
+ */\r
+#define USE_HAL_ADC_REGISTER_CALLBACKS 0U\r
+#define USE_HAL_COMP_REGISTER_CALLBACKS 0U\r
+#define USE_HAL_DAC_REGISTER_CALLBACKS 0U\r
+#define USE_HAL_I2C_REGISTER_CALLBACKS 0U\r
+#define USE_HAL_I2S_REGISTER_CALLBACKS 0U\r
+#define USE_HAL_IRDA_REGISTER_CALLBACKS 0U\r
+#define USE_HAL_OPAMP_REGISTER_CALLBACKS 0U\r
+#define USE_HAL_PCD_REGISTER_CALLBACKS 0U\r
+#define USE_HAL_RTC_REGISTER_CALLBACKS 0U\r
+#define USE_HAL_SDMMC_REGISTER_CALLBACKS 0U\r
+#define USE_HAL_SMARTCARD_REGISTER_CALLBACKS 0U\r
+#define USE_HAL_SPI_REGISTER_CALLBACKS 0U\r
+#define USE_HAL_TIM_REGISTER_CALLBACKS 0U\r
+#define USE_HAL_UART_REGISTER_CALLBACKS 0U\r
+#define USE_HAL_USART_REGISTER_CALLBACKS 0U\r
+#define USE_HAL_WWDG_REGISTER_CALLBACKS 0U\r
+\r
+/* ################## SPI peripheral configuration ########################## */\r
+\r
+/* CRC FEATURE: Use to activate CRC feature inside HAL SPI Driver\r
+ * Activated: CRC code is present inside driver\r
+ * Deactivated: CRC code cleaned from driver\r
+ */\r
+\r
+#define USE_SPI_CRC 0U\r
+/* Includes ------------------------------------------------------------------*/\r
+/**\r
+ * @brief Include module's header file \r
+ */\r
+\r
+#ifdef HAL_RCC_MODULE_ENABLED\r
+ #include "stm32l1xx_hal_rcc.h"\r
+#endif /* HAL_RCC_MODULE_ENABLED */\r
+\r
+#ifdef HAL_GPIO_MODULE_ENABLED\r
+ #include "stm32l1xx_hal_gpio.h"\r
+#endif /* HAL_GPIO_MODULE_ENABLED */\r
+\r
+#ifdef HAL_DMA_MODULE_ENABLED\r
+ #include "stm32l1xx_hal_dma.h"\r
+#endif /* HAL_DMA_MODULE_ENABLED */\r
+\r
+#ifdef HAL_CORTEX_MODULE_ENABLED\r
+ #include "stm32l1xx_hal_cortex.h"\r
+#endif /* HAL_CORTEX_MODULE_ENABLED */\r
+\r
+#ifdef HAL_ADC_MODULE_ENABLED\r
+ #include "stm32l1xx_hal_adc.h"\r
+#endif /* HAL_ADC_MODULE_ENABLED */\r
+\r
+#ifdef HAL_COMP_MODULE_ENABLED\r
+ #include "stm32l1xx_hal_comp.h"\r
+#endif /* HAL_COMP_MODULE_ENABLED */\r
+\r
+#ifdef HAL_CRC_MODULE_ENABLED\r
+ #include "stm32l1xx_hal_crc.h"\r
+#endif /* HAL_CRC_MODULE_ENABLED */\r
+\r
+#ifdef HAL_CRYP_MODULE_ENABLED\r
+ #include "stm32l1xx_hal_cryp.h"\r
+#endif /* HAL_CRYP_MODULE_ENABLED */\r
+\r
+#ifdef HAL_DAC_MODULE_ENABLED\r
+ #include "stm32l1xx_hal_dac.h"\r
+#endif /* HAL_DAC_MODULE_ENABLED */\r
+\r
+#ifdef HAL_FLASH_MODULE_ENABLED\r
+ #include "stm32l1xx_hal_flash.h"\r
+#endif /* HAL_FLASH_MODULE_ENABLED */\r
+\r
+#ifdef HAL_SRAM_MODULE_ENABLED\r
+ #include "stm32l1xx_hal_sram.h"\r
+#endif /* HAL_SRAM_MODULE_ENABLED */\r
+\r
+#ifdef HAL_NOR_MODULE_ENABLED\r
+ #include "stm32l1xx_hal_nor.h"\r
+#endif /* HAL_NOR_MODULE_ENABLED */ \r
+\r
+#ifdef HAL_I2C_MODULE_ENABLED\r
+ #include "stm32l1xx_hal_i2c.h"\r
+#endif /* HAL_I2C_MODULE_ENABLED */\r
+\r
+#ifdef HAL_I2S_MODULE_ENABLED\r
+ #include "stm32l1xx_hal_i2s.h"\r
+#endif /* HAL_I2S_MODULE_ENABLED */\r
+\r
+#ifdef HAL_IWDG_MODULE_ENABLED\r
+ #include "stm32l1xx_hal_iwdg.h"\r
+#endif /* HAL_IWDG_MODULE_ENABLED */\r
+\r
+#ifdef HAL_LCD_MODULE_ENABLED\r
+ #include "stm32l1xx_hal_lcd.h"\r
+#endif /* HAL_LCD_MODULE_ENABLED */\r
+ \r
+#ifdef HAL_OPAMP_MODULE_ENABLED\r
+ #include "stm32l1xx_hal_opamp.h"\r
+#endif /* HAL_OPAMP_MODULE_ENABLED */\r
+\r
+#ifdef HAL_PWR_MODULE_ENABLED\r
+ #include "stm32l1xx_hal_pwr.h"\r
+#endif /* HAL_PWR_MODULE_ENABLED */\r
+\r
+#ifdef HAL_RTC_MODULE_ENABLED\r
+ #include "stm32l1xx_hal_rtc.h"\r
+#endif /* HAL_RTC_MODULE_ENABLED */\r
+\r
+#ifdef HAL_SD_MODULE_ENABLED\r
+ #include "stm32l1xx_hal_sd.h"\r
+#endif /* HAL_SD_MODULE_ENABLED */ \r
+\r
+#ifdef HAL_SPI_MODULE_ENABLED\r
+ #include "stm32l1xx_hal_spi.h"\r
+#endif /* HAL_SPI_MODULE_ENABLED */\r
+\r
+#ifdef HAL_TIM_MODULE_ENABLED\r
+ #include "stm32l1xx_hal_tim.h"\r
+#endif /* HAL_TIM_MODULE_ENABLED */\r
+\r
+#ifdef HAL_UART_MODULE_ENABLED\r
+ #include "stm32l1xx_hal_uart.h"\r
+#endif /* HAL_UART_MODULE_ENABLED */\r
+\r
+#ifdef HAL_USART_MODULE_ENABLED\r
+ #include "stm32l1xx_hal_usart.h"\r
+#endif /* HAL_USART_MODULE_ENABLED */\r
+\r
+#ifdef HAL_IRDA_MODULE_ENABLED\r
+ #include "stm32l1xx_hal_irda.h"\r
+#endif /* HAL_IRDA_MODULE_ENABLED */\r
+\r
+#ifdef HAL_SMARTCARD_MODULE_ENABLED\r
+ #include "stm32l1xx_hal_smartcard.h"\r
+#endif /* HAL_SMARTCARD_MODULE_ENABLED */\r
+\r
+#ifdef HAL_WWDG_MODULE_ENABLED\r
+ #include "stm32l1xx_hal_wwdg.h"\r
+#endif /* HAL_WWDG_MODULE_ENABLED */\r
+\r
+#ifdef HAL_PCD_MODULE_ENABLED\r
+ #include "stm32l1xx_hal_pcd.h"\r
+#endif /* HAL_PCD_MODULE_ENABLED */\r
+\r
+#ifdef HAL_EXTI_MODULE_ENABLED\r
+ #include "stm32l1xx_hal_exti.h"\r
+#endif /* HAL_EXTI_MODULE_ENABLED */\r
+ \r
+/* Exported macro ------------------------------------------------------------*/\r
+#ifdef USE_FULL_ASSERT\r
+/**\r
+ * @brief The assert_param macro is used for function's parameters check.\r
+ * @param expr: If expr is false, it calls assert_failed function\r
+ * which reports the name of the source file and the source\r
+ * line number of the call that failed. \r
+ * If expr is true, it returns no value.\r
+ * @retval None\r
+ */\r
+ #define assert_param(expr) ((expr) ? (void)0U : assert_failed((uint8_t *)__FILE__, __LINE__))\r
+/* Exported functions ------------------------------------------------------- */\r
+ void assert_failed(uint8_t* file, uint32_t line);\r
+#else\r
+ #define assert_param(expr) ((void)0U)\r
+#endif /* USE_FULL_ASSERT */ \r
+ \r
+#ifdef __cplusplus\r
+}\r
+#endif\r
+\r
+#endif /* __STM32L1xx_HAL_CONF_H */\r
+\r
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\r
--- /dev/null
+/* USER CODE BEGIN Header */\r
+/**\r
+ ******************************************************************************\r
+ * @file stm32l1xx_it.h\r
+ * @brief This file contains the headers of the interrupt handlers.\r
+ ******************************************************************************\r
+ * @attention\r
+ *\r
+ * <h2><center>© Copyright (c) 2020 STMicroelectronics.\r
+ * All rights reserved.</center></h2>\r
+ *\r
+ * This software component is licensed by ST under BSD 3-Clause license,\r
+ * the "License"; You may not use this file except in compliance with the\r
+ * License. You may obtain a copy of the License at:\r
+ * opensource.org/licenses/BSD-3-Clause\r
+ *\r
+ ******************************************************************************\r
+ */\r
+/* USER CODE END Header */\r
+\r
+/* Define to prevent recursive inclusion -------------------------------------*/\r
+#ifndef __STM32L1xx_IT_H\r
+#define __STM32L1xx_IT_H\r
+\r
+#ifdef __cplusplus\r
+ extern "C" {\r
+#endif \r
+\r
+/* Private includes ----------------------------------------------------------*/\r
+/* USER CODE BEGIN Includes */\r
+\r
+/* USER CODE END Includes */\r
+\r
+/* Exported types ------------------------------------------------------------*/\r
+/* USER CODE BEGIN ET */\r
+\r
+/* USER CODE END ET */\r
+\r
+/* Exported constants --------------------------------------------------------*/\r
+/* USER CODE BEGIN EC */\r
+\r
+/* USER CODE END EC */\r
+\r
+/* Exported macro ------------------------------------------------------------*/\r
+/* USER CODE BEGIN EM */\r
+\r
+/* USER CODE END EM */\r
+\r
+/* Exported functions prototypes ---------------------------------------------*/\r
+void NMI_Handler(void);\r
+void HardFault_Handler(void);\r
+void BusFault_Handler(void);\r
+void UsageFault_Handler(void);\r
+void DebugMon_Handler(void);\r
+void TIM6_IRQHandler(void);\r
+/* USER CODE BEGIN EFP */\r
+\r
+/* USER CODE END EFP */\r
+\r
+#ifdef __cplusplus\r
+}\r
+#endif\r
+\r
+#endif /* __STM32L1xx_IT_H */\r
+\r
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\r
--- /dev/null
+/* USER CODE BEGIN Header */\r
+/**\r
+ ******************************************************************************\r
+ * @file : main.c\r
+ * @brief : Main program body\r
+ ******************************************************************************\r
+ * @attention\r
+ *\r
+ * <h2><center>© Copyright (c) 2020 STMicroelectronics.\r
+ * All rights reserved.</center></h2>\r
+ *\r
+ * This software component is licensed by ST under BSD 3-Clause license,\r
+ * the "License"; You may not use this file except in compliance with the\r
+ * License. You may obtain a copy of the License at:\r
+ * opensource.org/licenses/BSD-3-Clause\r
+ *\r
+ ******************************************************************************\r
+ */\r
+/* USER CODE END Header */\r
+\r
+/* Includes ------------------------------------------------------------------*/\r
+#include "main.h"\r
+\r
+/* Private includes ----------------------------------------------------------*/\r
+/* USER CODE BEGIN Includes */\r
+#include "app_main.h"\r
+/* USER CODE END Includes */\r
+\r
+/* Private typedef -----------------------------------------------------------*/\r
+/* USER CODE BEGIN PTD */\r
+\r
+/* USER CODE END PTD */\r
+\r
+/* Private define ------------------------------------------------------------*/\r
+/* USER CODE BEGIN PD */\r
+/* USER CODE END PD */\r
+\r
+/* Private macro -------------------------------------------------------------*/\r
+/* USER CODE BEGIN PM */\r
+\r
+/* USER CODE END PM */\r
+\r
+/* Private variables ---------------------------------------------------------*/\r
+UART_HandleTypeDef huart2;\r
+\r
+/* USER CODE BEGIN PV */\r
+\r
+/* USER CODE END PV */\r
+\r
+/* Private function prototypes -----------------------------------------------*/\r
+void SystemClock_Config(void);\r
+static void MX_GPIO_Init(void);\r
+static void MX_USART2_UART_Init(void);\r
+/* USER CODE BEGIN PFP */\r
+\r
+/* USER CODE END PFP */\r
+\r
+/* Private user code ---------------------------------------------------------*/\r
+/* USER CODE BEGIN 0 */\r
+\r
+/* USER CODE END 0 */\r
+\r
+/**\r
+ * @brief The application entry point.\r
+ * @retval int\r
+ */\r
+int main(void)\r
+{\r
+ /* USER CODE BEGIN 1 */\r
+\r
+ /* USER CODE END 1 */\r
+ \r
+\r
+ /* MCU Configuration--------------------------------------------------------*/\r
+\r
+ /* Reset of all peripherals, Initializes the Flash interface and the Systick. */\r
+ HAL_Init();\r
+\r
+ /* USER CODE BEGIN Init */\r
+\r
+ /* USER CODE END Init */\r
+\r
+ /* Configure the system clock */\r
+ SystemClock_Config();\r
+\r
+ /* USER CODE BEGIN SysInit */\r
+\r
+ /* USER CODE END SysInit */\r
+\r
+ /* Initialize all configured peripherals */\r
+ MX_GPIO_Init();\r
+ MX_USART2_UART_Init();\r
+ /* USER CODE BEGIN 2 */\r
+ /* Call our entry point. */\r
+ app_main();\r
+ /* USER CODE END 2 */\r
+\r
+ /* Infinite loop */\r
+ /* USER CODE BEGIN WHILE */\r
+ while (1)\r
+ {\r
+ /* USER CODE END WHILE */\r
+\r
+ /* USER CODE BEGIN 3 */\r
+ }\r
+ /* USER CODE END 3 */\r
+}\r
+\r
+/**\r
+ * @brief System Clock Configuration\r
+ * @retval None\r
+ */\r
+void SystemClock_Config(void)\r
+{\r
+ RCC_OscInitTypeDef RCC_OscInitStruct = {0};\r
+ RCC_ClkInitTypeDef RCC_ClkInitStruct = {0};\r
+\r
+ /** Configure the main internal regulator output voltage \r
+ */\r
+ __HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE1);\r
+ /** Initializes the CPU, AHB and APB busses clocks \r
+ */\r
+ RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSI;\r
+ RCC_OscInitStruct.HSIState = RCC_HSI_ON;\r
+ RCC_OscInitStruct.HSICalibrationValue = RCC_HSICALIBRATION_DEFAULT;\r
+ RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON;\r
+ RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSI;\r
+ RCC_OscInitStruct.PLL.PLLMUL = RCC_PLL_MUL6;\r
+ RCC_OscInitStruct.PLL.PLLDIV = RCC_PLL_DIV3;\r
+ if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK)\r
+ {\r
+ Error_Handler();\r
+ }\r
+ /** Initializes the CPU, AHB and APB busses clocks \r
+ */\r
+ RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK|RCC_CLOCKTYPE_SYSCLK\r
+ |RCC_CLOCKTYPE_PCLK1|RCC_CLOCKTYPE_PCLK2;\r
+ RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK;\r
+ RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1;\r
+ RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV1;\r
+ RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1;\r
+\r
+ if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_1) != HAL_OK)\r
+ {\r
+ Error_Handler();\r
+ }\r
+}\r
+\r
+/**\r
+ * @brief USART2 Initialization Function\r
+ * @param None\r
+ * @retval None\r
+ */\r
+static void MX_USART2_UART_Init(void)\r
+{\r
+\r
+ /* USER CODE BEGIN USART2_Init 0 */\r
+\r
+ /* USER CODE END USART2_Init 0 */\r
+\r
+ /* USER CODE BEGIN USART2_Init 1 */\r
+\r
+ /* USER CODE END USART2_Init 1 */\r
+ huart2.Instance = USART2;\r
+ huart2.Init.BaudRate = 115200;\r
+ huart2.Init.WordLength = UART_WORDLENGTH_8B;\r
+ huart2.Init.StopBits = UART_STOPBITS_1;\r
+ huart2.Init.Parity = UART_PARITY_NONE;\r
+ huart2.Init.Mode = UART_MODE_TX_RX;\r
+ huart2.Init.HwFlowCtl = UART_HWCONTROL_NONE;\r
+ huart2.Init.OverSampling = UART_OVERSAMPLING_16;\r
+ if (HAL_UART_Init(&huart2) != HAL_OK)\r
+ {\r
+ Error_Handler();\r
+ }\r
+ /* USER CODE BEGIN USART2_Init 2 */\r
+\r
+ /* USER CODE END USART2_Init 2 */\r
+\r
+}\r
+\r
+/**\r
+ * @brief GPIO Initialization Function\r
+ * @param None\r
+ * @retval None\r
+ */\r
+static void MX_GPIO_Init(void)\r
+{\r
+ GPIO_InitTypeDef GPIO_InitStruct = {0};\r
+\r
+ /* GPIO Ports Clock Enable */\r
+ __HAL_RCC_GPIOC_CLK_ENABLE();\r
+ __HAL_RCC_GPIOH_CLK_ENABLE();\r
+ __HAL_RCC_GPIOA_CLK_ENABLE();\r
+ __HAL_RCC_GPIOB_CLK_ENABLE();\r
+\r
+ /*Configure GPIO pin Output Level */\r
+ HAL_GPIO_WritePin(LD2_GPIO_Port, LD2_Pin, GPIO_PIN_RESET);\r
+\r
+ /*Configure GPIO pin : B1_Pin */\r
+ GPIO_InitStruct.Pin = B1_Pin;\r
+ GPIO_InitStruct.Mode = GPIO_MODE_IT_RISING;\r
+ GPIO_InitStruct.Pull = GPIO_NOPULL;\r
+ HAL_GPIO_Init(B1_GPIO_Port, &GPIO_InitStruct);\r
+\r
+ /*Configure GPIO pin : LD2_Pin */\r
+ GPIO_InitStruct.Pin = LD2_Pin;\r
+ GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP;\r
+ GPIO_InitStruct.Pull = GPIO_NOPULL;\r
+ GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW;\r
+ HAL_GPIO_Init(LD2_GPIO_Port, &GPIO_InitStruct);\r
+\r
+}\r
+\r
+/* USER CODE BEGIN 4 */\r
+\r
+/* USER CODE END 4 */\r
+\r
+/**\r
+ * @brief Period elapsed callback in non blocking mode\r
+ * @note This function is called when TIM6 interrupt took place, inside\r
+ * HAL_TIM_IRQHandler(). It makes a direct call to HAL_IncTick() to increment\r
+ * a global variable "uwTick" used as application time base.\r
+ * @param htim : TIM handle\r
+ * @retval None\r
+ */\r
+void HAL_TIM_PeriodElapsedCallback(TIM_HandleTypeDef *htim)\r
+{\r
+ /* USER CODE BEGIN Callback 0 */\r
+\r
+ /* USER CODE END Callback 0 */\r
+ if (htim->Instance == TIM6) {\r
+ HAL_IncTick();\r
+ }\r
+ /* USER CODE BEGIN Callback 1 */\r
+\r
+ /* USER CODE END Callback 1 */\r
+}\r
+\r
+/**\r
+ * @brief This function is executed in case of error occurrence.\r
+ * @retval None\r
+ */\r
+void Error_Handler(void)\r
+{\r
+ /* USER CODE BEGIN Error_Handler_Debug */\r
+ /* User can add his own implementation to report the HAL error return state */\r
+\r
+ /* USER CODE END Error_Handler_Debug */\r
+}\r
+\r
+#ifdef USE_FULL_ASSERT\r
+/**\r
+ * @brief Reports the name of the source file and the source line number\r
+ * where the assert_param error has occurred.\r
+ * @param file: pointer to the source file name\r
+ * @param line: assert_param error line source number\r
+ * @retval None\r
+ */\r
+void assert_failed(uint8_t *file, uint32_t line)\r
+{ \r
+ /* USER CODE BEGIN 6 */\r
+ /* User can add his own implementation to report the file name and line number,\r
+ tex: printf("Wrong parameters value: file %s on line %d\r\n", file, line) */\r
+ /* USER CODE END 6 */\r
+}\r
+#endif /* USE_FULL_ASSERT */\r
+\r
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\r
--- /dev/null
+/* USER CODE BEGIN Header */\r
+/**\r
+ ******************************************************************************\r
+ * File Name : stm32l1xx_hal_msp.c\r
+ * Description : This file provides code for the MSP Initialization \r
+ * and de-Initialization codes.\r
+ ******************************************************************************\r
+ * @attention\r
+ *\r
+ * <h2><center>© Copyright (c) 2020 STMicroelectronics.\r
+ * All rights reserved.</center></h2>\r
+ *\r
+ * This software component is licensed by ST under BSD 3-Clause license,\r
+ * the "License"; You may not use this file except in compliance with the\r
+ * License. You may obtain a copy of the License at:\r
+ * opensource.org/licenses/BSD-3-Clause\r
+ *\r
+ ******************************************************************************\r
+ */\r
+/* USER CODE END Header */\r
+\r
+/* Includes ------------------------------------------------------------------*/\r
+#include "main.h"\r
+/* USER CODE BEGIN Includes */\r
+\r
+/* USER CODE END Includes */\r
+\r
+/* Private typedef -----------------------------------------------------------*/\r
+/* USER CODE BEGIN TD */\r
+\r
+/* USER CODE END TD */\r
+\r
+/* Private define ------------------------------------------------------------*/\r
+/* USER CODE BEGIN Define */\r
+ \r
+/* USER CODE END Define */\r
+\r
+/* Private macro -------------------------------------------------------------*/\r
+/* USER CODE BEGIN Macro */\r
+\r
+/* USER CODE END Macro */\r
+\r
+/* Private variables ---------------------------------------------------------*/\r
+/* USER CODE BEGIN PV */\r
+\r
+/* USER CODE END PV */\r
+\r
+/* Private function prototypes -----------------------------------------------*/\r
+/* USER CODE BEGIN PFP */\r
+\r
+/* USER CODE END PFP */\r
+\r
+/* External functions --------------------------------------------------------*/\r
+/* USER CODE BEGIN ExternalFunctions */\r
+\r
+/* USER CODE END ExternalFunctions */\r
+\r
+/* USER CODE BEGIN 0 */\r
+\r
+/* USER CODE END 0 */\r
+/**\r
+ * Initializes the Global MSP.\r
+ */\r
+void HAL_MspInit(void)\r
+{\r
+ /* USER CODE BEGIN MspInit 0 */\r
+\r
+ /* USER CODE END MspInit 0 */\r
+\r
+ __HAL_RCC_COMP_CLK_ENABLE();\r
+ __HAL_RCC_SYSCFG_CLK_ENABLE();\r
+ __HAL_RCC_PWR_CLK_ENABLE();\r
+\r
+ /* System interrupt init*/\r
+\r
+ /* USER CODE BEGIN MspInit 1 */\r
+\r
+ /* USER CODE END MspInit 1 */\r
+}\r
+\r
+/**\r
+* @brief UART MSP Initialization\r
+* This function configures the hardware resources used in this example\r
+* @param huart: UART handle pointer\r
+* @retval None\r
+*/\r
+void HAL_UART_MspInit(UART_HandleTypeDef* huart)\r
+{\r
+ GPIO_InitTypeDef GPIO_InitStruct = {0};\r
+ if(huart->Instance==USART2)\r
+ {\r
+ /* USER CODE BEGIN USART2_MspInit 0 */\r
+\r
+ /* USER CODE END USART2_MspInit 0 */\r
+ /* Peripheral clock enable */\r
+ __HAL_RCC_USART2_CLK_ENABLE();\r
+ \r
+ __HAL_RCC_GPIOA_CLK_ENABLE();\r
+ /**USART2 GPIO Configuration \r
+ PA2 ------> USART2_TX\r
+ PA3 ------> USART2_RX \r
+ */\r
+ GPIO_InitStruct.Pin = USART_TX_Pin|USART_RX_Pin;\r
+ GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;\r
+ GPIO_InitStruct.Pull = GPIO_PULLUP;\r
+ GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH;\r
+ GPIO_InitStruct.Alternate = GPIO_AF7_USART2;\r
+ HAL_GPIO_Init(GPIOA, &GPIO_InitStruct);\r
+\r
+ /* USER CODE BEGIN USART2_MspInit 1 */\r
+\r
+ /* USER CODE END USART2_MspInit 1 */\r
+ }\r
+\r
+}\r
+\r
+/**\r
+* @brief UART MSP De-Initialization\r
+* This function freeze the hardware resources used in this example\r
+* @param huart: UART handle pointer\r
+* @retval None\r
+*/\r
+void HAL_UART_MspDeInit(UART_HandleTypeDef* huart)\r
+{\r
+ if(huart->Instance==USART2)\r
+ {\r
+ /* USER CODE BEGIN USART2_MspDeInit 0 */\r
+\r
+ /* USER CODE END USART2_MspDeInit 0 */\r
+ /* Peripheral clock disable */\r
+ __HAL_RCC_USART2_CLK_DISABLE();\r
+ \r
+ /**USART2 GPIO Configuration \r
+ PA2 ------> USART2_TX\r
+ PA3 ------> USART2_RX \r
+ */\r
+ HAL_GPIO_DeInit(GPIOA, USART_TX_Pin|USART_RX_Pin);\r
+\r
+ /* USER CODE BEGIN USART2_MspDeInit 1 */\r
+\r
+ /* USER CODE END USART2_MspDeInit 1 */\r
+ }\r
+\r
+}\r
+\r
+/* USER CODE BEGIN 1 */\r
+\r
+/* USER CODE END 1 */\r
+\r
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\r
--- /dev/null
+/* USER CODE BEGIN Header */\r
+/**\r
+ ******************************************************************************\r
+ * @file stm32l1xx_hal_timebase_TIM.c \r
+ * @brief HAL time base based on the hardware TIM.\r
+ ******************************************************************************\r
+ * @attention\r
+ *\r
+ * <h2><center>© Copyright (c) 2020 STMicroelectronics.\r
+ * All rights reserved.</center></h2>\r
+ *\r
+ * This software component is licensed by ST under BSD 3-Clause license,\r
+ * the "License"; You may not use this file except in compliance with the\r
+ * License. You may obtain a copy of the License at:\r
+ * opensource.org/licenses/BSD-3-Clause\r
+ *\r
+ ******************************************************************************\r
+ */\r
+/* USER CODE END Header */\r
+\r
+/* Includes ------------------------------------------------------------------*/\r
+#include "stm32l1xx_hal.h"\r
+#include "stm32l1xx_hal_tim.h"\r
+ \r
+/* Private typedef -----------------------------------------------------------*/\r
+/* Private define ------------------------------------------------------------*/\r
+/* Private macro -------------------------------------------------------------*/\r
+/* Private variables ---------------------------------------------------------*/\r
+TIM_HandleTypeDef htim6; \r
+/* Private function prototypes -----------------------------------------------*/\r
+/* Private functions ---------------------------------------------------------*/\r
+\r
+/**\r
+ * @brief This function configures the TIM6 as a time base source. \r
+ * The time source is configured to have 1ms time base with a dedicated \r
+ * Tick interrupt priority. \r
+ * @note This function is called automatically at the beginning of program after\r
+ * reset by HAL_Init() or at any time when clock is configured, by HAL_RCC_ClockConfig(). \r
+ * @param TickPriority: Tick interrupt priority.\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_InitTick(uint32_t TickPriority)\r
+{\r
+ RCC_ClkInitTypeDef clkconfig;\r
+ uint32_t uwTimclock = 0;\r
+ uint32_t uwPrescalerValue = 0;\r
+ uint32_t pFLatency;\r
+ \r
+ /*Configure the TIM6 IRQ priority */\r
+ HAL_NVIC_SetPriority(TIM6_IRQn, TickPriority ,0); \r
+ \r
+ /* Enable the TIM6 global Interrupt */\r
+ HAL_NVIC_EnableIRQ(TIM6_IRQn); \r
+ \r
+ /* Enable TIM6 clock */\r
+ __HAL_RCC_TIM6_CLK_ENABLE();\r
+ \r
+ /* Get clock configuration */\r
+ HAL_RCC_GetClockConfig(&clkconfig, &pFLatency);\r
+ \r
+ /* Compute TIM6 clock */\r
+ uwTimclock = HAL_RCC_GetPCLK1Freq();\r
+ \r
+ /* Compute the prescaler value to have TIM6 counter clock equal to 1MHz */\r
+ uwPrescalerValue = (uint32_t) ((uwTimclock / 1000000) - 1);\r
+ \r
+ /* Initialize TIM6 */\r
+ htim6.Instance = TIM6;\r
+ \r
+ /* Initialize TIMx peripheral as follow:\r
+ + Period = [(TIM6CLK/1000) - 1]. to have a (1/1000) s time base.\r
+ + Prescaler = (uwTimclock/1000000 - 1) to have a 1MHz counter clock.\r
+ + ClockDivision = 0\r
+ + Counter direction = Up\r
+ */\r
+ htim6.Init.Period = (1000000 / 1000) - 1;\r
+ htim6.Init.Prescaler = uwPrescalerValue;\r
+ htim6.Init.ClockDivision = 0;\r
+ htim6.Init.CounterMode = TIM_COUNTERMODE_UP;\r
+ if(HAL_TIM_Base_Init(&htim6) == HAL_OK)\r
+ {\r
+ /* Start the TIM time Base generation in interrupt mode */\r
+ return HAL_TIM_Base_Start_IT(&htim6);\r
+ }\r
+ \r
+ /* Return function status */\r
+ return HAL_ERROR;\r
+}\r
+\r
+/**\r
+ * @brief Suspend Tick increment.\r
+ * @note Disable the tick increment by disabling TIM6 update interrupt.\r
+ * @param None\r
+ * @retval None\r
+ */\r
+void HAL_SuspendTick(void)\r
+{\r
+ /* Disable TIM6 update Interrupt */\r
+ __HAL_TIM_DISABLE_IT(&htim6, TIM_IT_UPDATE); \r
+}\r
+\r
+/**\r
+ * @brief Resume Tick increment.\r
+ * @note Enable the tick increment by Enabling TIM6 update interrupt.\r
+ * @param None\r
+ * @retval None\r
+ */\r
+void HAL_ResumeTick(void)\r
+{\r
+ /* Enable TIM6 Update interrupt */\r
+ __HAL_TIM_ENABLE_IT(&htim6, TIM_IT_UPDATE);\r
+}\r
+\r
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\r
--- /dev/null
+/* USER CODE BEGIN Header */\r
+/**\r
+ ******************************************************************************\r
+ * @file stm32l1xx_it.c\r
+ * @brief Interrupt Service Routines.\r
+ ******************************************************************************\r
+ * @attention\r
+ *\r
+ * <h2><center>© Copyright (c) 2020 STMicroelectronics.\r
+ * All rights reserved.</center></h2>\r
+ *\r
+ * This software component is licensed by ST under BSD 3-Clause license,\r
+ * the "License"; You may not use this file except in compliance with the\r
+ * License. You may obtain a copy of the License at:\r
+ * opensource.org/licenses/BSD-3-Clause\r
+ *\r
+ ******************************************************************************\r
+ */\r
+/* USER CODE END Header */\r
+\r
+/* Includes ------------------------------------------------------------------*/\r
+#include "main.h"\r
+#include "stm32l1xx_it.h"\r
+/* Private includes ----------------------------------------------------------*/\r
+/* USER CODE BEGIN Includes */\r
+/* USER CODE END Includes */\r
+\r
+/* Private typedef -----------------------------------------------------------*/\r
+/* USER CODE BEGIN TD */\r
+\r
+/* USER CODE END TD */\r
+\r
+/* Private define ------------------------------------------------------------*/\r
+/* USER CODE BEGIN PD */\r
+ \r
+/* USER CODE END PD */\r
+\r
+/* Private macro -------------------------------------------------------------*/\r
+/* USER CODE BEGIN PM */\r
+\r
+/* USER CODE END PM */\r
+\r
+/* Private variables ---------------------------------------------------------*/\r
+/* USER CODE BEGIN PV */\r
+\r
+/* USER CODE END PV */\r
+\r
+/* Private function prototypes -----------------------------------------------*/\r
+/* USER CODE BEGIN PFP */\r
+\r
+/* USER CODE END PFP */\r
+\r
+/* Private user code ---------------------------------------------------------*/\r
+/* USER CODE BEGIN 0 */\r
+\r
+/* USER CODE END 0 */\r
+\r
+/* External variables --------------------------------------------------------*/\r
+extern TIM_HandleTypeDef htim6;\r
+\r
+/* USER CODE BEGIN EV */\r
+\r
+/* USER CODE END EV */\r
+\r
+/******************************************************************************/\r
+/* Cortex-M3 Processor Interruption and Exception Handlers */ \r
+/******************************************************************************/\r
+/**\r
+ * @brief This function handles Non maskable interrupt.\r
+ */\r
+void NMI_Handler(void)\r
+{\r
+ /* USER CODE BEGIN NonMaskableInt_IRQn 0 */\r
+\r
+ /* USER CODE END NonMaskableInt_IRQn 0 */\r
+ /* USER CODE BEGIN NonMaskableInt_IRQn 1 */\r
+\r
+ /* USER CODE END NonMaskableInt_IRQn 1 */\r
+}\r
+\r
+/**\r
+ * @brief This function handles Hard fault interrupt.\r
+ */\r
+void HardFault_Handler(void)\r
+{\r
+ /* USER CODE BEGIN HardFault_IRQn 0 */\r
+\r
+ /* USER CODE END HardFault_IRQn 0 */\r
+ while (1)\r
+ {\r
+ /* USER CODE BEGIN W1_HardFault_IRQn 0 */\r
+ /* USER CODE END W1_HardFault_IRQn 0 */\r
+ }\r
+}\r
+\r
+/**\r
+ * @brief This function handles Pre-fetch fault, memory access fault.\r
+ */\r
+void BusFault_Handler(void)\r
+{\r
+ /* USER CODE BEGIN BusFault_IRQn 0 */\r
+\r
+ /* USER CODE END BusFault_IRQn 0 */\r
+ while (1)\r
+ {\r
+ /* USER CODE BEGIN W1_BusFault_IRQn 0 */\r
+ /* USER CODE END W1_BusFault_IRQn 0 */\r
+ }\r
+}\r
+\r
+/**\r
+ * @brief This function handles Undefined instruction or illegal state.\r
+ */\r
+void UsageFault_Handler(void)\r
+{\r
+ /* USER CODE BEGIN UsageFault_IRQn 0 */\r
+\r
+ /* USER CODE END UsageFault_IRQn 0 */\r
+ while (1)\r
+ {\r
+ /* USER CODE BEGIN W1_UsageFault_IRQn 0 */\r
+ /* USER CODE END W1_UsageFault_IRQn 0 */\r
+ }\r
+}\r
+\r
+/**\r
+ * @brief This function handles Debug monitor.\r
+ */\r
+void DebugMon_Handler(void)\r
+{\r
+ /* USER CODE BEGIN DebugMonitor_IRQn 0 */\r
+\r
+ /* USER CODE END DebugMonitor_IRQn 0 */\r
+ /* USER CODE BEGIN DebugMonitor_IRQn 1 */\r
+\r
+ /* USER CODE END DebugMonitor_IRQn 1 */\r
+}\r
+\r
+/******************************************************************************/\r
+/* STM32L1xx Peripheral Interrupt Handlers */\r
+/* Add here the Interrupt Handlers for the used peripherals. */\r
+/* For the available peripheral interrupt handler names, */\r
+/* please refer to the startup file (startup_stm32l1xx.s). */\r
+/******************************************************************************/\r
+\r
+/**\r
+ * @brief This function handles TIM6 global interrupt.\r
+ */\r
+void TIM6_IRQHandler(void)\r
+{\r
+ /* USER CODE BEGIN TIM6_IRQn 0 */\r
+\r
+ /* USER CODE END TIM6_IRQn 0 */\r
+ HAL_TIM_IRQHandler(&htim6);\r
+ /* USER CODE BEGIN TIM6_IRQn 1 */\r
+\r
+ /* USER CODE END TIM6_IRQn 1 */\r
+}\r
+\r
+/* USER CODE BEGIN 1 */\r
+\r
+/* USER CODE END 1 */\r
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\r
--- /dev/null
+/**\r
+ ******************************************************************************\r
+ * @file system_stm32l1xx.c\r
+ * @author MCD Application Team\r
+ * @brief CMSIS Cortex-M3 Device Peripheral Access Layer System Source File.\r
+ * \r
+ * This file provides two functions and one global variable to be called from \r
+ * user application:\r
+ * - SystemInit(): This function is called at startup just after reset and \r
+ * before branch to main program. This call is made inside\r
+ * the "startup_stm32l1xx.s" file.\r
+ * \r
+ * - SystemCoreClock variable: Contains the core clock (HCLK), it can be used\r
+ * by the user application to setup the SysTick \r
+ * timer or configure other parameters.\r
+ * \r
+ * - SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must\r
+ * be called whenever the core clock is changed\r
+ * during program execution. \r
+ * \r
+ ******************************************************************************\r
+ * @attention\r
+ *\r
+ * <h2><center>© Copyright (c) 2017 STMicroelectronics.\r
+ * All rights reserved.</center></h2>\r
+ *\r
+ * This software component is licensed by ST under BSD 3-Clause license,\r
+ * the "License"; You may not use this file except in compliance with the\r
+ * License. You may obtain a copy of the License at:\r
+ * opensource.org/licenses/BSD-3-Clause\r
+ *\r
+ ******************************************************************************\r
+ */\r
+\r
+/** @addtogroup CMSIS\r
+ * @{\r
+ */\r
+\r
+/** @addtogroup stm32l1xx_system\r
+ * @{\r
+ */ \r
+ \r
+/** @addtogroup STM32L1xx_System_Private_Includes\r
+ * @{\r
+ */\r
+\r
+#include "stm32l1xx.h"\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @addtogroup STM32L1xx_System_Private_TypesDefinitions\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @addtogroup STM32L1xx_System_Private_Defines\r
+ * @{\r
+ */\r
+#if !defined (HSE_VALUE) \r
+ #define HSE_VALUE ((uint32_t)8000000U) /*!< Default value of the External oscillator in Hz.\r
+ This value can be provided and adapted by the user application. */\r
+#endif /* HSE_VALUE */\r
+\r
+#if !defined (HSI_VALUE)\r
+ #define HSI_VALUE ((uint32_t)8000000U) /*!< Default value of the Internal oscillator in Hz.\r
+ This value can be provided and adapted by the user application. */\r
+#endif /* HSI_VALUE */\r
+\r
+/*!< Uncomment the following line if you need to use external SRAM mounted\r
+ on STM32L152D_EVAL board as data memory */\r
+/* #define DATA_IN_ExtSRAM */\r
+ \r
+/*!< Uncomment the following line if you need to relocate your vector Table in\r
+ Internal SRAM. */ \r
+/* #define VECT_TAB_SRAM */\r
+#define VECT_TAB_OFFSET 0x00U /*!< Vector Table base offset field. \r
+ This value must be a multiple of 0x200. */\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @addtogroup STM32L1xx_System_Private_Macros\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @addtogroup STM32L1xx_System_Private_Variables\r
+ * @{\r
+ */\r
+ /* This variable is updated in three ways:\r
+ 1) by calling CMSIS function SystemCoreClockUpdate()\r
+ 2) by calling HAL API function HAL_RCC_GetHCLKFreq()\r
+ 3) each time HAL_RCC_ClockConfig() is called to configure the system clock frequency\r
+ Note: If you use this function to configure the system clock; then there\r
+ is no need to call the 2 first functions listed above, since SystemCoreClock\r
+ variable is updated automatically.\r
+ */\r
+uint32_t SystemCoreClock = 2097000U;\r
+const uint8_t PLLMulTable[9] = {3U, 4U, 6U, 8U, 12U, 16U, 24U, 32U, 48U};\r
+const uint8_t AHBPrescTable[16] = {0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 1U, 2U, 3U, 4U, 6U, 7U, 8U, 9U};\r
+const uint8_t APBPrescTable[8] = {0U, 0U, 0U, 0U, 1U, 2U, 3U, 4U};\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @addtogroup STM32L1xx_System_Private_FunctionPrototypes\r
+ * @{\r
+ */\r
+\r
+#if defined (STM32L151xD) || defined (STM32L152xD) || defined (STM32L162xD)\r
+#ifdef DATA_IN_ExtSRAM\r
+ static void SystemInit_ExtMemCtl(void); \r
+#endif /* DATA_IN_ExtSRAM */\r
+#endif /* STM32L151xD || STM32L152xD || STM32L162xD */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @addtogroup STM32L1xx_System_Private_Functions\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @brief Setup the microcontroller system.\r
+ * Initialize the Embedded Flash Interface, the PLL and update the \r
+ * SystemCoreClock variable.\r
+ * @param None\r
+ * @retval None\r
+ */\r
+void SystemInit (void)\r
+{\r
+ /*!< Set MSION bit */\r
+ RCC->CR |= (uint32_t)0x00000100;\r
+\r
+ /*!< Reset SW[1:0], HPRE[3:0], PPRE1[2:0], PPRE2[2:0], MCOSEL[2:0] and MCOPRE[2:0] bits */\r
+ RCC->CFGR &= (uint32_t)0x88FFC00C;\r
+ \r
+ /*!< Reset HSION, HSEON, CSSON and PLLON bits */\r
+ RCC->CR &= (uint32_t)0xEEFEFFFE;\r
+\r
+ /*!< Reset HSEBYP bit */\r
+ RCC->CR &= (uint32_t)0xFFFBFFFF;\r
+\r
+ /*!< Reset PLLSRC, PLLMUL[3:0] and PLLDIV[1:0] bits */\r
+ RCC->CFGR &= (uint32_t)0xFF02FFFF;\r
+\r
+ /*!< Disable all interrupts */\r
+ RCC->CIR = 0x00000000;\r
+\r
+#ifdef DATA_IN_ExtSRAM\r
+ SystemInit_ExtMemCtl(); \r
+#endif /* DATA_IN_ExtSRAM */\r
+ \r
+#ifdef VECT_TAB_SRAM\r
+ SCB->VTOR = SRAM_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM. */\r
+#else\r
+ SCB->VTOR = FLASH_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal FLASH. */\r
+#endif\r
+}\r
+\r
+/**\r
+ * @brief Update SystemCoreClock according to Clock Register Values\r
+ * The SystemCoreClock variable contains the core clock (HCLK), it can\r
+ * be used by the user application to setup the SysTick timer or configure\r
+ * other parameters.\r
+ * \r
+ * @note Each time the core clock (HCLK) changes, this function must be called\r
+ * to update SystemCoreClock variable value. Otherwise, any configuration\r
+ * based on this variable will be incorrect. \r
+ * \r
+ * @note - The system frequency computed by this function is not the real \r
+ * frequency in the chip. It is calculated based on the predefined \r
+ * constant and the selected clock source:\r
+ * \r
+ * - If SYSCLK source is MSI, SystemCoreClock will contain the MSI \r
+ * value as defined by the MSI range.\r
+ * \r
+ * - If SYSCLK source is HSI, SystemCoreClock will contain the HSI_VALUE(*)\r
+ * \r
+ * - If SYSCLK source is HSE, SystemCoreClock will contain the HSE_VALUE(**)\r
+ * \r
+ * - If SYSCLK source is PLL, SystemCoreClock will contain the HSE_VALUE(**)\r
+ * or HSI_VALUE(*) multiplied/divided by the PLL factors.\r
+ * \r
+ * (*) HSI_VALUE is a constant defined in stm32l1xx.h file (default value\r
+ * 16 MHz) but the real value may vary depending on the variations\r
+ * in voltage and temperature. \r
+ * \r
+ * (**) HSE_VALUE is a constant defined in stm32l1xx.h file (default value\r
+ * 8 MHz), user has to ensure that HSE_VALUE is same as the real\r
+ * frequency of the crystal used. Otherwise, this function may\r
+ * have wrong result.\r
+ * \r
+ * - The result of this function could be not correct when using fractional\r
+ * value for HSE crystal.\r
+ * @param None\r
+ * @retval None\r
+ */\r
+void SystemCoreClockUpdate (void)\r
+{\r
+ uint32_t tmp = 0, pllmul = 0, plldiv = 0, pllsource = 0, msirange = 0;\r
+\r
+ /* Get SYSCLK source -------------------------------------------------------*/\r
+ tmp = RCC->CFGR & RCC_CFGR_SWS;\r
+ \r
+ switch (tmp)\r
+ {\r
+ case 0x00: /* MSI used as system clock */\r
+ msirange = (RCC->ICSCR & RCC_ICSCR_MSIRANGE) >> 13;\r
+ SystemCoreClock = (32768 * (1 << (msirange + 1)));\r
+ break;\r
+ case 0x04: /* HSI used as system clock */\r
+ SystemCoreClock = HSI_VALUE;\r
+ break;\r
+ case 0x08: /* HSE used as system clock */\r
+ SystemCoreClock = HSE_VALUE;\r
+ break;\r
+ case 0x0C: /* PLL used as system clock */\r
+ /* Get PLL clock source and multiplication factor ----------------------*/\r
+ pllmul = RCC->CFGR & RCC_CFGR_PLLMUL;\r
+ plldiv = RCC->CFGR & RCC_CFGR_PLLDIV;\r
+ pllmul = PLLMulTable[(pllmul >> 18)];\r
+ plldiv = (plldiv >> 22) + 1;\r
+ \r
+ pllsource = RCC->CFGR & RCC_CFGR_PLLSRC;\r
+\r
+ if (pllsource == 0x00)\r
+ {\r
+ /* HSI oscillator clock selected as PLL clock entry */\r
+ SystemCoreClock = (((HSI_VALUE) * pllmul) / plldiv);\r
+ }\r
+ else\r
+ {\r
+ /* HSE selected as PLL clock entry */\r
+ SystemCoreClock = (((HSE_VALUE) * pllmul) / plldiv);\r
+ }\r
+ break;\r
+ default: /* MSI used as system clock */\r
+ msirange = (RCC->ICSCR & RCC_ICSCR_MSIRANGE) >> 13;\r
+ SystemCoreClock = (32768 * (1 << (msirange + 1)));\r
+ break;\r
+ }\r
+ /* Compute HCLK clock frequency --------------------------------------------*/\r
+ /* Get HCLK prescaler */\r
+ tmp = AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> 4)];\r
+ /* HCLK clock frequency */\r
+ SystemCoreClock >>= tmp;\r
+}\r
+\r
+#if defined (STM32L151xD) || defined (STM32L152xD) || defined (STM32L162xD)\r
+#ifdef DATA_IN_ExtSRAM\r
+/**\r
+ * @brief Setup the external memory controller.\r
+ * Called in SystemInit() function before jump to main.\r
+ * This function configures the external SRAM mounted on STM32L152D_EVAL board\r
+ * This SRAM will be used as program data memory (including heap and stack).\r
+ * @param None\r
+ * @retval None\r
+ */\r
+void SystemInit_ExtMemCtl(void)\r
+{\r
+ __IO uint32_t tmpreg = 0;\r
+\r
+ /* Flash 1 wait state */\r
+ FLASH->ACR |= FLASH_ACR_LATENCY;\r
+ \r
+ /* Power enable */\r
+ RCC->APB1ENR |= RCC_APB1ENR_PWREN;\r
+ \r
+ /* Delay after an RCC peripheral clock enabling */\r
+ tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_PWREN);\r
+\r
+ /* Select the Voltage Range 1 (1.8 V) */\r
+ PWR->CR = PWR_CR_VOS_0;\r
+ \r
+ /* Wait Until the Voltage Regulator is ready */\r
+ while((PWR->CSR & PWR_CSR_VOSF) != RESET)\r
+ {\r
+ }\r
+ \r
+/*-- GPIOs Configuration -----------------------------------------------------*/\r
+/*\r
+ +-------------------+--------------------+------------------+------------------+\r
+ + SRAM pins assignment +\r
+ +-------------------+--------------------+------------------+------------------+\r
+ | PD0 <-> FSMC_D2 | PE0 <-> FSMC_NBL0 | PF0 <-> FSMC_A0 | PG0 <-> FSMC_A10 |\r
+ | PD1 <-> FSMC_D3 | PE1 <-> FSMC_NBL1 | PF1 <-> FSMC_A1 | PG1 <-> FSMC_A11 |\r
+ | PD4 <-> FSMC_NOE | PE7 <-> FSMC_D4 | PF2 <-> FSMC_A2 | PG2 <-> FSMC_A12 |\r
+ | PD5 <-> FSMC_NWE | PE8 <-> FSMC_D5 | PF3 <-> FSMC_A3 | PG3 <-> FSMC_A13 |\r
+ | PD8 <-> FSMC_D13 | PE9 <-> FSMC_D6 | PF4 <-> FSMC_A4 | PG4 <-> FSMC_A14 |\r
+ | PD9 <-> FSMC_D14 | PE10 <-> FSMC_D7 | PF5 <-> FSMC_A5 | PG5 <-> FSMC_A15 |\r
+ | PD10 <-> FSMC_D15 | PE11 <-> FSMC_D8 | PF12 <-> FSMC_A6 | PG10<-> FSMC_NE2 |\r
+ | PD11 <-> FSMC_A16 | PE12 <-> FSMC_D9 | PF13 <-> FSMC_A7 |------------------+\r
+ | PD12 <-> FSMC_A17 | PE13 <-> FSMC_D10 | PF14 <-> FSMC_A8 | \r
+ | PD13 <-> FSMC_A18 | PE14 <-> FSMC_D11 | PF15 <-> FSMC_A9 | \r
+ | PD14 <-> FSMC_D0 | PE15 <-> FSMC_D12 |------------------+\r
+ | PD15 <-> FSMC_D1 |--------------------+ \r
+ +-------------------+\r
+*/\r
+\r
+ /* Enable GPIOD, GPIOE, GPIOF and GPIOG interface clock */\r
+ RCC->AHBENR = 0x000080D8;\r
+ \r
+ /* Delay after an RCC peripheral clock enabling */\r
+ tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_GPIODEN);\r
+ \r
+ /* Connect PDx pins to FSMC Alternate function */\r
+ GPIOD->AFR[0] = 0x00CC00CC;\r
+ GPIOD->AFR[1] = 0xCCCCCCCC;\r
+ /* Configure PDx pins in Alternate function mode */ \r
+ GPIOD->MODER = 0xAAAA0A0A;\r
+ /* Configure PDx pins speed to 40 MHz */ \r
+ GPIOD->OSPEEDR = 0xFFFF0F0F;\r
+ /* Configure PDx pins Output type to push-pull */ \r
+ GPIOD->OTYPER = 0x00000000;\r
+ /* No pull-up, pull-down for PDx pins */ \r
+ GPIOD->PUPDR = 0x00000000;\r
+\r
+ /* Connect PEx pins to FSMC Alternate function */\r
+ GPIOE->AFR[0] = 0xC00000CC;\r
+ GPIOE->AFR[1] = 0xCCCCCCCC;\r
+ /* Configure PEx pins in Alternate function mode */ \r
+ GPIOE->MODER = 0xAAAA800A;\r
+ /* Configure PEx pins speed to 40 MHz */ \r
+ GPIOE->OSPEEDR = 0xFFFFC00F;\r
+ /* Configure PEx pins Output type to push-pull */ \r
+ GPIOE->OTYPER = 0x00000000;\r
+ /* No pull-up, pull-down for PEx pins */ \r
+ GPIOE->PUPDR = 0x00000000;\r
+\r
+ /* Connect PFx pins to FSMC Alternate function */\r
+ GPIOF->AFR[0] = 0x00CCCCCC;\r
+ GPIOF->AFR[1] = 0xCCCC0000;\r
+ /* Configure PFx pins in Alternate function mode */ \r
+ GPIOF->MODER = 0xAA000AAA;\r
+ /* Configure PFx pins speed to 40 MHz */ \r
+ GPIOF->OSPEEDR = 0xFF000FFF;\r
+ /* Configure PFx pins Output type to push-pull */ \r
+ GPIOF->OTYPER = 0x00000000;\r
+ /* No pull-up, pull-down for PFx pins */ \r
+ GPIOF->PUPDR = 0x00000000;\r
+\r
+ /* Connect PGx pins to FSMC Alternate function */\r
+ GPIOG->AFR[0] = 0x00CCCCCC;\r
+ GPIOG->AFR[1] = 0x00000C00;\r
+ /* Configure PGx pins in Alternate function mode */ \r
+ GPIOG->MODER = 0x00200AAA;\r
+ /* Configure PGx pins speed to 40 MHz */ \r
+ GPIOG->OSPEEDR = 0x00300FFF;\r
+ /* Configure PGx pins Output type to push-pull */ \r
+ GPIOG->OTYPER = 0x00000000;\r
+ /* No pull-up, pull-down for PGx pins */ \r
+ GPIOG->PUPDR = 0x00000000;\r
+ \r
+/*-- FSMC Configuration ------------------------------------------------------*/\r
+ /* Enable the FSMC interface clock */\r
+ RCC->AHBENR = 0x400080D8;\r
+\r
+ /* Delay after an RCC peripheral clock enabling */\r
+ tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_FSMCEN);\r
+ \r
+ (void)(tmpreg);\r
+ \r
+ /* Configure and enable Bank1_SRAM3 */\r
+ FSMC_Bank1->BTCR[4] = 0x00001011;\r
+ FSMC_Bank1->BTCR[5] = 0x00000300;\r
+ FSMC_Bank1E->BWTR[4] = 0x0FFFFFFF;\r
+/*\r
+ Bank1_SRAM3 is configured as follow:\r
+\r
+ p.FSMC_AddressSetupTime = 0;\r
+ p.FSMC_AddressHoldTime = 0;\r
+ p.FSMC_DataSetupTime = 3;\r
+ p.FSMC_BusTurnAroundDuration = 0;\r
+ p.FSMC_CLKDivision = 0;\r
+ p.FSMC_DataLatency = 0;\r
+ p.FSMC_AccessMode = FSMC_AccessMode_A;\r
+\r
+ FSMC_NORSRAMInitStructure.FSMC_Bank = FSMC_Bank1_NORSRAM3;\r
+ FSMC_NORSRAMInitStructure.FSMC_DataAddressMux = FSMC_DataAddressMux_Disable;\r
+ FSMC_NORSRAMInitStructure.FSMC_MemoryType = FSMC_MemoryType_SRAM;\r
+ FSMC_NORSRAMInitStructure.FSMC_MemoryDataWidth = FSMC_MemoryDataWidth_16b;\r
+ FSMC_NORSRAMInitStructure.FSMC_BurstAccessMode = FSMC_BurstAccessMode_Disable;\r
+ FSMC_NORSRAMInitStructure.FSMC_AsynchronousWait = FSMC_AsynchronousWait_Disable;\r
+ FSMC_NORSRAMInitStructure.FSMC_WaitSignalPolarity = FSMC_WaitSignalPolarity_Low;\r
+ FSMC_NORSRAMInitStructure.FSMC_WrapMode = FSMC_WrapMode_Disable;\r
+ FSMC_NORSRAMInitStructure.FSMC_WaitSignalActive = FSMC_WaitSignalActive_BeforeWaitState;\r
+ FSMC_NORSRAMInitStructure.FSMC_WriteOperation = FSMC_WriteOperation_Enable;\r
+ FSMC_NORSRAMInitStructure.FSMC_WaitSignal = FSMC_WaitSignal_Disable;\r
+ FSMC_NORSRAMInitStructure.FSMC_ExtendedMode = FSMC_ExtendedMode_Disable;\r
+ FSMC_NORSRAMInitStructure.FSMC_WriteBurst = FSMC_WriteBurst_Disable;\r
+ FSMC_NORSRAMInitStructure.FSMC_ReadWriteTimingStruct = &p;\r
+ FSMC_NORSRAMInitStructure.FSMC_WriteTimingStruct = &p;\r
+\r
+ FSMC_NORSRAMInit(&FSMC_NORSRAMInitStructure); \r
+\r
+ FSMC_NORSRAMCmd(FSMC_Bank1_NORSRAM3, ENABLE);\r
+*/\r
+ \r
+}\r
+#endif /* DATA_IN_ExtSRAM */\r
+#endif /* STM32L151xD || STM32L152xD || STM32L162xD */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\r
--- /dev/null
+/**\r
+ ******************************************************************************\r
+ * @file stm32l152xe.h\r
+ * @author MCD Application Team\r
+ * @brief CMSIS Cortex-M3 Device Peripheral Access Layer Header File. \r
+ * This file contains all the peripheral register's definitions, bits \r
+ * definitions and memory mapping for STM32L1xx devices. \r
+ * \r
+ * This file contains:\r
+ * - Data structures and the address mapping for all peripherals\r
+ * - Peripheral's registers declarations and bits definition\r
+ * - Macros to access peripheral\92s registers hardware\r
+ * \r
+ ******************************************************************************\r
+ * @attention\r
+ *\r
+ * <h2><center>© Copyright (c) 2017 STMicroelectronics.\r
+ * All rights reserved.</center></h2>\r
+ *\r
+ * This software component is licensed by ST under BSD 3-Clause license,\r
+ * the "License"; You may not use this file except in compliance with the\r
+ * License. You may obtain a copy of the License at:\r
+ * opensource.org/licenses/BSD-3-Clause\r
+ *\r
+ ******************************************************************************\r
+ */\r
+\r
+/** @addtogroup CMSIS\r
+ * @{\r
+ */\r
+\r
+/** @addtogroup stm32l152xe\r
+ * @{\r
+ */\r
+ \r
+#ifndef __STM32L152xE_H\r
+#define __STM32L152xE_H\r
+\r
+#ifdef __cplusplus\r
+ extern "C" {\r
+#endif \r
+ \r
+\r
+ /** @addtogroup Configuration_section_for_CMSIS\r
+ * @{\r
+ */\r
+/**\r
+ * @brief Configuration of the Cortex-M3 Processor and Core Peripherals \r
+ */\r
+#define __CM3_REV 0x200U /*!< Cortex-M3 Revision r2p0 */\r
+#define __MPU_PRESENT 1U /*!< STM32L1xx provides MPU */\r
+#define __NVIC_PRIO_BITS 4U /*!< STM32L1xx uses 4 Bits for the Priority Levels */\r
+#define __Vendor_SysTickConfig 0U /*!< Set to 1 if different SysTick Config is used */\r
+ \r
+/**\r
+ * @}\r
+ */\r
+ \r
+/** @addtogroup Peripheral_interrupt_number_definition\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @brief STM32L1xx Interrupt Number Definition, according to the selected device \r
+ * in @ref Library_configuration_section \r
+ */\r
+\r
+ /*!< Interrupt Number Definition */\r
+typedef enum\r
+{\r
+/****** Cortex-M3 Processor Exceptions Numbers ******************************************************/\r
+ NonMaskableInt_IRQn = -14, /*!< 2 Non Maskable Interrupt */\r
+ HardFault_IRQn = -13, /*!< 3 Cortex-M3 Hard Fault Interrupt */\r
+ MemoryManagement_IRQn = -12, /*!< 4 Cortex-M3 Memory Management Interrupt */\r
+ BusFault_IRQn = -11, /*!< 5 Cortex-M3 Bus Fault Interrupt */\r
+ UsageFault_IRQn = -10, /*!< 6 Cortex-M3 Usage Fault Interrupt */\r
+ SVC_IRQn = -5, /*!< 11 Cortex-M3 SV Call Interrupt */\r
+ DebugMonitor_IRQn = -4, /*!< 12 Cortex-M3 Debug Monitor Interrupt */\r
+ PendSV_IRQn = -2, /*!< 14 Cortex-M3 Pend SV Interrupt */\r
+ SysTick_IRQn = -1, /*!< 15 Cortex-M3 System Tick Interrupt */\r
+\r
+/****** STM32L specific Interrupt Numbers ***********************************************************/\r
+ WWDG_IRQn = 0, /*!< Window WatchDog Interrupt */\r
+ PVD_IRQn = 1, /*!< PVD through EXTI Line detection Interrupt */\r
+ TAMPER_STAMP_IRQn = 2, /*!< Tamper and TimeStamp interrupts through the EXTI line */\r
+ RTC_WKUP_IRQn = 3, /*!< RTC Wakeup Timer through EXTI Line Interrupt */\r
+ FLASH_IRQn = 4, /*!< FLASH global Interrupt */\r
+ RCC_IRQn = 5, /*!< RCC global Interrupt */\r
+ EXTI0_IRQn = 6, /*!< EXTI Line0 Interrupt */\r
+ EXTI1_IRQn = 7, /*!< EXTI Line1 Interrupt */\r
+ EXTI2_IRQn = 8, /*!< EXTI Line2 Interrupt */\r
+ EXTI3_IRQn = 9, /*!< EXTI Line3 Interrupt */\r
+ EXTI4_IRQn = 10, /*!< EXTI Line4 Interrupt */\r
+ DMA1_Channel1_IRQn = 11, /*!< DMA1 Channel 1 global Interrupt */\r
+ DMA1_Channel2_IRQn = 12, /*!< DMA1 Channel 2 global Interrupt */\r
+ DMA1_Channel3_IRQn = 13, /*!< DMA1 Channel 3 global Interrupt */\r
+ DMA1_Channel4_IRQn = 14, /*!< DMA1 Channel 4 global Interrupt */\r
+ DMA1_Channel5_IRQn = 15, /*!< DMA1 Channel 5 global Interrupt */\r
+ DMA1_Channel6_IRQn = 16, /*!< DMA1 Channel 6 global Interrupt */\r
+ DMA1_Channel7_IRQn = 17, /*!< DMA1 Channel 7 global Interrupt */\r
+ ADC1_IRQn = 18, /*!< ADC1 global Interrupt */\r
+ USB_HP_IRQn = 19, /*!< USB High Priority Interrupt */\r
+ USB_LP_IRQn = 20, /*!< USB Low Priority Interrupt */\r
+ DAC_IRQn = 21, /*!< DAC Interrupt */\r
+ COMP_IRQn = 22, /*!< Comparator through EXTI Line Interrupt */\r
+ EXTI9_5_IRQn = 23, /*!< External Line[9:5] Interrupts */\r
+ LCD_IRQn = 24, /*!< LCD Interrupt */\r
+ TIM9_IRQn = 25, /*!< TIM9 global Interrupt */\r
+ TIM10_IRQn = 26, /*!< TIM10 global Interrupt */\r
+ TIM11_IRQn = 27, /*!< TIM11 global Interrupt */\r
+ TIM2_IRQn = 28, /*!< TIM2 global Interrupt */\r
+ TIM3_IRQn = 29, /*!< TIM3 global Interrupt */\r
+ TIM4_IRQn = 30, /*!< TIM4 global Interrupt */\r
+ I2C1_EV_IRQn = 31, /*!< I2C1 Event Interrupt */\r
+ I2C1_ER_IRQn = 32, /*!< I2C1 Error Interrupt */\r
+ I2C2_EV_IRQn = 33, /*!< I2C2 Event Interrupt */\r
+ I2C2_ER_IRQn = 34, /*!< I2C2 Error Interrupt */\r
+ SPI1_IRQn = 35, /*!< SPI1 global Interrupt */\r
+ SPI2_IRQn = 36, /*!< SPI2 global Interrupt */\r
+ USART1_IRQn = 37, /*!< USART1 global Interrupt */\r
+ USART2_IRQn = 38, /*!< USART2 global Interrupt */\r
+ USART3_IRQn = 39, /*!< USART3 global Interrupt */\r
+ EXTI15_10_IRQn = 40, /*!< External Line[15:10] Interrupts */\r
+ RTC_Alarm_IRQn = 41, /*!< RTC Alarm through EXTI Line Interrupt */\r
+ USB_FS_WKUP_IRQn = 42, /*!< USB FS WakeUp from suspend through EXTI Line Interrupt */\r
+ TIM6_IRQn = 43, /*!< TIM6 global Interrupt */\r
+ TIM7_IRQn = 44, /*!< TIM7 global Interrupt */\r
+ TIM5_IRQn = 46, /*!< TIM5 global Interrupt */\r
+ SPI3_IRQn = 47, /*!< SPI3 global Interrupt */\r
+ UART4_IRQn = 48, /*!< UART4 global Interrupt */\r
+ UART5_IRQn = 49, /*!< UART5 global Interrupt */\r
+ DMA2_Channel1_IRQn = 50, /*!< DMA2 Channel 1 global Interrupt */\r
+ DMA2_Channel2_IRQn = 51, /*!< DMA2 Channel 2 global Interrupt */\r
+ DMA2_Channel3_IRQn = 52, /*!< DMA2 Channel 3 global Interrupt */\r
+ DMA2_Channel4_IRQn = 53, /*!< DMA2 Channel 4 global Interrupt */\r
+ DMA2_Channel5_IRQn = 54, /*!< DMA2 Channel 5 global Interrupt */\r
+ COMP_ACQ_IRQn = 56 /*!< Comparator Channel Acquisition global Interrupt */\r
+} IRQn_Type;\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+#include "core_cm3.h"\r
+#include "system_stm32l1xx.h"\r
+#include <stdint.h>\r
+\r
+/** @addtogroup Peripheral_registers_structures\r
+ * @{\r
+ */ \r
+\r
+/** \r
+ * @brief Analog to Digital Converter\r
+ */\r
+\r
+typedef struct\r
+{\r
+ __IO uint32_t SR; /*!< ADC status register, Address offset: 0x00 */\r
+ __IO uint32_t CR1; /*!< ADC control register 1, Address offset: 0x04 */\r
+ __IO uint32_t CR2; /*!< ADC control register 2, Address offset: 0x08 */\r
+ __IO uint32_t SMPR1; /*!< ADC sample time register 1, Address offset: 0x0C */\r
+ __IO uint32_t SMPR2; /*!< ADC sample time register 2, Address offset: 0x10 */\r
+ __IO uint32_t SMPR3; /*!< ADC sample time register 3, Address offset: 0x14 */\r
+ __IO uint32_t JOFR1; /*!< ADC injected channel data offset register 1, Address offset: 0x18 */\r
+ __IO uint32_t JOFR2; /*!< ADC injected channel data offset register 2, Address offset: 0x1C */\r
+ __IO uint32_t JOFR3; /*!< ADC injected channel data offset register 3, Address offset: 0x20 */\r
+ __IO uint32_t JOFR4; /*!< ADC injected channel data offset register 4, Address offset: 0x24 */\r
+ __IO uint32_t HTR; /*!< ADC watchdog higher threshold register, Address offset: 0x28 */\r
+ __IO uint32_t LTR; /*!< ADC watchdog lower threshold register, Address offset: 0x2C */\r
+ __IO uint32_t SQR1; /*!< ADC regular sequence register 1, Address offset: 0x30 */\r
+ __IO uint32_t SQR2; /*!< ADC regular sequence register 2, Address offset: 0x34 */\r
+ __IO uint32_t SQR3; /*!< ADC regular sequence register 3, Address offset: 0x38 */\r
+ __IO uint32_t SQR4; /*!< ADC regular sequence register 4, Address offset: 0x3C */\r
+ __IO uint32_t SQR5; /*!< ADC regular sequence register 5, Address offset: 0x40 */\r
+ __IO uint32_t JSQR; /*!< ADC injected sequence register, Address offset: 0x44 */\r
+ __IO uint32_t JDR1; /*!< ADC injected data register 1, Address offset: 0x48 */\r
+ __IO uint32_t JDR2; /*!< ADC injected data register 2, Address offset: 0x4C */\r
+ __IO uint32_t JDR3; /*!< ADC injected data register 3, Address offset: 0x50 */\r
+ __IO uint32_t JDR4; /*!< ADC injected data register 4, Address offset: 0x54 */\r
+ __IO uint32_t DR; /*!< ADC regular data register, Address offset: 0x58 */\r
+ __IO uint32_t SMPR0; /*!< ADC sample time register 0, Address offset: 0x5C */\r
+} ADC_TypeDef;\r
+\r
+typedef struct\r
+{\r
+ __IO uint32_t CSR; /*!< ADC common status register, Address offset: ADC1 base address + 0x300 */\r
+ __IO uint32_t CCR; /*!< ADC common control register, Address offset: ADC1 base address + 0x304 */\r
+} ADC_Common_TypeDef;\r
+\r
+/** \r
+ * @brief Comparator \r
+ */\r
+\r
+typedef struct\r
+{\r
+ __IO uint32_t CSR; /*!< COMP control and status register, Address offset: 0x00 */\r
+} COMP_TypeDef;\r
+\r
+typedef struct\r
+{\r
+ __IO uint32_t CSR; /*!< COMP control and status register, used for bits common to several COMP instances, Address offset: 0x00 */\r
+} COMP_Common_TypeDef;\r
+\r
+/** \r
+ * @brief CRC calculation unit\r
+ */\r
+\r
+typedef struct\r
+{\r
+ __IO uint32_t DR; /*!< CRC Data register, Address offset: 0x00 */\r
+ __IO uint8_t IDR; /*!< CRC Independent data register, Address offset: 0x04 */\r
+ uint8_t RESERVED0; /*!< Reserved, Address offset: 0x05 */\r
+ uint16_t RESERVED1; /*!< Reserved, Address offset: 0x06 */ \r
+ __IO uint32_t CR; /*!< CRC Control register, Address offset: 0x08 */ \r
+} CRC_TypeDef;\r
+\r
+/** \r
+ * @brief Digital to Analog Converter\r
+ */\r
+\r
+typedef struct\r
+{\r
+ __IO uint32_t CR; /*!< DAC control register, Address offset: 0x00 */\r
+ __IO uint32_t SWTRIGR; /*!< DAC software trigger register, Address offset: 0x04 */\r
+ __IO uint32_t DHR12R1; /*!< DAC channel1 12-bit right-aligned data holding register, Address offset: 0x08 */\r
+ __IO uint32_t DHR12L1; /*!< DAC channel1 12-bit left aligned data holding register, Address offset: 0x0C */\r
+ __IO uint32_t DHR8R1; /*!< DAC channel1 8-bit right aligned data holding register, Address offset: 0x10 */\r
+ __IO uint32_t DHR12R2; /*!< DAC channel2 12-bit right aligned data holding register, Address offset: 0x14 */\r
+ __IO uint32_t DHR12L2; /*!< DAC channel2 12-bit left aligned data holding register, Address offset: 0x18 */\r
+ __IO uint32_t DHR8R2; /*!< DAC channel2 8-bit right-aligned data holding register, Address offset: 0x1C */\r
+ __IO uint32_t DHR12RD; /*!< Dual DAC 12-bit right-aligned data holding register, Address offset: 0x20 */\r
+ __IO uint32_t DHR12LD; /*!< DUAL DAC 12-bit left aligned data holding register, Address offset: 0x24 */\r
+ __IO uint32_t DHR8RD; /*!< DUAL DAC 8-bit right aligned data holding register, Address offset: 0x28 */\r
+ __IO uint32_t DOR1; /*!< DAC channel1 data output register, Address offset: 0x2C */\r
+ __IO uint32_t DOR2; /*!< DAC channel2 data output register, Address offset: 0x30 */\r
+ __IO uint32_t SR; /*!< DAC status register, Address offset: 0x34 */\r
+} DAC_TypeDef;\r
+\r
+/** \r
+ * @brief Debug MCU\r
+ */\r
+\r
+typedef struct\r
+{\r
+ __IO uint32_t IDCODE; /*!< MCU device ID code, Address offset: 0x00 */\r
+ __IO uint32_t CR; /*!< Debug MCU configuration register, Address offset: 0x04 */\r
+ __IO uint32_t APB1FZ; /*!< Debug MCU APB1 freeze register, Address offset: 0x08 */\r
+ __IO uint32_t APB2FZ; /*!< Debug MCU APB2 freeze register, Address offset: 0x0C */\r
+}DBGMCU_TypeDef;\r
+\r
+/** \r
+ * @brief DMA Controller\r
+ */\r
+\r
+typedef struct\r
+{\r
+ __IO uint32_t CCR; /*!< DMA channel x configuration register */\r
+ __IO uint32_t CNDTR; /*!< DMA channel x number of data register */\r
+ __IO uint32_t CPAR; /*!< DMA channel x peripheral address register */\r
+ __IO uint32_t CMAR; /*!< DMA channel x memory address register */\r
+} DMA_Channel_TypeDef;\r
+\r
+typedef struct\r
+{\r
+ __IO uint32_t ISR; /*!< DMA interrupt status register, Address offset: 0x00 */\r
+ __IO uint32_t IFCR; /*!< DMA interrupt flag clear register, Address offset: 0x04 */\r
+} DMA_TypeDef;\r
+\r
+/** \r
+ * @brief External Interrupt/Event Controller\r
+ */\r
+\r
+typedef struct\r
+{\r
+ __IO uint32_t IMR; /*!<EXTI Interrupt mask register, Address offset: 0x00 */\r
+ __IO uint32_t EMR; /*!<EXTI Event mask register, Address offset: 0x04 */\r
+ __IO uint32_t RTSR; /*!<EXTI Rising trigger selection register , Address offset: 0x08 */\r
+ __IO uint32_t FTSR; /*!<EXTI Falling trigger selection register, Address offset: 0x0C */\r
+ __IO uint32_t SWIER; /*!<EXTI Software interrupt event register, Address offset: 0x10 */\r
+ __IO uint32_t PR; /*!<EXTI Pending register, Address offset: 0x14 */\r
+} EXTI_TypeDef;\r
+\r
+/** \r
+ * @brief FLASH Registers\r
+ */\r
+typedef struct\r
+{\r
+ __IO uint32_t ACR; /*!< Access control register, Address offset: 0x00 */\r
+ __IO uint32_t PECR; /*!< Program/erase control register, Address offset: 0x04 */\r
+ __IO uint32_t PDKEYR; /*!< Power down key register, Address offset: 0x08 */\r
+ __IO uint32_t PEKEYR; /*!< Program/erase key register, Address offset: 0x0c */\r
+ __IO uint32_t PRGKEYR; /*!< Program memory key register, Address offset: 0x10 */\r
+ __IO uint32_t OPTKEYR; /*!< Option byte key register, Address offset: 0x14 */\r
+ __IO uint32_t SR; /*!< Status register, Address offset: 0x18 */\r
+ __IO uint32_t OBR; /*!< Option byte register, Address offset: 0x1c */\r
+ __IO uint32_t WRPR1; /*!< Write protection register 1, Address offset: 0x20 */\r
+ uint32_t RESERVED[23]; /*!< Reserved, Address offset: 0x24 */\r
+ __IO uint32_t WRPR2; /*!< Write protection register 2, Address offset: 0x80 */\r
+ __IO uint32_t WRPR3; /*!< Write protection register 3, Address offset: 0x84 */\r
+ __IO uint32_t WRPR4; /*!< Write protection register 4, Address offset: 0x88 */\r
+} FLASH_TypeDef;\r
+\r
+/** \r
+ * @brief Option Bytes Registers\r
+ */\r
+typedef struct\r
+{\r
+ __IO uint32_t RDP; /*!< Read protection register, Address offset: 0x00 */\r
+ __IO uint32_t USER; /*!< user register, Address offset: 0x04 */\r
+ __IO uint32_t WRP01; /*!< write protection register 0 1, Address offset: 0x08 */\r
+ __IO uint32_t WRP23; /*!< write protection register 2 3, Address offset: 0x0C */\r
+ __IO uint32_t WRP45; /*!< write protection register 4 5, Address offset: 0x10 */\r
+ __IO uint32_t WRP67; /*!< write protection register 6 7, Address offset: 0x14 */\r
+ __IO uint32_t WRP89; /*!< write protection register 8 9, Address offset: 0x18 */\r
+ __IO uint32_t WRP1011; /*!< write protection register 10 11, Address offset: 0x1C */\r
+ uint32_t RESERVED[24]; /*!< Reserved, 0x20 -> 0x7C */\r
+ __IO uint32_t WRP1213; /*!< write protection register 12 13, Address offset: 0x80 */\r
+ __IO uint32_t WRP1415; /*!< write protection register 14 15, Address offset: 0x84 */\r
+} OB_TypeDef;\r
+\r
+/** \r
+ * @brief Operational Amplifier (OPAMP)\r
+ */\r
+typedef struct\r
+{\r
+ __IO uint32_t CSR; /*!< OPAMP control and status register, Address offset: 0x00 */\r
+ __IO uint32_t OTR; /*!< OPAMP offset trimming register for normal mode, Address offset: 0x04 */ \r
+ __IO uint32_t LPOTR; /*!< OPAMP offset trimming register for low power mode, Address offset: 0x08 */\r
+} OPAMP_TypeDef;\r
+\r
+typedef struct\r
+{\r
+ __IO uint32_t CSR; /*!< OPAMP control and status register, used for bits common to several OPAMP instances, Address offset: 0x00 */\r
+ __IO uint32_t OTR; /*!< OPAMP offset trimming register for normal mode, used for bits common to several OPAMP instances, Address offset: 0x04 */ \r
+} OPAMP_Common_TypeDef;\r
+\r
+/** \r
+ * @brief General Purpose IO\r
+ */\r
+\r
+typedef struct\r
+{\r
+ __IO uint32_t MODER; /*!< GPIO port mode register, Address offset: 0x00 */\r
+ __IO uint32_t OTYPER; /*!< GPIO port output type register, Address offset: 0x04 */\r
+ __IO uint32_t OSPEEDR; /*!< GPIO port output speed register, Address offset: 0x08 */\r
+ __IO uint32_t PUPDR; /*!< GPIO port pull-up/pull-down register, Address offset: 0x0C */\r
+ __IO uint32_t IDR; /*!< GPIO port input data register, Address offset: 0x10 */\r
+ __IO uint32_t ODR; /*!< GPIO port output data register, Address offset: 0x14 */\r
+ __IO uint32_t BSRR; /*!< GPIO port bit set/reset registerBSRR, Address offset: 0x18 */\r
+ __IO uint32_t LCKR; /*!< GPIO port configuration lock register, Address offset: 0x1C */\r
+ __IO uint32_t AFR[2]; /*!< GPIO alternate function register, Address offset: 0x20-0x24 */\r
+ __IO uint32_t BRR; /*!< GPIO bit reset register, Address offset: 0x28 */\r
+} GPIO_TypeDef;\r
+\r
+/** \r
+ * @brief SysTem Configuration\r
+ */\r
+\r
+typedef struct\r
+{\r
+ __IO uint32_t MEMRMP; /*!< SYSCFG memory remap register, Address offset: 0x00 */\r
+ __IO uint32_t PMC; /*!< SYSCFG peripheral mode configuration register, Address offset: 0x04 */\r
+ __IO uint32_t EXTICR[4]; /*!< SYSCFG external interrupt configuration registers, Address offset: 0x08-0x14 */\r
+} SYSCFG_TypeDef;\r
+\r
+/** \r
+ * @brief Inter-integrated Circuit Interface\r
+ */\r
+\r
+typedef struct\r
+{\r
+ __IO uint32_t CR1; /*!< I2C Control register 1, Address offset: 0x00 */\r
+ __IO uint32_t CR2; /*!< I2C Control register 2, Address offset: 0x04 */\r
+ __IO uint32_t OAR1; /*!< I2C Own address register 1, Address offset: 0x08 */\r
+ __IO uint32_t OAR2; /*!< I2C Own address register 2, Address offset: 0x0C */\r
+ __IO uint32_t DR; /*!< I2C Data register, Address offset: 0x10 */\r
+ __IO uint32_t SR1; /*!< I2C Status register 1, Address offset: 0x14 */\r
+ __IO uint32_t SR2; /*!< I2C Status register 2, Address offset: 0x18 */\r
+ __IO uint32_t CCR; /*!< I2C Clock control register, Address offset: 0x1C */\r
+ __IO uint32_t TRISE; /*!< I2C TRISE register, Address offset: 0x20 */\r
+} I2C_TypeDef;\r
+\r
+/** \r
+ * @brief Independent WATCHDOG\r
+ */\r
+\r
+typedef struct\r
+{\r
+ __IO uint32_t KR; /*!< Key register, Address offset: 0x00 */\r
+ __IO uint32_t PR; /*!< Prescaler register, Address offset: 0x04 */\r
+ __IO uint32_t RLR; /*!< Reload register, Address offset: 0x08 */\r
+ __IO uint32_t SR; /*!< Status register, Address offset: 0x0C */\r
+} IWDG_TypeDef;\r
+\r
+/** \r
+ * @brief LCD\r
+ */\r
+\r
+typedef struct\r
+{\r
+ __IO uint32_t CR; /*!< LCD control register, Address offset: 0x00 */\r
+ __IO uint32_t FCR; /*!< LCD frame control register, Address offset: 0x04 */\r
+ __IO uint32_t SR; /*!< LCD status register, Address offset: 0x08 */\r
+ __IO uint32_t CLR; /*!< LCD clear register, Address offset: 0x0C */\r
+ uint32_t RESERVED; /*!< Reserved, Address offset: 0x10 */\r
+ __IO uint32_t RAM[16]; /*!< LCD display memory, Address offset: 0x14-0x50 */\r
+} LCD_TypeDef;\r
+\r
+/** \r
+ * @brief Power Control\r
+ */\r
+\r
+typedef struct\r
+{\r
+ __IO uint32_t CR; /*!< PWR power control register, Address offset: 0x00 */\r
+ __IO uint32_t CSR; /*!< PWR power control/status register, Address offset: 0x04 */\r
+} PWR_TypeDef;\r
+\r
+/** \r
+ * @brief Reset and Clock Control\r
+ */\r
+\r
+typedef struct\r
+{\r
+ __IO uint32_t CR; /*!< RCC clock control register, Address offset: 0x00 */\r
+ __IO uint32_t ICSCR; /*!< RCC Internal clock sources calibration register, Address offset: 0x04 */\r
+ __IO uint32_t CFGR; /*!< RCC Clock configuration register, Address offset: 0x08 */\r
+ __IO uint32_t CIR; /*!< RCC Clock interrupt register, Address offset: 0x0C */\r
+ __IO uint32_t AHBRSTR; /*!< RCC AHB peripheral reset register, Address offset: 0x10 */\r
+ __IO uint32_t APB2RSTR; /*!< RCC APB2 peripheral reset register, Address offset: 0x14 */\r
+ __IO uint32_t APB1RSTR; /*!< RCC APB1 peripheral reset register, Address offset: 0x18 */\r
+ __IO uint32_t AHBENR; /*!< RCC AHB peripheral clock enable register, Address offset: 0x1C */\r
+ __IO uint32_t APB2ENR; /*!< RCC APB2 peripheral clock enable register, Address offset: 0x20 */\r
+ __IO uint32_t APB1ENR; /*!< RCC APB1 peripheral clock enable register, Address offset: 0x24 */\r
+ __IO uint32_t AHBLPENR; /*!< RCC AHB peripheral clock enable in low power mode register, Address offset: 0x28 */\r
+ __IO uint32_t APB2LPENR; /*!< RCC APB2 peripheral clock enable in low power mode register, Address offset: 0x2C */\r
+ __IO uint32_t APB1LPENR; /*!< RCC APB1 peripheral clock enable in low power mode register, Address offset: 0x30 */\r
+ __IO uint32_t CSR; /*!< RCC Control/status register, Address offset: 0x34 */\r
+} RCC_TypeDef;\r
+\r
+/** \r
+ * @brief Routing Interface \r
+ */\r
+\r
+typedef struct\r
+{\r
+ __IO uint32_t ICR; /*!< RI input capture register, Address offset: 0x00 */\r
+ __IO uint32_t ASCR1; /*!< RI analog switches control register, Address offset: 0x04 */\r
+ __IO uint32_t ASCR2; /*!< RI analog switch control register 2, Address offset: 0x08 */\r
+ __IO uint32_t HYSCR1; /*!< RI hysteresis control register, Address offset: 0x0C */\r
+ __IO uint32_t HYSCR2; /*!< RI Hysteresis control register, Address offset: 0x10 */\r
+ __IO uint32_t HYSCR3; /*!< RI Hysteresis control register, Address offset: 0x14 */\r
+ __IO uint32_t HYSCR4; /*!< RI Hysteresis control register, Address offset: 0x18 */\r
+ __IO uint32_t ASMR1; /*!< RI Analog switch mode register 1, Address offset: 0x1C */\r
+ __IO uint32_t CMR1; /*!< RI Channel mask register 1, Address offset: 0x20 */\r
+ __IO uint32_t CICR1; /*!< RI Channel Iden for capture register 1, Address offset: 0x24 */\r
+ __IO uint32_t ASMR2; /*!< RI Analog switch mode register 2, Address offset: 0x28 */\r
+ __IO uint32_t CMR2; /*!< RI Channel mask register 2, Address offset: 0x2C */\r
+ __IO uint32_t CICR2; /*!< RI Channel Iden for capture register 2, Address offset: 0x30 */\r
+ __IO uint32_t ASMR3; /*!< RI Analog switch mode register 3, Address offset: 0x34 */\r
+ __IO uint32_t CMR3; /*!< RI Channel mask register 3, Address offset: 0x38 */\r
+ __IO uint32_t CICR3; /*!< RI Channel Iden for capture register 3, Address offset: 0x3C */\r
+ __IO uint32_t ASMR4; /*!< RI Analog switch mode register 4, Address offset: 0x40 */\r
+ __IO uint32_t CMR4; /*!< RI Channel mask register 4, Address offset: 0x44 */\r
+ __IO uint32_t CICR4; /*!< RI Channel Iden for capture register 4, Address offset: 0x48 */\r
+ __IO uint32_t ASMR5; /*!< RI Analog switch mode register 5, Address offset: 0x4C */\r
+ __IO uint32_t CMR5; /*!< RI Channel mask register 5, Address offset: 0x50 */\r
+ __IO uint32_t CICR5; /*!< RI Channel Iden for capture register 5, Address offset: 0x54 */\r
+} RI_TypeDef;\r
+\r
+/** \r
+ * @brief Real-Time Clock\r
+ */\r
+typedef struct\r
+{\r
+ __IO uint32_t TR; /*!< RTC time register, Address offset: 0x00 */\r
+ __IO uint32_t DR; /*!< RTC date register, Address offset: 0x04 */\r
+ __IO uint32_t CR; /*!< RTC control register, Address offset: 0x08 */ \r
+ __IO uint32_t ISR; /*!< RTC initialization and status register, Address offset: 0x0C */\r
+ __IO uint32_t PRER; /*!< RTC prescaler register, Address offset: 0x10 */\r
+ __IO uint32_t WUTR; /*!< RTC wakeup timer register, Address offset: 0x14 */\r
+ __IO uint32_t CALIBR; /*!< RTC calibration register, Address offset: 0x18 */\r
+ __IO uint32_t ALRMAR; /*!< RTC alarm A register, Address offset: 0x1C */\r
+ __IO uint32_t ALRMBR; /*!< RTC alarm B register, Address offset: 0x20 */\r
+ __IO uint32_t WPR; /*!< RTC write protection register, Address offset: 0x24 */\r
+ __IO uint32_t SSR; /*!< RTC sub second register, Address offset: 0x28 */\r
+ __IO uint32_t SHIFTR; /*!< RTC shift control register, Address offset: 0x2C */\r
+ __IO uint32_t TSTR; /*!< RTC time stamp time register, Address offset: 0x30 */\r
+ __IO uint32_t TSDR; /*!< RTC time stamp date register, Address offset: 0x34 */\r
+ __IO uint32_t TSSSR; /*!< RTC time-stamp sub second register, Address offset: 0x38 */\r
+ __IO uint32_t CALR; /*!< RRTC calibration register, Address offset: 0x3C */\r
+ __IO uint32_t TAFCR; /*!< RTC tamper and alternate function configuration register, Address offset: 0x40 */\r
+ __IO uint32_t ALRMASSR; /*!< RTC alarm A sub second register, Address offset: 0x44 */\r
+ __IO uint32_t ALRMBSSR; /*!< RTC alarm B sub second register, Address offset: 0x48 */\r
+ uint32_t RESERVED7; /*!< Reserved, 0x4C */\r
+ __IO uint32_t BKP0R; /*!< RTC backup register 0, Address offset: 0x50 */\r
+ __IO uint32_t BKP1R; /*!< RTC backup register 1, Address offset: 0x54 */\r
+ __IO uint32_t BKP2R; /*!< RTC backup register 2, Address offset: 0x58 */\r
+ __IO uint32_t BKP3R; /*!< RTC backup register 3, Address offset: 0x5C */\r
+ __IO uint32_t BKP4R; /*!< RTC backup register 4, Address offset: 0x60 */\r
+ __IO uint32_t BKP5R; /*!< RTC backup register 5, Address offset: 0x64 */\r
+ __IO uint32_t BKP6R; /*!< RTC backup register 6, Address offset: 0x68 */\r
+ __IO uint32_t BKP7R; /*!< RTC backup register 7, Address offset: 0x6C */\r
+ __IO uint32_t BKP8R; /*!< RTC backup register 8, Address offset: 0x70 */\r
+ __IO uint32_t BKP9R; /*!< RTC backup register 9, Address offset: 0x74 */\r
+ __IO uint32_t BKP10R; /*!< RTC backup register 10, Address offset: 0x78 */\r
+ __IO uint32_t BKP11R; /*!< RTC backup register 11, Address offset: 0x7C */\r
+ __IO uint32_t BKP12R; /*!< RTC backup register 12, Address offset: 0x80 */\r
+ __IO uint32_t BKP13R; /*!< RTC backup register 13, Address offset: 0x84 */\r
+ __IO uint32_t BKP14R; /*!< RTC backup register 14, Address offset: 0x88 */\r
+ __IO uint32_t BKP15R; /*!< RTC backup register 15, Address offset: 0x8C */\r
+ __IO uint32_t BKP16R; /*!< RTC backup register 16, Address offset: 0x90 */\r
+ __IO uint32_t BKP17R; /*!< RTC backup register 17, Address offset: 0x94 */\r
+ __IO uint32_t BKP18R; /*!< RTC backup register 18, Address offset: 0x98 */\r
+ __IO uint32_t BKP19R; /*!< RTC backup register 19, Address offset: 0x9C */\r
+ __IO uint32_t BKP20R; /*!< RTC backup register 20, Address offset: 0xA0 */\r
+ __IO uint32_t BKP21R; /*!< RTC backup register 21, Address offset: 0xA4 */\r
+ __IO uint32_t BKP22R; /*!< RTC backup register 22, Address offset: 0xA8 */\r
+ __IO uint32_t BKP23R; /*!< RTC backup register 23, Address offset: 0xAC */\r
+ __IO uint32_t BKP24R; /*!< RTC backup register 24, Address offset: 0xB0 */\r
+ __IO uint32_t BKP25R; /*!< RTC backup register 25, Address offset: 0xB4 */\r
+ __IO uint32_t BKP26R; /*!< RTC backup register 26, Address offset: 0xB8 */\r
+ __IO uint32_t BKP27R; /*!< RTC backup register 27, Address offset: 0xBC */\r
+ __IO uint32_t BKP28R; /*!< RTC backup register 28, Address offset: 0xC0 */\r
+ __IO uint32_t BKP29R; /*!< RTC backup register 29, Address offset: 0xC4 */\r
+ __IO uint32_t BKP30R; /*!< RTC backup register 30, Address offset: 0xC8 */\r
+ __IO uint32_t BKP31R; /*!< RTC backup register 31, Address offset: 0xCC */\r
+} RTC_TypeDef;\r
+\r
+/** \r
+ * @brief Serial Peripheral Interface\r
+ */\r
+\r
+typedef struct\r
+{\r
+ __IO uint32_t CR1; /*!< SPI Control register 1 (not used in I2S mode), Address offset: 0x00 */\r
+ __IO uint32_t CR2; /*!< SPI Control register 2, Address offset: 0x04 */\r
+ __IO uint32_t SR; /*!< SPI Status register, Address offset: 0x08 */\r
+ __IO uint32_t DR; /*!< SPI data register, Address offset: 0x0C */\r
+ __IO uint32_t CRCPR; /*!< SPI CRC polynomial register (not used in I2S mode), Address offset: 0x10 */\r
+ __IO uint32_t RXCRCR; /*!< SPI Rx CRC register (not used in I2S mode), Address offset: 0x14 */\r
+ __IO uint32_t TXCRCR; /*!< SPI Tx CRC register (not used in I2S mode), Address offset: 0x18 */\r
+ __IO uint32_t I2SCFGR; /*!< SPI_I2S configuration register, Address offset: 0x1C */\r
+ __IO uint32_t I2SPR; /*!< SPI_I2S prescaler register, Address offset: 0x20 */\r
+} SPI_TypeDef;\r
+\r
+/** \r
+ * @brief TIM\r
+ */\r
+typedef struct\r
+{\r
+ __IO uint32_t CR1; /*!< TIM control register 1, Address offset: 0x00 */\r
+ __IO uint32_t CR2; /*!< TIM control register 2, Address offset: 0x04 */\r
+ __IO uint32_t SMCR; /*!< TIM slave Mode Control register, Address offset: 0x08 */\r
+ __IO uint32_t DIER; /*!< TIM DMA/interrupt enable register, Address offset: 0x0C */\r
+ __IO uint32_t SR; /*!< TIM status register, Address offset: 0x10 */\r
+ __IO uint32_t EGR; /*!< TIM event generation register, Address offset: 0x14 */\r
+ __IO uint32_t CCMR1; /*!< TIM capture/compare mode register 1, Address offset: 0x18 */\r
+ __IO uint32_t CCMR2; /*!< TIM capture/compare mode register 2, Address offset: 0x1C */\r
+ __IO uint32_t CCER; /*!< TIM capture/compare enable register, Address offset: 0x20 */\r
+ __IO uint32_t CNT; /*!< TIM counter register, Address offset: 0x24 */\r
+ __IO uint32_t PSC; /*!< TIM prescaler register, Address offset: 0x28 */\r
+ __IO uint32_t ARR; /*!< TIM auto-reload register, Address offset: 0x2C */\r
+ uint32_t RESERVED12; /*!< Reserved, 0x30 */ \r
+ __IO uint32_t CCR1; /*!< TIM capture/compare register 1, Address offset: 0x34 */ \r
+ __IO uint32_t CCR2; /*!< TIM capture/compare register 2, Address offset: 0x38 */ \r
+ __IO uint32_t CCR3; /*!< TIM capture/compare register 3, Address offset: 0x3C */\r
+ __IO uint32_t CCR4; /*!< TIM capture/compare register 4, Address offset: 0x40 */\r
+ uint32_t RESERVED17; /*!< Reserved, 0x44 */ \r
+ __IO uint32_t DCR; /*!< TIM DMA control register, Address offset: 0x48 */\r
+ __IO uint32_t DMAR; /*!< TIM DMA address for full transfer, Address offset: 0x4C */\r
+ __IO uint32_t OR; /*!< TIM option register, Address offset: 0x50 */\r
+} TIM_TypeDef;\r
+/** \r
+ * @brief Universal Synchronous Asynchronous Receiver Transmitter\r
+ */\r
+ \r
+typedef struct\r
+{\r
+ __IO uint32_t SR; /*!< USART Status register, Address offset: 0x00 */\r
+ __IO uint32_t DR; /*!< USART Data register, Address offset: 0x04 */\r
+ __IO uint32_t BRR; /*!< USART Baud rate register, Address offset: 0x08 */\r
+ __IO uint32_t CR1; /*!< USART Control register 1, Address offset: 0x0C */\r
+ __IO uint32_t CR2; /*!< USART Control register 2, Address offset: 0x10 */\r
+ __IO uint32_t CR3; /*!< USART Control register 3, Address offset: 0x14 */\r
+ __IO uint32_t GTPR; /*!< USART Guard time and prescaler register, Address offset: 0x18 */\r
+} USART_TypeDef;\r
+\r
+/** \r
+ * @brief Universal Serial Bus Full Speed Device\r
+ */\r
+ \r
+typedef struct\r
+{\r
+ __IO uint16_t EP0R; /*!< USB Endpoint 0 register, Address offset: 0x00 */ \r
+ __IO uint16_t RESERVED0; /*!< Reserved */ \r
+ __IO uint16_t EP1R; /*!< USB Endpoint 1 register, Address offset: 0x04 */\r
+ __IO uint16_t RESERVED1; /*!< Reserved */ \r
+ __IO uint16_t EP2R; /*!< USB Endpoint 2 register, Address offset: 0x08 */\r
+ __IO uint16_t RESERVED2; /*!< Reserved */ \r
+ __IO uint16_t EP3R; /*!< USB Endpoint 3 register, Address offset: 0x0C */ \r
+ __IO uint16_t RESERVED3; /*!< Reserved */ \r
+ __IO uint16_t EP4R; /*!< USB Endpoint 4 register, Address offset: 0x10 */\r
+ __IO uint16_t RESERVED4; /*!< Reserved */ \r
+ __IO uint16_t EP5R; /*!< USB Endpoint 5 register, Address offset: 0x14 */\r
+ __IO uint16_t RESERVED5; /*!< Reserved */ \r
+ __IO uint16_t EP6R; /*!< USB Endpoint 6 register, Address offset: 0x18 */\r
+ __IO uint16_t RESERVED6; /*!< Reserved */ \r
+ __IO uint16_t EP7R; /*!< USB Endpoint 7 register, Address offset: 0x1C */\r
+ __IO uint16_t RESERVED7[17]; /*!< Reserved */ \r
+ __IO uint16_t CNTR; /*!< Control register, Address offset: 0x40 */\r
+ __IO uint16_t RESERVED8; /*!< Reserved */ \r
+ __IO uint16_t ISTR; /*!< Interrupt status register, Address offset: 0x44 */\r
+ __IO uint16_t RESERVED9; /*!< Reserved */ \r
+ __IO uint16_t FNR; /*!< Frame number register, Address offset: 0x48 */\r
+ __IO uint16_t RESERVEDA; /*!< Reserved */ \r
+ __IO uint16_t DADDR; /*!< Device address register, Address offset: 0x4C */\r
+ __IO uint16_t RESERVEDB; /*!< Reserved */ \r
+ __IO uint16_t BTABLE; /*!< Buffer Table address register, Address offset: 0x50 */\r
+ __IO uint16_t RESERVEDC; /*!< Reserved */ \r
+} USB_TypeDef;\r
+\r
+/** \r
+ * @brief Window WATCHDOG\r
+ */\r
+typedef struct\r
+{\r
+ __IO uint32_t CR; /*!< WWDG Control register, Address offset: 0x00 */\r
+ __IO uint32_t CFR; /*!< WWDG Configuration register, Address offset: 0x04 */\r
+ __IO uint32_t SR; /*!< WWDG Status register, Address offset: 0x08 */\r
+} WWDG_TypeDef;\r
+\r
+/** \r
+ * @brief Universal Serial Bus Full Speed Device\r
+ */\r
+/** \r
+ * @}\r
+ */\r
+ \r
+/** @addtogroup Peripheral_memory_map\r
+ * @{\r
+ */\r
+\r
+#define FLASH_BASE (0x08000000UL) /*!< FLASH base address in the alias region */\r
+#define FLASH_EEPROM_BASE (FLASH_BASE + 0x80000UL) /*!< FLASH EEPROM base address in the alias region */\r
+#define SRAM_BASE (0x20000000UL) /*!< SRAM base address in the alias region */\r
+#define PERIPH_BASE (0x40000000UL) /*!< Peripheral base address in the alias region */\r
+#define SRAM_BB_BASE (0x22000000UL) /*!< SRAM base address in the bit-band region */\r
+#define PERIPH_BB_BASE (0x42000000UL) /*!< Peripheral base address in the bit-band region */\r
+#define FLASH_BANK2_BASE (0x08040000UL) /*!< FLASH BANK2 base address in the alias region */\r
+#define FLASH_BANK1_END (0x0803FFFFUL) /*!< Program end FLASH BANK1 address */\r
+#define FLASH_BANK2_END (0x0807FFFFUL) /*!< Program end FLASH BANK2 address */\r
+#define FLASH_EEPROM_END (0x08083FFFUL) /*!< FLASH EEPROM end address (16KB) */\r
+\r
+/*!< Peripheral memory map */\r
+#define APB1PERIPH_BASE PERIPH_BASE\r
+#define APB2PERIPH_BASE (PERIPH_BASE + 0x00010000UL)\r
+#define AHBPERIPH_BASE (PERIPH_BASE + 0x00020000UL)\r
+\r
+/*!< APB1 peripherals */\r
+#define TIM2_BASE (APB1PERIPH_BASE + 0x00000000UL)\r
+#define TIM3_BASE (APB1PERIPH_BASE + 0x00000400UL)\r
+#define TIM4_BASE (APB1PERIPH_BASE + 0x00000800UL)\r
+#define TIM5_BASE (APB1PERIPH_BASE + 0x00000C00UL)\r
+#define TIM6_BASE (APB1PERIPH_BASE + 0x00001000UL)\r
+#define TIM7_BASE (APB1PERIPH_BASE + 0x00001400UL)\r
+#define LCD_BASE (APB1PERIPH_BASE + 0x00002400UL)\r
+#define RTC_BASE (APB1PERIPH_BASE + 0x00002800UL)\r
+#define WWDG_BASE (APB1PERIPH_BASE + 0x00002C00UL)\r
+#define IWDG_BASE (APB1PERIPH_BASE + 0x00003000UL)\r
+#define SPI2_BASE (APB1PERIPH_BASE + 0x00003800UL)\r
+#define SPI3_BASE (APB1PERIPH_BASE + 0x00003C00UL)\r
+#define USART2_BASE (APB1PERIPH_BASE + 0x00004400UL)\r
+#define USART3_BASE (APB1PERIPH_BASE + 0x00004800UL)\r
+#define UART4_BASE (APB1PERIPH_BASE + 0x00004C00UL)\r
+#define UART5_BASE (APB1PERIPH_BASE + 0x00005000UL)\r
+#define I2C1_BASE (APB1PERIPH_BASE + 0x00005400UL)\r
+#define I2C2_BASE (APB1PERIPH_BASE + 0x00005800UL)\r
+\r
+/* USB device FS */\r
+#define USB_BASE (APB1PERIPH_BASE + 0x00005C00UL) /*!< USB_IP Peripheral Registers base address */\r
+#define USB_PMAADDR (APB1PERIPH_BASE + 0x00006000UL) /*!< USB_IP Packet Memory Area base address */\r
+\r
+/* USB device FS SRAM */\r
+#define PWR_BASE (APB1PERIPH_BASE + 0x00007000UL)\r
+#define DAC_BASE (APB1PERIPH_BASE + 0x00007400UL)\r
+#define COMP_BASE (APB1PERIPH_BASE + 0x00007C00UL)\r
+#define RI_BASE (APB1PERIPH_BASE + 0x00007C04UL)\r
+#define OPAMP_BASE (APB1PERIPH_BASE + 0x00007C5CUL)\r
+\r
+/*!< APB2 peripherals */\r
+#define SYSCFG_BASE (APB2PERIPH_BASE + 0x00000000UL)\r
+#define EXTI_BASE (APB2PERIPH_BASE + 0x00000400UL)\r
+#define TIM9_BASE (APB2PERIPH_BASE + 0x00000800UL)\r
+#define TIM10_BASE (APB2PERIPH_BASE + 0x00000C00UL)\r
+#define TIM11_BASE (APB2PERIPH_BASE + 0x00001000UL)\r
+#define ADC1_BASE (APB2PERIPH_BASE + 0x00002400UL)\r
+#define ADC_BASE (APB2PERIPH_BASE + 0x00002700UL)\r
+#define SPI1_BASE (APB2PERIPH_BASE + 0x00003000UL)\r
+#define USART1_BASE (APB2PERIPH_BASE + 0x00003800UL)\r
+\r
+/*!< AHB peripherals */\r
+#define GPIOA_BASE (AHBPERIPH_BASE + 0x00000000UL)\r
+#define GPIOB_BASE (AHBPERIPH_BASE + 0x00000400UL)\r
+#define GPIOC_BASE (AHBPERIPH_BASE + 0x00000800UL)\r
+#define GPIOD_BASE (AHBPERIPH_BASE + 0x00000C00UL)\r
+#define GPIOE_BASE (AHBPERIPH_BASE + 0x00001000UL)\r
+#define GPIOH_BASE (AHBPERIPH_BASE + 0x00001400UL)\r
+#define GPIOF_BASE (AHBPERIPH_BASE + 0x00001800UL)\r
+#define GPIOG_BASE (AHBPERIPH_BASE + 0x00001C00UL)\r
+#define CRC_BASE (AHBPERIPH_BASE + 0x00003000UL)\r
+#define RCC_BASE (AHBPERIPH_BASE + 0x00003800UL)\r
+#define FLASH_R_BASE (AHBPERIPH_BASE + 0x00003C00UL) /*!< FLASH registers base address */\r
+#define OB_BASE (0x1FF80000UL) /*!< FLASH Option Bytes base address */\r
+#define FLASHSIZE_BASE (0x1FF800CCUL) /*!< FLASH Size register base address for Cat.3, Cat.4, Cat.5 and Cat.6 devices */\r
+#define UID_BASE (0x1FF800D0UL) /*!< Unique device ID register base address for Cat.3, Cat.4, Cat.5 and Cat.6 devices */\r
+#define DMA1_BASE (AHBPERIPH_BASE + 0x00006000UL)\r
+#define DMA1_Channel1_BASE (DMA1_BASE + 0x00000008UL)\r
+#define DMA1_Channel2_BASE (DMA1_BASE + 0x0000001CUL)\r
+#define DMA1_Channel3_BASE (DMA1_BASE + 0x00000030UL)\r
+#define DMA1_Channel4_BASE (DMA1_BASE + 0x00000044UL)\r
+#define DMA1_Channel5_BASE (DMA1_BASE + 0x00000058UL)\r
+#define DMA1_Channel6_BASE (DMA1_BASE + 0x0000006CUL)\r
+#define DMA1_Channel7_BASE (DMA1_BASE + 0x00000080UL)\r
+#define DMA2_BASE (AHBPERIPH_BASE + 0x00006400UL)\r
+#define DMA2_Channel1_BASE (DMA2_BASE + 0x00000008UL)\r
+#define DMA2_Channel2_BASE (DMA2_BASE + 0x0000001CUL)\r
+#define DMA2_Channel3_BASE (DMA2_BASE + 0x00000030UL)\r
+#define DMA2_Channel4_BASE (DMA2_BASE + 0x00000044UL)\r
+#define DMA2_Channel5_BASE (DMA2_BASE + 0x00000058UL)\r
+#define DBGMCU_BASE (0xE0042000UL) /*!< Debug MCU registers base address */\r
+\r
+/**\r
+ * @}\r
+ */\r
+ \r
+/** @addtogroup Peripheral_declaration\r
+ * @{\r
+ */ \r
+\r
+#define TIM2 ((TIM_TypeDef *) TIM2_BASE)\r
+#define TIM3 ((TIM_TypeDef *) TIM3_BASE)\r
+#define TIM4 ((TIM_TypeDef *) TIM4_BASE)\r
+#define TIM5 ((TIM_TypeDef *) TIM5_BASE)\r
+#define TIM6 ((TIM_TypeDef *) TIM6_BASE)\r
+#define TIM7 ((TIM_TypeDef *) TIM7_BASE)\r
+#define LCD ((LCD_TypeDef *) LCD_BASE)\r
+#define RTC ((RTC_TypeDef *) RTC_BASE)\r
+#define WWDG ((WWDG_TypeDef *) WWDG_BASE)\r
+#define IWDG ((IWDG_TypeDef *) IWDG_BASE)\r
+#define SPI2 ((SPI_TypeDef *) SPI2_BASE)\r
+#define SPI3 ((SPI_TypeDef *) SPI3_BASE)\r
+#define USART2 ((USART_TypeDef *) USART2_BASE)\r
+#define USART3 ((USART_TypeDef *) USART3_BASE)\r
+#define UART4 ((USART_TypeDef *) UART4_BASE)\r
+#define UART5 ((USART_TypeDef *) UART5_BASE)\r
+#define I2C1 ((I2C_TypeDef *) I2C1_BASE)\r
+#define I2C2 ((I2C_TypeDef *) I2C2_BASE)\r
+/* USB device FS */\r
+#define USB ((USB_TypeDef *) USB_BASE)\r
+/* USB device FS SRAM */\r
+#define PWR ((PWR_TypeDef *) PWR_BASE)\r
+\r
+#define DAC1 ((DAC_TypeDef *) DAC_BASE)\r
+/* Legacy define */\r
+#define DAC DAC1\r
+\r
+#define COMP ((COMP_TypeDef *) COMP_BASE) /* COMP generic instance include bits of COMP1 and COMP2 mixed in the same register */\r
+#define COMP1 ((COMP_TypeDef *) COMP_BASE) /* COMP1 instance definition to differentiate COMP1 and COMP2, not to be used to access comparator register */\r
+#define COMP2 ((COMP_TypeDef *) (COMP_BASE + 0x00000001U)) /* COMP2 instance definition to differentiate COMP1 and COMP2, not to be used to access comparator register */\r
+#define COMP12_COMMON ((COMP_Common_TypeDef *) COMP_BASE) /* COMP common instance definition to access comparator register bits used by both comparator instances (window mode) */\r
+\r
+#define RI ((RI_TypeDef *) RI_BASE)\r
+\r
+#define OPAMP ((OPAMP_TypeDef *) OPAMP_BASE)\r
+#define OPAMP1 ((OPAMP_TypeDef *) OPAMP_BASE)\r
+#define OPAMP2 ((OPAMP_TypeDef *) (OPAMP_BASE + 0x00000001U))\r
+#define OPAMP12_COMMON ((OPAMP_Common_TypeDef *) OPAMP_BASE)\r
+#define SYSCFG ((SYSCFG_TypeDef *) SYSCFG_BASE)\r
+#define EXTI ((EXTI_TypeDef *) EXTI_BASE)\r
+#define TIM9 ((TIM_TypeDef *) TIM9_BASE)\r
+#define TIM10 ((TIM_TypeDef *) TIM10_BASE)\r
+#define TIM11 ((TIM_TypeDef *) TIM11_BASE)\r
+\r
+#define ADC1 ((ADC_TypeDef *) ADC1_BASE)\r
+#define ADC1_COMMON ((ADC_Common_TypeDef *) ADC_BASE)\r
+/* Legacy defines */\r
+#define ADC ADC1_COMMON\r
+\r
+#define SPI1 ((SPI_TypeDef *) SPI1_BASE)\r
+#define USART1 ((USART_TypeDef *) USART1_BASE)\r
+#define GPIOA ((GPIO_TypeDef *) GPIOA_BASE)\r
+#define GPIOB ((GPIO_TypeDef *) GPIOB_BASE)\r
+#define GPIOC ((GPIO_TypeDef *) GPIOC_BASE)\r
+#define GPIOD ((GPIO_TypeDef *) GPIOD_BASE)\r
+#define GPIOE ((GPIO_TypeDef *) GPIOE_BASE)\r
+#define GPIOH ((GPIO_TypeDef *) GPIOH_BASE)\r
+#define GPIOF ((GPIO_TypeDef *) GPIOF_BASE)\r
+#define GPIOG ((GPIO_TypeDef *) GPIOG_BASE)\r
+#define CRC ((CRC_TypeDef *) CRC_BASE)\r
+#define RCC ((RCC_TypeDef *) RCC_BASE)\r
+#define FLASH ((FLASH_TypeDef *) FLASH_R_BASE)\r
+#define OB ((OB_TypeDef *) OB_BASE) \r
+#define DMA1 ((DMA_TypeDef *) DMA1_BASE)\r
+#define DMA1_Channel1 ((DMA_Channel_TypeDef *) DMA1_Channel1_BASE)\r
+#define DMA1_Channel2 ((DMA_Channel_TypeDef *) DMA1_Channel2_BASE)\r
+#define DMA1_Channel3 ((DMA_Channel_TypeDef *) DMA1_Channel3_BASE)\r
+#define DMA1_Channel4 ((DMA_Channel_TypeDef *) DMA1_Channel4_BASE)\r
+#define DMA1_Channel5 ((DMA_Channel_TypeDef *) DMA1_Channel5_BASE)\r
+#define DMA1_Channel6 ((DMA_Channel_TypeDef *) DMA1_Channel6_BASE)\r
+#define DMA1_Channel7 ((DMA_Channel_TypeDef *) DMA1_Channel7_BASE)\r
+#define DMA2 ((DMA_TypeDef *) DMA2_BASE)\r
+#define DMA2_Channel1 ((DMA_Channel_TypeDef *) DMA2_Channel1_BASE)\r
+#define DMA2_Channel2 ((DMA_Channel_TypeDef *) DMA2_Channel2_BASE)\r
+#define DMA2_Channel3 ((DMA_Channel_TypeDef *) DMA2_Channel3_BASE)\r
+#define DMA2_Channel4 ((DMA_Channel_TypeDef *) DMA2_Channel4_BASE)\r
+#define DMA2_Channel5 ((DMA_Channel_TypeDef *) DMA2_Channel5_BASE)\r
+#define DBGMCU ((DBGMCU_TypeDef *) DBGMCU_BASE)\r
+\r
+ /**\r
+ * @}\r
+ */\r
+\r
+/** @addtogroup Exported_constants\r
+ * @{\r
+ */\r
+\r
+/** @addtogroup Peripheral_Registers_Bits_Definition\r
+ * @{\r
+ */\r
+ \r
+/******************************************************************************/\r
+/* Peripheral Registers Bits Definition */\r
+/******************************************************************************/\r
+/******************************************************************************/\r
+/* */\r
+/* Analog to Digital Converter (ADC) */\r
+/* */\r
+/******************************************************************************/\r
+\r
+/******************** Bit definition for ADC_SR register ********************/\r
+#define ADC_SR_AWD_Pos (0U) \r
+#define ADC_SR_AWD_Msk (0x1UL << ADC_SR_AWD_Pos) /*!< 0x00000001 */\r
+#define ADC_SR_AWD ADC_SR_AWD_Msk /*!< ADC analog watchdog 1 flag */\r
+#define ADC_SR_EOCS_Pos (1U) \r
+#define ADC_SR_EOCS_Msk (0x1UL << ADC_SR_EOCS_Pos) /*!< 0x00000002 */\r
+#define ADC_SR_EOCS ADC_SR_EOCS_Msk /*!< ADC group regular end of unitary conversion or end of sequence conversions flag */\r
+#define ADC_SR_JEOS_Pos (2U) \r
+#define ADC_SR_JEOS_Msk (0x1UL << ADC_SR_JEOS_Pos) /*!< 0x00000004 */\r
+#define ADC_SR_JEOS ADC_SR_JEOS_Msk /*!< ADC group injected end of sequence conversions flag */\r
+#define ADC_SR_JSTRT_Pos (3U) \r
+#define ADC_SR_JSTRT_Msk (0x1UL << ADC_SR_JSTRT_Pos) /*!< 0x00000008 */\r
+#define ADC_SR_JSTRT ADC_SR_JSTRT_Msk /*!< ADC group injected conversion start flag */\r
+#define ADC_SR_STRT_Pos (4U) \r
+#define ADC_SR_STRT_Msk (0x1UL << ADC_SR_STRT_Pos) /*!< 0x00000010 */\r
+#define ADC_SR_STRT ADC_SR_STRT_Msk /*!< ADC group regular conversion start flag */\r
+#define ADC_SR_OVR_Pos (5U) \r
+#define ADC_SR_OVR_Msk (0x1UL << ADC_SR_OVR_Pos) /*!< 0x00000020 */\r
+#define ADC_SR_OVR ADC_SR_OVR_Msk /*!< ADC group regular overrun flag */\r
+#define ADC_SR_ADONS_Pos (6U) \r
+#define ADC_SR_ADONS_Msk (0x1UL << ADC_SR_ADONS_Pos) /*!< 0x00000040 */\r
+#define ADC_SR_ADONS ADC_SR_ADONS_Msk /*!< ADC ready flag */\r
+#define ADC_SR_RCNR_Pos (8U) \r
+#define ADC_SR_RCNR_Msk (0x1UL << ADC_SR_RCNR_Pos) /*!< 0x00000100 */\r
+#define ADC_SR_RCNR ADC_SR_RCNR_Msk /*!< ADC group regular not ready flag */\r
+#define ADC_SR_JCNR_Pos (9U) \r
+#define ADC_SR_JCNR_Msk (0x1UL << ADC_SR_JCNR_Pos) /*!< 0x00000200 */\r
+#define ADC_SR_JCNR ADC_SR_JCNR_Msk /*!< ADC group injected not ready flag */\r
+\r
+/* Legacy defines */\r
+#define ADC_SR_EOC (ADC_SR_EOCS)\r
+#define ADC_SR_JEOC (ADC_SR_JEOS)\r
+\r
+/******************* Bit definition for ADC_CR1 register ********************/\r
+#define ADC_CR1_AWDCH_Pos (0U) \r
+#define ADC_CR1_AWDCH_Msk (0x1FUL << ADC_CR1_AWDCH_Pos) /*!< 0x0000001F */\r
+#define ADC_CR1_AWDCH ADC_CR1_AWDCH_Msk /*!< ADC analog watchdog 1 monitored channel selection */\r
+#define ADC_CR1_AWDCH_0 (0x01UL << ADC_CR1_AWDCH_Pos) /*!< 0x00000001 */\r
+#define ADC_CR1_AWDCH_1 (0x02UL << ADC_CR1_AWDCH_Pos) /*!< 0x00000002 */\r
+#define ADC_CR1_AWDCH_2 (0x04UL << ADC_CR1_AWDCH_Pos) /*!< 0x00000004 */\r
+#define ADC_CR1_AWDCH_3 (0x08UL << ADC_CR1_AWDCH_Pos) /*!< 0x00000008 */\r
+#define ADC_CR1_AWDCH_4 (0x10UL << ADC_CR1_AWDCH_Pos) /*!< 0x00000010 */\r
+\r
+#define ADC_CR1_EOCSIE_Pos (5U) \r
+#define ADC_CR1_EOCSIE_Msk (0x1UL << ADC_CR1_EOCSIE_Pos) /*!< 0x00000020 */\r
+#define ADC_CR1_EOCSIE ADC_CR1_EOCSIE_Msk /*!< ADC group regular end of unitary conversion or end of sequence conversions interrupt */\r
+#define ADC_CR1_AWDIE_Pos (6U) \r
+#define ADC_CR1_AWDIE_Msk (0x1UL << ADC_CR1_AWDIE_Pos) /*!< 0x00000040 */\r
+#define ADC_CR1_AWDIE ADC_CR1_AWDIE_Msk /*!< ADC analog watchdog 1 interrupt */\r
+#define ADC_CR1_JEOSIE_Pos (7U) \r
+#define ADC_CR1_JEOSIE_Msk (0x1UL << ADC_CR1_JEOSIE_Pos) /*!< 0x00000080 */\r
+#define ADC_CR1_JEOSIE ADC_CR1_JEOSIE_Msk /*!< ADC group injected end of sequence conversions interrupt */\r
+#define ADC_CR1_SCAN_Pos (8U) \r
+#define ADC_CR1_SCAN_Msk (0x1UL << ADC_CR1_SCAN_Pos) /*!< 0x00000100 */\r
+#define ADC_CR1_SCAN ADC_CR1_SCAN_Msk /*!< ADC scan mode */\r
+#define ADC_CR1_AWDSGL_Pos (9U) \r
+#define ADC_CR1_AWDSGL_Msk (0x1UL << ADC_CR1_AWDSGL_Pos) /*!< 0x00000200 */\r
+#define ADC_CR1_AWDSGL ADC_CR1_AWDSGL_Msk /*!< ADC analog watchdog 1 monitoring a single channel or all channels */\r
+#define ADC_CR1_JAUTO_Pos (10U) \r
+#define ADC_CR1_JAUTO_Msk (0x1UL << ADC_CR1_JAUTO_Pos) /*!< 0x00000400 */\r
+#define ADC_CR1_JAUTO ADC_CR1_JAUTO_Msk /*!< ADC group injected automatic trigger mode */\r
+#define ADC_CR1_DISCEN_Pos (11U) \r
+#define ADC_CR1_DISCEN_Msk (0x1UL << ADC_CR1_DISCEN_Pos) /*!< 0x00000800 */\r
+#define ADC_CR1_DISCEN ADC_CR1_DISCEN_Msk /*!< ADC group regular sequencer discontinuous mode */\r
+#define ADC_CR1_JDISCEN_Pos (12U) \r
+#define ADC_CR1_JDISCEN_Msk (0x1UL << ADC_CR1_JDISCEN_Pos) /*!< 0x00001000 */\r
+#define ADC_CR1_JDISCEN ADC_CR1_JDISCEN_Msk /*!< ADC group injected sequencer discontinuous mode */\r
+\r
+#define ADC_CR1_DISCNUM_Pos (13U) \r
+#define ADC_CR1_DISCNUM_Msk (0x7UL << ADC_CR1_DISCNUM_Pos) /*!< 0x0000E000 */\r
+#define ADC_CR1_DISCNUM ADC_CR1_DISCNUM_Msk /*!< ADC group regular sequencer discontinuous number of ranks */\r
+#define ADC_CR1_DISCNUM_0 (0x1UL << ADC_CR1_DISCNUM_Pos) /*!< 0x00002000 */\r
+#define ADC_CR1_DISCNUM_1 (0x2UL << ADC_CR1_DISCNUM_Pos) /*!< 0x00004000 */\r
+#define ADC_CR1_DISCNUM_2 (0x4UL << ADC_CR1_DISCNUM_Pos) /*!< 0x00008000 */\r
+\r
+#define ADC_CR1_PDD_Pos (16U) \r
+#define ADC_CR1_PDD_Msk (0x1UL << ADC_CR1_PDD_Pos) /*!< 0x00010000 */\r
+#define ADC_CR1_PDD ADC_CR1_PDD_Msk /*!< ADC power down during auto delay phase */\r
+#define ADC_CR1_PDI_Pos (17U) \r
+#define ADC_CR1_PDI_Msk (0x1UL << ADC_CR1_PDI_Pos) /*!< 0x00020000 */\r
+#define ADC_CR1_PDI ADC_CR1_PDI_Msk /*!< ADC power down during idle phase */\r
+\r
+#define ADC_CR1_JAWDEN_Pos (22U) \r
+#define ADC_CR1_JAWDEN_Msk (0x1UL << ADC_CR1_JAWDEN_Pos) /*!< 0x00400000 */\r
+#define ADC_CR1_JAWDEN ADC_CR1_JAWDEN_Msk /*!< ADC analog watchdog 1 enable on scope ADC group injected */\r
+#define ADC_CR1_AWDEN_Pos (23U) \r
+#define ADC_CR1_AWDEN_Msk (0x1UL << ADC_CR1_AWDEN_Pos) /*!< 0x00800000 */\r
+#define ADC_CR1_AWDEN ADC_CR1_AWDEN_Msk /*!< ADC analog watchdog 1 enable on scope ADC group regular */\r
+\r
+#define ADC_CR1_RES_Pos (24U) \r
+#define ADC_CR1_RES_Msk (0x3UL << ADC_CR1_RES_Pos) /*!< 0x03000000 */\r
+#define ADC_CR1_RES ADC_CR1_RES_Msk /*!< ADC resolution */\r
+#define ADC_CR1_RES_0 (0x1UL << ADC_CR1_RES_Pos) /*!< 0x01000000 */\r
+#define ADC_CR1_RES_1 (0x2UL << ADC_CR1_RES_Pos) /*!< 0x02000000 */\r
+\r
+#define ADC_CR1_OVRIE_Pos (26U) \r
+#define ADC_CR1_OVRIE_Msk (0x1UL << ADC_CR1_OVRIE_Pos) /*!< 0x04000000 */\r
+#define ADC_CR1_OVRIE ADC_CR1_OVRIE_Msk /*!< ADC group regular overrun interrupt */\r
+\r
+/* Legacy defines */\r
+#define ADC_CR1_EOCIE (ADC_CR1_EOCSIE)\r
+#define ADC_CR1_JEOCIE (ADC_CR1_JEOSIE)\r
+\r
+/******************* Bit definition for ADC_CR2 register ********************/\r
+#define ADC_CR2_ADON_Pos (0U) \r
+#define ADC_CR2_ADON_Msk (0x1UL << ADC_CR2_ADON_Pos) /*!< 0x00000001 */\r
+#define ADC_CR2_ADON ADC_CR2_ADON_Msk /*!< ADC enable */\r
+#define ADC_CR2_CONT_Pos (1U) \r
+#define ADC_CR2_CONT_Msk (0x1UL << ADC_CR2_CONT_Pos) /*!< 0x00000002 */\r
+#define ADC_CR2_CONT ADC_CR2_CONT_Msk /*!< ADC group regular continuous conversion mode */\r
+#define ADC_CR2_CFG_Pos (2U) \r
+#define ADC_CR2_CFG_Msk (0x1UL << ADC_CR2_CFG_Pos) /*!< 0x00000004 */\r
+#define ADC_CR2_CFG ADC_CR2_CFG_Msk /*!< ADC channels bank selection */\r
+\r
+#define ADC_CR2_DELS_Pos (4U) \r
+#define ADC_CR2_DELS_Msk (0x7UL << ADC_CR2_DELS_Pos) /*!< 0x00000070 */\r
+#define ADC_CR2_DELS ADC_CR2_DELS_Msk /*!< ADC auto delay selection */\r
+#define ADC_CR2_DELS_0 (0x1UL << ADC_CR2_DELS_Pos) /*!< 0x00000010 */\r
+#define ADC_CR2_DELS_1 (0x2UL << ADC_CR2_DELS_Pos) /*!< 0x00000020 */\r
+#define ADC_CR2_DELS_2 (0x4UL << ADC_CR2_DELS_Pos) /*!< 0x00000040 */\r
+\r
+#define ADC_CR2_DMA_Pos (8U) \r
+#define ADC_CR2_DMA_Msk (0x1UL << ADC_CR2_DMA_Pos) /*!< 0x00000100 */\r
+#define ADC_CR2_DMA ADC_CR2_DMA_Msk /*!< ADC DMA transfer enable */\r
+#define ADC_CR2_DDS_Pos (9U) \r
+#define ADC_CR2_DDS_Msk (0x1UL << ADC_CR2_DDS_Pos) /*!< 0x00000200 */\r
+#define ADC_CR2_DDS ADC_CR2_DDS_Msk /*!< ADC DMA transfer configuration */\r
+#define ADC_CR2_EOCS_Pos (10U) \r
+#define ADC_CR2_EOCS_Msk (0x1UL << ADC_CR2_EOCS_Pos) /*!< 0x00000400 */\r
+#define ADC_CR2_EOCS ADC_CR2_EOCS_Msk /*!< ADC end of unitary or end of sequence conversions selection */\r
+#define ADC_CR2_ALIGN_Pos (11U) \r
+#define ADC_CR2_ALIGN_Msk (0x1UL << ADC_CR2_ALIGN_Pos) /*!< 0x00000800 */\r
+#define ADC_CR2_ALIGN ADC_CR2_ALIGN_Msk /*!< ADC data alignement */\r
+\r
+#define ADC_CR2_JEXTSEL_Pos (16U) \r
+#define ADC_CR2_JEXTSEL_Msk (0xFUL << ADC_CR2_JEXTSEL_Pos) /*!< 0x000F0000 */\r
+#define ADC_CR2_JEXTSEL ADC_CR2_JEXTSEL_Msk /*!< ADC group injected external trigger source */\r
+#define ADC_CR2_JEXTSEL_0 (0x1UL << ADC_CR2_JEXTSEL_Pos) /*!< 0x00010000 */\r
+#define ADC_CR2_JEXTSEL_1 (0x2UL << ADC_CR2_JEXTSEL_Pos) /*!< 0x00020000 */\r
+#define ADC_CR2_JEXTSEL_2 (0x4UL << ADC_CR2_JEXTSEL_Pos) /*!< 0x00040000 */\r
+#define ADC_CR2_JEXTSEL_3 (0x8UL << ADC_CR2_JEXTSEL_Pos) /*!< 0x00080000 */\r
+\r
+#define ADC_CR2_JEXTEN_Pos (20U) \r
+#define ADC_CR2_JEXTEN_Msk (0x3UL << ADC_CR2_JEXTEN_Pos) /*!< 0x00300000 */\r
+#define ADC_CR2_JEXTEN ADC_CR2_JEXTEN_Msk /*!< ADC group injected external trigger polarity */\r
+#define ADC_CR2_JEXTEN_0 (0x1UL << ADC_CR2_JEXTEN_Pos) /*!< 0x00100000 */\r
+#define ADC_CR2_JEXTEN_1 (0x2UL << ADC_CR2_JEXTEN_Pos) /*!< 0x00200000 */\r
+\r
+#define ADC_CR2_JSWSTART_Pos (22U) \r
+#define ADC_CR2_JSWSTART_Msk (0x1UL << ADC_CR2_JSWSTART_Pos) /*!< 0x00400000 */\r
+#define ADC_CR2_JSWSTART ADC_CR2_JSWSTART_Msk /*!< ADC group injected conversion start */\r
+\r
+#define ADC_CR2_EXTSEL_Pos (24U) \r
+#define ADC_CR2_EXTSEL_Msk (0xFUL << ADC_CR2_EXTSEL_Pos) /*!< 0x0F000000 */\r
+#define ADC_CR2_EXTSEL ADC_CR2_EXTSEL_Msk /*!< ADC group regular external trigger source */\r
+#define ADC_CR2_EXTSEL_0 (0x1UL << ADC_CR2_EXTSEL_Pos) /*!< 0x01000000 */\r
+#define ADC_CR2_EXTSEL_1 (0x2UL << ADC_CR2_EXTSEL_Pos) /*!< 0x02000000 */\r
+#define ADC_CR2_EXTSEL_2 (0x4UL << ADC_CR2_EXTSEL_Pos) /*!< 0x04000000 */\r
+#define ADC_CR2_EXTSEL_3 (0x8UL << ADC_CR2_EXTSEL_Pos) /*!< 0x08000000 */\r
+\r
+#define ADC_CR2_EXTEN_Pos (28U) \r
+#define ADC_CR2_EXTEN_Msk (0x3UL << ADC_CR2_EXTEN_Pos) /*!< 0x30000000 */\r
+#define ADC_CR2_EXTEN ADC_CR2_EXTEN_Msk /*!< ADC group regular external trigger polarity */\r
+#define ADC_CR2_EXTEN_0 (0x1UL << ADC_CR2_EXTEN_Pos) /*!< 0x10000000 */\r
+#define ADC_CR2_EXTEN_1 (0x2UL << ADC_CR2_EXTEN_Pos) /*!< 0x20000000 */\r
+\r
+#define ADC_CR2_SWSTART_Pos (30U) \r
+#define ADC_CR2_SWSTART_Msk (0x1UL << ADC_CR2_SWSTART_Pos) /*!< 0x40000000 */\r
+#define ADC_CR2_SWSTART ADC_CR2_SWSTART_Msk /*!< ADC group regular conversion start */\r
+\r
+/****************** Bit definition for ADC_SMPR1 register *******************/\r
+#define ADC_SMPR1_SMP20_Pos (0U) \r
+#define ADC_SMPR1_SMP20_Msk (0x7UL << ADC_SMPR1_SMP20_Pos) /*!< 0x00000007 */\r
+#define ADC_SMPR1_SMP20 ADC_SMPR1_SMP20_Msk /*!< ADC channel 20 sampling time selection */\r
+#define ADC_SMPR1_SMP20_0 (0x1UL << ADC_SMPR1_SMP20_Pos) /*!< 0x00000001 */\r
+#define ADC_SMPR1_SMP20_1 (0x2UL << ADC_SMPR1_SMP20_Pos) /*!< 0x00000002 */\r
+#define ADC_SMPR1_SMP20_2 (0x4UL << ADC_SMPR1_SMP20_Pos) /*!< 0x00000004 */\r
+\r
+#define ADC_SMPR1_SMP21_Pos (3U) \r
+#define ADC_SMPR1_SMP21_Msk (0x7UL << ADC_SMPR1_SMP21_Pos) /*!< 0x00000038 */\r
+#define ADC_SMPR1_SMP21 ADC_SMPR1_SMP21_Msk /*!< ADC channel 21 sampling time selection */\r
+#define ADC_SMPR1_SMP21_0 (0x1UL << ADC_SMPR1_SMP21_Pos) /*!< 0x00000008 */\r
+#define ADC_SMPR1_SMP21_1 (0x2UL << ADC_SMPR1_SMP21_Pos) /*!< 0x00000010 */\r
+#define ADC_SMPR1_SMP21_2 (0x4UL << ADC_SMPR1_SMP21_Pos) /*!< 0x00000020 */\r
+\r
+#define ADC_SMPR1_SMP22_Pos (6U) \r
+#define ADC_SMPR1_SMP22_Msk (0x7UL << ADC_SMPR1_SMP22_Pos) /*!< 0x000001C0 */\r
+#define ADC_SMPR1_SMP22 ADC_SMPR1_SMP22_Msk /*!< ADC channel 22 sampling time selection */\r
+#define ADC_SMPR1_SMP22_0 (0x1UL << ADC_SMPR1_SMP22_Pos) /*!< 0x00000040 */\r
+#define ADC_SMPR1_SMP22_1 (0x2UL << ADC_SMPR1_SMP22_Pos) /*!< 0x00000080 */\r
+#define ADC_SMPR1_SMP22_2 (0x4UL << ADC_SMPR1_SMP22_Pos) /*!< 0x00000100 */\r
+\r
+#define ADC_SMPR1_SMP23_Pos (9U) \r
+#define ADC_SMPR1_SMP23_Msk (0x7UL << ADC_SMPR1_SMP23_Pos) /*!< 0x00000E00 */\r
+#define ADC_SMPR1_SMP23 ADC_SMPR1_SMP23_Msk /*!< ADC channel 23 sampling time selection */\r
+#define ADC_SMPR1_SMP23_0 (0x1UL << ADC_SMPR1_SMP23_Pos) /*!< 0x00000200 */\r
+#define ADC_SMPR1_SMP23_1 (0x2UL << ADC_SMPR1_SMP23_Pos) /*!< 0x00000400 */\r
+#define ADC_SMPR1_SMP23_2 (0x4UL << ADC_SMPR1_SMP23_Pos) /*!< 0x00000800 */\r
+\r
+#define ADC_SMPR1_SMP24_Pos (12U) \r
+#define ADC_SMPR1_SMP24_Msk (0x7UL << ADC_SMPR1_SMP24_Pos) /*!< 0x00007000 */\r
+#define ADC_SMPR1_SMP24 ADC_SMPR1_SMP24_Msk /*!< ADC channel 24 sampling time selection */\r
+#define ADC_SMPR1_SMP24_0 (0x1UL << ADC_SMPR1_SMP24_Pos) /*!< 0x00001000 */\r
+#define ADC_SMPR1_SMP24_1 (0x2UL << ADC_SMPR1_SMP24_Pos) /*!< 0x00002000 */\r
+#define ADC_SMPR1_SMP24_2 (0x4UL << ADC_SMPR1_SMP24_Pos) /*!< 0x00004000 */\r
+\r
+#define ADC_SMPR1_SMP25_Pos (15U) \r
+#define ADC_SMPR1_SMP25_Msk (0x7UL << ADC_SMPR1_SMP25_Pos) /*!< 0x00038000 */\r
+#define ADC_SMPR1_SMP25 ADC_SMPR1_SMP25_Msk /*!< ADC channel 25 sampling time selection */\r
+#define ADC_SMPR1_SMP25_0 (0x1UL << ADC_SMPR1_SMP25_Pos) /*!< 0x00008000 */\r
+#define ADC_SMPR1_SMP25_1 (0x2UL << ADC_SMPR1_SMP25_Pos) /*!< 0x00010000 */\r
+#define ADC_SMPR1_SMP25_2 (0x4UL << ADC_SMPR1_SMP25_Pos) /*!< 0x00020000 */\r
+\r
+#define ADC_SMPR1_SMP26_Pos (18U) \r
+#define ADC_SMPR1_SMP26_Msk (0x7UL << ADC_SMPR1_SMP26_Pos) /*!< 0x001C0000 */\r
+#define ADC_SMPR1_SMP26 ADC_SMPR1_SMP26_Msk /*!< ADC channel 26 sampling time selection */\r
+#define ADC_SMPR1_SMP26_0 (0x1UL << ADC_SMPR1_SMP26_Pos) /*!< 0x00040000 */\r
+#define ADC_SMPR1_SMP26_1 (0x2UL << ADC_SMPR1_SMP26_Pos) /*!< 0x00080000 */\r
+#define ADC_SMPR1_SMP26_2 (0x4UL << ADC_SMPR1_SMP26_Pos) /*!< 0x00100000 */\r
+\r
+#define ADC_SMPR1_SMP27_Pos (21U) \r
+#define ADC_SMPR1_SMP27_Msk (0x7UL << ADC_SMPR1_SMP27_Pos) /*!< 0x00E00000 */\r
+#define ADC_SMPR1_SMP27 ADC_SMPR1_SMP27_Msk /*!< ADC channel 27 sampling time selection */\r
+#define ADC_SMPR1_SMP27_0 (0x1UL << ADC_SMPR1_SMP27_Pos) /*!< 0x00200000 */\r
+#define ADC_SMPR1_SMP27_1 (0x2UL << ADC_SMPR1_SMP27_Pos) /*!< 0x00400000 */\r
+#define ADC_SMPR1_SMP27_2 (0x4UL << ADC_SMPR1_SMP27_Pos) /*!< 0x00800000 */\r
+\r
+#define ADC_SMPR1_SMP28_Pos (24U) \r
+#define ADC_SMPR1_SMP28_Msk (0x7UL << ADC_SMPR1_SMP28_Pos) /*!< 0x07000000 */\r
+#define ADC_SMPR1_SMP28 ADC_SMPR1_SMP28_Msk /*!< ADC channel 28 sampling time selection */\r
+#define ADC_SMPR1_SMP28_0 (0x1UL << ADC_SMPR1_SMP28_Pos) /*!< 0x01000000 */\r
+#define ADC_SMPR1_SMP28_1 (0x2UL << ADC_SMPR1_SMP28_Pos) /*!< 0x02000000 */\r
+#define ADC_SMPR1_SMP28_2 (0x4UL << ADC_SMPR1_SMP28_Pos) /*!< 0x04000000 */\r
+\r
+#define ADC_SMPR1_SMP29_Pos (27U) \r
+#define ADC_SMPR1_SMP29_Msk (0x7UL << ADC_SMPR1_SMP29_Pos) /*!< 0x38000000 */\r
+#define ADC_SMPR1_SMP29 ADC_SMPR1_SMP29_Msk /*!< ADC channel 29 sampling time selection */\r
+#define ADC_SMPR1_SMP29_0 (0x1UL << ADC_SMPR1_SMP29_Pos) /*!< 0x08000000 */\r
+#define ADC_SMPR1_SMP29_1 (0x2UL << ADC_SMPR1_SMP29_Pos) /*!< 0x10000000 */\r
+#define ADC_SMPR1_SMP29_2 (0x4UL << ADC_SMPR1_SMP29_Pos) /*!< 0x20000000 */\r
+\r
+/****************** Bit definition for ADC_SMPR2 register *******************/\r
+#define ADC_SMPR2_SMP10_Pos (0U) \r
+#define ADC_SMPR2_SMP10_Msk (0x7UL << ADC_SMPR2_SMP10_Pos) /*!< 0x00000007 */\r
+#define ADC_SMPR2_SMP10 ADC_SMPR2_SMP10_Msk /*!< ADC channel 10 sampling time selection */\r
+#define ADC_SMPR2_SMP10_0 (0x1UL << ADC_SMPR2_SMP10_Pos) /*!< 0x00000001 */\r
+#define ADC_SMPR2_SMP10_1 (0x2UL << ADC_SMPR2_SMP10_Pos) /*!< 0x00000002 */\r
+#define ADC_SMPR2_SMP10_2 (0x4UL << ADC_SMPR2_SMP10_Pos) /*!< 0x00000004 */\r
+\r
+#define ADC_SMPR2_SMP11_Pos (3U) \r
+#define ADC_SMPR2_SMP11_Msk (0x7UL << ADC_SMPR2_SMP11_Pos) /*!< 0x00000038 */\r
+#define ADC_SMPR2_SMP11 ADC_SMPR2_SMP11_Msk /*!< ADC channel 11 sampling time selection */\r
+#define ADC_SMPR2_SMP11_0 (0x1UL << ADC_SMPR2_SMP11_Pos) /*!< 0x00000008 */\r
+#define ADC_SMPR2_SMP11_1 (0x2UL << ADC_SMPR2_SMP11_Pos) /*!< 0x00000010 */\r
+#define ADC_SMPR2_SMP11_2 (0x4UL << ADC_SMPR2_SMP11_Pos) /*!< 0x00000020 */\r
+\r
+#define ADC_SMPR2_SMP12_Pos (6U) \r
+#define ADC_SMPR2_SMP12_Msk (0x7UL << ADC_SMPR2_SMP12_Pos) /*!< 0x000001C0 */\r
+#define ADC_SMPR2_SMP12 ADC_SMPR2_SMP12_Msk /*!< ADC channel 12 sampling time selection */\r
+#define ADC_SMPR2_SMP12_0 (0x1UL << ADC_SMPR2_SMP12_Pos) /*!< 0x00000040 */\r
+#define ADC_SMPR2_SMP12_1 (0x2UL << ADC_SMPR2_SMP12_Pos) /*!< 0x00000080 */\r
+#define ADC_SMPR2_SMP12_2 (0x4UL << ADC_SMPR2_SMP12_Pos) /*!< 0x00000100 */\r
+\r
+#define ADC_SMPR2_SMP13_Pos (9U) \r
+#define ADC_SMPR2_SMP13_Msk (0x7UL << ADC_SMPR2_SMP13_Pos) /*!< 0x00000E00 */\r
+#define ADC_SMPR2_SMP13 ADC_SMPR2_SMP13_Msk /*!< ADC channel 13 sampling time selection */\r
+#define ADC_SMPR2_SMP13_0 (0x1UL << ADC_SMPR2_SMP13_Pos) /*!< 0x00000200 */\r
+#define ADC_SMPR2_SMP13_1 (0x2UL << ADC_SMPR2_SMP13_Pos) /*!< 0x00000400 */\r
+#define ADC_SMPR2_SMP13_2 (0x4UL << ADC_SMPR2_SMP13_Pos) /*!< 0x00000800 */\r
+\r
+#define ADC_SMPR2_SMP14_Pos (12U) \r
+#define ADC_SMPR2_SMP14_Msk (0x7UL << ADC_SMPR2_SMP14_Pos) /*!< 0x00007000 */\r
+#define ADC_SMPR2_SMP14 ADC_SMPR2_SMP14_Msk /*!< ADC channel 14 sampling time selection */\r
+#define ADC_SMPR2_SMP14_0 (0x1UL << ADC_SMPR2_SMP14_Pos) /*!< 0x00001000 */\r
+#define ADC_SMPR2_SMP14_1 (0x2UL << ADC_SMPR2_SMP14_Pos) /*!< 0x00002000 */\r
+#define ADC_SMPR2_SMP14_2 (0x4UL << ADC_SMPR2_SMP14_Pos) /*!< 0x00004000 */\r
+\r
+#define ADC_SMPR2_SMP15_Pos (15U) \r
+#define ADC_SMPR2_SMP15_Msk (0x7UL << ADC_SMPR2_SMP15_Pos) /*!< 0x00038000 */\r
+#define ADC_SMPR2_SMP15 ADC_SMPR2_SMP15_Msk /*!< ADC channel 5 sampling time selection */\r
+#define ADC_SMPR2_SMP15_0 (0x1UL << ADC_SMPR2_SMP15_Pos) /*!< 0x00008000 */\r
+#define ADC_SMPR2_SMP15_1 (0x2UL << ADC_SMPR2_SMP15_Pos) /*!< 0x00010000 */\r
+#define ADC_SMPR2_SMP15_2 (0x4UL << ADC_SMPR2_SMP15_Pos) /*!< 0x00020000 */\r
+\r
+#define ADC_SMPR2_SMP16_Pos (18U) \r
+#define ADC_SMPR2_SMP16_Msk (0x7UL << ADC_SMPR2_SMP16_Pos) /*!< 0x001C0000 */\r
+#define ADC_SMPR2_SMP16 ADC_SMPR2_SMP16_Msk /*!< ADC channel 16 sampling time selection */\r
+#define ADC_SMPR2_SMP16_0 (0x1UL << ADC_SMPR2_SMP16_Pos) /*!< 0x00040000 */\r
+#define ADC_SMPR2_SMP16_1 (0x2UL << ADC_SMPR2_SMP16_Pos) /*!< 0x00080000 */\r
+#define ADC_SMPR2_SMP16_2 (0x4UL << ADC_SMPR2_SMP16_Pos) /*!< 0x00100000 */\r
+\r
+#define ADC_SMPR2_SMP17_Pos (21U) \r
+#define ADC_SMPR2_SMP17_Msk (0x7UL << ADC_SMPR2_SMP17_Pos) /*!< 0x00E00000 */\r
+#define ADC_SMPR2_SMP17 ADC_SMPR2_SMP17_Msk /*!< ADC channel 17 sampling time selection */\r
+#define ADC_SMPR2_SMP17_0 (0x1UL << ADC_SMPR2_SMP17_Pos) /*!< 0x00200000 */\r
+#define ADC_SMPR2_SMP17_1 (0x2UL << ADC_SMPR2_SMP17_Pos) /*!< 0x00400000 */\r
+#define ADC_SMPR2_SMP17_2 (0x4UL << ADC_SMPR2_SMP17_Pos) /*!< 0x00800000 */\r
+\r
+#define ADC_SMPR2_SMP18_Pos (24U) \r
+#define ADC_SMPR2_SMP18_Msk (0x7UL << ADC_SMPR2_SMP18_Pos) /*!< 0x07000000 */\r
+#define ADC_SMPR2_SMP18 ADC_SMPR2_SMP18_Msk /*!< ADC channel 18 sampling time selection */\r
+#define ADC_SMPR2_SMP18_0 (0x1UL << ADC_SMPR2_SMP18_Pos) /*!< 0x01000000 */\r
+#define ADC_SMPR2_SMP18_1 (0x2UL << ADC_SMPR2_SMP18_Pos) /*!< 0x02000000 */\r
+#define ADC_SMPR2_SMP18_2 (0x4UL << ADC_SMPR2_SMP18_Pos) /*!< 0x04000000 */\r
+\r
+#define ADC_SMPR2_SMP19_Pos (27U) \r
+#define ADC_SMPR2_SMP19_Msk (0x7UL << ADC_SMPR2_SMP19_Pos) /*!< 0x38000000 */\r
+#define ADC_SMPR2_SMP19 ADC_SMPR2_SMP19_Msk /*!< ADC channel 19 sampling time selection */\r
+#define ADC_SMPR2_SMP19_0 (0x1UL << ADC_SMPR2_SMP19_Pos) /*!< 0x08000000 */\r
+#define ADC_SMPR2_SMP19_1 (0x2UL << ADC_SMPR2_SMP19_Pos) /*!< 0x10000000 */\r
+#define ADC_SMPR2_SMP19_2 (0x4UL << ADC_SMPR2_SMP19_Pos) /*!< 0x20000000 */\r
+\r
+/****************** Bit definition for ADC_SMPR3 register *******************/\r
+#define ADC_SMPR3_SMP0_Pos (0U) \r
+#define ADC_SMPR3_SMP0_Msk (0x7UL << ADC_SMPR3_SMP0_Pos) /*!< 0x00000007 */\r
+#define ADC_SMPR3_SMP0 ADC_SMPR3_SMP0_Msk /*!< ADC channel 0 sampling time selection */\r
+#define ADC_SMPR3_SMP0_0 (0x1UL << ADC_SMPR3_SMP0_Pos) /*!< 0x00000001 */\r
+#define ADC_SMPR3_SMP0_1 (0x2UL << ADC_SMPR3_SMP0_Pos) /*!< 0x00000002 */\r
+#define ADC_SMPR3_SMP0_2 (0x4UL << ADC_SMPR3_SMP0_Pos) /*!< 0x00000004 */\r
+ \r
+#define ADC_SMPR3_SMP1_Pos (3U) \r
+#define ADC_SMPR3_SMP1_Msk (0x7UL << ADC_SMPR3_SMP1_Pos) /*!< 0x00000038 */\r
+#define ADC_SMPR3_SMP1 ADC_SMPR3_SMP1_Msk /*!< ADC channel 1 sampling time selection */\r
+#define ADC_SMPR3_SMP1_0 (0x1UL << ADC_SMPR3_SMP1_Pos) /*!< 0x00000008 */\r
+#define ADC_SMPR3_SMP1_1 (0x2UL << ADC_SMPR3_SMP1_Pos) /*!< 0x00000010 */\r
+#define ADC_SMPR3_SMP1_2 (0x4UL << ADC_SMPR3_SMP1_Pos) /*!< 0x00000020 */\r
+\r
+#define ADC_SMPR3_SMP2_Pos (6U) \r
+#define ADC_SMPR3_SMP2_Msk (0x7UL << ADC_SMPR3_SMP2_Pos) /*!< 0x000001C0 */\r
+#define ADC_SMPR3_SMP2 ADC_SMPR3_SMP2_Msk /*!< ADC channel 2 sampling time selection */\r
+#define ADC_SMPR3_SMP2_0 (0x1UL << ADC_SMPR3_SMP2_Pos) /*!< 0x00000040 */\r
+#define ADC_SMPR3_SMP2_1 (0x2UL << ADC_SMPR3_SMP2_Pos) /*!< 0x00000080 */\r
+#define ADC_SMPR3_SMP2_2 (0x4UL << ADC_SMPR3_SMP2_Pos) /*!< 0x00000100 */\r
+\r
+#define ADC_SMPR3_SMP3_Pos (9U) \r
+#define ADC_SMPR3_SMP3_Msk (0x7UL << ADC_SMPR3_SMP3_Pos) /*!< 0x00000E00 */\r
+#define ADC_SMPR3_SMP3 ADC_SMPR3_SMP3_Msk /*!< ADC channel 3 sampling time selection */\r
+#define ADC_SMPR3_SMP3_0 (0x1UL << ADC_SMPR3_SMP3_Pos) /*!< 0x00000200 */\r
+#define ADC_SMPR3_SMP3_1 (0x2UL << ADC_SMPR3_SMP3_Pos) /*!< 0x00000400 */\r
+#define ADC_SMPR3_SMP3_2 (0x4UL << ADC_SMPR3_SMP3_Pos) /*!< 0x00000800 */\r
+\r
+#define ADC_SMPR3_SMP4_Pos (12U) \r
+#define ADC_SMPR3_SMP4_Msk (0x7UL << ADC_SMPR3_SMP4_Pos) /*!< 0x00007000 */\r
+#define ADC_SMPR3_SMP4 ADC_SMPR3_SMP4_Msk /*!< ADC channel 4 sampling time selection */\r
+#define ADC_SMPR3_SMP4_0 (0x1UL << ADC_SMPR3_SMP4_Pos) /*!< 0x00001000 */\r
+#define ADC_SMPR3_SMP4_1 (0x2UL << ADC_SMPR3_SMP4_Pos) /*!< 0x00002000 */\r
+#define ADC_SMPR3_SMP4_2 (0x4UL << ADC_SMPR3_SMP4_Pos) /*!< 0x00004000 */\r
+\r
+#define ADC_SMPR3_SMP5_Pos (15U) \r
+#define ADC_SMPR3_SMP5_Msk (0x7UL << ADC_SMPR3_SMP5_Pos) /*!< 0x00038000 */\r
+#define ADC_SMPR3_SMP5 ADC_SMPR3_SMP5_Msk /*!< ADC channel 5 sampling time selection */\r
+#define ADC_SMPR3_SMP5_0 (0x1UL << ADC_SMPR3_SMP5_Pos) /*!< 0x00008000 */\r
+#define ADC_SMPR3_SMP5_1 (0x2UL << ADC_SMPR3_SMP5_Pos) /*!< 0x00010000 */\r
+#define ADC_SMPR3_SMP5_2 (0x4UL << ADC_SMPR3_SMP5_Pos) /*!< 0x00020000 */\r
+\r
+#define ADC_SMPR3_SMP6_Pos (18U) \r
+#define ADC_SMPR3_SMP6_Msk (0x7UL << ADC_SMPR3_SMP6_Pos) /*!< 0x001C0000 */\r
+#define ADC_SMPR3_SMP6 ADC_SMPR3_SMP6_Msk /*!< ADC channel 6 sampling time selection */\r
+#define ADC_SMPR3_SMP6_0 (0x1UL << ADC_SMPR3_SMP6_Pos) /*!< 0x00040000 */\r
+#define ADC_SMPR3_SMP6_1 (0x2UL << ADC_SMPR3_SMP6_Pos) /*!< 0x00080000 */\r
+#define ADC_SMPR3_SMP6_2 (0x4UL << ADC_SMPR3_SMP6_Pos) /*!< 0x00100000 */\r
+\r
+#define ADC_SMPR3_SMP7_Pos (21U) \r
+#define ADC_SMPR3_SMP7_Msk (0x7UL << ADC_SMPR3_SMP7_Pos) /*!< 0x00E00000 */\r
+#define ADC_SMPR3_SMP7 ADC_SMPR3_SMP7_Msk /*!< ADC channel 7 sampling time selection */\r
+#define ADC_SMPR3_SMP7_0 (0x1UL << ADC_SMPR3_SMP7_Pos) /*!< 0x00200000 */\r
+#define ADC_SMPR3_SMP7_1 (0x2UL << ADC_SMPR3_SMP7_Pos) /*!< 0x00400000 */\r
+#define ADC_SMPR3_SMP7_2 (0x4UL << ADC_SMPR3_SMP7_Pos) /*!< 0x00800000 */\r
+\r
+#define ADC_SMPR3_SMP8_Pos (24U) \r
+#define ADC_SMPR3_SMP8_Msk (0x7UL << ADC_SMPR3_SMP8_Pos) /*!< 0x07000000 */\r
+#define ADC_SMPR3_SMP8 ADC_SMPR3_SMP8_Msk /*!< ADC channel 8 sampling time selection */\r
+#define ADC_SMPR3_SMP8_0 (0x1UL << ADC_SMPR3_SMP8_Pos) /*!< 0x01000000 */\r
+#define ADC_SMPR3_SMP8_1 (0x2UL << ADC_SMPR3_SMP8_Pos) /*!< 0x02000000 */\r
+#define ADC_SMPR3_SMP8_2 (0x4UL << ADC_SMPR3_SMP8_Pos) /*!< 0x04000000 */\r
+\r
+#define ADC_SMPR3_SMP9_Pos (27U) \r
+#define ADC_SMPR3_SMP9_Msk (0x7UL << ADC_SMPR3_SMP9_Pos) /*!< 0x38000000 */\r
+#define ADC_SMPR3_SMP9 ADC_SMPR3_SMP9_Msk /*!< ADC channel 9 sampling time selection */\r
+#define ADC_SMPR3_SMP9_0 (0x1UL << ADC_SMPR3_SMP9_Pos) /*!< 0x08000000 */\r
+#define ADC_SMPR3_SMP9_1 (0x2UL << ADC_SMPR3_SMP9_Pos) /*!< 0x10000000 */\r
+#define ADC_SMPR3_SMP9_2 (0x4UL << ADC_SMPR3_SMP9_Pos) /*!< 0x20000000 */\r
+\r
+/****************** Bit definition for ADC_JOFR1 register *******************/\r
+#define ADC_JOFR1_JOFFSET1_Pos (0U) \r
+#define ADC_JOFR1_JOFFSET1_Msk (0xFFFUL << ADC_JOFR1_JOFFSET1_Pos) /*!< 0x00000FFF */\r
+#define ADC_JOFR1_JOFFSET1 ADC_JOFR1_JOFFSET1_Msk /*!< ADC group injected sequencer rank 1 offset value */\r
+\r
+/****************** Bit definition for ADC_JOFR2 register *******************/\r
+#define ADC_JOFR2_JOFFSET2_Pos (0U) \r
+#define ADC_JOFR2_JOFFSET2_Msk (0xFFFUL << ADC_JOFR2_JOFFSET2_Pos) /*!< 0x00000FFF */\r
+#define ADC_JOFR2_JOFFSET2 ADC_JOFR2_JOFFSET2_Msk /*!< ADC group injected sequencer rank 2 offset value */\r
+\r
+/****************** Bit definition for ADC_JOFR3 register *******************/\r
+#define ADC_JOFR3_JOFFSET3_Pos (0U) \r
+#define ADC_JOFR3_JOFFSET3_Msk (0xFFFUL << ADC_JOFR3_JOFFSET3_Pos) /*!< 0x00000FFF */\r
+#define ADC_JOFR3_JOFFSET3 ADC_JOFR3_JOFFSET3_Msk /*!< ADC group injected sequencer rank 3 offset value */\r
+\r
+/****************** Bit definition for ADC_JOFR4 register *******************/\r
+#define ADC_JOFR4_JOFFSET4_Pos (0U) \r
+#define ADC_JOFR4_JOFFSET4_Msk (0xFFFUL << ADC_JOFR4_JOFFSET4_Pos) /*!< 0x00000FFF */\r
+#define ADC_JOFR4_JOFFSET4 ADC_JOFR4_JOFFSET4_Msk /*!< ADC group injected sequencer rank 4 offset value */\r
+\r
+/******************* Bit definition for ADC_HTR register ********************/\r
+#define ADC_HTR_HT_Pos (0U) \r
+#define ADC_HTR_HT_Msk (0xFFFUL << ADC_HTR_HT_Pos) /*!< 0x00000FFF */\r
+#define ADC_HTR_HT ADC_HTR_HT_Msk /*!< ADC analog watchdog 1 threshold high */\r
+\r
+/******************* Bit definition for ADC_LTR register ********************/\r
+#define ADC_LTR_LT_Pos (0U) \r
+#define ADC_LTR_LT_Msk (0xFFFUL << ADC_LTR_LT_Pos) /*!< 0x00000FFF */\r
+#define ADC_LTR_LT ADC_LTR_LT_Msk /*!< ADC analog watchdog 1 threshold low */\r
+\r
+/******************* Bit definition for ADC_SQR1 register *******************/\r
+#define ADC_SQR1_L_Pos (20U) \r
+#define ADC_SQR1_L_Msk (0x1FUL << ADC_SQR1_L_Pos) /*!< 0x01F00000 */\r
+#define ADC_SQR1_L ADC_SQR1_L_Msk /*!< ADC group regular sequencer scan length */\r
+#define ADC_SQR1_L_0 (0x01UL << ADC_SQR1_L_Pos) /*!< 0x00100000 */\r
+#define ADC_SQR1_L_1 (0x02UL << ADC_SQR1_L_Pos) /*!< 0x00200000 */\r
+#define ADC_SQR1_L_2 (0x04UL << ADC_SQR1_L_Pos) /*!< 0x00400000 */\r
+#define ADC_SQR1_L_3 (0x08UL << ADC_SQR1_L_Pos) /*!< 0x00800000 */\r
+#define ADC_SQR1_L_4 (0x10UL << ADC_SQR1_L_Pos) /*!< 0x01000000 */\r
+\r
+#define ADC_SQR1_SQ28_Pos (15U) \r
+#define ADC_SQR1_SQ28_Msk (0x1FUL << ADC_SQR1_SQ28_Pos) /*!< 0x000F8000 */\r
+#define ADC_SQR1_SQ28 ADC_SQR1_SQ28_Msk /*!< ADC group regular sequencer rank 28 */\r
+#define ADC_SQR1_SQ28_0 (0x01UL << ADC_SQR1_SQ28_Pos) /*!< 0x00008000 */\r
+#define ADC_SQR1_SQ28_1 (0x02UL << ADC_SQR1_SQ28_Pos) /*!< 0x00010000 */\r
+#define ADC_SQR1_SQ28_2 (0x04UL << ADC_SQR1_SQ28_Pos) /*!< 0x00020000 */\r
+#define ADC_SQR1_SQ28_3 (0x08UL << ADC_SQR1_SQ28_Pos) /*!< 0x00040000 */\r
+#define ADC_SQR1_SQ28_4 (0x10UL << ADC_SQR1_SQ28_Pos) /*!< 0x00080000 */\r
+\r
+#define ADC_SQR1_SQ27_Pos (10U) \r
+#define ADC_SQR1_SQ27_Msk (0x1FUL << ADC_SQR1_SQ27_Pos) /*!< 0x00007C00 */\r
+#define ADC_SQR1_SQ27 ADC_SQR1_SQ27_Msk /*!< ADC group regular sequencer rank 27 */\r
+#define ADC_SQR1_SQ27_0 (0x01UL << ADC_SQR1_SQ27_Pos) /*!< 0x00000400 */\r
+#define ADC_SQR1_SQ27_1 (0x02UL << ADC_SQR1_SQ27_Pos) /*!< 0x00000800 */\r
+#define ADC_SQR1_SQ27_2 (0x04UL << ADC_SQR1_SQ27_Pos) /*!< 0x00001000 */\r
+#define ADC_SQR1_SQ27_3 (0x08UL << ADC_SQR1_SQ27_Pos) /*!< 0x00002000 */\r
+#define ADC_SQR1_SQ27_4 (0x10UL << ADC_SQR1_SQ27_Pos) /*!< 0x00004000 */\r
+\r
+#define ADC_SQR1_SQ26_Pos (5U) \r
+#define ADC_SQR1_SQ26_Msk (0x1FUL << ADC_SQR1_SQ26_Pos) /*!< 0x000003E0 */\r
+#define ADC_SQR1_SQ26 ADC_SQR1_SQ26_Msk /*!< ADC group regular sequencer rank 26 */\r
+#define ADC_SQR1_SQ26_0 (0x01UL << ADC_SQR1_SQ26_Pos) /*!< 0x00000020 */\r
+#define ADC_SQR1_SQ26_1 (0x02UL << ADC_SQR1_SQ26_Pos) /*!< 0x00000040 */\r
+#define ADC_SQR1_SQ26_2 (0x04UL << ADC_SQR1_SQ26_Pos) /*!< 0x00000080 */\r
+#define ADC_SQR1_SQ26_3 (0x08UL << ADC_SQR1_SQ26_Pos) /*!< 0x00000100 */\r
+#define ADC_SQR1_SQ26_4 (0x10UL << ADC_SQR1_SQ26_Pos) /*!< 0x00000200 */\r
+\r
+#define ADC_SQR1_SQ25_Pos (0U) \r
+#define ADC_SQR1_SQ25_Msk (0x1FUL << ADC_SQR1_SQ25_Pos) /*!< 0x0000001F */\r
+#define ADC_SQR1_SQ25 ADC_SQR1_SQ25_Msk /*!< ADC group regular sequencer rank 25 */\r
+#define ADC_SQR1_SQ25_0 (0x01UL << ADC_SQR1_SQ25_Pos) /*!< 0x00000001 */\r
+#define ADC_SQR1_SQ25_1 (0x02UL << ADC_SQR1_SQ25_Pos) /*!< 0x00000002 */\r
+#define ADC_SQR1_SQ25_2 (0x04UL << ADC_SQR1_SQ25_Pos) /*!< 0x00000004 */\r
+#define ADC_SQR1_SQ25_3 (0x08UL << ADC_SQR1_SQ25_Pos) /*!< 0x00000008 */\r
+#define ADC_SQR1_SQ25_4 (0x10UL << ADC_SQR1_SQ25_Pos) /*!< 0x00000010 */\r
+\r
+/******************* Bit definition for ADC_SQR2 register *******************/\r
+#define ADC_SQR2_SQ19_Pos (0U) \r
+#define ADC_SQR2_SQ19_Msk (0x1FUL << ADC_SQR2_SQ19_Pos) /*!< 0x0000001F */\r
+#define ADC_SQR2_SQ19 ADC_SQR2_SQ19_Msk /*!< ADC group regular sequencer rank 19 */\r
+#define ADC_SQR2_SQ19_0 (0x01UL << ADC_SQR2_SQ19_Pos) /*!< 0x00000001 */\r
+#define ADC_SQR2_SQ19_1 (0x02UL << ADC_SQR2_SQ19_Pos) /*!< 0x00000002 */\r
+#define ADC_SQR2_SQ19_2 (0x04UL << ADC_SQR2_SQ19_Pos) /*!< 0x00000004 */\r
+#define ADC_SQR2_SQ19_3 (0x08UL << ADC_SQR2_SQ19_Pos) /*!< 0x00000008 */\r
+#define ADC_SQR2_SQ19_4 (0x10UL << ADC_SQR2_SQ19_Pos) /*!< 0x00000010 */\r
+\r
+#define ADC_SQR2_SQ20_Pos (5U) \r
+#define ADC_SQR2_SQ20_Msk (0x1FUL << ADC_SQR2_SQ20_Pos) /*!< 0x000003E0 */\r
+#define ADC_SQR2_SQ20 ADC_SQR2_SQ20_Msk /*!< ADC group regular sequencer rank 20 */\r
+#define ADC_SQR2_SQ20_0 (0x01UL << ADC_SQR2_SQ20_Pos) /*!< 0x00000020 */\r
+#define ADC_SQR2_SQ20_1 (0x02UL << ADC_SQR2_SQ20_Pos) /*!< 0x00000040 */\r
+#define ADC_SQR2_SQ20_2 (0x04UL << ADC_SQR2_SQ20_Pos) /*!< 0x00000080 */\r
+#define ADC_SQR2_SQ20_3 (0x08UL << ADC_SQR2_SQ20_Pos) /*!< 0x00000100 */\r
+#define ADC_SQR2_SQ20_4 (0x10UL << ADC_SQR2_SQ20_Pos) /*!< 0x00000200 */\r
+\r
+#define ADC_SQR2_SQ21_Pos (10U) \r
+#define ADC_SQR2_SQ21_Msk (0x1FUL << ADC_SQR2_SQ21_Pos) /*!< 0x00007C00 */\r
+#define ADC_SQR2_SQ21 ADC_SQR2_SQ21_Msk /*!< ADC group regular sequencer rank 21 */\r
+#define ADC_SQR2_SQ21_0 (0x01UL << ADC_SQR2_SQ21_Pos) /*!< 0x00000400 */\r
+#define ADC_SQR2_SQ21_1 (0x02UL << ADC_SQR2_SQ21_Pos) /*!< 0x00000800 */\r
+#define ADC_SQR2_SQ21_2 (0x04UL << ADC_SQR2_SQ21_Pos) /*!< 0x00001000 */\r
+#define ADC_SQR2_SQ21_3 (0x08UL << ADC_SQR2_SQ21_Pos) /*!< 0x00002000 */\r
+#define ADC_SQR2_SQ21_4 (0x10UL << ADC_SQR2_SQ21_Pos) /*!< 0x00004000 */\r
+\r
+#define ADC_SQR2_SQ22_Pos (15U) \r
+#define ADC_SQR2_SQ22_Msk (0x1FUL << ADC_SQR2_SQ22_Pos) /*!< 0x000F8000 */\r
+#define ADC_SQR2_SQ22 ADC_SQR2_SQ22_Msk /*!< ADC group regular sequencer rank 22 */\r
+#define ADC_SQR2_SQ22_0 (0x01UL << ADC_SQR2_SQ22_Pos) /*!< 0x00008000 */\r
+#define ADC_SQR2_SQ22_1 (0x02UL << ADC_SQR2_SQ22_Pos) /*!< 0x00010000 */\r
+#define ADC_SQR2_SQ22_2 (0x04UL << ADC_SQR2_SQ22_Pos) /*!< 0x00020000 */\r
+#define ADC_SQR2_SQ22_3 (0x08UL << ADC_SQR2_SQ22_Pos) /*!< 0x00040000 */\r
+#define ADC_SQR2_SQ22_4 (0x10UL << ADC_SQR2_SQ22_Pos) /*!< 0x00080000 */\r
+\r
+#define ADC_SQR2_SQ23_Pos (20U) \r
+#define ADC_SQR2_SQ23_Msk (0x1FUL << ADC_SQR2_SQ23_Pos) /*!< 0x01F00000 */\r
+#define ADC_SQR2_SQ23 ADC_SQR2_SQ23_Msk /*!< ADC group regular sequencer rank 23 */\r
+#define ADC_SQR2_SQ23_0 (0x01UL << ADC_SQR2_SQ23_Pos) /*!< 0x00100000 */\r
+#define ADC_SQR2_SQ23_1 (0x02UL << ADC_SQR2_SQ23_Pos) /*!< 0x00200000 */\r
+#define ADC_SQR2_SQ23_2 (0x04UL << ADC_SQR2_SQ23_Pos) /*!< 0x00400000 */\r
+#define ADC_SQR2_SQ23_3 (0x08UL << ADC_SQR2_SQ23_Pos) /*!< 0x00800000 */\r
+#define ADC_SQR2_SQ23_4 (0x10UL << ADC_SQR2_SQ23_Pos) /*!< 0x01000000 */\r
+\r
+#define ADC_SQR2_SQ24_Pos (25U) \r
+#define ADC_SQR2_SQ24_Msk (0x1FUL << ADC_SQR2_SQ24_Pos) /*!< 0x3E000000 */\r
+#define ADC_SQR2_SQ24 ADC_SQR2_SQ24_Msk /*!< ADC group regular sequencer rank 24 */\r
+#define ADC_SQR2_SQ24_0 (0x01UL << ADC_SQR2_SQ24_Pos) /*!< 0x02000000 */\r
+#define ADC_SQR2_SQ24_1 (0x02UL << ADC_SQR2_SQ24_Pos) /*!< 0x04000000 */\r
+#define ADC_SQR2_SQ24_2 (0x04UL << ADC_SQR2_SQ24_Pos) /*!< 0x08000000 */\r
+#define ADC_SQR2_SQ24_3 (0x08UL << ADC_SQR2_SQ24_Pos) /*!< 0x10000000 */\r
+#define ADC_SQR2_SQ24_4 (0x10UL << ADC_SQR2_SQ24_Pos) /*!< 0x20000000 */\r
+\r
+/******************* Bit definition for ADC_SQR3 register *******************/\r
+#define ADC_SQR3_SQ13_Pos (0U) \r
+#define ADC_SQR3_SQ13_Msk (0x1FUL << ADC_SQR3_SQ13_Pos) /*!< 0x0000001F */\r
+#define ADC_SQR3_SQ13 ADC_SQR3_SQ13_Msk /*!< ADC group regular sequencer rank 13 */\r
+#define ADC_SQR3_SQ13_0 (0x01UL << ADC_SQR3_SQ13_Pos) /*!< 0x00000001 */\r
+#define ADC_SQR3_SQ13_1 (0x02UL << ADC_SQR3_SQ13_Pos) /*!< 0x00000002 */\r
+#define ADC_SQR3_SQ13_2 (0x04UL << ADC_SQR3_SQ13_Pos) /*!< 0x00000004 */\r
+#define ADC_SQR3_SQ13_3 (0x08UL << ADC_SQR3_SQ13_Pos) /*!< 0x00000008 */\r
+#define ADC_SQR3_SQ13_4 (0x10UL << ADC_SQR3_SQ13_Pos) /*!< 0x00000010 */\r
+\r
+#define ADC_SQR3_SQ14_Pos (5U) \r
+#define ADC_SQR3_SQ14_Msk (0x1FUL << ADC_SQR3_SQ14_Pos) /*!< 0x000003E0 */\r
+#define ADC_SQR3_SQ14 ADC_SQR3_SQ14_Msk /*!< ADC group regular sequencer rank 14 */\r
+#define ADC_SQR3_SQ14_0 (0x01UL << ADC_SQR3_SQ14_Pos) /*!< 0x00000020 */\r
+#define ADC_SQR3_SQ14_1 (0x02UL << ADC_SQR3_SQ14_Pos) /*!< 0x00000040 */\r
+#define ADC_SQR3_SQ14_2 (0x04UL << ADC_SQR3_SQ14_Pos) /*!< 0x00000080 */\r
+#define ADC_SQR3_SQ14_3 (0x08UL << ADC_SQR3_SQ14_Pos) /*!< 0x00000100 */\r
+#define ADC_SQR3_SQ14_4 (0x10UL << ADC_SQR3_SQ14_Pos) /*!< 0x00000200 */\r
+\r
+#define ADC_SQR3_SQ15_Pos (10U) \r
+#define ADC_SQR3_SQ15_Msk (0x1FUL << ADC_SQR3_SQ15_Pos) /*!< 0x00007C00 */\r
+#define ADC_SQR3_SQ15 ADC_SQR3_SQ15_Msk /*!< ADC group regular sequencer rank 15 */\r
+#define ADC_SQR3_SQ15_0 (0x01UL << ADC_SQR3_SQ15_Pos) /*!< 0x00000400 */\r
+#define ADC_SQR3_SQ15_1 (0x02UL << ADC_SQR3_SQ15_Pos) /*!< 0x00000800 */\r
+#define ADC_SQR3_SQ15_2 (0x04UL << ADC_SQR3_SQ15_Pos) /*!< 0x00001000 */\r
+#define ADC_SQR3_SQ15_3 (0x08UL << ADC_SQR3_SQ15_Pos) /*!< 0x00002000 */\r
+#define ADC_SQR3_SQ15_4 (0x10UL << ADC_SQR3_SQ15_Pos) /*!< 0x00004000 */\r
+\r
+#define ADC_SQR3_SQ16_Pos (15U) \r
+#define ADC_SQR3_SQ16_Msk (0x1FUL << ADC_SQR3_SQ16_Pos) /*!< 0x000F8000 */\r
+#define ADC_SQR3_SQ16 ADC_SQR3_SQ16_Msk /*!< ADC group regular sequencer rank 16 */\r
+#define ADC_SQR3_SQ16_0 (0x01UL << ADC_SQR3_SQ16_Pos) /*!< 0x00008000 */\r
+#define ADC_SQR3_SQ16_1 (0x02UL << ADC_SQR3_SQ16_Pos) /*!< 0x00010000 */\r
+#define ADC_SQR3_SQ16_2 (0x04UL << ADC_SQR3_SQ16_Pos) /*!< 0x00020000 */\r
+#define ADC_SQR3_SQ16_3 (0x08UL << ADC_SQR3_SQ16_Pos) /*!< 0x00040000 */\r
+#define ADC_SQR3_SQ16_4 (0x10UL << ADC_SQR3_SQ16_Pos) /*!< 0x00080000 */\r
+\r
+#define ADC_SQR3_SQ17_Pos (20U) \r
+#define ADC_SQR3_SQ17_Msk (0x1FUL << ADC_SQR3_SQ17_Pos) /*!< 0x01F00000 */\r
+#define ADC_SQR3_SQ17 ADC_SQR3_SQ17_Msk /*!< ADC group regular sequencer rank 17 */\r
+#define ADC_SQR3_SQ17_0 (0x01UL << ADC_SQR3_SQ17_Pos) /*!< 0x00100000 */\r
+#define ADC_SQR3_SQ17_1 (0x02UL << ADC_SQR3_SQ17_Pos) /*!< 0x00200000 */\r
+#define ADC_SQR3_SQ17_2 (0x04UL << ADC_SQR3_SQ17_Pos) /*!< 0x00400000 */\r
+#define ADC_SQR3_SQ17_3 (0x08UL << ADC_SQR3_SQ17_Pos) /*!< 0x00800000 */\r
+#define ADC_SQR3_SQ17_4 (0x10UL << ADC_SQR3_SQ17_Pos) /*!< 0x01000000 */\r
+\r
+#define ADC_SQR3_SQ18_Pos (25U) \r
+#define ADC_SQR3_SQ18_Msk (0x1FUL << ADC_SQR3_SQ18_Pos) /*!< 0x3E000000 */\r
+#define ADC_SQR3_SQ18 ADC_SQR3_SQ18_Msk /*!< ADC group regular sequencer rank 18 */\r
+#define ADC_SQR3_SQ18_0 (0x01UL << ADC_SQR3_SQ18_Pos) /*!< 0x02000000 */\r
+#define ADC_SQR3_SQ18_1 (0x02UL << ADC_SQR3_SQ18_Pos) /*!< 0x04000000 */\r
+#define ADC_SQR3_SQ18_2 (0x04UL << ADC_SQR3_SQ18_Pos) /*!< 0x08000000 */\r
+#define ADC_SQR3_SQ18_3 (0x08UL << ADC_SQR3_SQ18_Pos) /*!< 0x10000000 */\r
+#define ADC_SQR3_SQ18_4 (0x10UL << ADC_SQR3_SQ18_Pos) /*!< 0x20000000 */\r
+\r
+/******************* Bit definition for ADC_SQR4 register *******************/\r
+#define ADC_SQR4_SQ7_Pos (0U) \r
+#define ADC_SQR4_SQ7_Msk (0x1FUL << ADC_SQR4_SQ7_Pos) /*!< 0x0000001F */\r
+#define ADC_SQR4_SQ7 ADC_SQR4_SQ7_Msk /*!< ADC group regular sequencer rank 7 */\r
+#define ADC_SQR4_SQ7_0 (0x01UL << ADC_SQR4_SQ7_Pos) /*!< 0x00000001 */\r
+#define ADC_SQR4_SQ7_1 (0x02UL << ADC_SQR4_SQ7_Pos) /*!< 0x00000002 */\r
+#define ADC_SQR4_SQ7_2 (0x04UL << ADC_SQR4_SQ7_Pos) /*!< 0x00000004 */\r
+#define ADC_SQR4_SQ7_3 (0x08UL << ADC_SQR4_SQ7_Pos) /*!< 0x00000008 */\r
+#define ADC_SQR4_SQ7_4 (0x10UL << ADC_SQR4_SQ7_Pos) /*!< 0x00000010 */\r
+\r
+#define ADC_SQR4_SQ8_Pos (5U) \r
+#define ADC_SQR4_SQ8_Msk (0x1FUL << ADC_SQR4_SQ8_Pos) /*!< 0x000003E0 */\r
+#define ADC_SQR4_SQ8 ADC_SQR4_SQ8_Msk /*!< ADC group regular sequencer rank 8 */\r
+#define ADC_SQR4_SQ8_0 (0x01UL << ADC_SQR4_SQ8_Pos) /*!< 0x00000020 */\r
+#define ADC_SQR4_SQ8_1 (0x02UL << ADC_SQR4_SQ8_Pos) /*!< 0x00000040 */\r
+#define ADC_SQR4_SQ8_2 (0x04UL << ADC_SQR4_SQ8_Pos) /*!< 0x00000080 */\r
+#define ADC_SQR4_SQ8_3 (0x08UL << ADC_SQR4_SQ8_Pos) /*!< 0x00000100 */\r
+#define ADC_SQR4_SQ8_4 (0x10UL << ADC_SQR4_SQ8_Pos) /*!< 0x00000200 */\r
+\r
+#define ADC_SQR4_SQ9_Pos (10U) \r
+#define ADC_SQR4_SQ9_Msk (0x1FUL << ADC_SQR4_SQ9_Pos) /*!< 0x00007C00 */\r
+#define ADC_SQR4_SQ9 ADC_SQR4_SQ9_Msk /*!< ADC group regular sequencer rank 9 */\r
+#define ADC_SQR4_SQ9_0 (0x01UL << ADC_SQR4_SQ9_Pos) /*!< 0x00000400 */\r
+#define ADC_SQR4_SQ9_1 (0x02UL << ADC_SQR4_SQ9_Pos) /*!< 0x00000800 */\r
+#define ADC_SQR4_SQ9_2 (0x04UL << ADC_SQR4_SQ9_Pos) /*!< 0x00001000 */\r
+#define ADC_SQR4_SQ9_3 (0x08UL << ADC_SQR4_SQ9_Pos) /*!< 0x00002000 */\r
+#define ADC_SQR4_SQ9_4 (0x10UL << ADC_SQR4_SQ9_Pos) /*!< 0x00004000 */\r
+\r
+#define ADC_SQR4_SQ10_Pos (15U) \r
+#define ADC_SQR4_SQ10_Msk (0x1FUL << ADC_SQR4_SQ10_Pos) /*!< 0x000F8000 */\r
+#define ADC_SQR4_SQ10 ADC_SQR4_SQ10_Msk /*!< ADC group regular sequencer rank 10 */\r
+#define ADC_SQR4_SQ10_0 (0x01UL << ADC_SQR4_SQ10_Pos) /*!< 0x00008000 */\r
+#define ADC_SQR4_SQ10_1 (0x02UL << ADC_SQR4_SQ10_Pos) /*!< 0x00010000 */\r
+#define ADC_SQR4_SQ10_2 (0x04UL << ADC_SQR4_SQ10_Pos) /*!< 0x00020000 */\r
+#define ADC_SQR4_SQ10_3 (0x08UL << ADC_SQR4_SQ10_Pos) /*!< 0x00040000 */\r
+#define ADC_SQR4_SQ10_4 (0x10UL << ADC_SQR4_SQ10_Pos) /*!< 0x00080000 */\r
+\r
+#define ADC_SQR4_SQ11_Pos (20U) \r
+#define ADC_SQR4_SQ11_Msk (0x1FUL << ADC_SQR4_SQ11_Pos) /*!< 0x01F00000 */\r
+#define ADC_SQR4_SQ11 ADC_SQR4_SQ11_Msk /*!< ADC group regular sequencer rank 11 */\r
+#define ADC_SQR4_SQ11_0 (0x01UL << ADC_SQR4_SQ11_Pos) /*!< 0x00100000 */\r
+#define ADC_SQR4_SQ11_1 (0x02UL << ADC_SQR4_SQ11_Pos) /*!< 0x00200000 */\r
+#define ADC_SQR4_SQ11_2 (0x04UL << ADC_SQR4_SQ11_Pos) /*!< 0x00400000 */\r
+#define ADC_SQR4_SQ11_3 (0x08UL << ADC_SQR4_SQ11_Pos) /*!< 0x00800000 */\r
+#define ADC_SQR4_SQ11_4 (0x10UL << ADC_SQR4_SQ11_Pos) /*!< 0x01000000 */\r
+\r
+#define ADC_SQR4_SQ12_Pos (25U) \r
+#define ADC_SQR4_SQ12_Msk (0x1FUL << ADC_SQR4_SQ12_Pos) /*!< 0x3E000000 */\r
+#define ADC_SQR4_SQ12 ADC_SQR4_SQ12_Msk /*!< ADC group regular sequencer rank 12 */\r
+#define ADC_SQR4_SQ12_0 (0x01UL << ADC_SQR4_SQ12_Pos) /*!< 0x02000000 */\r
+#define ADC_SQR4_SQ12_1 (0x02UL << ADC_SQR4_SQ12_Pos) /*!< 0x04000000 */\r
+#define ADC_SQR4_SQ12_2 (0x04UL << ADC_SQR4_SQ12_Pos) /*!< 0x08000000 */\r
+#define ADC_SQR4_SQ12_3 (0x08UL << ADC_SQR4_SQ12_Pos) /*!< 0x10000000 */\r
+#define ADC_SQR4_SQ12_4 (0x10UL << ADC_SQR4_SQ12_Pos) /*!< 0x20000000 */\r
+\r
+/******************* Bit definition for ADC_SQR5 register *******************/\r
+#define ADC_SQR5_SQ1_Pos (0U) \r
+#define ADC_SQR5_SQ1_Msk (0x1FUL << ADC_SQR5_SQ1_Pos) /*!< 0x0000001F */\r
+#define ADC_SQR5_SQ1 ADC_SQR5_SQ1_Msk /*!< ADC group regular sequencer rank 1 */\r
+#define ADC_SQR5_SQ1_0 (0x01UL << ADC_SQR5_SQ1_Pos) /*!< 0x00000001 */\r
+#define ADC_SQR5_SQ1_1 (0x02UL << ADC_SQR5_SQ1_Pos) /*!< 0x00000002 */\r
+#define ADC_SQR5_SQ1_2 (0x04UL << ADC_SQR5_SQ1_Pos) /*!< 0x00000004 */\r
+#define ADC_SQR5_SQ1_3 (0x08UL << ADC_SQR5_SQ1_Pos) /*!< 0x00000008 */\r
+#define ADC_SQR5_SQ1_4 (0x10UL << ADC_SQR5_SQ1_Pos) /*!< 0x00000010 */\r
+\r
+#define ADC_SQR5_SQ2_Pos (5U) \r
+#define ADC_SQR5_SQ2_Msk (0x1FUL << ADC_SQR5_SQ2_Pos) /*!< 0x000003E0 */\r
+#define ADC_SQR5_SQ2 ADC_SQR5_SQ2_Msk /*!< ADC group regular sequencer rank 2 */\r
+#define ADC_SQR5_SQ2_0 (0x01UL << ADC_SQR5_SQ2_Pos) /*!< 0x00000020 */\r
+#define ADC_SQR5_SQ2_1 (0x02UL << ADC_SQR5_SQ2_Pos) /*!< 0x00000040 */\r
+#define ADC_SQR5_SQ2_2 (0x04UL << ADC_SQR5_SQ2_Pos) /*!< 0x00000080 */\r
+#define ADC_SQR5_SQ2_3 (0x08UL << ADC_SQR5_SQ2_Pos) /*!< 0x00000100 */\r
+#define ADC_SQR5_SQ2_4 (0x10UL << ADC_SQR5_SQ2_Pos) /*!< 0x00000200 */\r
+\r
+#define ADC_SQR5_SQ3_Pos (10U) \r
+#define ADC_SQR5_SQ3_Msk (0x1FUL << ADC_SQR5_SQ3_Pos) /*!< 0x00007C00 */\r
+#define ADC_SQR5_SQ3 ADC_SQR5_SQ3_Msk /*!< ADC group regular sequencer rank 3 */\r
+#define ADC_SQR5_SQ3_0 (0x01UL << ADC_SQR5_SQ3_Pos) /*!< 0x00000400 */\r
+#define ADC_SQR5_SQ3_1 (0x02UL << ADC_SQR5_SQ3_Pos) /*!< 0x00000800 */\r
+#define ADC_SQR5_SQ3_2 (0x04UL << ADC_SQR5_SQ3_Pos) /*!< 0x00001000 */\r
+#define ADC_SQR5_SQ3_3 (0x08UL << ADC_SQR5_SQ3_Pos) /*!< 0x00002000 */\r
+#define ADC_SQR5_SQ3_4 (0x10UL << ADC_SQR5_SQ3_Pos) /*!< 0x00004000 */\r
+\r
+#define ADC_SQR5_SQ4_Pos (15U) \r
+#define ADC_SQR5_SQ4_Msk (0x1FUL << ADC_SQR5_SQ4_Pos) /*!< 0x000F8000 */\r
+#define ADC_SQR5_SQ4 ADC_SQR5_SQ4_Msk /*!< ADC group regular sequencer rank 4 */\r
+#define ADC_SQR5_SQ4_0 (0x01UL << ADC_SQR5_SQ4_Pos) /*!< 0x00008000 */\r
+#define ADC_SQR5_SQ4_1 (0x02UL << ADC_SQR5_SQ4_Pos) /*!< 0x00010000 */\r
+#define ADC_SQR5_SQ4_2 (0x04UL << ADC_SQR5_SQ4_Pos) /*!< 0x00020000 */\r
+#define ADC_SQR5_SQ4_3 (0x08UL << ADC_SQR5_SQ4_Pos) /*!< 0x00040000 */\r
+#define ADC_SQR5_SQ4_4 (0x10UL << ADC_SQR5_SQ4_Pos) /*!< 0x00080000 */\r
+\r
+#define ADC_SQR5_SQ5_Pos (20U) \r
+#define ADC_SQR5_SQ5_Msk (0x1FUL << ADC_SQR5_SQ5_Pos) /*!< 0x01F00000 */\r
+#define ADC_SQR5_SQ5 ADC_SQR5_SQ5_Msk /*!< ADC group regular sequencer rank 5 */\r
+#define ADC_SQR5_SQ5_0 (0x01UL << ADC_SQR5_SQ5_Pos) /*!< 0x00100000 */\r
+#define ADC_SQR5_SQ5_1 (0x02UL << ADC_SQR5_SQ5_Pos) /*!< 0x00200000 */\r
+#define ADC_SQR5_SQ5_2 (0x04UL << ADC_SQR5_SQ5_Pos) /*!< 0x00400000 */\r
+#define ADC_SQR5_SQ5_3 (0x08UL << ADC_SQR5_SQ5_Pos) /*!< 0x00800000 */\r
+#define ADC_SQR5_SQ5_4 (0x10UL << ADC_SQR5_SQ5_Pos) /*!< 0x01000000 */\r
+\r
+#define ADC_SQR5_SQ6_Pos (25U) \r
+#define ADC_SQR5_SQ6_Msk (0x1FUL << ADC_SQR5_SQ6_Pos) /*!< 0x3E000000 */\r
+#define ADC_SQR5_SQ6 ADC_SQR5_SQ6_Msk /*!< ADC group regular sequencer rank 6 */\r
+#define ADC_SQR5_SQ6_0 (0x01UL << ADC_SQR5_SQ6_Pos) /*!< 0x02000000 */\r
+#define ADC_SQR5_SQ6_1 (0x02UL << ADC_SQR5_SQ6_Pos) /*!< 0x04000000 */\r
+#define ADC_SQR5_SQ6_2 (0x04UL << ADC_SQR5_SQ6_Pos) /*!< 0x08000000 */\r
+#define ADC_SQR5_SQ6_3 (0x08UL << ADC_SQR5_SQ6_Pos) /*!< 0x10000000 */\r
+#define ADC_SQR5_SQ6_4 (0x10UL << ADC_SQR5_SQ6_Pos) /*!< 0x20000000 */\r
+\r
+\r
+/******************* Bit definition for ADC_JSQR register *******************/\r
+#define ADC_JSQR_JSQ1_Pos (0U) \r
+#define ADC_JSQR_JSQ1_Msk (0x1FUL << ADC_JSQR_JSQ1_Pos) /*!< 0x0000001F */\r
+#define ADC_JSQR_JSQ1 ADC_JSQR_JSQ1_Msk /*!< ADC group injected sequencer rank 1 */\r
+#define ADC_JSQR_JSQ1_0 (0x01UL << ADC_JSQR_JSQ1_Pos) /*!< 0x00000001 */\r
+#define ADC_JSQR_JSQ1_1 (0x02UL << ADC_JSQR_JSQ1_Pos) /*!< 0x00000002 */\r
+#define ADC_JSQR_JSQ1_2 (0x04UL << ADC_JSQR_JSQ1_Pos) /*!< 0x00000004 */\r
+#define ADC_JSQR_JSQ1_3 (0x08UL << ADC_JSQR_JSQ1_Pos) /*!< 0x00000008 */\r
+#define ADC_JSQR_JSQ1_4 (0x10UL << ADC_JSQR_JSQ1_Pos) /*!< 0x00000010 */\r
+\r
+#define ADC_JSQR_JSQ2_Pos (5U) \r
+#define ADC_JSQR_JSQ2_Msk (0x1FUL << ADC_JSQR_JSQ2_Pos) /*!< 0x000003E0 */\r
+#define ADC_JSQR_JSQ2 ADC_JSQR_JSQ2_Msk /*!< ADC group injected sequencer rank 2 */\r
+#define ADC_JSQR_JSQ2_0 (0x01UL << ADC_JSQR_JSQ2_Pos) /*!< 0x00000020 */\r
+#define ADC_JSQR_JSQ2_1 (0x02UL << ADC_JSQR_JSQ2_Pos) /*!< 0x00000040 */\r
+#define ADC_JSQR_JSQ2_2 (0x04UL << ADC_JSQR_JSQ2_Pos) /*!< 0x00000080 */\r
+#define ADC_JSQR_JSQ2_3 (0x08UL << ADC_JSQR_JSQ2_Pos) /*!< 0x00000100 */\r
+#define ADC_JSQR_JSQ2_4 (0x10UL << ADC_JSQR_JSQ2_Pos) /*!< 0x00000200 */\r
+\r
+#define ADC_JSQR_JSQ3_Pos (10U) \r
+#define ADC_JSQR_JSQ3_Msk (0x1FUL << ADC_JSQR_JSQ3_Pos) /*!< 0x00007C00 */\r
+#define ADC_JSQR_JSQ3 ADC_JSQR_JSQ3_Msk /*!< ADC group injected sequencer rank 3 */\r
+#define ADC_JSQR_JSQ3_0 (0x01UL << ADC_JSQR_JSQ3_Pos) /*!< 0x00000400 */\r
+#define ADC_JSQR_JSQ3_1 (0x02UL << ADC_JSQR_JSQ3_Pos) /*!< 0x00000800 */\r
+#define ADC_JSQR_JSQ3_2 (0x04UL << ADC_JSQR_JSQ3_Pos) /*!< 0x00001000 */\r
+#define ADC_JSQR_JSQ3_3 (0x08UL << ADC_JSQR_JSQ3_Pos) /*!< 0x00002000 */\r
+#define ADC_JSQR_JSQ3_4 (0x10UL << ADC_JSQR_JSQ3_Pos) /*!< 0x00004000 */\r
+\r
+#define ADC_JSQR_JSQ4_Pos (15U) \r
+#define ADC_JSQR_JSQ4_Msk (0x1FUL << ADC_JSQR_JSQ4_Pos) /*!< 0x000F8000 */\r
+#define ADC_JSQR_JSQ4 ADC_JSQR_JSQ4_Msk /*!< ADC group injected sequencer rank 4 */\r
+#define ADC_JSQR_JSQ4_0 (0x01UL << ADC_JSQR_JSQ4_Pos) /*!< 0x00008000 */\r
+#define ADC_JSQR_JSQ4_1 (0x02UL << ADC_JSQR_JSQ4_Pos) /*!< 0x00010000 */\r
+#define ADC_JSQR_JSQ4_2 (0x04UL << ADC_JSQR_JSQ4_Pos) /*!< 0x00020000 */\r
+#define ADC_JSQR_JSQ4_3 (0x08UL << ADC_JSQR_JSQ4_Pos) /*!< 0x00040000 */\r
+#define ADC_JSQR_JSQ4_4 (0x10UL << ADC_JSQR_JSQ4_Pos) /*!< 0x00080000 */\r
+\r
+#define ADC_JSQR_JL_Pos (20U) \r
+#define ADC_JSQR_JL_Msk (0x3UL << ADC_JSQR_JL_Pos) /*!< 0x00300000 */\r
+#define ADC_JSQR_JL ADC_JSQR_JL_Msk /*!< ADC group injected sequencer scan length */\r
+#define ADC_JSQR_JL_0 (0x1UL << ADC_JSQR_JL_Pos) /*!< 0x00100000 */\r
+#define ADC_JSQR_JL_1 (0x2UL << ADC_JSQR_JL_Pos) /*!< 0x00200000 */\r
+\r
+/******************* Bit definition for ADC_JDR1 register *******************/\r
+#define ADC_JDR1_JDATA_Pos (0U) \r
+#define ADC_JDR1_JDATA_Msk (0xFFFFUL << ADC_JDR1_JDATA_Pos) /*!< 0x0000FFFF */\r
+#define ADC_JDR1_JDATA ADC_JDR1_JDATA_Msk /*!< ADC group injected sequencer rank 1 conversion data */\r
+\r
+/******************* Bit definition for ADC_JDR2 register *******************/\r
+#define ADC_JDR2_JDATA_Pos (0U) \r
+#define ADC_JDR2_JDATA_Msk (0xFFFFUL << ADC_JDR2_JDATA_Pos) /*!< 0x0000FFFF */\r
+#define ADC_JDR2_JDATA ADC_JDR2_JDATA_Msk /*!< ADC group injected sequencer rank 2 conversion data */\r
+\r
+/******************* Bit definition for ADC_JDR3 register *******************/\r
+#define ADC_JDR3_JDATA_Pos (0U) \r
+#define ADC_JDR3_JDATA_Msk (0xFFFFUL << ADC_JDR3_JDATA_Pos) /*!< 0x0000FFFF */\r
+#define ADC_JDR3_JDATA ADC_JDR3_JDATA_Msk /*!< ADC group injected sequencer rank 3 conversion data */\r
+\r
+/******************* Bit definition for ADC_JDR4 register *******************/\r
+#define ADC_JDR4_JDATA_Pos (0U) \r
+#define ADC_JDR4_JDATA_Msk (0xFFFFUL << ADC_JDR4_JDATA_Pos) /*!< 0x0000FFFF */\r
+#define ADC_JDR4_JDATA ADC_JDR4_JDATA_Msk /*!< ADC group injected sequencer rank 4 conversion data */\r
+\r
+/******************** Bit definition for ADC_DR register ********************/\r
+#define ADC_DR_DATA_Pos (0U) \r
+#define ADC_DR_DATA_Msk (0xFFFFUL << ADC_DR_DATA_Pos) /*!< 0x0000FFFF */\r
+#define ADC_DR_DATA ADC_DR_DATA_Msk /*!< ADC group regular conversion data */\r
+\r
+/****************** Bit definition for ADC_SMPR0 register *******************/\r
+#define ADC_SMPR0_SMP30_Pos (0U) \r
+#define ADC_SMPR0_SMP30_Msk (0x7UL << ADC_SMPR0_SMP30_Pos) /*!< 0x00000007 */\r
+#define ADC_SMPR0_SMP30 ADC_SMPR0_SMP30_Msk /*!< ADC channel 30 sampling time selection */\r
+#define ADC_SMPR0_SMP30_0 (0x1UL << ADC_SMPR0_SMP30_Pos) /*!< 0x00000001 */\r
+#define ADC_SMPR0_SMP30_1 (0x2UL << ADC_SMPR0_SMP30_Pos) /*!< 0x00000002 */\r
+#define ADC_SMPR0_SMP30_2 (0x4UL << ADC_SMPR0_SMP30_Pos) /*!< 0x00000004 */\r
+ \r
+#define ADC_SMPR0_SMP31_Pos (3U) \r
+#define ADC_SMPR0_SMP31_Msk (0x7UL << ADC_SMPR0_SMP31_Pos) /*!< 0x00000038 */\r
+#define ADC_SMPR0_SMP31 ADC_SMPR0_SMP31_Msk /*!< ADC channel 31 sampling time selection */\r
+#define ADC_SMPR0_SMP31_0 (0x1UL << ADC_SMPR0_SMP31_Pos) /*!< 0x00000008 */\r
+#define ADC_SMPR0_SMP31_1 (0x2UL << ADC_SMPR0_SMP31_Pos) /*!< 0x00000010 */\r
+#define ADC_SMPR0_SMP31_2 (0x4UL << ADC_SMPR0_SMP31_Pos) /*!< 0x00000020 */\r
+\r
+/******************* Bit definition for ADC_CSR register ********************/\r
+#define ADC_CSR_AWD1_Pos (0U) \r
+#define ADC_CSR_AWD1_Msk (0x1UL << ADC_CSR_AWD1_Pos) /*!< 0x00000001 */\r
+#define ADC_CSR_AWD1 ADC_CSR_AWD1_Msk /*!< ADC multimode master analog watchdog 1 flag */\r
+#define ADC_CSR_EOCS1_Pos (1U) \r
+#define ADC_CSR_EOCS1_Msk (0x1UL << ADC_CSR_EOCS1_Pos) /*!< 0x00000002 */\r
+#define ADC_CSR_EOCS1 ADC_CSR_EOCS1_Msk /*!< ADC multimode master group regular end of unitary conversion or end of sequence conversions flag */\r
+#define ADC_CSR_JEOS1_Pos (2U) \r
+#define ADC_CSR_JEOS1_Msk (0x1UL << ADC_CSR_JEOS1_Pos) /*!< 0x00000004 */\r
+#define ADC_CSR_JEOS1 ADC_CSR_JEOS1_Msk /*!< ADC multimode master group injected end of sequence conversions flag */\r
+#define ADC_CSR_JSTRT1_Pos (3U) \r
+#define ADC_CSR_JSTRT1_Msk (0x1UL << ADC_CSR_JSTRT1_Pos) /*!< 0x00000008 */\r
+#define ADC_CSR_JSTRT1 ADC_CSR_JSTRT1_Msk /*!< ADC multimode master group injected conversion start flag */\r
+#define ADC_CSR_STRT1_Pos (4U) \r
+#define ADC_CSR_STRT1_Msk (0x1UL << ADC_CSR_STRT1_Pos) /*!< 0x00000010 */\r
+#define ADC_CSR_STRT1 ADC_CSR_STRT1_Msk /*!< ADC multimode master group regular conversion start flag */\r
+#define ADC_CSR_OVR1_Pos (5U) \r
+#define ADC_CSR_OVR1_Msk (0x1UL << ADC_CSR_OVR1_Pos) /*!< 0x00000020 */\r
+#define ADC_CSR_OVR1 ADC_CSR_OVR1_Msk /*!< ADC multimode master group regular overrun flag */\r
+#define ADC_CSR_ADONS1_Pos (6U) \r
+#define ADC_CSR_ADONS1_Msk (0x1UL << ADC_CSR_ADONS1_Pos) /*!< 0x00000040 */\r
+#define ADC_CSR_ADONS1 ADC_CSR_ADONS1_Msk /*!< ADC multimode master ready flag */\r
+\r
+/* Legacy defines */\r
+#define ADC_CSR_EOC1 (ADC_CSR_EOCS1)\r
+#define ADC_CSR_JEOC1 (ADC_CSR_JEOS1)\r
+\r
+/******************* Bit definition for ADC_CCR register ********************/\r
+#define ADC_CCR_ADCPRE_Pos (16U) \r
+#define ADC_CCR_ADCPRE_Msk (0x3UL << ADC_CCR_ADCPRE_Pos) /*!< 0x00030000 */\r
+#define ADC_CCR_ADCPRE ADC_CCR_ADCPRE_Msk /*!< ADC clock source asynchronous prescaler */\r
+#define ADC_CCR_ADCPRE_0 (0x1UL << ADC_CCR_ADCPRE_Pos) /*!< 0x00010000 */\r
+#define ADC_CCR_ADCPRE_1 (0x2UL << ADC_CCR_ADCPRE_Pos) /*!< 0x00020000 */\r
+#define ADC_CCR_TSVREFE_Pos (23U) \r
+#define ADC_CCR_TSVREFE_Msk (0x1UL << ADC_CCR_TSVREFE_Pos) /*!< 0x00800000 */\r
+#define ADC_CCR_TSVREFE ADC_CCR_TSVREFE_Msk /*!< ADC internal path to VrefInt and temperature sensor enable */\r
+\r
+/******************************************************************************/\r
+/* */\r
+/* Analog Comparators (COMP) */\r
+/* */\r
+/******************************************************************************/\r
+\r
+/****************** Bit definition for COMP_CSR register ********************/\r
+#define COMP_CSR_10KPU (0x00000001U) /*!< Comparator 1 input plus 10K pull-up resistor */\r
+#define COMP_CSR_400KPU (0x00000002U) /*!< Comparator 1 input plus 400K pull-up resistor */\r
+#define COMP_CSR_10KPD (0x00000004U) /*!< Comparator 1 input plus 10K pull-down resistor */\r
+#define COMP_CSR_400KPD (0x00000008U) /*!< Comparator 1 input plus 400K pull-down resistor */\r
+#define COMP_CSR_CMP1EN_Pos (4U) \r
+#define COMP_CSR_CMP1EN_Msk (0x1UL << COMP_CSR_CMP1EN_Pos) /*!< 0x00000010 */\r
+#define COMP_CSR_CMP1EN COMP_CSR_CMP1EN_Msk /*!< Comparator 1 enable */\r
+#define COMP_CSR_CMP1OUT_Pos (7U) \r
+#define COMP_CSR_CMP1OUT_Msk (0x1UL << COMP_CSR_CMP1OUT_Pos) /*!< 0x00000080 */\r
+#define COMP_CSR_CMP1OUT COMP_CSR_CMP1OUT_Msk /*!< Comparator 1 output level */\r
+#define COMP_CSR_SPEED_Pos (12U) \r
+#define COMP_CSR_SPEED_Msk (0x1UL << COMP_CSR_SPEED_Pos) /*!< 0x00001000 */\r
+#define COMP_CSR_SPEED COMP_CSR_SPEED_Msk /*!< Comparator 2 power mode */\r
+#define COMP_CSR_CMP2OUT_Pos (13U) \r
+#define COMP_CSR_CMP2OUT_Msk (0x1UL << COMP_CSR_CMP2OUT_Pos) /*!< 0x00002000 */\r
+#define COMP_CSR_CMP2OUT COMP_CSR_CMP2OUT_Msk /*!< Comparator 2 output level */\r
+\r
+#define COMP_CSR_WNDWE_Pos (17U) \r
+#define COMP_CSR_WNDWE_Msk (0x1UL << COMP_CSR_WNDWE_Pos) /*!< 0x00020000 */\r
+#define COMP_CSR_WNDWE COMP_CSR_WNDWE_Msk /*!< Pair of comparators window mode. Bit intended to be used with COMP common instance (COMP_Common_TypeDef) */\r
+\r
+#define COMP_CSR_INSEL_Pos (18U) \r
+#define COMP_CSR_INSEL_Msk (0x7UL << COMP_CSR_INSEL_Pos) /*!< 0x001C0000 */\r
+#define COMP_CSR_INSEL COMP_CSR_INSEL_Msk /*!< Comparator 2 input minus selection */\r
+#define COMP_CSR_INSEL_0 (0x1UL << COMP_CSR_INSEL_Pos) /*!< 0x00040000 */\r
+#define COMP_CSR_INSEL_1 (0x2UL << COMP_CSR_INSEL_Pos) /*!< 0x00080000 */\r
+#define COMP_CSR_INSEL_2 (0x4UL << COMP_CSR_INSEL_Pos) /*!< 0x00100000 */\r
+#define COMP_CSR_OUTSEL_Pos (21U) \r
+#define COMP_CSR_OUTSEL_Msk (0x7UL << COMP_CSR_OUTSEL_Pos) /*!< 0x00E00000 */\r
+#define COMP_CSR_OUTSEL COMP_CSR_OUTSEL_Msk /*!< Comparator 2 output redirection */\r
+#define COMP_CSR_OUTSEL_0 (0x1UL << COMP_CSR_OUTSEL_Pos) /*!< 0x00200000 */\r
+#define COMP_CSR_OUTSEL_1 (0x2UL << COMP_CSR_OUTSEL_Pos) /*!< 0x00400000 */\r
+#define COMP_CSR_OUTSEL_2 (0x4UL << COMP_CSR_OUTSEL_Pos) /*!< 0x00800000 */\r
+\r
+/* Bits present in COMP register but not related to comparator */\r
+/* (or partially related to comparator, in addition to other peripherals) */\r
+#define COMP_CSR_SW1_Pos (5U) \r
+#define COMP_CSR_SW1_Msk (0x1UL << COMP_CSR_SW1_Pos) /*!< 0x00000020 */\r
+#define COMP_CSR_SW1 COMP_CSR_SW1_Msk /*!< SW1 analog switch enable */\r
+#define COMP_CSR_VREFOUTEN_Pos (16U) \r
+#define COMP_CSR_VREFOUTEN_Msk (0x1UL << COMP_CSR_VREFOUTEN_Pos) /*!< 0x00010000 */\r
+#define COMP_CSR_VREFOUTEN COMP_CSR_VREFOUTEN_Msk /*!< VrefInt output enable on GPIO group 3 */\r
+\r
+#define COMP_CSR_FCH3_Pos (26U) \r
+#define COMP_CSR_FCH3_Msk (0x1UL << COMP_CSR_FCH3_Pos) /*!< 0x04000000 */\r
+#define COMP_CSR_FCH3 COMP_CSR_FCH3_Msk /*!< Bit 26 */\r
+#define COMP_CSR_FCH8_Pos (27U) \r
+#define COMP_CSR_FCH8_Msk (0x1UL << COMP_CSR_FCH8_Pos) /*!< 0x08000000 */\r
+#define COMP_CSR_FCH8 COMP_CSR_FCH8_Msk /*!< Bit 27 */\r
+#define COMP_CSR_RCH13_Pos (28U) \r
+#define COMP_CSR_RCH13_Msk (0x1UL << COMP_CSR_RCH13_Pos) /*!< 0x10000000 */\r
+#define COMP_CSR_RCH13 COMP_CSR_RCH13_Msk /*!< Bit 28 */\r
+\r
+#define COMP_CSR_CAIE_Pos (29U) \r
+#define COMP_CSR_CAIE_Msk (0x1UL << COMP_CSR_CAIE_Pos) /*!< 0x20000000 */\r
+#define COMP_CSR_CAIE COMP_CSR_CAIE_Msk /*!< Bit 29 */\r
+#define COMP_CSR_CAIF_Pos (30U) \r
+#define COMP_CSR_CAIF_Msk (0x1UL << COMP_CSR_CAIF_Pos) /*!< 0x40000000 */\r
+#define COMP_CSR_CAIF COMP_CSR_CAIF_Msk /*!< Bit 30 */\r
+#define COMP_CSR_TSUSP_Pos (31U) \r
+#define COMP_CSR_TSUSP_Msk (0x1UL << COMP_CSR_TSUSP_Pos) /*!< 0x80000000 */\r
+#define COMP_CSR_TSUSP COMP_CSR_TSUSP_Msk /*!< Bit 31 */\r
+\r
+/******************************************************************************/\r
+/* */\r
+/* Operational Amplifier (OPAMP) */\r
+/* */\r
+/******************************************************************************/\r
+/******************* Bit definition for OPAMP_CSR register ******************/\r
+#define OPAMP_CSR_OPA1PD_Pos (0U) \r
+#define OPAMP_CSR_OPA1PD_Msk (0x1UL << OPAMP_CSR_OPA1PD_Pos) /*!< 0x00000001 */\r
+#define OPAMP_CSR_OPA1PD OPAMP_CSR_OPA1PD_Msk /*!< OPAMP1 disable */\r
+#define OPAMP_CSR_S3SEL1_Pos (1U) \r
+#define OPAMP_CSR_S3SEL1_Msk (0x1UL << OPAMP_CSR_S3SEL1_Pos) /*!< 0x00000002 */\r
+#define OPAMP_CSR_S3SEL1 OPAMP_CSR_S3SEL1_Msk /*!< Switch 3 for OPAMP1 Enable */\r
+#define OPAMP_CSR_S4SEL1_Pos (2U) \r
+#define OPAMP_CSR_S4SEL1_Msk (0x1UL << OPAMP_CSR_S4SEL1_Pos) /*!< 0x00000004 */\r
+#define OPAMP_CSR_S4SEL1 OPAMP_CSR_S4SEL1_Msk /*!< Switch 4 for OPAMP1 Enable */\r
+#define OPAMP_CSR_S5SEL1_Pos (3U) \r
+#define OPAMP_CSR_S5SEL1_Msk (0x1UL << OPAMP_CSR_S5SEL1_Pos) /*!< 0x00000008 */\r
+#define OPAMP_CSR_S5SEL1 OPAMP_CSR_S5SEL1_Msk /*!< Switch 5 for OPAMP1 Enable */\r
+#define OPAMP_CSR_S6SEL1_Pos (4U) \r
+#define OPAMP_CSR_S6SEL1_Msk (0x1UL << OPAMP_CSR_S6SEL1_Pos) /*!< 0x00000010 */\r
+#define OPAMP_CSR_S6SEL1 OPAMP_CSR_S6SEL1_Msk /*!< Switch 6 for OPAMP1 Enable */\r
+#define OPAMP_CSR_OPA1CAL_L_Pos (5U) \r
+#define OPAMP_CSR_OPA1CAL_L_Msk (0x1UL << OPAMP_CSR_OPA1CAL_L_Pos) /*!< 0x00000020 */\r
+#define OPAMP_CSR_OPA1CAL_L OPAMP_CSR_OPA1CAL_L_Msk /*!< OPAMP1 Offset calibration for P differential pair */\r
+#define OPAMP_CSR_OPA1CAL_H_Pos (6U) \r
+#define OPAMP_CSR_OPA1CAL_H_Msk (0x1UL << OPAMP_CSR_OPA1CAL_H_Pos) /*!< 0x00000040 */\r
+#define OPAMP_CSR_OPA1CAL_H OPAMP_CSR_OPA1CAL_H_Msk /*!< OPAMP1 Offset calibration for N differential pair */\r
+#define OPAMP_CSR_OPA1LPM_Pos (7U) \r
+#define OPAMP_CSR_OPA1LPM_Msk (0x1UL << OPAMP_CSR_OPA1LPM_Pos) /*!< 0x00000080 */\r
+#define OPAMP_CSR_OPA1LPM OPAMP_CSR_OPA1LPM_Msk /*!< OPAMP1 Low power enable */\r
+#define OPAMP_CSR_OPA2PD_Pos (8U) \r
+#define OPAMP_CSR_OPA2PD_Msk (0x1UL << OPAMP_CSR_OPA2PD_Pos) /*!< 0x00000100 */\r
+#define OPAMP_CSR_OPA2PD OPAMP_CSR_OPA2PD_Msk /*!< OPAMP2 disable */\r
+#define OPAMP_CSR_S3SEL2_Pos (9U) \r
+#define OPAMP_CSR_S3SEL2_Msk (0x1UL << OPAMP_CSR_S3SEL2_Pos) /*!< 0x00000200 */\r
+#define OPAMP_CSR_S3SEL2 OPAMP_CSR_S3SEL2_Msk /*!< Switch 3 for OPAMP2 Enable */\r
+#define OPAMP_CSR_S4SEL2_Pos (10U) \r
+#define OPAMP_CSR_S4SEL2_Msk (0x1UL << OPAMP_CSR_S4SEL2_Pos) /*!< 0x00000400 */\r
+#define OPAMP_CSR_S4SEL2 OPAMP_CSR_S4SEL2_Msk /*!< Switch 4 for OPAMP2 Enable */\r
+#define OPAMP_CSR_S5SEL2_Pos (11U) \r
+#define OPAMP_CSR_S5SEL2_Msk (0x1UL << OPAMP_CSR_S5SEL2_Pos) /*!< 0x00000800 */\r
+#define OPAMP_CSR_S5SEL2 OPAMP_CSR_S5SEL2_Msk /*!< Switch 5 for OPAMP2 Enable */\r
+#define OPAMP_CSR_S6SEL2_Pos (12U) \r
+#define OPAMP_CSR_S6SEL2_Msk (0x1UL << OPAMP_CSR_S6SEL2_Pos) /*!< 0x00001000 */\r
+#define OPAMP_CSR_S6SEL2 OPAMP_CSR_S6SEL2_Msk /*!< Switch 6 for OPAMP2 Enable */\r
+#define OPAMP_CSR_OPA2CAL_L_Pos (13U) \r
+#define OPAMP_CSR_OPA2CAL_L_Msk (0x1UL << OPAMP_CSR_OPA2CAL_L_Pos) /*!< 0x00002000 */\r
+#define OPAMP_CSR_OPA2CAL_L OPAMP_CSR_OPA2CAL_L_Msk /*!< OPAMP2 Offset calibration for P differential pair */\r
+#define OPAMP_CSR_OPA2CAL_H_Pos (14U) \r
+#define OPAMP_CSR_OPA2CAL_H_Msk (0x1UL << OPAMP_CSR_OPA2CAL_H_Pos) /*!< 0x00004000 */\r
+#define OPAMP_CSR_OPA2CAL_H OPAMP_CSR_OPA2CAL_H_Msk /*!< OPAMP2 Offset calibration for N differential pair */\r
+#define OPAMP_CSR_OPA2LPM_Pos (15U) \r
+#define OPAMP_CSR_OPA2LPM_Msk (0x1UL << OPAMP_CSR_OPA2LPM_Pos) /*!< 0x00008000 */\r
+#define OPAMP_CSR_OPA2LPM OPAMP_CSR_OPA2LPM_Msk /*!< OPAMP2 Low power enable */\r
+#define OPAMP_CSR_ANAWSEL1_Pos (24U) \r
+#define OPAMP_CSR_ANAWSEL1_Msk (0x1UL << OPAMP_CSR_ANAWSEL1_Pos) /*!< 0x01000000 */\r
+#define OPAMP_CSR_ANAWSEL1 OPAMP_CSR_ANAWSEL1_Msk /*!< Switch ANA Enable for OPAMP1 */ \r
+#define OPAMP_CSR_ANAWSEL2_Pos (25U) \r
+#define OPAMP_CSR_ANAWSEL2_Msk (0x1UL << OPAMP_CSR_ANAWSEL2_Pos) /*!< 0x02000000 */\r
+#define OPAMP_CSR_ANAWSEL2 OPAMP_CSR_ANAWSEL2_Msk /*!< Switch ANA Enable for OPAMP2 */\r
+#define OPAMP_CSR_S7SEL2_Pos (27U) \r
+#define OPAMP_CSR_S7SEL2_Msk (0x1UL << OPAMP_CSR_S7SEL2_Pos) /*!< 0x08000000 */\r
+#define OPAMP_CSR_S7SEL2 OPAMP_CSR_S7SEL2_Msk /*!< Switch 7 for OPAMP2 Enable */\r
+#define OPAMP_CSR_AOP_RANGE_Pos (28U) \r
+#define OPAMP_CSR_AOP_RANGE_Msk (0x1UL << OPAMP_CSR_AOP_RANGE_Pos) /*!< 0x10000000 */\r
+#define OPAMP_CSR_AOP_RANGE OPAMP_CSR_AOP_RANGE_Msk /*!< Common to several OPAMP instances: Operational amplifier voltage supply range. Bit intended to be used with OPAMP common instance (OPAMP_Common_TypeDef) */\r
+#define OPAMP_CSR_OPA1CALOUT_Pos (29U) \r
+#define OPAMP_CSR_OPA1CALOUT_Msk (0x1UL << OPAMP_CSR_OPA1CALOUT_Pos) /*!< 0x20000000 */\r
+#define OPAMP_CSR_OPA1CALOUT OPAMP_CSR_OPA1CALOUT_Msk /*!< OPAMP1 calibration output */\r
+#define OPAMP_CSR_OPA2CALOUT_Pos (30U) \r
+#define OPAMP_CSR_OPA2CALOUT_Msk (0x1UL << OPAMP_CSR_OPA2CALOUT_Pos) /*!< 0x40000000 */\r
+#define OPAMP_CSR_OPA2CALOUT OPAMP_CSR_OPA2CALOUT_Msk /*!< OPAMP2 calibration output */\r
+\r
+/******************* Bit definition for OPAMP_OTR register ******************/\r
+#define OPAMP_OTR_AO1_OPT_OFFSET_TRIM_LOW_Pos (0U) \r
+#define OPAMP_OTR_AO1_OPT_OFFSET_TRIM_LOW_Msk (0x1FUL << OPAMP_OTR_AO1_OPT_OFFSET_TRIM_LOW_Pos) /*!< 0x0000001F */\r
+#define OPAMP_OTR_AO1_OPT_OFFSET_TRIM_LOW OPAMP_OTR_AO1_OPT_OFFSET_TRIM_LOW_Msk /*!< Offset trim for transistors differential pair PMOS of OPAMP1 */\r
+#define OPAMP_OTR_AO1_OPT_OFFSET_TRIM_HIGH_Pos (5U) \r
+#define OPAMP_OTR_AO1_OPT_OFFSET_TRIM_HIGH_Msk (0x1FUL << OPAMP_OTR_AO1_OPT_OFFSET_TRIM_HIGH_Pos) /*!< 0x000003E0 */\r
+#define OPAMP_OTR_AO1_OPT_OFFSET_TRIM_HIGH OPAMP_OTR_AO1_OPT_OFFSET_TRIM_HIGH_Msk /*!< Offset trim for transistors differential pair NMOS of OPAMP1 */\r
+#define OPAMP_OTR_AO2_OPT_OFFSET_TRIM_LOW_Pos (10U) \r
+#define OPAMP_OTR_AO2_OPT_OFFSET_TRIM_LOW_Msk (0x1FUL << OPAMP_OTR_AO2_OPT_OFFSET_TRIM_LOW_Pos) /*!< 0x00007C00 */\r
+#define OPAMP_OTR_AO2_OPT_OFFSET_TRIM_LOW OPAMP_OTR_AO2_OPT_OFFSET_TRIM_LOW_Msk /*!< Offset trim for transistors differential pair PMOS of OPAMP2 */\r
+#define OPAMP_OTR_AO2_OPT_OFFSET_TRIM_HIGH_Pos (15U) \r
+#define OPAMP_OTR_AO2_OPT_OFFSET_TRIM_HIGH_Msk (0x1FUL << OPAMP_OTR_AO2_OPT_OFFSET_TRIM_HIGH_Pos) /*!< 0x000F8000 */\r
+#define OPAMP_OTR_AO2_OPT_OFFSET_TRIM_HIGH OPAMP_OTR_AO2_OPT_OFFSET_TRIM_HIGH_Msk /*!< Offset trim for transistors differential pair NMOS of OPAMP2 */\r
+#define OPAMP_OTR_OT_USER_Pos (31U) \r
+#define OPAMP_OTR_OT_USER_Msk (0x1UL << OPAMP_OTR_OT_USER_Pos) /*!< 0x80000000 */\r
+#define OPAMP_OTR_OT_USER OPAMP_OTR_OT_USER_Msk /*!< Switch to OPAMP offset user trimmed values */\r
+\r
+/******************* Bit definition for OPAMP_LPOTR register ****************/\r
+#define OPAMP_OTR_AO1_OPT_OFFSET_TRIM_LP_LOW_Pos (0U) \r
+#define OPAMP_OTR_AO1_OPT_OFFSET_TRIM_LP_LOW_Msk (0x1FUL << OPAMP_OTR_AO1_OPT_OFFSET_TRIM_LP_LOW_Pos) /*!< 0x0000001F */\r
+#define OPAMP_OTR_AO1_OPT_OFFSET_TRIM_LP_LOW OPAMP_OTR_AO1_OPT_OFFSET_TRIM_LP_LOW_Msk /*!< Offset trim for transistors differential pair PMOS of OPAMP1 */\r
+#define OPAMP_OTR_AO1_OPT_OFFSET_TRIM_LP_HIGH_Pos (5U) \r
+#define OPAMP_OTR_AO1_OPT_OFFSET_TRIM_LP_HIGH_Msk (0x1FUL << OPAMP_OTR_AO1_OPT_OFFSET_TRIM_LP_HIGH_Pos) /*!< 0x000003E0 */\r
+#define OPAMP_OTR_AO1_OPT_OFFSET_TRIM_LP_HIGH OPAMP_OTR_AO1_OPT_OFFSET_TRIM_LP_HIGH_Msk /*!< Offset trim for transistors differential pair NMOS of OPAMP1 */\r
+#define OPAMP_OTR_AO2_OPT_OFFSET_TRIM_LP_LOW_Pos (10U) \r
+#define OPAMP_OTR_AO2_OPT_OFFSET_TRIM_LP_LOW_Msk (0x1FUL << OPAMP_OTR_AO2_OPT_OFFSET_TRIM_LP_LOW_Pos) /*!< 0x00007C00 */\r
+#define OPAMP_OTR_AO2_OPT_OFFSET_TRIM_LP_LOW OPAMP_OTR_AO2_OPT_OFFSET_TRIM_LP_LOW_Msk /*!< Offset trim for transistors differential pair PMOS of OPAMP2 */\r
+#define OPAMP_OTR_AO2_OPT_OFFSET_TRIM_LP_HIGH_Pos (15U) \r
+#define OPAMP_OTR_AO2_OPT_OFFSET_TRIM_LP_HIGH_Msk (0x1FUL << OPAMP_OTR_AO2_OPT_OFFSET_TRIM_LP_HIGH_Pos) /*!< 0x000F8000 */\r
+#define OPAMP_OTR_AO2_OPT_OFFSET_TRIM_LP_HIGH OPAMP_OTR_AO2_OPT_OFFSET_TRIM_LP_HIGH_Msk /*!< Offset trim for transistors differential pair NMOS of OPAMP2 */\r
+\r
+/******************************************************************************/\r
+/* */\r
+/* CRC calculation unit (CRC) */\r
+/* */\r
+/******************************************************************************/\r
+\r
+/******************* Bit definition for CRC_DR register *********************/\r
+#define CRC_DR_DR_Pos (0U) \r
+#define CRC_DR_DR_Msk (0xFFFFFFFFUL << CRC_DR_DR_Pos) /*!< 0xFFFFFFFF */\r
+#define CRC_DR_DR CRC_DR_DR_Msk /*!< Data register bits */\r
+\r
+/******************* Bit definition for CRC_IDR register ********************/\r
+#define CRC_IDR_IDR_Pos (0U) \r
+#define CRC_IDR_IDR_Msk (0xFFUL << CRC_IDR_IDR_Pos) /*!< 0x000000FF */\r
+#define CRC_IDR_IDR CRC_IDR_IDR_Msk /*!< General-purpose 8-bit data register bits */\r
+\r
+/******************** Bit definition for CRC_CR register ********************/\r
+#define CRC_CR_RESET_Pos (0U) \r
+#define CRC_CR_RESET_Msk (0x1UL << CRC_CR_RESET_Pos) /*!< 0x00000001 */\r
+#define CRC_CR_RESET CRC_CR_RESET_Msk /*!< RESET bit */\r
+\r
+/******************************************************************************/\r
+/* */\r
+/* Digital to Analog Converter (DAC) */\r
+/* */\r
+/******************************************************************************/\r
+\r
+/******************** Bit definition for DAC_CR register ********************/\r
+#define DAC_CR_EN1_Pos (0U) \r
+#define DAC_CR_EN1_Msk (0x1UL << DAC_CR_EN1_Pos) /*!< 0x00000001 */\r
+#define DAC_CR_EN1 DAC_CR_EN1_Msk /*!<DAC channel1 enable */\r
+#define DAC_CR_BOFF1_Pos (1U) \r
+#define DAC_CR_BOFF1_Msk (0x1UL << DAC_CR_BOFF1_Pos) /*!< 0x00000002 */\r
+#define DAC_CR_BOFF1 DAC_CR_BOFF1_Msk /*!<DAC channel1 output buffer disable */\r
+#define DAC_CR_TEN1_Pos (2U) \r
+#define DAC_CR_TEN1_Msk (0x1UL << DAC_CR_TEN1_Pos) /*!< 0x00000004 */\r
+#define DAC_CR_TEN1 DAC_CR_TEN1_Msk /*!<DAC channel1 Trigger enable */\r
+\r
+#define DAC_CR_TSEL1_Pos (3U) \r
+#define DAC_CR_TSEL1_Msk (0x7UL << DAC_CR_TSEL1_Pos) /*!< 0x00000038 */\r
+#define DAC_CR_TSEL1 DAC_CR_TSEL1_Msk /*!<TSEL1[2:0] (DAC channel1 Trigger selection) */\r
+#define DAC_CR_TSEL1_0 (0x1UL << DAC_CR_TSEL1_Pos) /*!< 0x00000008 */\r
+#define DAC_CR_TSEL1_1 (0x2UL << DAC_CR_TSEL1_Pos) /*!< 0x00000010 */\r
+#define DAC_CR_TSEL1_2 (0x4UL << DAC_CR_TSEL1_Pos) /*!< 0x00000020 */\r
+\r
+#define DAC_CR_WAVE1_Pos (6U) \r
+#define DAC_CR_WAVE1_Msk (0x3UL << DAC_CR_WAVE1_Pos) /*!< 0x000000C0 */\r
+#define DAC_CR_WAVE1 DAC_CR_WAVE1_Msk /*!<WAVE1[1:0] (DAC channel1 noise/triangle wave generation enable) */\r
+#define DAC_CR_WAVE1_0 (0x1UL << DAC_CR_WAVE1_Pos) /*!< 0x00000040 */\r
+#define DAC_CR_WAVE1_1 (0x2UL << DAC_CR_WAVE1_Pos) /*!< 0x00000080 */\r
+\r
+#define DAC_CR_MAMP1_Pos (8U) \r
+#define DAC_CR_MAMP1_Msk (0xFUL << DAC_CR_MAMP1_Pos) /*!< 0x00000F00 */\r
+#define DAC_CR_MAMP1 DAC_CR_MAMP1_Msk /*!<MAMP1[3:0] (DAC channel1 Mask/Amplitude selector) */\r
+#define DAC_CR_MAMP1_0 (0x1UL << DAC_CR_MAMP1_Pos) /*!< 0x00000100 */\r
+#define DAC_CR_MAMP1_1 (0x2UL << DAC_CR_MAMP1_Pos) /*!< 0x00000200 */\r
+#define DAC_CR_MAMP1_2 (0x4UL << DAC_CR_MAMP1_Pos) /*!< 0x00000400 */\r
+#define DAC_CR_MAMP1_3 (0x8UL << DAC_CR_MAMP1_Pos) /*!< 0x00000800 */\r
+\r
+#define DAC_CR_DMAEN1_Pos (12U) \r
+#define DAC_CR_DMAEN1_Msk (0x1UL << DAC_CR_DMAEN1_Pos) /*!< 0x00001000 */\r
+#define DAC_CR_DMAEN1 DAC_CR_DMAEN1_Msk /*!<DAC channel1 DMA enable */\r
+#define DAC_CR_DMAUDRIE1_Pos (13U) \r
+#define DAC_CR_DMAUDRIE1_Msk (0x1UL << DAC_CR_DMAUDRIE1_Pos) /*!< 0x00002000 */\r
+#define DAC_CR_DMAUDRIE1 DAC_CR_DMAUDRIE1_Msk /*!<DAC channel1 DMA Interrupt enable */\r
+#define DAC_CR_EN2_Pos (16U) \r
+#define DAC_CR_EN2_Msk (0x1UL << DAC_CR_EN2_Pos) /*!< 0x00010000 */\r
+#define DAC_CR_EN2 DAC_CR_EN2_Msk /*!<DAC channel2 enable */\r
+#define DAC_CR_BOFF2_Pos (17U) \r
+#define DAC_CR_BOFF2_Msk (0x1UL << DAC_CR_BOFF2_Pos) /*!< 0x00020000 */\r
+#define DAC_CR_BOFF2 DAC_CR_BOFF2_Msk /*!<DAC channel2 output buffer disable */\r
+#define DAC_CR_TEN2_Pos (18U) \r
+#define DAC_CR_TEN2_Msk (0x1UL << DAC_CR_TEN2_Pos) /*!< 0x00040000 */\r
+#define DAC_CR_TEN2 DAC_CR_TEN2_Msk /*!<DAC channel2 Trigger enable */\r
+\r
+#define DAC_CR_TSEL2_Pos (19U) \r
+#define DAC_CR_TSEL2_Msk (0x7UL << DAC_CR_TSEL2_Pos) /*!< 0x00380000 */\r
+#define DAC_CR_TSEL2 DAC_CR_TSEL2_Msk /*!<TSEL2[2:0] (DAC channel2 Trigger selection) */\r
+#define DAC_CR_TSEL2_0 (0x1UL << DAC_CR_TSEL2_Pos) /*!< 0x00080000 */\r
+#define DAC_CR_TSEL2_1 (0x2UL << DAC_CR_TSEL2_Pos) /*!< 0x00100000 */\r
+#define DAC_CR_TSEL2_2 (0x4UL << DAC_CR_TSEL2_Pos) /*!< 0x00200000 */\r
+\r
+#define DAC_CR_WAVE2_Pos (22U) \r
+#define DAC_CR_WAVE2_Msk (0x3UL << DAC_CR_WAVE2_Pos) /*!< 0x00C00000 */\r
+#define DAC_CR_WAVE2 DAC_CR_WAVE2_Msk /*!<WAVE2[1:0] (DAC channel2 noise/triangle wave generation enable) */\r
+#define DAC_CR_WAVE2_0 (0x1UL << DAC_CR_WAVE2_Pos) /*!< 0x00400000 */\r
+#define DAC_CR_WAVE2_1 (0x2UL << DAC_CR_WAVE2_Pos) /*!< 0x00800000 */\r
+\r
+#define DAC_CR_MAMP2_Pos (24U) \r
+#define DAC_CR_MAMP2_Msk (0xFUL << DAC_CR_MAMP2_Pos) /*!< 0x0F000000 */\r
+#define DAC_CR_MAMP2 DAC_CR_MAMP2_Msk /*!<MAMP2[3:0] (DAC channel2 Mask/Amplitude selector) */\r
+#define DAC_CR_MAMP2_0 (0x1UL << DAC_CR_MAMP2_Pos) /*!< 0x01000000 */\r
+#define DAC_CR_MAMP2_1 (0x2UL << DAC_CR_MAMP2_Pos) /*!< 0x02000000 */\r
+#define DAC_CR_MAMP2_2 (0x4UL << DAC_CR_MAMP2_Pos) /*!< 0x04000000 */\r
+#define DAC_CR_MAMP2_3 (0x8UL << DAC_CR_MAMP2_Pos) /*!< 0x08000000 */\r
+\r
+#define DAC_CR_DMAEN2_Pos (28U) \r
+#define DAC_CR_DMAEN2_Msk (0x1UL << DAC_CR_DMAEN2_Pos) /*!< 0x10000000 */\r
+#define DAC_CR_DMAEN2 DAC_CR_DMAEN2_Msk /*!<DAC channel2 DMA enabled */\r
+#define DAC_CR_DMAUDRIE2_Pos (29U) \r
+#define DAC_CR_DMAUDRIE2_Msk (0x1UL << DAC_CR_DMAUDRIE2_Pos) /*!< 0x20000000 */\r
+#define DAC_CR_DMAUDRIE2 DAC_CR_DMAUDRIE2_Msk /*!<DAC channel2 DMA underrun interrupt enable */\r
+/***************** Bit definition for DAC_SWTRIGR register ******************/\r
+#define DAC_SWTRIGR_SWTRIG1_Pos (0U) \r
+#define DAC_SWTRIGR_SWTRIG1_Msk (0x1UL << DAC_SWTRIGR_SWTRIG1_Pos) /*!< 0x00000001 */\r
+#define DAC_SWTRIGR_SWTRIG1 DAC_SWTRIGR_SWTRIG1_Msk /*!<DAC channel1 software trigger */\r
+#define DAC_SWTRIGR_SWTRIG2_Pos (1U) \r
+#define DAC_SWTRIGR_SWTRIG2_Msk (0x1UL << DAC_SWTRIGR_SWTRIG2_Pos) /*!< 0x00000002 */\r
+#define DAC_SWTRIGR_SWTRIG2 DAC_SWTRIGR_SWTRIG2_Msk /*!<DAC channel2 software trigger */\r
+\r
+/***************** Bit definition for DAC_DHR12R1 register ******************/\r
+#define DAC_DHR12R1_DACC1DHR_Pos (0U) \r
+#define DAC_DHR12R1_DACC1DHR_Msk (0xFFFUL << DAC_DHR12R1_DACC1DHR_Pos) /*!< 0x00000FFF */\r
+#define DAC_DHR12R1_DACC1DHR DAC_DHR12R1_DACC1DHR_Msk /*!<DAC channel1 12-bit Right aligned data */\r
+\r
+/***************** Bit definition for DAC_DHR12L1 register ******************/\r
+#define DAC_DHR12L1_DACC1DHR_Pos (4U) \r
+#define DAC_DHR12L1_DACC1DHR_Msk (0xFFFUL << DAC_DHR12L1_DACC1DHR_Pos) /*!< 0x0000FFF0 */\r
+#define DAC_DHR12L1_DACC1DHR DAC_DHR12L1_DACC1DHR_Msk /*!<DAC channel1 12-bit Left aligned data */\r
+\r
+/****************** Bit definition for DAC_DHR8R1 register ******************/\r
+#define DAC_DHR8R1_DACC1DHR_Pos (0U) \r
+#define DAC_DHR8R1_DACC1DHR_Msk (0xFFUL << DAC_DHR8R1_DACC1DHR_Pos) /*!< 0x000000FF */\r
+#define DAC_DHR8R1_DACC1DHR DAC_DHR8R1_DACC1DHR_Msk /*!<DAC channel1 8-bit Right aligned data */\r
+\r
+/***************** Bit definition for DAC_DHR12R2 register ******************/\r
+#define DAC_DHR12R2_DACC2DHR_Pos (0U) \r
+#define DAC_DHR12R2_DACC2DHR_Msk (0xFFFUL << DAC_DHR12R2_DACC2DHR_Pos) /*!< 0x00000FFF */\r
+#define DAC_DHR12R2_DACC2DHR DAC_DHR12R2_DACC2DHR_Msk /*!<DAC channel2 12-bit Right aligned data */\r
+\r
+/***************** Bit definition for DAC_DHR12L2 register ******************/\r
+#define DAC_DHR12L2_DACC2DHR_Pos (4U) \r
+#define DAC_DHR12L2_DACC2DHR_Msk (0xFFFUL << DAC_DHR12L2_DACC2DHR_Pos) /*!< 0x0000FFF0 */\r
+#define DAC_DHR12L2_DACC2DHR DAC_DHR12L2_DACC2DHR_Msk /*!<DAC channel2 12-bit Left aligned data */\r
+\r
+/****************** Bit definition for DAC_DHR8R2 register ******************/\r
+#define DAC_DHR8R2_DACC2DHR_Pos (0U) \r
+#define DAC_DHR8R2_DACC2DHR_Msk (0xFFUL << DAC_DHR8R2_DACC2DHR_Pos) /*!< 0x000000FF */\r
+#define DAC_DHR8R2_DACC2DHR DAC_DHR8R2_DACC2DHR_Msk /*!<DAC channel2 8-bit Right aligned data */\r
+\r
+/***************** Bit definition for DAC_DHR12RD register ******************/\r
+#define DAC_DHR12RD_DACC1DHR_Pos (0U) \r
+#define DAC_DHR12RD_DACC1DHR_Msk (0xFFFUL << DAC_DHR12RD_DACC1DHR_Pos) /*!< 0x00000FFF */\r
+#define DAC_DHR12RD_DACC1DHR DAC_DHR12RD_DACC1DHR_Msk /*!<DAC channel1 12-bit Right aligned data */\r
+#define DAC_DHR12RD_DACC2DHR_Pos (16U) \r
+#define DAC_DHR12RD_DACC2DHR_Msk (0xFFFUL << DAC_DHR12RD_DACC2DHR_Pos) /*!< 0x0FFF0000 */\r
+#define DAC_DHR12RD_DACC2DHR DAC_DHR12RD_DACC2DHR_Msk /*!<DAC channel2 12-bit Right aligned data */\r
+\r
+/***************** Bit definition for DAC_DHR12LD register ******************/\r
+#define DAC_DHR12LD_DACC1DHR_Pos (4U) \r
+#define DAC_DHR12LD_DACC1DHR_Msk (0xFFFUL << DAC_DHR12LD_DACC1DHR_Pos) /*!< 0x0000FFF0 */\r
+#define DAC_DHR12LD_DACC1DHR DAC_DHR12LD_DACC1DHR_Msk /*!<DAC channel1 12-bit Left aligned data */\r
+#define DAC_DHR12LD_DACC2DHR_Pos (20U) \r
+#define DAC_DHR12LD_DACC2DHR_Msk (0xFFFUL << DAC_DHR12LD_DACC2DHR_Pos) /*!< 0xFFF00000 */\r
+#define DAC_DHR12LD_DACC2DHR DAC_DHR12LD_DACC2DHR_Msk /*!<DAC channel2 12-bit Left aligned data */\r
+\r
+/****************** Bit definition for DAC_DHR8RD register ******************/\r
+#define DAC_DHR8RD_DACC1DHR_Pos (0U) \r
+#define DAC_DHR8RD_DACC1DHR_Msk (0xFFUL << DAC_DHR8RD_DACC1DHR_Pos) /*!< 0x000000FF */\r
+#define DAC_DHR8RD_DACC1DHR DAC_DHR8RD_DACC1DHR_Msk /*!<DAC channel1 8-bit Right aligned data */\r
+#define DAC_DHR8RD_DACC2DHR_Pos (8U) \r
+#define DAC_DHR8RD_DACC2DHR_Msk (0xFFUL << DAC_DHR8RD_DACC2DHR_Pos) /*!< 0x0000FF00 */\r
+#define DAC_DHR8RD_DACC2DHR DAC_DHR8RD_DACC2DHR_Msk /*!<DAC channel2 8-bit Right aligned data */\r
+\r
+/******************* Bit definition for DAC_DOR1 register *******************/\r
+#define DAC_DOR1_DACC1DOR_Pos (0U) \r
+#define DAC_DOR1_DACC1DOR_Msk (0xFFFUL << DAC_DOR1_DACC1DOR_Pos) /*!< 0x00000FFF */\r
+#define DAC_DOR1_DACC1DOR DAC_DOR1_DACC1DOR_Msk /*!<DAC channel1 data output */\r
+\r
+/******************* Bit definition for DAC_DOR2 register *******************/\r
+#define DAC_DOR2_DACC2DOR_Pos (0U) \r
+#define DAC_DOR2_DACC2DOR_Msk (0xFFFUL << DAC_DOR2_DACC2DOR_Pos) /*!< 0x00000FFF */\r
+#define DAC_DOR2_DACC2DOR DAC_DOR2_DACC2DOR_Msk /*!<DAC channel2 data output */\r
+\r
+/******************** Bit definition for DAC_SR register ********************/\r
+#define DAC_SR_DMAUDR1_Pos (13U) \r
+#define DAC_SR_DMAUDR1_Msk (0x1UL << DAC_SR_DMAUDR1_Pos) /*!< 0x00002000 */\r
+#define DAC_SR_DMAUDR1 DAC_SR_DMAUDR1_Msk /*!<DAC channel1 DMA underrun flag */\r
+#define DAC_SR_DMAUDR2_Pos (29U) \r
+#define DAC_SR_DMAUDR2_Msk (0x1UL << DAC_SR_DMAUDR2_Pos) /*!< 0x20000000 */\r
+#define DAC_SR_DMAUDR2 DAC_SR_DMAUDR2_Msk /*!<DAC channel2 DMA underrun flag */\r
+\r
+/******************************************************************************/\r
+/* */\r
+/* Debug MCU (DBGMCU) */\r
+/* */\r
+/******************************************************************************/\r
+\r
+/**************** Bit definition for DBGMCU_IDCODE register *****************/\r
+#define DBGMCU_IDCODE_DEV_ID_Pos (0U) \r
+#define DBGMCU_IDCODE_DEV_ID_Msk (0xFFFUL << DBGMCU_IDCODE_DEV_ID_Pos) /*!< 0x00000FFF */\r
+#define DBGMCU_IDCODE_DEV_ID DBGMCU_IDCODE_DEV_ID_Msk /*!< Device Identifier */\r
+\r
+#define DBGMCU_IDCODE_REV_ID_Pos (16U) \r
+#define DBGMCU_IDCODE_REV_ID_Msk (0xFFFFUL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0xFFFF0000 */\r
+#define DBGMCU_IDCODE_REV_ID DBGMCU_IDCODE_REV_ID_Msk /*!< REV_ID[15:0] bits (Revision Identifier) */\r
+#define DBGMCU_IDCODE_REV_ID_0 (0x0001UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x00010000 */\r
+#define DBGMCU_IDCODE_REV_ID_1 (0x0002UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x00020000 */\r
+#define DBGMCU_IDCODE_REV_ID_2 (0x0004UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x00040000 */\r
+#define DBGMCU_IDCODE_REV_ID_3 (0x0008UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x00080000 */\r
+#define DBGMCU_IDCODE_REV_ID_4 (0x0010UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x00100000 */\r
+#define DBGMCU_IDCODE_REV_ID_5 (0x0020UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x00200000 */\r
+#define DBGMCU_IDCODE_REV_ID_6 (0x0040UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x00400000 */\r
+#define DBGMCU_IDCODE_REV_ID_7 (0x0080UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x00800000 */\r
+#define DBGMCU_IDCODE_REV_ID_8 (0x0100UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x01000000 */\r
+#define DBGMCU_IDCODE_REV_ID_9 (0x0200UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x02000000 */\r
+#define DBGMCU_IDCODE_REV_ID_10 (0x0400UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x04000000 */\r
+#define DBGMCU_IDCODE_REV_ID_11 (0x0800UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x08000000 */\r
+#define DBGMCU_IDCODE_REV_ID_12 (0x1000UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x10000000 */\r
+#define DBGMCU_IDCODE_REV_ID_13 (0x2000UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x20000000 */\r
+#define DBGMCU_IDCODE_REV_ID_14 (0x4000UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x40000000 */\r
+#define DBGMCU_IDCODE_REV_ID_15 (0x8000UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x80000000 */\r
+\r
+/****************** Bit definition for DBGMCU_CR register *******************/\r
+#define DBGMCU_CR_DBG_SLEEP_Pos (0U) \r
+#define DBGMCU_CR_DBG_SLEEP_Msk (0x1UL << DBGMCU_CR_DBG_SLEEP_Pos) /*!< 0x00000001 */\r
+#define DBGMCU_CR_DBG_SLEEP DBGMCU_CR_DBG_SLEEP_Msk /*!< Debug Sleep Mode */\r
+#define DBGMCU_CR_DBG_STOP_Pos (1U) \r
+#define DBGMCU_CR_DBG_STOP_Msk (0x1UL << DBGMCU_CR_DBG_STOP_Pos) /*!< 0x00000002 */\r
+#define DBGMCU_CR_DBG_STOP DBGMCU_CR_DBG_STOP_Msk /*!< Debug Stop Mode */\r
+#define DBGMCU_CR_DBG_STANDBY_Pos (2U) \r
+#define DBGMCU_CR_DBG_STANDBY_Msk (0x1UL << DBGMCU_CR_DBG_STANDBY_Pos) /*!< 0x00000004 */\r
+#define DBGMCU_CR_DBG_STANDBY DBGMCU_CR_DBG_STANDBY_Msk /*!< Debug Standby mode */\r
+#define DBGMCU_CR_TRACE_IOEN_Pos (5U) \r
+#define DBGMCU_CR_TRACE_IOEN_Msk (0x1UL << DBGMCU_CR_TRACE_IOEN_Pos) /*!< 0x00000020 */\r
+#define DBGMCU_CR_TRACE_IOEN DBGMCU_CR_TRACE_IOEN_Msk /*!< Trace Pin Assignment Control */\r
+\r
+#define DBGMCU_CR_TRACE_MODE_Pos (6U) \r
+#define DBGMCU_CR_TRACE_MODE_Msk (0x3UL << DBGMCU_CR_TRACE_MODE_Pos) /*!< 0x000000C0 */\r
+#define DBGMCU_CR_TRACE_MODE DBGMCU_CR_TRACE_MODE_Msk /*!< TRACE_MODE[1:0] bits (Trace Pin Assignment Control) */\r
+#define DBGMCU_CR_TRACE_MODE_0 (0x1UL << DBGMCU_CR_TRACE_MODE_Pos) /*!< 0x00000040 */\r
+#define DBGMCU_CR_TRACE_MODE_1 (0x2UL << DBGMCU_CR_TRACE_MODE_Pos) /*!< 0x00000080 */\r
+\r
+/****************** Bit definition for DBGMCU_APB1_FZ register **************/\r
+\r
+#define DBGMCU_APB1_FZ_DBG_TIM2_STOP_Pos (0U) \r
+#define DBGMCU_APB1_FZ_DBG_TIM2_STOP_Msk (0x1UL << DBGMCU_APB1_FZ_DBG_TIM2_STOP_Pos) /*!< 0x00000001 */\r
+#define DBGMCU_APB1_FZ_DBG_TIM2_STOP DBGMCU_APB1_FZ_DBG_TIM2_STOP_Msk /*!< TIM2 counter stopped when core is halted */\r
+#define DBGMCU_APB1_FZ_DBG_TIM3_STOP_Pos (1U) \r
+#define DBGMCU_APB1_FZ_DBG_TIM3_STOP_Msk (0x1UL << DBGMCU_APB1_FZ_DBG_TIM3_STOP_Pos) /*!< 0x00000002 */\r
+#define DBGMCU_APB1_FZ_DBG_TIM3_STOP DBGMCU_APB1_FZ_DBG_TIM3_STOP_Msk /*!< TIM3 counter stopped when core is halted */\r
+#define DBGMCU_APB1_FZ_DBG_TIM4_STOP_Pos (2U) \r
+#define DBGMCU_APB1_FZ_DBG_TIM4_STOP_Msk (0x1UL << DBGMCU_APB1_FZ_DBG_TIM4_STOP_Pos) /*!< 0x00000004 */\r
+#define DBGMCU_APB1_FZ_DBG_TIM4_STOP DBGMCU_APB1_FZ_DBG_TIM4_STOP_Msk /*!< TIM4 counter stopped when core is halted */\r
+#define DBGMCU_APB1_FZ_DBG_TIM5_STOP_Pos (3U) \r
+#define DBGMCU_APB1_FZ_DBG_TIM5_STOP_Msk (0x1UL << DBGMCU_APB1_FZ_DBG_TIM5_STOP_Pos) /*!< 0x00000008 */\r
+#define DBGMCU_APB1_FZ_DBG_TIM5_STOP DBGMCU_APB1_FZ_DBG_TIM5_STOP_Msk /*!< TIM5 counter stopped when core is halted */\r
+#define DBGMCU_APB1_FZ_DBG_TIM6_STOP_Pos (4U) \r
+#define DBGMCU_APB1_FZ_DBG_TIM6_STOP_Msk (0x1UL << DBGMCU_APB1_FZ_DBG_TIM6_STOP_Pos) /*!< 0x00000010 */\r
+#define DBGMCU_APB1_FZ_DBG_TIM6_STOP DBGMCU_APB1_FZ_DBG_TIM6_STOP_Msk /*!< TIM6 counter stopped when core is halted */\r
+#define DBGMCU_APB1_FZ_DBG_TIM7_STOP_Pos (5U) \r
+#define DBGMCU_APB1_FZ_DBG_TIM7_STOP_Msk (0x1UL << DBGMCU_APB1_FZ_DBG_TIM7_STOP_Pos) /*!< 0x00000020 */\r
+#define DBGMCU_APB1_FZ_DBG_TIM7_STOP DBGMCU_APB1_FZ_DBG_TIM7_STOP_Msk /*!< TIM7 counter stopped when core is halted */\r
+#define DBGMCU_APB1_FZ_DBG_RTC_STOP_Pos (10U) \r
+#define DBGMCU_APB1_FZ_DBG_RTC_STOP_Msk (0x1UL << DBGMCU_APB1_FZ_DBG_RTC_STOP_Pos) /*!< 0x00000400 */\r
+#define DBGMCU_APB1_FZ_DBG_RTC_STOP DBGMCU_APB1_FZ_DBG_RTC_STOP_Msk /*!< RTC Counter stopped when Core is halted */\r
+#define DBGMCU_APB1_FZ_DBG_WWDG_STOP_Pos (11U) \r
+#define DBGMCU_APB1_FZ_DBG_WWDG_STOP_Msk (0x1UL << DBGMCU_APB1_FZ_DBG_WWDG_STOP_Pos) /*!< 0x00000800 */\r
+#define DBGMCU_APB1_FZ_DBG_WWDG_STOP DBGMCU_APB1_FZ_DBG_WWDG_STOP_Msk /*!< Debug Window Watchdog stopped when Core is halted */\r
+#define DBGMCU_APB1_FZ_DBG_IWDG_STOP_Pos (12U) \r
+#define DBGMCU_APB1_FZ_DBG_IWDG_STOP_Msk (0x1UL << DBGMCU_APB1_FZ_DBG_IWDG_STOP_Pos) /*!< 0x00001000 */\r
+#define DBGMCU_APB1_FZ_DBG_IWDG_STOP DBGMCU_APB1_FZ_DBG_IWDG_STOP_Msk /*!< Debug Independent Watchdog stopped when Core is halted */\r
+#define DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT_Pos (21U) \r
+#define DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT_Msk (0x1UL << DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT_Pos) /*!< 0x00200000 */\r
+#define DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT_Msk /*!< SMBUS timeout mode stopped when Core is halted */\r
+#define DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT_Pos (22U) \r
+#define DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT_Msk (0x1UL << DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT_Pos) /*!< 0x00400000 */\r
+#define DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT_Msk /*!< SMBUS timeout mode stopped when Core is halted */\r
+\r
+/****************** Bit definition for DBGMCU_APB2_FZ register **************/\r
+\r
+#define DBGMCU_APB2_FZ_DBG_TIM9_STOP_Pos (2U) \r
+#define DBGMCU_APB2_FZ_DBG_TIM9_STOP_Msk (0x1UL << DBGMCU_APB2_FZ_DBG_TIM9_STOP_Pos) /*!< 0x00000004 */\r
+#define DBGMCU_APB2_FZ_DBG_TIM9_STOP DBGMCU_APB2_FZ_DBG_TIM9_STOP_Msk /*!< TIM9 counter stopped when core is halted */\r
+#define DBGMCU_APB2_FZ_DBG_TIM10_STOP_Pos (3U) \r
+#define DBGMCU_APB2_FZ_DBG_TIM10_STOP_Msk (0x1UL << DBGMCU_APB2_FZ_DBG_TIM10_STOP_Pos) /*!< 0x00000008 */\r
+#define DBGMCU_APB2_FZ_DBG_TIM10_STOP DBGMCU_APB2_FZ_DBG_TIM10_STOP_Msk /*!< TIM10 counter stopped when core is halted */\r
+#define DBGMCU_APB2_FZ_DBG_TIM11_STOP_Pos (4U) \r
+#define DBGMCU_APB2_FZ_DBG_TIM11_STOP_Msk (0x1UL << DBGMCU_APB2_FZ_DBG_TIM11_STOP_Pos) /*!< 0x00000010 */\r
+#define DBGMCU_APB2_FZ_DBG_TIM11_STOP DBGMCU_APB2_FZ_DBG_TIM11_STOP_Msk /*!< TIM11 counter stopped when core is halted */\r
+\r
+/******************************************************************************/\r
+/* */\r
+/* DMA Controller (DMA) */\r
+/* */\r
+/******************************************************************************/\r
+\r
+/******************* Bit definition for DMA_ISR register ********************/\r
+#define DMA_ISR_GIF1_Pos (0U) \r
+#define DMA_ISR_GIF1_Msk (0x1UL << DMA_ISR_GIF1_Pos) /*!< 0x00000001 */\r
+#define DMA_ISR_GIF1 DMA_ISR_GIF1_Msk /*!< Channel 1 Global interrupt flag */\r
+#define DMA_ISR_TCIF1_Pos (1U) \r
+#define DMA_ISR_TCIF1_Msk (0x1UL << DMA_ISR_TCIF1_Pos) /*!< 0x00000002 */\r
+#define DMA_ISR_TCIF1 DMA_ISR_TCIF1_Msk /*!< Channel 1 Transfer Complete flag */\r
+#define DMA_ISR_HTIF1_Pos (2U) \r
+#define DMA_ISR_HTIF1_Msk (0x1UL << DMA_ISR_HTIF1_Pos) /*!< 0x00000004 */\r
+#define DMA_ISR_HTIF1 DMA_ISR_HTIF1_Msk /*!< Channel 1 Half Transfer flag */\r
+#define DMA_ISR_TEIF1_Pos (3U) \r
+#define DMA_ISR_TEIF1_Msk (0x1UL << DMA_ISR_TEIF1_Pos) /*!< 0x00000008 */\r
+#define DMA_ISR_TEIF1 DMA_ISR_TEIF1_Msk /*!< Channel 1 Transfer Error flag */\r
+#define DMA_ISR_GIF2_Pos (4U) \r
+#define DMA_ISR_GIF2_Msk (0x1UL << DMA_ISR_GIF2_Pos) /*!< 0x00000010 */\r
+#define DMA_ISR_GIF2 DMA_ISR_GIF2_Msk /*!< Channel 2 Global interrupt flag */\r
+#define DMA_ISR_TCIF2_Pos (5U) \r
+#define DMA_ISR_TCIF2_Msk (0x1UL << DMA_ISR_TCIF2_Pos) /*!< 0x00000020 */\r
+#define DMA_ISR_TCIF2 DMA_ISR_TCIF2_Msk /*!< Channel 2 Transfer Complete flag */\r
+#define DMA_ISR_HTIF2_Pos (6U) \r
+#define DMA_ISR_HTIF2_Msk (0x1UL << DMA_ISR_HTIF2_Pos) /*!< 0x00000040 */\r
+#define DMA_ISR_HTIF2 DMA_ISR_HTIF2_Msk /*!< Channel 2 Half Transfer flag */\r
+#define DMA_ISR_TEIF2_Pos (7U) \r
+#define DMA_ISR_TEIF2_Msk (0x1UL << DMA_ISR_TEIF2_Pos) /*!< 0x00000080 */\r
+#define DMA_ISR_TEIF2 DMA_ISR_TEIF2_Msk /*!< Channel 2 Transfer Error flag */\r
+#define DMA_ISR_GIF3_Pos (8U) \r
+#define DMA_ISR_GIF3_Msk (0x1UL << DMA_ISR_GIF3_Pos) /*!< 0x00000100 */\r
+#define DMA_ISR_GIF3 DMA_ISR_GIF3_Msk /*!< Channel 3 Global interrupt flag */\r
+#define DMA_ISR_TCIF3_Pos (9U) \r
+#define DMA_ISR_TCIF3_Msk (0x1UL << DMA_ISR_TCIF3_Pos) /*!< 0x00000200 */\r
+#define DMA_ISR_TCIF3 DMA_ISR_TCIF3_Msk /*!< Channel 3 Transfer Complete flag */\r
+#define DMA_ISR_HTIF3_Pos (10U) \r
+#define DMA_ISR_HTIF3_Msk (0x1UL << DMA_ISR_HTIF3_Pos) /*!< 0x00000400 */\r
+#define DMA_ISR_HTIF3 DMA_ISR_HTIF3_Msk /*!< Channel 3 Half Transfer flag */\r
+#define DMA_ISR_TEIF3_Pos (11U) \r
+#define DMA_ISR_TEIF3_Msk (0x1UL << DMA_ISR_TEIF3_Pos) /*!< 0x00000800 */\r
+#define DMA_ISR_TEIF3 DMA_ISR_TEIF3_Msk /*!< Channel 3 Transfer Error flag */\r
+#define DMA_ISR_GIF4_Pos (12U) \r
+#define DMA_ISR_GIF4_Msk (0x1UL << DMA_ISR_GIF4_Pos) /*!< 0x00001000 */\r
+#define DMA_ISR_GIF4 DMA_ISR_GIF4_Msk /*!< Channel 4 Global interrupt flag */\r
+#define DMA_ISR_TCIF4_Pos (13U) \r
+#define DMA_ISR_TCIF4_Msk (0x1UL << DMA_ISR_TCIF4_Pos) /*!< 0x00002000 */\r
+#define DMA_ISR_TCIF4 DMA_ISR_TCIF4_Msk /*!< Channel 4 Transfer Complete flag */\r
+#define DMA_ISR_HTIF4_Pos (14U) \r
+#define DMA_ISR_HTIF4_Msk (0x1UL << DMA_ISR_HTIF4_Pos) /*!< 0x00004000 */\r
+#define DMA_ISR_HTIF4 DMA_ISR_HTIF4_Msk /*!< Channel 4 Half Transfer flag */\r
+#define DMA_ISR_TEIF4_Pos (15U) \r
+#define DMA_ISR_TEIF4_Msk (0x1UL << DMA_ISR_TEIF4_Pos) /*!< 0x00008000 */\r
+#define DMA_ISR_TEIF4 DMA_ISR_TEIF4_Msk /*!< Channel 4 Transfer Error flag */\r
+#define DMA_ISR_GIF5_Pos (16U) \r
+#define DMA_ISR_GIF5_Msk (0x1UL << DMA_ISR_GIF5_Pos) /*!< 0x00010000 */\r
+#define DMA_ISR_GIF5 DMA_ISR_GIF5_Msk /*!< Channel 5 Global interrupt flag */\r
+#define DMA_ISR_TCIF5_Pos (17U) \r
+#define DMA_ISR_TCIF5_Msk (0x1UL << DMA_ISR_TCIF5_Pos) /*!< 0x00020000 */\r
+#define DMA_ISR_TCIF5 DMA_ISR_TCIF5_Msk /*!< Channel 5 Transfer Complete flag */\r
+#define DMA_ISR_HTIF5_Pos (18U) \r
+#define DMA_ISR_HTIF5_Msk (0x1UL << DMA_ISR_HTIF5_Pos) /*!< 0x00040000 */\r
+#define DMA_ISR_HTIF5 DMA_ISR_HTIF5_Msk /*!< Channel 5 Half Transfer flag */\r
+#define DMA_ISR_TEIF5_Pos (19U) \r
+#define DMA_ISR_TEIF5_Msk (0x1UL << DMA_ISR_TEIF5_Pos) /*!< 0x00080000 */\r
+#define DMA_ISR_TEIF5 DMA_ISR_TEIF5_Msk /*!< Channel 5 Transfer Error flag */\r
+#define DMA_ISR_GIF6_Pos (20U) \r
+#define DMA_ISR_GIF6_Msk (0x1UL << DMA_ISR_GIF6_Pos) /*!< 0x00100000 */\r
+#define DMA_ISR_GIF6 DMA_ISR_GIF6_Msk /*!< Channel 6 Global interrupt flag */\r
+#define DMA_ISR_TCIF6_Pos (21U) \r
+#define DMA_ISR_TCIF6_Msk (0x1UL << DMA_ISR_TCIF6_Pos) /*!< 0x00200000 */\r
+#define DMA_ISR_TCIF6 DMA_ISR_TCIF6_Msk /*!< Channel 6 Transfer Complete flag */\r
+#define DMA_ISR_HTIF6_Pos (22U) \r
+#define DMA_ISR_HTIF6_Msk (0x1UL << DMA_ISR_HTIF6_Pos) /*!< 0x00400000 */\r
+#define DMA_ISR_HTIF6 DMA_ISR_HTIF6_Msk /*!< Channel 6 Half Transfer flag */\r
+#define DMA_ISR_TEIF6_Pos (23U) \r
+#define DMA_ISR_TEIF6_Msk (0x1UL << DMA_ISR_TEIF6_Pos) /*!< 0x00800000 */\r
+#define DMA_ISR_TEIF6 DMA_ISR_TEIF6_Msk /*!< Channel 6 Transfer Error flag */\r
+#define DMA_ISR_GIF7_Pos (24U) \r
+#define DMA_ISR_GIF7_Msk (0x1UL << DMA_ISR_GIF7_Pos) /*!< 0x01000000 */\r
+#define DMA_ISR_GIF7 DMA_ISR_GIF7_Msk /*!< Channel 7 Global interrupt flag */\r
+#define DMA_ISR_TCIF7_Pos (25U) \r
+#define DMA_ISR_TCIF7_Msk (0x1UL << DMA_ISR_TCIF7_Pos) /*!< 0x02000000 */\r
+#define DMA_ISR_TCIF7 DMA_ISR_TCIF7_Msk /*!< Channel 7 Transfer Complete flag */\r
+#define DMA_ISR_HTIF7_Pos (26U) \r
+#define DMA_ISR_HTIF7_Msk (0x1UL << DMA_ISR_HTIF7_Pos) /*!< 0x04000000 */\r
+#define DMA_ISR_HTIF7 DMA_ISR_HTIF7_Msk /*!< Channel 7 Half Transfer flag */\r
+#define DMA_ISR_TEIF7_Pos (27U) \r
+#define DMA_ISR_TEIF7_Msk (0x1UL << DMA_ISR_TEIF7_Pos) /*!< 0x08000000 */\r
+#define DMA_ISR_TEIF7 DMA_ISR_TEIF7_Msk /*!< Channel 7 Transfer Error flag */\r
+\r
+/******************* Bit definition for DMA_IFCR register *******************/\r
+#define DMA_IFCR_CGIF1_Pos (0U) \r
+#define DMA_IFCR_CGIF1_Msk (0x1UL << DMA_IFCR_CGIF1_Pos) /*!< 0x00000001 */\r
+#define DMA_IFCR_CGIF1 DMA_IFCR_CGIF1_Msk /*!< Channel 1 Global interrupt clear */\r
+#define DMA_IFCR_CTCIF1_Pos (1U) \r
+#define DMA_IFCR_CTCIF1_Msk (0x1UL << DMA_IFCR_CTCIF1_Pos) /*!< 0x00000002 */\r
+#define DMA_IFCR_CTCIF1 DMA_IFCR_CTCIF1_Msk /*!< Channel 1 Transfer Complete clear */\r
+#define DMA_IFCR_CHTIF1_Pos (2U) \r
+#define DMA_IFCR_CHTIF1_Msk (0x1UL << DMA_IFCR_CHTIF1_Pos) /*!< 0x00000004 */\r
+#define DMA_IFCR_CHTIF1 DMA_IFCR_CHTIF1_Msk /*!< Channel 1 Half Transfer clear */\r
+#define DMA_IFCR_CTEIF1_Pos (3U) \r
+#define DMA_IFCR_CTEIF1_Msk (0x1UL << DMA_IFCR_CTEIF1_Pos) /*!< 0x00000008 */\r
+#define DMA_IFCR_CTEIF1 DMA_IFCR_CTEIF1_Msk /*!< Channel 1 Transfer Error clear */\r
+#define DMA_IFCR_CGIF2_Pos (4U) \r
+#define DMA_IFCR_CGIF2_Msk (0x1UL << DMA_IFCR_CGIF2_Pos) /*!< 0x00000010 */\r
+#define DMA_IFCR_CGIF2 DMA_IFCR_CGIF2_Msk /*!< Channel 2 Global interrupt clear */\r
+#define DMA_IFCR_CTCIF2_Pos (5U) \r
+#define DMA_IFCR_CTCIF2_Msk (0x1UL << DMA_IFCR_CTCIF2_Pos) /*!< 0x00000020 */\r
+#define DMA_IFCR_CTCIF2 DMA_IFCR_CTCIF2_Msk /*!< Channel 2 Transfer Complete clear */\r
+#define DMA_IFCR_CHTIF2_Pos (6U) \r
+#define DMA_IFCR_CHTIF2_Msk (0x1UL << DMA_IFCR_CHTIF2_Pos) /*!< 0x00000040 */\r
+#define DMA_IFCR_CHTIF2 DMA_IFCR_CHTIF2_Msk /*!< Channel 2 Half Transfer clear */\r
+#define DMA_IFCR_CTEIF2_Pos (7U) \r
+#define DMA_IFCR_CTEIF2_Msk (0x1UL << DMA_IFCR_CTEIF2_Pos) /*!< 0x00000080 */\r
+#define DMA_IFCR_CTEIF2 DMA_IFCR_CTEIF2_Msk /*!< Channel 2 Transfer Error clear */\r
+#define DMA_IFCR_CGIF3_Pos (8U) \r
+#define DMA_IFCR_CGIF3_Msk (0x1UL << DMA_IFCR_CGIF3_Pos) /*!< 0x00000100 */\r
+#define DMA_IFCR_CGIF3 DMA_IFCR_CGIF3_Msk /*!< Channel 3 Global interrupt clear */\r
+#define DMA_IFCR_CTCIF3_Pos (9U) \r
+#define DMA_IFCR_CTCIF3_Msk (0x1UL << DMA_IFCR_CTCIF3_Pos) /*!< 0x00000200 */\r
+#define DMA_IFCR_CTCIF3 DMA_IFCR_CTCIF3_Msk /*!< Channel 3 Transfer Complete clear */\r
+#define DMA_IFCR_CHTIF3_Pos (10U) \r
+#define DMA_IFCR_CHTIF3_Msk (0x1UL << DMA_IFCR_CHTIF3_Pos) /*!< 0x00000400 */\r
+#define DMA_IFCR_CHTIF3 DMA_IFCR_CHTIF3_Msk /*!< Channel 3 Half Transfer clear */\r
+#define DMA_IFCR_CTEIF3_Pos (11U) \r
+#define DMA_IFCR_CTEIF3_Msk (0x1UL << DMA_IFCR_CTEIF3_Pos) /*!< 0x00000800 */\r
+#define DMA_IFCR_CTEIF3 DMA_IFCR_CTEIF3_Msk /*!< Channel 3 Transfer Error clear */\r
+#define DMA_IFCR_CGIF4_Pos (12U) \r
+#define DMA_IFCR_CGIF4_Msk (0x1UL << DMA_IFCR_CGIF4_Pos) /*!< 0x00001000 */\r
+#define DMA_IFCR_CGIF4 DMA_IFCR_CGIF4_Msk /*!< Channel 4 Global interrupt clear */\r
+#define DMA_IFCR_CTCIF4_Pos (13U) \r
+#define DMA_IFCR_CTCIF4_Msk (0x1UL << DMA_IFCR_CTCIF4_Pos) /*!< 0x00002000 */\r
+#define DMA_IFCR_CTCIF4 DMA_IFCR_CTCIF4_Msk /*!< Channel 4 Transfer Complete clear */\r
+#define DMA_IFCR_CHTIF4_Pos (14U) \r
+#define DMA_IFCR_CHTIF4_Msk (0x1UL << DMA_IFCR_CHTIF4_Pos) /*!< 0x00004000 */\r
+#define DMA_IFCR_CHTIF4 DMA_IFCR_CHTIF4_Msk /*!< Channel 4 Half Transfer clear */\r
+#define DMA_IFCR_CTEIF4_Pos (15U) \r
+#define DMA_IFCR_CTEIF4_Msk (0x1UL << DMA_IFCR_CTEIF4_Pos) /*!< 0x00008000 */\r
+#define DMA_IFCR_CTEIF4 DMA_IFCR_CTEIF4_Msk /*!< Channel 4 Transfer Error clear */\r
+#define DMA_IFCR_CGIF5_Pos (16U) \r
+#define DMA_IFCR_CGIF5_Msk (0x1UL << DMA_IFCR_CGIF5_Pos) /*!< 0x00010000 */\r
+#define DMA_IFCR_CGIF5 DMA_IFCR_CGIF5_Msk /*!< Channel 5 Global interrupt clear */\r
+#define DMA_IFCR_CTCIF5_Pos (17U) \r
+#define DMA_IFCR_CTCIF5_Msk (0x1UL << DMA_IFCR_CTCIF5_Pos) /*!< 0x00020000 */\r
+#define DMA_IFCR_CTCIF5 DMA_IFCR_CTCIF5_Msk /*!< Channel 5 Transfer Complete clear */\r
+#define DMA_IFCR_CHTIF5_Pos (18U) \r
+#define DMA_IFCR_CHTIF5_Msk (0x1UL << DMA_IFCR_CHTIF5_Pos) /*!< 0x00040000 */\r
+#define DMA_IFCR_CHTIF5 DMA_IFCR_CHTIF5_Msk /*!< Channel 5 Half Transfer clear */\r
+#define DMA_IFCR_CTEIF5_Pos (19U) \r
+#define DMA_IFCR_CTEIF5_Msk (0x1UL << DMA_IFCR_CTEIF5_Pos) /*!< 0x00080000 */\r
+#define DMA_IFCR_CTEIF5 DMA_IFCR_CTEIF5_Msk /*!< Channel 5 Transfer Error clear */\r
+#define DMA_IFCR_CGIF6_Pos (20U) \r
+#define DMA_IFCR_CGIF6_Msk (0x1UL << DMA_IFCR_CGIF6_Pos) /*!< 0x00100000 */\r
+#define DMA_IFCR_CGIF6 DMA_IFCR_CGIF6_Msk /*!< Channel 6 Global interrupt clear */\r
+#define DMA_IFCR_CTCIF6_Pos (21U) \r
+#define DMA_IFCR_CTCIF6_Msk (0x1UL << DMA_IFCR_CTCIF6_Pos) /*!< 0x00200000 */\r
+#define DMA_IFCR_CTCIF6 DMA_IFCR_CTCIF6_Msk /*!< Channel 6 Transfer Complete clear */\r
+#define DMA_IFCR_CHTIF6_Pos (22U) \r
+#define DMA_IFCR_CHTIF6_Msk (0x1UL << DMA_IFCR_CHTIF6_Pos) /*!< 0x00400000 */\r
+#define DMA_IFCR_CHTIF6 DMA_IFCR_CHTIF6_Msk /*!< Channel 6 Half Transfer clear */\r
+#define DMA_IFCR_CTEIF6_Pos (23U) \r
+#define DMA_IFCR_CTEIF6_Msk (0x1UL << DMA_IFCR_CTEIF6_Pos) /*!< 0x00800000 */\r
+#define DMA_IFCR_CTEIF6 DMA_IFCR_CTEIF6_Msk /*!< Channel 6 Transfer Error clear */\r
+#define DMA_IFCR_CGIF7_Pos (24U) \r
+#define DMA_IFCR_CGIF7_Msk (0x1UL << DMA_IFCR_CGIF7_Pos) /*!< 0x01000000 */\r
+#define DMA_IFCR_CGIF7 DMA_IFCR_CGIF7_Msk /*!< Channel 7 Global interrupt clear */\r
+#define DMA_IFCR_CTCIF7_Pos (25U) \r
+#define DMA_IFCR_CTCIF7_Msk (0x1UL << DMA_IFCR_CTCIF7_Pos) /*!< 0x02000000 */\r
+#define DMA_IFCR_CTCIF7 DMA_IFCR_CTCIF7_Msk /*!< Channel 7 Transfer Complete clear */\r
+#define DMA_IFCR_CHTIF7_Pos (26U) \r
+#define DMA_IFCR_CHTIF7_Msk (0x1UL << DMA_IFCR_CHTIF7_Pos) /*!< 0x04000000 */\r
+#define DMA_IFCR_CHTIF7 DMA_IFCR_CHTIF7_Msk /*!< Channel 7 Half Transfer clear */\r
+#define DMA_IFCR_CTEIF7_Pos (27U) \r
+#define DMA_IFCR_CTEIF7_Msk (0x1UL << DMA_IFCR_CTEIF7_Pos) /*!< 0x08000000 */\r
+#define DMA_IFCR_CTEIF7 DMA_IFCR_CTEIF7_Msk /*!< Channel 7 Transfer Error clear */\r
+\r
+/******************* Bit definition for DMA_CCR register *******************/\r
+#define DMA_CCR_EN_Pos (0U) \r
+#define DMA_CCR_EN_Msk (0x1UL << DMA_CCR_EN_Pos) /*!< 0x00000001 */\r
+#define DMA_CCR_EN DMA_CCR_EN_Msk /*!< Channel enable*/\r
+#define DMA_CCR_TCIE_Pos (1U) \r
+#define DMA_CCR_TCIE_Msk (0x1UL << DMA_CCR_TCIE_Pos) /*!< 0x00000002 */\r
+#define DMA_CCR_TCIE DMA_CCR_TCIE_Msk /*!< Transfer complete interrupt enable */\r
+#define DMA_CCR_HTIE_Pos (2U) \r
+#define DMA_CCR_HTIE_Msk (0x1UL << DMA_CCR_HTIE_Pos) /*!< 0x00000004 */\r
+#define DMA_CCR_HTIE DMA_CCR_HTIE_Msk /*!< Half Transfer interrupt enable */\r
+#define DMA_CCR_TEIE_Pos (3U) \r
+#define DMA_CCR_TEIE_Msk (0x1UL << DMA_CCR_TEIE_Pos) /*!< 0x00000008 */\r
+#define DMA_CCR_TEIE DMA_CCR_TEIE_Msk /*!< Transfer error interrupt enable */\r
+#define DMA_CCR_DIR_Pos (4U) \r
+#define DMA_CCR_DIR_Msk (0x1UL << DMA_CCR_DIR_Pos) /*!< 0x00000010 */\r
+#define DMA_CCR_DIR DMA_CCR_DIR_Msk /*!< Data transfer direction */\r
+#define DMA_CCR_CIRC_Pos (5U) \r
+#define DMA_CCR_CIRC_Msk (0x1UL << DMA_CCR_CIRC_Pos) /*!< 0x00000020 */\r
+#define DMA_CCR_CIRC DMA_CCR_CIRC_Msk /*!< Circular mode */\r
+#define DMA_CCR_PINC_Pos (6U) \r
+#define DMA_CCR_PINC_Msk (0x1UL << DMA_CCR_PINC_Pos) /*!< 0x00000040 */\r
+#define DMA_CCR_PINC DMA_CCR_PINC_Msk /*!< Peripheral increment mode */\r
+#define DMA_CCR_MINC_Pos (7U) \r
+#define DMA_CCR_MINC_Msk (0x1UL << DMA_CCR_MINC_Pos) /*!< 0x00000080 */\r
+#define DMA_CCR_MINC DMA_CCR_MINC_Msk /*!< Memory increment mode */\r
+\r
+#define DMA_CCR_PSIZE_Pos (8U) \r
+#define DMA_CCR_PSIZE_Msk (0x3UL << DMA_CCR_PSIZE_Pos) /*!< 0x00000300 */\r
+#define DMA_CCR_PSIZE DMA_CCR_PSIZE_Msk /*!< PSIZE[1:0] bits (Peripheral size) */\r
+#define DMA_CCR_PSIZE_0 (0x1UL << DMA_CCR_PSIZE_Pos) /*!< 0x00000100 */\r
+#define DMA_CCR_PSIZE_1 (0x2UL << DMA_CCR_PSIZE_Pos) /*!< 0x00000200 */\r
+\r
+#define DMA_CCR_MSIZE_Pos (10U) \r
+#define DMA_CCR_MSIZE_Msk (0x3UL << DMA_CCR_MSIZE_Pos) /*!< 0x00000C00 */\r
+#define DMA_CCR_MSIZE DMA_CCR_MSIZE_Msk /*!< MSIZE[1:0] bits (Memory size) */\r
+#define DMA_CCR_MSIZE_0 (0x1UL << DMA_CCR_MSIZE_Pos) /*!< 0x00000400 */\r
+#define DMA_CCR_MSIZE_1 (0x2UL << DMA_CCR_MSIZE_Pos) /*!< 0x00000800 */\r
+\r
+#define DMA_CCR_PL_Pos (12U) \r
+#define DMA_CCR_PL_Msk (0x3UL << DMA_CCR_PL_Pos) /*!< 0x00003000 */\r
+#define DMA_CCR_PL DMA_CCR_PL_Msk /*!< PL[1:0] bits(Channel Priority level) */\r
+#define DMA_CCR_PL_0 (0x1UL << DMA_CCR_PL_Pos) /*!< 0x00001000 */\r
+#define DMA_CCR_PL_1 (0x2UL << DMA_CCR_PL_Pos) /*!< 0x00002000 */\r
+\r
+#define DMA_CCR_MEM2MEM_Pos (14U) \r
+#define DMA_CCR_MEM2MEM_Msk (0x1UL << DMA_CCR_MEM2MEM_Pos) /*!< 0x00004000 */\r
+#define DMA_CCR_MEM2MEM DMA_CCR_MEM2MEM_Msk /*!< Memory to memory mode */\r
+\r
+/****************** Bit definition generic for DMA_CNDTR register *******************/\r
+#define DMA_CNDTR_NDT_Pos (0U) \r
+#define DMA_CNDTR_NDT_Msk (0xFFFFUL << DMA_CNDTR_NDT_Pos) /*!< 0x0000FFFF */\r
+#define DMA_CNDTR_NDT DMA_CNDTR_NDT_Msk /*!< Number of data to Transfer */\r
+\r
+/****************** Bit definition for DMA_CNDTR1 register ******************/\r
+#define DMA_CNDTR1_NDT_Pos (0U) \r
+#define DMA_CNDTR1_NDT_Msk (0xFFFFUL << DMA_CNDTR1_NDT_Pos) /*!< 0x0000FFFF */\r
+#define DMA_CNDTR1_NDT DMA_CNDTR1_NDT_Msk /*!< Number of data to Transfer */\r
+\r
+/****************** Bit definition for DMA_CNDTR2 register ******************/\r
+#define DMA_CNDTR2_NDT_Pos (0U) \r
+#define DMA_CNDTR2_NDT_Msk (0xFFFFUL << DMA_CNDTR2_NDT_Pos) /*!< 0x0000FFFF */\r
+#define DMA_CNDTR2_NDT DMA_CNDTR2_NDT_Msk /*!< Number of data to Transfer */\r
+\r
+/****************** Bit definition for DMA_CNDTR3 register ******************/\r
+#define DMA_CNDTR3_NDT_Pos (0U) \r
+#define DMA_CNDTR3_NDT_Msk (0xFFFFUL << DMA_CNDTR3_NDT_Pos) /*!< 0x0000FFFF */\r
+#define DMA_CNDTR3_NDT DMA_CNDTR3_NDT_Msk /*!< Number of data to Transfer */\r
+\r
+/****************** Bit definition for DMA_CNDTR4 register ******************/\r
+#define DMA_CNDTR4_NDT_Pos (0U) \r
+#define DMA_CNDTR4_NDT_Msk (0xFFFFUL << DMA_CNDTR4_NDT_Pos) /*!< 0x0000FFFF */\r
+#define DMA_CNDTR4_NDT DMA_CNDTR4_NDT_Msk /*!< Number of data to Transfer */\r
+\r
+/****************** Bit definition for DMA_CNDTR5 register ******************/\r
+#define DMA_CNDTR5_NDT_Pos (0U) \r
+#define DMA_CNDTR5_NDT_Msk (0xFFFFUL << DMA_CNDTR5_NDT_Pos) /*!< 0x0000FFFF */\r
+#define DMA_CNDTR5_NDT DMA_CNDTR5_NDT_Msk /*!< Number of data to Transfer */\r
+\r
+/****************** Bit definition for DMA_CNDTR6 register ******************/\r
+#define DMA_CNDTR6_NDT_Pos (0U) \r
+#define DMA_CNDTR6_NDT_Msk (0xFFFFUL << DMA_CNDTR6_NDT_Pos) /*!< 0x0000FFFF */\r
+#define DMA_CNDTR6_NDT DMA_CNDTR6_NDT_Msk /*!< Number of data to Transfer */\r
+\r
+/****************** Bit definition for DMA_CNDTR7 register ******************/\r
+#define DMA_CNDTR7_NDT_Pos (0U) \r
+#define DMA_CNDTR7_NDT_Msk (0xFFFFUL << DMA_CNDTR7_NDT_Pos) /*!< 0x0000FFFF */\r
+#define DMA_CNDTR7_NDT DMA_CNDTR7_NDT_Msk /*!< Number of data to Transfer */\r
+\r
+/****************** Bit definition generic for DMA_CPAR register ********************/\r
+#define DMA_CPAR_PA_Pos (0U) \r
+#define DMA_CPAR_PA_Msk (0xFFFFFFFFUL << DMA_CPAR_PA_Pos) /*!< 0xFFFFFFFF */\r
+#define DMA_CPAR_PA DMA_CPAR_PA_Msk /*!< Peripheral Address */\r
+\r
+/****************** Bit definition for DMA_CPAR1 register *******************/\r
+#define DMA_CPAR1_PA_Pos (0U) \r
+#define DMA_CPAR1_PA_Msk (0xFFFFFFFFUL << DMA_CPAR1_PA_Pos) /*!< 0xFFFFFFFF */\r
+#define DMA_CPAR1_PA DMA_CPAR1_PA_Msk /*!< Peripheral Address */\r
+\r
+/****************** Bit definition for DMA_CPAR2 register *******************/\r
+#define DMA_CPAR2_PA_Pos (0U) \r
+#define DMA_CPAR2_PA_Msk (0xFFFFFFFFUL << DMA_CPAR2_PA_Pos) /*!< 0xFFFFFFFF */\r
+#define DMA_CPAR2_PA DMA_CPAR2_PA_Msk /*!< Peripheral Address */\r
+\r
+/****************** Bit definition for DMA_CPAR3 register *******************/\r
+#define DMA_CPAR3_PA_Pos (0U) \r
+#define DMA_CPAR3_PA_Msk (0xFFFFFFFFUL << DMA_CPAR3_PA_Pos) /*!< 0xFFFFFFFF */\r
+#define DMA_CPAR3_PA DMA_CPAR3_PA_Msk /*!< Peripheral Address */\r
+\r
+\r
+/****************** Bit definition for DMA_CPAR4 register *******************/\r
+#define DMA_CPAR4_PA_Pos (0U) \r
+#define DMA_CPAR4_PA_Msk (0xFFFFFFFFUL << DMA_CPAR4_PA_Pos) /*!< 0xFFFFFFFF */\r
+#define DMA_CPAR4_PA DMA_CPAR4_PA_Msk /*!< Peripheral Address */\r
+\r
+/****************** Bit definition for DMA_CPAR5 register *******************/\r
+#define DMA_CPAR5_PA_Pos (0U) \r
+#define DMA_CPAR5_PA_Msk (0xFFFFFFFFUL << DMA_CPAR5_PA_Pos) /*!< 0xFFFFFFFF */\r
+#define DMA_CPAR5_PA DMA_CPAR5_PA_Msk /*!< Peripheral Address */\r
+\r
+/****************** Bit definition for DMA_CPAR6 register *******************/\r
+#define DMA_CPAR6_PA_Pos (0U) \r
+#define DMA_CPAR6_PA_Msk (0xFFFFFFFFUL << DMA_CPAR6_PA_Pos) /*!< 0xFFFFFFFF */\r
+#define DMA_CPAR6_PA DMA_CPAR6_PA_Msk /*!< Peripheral Address */\r
+\r
+\r
+/****************** Bit definition for DMA_CPAR7 register *******************/\r
+#define DMA_CPAR7_PA_Pos (0U) \r
+#define DMA_CPAR7_PA_Msk (0xFFFFFFFFUL << DMA_CPAR7_PA_Pos) /*!< 0xFFFFFFFF */\r
+#define DMA_CPAR7_PA DMA_CPAR7_PA_Msk /*!< Peripheral Address */\r
+\r
+/****************** Bit definition generic for DMA_CMAR register ********************/\r
+#define DMA_CMAR_MA_Pos (0U) \r
+#define DMA_CMAR_MA_Msk (0xFFFFFFFFUL << DMA_CMAR_MA_Pos) /*!< 0xFFFFFFFF */\r
+#define DMA_CMAR_MA DMA_CMAR_MA_Msk /*!< Memory Address */\r
+\r
+/****************** Bit definition for DMA_CMAR1 register *******************/\r
+#define DMA_CMAR1_MA_Pos (0U) \r
+#define DMA_CMAR1_MA_Msk (0xFFFFFFFFUL << DMA_CMAR1_MA_Pos) /*!< 0xFFFFFFFF */\r
+#define DMA_CMAR1_MA DMA_CMAR1_MA_Msk /*!< Memory Address */\r
+\r
+/****************** Bit definition for DMA_CMAR2 register *******************/\r
+#define DMA_CMAR2_MA_Pos (0U) \r
+#define DMA_CMAR2_MA_Msk (0xFFFFFFFFUL << DMA_CMAR2_MA_Pos) /*!< 0xFFFFFFFF */\r
+#define DMA_CMAR2_MA DMA_CMAR2_MA_Msk /*!< Memory Address */\r
+\r
+/****************** Bit definition for DMA_CMAR3 register *******************/\r
+#define DMA_CMAR3_MA_Pos (0U) \r
+#define DMA_CMAR3_MA_Msk (0xFFFFFFFFUL << DMA_CMAR3_MA_Pos) /*!< 0xFFFFFFFF */\r
+#define DMA_CMAR3_MA DMA_CMAR3_MA_Msk /*!< Memory Address */\r
+\r
+\r
+/****************** Bit definition for DMA_CMAR4 register *******************/\r
+#define DMA_CMAR4_MA_Pos (0U) \r
+#define DMA_CMAR4_MA_Msk (0xFFFFFFFFUL << DMA_CMAR4_MA_Pos) /*!< 0xFFFFFFFF */\r
+#define DMA_CMAR4_MA DMA_CMAR4_MA_Msk /*!< Memory Address */\r
+\r
+/****************** Bit definition for DMA_CMAR5 register *******************/\r
+#define DMA_CMAR5_MA_Pos (0U) \r
+#define DMA_CMAR5_MA_Msk (0xFFFFFFFFUL << DMA_CMAR5_MA_Pos) /*!< 0xFFFFFFFF */\r
+#define DMA_CMAR5_MA DMA_CMAR5_MA_Msk /*!< Memory Address */\r
+\r
+/****************** Bit definition for DMA_CMAR6 register *******************/\r
+#define DMA_CMAR6_MA_Pos (0U) \r
+#define DMA_CMAR6_MA_Msk (0xFFFFFFFFUL << DMA_CMAR6_MA_Pos) /*!< 0xFFFFFFFF */\r
+#define DMA_CMAR6_MA DMA_CMAR6_MA_Msk /*!< Memory Address */\r
+\r
+/****************** Bit definition for DMA_CMAR7 register *******************/\r
+#define DMA_CMAR7_MA_Pos (0U) \r
+#define DMA_CMAR7_MA_Msk (0xFFFFFFFFUL << DMA_CMAR7_MA_Pos) /*!< 0xFFFFFFFF */\r
+#define DMA_CMAR7_MA DMA_CMAR7_MA_Msk /*!< Memory Address */\r
+\r
+/******************************************************************************/\r
+/* */\r
+/* External Interrupt/Event Controller (EXTI) */\r
+/* */\r
+/******************************************************************************/\r
+\r
+/******************* Bit definition for EXTI_IMR register *******************/\r
+#define EXTI_IMR_MR0_Pos (0U) \r
+#define EXTI_IMR_MR0_Msk (0x1UL << EXTI_IMR_MR0_Pos) /*!< 0x00000001 */\r
+#define EXTI_IMR_MR0 EXTI_IMR_MR0_Msk /*!< Interrupt Mask on line 0 */\r
+#define EXTI_IMR_MR1_Pos (1U) \r
+#define EXTI_IMR_MR1_Msk (0x1UL << EXTI_IMR_MR1_Pos) /*!< 0x00000002 */\r
+#define EXTI_IMR_MR1 EXTI_IMR_MR1_Msk /*!< Interrupt Mask on line 1 */\r
+#define EXTI_IMR_MR2_Pos (2U) \r
+#define EXTI_IMR_MR2_Msk (0x1UL << EXTI_IMR_MR2_Pos) /*!< 0x00000004 */\r
+#define EXTI_IMR_MR2 EXTI_IMR_MR2_Msk /*!< Interrupt Mask on line 2 */\r
+#define EXTI_IMR_MR3_Pos (3U) \r
+#define EXTI_IMR_MR3_Msk (0x1UL << EXTI_IMR_MR3_Pos) /*!< 0x00000008 */\r
+#define EXTI_IMR_MR3 EXTI_IMR_MR3_Msk /*!< Interrupt Mask on line 3 */\r
+#define EXTI_IMR_MR4_Pos (4U) \r
+#define EXTI_IMR_MR4_Msk (0x1UL << EXTI_IMR_MR4_Pos) /*!< 0x00000010 */\r
+#define EXTI_IMR_MR4 EXTI_IMR_MR4_Msk /*!< Interrupt Mask on line 4 */\r
+#define EXTI_IMR_MR5_Pos (5U) \r
+#define EXTI_IMR_MR5_Msk (0x1UL << EXTI_IMR_MR5_Pos) /*!< 0x00000020 */\r
+#define EXTI_IMR_MR5 EXTI_IMR_MR5_Msk /*!< Interrupt Mask on line 5 */\r
+#define EXTI_IMR_MR6_Pos (6U) \r
+#define EXTI_IMR_MR6_Msk (0x1UL << EXTI_IMR_MR6_Pos) /*!< 0x00000040 */\r
+#define EXTI_IMR_MR6 EXTI_IMR_MR6_Msk /*!< Interrupt Mask on line 6 */\r
+#define EXTI_IMR_MR7_Pos (7U) \r
+#define EXTI_IMR_MR7_Msk (0x1UL << EXTI_IMR_MR7_Pos) /*!< 0x00000080 */\r
+#define EXTI_IMR_MR7 EXTI_IMR_MR7_Msk /*!< Interrupt Mask on line 7 */\r
+#define EXTI_IMR_MR8_Pos (8U) \r
+#define EXTI_IMR_MR8_Msk (0x1UL << EXTI_IMR_MR8_Pos) /*!< 0x00000100 */\r
+#define EXTI_IMR_MR8 EXTI_IMR_MR8_Msk /*!< Interrupt Mask on line 8 */\r
+#define EXTI_IMR_MR9_Pos (9U) \r
+#define EXTI_IMR_MR9_Msk (0x1UL << EXTI_IMR_MR9_Pos) /*!< 0x00000200 */\r
+#define EXTI_IMR_MR9 EXTI_IMR_MR9_Msk /*!< Interrupt Mask on line 9 */\r
+#define EXTI_IMR_MR10_Pos (10U) \r
+#define EXTI_IMR_MR10_Msk (0x1UL << EXTI_IMR_MR10_Pos) /*!< 0x00000400 */\r
+#define EXTI_IMR_MR10 EXTI_IMR_MR10_Msk /*!< Interrupt Mask on line 10 */\r
+#define EXTI_IMR_MR11_Pos (11U) \r
+#define EXTI_IMR_MR11_Msk (0x1UL << EXTI_IMR_MR11_Pos) /*!< 0x00000800 */\r
+#define EXTI_IMR_MR11 EXTI_IMR_MR11_Msk /*!< Interrupt Mask on line 11 */\r
+#define EXTI_IMR_MR12_Pos (12U) \r
+#define EXTI_IMR_MR12_Msk (0x1UL << EXTI_IMR_MR12_Pos) /*!< 0x00001000 */\r
+#define EXTI_IMR_MR12 EXTI_IMR_MR12_Msk /*!< Interrupt Mask on line 12 */\r
+#define EXTI_IMR_MR13_Pos (13U) \r
+#define EXTI_IMR_MR13_Msk (0x1UL << EXTI_IMR_MR13_Pos) /*!< 0x00002000 */\r
+#define EXTI_IMR_MR13 EXTI_IMR_MR13_Msk /*!< Interrupt Mask on line 13 */\r
+#define EXTI_IMR_MR14_Pos (14U) \r
+#define EXTI_IMR_MR14_Msk (0x1UL << EXTI_IMR_MR14_Pos) /*!< 0x00004000 */\r
+#define EXTI_IMR_MR14 EXTI_IMR_MR14_Msk /*!< Interrupt Mask on line 14 */\r
+#define EXTI_IMR_MR15_Pos (15U) \r
+#define EXTI_IMR_MR15_Msk (0x1UL << EXTI_IMR_MR15_Pos) /*!< 0x00008000 */\r
+#define EXTI_IMR_MR15 EXTI_IMR_MR15_Msk /*!< Interrupt Mask on line 15 */\r
+#define EXTI_IMR_MR16_Pos (16U) \r
+#define EXTI_IMR_MR16_Msk (0x1UL << EXTI_IMR_MR16_Pos) /*!< 0x00010000 */\r
+#define EXTI_IMR_MR16 EXTI_IMR_MR16_Msk /*!< Interrupt Mask on line 16 */\r
+#define EXTI_IMR_MR17_Pos (17U) \r
+#define EXTI_IMR_MR17_Msk (0x1UL << EXTI_IMR_MR17_Pos) /*!< 0x00020000 */\r
+#define EXTI_IMR_MR17 EXTI_IMR_MR17_Msk /*!< Interrupt Mask on line 17 */\r
+#define EXTI_IMR_MR18_Pos (18U) \r
+#define EXTI_IMR_MR18_Msk (0x1UL << EXTI_IMR_MR18_Pos) /*!< 0x00040000 */\r
+#define EXTI_IMR_MR18 EXTI_IMR_MR18_Msk /*!< Interrupt Mask on line 18 */\r
+#define EXTI_IMR_MR19_Pos (19U) \r
+#define EXTI_IMR_MR19_Msk (0x1UL << EXTI_IMR_MR19_Pos) /*!< 0x00080000 */\r
+#define EXTI_IMR_MR19 EXTI_IMR_MR19_Msk /*!< Interrupt Mask on line 19 */\r
+#define EXTI_IMR_MR20_Pos (20U) \r
+#define EXTI_IMR_MR20_Msk (0x1UL << EXTI_IMR_MR20_Pos) /*!< 0x00100000 */\r
+#define EXTI_IMR_MR20 EXTI_IMR_MR20_Msk /*!< Interrupt Mask on line 20 */\r
+#define EXTI_IMR_MR21_Pos (21U) \r
+#define EXTI_IMR_MR21_Msk (0x1UL << EXTI_IMR_MR21_Pos) /*!< 0x00200000 */\r
+#define EXTI_IMR_MR21 EXTI_IMR_MR21_Msk /*!< Interrupt Mask on line 21 */\r
+#define EXTI_IMR_MR22_Pos (22U) \r
+#define EXTI_IMR_MR22_Msk (0x1UL << EXTI_IMR_MR22_Pos) /*!< 0x00400000 */\r
+#define EXTI_IMR_MR22 EXTI_IMR_MR22_Msk /*!< Interrupt Mask on line 22 */\r
+#define EXTI_IMR_MR23_Pos (23U) \r
+#define EXTI_IMR_MR23_Msk (0x1UL << EXTI_IMR_MR23_Pos) /*!< 0x00800000 */\r
+#define EXTI_IMR_MR23 EXTI_IMR_MR23_Msk /*!< Interrupt Mask on line 23 */\r
+\r
+/* References Defines */\r
+#define EXTI_IMR_IM0 EXTI_IMR_MR0\r
+#define EXTI_IMR_IM1 EXTI_IMR_MR1\r
+#define EXTI_IMR_IM2 EXTI_IMR_MR2\r
+#define EXTI_IMR_IM3 EXTI_IMR_MR3\r
+#define EXTI_IMR_IM4 EXTI_IMR_MR4\r
+#define EXTI_IMR_IM5 EXTI_IMR_MR5\r
+#define EXTI_IMR_IM6 EXTI_IMR_MR6\r
+#define EXTI_IMR_IM7 EXTI_IMR_MR7\r
+#define EXTI_IMR_IM8 EXTI_IMR_MR8\r
+#define EXTI_IMR_IM9 EXTI_IMR_MR9\r
+#define EXTI_IMR_IM10 EXTI_IMR_MR10\r
+#define EXTI_IMR_IM11 EXTI_IMR_MR11\r
+#define EXTI_IMR_IM12 EXTI_IMR_MR12\r
+#define EXTI_IMR_IM13 EXTI_IMR_MR13\r
+#define EXTI_IMR_IM14 EXTI_IMR_MR14\r
+#define EXTI_IMR_IM15 EXTI_IMR_MR15\r
+#define EXTI_IMR_IM16 EXTI_IMR_MR16\r
+#define EXTI_IMR_IM17 EXTI_IMR_MR17\r
+#define EXTI_IMR_IM18 EXTI_IMR_MR18\r
+#define EXTI_IMR_IM19 EXTI_IMR_MR19\r
+#define EXTI_IMR_IM20 EXTI_IMR_MR20\r
+#define EXTI_IMR_IM21 EXTI_IMR_MR21\r
+#define EXTI_IMR_IM22 EXTI_IMR_MR22\r
+/* Category 3, 4 & 5 */\r
+#define EXTI_IMR_IM23 EXTI_IMR_MR23\r
+#define EXTI_IMR_IM_Pos (0U) \r
+#define EXTI_IMR_IM_Msk (0xFFFFFFUL << EXTI_IMR_IM_Pos) /*!< 0x00FFFFFF */\r
+#define EXTI_IMR_IM EXTI_IMR_IM_Msk /*!< Interrupt Mask All */\r
+\r
+/******************* Bit definition for EXTI_EMR register *******************/\r
+#define EXTI_EMR_MR0_Pos (0U) \r
+#define EXTI_EMR_MR0_Msk (0x1UL << EXTI_EMR_MR0_Pos) /*!< 0x00000001 */\r
+#define EXTI_EMR_MR0 EXTI_EMR_MR0_Msk /*!< Event Mask on line 0 */\r
+#define EXTI_EMR_MR1_Pos (1U) \r
+#define EXTI_EMR_MR1_Msk (0x1UL << EXTI_EMR_MR1_Pos) /*!< 0x00000002 */\r
+#define EXTI_EMR_MR1 EXTI_EMR_MR1_Msk /*!< Event Mask on line 1 */\r
+#define EXTI_EMR_MR2_Pos (2U) \r
+#define EXTI_EMR_MR2_Msk (0x1UL << EXTI_EMR_MR2_Pos) /*!< 0x00000004 */\r
+#define EXTI_EMR_MR2 EXTI_EMR_MR2_Msk /*!< Event Mask on line 2 */\r
+#define EXTI_EMR_MR3_Pos (3U) \r
+#define EXTI_EMR_MR3_Msk (0x1UL << EXTI_EMR_MR3_Pos) /*!< 0x00000008 */\r
+#define EXTI_EMR_MR3 EXTI_EMR_MR3_Msk /*!< Event Mask on line 3 */\r
+#define EXTI_EMR_MR4_Pos (4U) \r
+#define EXTI_EMR_MR4_Msk (0x1UL << EXTI_EMR_MR4_Pos) /*!< 0x00000010 */\r
+#define EXTI_EMR_MR4 EXTI_EMR_MR4_Msk /*!< Event Mask on line 4 */\r
+#define EXTI_EMR_MR5_Pos (5U) \r
+#define EXTI_EMR_MR5_Msk (0x1UL << EXTI_EMR_MR5_Pos) /*!< 0x00000020 */\r
+#define EXTI_EMR_MR5 EXTI_EMR_MR5_Msk /*!< Event Mask on line 5 */\r
+#define EXTI_EMR_MR6_Pos (6U) \r
+#define EXTI_EMR_MR6_Msk (0x1UL << EXTI_EMR_MR6_Pos) /*!< 0x00000040 */\r
+#define EXTI_EMR_MR6 EXTI_EMR_MR6_Msk /*!< Event Mask on line 6 */\r
+#define EXTI_EMR_MR7_Pos (7U) \r
+#define EXTI_EMR_MR7_Msk (0x1UL << EXTI_EMR_MR7_Pos) /*!< 0x00000080 */\r
+#define EXTI_EMR_MR7 EXTI_EMR_MR7_Msk /*!< Event Mask on line 7 */\r
+#define EXTI_EMR_MR8_Pos (8U) \r
+#define EXTI_EMR_MR8_Msk (0x1UL << EXTI_EMR_MR8_Pos) /*!< 0x00000100 */\r
+#define EXTI_EMR_MR8 EXTI_EMR_MR8_Msk /*!< Event Mask on line 8 */\r
+#define EXTI_EMR_MR9_Pos (9U) \r
+#define EXTI_EMR_MR9_Msk (0x1UL << EXTI_EMR_MR9_Pos) /*!< 0x00000200 */\r
+#define EXTI_EMR_MR9 EXTI_EMR_MR9_Msk /*!< Event Mask on line 9 */\r
+#define EXTI_EMR_MR10_Pos (10U) \r
+#define EXTI_EMR_MR10_Msk (0x1UL << EXTI_EMR_MR10_Pos) /*!< 0x00000400 */\r
+#define EXTI_EMR_MR10 EXTI_EMR_MR10_Msk /*!< Event Mask on line 10 */\r
+#define EXTI_EMR_MR11_Pos (11U) \r
+#define EXTI_EMR_MR11_Msk (0x1UL << EXTI_EMR_MR11_Pos) /*!< 0x00000800 */\r
+#define EXTI_EMR_MR11 EXTI_EMR_MR11_Msk /*!< Event Mask on line 11 */\r
+#define EXTI_EMR_MR12_Pos (12U) \r
+#define EXTI_EMR_MR12_Msk (0x1UL << EXTI_EMR_MR12_Pos) /*!< 0x00001000 */\r
+#define EXTI_EMR_MR12 EXTI_EMR_MR12_Msk /*!< Event Mask on line 12 */\r
+#define EXTI_EMR_MR13_Pos (13U) \r
+#define EXTI_EMR_MR13_Msk (0x1UL << EXTI_EMR_MR13_Pos) /*!< 0x00002000 */\r
+#define EXTI_EMR_MR13 EXTI_EMR_MR13_Msk /*!< Event Mask on line 13 */\r
+#define EXTI_EMR_MR14_Pos (14U) \r
+#define EXTI_EMR_MR14_Msk (0x1UL << EXTI_EMR_MR14_Pos) /*!< 0x00004000 */\r
+#define EXTI_EMR_MR14 EXTI_EMR_MR14_Msk /*!< Event Mask on line 14 */\r
+#define EXTI_EMR_MR15_Pos (15U) \r
+#define EXTI_EMR_MR15_Msk (0x1UL << EXTI_EMR_MR15_Pos) /*!< 0x00008000 */\r
+#define EXTI_EMR_MR15 EXTI_EMR_MR15_Msk /*!< Event Mask on line 15 */\r
+#define EXTI_EMR_MR16_Pos (16U) \r
+#define EXTI_EMR_MR16_Msk (0x1UL << EXTI_EMR_MR16_Pos) /*!< 0x00010000 */\r
+#define EXTI_EMR_MR16 EXTI_EMR_MR16_Msk /*!< Event Mask on line 16 */\r
+#define EXTI_EMR_MR17_Pos (17U) \r
+#define EXTI_EMR_MR17_Msk (0x1UL << EXTI_EMR_MR17_Pos) /*!< 0x00020000 */\r
+#define EXTI_EMR_MR17 EXTI_EMR_MR17_Msk /*!< Event Mask on line 17 */\r
+#define EXTI_EMR_MR18_Pos (18U) \r
+#define EXTI_EMR_MR18_Msk (0x1UL << EXTI_EMR_MR18_Pos) /*!< 0x00040000 */\r
+#define EXTI_EMR_MR18 EXTI_EMR_MR18_Msk /*!< Event Mask on line 18 */\r
+#define EXTI_EMR_MR19_Pos (19U) \r
+#define EXTI_EMR_MR19_Msk (0x1UL << EXTI_EMR_MR19_Pos) /*!< 0x00080000 */\r
+#define EXTI_EMR_MR19 EXTI_EMR_MR19_Msk /*!< Event Mask on line 19 */\r
+#define EXTI_EMR_MR20_Pos (20U) \r
+#define EXTI_EMR_MR20_Msk (0x1UL << EXTI_EMR_MR20_Pos) /*!< 0x00100000 */\r
+#define EXTI_EMR_MR20 EXTI_EMR_MR20_Msk /*!< Event Mask on line 20 */\r
+#define EXTI_EMR_MR21_Pos (21U) \r
+#define EXTI_EMR_MR21_Msk (0x1UL << EXTI_EMR_MR21_Pos) /*!< 0x00200000 */\r
+#define EXTI_EMR_MR21 EXTI_EMR_MR21_Msk /*!< Event Mask on line 21 */\r
+#define EXTI_EMR_MR22_Pos (22U) \r
+#define EXTI_EMR_MR22_Msk (0x1UL << EXTI_EMR_MR22_Pos) /*!< 0x00400000 */\r
+#define EXTI_EMR_MR22 EXTI_EMR_MR22_Msk /*!< Event Mask on line 22 */\r
+#define EXTI_EMR_MR23_Pos (23U) \r
+#define EXTI_EMR_MR23_Msk (0x1UL << EXTI_EMR_MR23_Pos) /*!< 0x00800000 */\r
+#define EXTI_EMR_MR23 EXTI_EMR_MR23_Msk /*!< Event Mask on line 23 */\r
+\r
+/* References Defines */\r
+#define EXTI_EMR_EM0 EXTI_EMR_MR0\r
+#define EXTI_EMR_EM1 EXTI_EMR_MR1\r
+#define EXTI_EMR_EM2 EXTI_EMR_MR2\r
+#define EXTI_EMR_EM3 EXTI_EMR_MR3\r
+#define EXTI_EMR_EM4 EXTI_EMR_MR4\r
+#define EXTI_EMR_EM5 EXTI_EMR_MR5\r
+#define EXTI_EMR_EM6 EXTI_EMR_MR6\r
+#define EXTI_EMR_EM7 EXTI_EMR_MR7\r
+#define EXTI_EMR_EM8 EXTI_EMR_MR8\r
+#define EXTI_EMR_EM9 EXTI_EMR_MR9\r
+#define EXTI_EMR_EM10 EXTI_EMR_MR10\r
+#define EXTI_EMR_EM11 EXTI_EMR_MR11\r
+#define EXTI_EMR_EM12 EXTI_EMR_MR12\r
+#define EXTI_EMR_EM13 EXTI_EMR_MR13\r
+#define EXTI_EMR_EM14 EXTI_EMR_MR14\r
+#define EXTI_EMR_EM15 EXTI_EMR_MR15\r
+#define EXTI_EMR_EM16 EXTI_EMR_MR16\r
+#define EXTI_EMR_EM17 EXTI_EMR_MR17\r
+#define EXTI_EMR_EM18 EXTI_EMR_MR18\r
+#define EXTI_EMR_EM19 EXTI_EMR_MR19\r
+#define EXTI_EMR_EM20 EXTI_EMR_MR20\r
+#define EXTI_EMR_EM21 EXTI_EMR_MR21\r
+#define EXTI_EMR_EM22 EXTI_EMR_MR22\r
+#define EXTI_EMR_EM23 EXTI_EMR_MR23\r
+\r
+/****************** Bit definition for EXTI_RTSR register *******************/\r
+#define EXTI_RTSR_TR0_Pos (0U) \r
+#define EXTI_RTSR_TR0_Msk (0x1UL << EXTI_RTSR_TR0_Pos) /*!< 0x00000001 */\r
+#define EXTI_RTSR_TR0 EXTI_RTSR_TR0_Msk /*!< Rising trigger event configuration bit of line 0 */\r
+#define EXTI_RTSR_TR1_Pos (1U) \r
+#define EXTI_RTSR_TR1_Msk (0x1UL << EXTI_RTSR_TR1_Pos) /*!< 0x00000002 */\r
+#define EXTI_RTSR_TR1 EXTI_RTSR_TR1_Msk /*!< Rising trigger event configuration bit of line 1 */\r
+#define EXTI_RTSR_TR2_Pos (2U) \r
+#define EXTI_RTSR_TR2_Msk (0x1UL << EXTI_RTSR_TR2_Pos) /*!< 0x00000004 */\r
+#define EXTI_RTSR_TR2 EXTI_RTSR_TR2_Msk /*!< Rising trigger event configuration bit of line 2 */\r
+#define EXTI_RTSR_TR3_Pos (3U) \r
+#define EXTI_RTSR_TR3_Msk (0x1UL << EXTI_RTSR_TR3_Pos) /*!< 0x00000008 */\r
+#define EXTI_RTSR_TR3 EXTI_RTSR_TR3_Msk /*!< Rising trigger event configuration bit of line 3 */\r
+#define EXTI_RTSR_TR4_Pos (4U) \r
+#define EXTI_RTSR_TR4_Msk (0x1UL << EXTI_RTSR_TR4_Pos) /*!< 0x00000010 */\r
+#define EXTI_RTSR_TR4 EXTI_RTSR_TR4_Msk /*!< Rising trigger event configuration bit of line 4 */\r
+#define EXTI_RTSR_TR5_Pos (5U) \r
+#define EXTI_RTSR_TR5_Msk (0x1UL << EXTI_RTSR_TR5_Pos) /*!< 0x00000020 */\r
+#define EXTI_RTSR_TR5 EXTI_RTSR_TR5_Msk /*!< Rising trigger event configuration bit of line 5 */\r
+#define EXTI_RTSR_TR6_Pos (6U) \r
+#define EXTI_RTSR_TR6_Msk (0x1UL << EXTI_RTSR_TR6_Pos) /*!< 0x00000040 */\r
+#define EXTI_RTSR_TR6 EXTI_RTSR_TR6_Msk /*!< Rising trigger event configuration bit of line 6 */\r
+#define EXTI_RTSR_TR7_Pos (7U) \r
+#define EXTI_RTSR_TR7_Msk (0x1UL << EXTI_RTSR_TR7_Pos) /*!< 0x00000080 */\r
+#define EXTI_RTSR_TR7 EXTI_RTSR_TR7_Msk /*!< Rising trigger event configuration bit of line 7 */\r
+#define EXTI_RTSR_TR8_Pos (8U) \r
+#define EXTI_RTSR_TR8_Msk (0x1UL << EXTI_RTSR_TR8_Pos) /*!< 0x00000100 */\r
+#define EXTI_RTSR_TR8 EXTI_RTSR_TR8_Msk /*!< Rising trigger event configuration bit of line 8 */\r
+#define EXTI_RTSR_TR9_Pos (9U) \r
+#define EXTI_RTSR_TR9_Msk (0x1UL << EXTI_RTSR_TR9_Pos) /*!< 0x00000200 */\r
+#define EXTI_RTSR_TR9 EXTI_RTSR_TR9_Msk /*!< Rising trigger event configuration bit of line 9 */\r
+#define EXTI_RTSR_TR10_Pos (10U) \r
+#define EXTI_RTSR_TR10_Msk (0x1UL << EXTI_RTSR_TR10_Pos) /*!< 0x00000400 */\r
+#define EXTI_RTSR_TR10 EXTI_RTSR_TR10_Msk /*!< Rising trigger event configuration bit of line 10 */\r
+#define EXTI_RTSR_TR11_Pos (11U) \r
+#define EXTI_RTSR_TR11_Msk (0x1UL << EXTI_RTSR_TR11_Pos) /*!< 0x00000800 */\r
+#define EXTI_RTSR_TR11 EXTI_RTSR_TR11_Msk /*!< Rising trigger event configuration bit of line 11 */\r
+#define EXTI_RTSR_TR12_Pos (12U) \r
+#define EXTI_RTSR_TR12_Msk (0x1UL << EXTI_RTSR_TR12_Pos) /*!< 0x00001000 */\r
+#define EXTI_RTSR_TR12 EXTI_RTSR_TR12_Msk /*!< Rising trigger event configuration bit of line 12 */\r
+#define EXTI_RTSR_TR13_Pos (13U) \r
+#define EXTI_RTSR_TR13_Msk (0x1UL << EXTI_RTSR_TR13_Pos) /*!< 0x00002000 */\r
+#define EXTI_RTSR_TR13 EXTI_RTSR_TR13_Msk /*!< Rising trigger event configuration bit of line 13 */\r
+#define EXTI_RTSR_TR14_Pos (14U) \r
+#define EXTI_RTSR_TR14_Msk (0x1UL << EXTI_RTSR_TR14_Pos) /*!< 0x00004000 */\r
+#define EXTI_RTSR_TR14 EXTI_RTSR_TR14_Msk /*!< Rising trigger event configuration bit of line 14 */\r
+#define EXTI_RTSR_TR15_Pos (15U) \r
+#define EXTI_RTSR_TR15_Msk (0x1UL << EXTI_RTSR_TR15_Pos) /*!< 0x00008000 */\r
+#define EXTI_RTSR_TR15 EXTI_RTSR_TR15_Msk /*!< Rising trigger event configuration bit of line 15 */\r
+#define EXTI_RTSR_TR16_Pos (16U) \r
+#define EXTI_RTSR_TR16_Msk (0x1UL << EXTI_RTSR_TR16_Pos) /*!< 0x00010000 */\r
+#define EXTI_RTSR_TR16 EXTI_RTSR_TR16_Msk /*!< Rising trigger event configuration bit of line 16 */\r
+#define EXTI_RTSR_TR17_Pos (17U) \r
+#define EXTI_RTSR_TR17_Msk (0x1UL << EXTI_RTSR_TR17_Pos) /*!< 0x00020000 */\r
+#define EXTI_RTSR_TR17 EXTI_RTSR_TR17_Msk /*!< Rising trigger event configuration bit of line 17 */\r
+#define EXTI_RTSR_TR18_Pos (18U) \r
+#define EXTI_RTSR_TR18_Msk (0x1UL << EXTI_RTSR_TR18_Pos) /*!< 0x00040000 */\r
+#define EXTI_RTSR_TR18 EXTI_RTSR_TR18_Msk /*!< Rising trigger event configuration bit of line 18 */\r
+#define EXTI_RTSR_TR19_Pos (19U) \r
+#define EXTI_RTSR_TR19_Msk (0x1UL << EXTI_RTSR_TR19_Pos) /*!< 0x00080000 */\r
+#define EXTI_RTSR_TR19 EXTI_RTSR_TR19_Msk /*!< Rising trigger event configuration bit of line 19 */\r
+#define EXTI_RTSR_TR20_Pos (20U) \r
+#define EXTI_RTSR_TR20_Msk (0x1UL << EXTI_RTSR_TR20_Pos) /*!< 0x00100000 */\r
+#define EXTI_RTSR_TR20 EXTI_RTSR_TR20_Msk /*!< Rising trigger event configuration bit of line 20 */\r
+#define EXTI_RTSR_TR21_Pos (21U) \r
+#define EXTI_RTSR_TR21_Msk (0x1UL << EXTI_RTSR_TR21_Pos) /*!< 0x00200000 */\r
+#define EXTI_RTSR_TR21 EXTI_RTSR_TR21_Msk /*!< Rising trigger event configuration bit of line 21 */\r
+#define EXTI_RTSR_TR22_Pos (22U) \r
+#define EXTI_RTSR_TR22_Msk (0x1UL << EXTI_RTSR_TR22_Pos) /*!< 0x00400000 */\r
+#define EXTI_RTSR_TR22 EXTI_RTSR_TR22_Msk /*!< Rising trigger event configuration bit of line 22 */\r
+#define EXTI_RTSR_TR23_Pos (23U) \r
+#define EXTI_RTSR_TR23_Msk (0x1UL << EXTI_RTSR_TR23_Pos) /*!< 0x00800000 */\r
+#define EXTI_RTSR_TR23 EXTI_RTSR_TR23_Msk /*!< Rising trigger event configuration bit of line 23 */\r
+\r
+/* References Defines */\r
+#define EXTI_RTSR_RT0 EXTI_RTSR_TR0\r
+#define EXTI_RTSR_RT1 EXTI_RTSR_TR1\r
+#define EXTI_RTSR_RT2 EXTI_RTSR_TR2\r
+#define EXTI_RTSR_RT3 EXTI_RTSR_TR3\r
+#define EXTI_RTSR_RT4 EXTI_RTSR_TR4\r
+#define EXTI_RTSR_RT5 EXTI_RTSR_TR5\r
+#define EXTI_RTSR_RT6 EXTI_RTSR_TR6\r
+#define EXTI_RTSR_RT7 EXTI_RTSR_TR7\r
+#define EXTI_RTSR_RT8 EXTI_RTSR_TR8\r
+#define EXTI_RTSR_RT9 EXTI_RTSR_TR9\r
+#define EXTI_RTSR_RT10 EXTI_RTSR_TR10\r
+#define EXTI_RTSR_RT11 EXTI_RTSR_TR11\r
+#define EXTI_RTSR_RT12 EXTI_RTSR_TR12\r
+#define EXTI_RTSR_RT13 EXTI_RTSR_TR13\r
+#define EXTI_RTSR_RT14 EXTI_RTSR_TR14\r
+#define EXTI_RTSR_RT15 EXTI_RTSR_TR15\r
+#define EXTI_RTSR_RT16 EXTI_RTSR_TR16\r
+#define EXTI_RTSR_RT17 EXTI_RTSR_TR17\r
+#define EXTI_RTSR_RT18 EXTI_RTSR_TR18\r
+#define EXTI_RTSR_RT19 EXTI_RTSR_TR19\r
+#define EXTI_RTSR_RT20 EXTI_RTSR_TR20\r
+#define EXTI_RTSR_RT21 EXTI_RTSR_TR21\r
+#define EXTI_RTSR_RT22 EXTI_RTSR_TR22\r
+#define EXTI_RTSR_RT23 EXTI_RTSR_TR23\r
+\r
+/****************** Bit definition for EXTI_FTSR register *******************/\r
+#define EXTI_FTSR_TR0_Pos (0U) \r
+#define EXTI_FTSR_TR0_Msk (0x1UL << EXTI_FTSR_TR0_Pos) /*!< 0x00000001 */\r
+#define EXTI_FTSR_TR0 EXTI_FTSR_TR0_Msk /*!< Falling trigger event configuration bit of line 0 */\r
+#define EXTI_FTSR_TR1_Pos (1U) \r
+#define EXTI_FTSR_TR1_Msk (0x1UL << EXTI_FTSR_TR1_Pos) /*!< 0x00000002 */\r
+#define EXTI_FTSR_TR1 EXTI_FTSR_TR1_Msk /*!< Falling trigger event configuration bit of line 1 */\r
+#define EXTI_FTSR_TR2_Pos (2U) \r
+#define EXTI_FTSR_TR2_Msk (0x1UL << EXTI_FTSR_TR2_Pos) /*!< 0x00000004 */\r
+#define EXTI_FTSR_TR2 EXTI_FTSR_TR2_Msk /*!< Falling trigger event configuration bit of line 2 */\r
+#define EXTI_FTSR_TR3_Pos (3U) \r
+#define EXTI_FTSR_TR3_Msk (0x1UL << EXTI_FTSR_TR3_Pos) /*!< 0x00000008 */\r
+#define EXTI_FTSR_TR3 EXTI_FTSR_TR3_Msk /*!< Falling trigger event configuration bit of line 3 */\r
+#define EXTI_FTSR_TR4_Pos (4U) \r
+#define EXTI_FTSR_TR4_Msk (0x1UL << EXTI_FTSR_TR4_Pos) /*!< 0x00000010 */\r
+#define EXTI_FTSR_TR4 EXTI_FTSR_TR4_Msk /*!< Falling trigger event configuration bit of line 4 */\r
+#define EXTI_FTSR_TR5_Pos (5U) \r
+#define EXTI_FTSR_TR5_Msk (0x1UL << EXTI_FTSR_TR5_Pos) /*!< 0x00000020 */\r
+#define EXTI_FTSR_TR5 EXTI_FTSR_TR5_Msk /*!< Falling trigger event configuration bit of line 5 */\r
+#define EXTI_FTSR_TR6_Pos (6U) \r
+#define EXTI_FTSR_TR6_Msk (0x1UL << EXTI_FTSR_TR6_Pos) /*!< 0x00000040 */\r
+#define EXTI_FTSR_TR6 EXTI_FTSR_TR6_Msk /*!< Falling trigger event configuration bit of line 6 */\r
+#define EXTI_FTSR_TR7_Pos (7U) \r
+#define EXTI_FTSR_TR7_Msk (0x1UL << EXTI_FTSR_TR7_Pos) /*!< 0x00000080 */\r
+#define EXTI_FTSR_TR7 EXTI_FTSR_TR7_Msk /*!< Falling trigger event configuration bit of line 7 */\r
+#define EXTI_FTSR_TR8_Pos (8U) \r
+#define EXTI_FTSR_TR8_Msk (0x1UL << EXTI_FTSR_TR8_Pos) /*!< 0x00000100 */\r
+#define EXTI_FTSR_TR8 EXTI_FTSR_TR8_Msk /*!< Falling trigger event configuration bit of line 8 */\r
+#define EXTI_FTSR_TR9_Pos (9U) \r
+#define EXTI_FTSR_TR9_Msk (0x1UL << EXTI_FTSR_TR9_Pos) /*!< 0x00000200 */\r
+#define EXTI_FTSR_TR9 EXTI_FTSR_TR9_Msk /*!< Falling trigger event configuration bit of line 9 */\r
+#define EXTI_FTSR_TR10_Pos (10U) \r
+#define EXTI_FTSR_TR10_Msk (0x1UL << EXTI_FTSR_TR10_Pos) /*!< 0x00000400 */\r
+#define EXTI_FTSR_TR10 EXTI_FTSR_TR10_Msk /*!< Falling trigger event configuration bit of line 10 */\r
+#define EXTI_FTSR_TR11_Pos (11U) \r
+#define EXTI_FTSR_TR11_Msk (0x1UL << EXTI_FTSR_TR11_Pos) /*!< 0x00000800 */\r
+#define EXTI_FTSR_TR11 EXTI_FTSR_TR11_Msk /*!< Falling trigger event configuration bit of line 11 */\r
+#define EXTI_FTSR_TR12_Pos (12U) \r
+#define EXTI_FTSR_TR12_Msk (0x1UL << EXTI_FTSR_TR12_Pos) /*!< 0x00001000 */\r
+#define EXTI_FTSR_TR12 EXTI_FTSR_TR12_Msk /*!< Falling trigger event configuration bit of line 12 */\r
+#define EXTI_FTSR_TR13_Pos (13U) \r
+#define EXTI_FTSR_TR13_Msk (0x1UL << EXTI_FTSR_TR13_Pos) /*!< 0x00002000 */\r
+#define EXTI_FTSR_TR13 EXTI_FTSR_TR13_Msk /*!< Falling trigger event configuration bit of line 13 */\r
+#define EXTI_FTSR_TR14_Pos (14U) \r
+#define EXTI_FTSR_TR14_Msk (0x1UL << EXTI_FTSR_TR14_Pos) /*!< 0x00004000 */\r
+#define EXTI_FTSR_TR14 EXTI_FTSR_TR14_Msk /*!< Falling trigger event configuration bit of line 14 */\r
+#define EXTI_FTSR_TR15_Pos (15U) \r
+#define EXTI_FTSR_TR15_Msk (0x1UL << EXTI_FTSR_TR15_Pos) /*!< 0x00008000 */\r
+#define EXTI_FTSR_TR15 EXTI_FTSR_TR15_Msk /*!< Falling trigger event configuration bit of line 15 */\r
+#define EXTI_FTSR_TR16_Pos (16U) \r
+#define EXTI_FTSR_TR16_Msk (0x1UL << EXTI_FTSR_TR16_Pos) /*!< 0x00010000 */\r
+#define EXTI_FTSR_TR16 EXTI_FTSR_TR16_Msk /*!< Falling trigger event configuration bit of line 16 */\r
+#define EXTI_FTSR_TR17_Pos (17U) \r
+#define EXTI_FTSR_TR17_Msk (0x1UL << EXTI_FTSR_TR17_Pos) /*!< 0x00020000 */\r
+#define EXTI_FTSR_TR17 EXTI_FTSR_TR17_Msk /*!< Falling trigger event configuration bit of line 17 */\r
+#define EXTI_FTSR_TR18_Pos (18U) \r
+#define EXTI_FTSR_TR18_Msk (0x1UL << EXTI_FTSR_TR18_Pos) /*!< 0x00040000 */\r
+#define EXTI_FTSR_TR18 EXTI_FTSR_TR18_Msk /*!< Falling trigger event configuration bit of line 18 */\r
+#define EXTI_FTSR_TR19_Pos (19U) \r
+#define EXTI_FTSR_TR19_Msk (0x1UL << EXTI_FTSR_TR19_Pos) /*!< 0x00080000 */\r
+#define EXTI_FTSR_TR19 EXTI_FTSR_TR19_Msk /*!< Falling trigger event configuration bit of line 19 */\r
+#define EXTI_FTSR_TR20_Pos (20U) \r
+#define EXTI_FTSR_TR20_Msk (0x1UL << EXTI_FTSR_TR20_Pos) /*!< 0x00100000 */\r
+#define EXTI_FTSR_TR20 EXTI_FTSR_TR20_Msk /*!< Falling trigger event configuration bit of line 20 */\r
+#define EXTI_FTSR_TR21_Pos (21U) \r
+#define EXTI_FTSR_TR21_Msk (0x1UL << EXTI_FTSR_TR21_Pos) /*!< 0x00200000 */\r
+#define EXTI_FTSR_TR21 EXTI_FTSR_TR21_Msk /*!< Falling trigger event configuration bit of line 21 */\r
+#define EXTI_FTSR_TR22_Pos (22U) \r
+#define EXTI_FTSR_TR22_Msk (0x1UL << EXTI_FTSR_TR22_Pos) /*!< 0x00400000 */\r
+#define EXTI_FTSR_TR22 EXTI_FTSR_TR22_Msk /*!< Falling trigger event configuration bit of line 22 */\r
+#define EXTI_FTSR_TR23_Pos (23U) \r
+#define EXTI_FTSR_TR23_Msk (0x1UL << EXTI_FTSR_TR23_Pos) /*!< 0x00800000 */\r
+#define EXTI_FTSR_TR23 EXTI_FTSR_TR23_Msk /*!< Falling trigger event configuration bit of line 23 */\r
+\r
+/* References Defines */\r
+#define EXTI_FTSR_FT0 EXTI_FTSR_TR0\r
+#define EXTI_FTSR_FT1 EXTI_FTSR_TR1\r
+#define EXTI_FTSR_FT2 EXTI_FTSR_TR2\r
+#define EXTI_FTSR_FT3 EXTI_FTSR_TR3\r
+#define EXTI_FTSR_FT4 EXTI_FTSR_TR4\r
+#define EXTI_FTSR_FT5 EXTI_FTSR_TR5\r
+#define EXTI_FTSR_FT6 EXTI_FTSR_TR6\r
+#define EXTI_FTSR_FT7 EXTI_FTSR_TR7\r
+#define EXTI_FTSR_FT8 EXTI_FTSR_TR8\r
+#define EXTI_FTSR_FT9 EXTI_FTSR_TR9\r
+#define EXTI_FTSR_FT10 EXTI_FTSR_TR10\r
+#define EXTI_FTSR_FT11 EXTI_FTSR_TR11\r
+#define EXTI_FTSR_FT12 EXTI_FTSR_TR12\r
+#define EXTI_FTSR_FT13 EXTI_FTSR_TR13\r
+#define EXTI_FTSR_FT14 EXTI_FTSR_TR14\r
+#define EXTI_FTSR_FT15 EXTI_FTSR_TR15\r
+#define EXTI_FTSR_FT16 EXTI_FTSR_TR16\r
+#define EXTI_FTSR_FT17 EXTI_FTSR_TR17\r
+#define EXTI_FTSR_FT18 EXTI_FTSR_TR18\r
+#define EXTI_FTSR_FT19 EXTI_FTSR_TR19\r
+#define EXTI_FTSR_FT20 EXTI_FTSR_TR20\r
+#define EXTI_FTSR_FT21 EXTI_FTSR_TR21\r
+#define EXTI_FTSR_FT22 EXTI_FTSR_TR22\r
+#define EXTI_FTSR_FT23 EXTI_FTSR_TR23\r
+\r
+/****************** Bit definition for EXTI_SWIER register ******************/\r
+#define EXTI_SWIER_SWIER0_Pos (0U) \r
+#define EXTI_SWIER_SWIER0_Msk (0x1UL << EXTI_SWIER_SWIER0_Pos) /*!< 0x00000001 */\r
+#define EXTI_SWIER_SWIER0 EXTI_SWIER_SWIER0_Msk /*!< Software Interrupt on line 0 */\r
+#define EXTI_SWIER_SWIER1_Pos (1U) \r
+#define EXTI_SWIER_SWIER1_Msk (0x1UL << EXTI_SWIER_SWIER1_Pos) /*!< 0x00000002 */\r
+#define EXTI_SWIER_SWIER1 EXTI_SWIER_SWIER1_Msk /*!< Software Interrupt on line 1 */\r
+#define EXTI_SWIER_SWIER2_Pos (2U) \r
+#define EXTI_SWIER_SWIER2_Msk (0x1UL << EXTI_SWIER_SWIER2_Pos) /*!< 0x00000004 */\r
+#define EXTI_SWIER_SWIER2 EXTI_SWIER_SWIER2_Msk /*!< Software Interrupt on line 2 */\r
+#define EXTI_SWIER_SWIER3_Pos (3U) \r
+#define EXTI_SWIER_SWIER3_Msk (0x1UL << EXTI_SWIER_SWIER3_Pos) /*!< 0x00000008 */\r
+#define EXTI_SWIER_SWIER3 EXTI_SWIER_SWIER3_Msk /*!< Software Interrupt on line 3 */\r
+#define EXTI_SWIER_SWIER4_Pos (4U) \r
+#define EXTI_SWIER_SWIER4_Msk (0x1UL << EXTI_SWIER_SWIER4_Pos) /*!< 0x00000010 */\r
+#define EXTI_SWIER_SWIER4 EXTI_SWIER_SWIER4_Msk /*!< Software Interrupt on line 4 */\r
+#define EXTI_SWIER_SWIER5_Pos (5U) \r
+#define EXTI_SWIER_SWIER5_Msk (0x1UL << EXTI_SWIER_SWIER5_Pos) /*!< 0x00000020 */\r
+#define EXTI_SWIER_SWIER5 EXTI_SWIER_SWIER5_Msk /*!< Software Interrupt on line 5 */\r
+#define EXTI_SWIER_SWIER6_Pos (6U) \r
+#define EXTI_SWIER_SWIER6_Msk (0x1UL << EXTI_SWIER_SWIER6_Pos) /*!< 0x00000040 */\r
+#define EXTI_SWIER_SWIER6 EXTI_SWIER_SWIER6_Msk /*!< Software Interrupt on line 6 */\r
+#define EXTI_SWIER_SWIER7_Pos (7U) \r
+#define EXTI_SWIER_SWIER7_Msk (0x1UL << EXTI_SWIER_SWIER7_Pos) /*!< 0x00000080 */\r
+#define EXTI_SWIER_SWIER7 EXTI_SWIER_SWIER7_Msk /*!< Software Interrupt on line 7 */\r
+#define EXTI_SWIER_SWIER8_Pos (8U) \r
+#define EXTI_SWIER_SWIER8_Msk (0x1UL << EXTI_SWIER_SWIER8_Pos) /*!< 0x00000100 */\r
+#define EXTI_SWIER_SWIER8 EXTI_SWIER_SWIER8_Msk /*!< Software Interrupt on line 8 */\r
+#define EXTI_SWIER_SWIER9_Pos (9U) \r
+#define EXTI_SWIER_SWIER9_Msk (0x1UL << EXTI_SWIER_SWIER9_Pos) /*!< 0x00000200 */\r
+#define EXTI_SWIER_SWIER9 EXTI_SWIER_SWIER9_Msk /*!< Software Interrupt on line 9 */\r
+#define EXTI_SWIER_SWIER10_Pos (10U) \r
+#define EXTI_SWIER_SWIER10_Msk (0x1UL << EXTI_SWIER_SWIER10_Pos) /*!< 0x00000400 */\r
+#define EXTI_SWIER_SWIER10 EXTI_SWIER_SWIER10_Msk /*!< Software Interrupt on line 10 */\r
+#define EXTI_SWIER_SWIER11_Pos (11U) \r
+#define EXTI_SWIER_SWIER11_Msk (0x1UL << EXTI_SWIER_SWIER11_Pos) /*!< 0x00000800 */\r
+#define EXTI_SWIER_SWIER11 EXTI_SWIER_SWIER11_Msk /*!< Software Interrupt on line 11 */\r
+#define EXTI_SWIER_SWIER12_Pos (12U) \r
+#define EXTI_SWIER_SWIER12_Msk (0x1UL << EXTI_SWIER_SWIER12_Pos) /*!< 0x00001000 */\r
+#define EXTI_SWIER_SWIER12 EXTI_SWIER_SWIER12_Msk /*!< Software Interrupt on line 12 */\r
+#define EXTI_SWIER_SWIER13_Pos (13U) \r
+#define EXTI_SWIER_SWIER13_Msk (0x1UL << EXTI_SWIER_SWIER13_Pos) /*!< 0x00002000 */\r
+#define EXTI_SWIER_SWIER13 EXTI_SWIER_SWIER13_Msk /*!< Software Interrupt on line 13 */\r
+#define EXTI_SWIER_SWIER14_Pos (14U) \r
+#define EXTI_SWIER_SWIER14_Msk (0x1UL << EXTI_SWIER_SWIER14_Pos) /*!< 0x00004000 */\r
+#define EXTI_SWIER_SWIER14 EXTI_SWIER_SWIER14_Msk /*!< Software Interrupt on line 14 */\r
+#define EXTI_SWIER_SWIER15_Pos (15U) \r
+#define EXTI_SWIER_SWIER15_Msk (0x1UL << EXTI_SWIER_SWIER15_Pos) /*!< 0x00008000 */\r
+#define EXTI_SWIER_SWIER15 EXTI_SWIER_SWIER15_Msk /*!< Software Interrupt on line 15 */\r
+#define EXTI_SWIER_SWIER16_Pos (16U) \r
+#define EXTI_SWIER_SWIER16_Msk (0x1UL << EXTI_SWIER_SWIER16_Pos) /*!< 0x00010000 */\r
+#define EXTI_SWIER_SWIER16 EXTI_SWIER_SWIER16_Msk /*!< Software Interrupt on line 16 */\r
+#define EXTI_SWIER_SWIER17_Pos (17U) \r
+#define EXTI_SWIER_SWIER17_Msk (0x1UL << EXTI_SWIER_SWIER17_Pos) /*!< 0x00020000 */\r
+#define EXTI_SWIER_SWIER17 EXTI_SWIER_SWIER17_Msk /*!< Software Interrupt on line 17 */\r
+#define EXTI_SWIER_SWIER18_Pos (18U) \r
+#define EXTI_SWIER_SWIER18_Msk (0x1UL << EXTI_SWIER_SWIER18_Pos) /*!< 0x00040000 */\r
+#define EXTI_SWIER_SWIER18 EXTI_SWIER_SWIER18_Msk /*!< Software Interrupt on line 18 */\r
+#define EXTI_SWIER_SWIER19_Pos (19U) \r
+#define EXTI_SWIER_SWIER19_Msk (0x1UL << EXTI_SWIER_SWIER19_Pos) /*!< 0x00080000 */\r
+#define EXTI_SWIER_SWIER19 EXTI_SWIER_SWIER19_Msk /*!< Software Interrupt on line 19 */\r
+#define EXTI_SWIER_SWIER20_Pos (20U) \r
+#define EXTI_SWIER_SWIER20_Msk (0x1UL << EXTI_SWIER_SWIER20_Pos) /*!< 0x00100000 */\r
+#define EXTI_SWIER_SWIER20 EXTI_SWIER_SWIER20_Msk /*!< Software Interrupt on line 20 */\r
+#define EXTI_SWIER_SWIER21_Pos (21U) \r
+#define EXTI_SWIER_SWIER21_Msk (0x1UL << EXTI_SWIER_SWIER21_Pos) /*!< 0x00200000 */\r
+#define EXTI_SWIER_SWIER21 EXTI_SWIER_SWIER21_Msk /*!< Software Interrupt on line 21 */\r
+#define EXTI_SWIER_SWIER22_Pos (22U) \r
+#define EXTI_SWIER_SWIER22_Msk (0x1UL << EXTI_SWIER_SWIER22_Pos) /*!< 0x00400000 */\r
+#define EXTI_SWIER_SWIER22 EXTI_SWIER_SWIER22_Msk /*!< Software Interrupt on line 22 */\r
+#define EXTI_SWIER_SWIER23_Pos (23U) \r
+#define EXTI_SWIER_SWIER23_Msk (0x1UL << EXTI_SWIER_SWIER23_Pos) /*!< 0x00800000 */\r
+#define EXTI_SWIER_SWIER23 EXTI_SWIER_SWIER23_Msk /*!< Software Interrupt on line 23 */\r
+\r
+/* References Defines */\r
+#define EXTI_SWIER_SWI0 EXTI_SWIER_SWIER0\r
+#define EXTI_SWIER_SWI1 EXTI_SWIER_SWIER1\r
+#define EXTI_SWIER_SWI2 EXTI_SWIER_SWIER2\r
+#define EXTI_SWIER_SWI3 EXTI_SWIER_SWIER3\r
+#define EXTI_SWIER_SWI4 EXTI_SWIER_SWIER4\r
+#define EXTI_SWIER_SWI5 EXTI_SWIER_SWIER5\r
+#define EXTI_SWIER_SWI6 EXTI_SWIER_SWIER6\r
+#define EXTI_SWIER_SWI7 EXTI_SWIER_SWIER7\r
+#define EXTI_SWIER_SWI8 EXTI_SWIER_SWIER8\r
+#define EXTI_SWIER_SWI9 EXTI_SWIER_SWIER9\r
+#define EXTI_SWIER_SWI10 EXTI_SWIER_SWIER10\r
+#define EXTI_SWIER_SWI11 EXTI_SWIER_SWIER11\r
+#define EXTI_SWIER_SWI12 EXTI_SWIER_SWIER12\r
+#define EXTI_SWIER_SWI13 EXTI_SWIER_SWIER13\r
+#define EXTI_SWIER_SWI14 EXTI_SWIER_SWIER14\r
+#define EXTI_SWIER_SWI15 EXTI_SWIER_SWIER15\r
+#define EXTI_SWIER_SWI16 EXTI_SWIER_SWIER16\r
+#define EXTI_SWIER_SWI17 EXTI_SWIER_SWIER17\r
+#define EXTI_SWIER_SWI18 EXTI_SWIER_SWIER18\r
+#define EXTI_SWIER_SWI19 EXTI_SWIER_SWIER19\r
+#define EXTI_SWIER_SWI20 EXTI_SWIER_SWIER20\r
+#define EXTI_SWIER_SWI21 EXTI_SWIER_SWIER21\r
+#define EXTI_SWIER_SWI22 EXTI_SWIER_SWIER22\r
+#define EXTI_SWIER_SWI23 EXTI_SWIER_SWIER23\r
+\r
+/******************* Bit definition for EXTI_PR register ********************/\r
+#define EXTI_PR_PR0_Pos (0U) \r
+#define EXTI_PR_PR0_Msk (0x1UL << EXTI_PR_PR0_Pos) /*!< 0x00000001 */\r
+#define EXTI_PR_PR0 EXTI_PR_PR0_Msk /*!< Pending bit for line 0 */\r
+#define EXTI_PR_PR1_Pos (1U) \r
+#define EXTI_PR_PR1_Msk (0x1UL << EXTI_PR_PR1_Pos) /*!< 0x00000002 */\r
+#define EXTI_PR_PR1 EXTI_PR_PR1_Msk /*!< Pending bit for line 1 */\r
+#define EXTI_PR_PR2_Pos (2U) \r
+#define EXTI_PR_PR2_Msk (0x1UL << EXTI_PR_PR2_Pos) /*!< 0x00000004 */\r
+#define EXTI_PR_PR2 EXTI_PR_PR2_Msk /*!< Pending bit for line 2 */\r
+#define EXTI_PR_PR3_Pos (3U) \r
+#define EXTI_PR_PR3_Msk (0x1UL << EXTI_PR_PR3_Pos) /*!< 0x00000008 */\r
+#define EXTI_PR_PR3 EXTI_PR_PR3_Msk /*!< Pending bit for line 3 */\r
+#define EXTI_PR_PR4_Pos (4U) \r
+#define EXTI_PR_PR4_Msk (0x1UL << EXTI_PR_PR4_Pos) /*!< 0x00000010 */\r
+#define EXTI_PR_PR4 EXTI_PR_PR4_Msk /*!< Pending bit for line 4 */\r
+#define EXTI_PR_PR5_Pos (5U) \r
+#define EXTI_PR_PR5_Msk (0x1UL << EXTI_PR_PR5_Pos) /*!< 0x00000020 */\r
+#define EXTI_PR_PR5 EXTI_PR_PR5_Msk /*!< Pending bit for line 5 */\r
+#define EXTI_PR_PR6_Pos (6U) \r
+#define EXTI_PR_PR6_Msk (0x1UL << EXTI_PR_PR6_Pos) /*!< 0x00000040 */\r
+#define EXTI_PR_PR6 EXTI_PR_PR6_Msk /*!< Pending bit for line 6 */\r
+#define EXTI_PR_PR7_Pos (7U) \r
+#define EXTI_PR_PR7_Msk (0x1UL << EXTI_PR_PR7_Pos) /*!< 0x00000080 */\r
+#define EXTI_PR_PR7 EXTI_PR_PR7_Msk /*!< Pending bit for line 7 */\r
+#define EXTI_PR_PR8_Pos (8U) \r
+#define EXTI_PR_PR8_Msk (0x1UL << EXTI_PR_PR8_Pos) /*!< 0x00000100 */\r
+#define EXTI_PR_PR8 EXTI_PR_PR8_Msk /*!< Pending bit for line 8 */\r
+#define EXTI_PR_PR9_Pos (9U) \r
+#define EXTI_PR_PR9_Msk (0x1UL << EXTI_PR_PR9_Pos) /*!< 0x00000200 */\r
+#define EXTI_PR_PR9 EXTI_PR_PR9_Msk /*!< Pending bit for line 9 */\r
+#define EXTI_PR_PR10_Pos (10U) \r
+#define EXTI_PR_PR10_Msk (0x1UL << EXTI_PR_PR10_Pos) /*!< 0x00000400 */\r
+#define EXTI_PR_PR10 EXTI_PR_PR10_Msk /*!< Pending bit for line 10 */\r
+#define EXTI_PR_PR11_Pos (11U) \r
+#define EXTI_PR_PR11_Msk (0x1UL << EXTI_PR_PR11_Pos) /*!< 0x00000800 */\r
+#define EXTI_PR_PR11 EXTI_PR_PR11_Msk /*!< Pending bit for line 11 */\r
+#define EXTI_PR_PR12_Pos (12U) \r
+#define EXTI_PR_PR12_Msk (0x1UL << EXTI_PR_PR12_Pos) /*!< 0x00001000 */\r
+#define EXTI_PR_PR12 EXTI_PR_PR12_Msk /*!< Pending bit for line 12 */\r
+#define EXTI_PR_PR13_Pos (13U) \r
+#define EXTI_PR_PR13_Msk (0x1UL << EXTI_PR_PR13_Pos) /*!< 0x00002000 */\r
+#define EXTI_PR_PR13 EXTI_PR_PR13_Msk /*!< Pending bit for line 13 */\r
+#define EXTI_PR_PR14_Pos (14U) \r
+#define EXTI_PR_PR14_Msk (0x1UL << EXTI_PR_PR14_Pos) /*!< 0x00004000 */\r
+#define EXTI_PR_PR14 EXTI_PR_PR14_Msk /*!< Pending bit for line 14 */\r
+#define EXTI_PR_PR15_Pos (15U) \r
+#define EXTI_PR_PR15_Msk (0x1UL << EXTI_PR_PR15_Pos) /*!< 0x00008000 */\r
+#define EXTI_PR_PR15 EXTI_PR_PR15_Msk /*!< Pending bit for line 15 */\r
+#define EXTI_PR_PR16_Pos (16U) \r
+#define EXTI_PR_PR16_Msk (0x1UL << EXTI_PR_PR16_Pos) /*!< 0x00010000 */\r
+#define EXTI_PR_PR16 EXTI_PR_PR16_Msk /*!< Pending bit for line 16 */\r
+#define EXTI_PR_PR17_Pos (17U) \r
+#define EXTI_PR_PR17_Msk (0x1UL << EXTI_PR_PR17_Pos) /*!< 0x00020000 */\r
+#define EXTI_PR_PR17 EXTI_PR_PR17_Msk /*!< Pending bit for line 17 */\r
+#define EXTI_PR_PR18_Pos (18U) \r
+#define EXTI_PR_PR18_Msk (0x1UL << EXTI_PR_PR18_Pos) /*!< 0x00040000 */\r
+#define EXTI_PR_PR18 EXTI_PR_PR18_Msk /*!< Pending bit for line 18 */\r
+#define EXTI_PR_PR19_Pos (19U) \r
+#define EXTI_PR_PR19_Msk (0x1UL << EXTI_PR_PR19_Pos) /*!< 0x00080000 */\r
+#define EXTI_PR_PR19 EXTI_PR_PR19_Msk /*!< Pending bit for line 19 */\r
+#define EXTI_PR_PR20_Pos (20U) \r
+#define EXTI_PR_PR20_Msk (0x1UL << EXTI_PR_PR20_Pos) /*!< 0x00100000 */\r
+#define EXTI_PR_PR20 EXTI_PR_PR20_Msk /*!< Pending bit for line 20 */\r
+#define EXTI_PR_PR21_Pos (21U) \r
+#define EXTI_PR_PR21_Msk (0x1UL << EXTI_PR_PR21_Pos) /*!< 0x00200000 */\r
+#define EXTI_PR_PR21 EXTI_PR_PR21_Msk /*!< Pending bit for line 21 */\r
+#define EXTI_PR_PR22_Pos (22U) \r
+#define EXTI_PR_PR22_Msk (0x1UL << EXTI_PR_PR22_Pos) /*!< 0x00400000 */\r
+#define EXTI_PR_PR22 EXTI_PR_PR22_Msk /*!< Pending bit for line 22 */\r
+#define EXTI_PR_PR23_Pos (23U) \r
+#define EXTI_PR_PR23_Msk (0x1UL << EXTI_PR_PR23_Pos) /*!< 0x00800000 */\r
+#define EXTI_PR_PR23 EXTI_PR_PR23_Msk /*!< Pending bit for line 23 */\r
+\r
+/* References Defines */\r
+#define EXTI_PR_PIF0 EXTI_PR_PR0\r
+#define EXTI_PR_PIF1 EXTI_PR_PR1\r
+#define EXTI_PR_PIF2 EXTI_PR_PR2\r
+#define EXTI_PR_PIF3 EXTI_PR_PR3\r
+#define EXTI_PR_PIF4 EXTI_PR_PR4\r
+#define EXTI_PR_PIF5 EXTI_PR_PR5\r
+#define EXTI_PR_PIF6 EXTI_PR_PR6\r
+#define EXTI_PR_PIF7 EXTI_PR_PR7\r
+#define EXTI_PR_PIF8 EXTI_PR_PR8\r
+#define EXTI_PR_PIF9 EXTI_PR_PR9\r
+#define EXTI_PR_PIF10 EXTI_PR_PR10\r
+#define EXTI_PR_PIF11 EXTI_PR_PR11\r
+#define EXTI_PR_PIF12 EXTI_PR_PR12\r
+#define EXTI_PR_PIF13 EXTI_PR_PR13\r
+#define EXTI_PR_PIF14 EXTI_PR_PR14\r
+#define EXTI_PR_PIF15 EXTI_PR_PR15\r
+#define EXTI_PR_PIF16 EXTI_PR_PR16\r
+#define EXTI_PR_PIF17 EXTI_PR_PR17\r
+#define EXTI_PR_PIF18 EXTI_PR_PR18\r
+#define EXTI_PR_PIF19 EXTI_PR_PR19\r
+#define EXTI_PR_PIF20 EXTI_PR_PR20\r
+#define EXTI_PR_PIF21 EXTI_PR_PR21\r
+#define EXTI_PR_PIF22 EXTI_PR_PR22\r
+#define EXTI_PR_PIF23 EXTI_PR_PR23\r
+\r
+/******************************************************************************/\r
+/* */\r
+/* FLASH, DATA EEPROM and Option Bytes Registers */\r
+/* (FLASH, DATA_EEPROM, OB) */\r
+/* */\r
+/******************************************************************************/\r
+\r
+/******************* Bit definition for FLASH_ACR register ******************/\r
+#define FLASH_ACR_LATENCY_Pos (0U) \r
+#define FLASH_ACR_LATENCY_Msk (0x1UL << FLASH_ACR_LATENCY_Pos) /*!< 0x00000001 */\r
+#define FLASH_ACR_LATENCY FLASH_ACR_LATENCY_Msk /*!< Latency */\r
+#define FLASH_ACR_PRFTEN_Pos (1U) \r
+#define FLASH_ACR_PRFTEN_Msk (0x1UL << FLASH_ACR_PRFTEN_Pos) /*!< 0x00000002 */\r
+#define FLASH_ACR_PRFTEN FLASH_ACR_PRFTEN_Msk /*!< Prefetch Buffer Enable */\r
+#define FLASH_ACR_ACC64_Pos (2U) \r
+#define FLASH_ACR_ACC64_Msk (0x1UL << FLASH_ACR_ACC64_Pos) /*!< 0x00000004 */\r
+#define FLASH_ACR_ACC64 FLASH_ACR_ACC64_Msk /*!< Access 64 bits */\r
+#define FLASH_ACR_SLEEP_PD_Pos (3U) \r
+#define FLASH_ACR_SLEEP_PD_Msk (0x1UL << FLASH_ACR_SLEEP_PD_Pos) /*!< 0x00000008 */\r
+#define FLASH_ACR_SLEEP_PD FLASH_ACR_SLEEP_PD_Msk /*!< Flash mode during sleep mode */\r
+#define FLASH_ACR_RUN_PD_Pos (4U) \r
+#define FLASH_ACR_RUN_PD_Msk (0x1UL << FLASH_ACR_RUN_PD_Pos) /*!< 0x00000010 */\r
+#define FLASH_ACR_RUN_PD FLASH_ACR_RUN_PD_Msk /*!< Flash mode during RUN mode */\r
+\r
+/******************* Bit definition for FLASH_PECR register ******************/\r
+#define FLASH_PECR_PELOCK_Pos (0U) \r
+#define FLASH_PECR_PELOCK_Msk (0x1UL << FLASH_PECR_PELOCK_Pos) /*!< 0x00000001 */\r
+#define FLASH_PECR_PELOCK FLASH_PECR_PELOCK_Msk /*!< FLASH_PECR and Flash data Lock */\r
+#define FLASH_PECR_PRGLOCK_Pos (1U) \r
+#define FLASH_PECR_PRGLOCK_Msk (0x1UL << FLASH_PECR_PRGLOCK_Pos) /*!< 0x00000002 */\r
+#define FLASH_PECR_PRGLOCK FLASH_PECR_PRGLOCK_Msk /*!< Program matrix Lock */\r
+#define FLASH_PECR_OPTLOCK_Pos (2U) \r
+#define FLASH_PECR_OPTLOCK_Msk (0x1UL << FLASH_PECR_OPTLOCK_Pos) /*!< 0x00000004 */\r
+#define FLASH_PECR_OPTLOCK FLASH_PECR_OPTLOCK_Msk /*!< Option byte matrix Lock */\r
+#define FLASH_PECR_PROG_Pos (3U) \r
+#define FLASH_PECR_PROG_Msk (0x1UL << FLASH_PECR_PROG_Pos) /*!< 0x00000008 */\r
+#define FLASH_PECR_PROG FLASH_PECR_PROG_Msk /*!< Program matrix selection */\r
+#define FLASH_PECR_DATA_Pos (4U) \r
+#define FLASH_PECR_DATA_Msk (0x1UL << FLASH_PECR_DATA_Pos) /*!< 0x00000010 */\r
+#define FLASH_PECR_DATA FLASH_PECR_DATA_Msk /*!< Data matrix selection */\r
+#define FLASH_PECR_FTDW_Pos (8U) \r
+#define FLASH_PECR_FTDW_Msk (0x1UL << FLASH_PECR_FTDW_Pos) /*!< 0x00000100 */\r
+#define FLASH_PECR_FTDW FLASH_PECR_FTDW_Msk /*!< Fixed Time Data write for Word/Half Word/Byte programming */\r
+#define FLASH_PECR_ERASE_Pos (9U) \r
+#define FLASH_PECR_ERASE_Msk (0x1UL << FLASH_PECR_ERASE_Pos) /*!< 0x00000200 */\r
+#define FLASH_PECR_ERASE FLASH_PECR_ERASE_Msk /*!< Page erasing mode */\r
+#define FLASH_PECR_FPRG_Pos (10U) \r
+#define FLASH_PECR_FPRG_Msk (0x1UL << FLASH_PECR_FPRG_Pos) /*!< 0x00000400 */\r
+#define FLASH_PECR_FPRG FLASH_PECR_FPRG_Msk /*!< Fast Page/Half Page programming mode */\r
+#define FLASH_PECR_PARALLBANK_Pos (15U) \r
+#define FLASH_PECR_PARALLBANK_Msk (0x1UL << FLASH_PECR_PARALLBANK_Pos) /*!< 0x00008000 */\r
+#define FLASH_PECR_PARALLBANK FLASH_PECR_PARALLBANK_Msk /*!< Parallel Bank mode */\r
+#define FLASH_PECR_EOPIE_Pos (16U) \r
+#define FLASH_PECR_EOPIE_Msk (0x1UL << FLASH_PECR_EOPIE_Pos) /*!< 0x00010000 */\r
+#define FLASH_PECR_EOPIE FLASH_PECR_EOPIE_Msk /*!< End of programming interrupt */ \r
+#define FLASH_PECR_ERRIE_Pos (17U) \r
+#define FLASH_PECR_ERRIE_Msk (0x1UL << FLASH_PECR_ERRIE_Pos) /*!< 0x00020000 */\r
+#define FLASH_PECR_ERRIE FLASH_PECR_ERRIE_Msk /*!< Error interrupt */ \r
+#define FLASH_PECR_OBL_LAUNCH_Pos (18U) \r
+#define FLASH_PECR_OBL_LAUNCH_Msk (0x1UL << FLASH_PECR_OBL_LAUNCH_Pos) /*!< 0x00040000 */\r
+#define FLASH_PECR_OBL_LAUNCH FLASH_PECR_OBL_LAUNCH_Msk /*!< Launch the option byte loading */ \r
+\r
+/****************** Bit definition for FLASH_PDKEYR register ******************/\r
+#define FLASH_PDKEYR_PDKEYR_Pos (0U) \r
+#define FLASH_PDKEYR_PDKEYR_Msk (0xFFFFFFFFUL << FLASH_PDKEYR_PDKEYR_Pos) /*!< 0xFFFFFFFF */\r
+#define FLASH_PDKEYR_PDKEYR FLASH_PDKEYR_PDKEYR_Msk /*!< FLASH_PEC and data matrix Key */\r
+\r
+/****************** Bit definition for FLASH_PEKEYR register ******************/\r
+#define FLASH_PEKEYR_PEKEYR_Pos (0U) \r
+#define FLASH_PEKEYR_PEKEYR_Msk (0xFFFFFFFFUL << FLASH_PEKEYR_PEKEYR_Pos) /*!< 0xFFFFFFFF */\r
+#define FLASH_PEKEYR_PEKEYR FLASH_PEKEYR_PEKEYR_Msk /*!< FLASH_PEC and data matrix Key */\r
+\r
+/****************** Bit definition for FLASH_PRGKEYR register ******************/\r
+#define FLASH_PRGKEYR_PRGKEYR_Pos (0U) \r
+#define FLASH_PRGKEYR_PRGKEYR_Msk (0xFFFFFFFFUL << FLASH_PRGKEYR_PRGKEYR_Pos) /*!< 0xFFFFFFFF */\r
+#define FLASH_PRGKEYR_PRGKEYR FLASH_PRGKEYR_PRGKEYR_Msk /*!< Program matrix Key */\r
+\r
+/****************** Bit definition for FLASH_OPTKEYR register ******************/\r
+#define FLASH_OPTKEYR_OPTKEYR_Pos (0U) \r
+#define FLASH_OPTKEYR_OPTKEYR_Msk (0xFFFFFFFFUL << FLASH_OPTKEYR_OPTKEYR_Pos) /*!< 0xFFFFFFFF */\r
+#define FLASH_OPTKEYR_OPTKEYR FLASH_OPTKEYR_OPTKEYR_Msk /*!< Option bytes matrix Key */\r
+\r
+/****************** Bit definition for FLASH_SR register *******************/\r
+#define FLASH_SR_BSY_Pos (0U) \r
+#define FLASH_SR_BSY_Msk (0x1UL << FLASH_SR_BSY_Pos) /*!< 0x00000001 */\r
+#define FLASH_SR_BSY FLASH_SR_BSY_Msk /*!< Busy */\r
+#define FLASH_SR_EOP_Pos (1U) \r
+#define FLASH_SR_EOP_Msk (0x1UL << FLASH_SR_EOP_Pos) /*!< 0x00000002 */\r
+#define FLASH_SR_EOP FLASH_SR_EOP_Msk /*!< End Of Programming*/\r
+#define FLASH_SR_ENDHV_Pos (2U) \r
+#define FLASH_SR_ENDHV_Msk (0x1UL << FLASH_SR_ENDHV_Pos) /*!< 0x00000004 */\r
+#define FLASH_SR_ENDHV FLASH_SR_ENDHV_Msk /*!< End of high voltage */\r
+#define FLASH_SR_READY_Pos (3U) \r
+#define FLASH_SR_READY_Msk (0x1UL << FLASH_SR_READY_Pos) /*!< 0x00000008 */\r
+#define FLASH_SR_READY FLASH_SR_READY_Msk /*!< Flash ready after low power mode */\r
+\r
+#define FLASH_SR_WRPERR_Pos (8U) \r
+#define FLASH_SR_WRPERR_Msk (0x1UL << FLASH_SR_WRPERR_Pos) /*!< 0x00000100 */\r
+#define FLASH_SR_WRPERR FLASH_SR_WRPERR_Msk /*!< Write protected error */\r
+#define FLASH_SR_PGAERR_Pos (9U) \r
+#define FLASH_SR_PGAERR_Msk (0x1UL << FLASH_SR_PGAERR_Pos) /*!< 0x00000200 */\r
+#define FLASH_SR_PGAERR FLASH_SR_PGAERR_Msk /*!< Programming Alignment Error */\r
+#define FLASH_SR_SIZERR_Pos (10U) \r
+#define FLASH_SR_SIZERR_Msk (0x1UL << FLASH_SR_SIZERR_Pos) /*!< 0x00000400 */\r
+#define FLASH_SR_SIZERR FLASH_SR_SIZERR_Msk /*!< Size error */\r
+#define FLASH_SR_OPTVERR_Pos (11U) \r
+#define FLASH_SR_OPTVERR_Msk (0x1UL << FLASH_SR_OPTVERR_Pos) /*!< 0x00000800 */\r
+#define FLASH_SR_OPTVERR FLASH_SR_OPTVERR_Msk /*!< Option validity error */\r
+#define FLASH_SR_OPTVERRUSR_Pos (12U) \r
+#define FLASH_SR_OPTVERRUSR_Msk (0x1UL << FLASH_SR_OPTVERRUSR_Pos) /*!< 0x00001000 */\r
+#define FLASH_SR_OPTVERRUSR FLASH_SR_OPTVERRUSR_Msk /*!< Option User validity error */\r
+\r
+/****************** Bit definition for FLASH_OBR register *******************/\r
+#define FLASH_OBR_RDPRT_Pos (0U) \r
+#define FLASH_OBR_RDPRT_Msk (0xFFUL << FLASH_OBR_RDPRT_Pos) /*!< 0x000000FF */\r
+#define FLASH_OBR_RDPRT FLASH_OBR_RDPRT_Msk /*!< Read Protection */\r
+#define FLASH_OBR_BOR_LEV_Pos (16U) \r
+#define FLASH_OBR_BOR_LEV_Msk (0xFUL << FLASH_OBR_BOR_LEV_Pos) /*!< 0x000F0000 */\r
+#define FLASH_OBR_BOR_LEV FLASH_OBR_BOR_LEV_Msk /*!< BOR_LEV[3:0] Brown Out Reset Threshold Level*/\r
+#define FLASH_OBR_USER_Pos (20U) \r
+#define FLASH_OBR_USER_Msk (0xFUL << FLASH_OBR_USER_Pos) /*!< 0x00F00000 */\r
+#define FLASH_OBR_USER FLASH_OBR_USER_Msk /*!< User Option Bytes */\r
+#define FLASH_OBR_IWDG_SW_Pos (20U) \r
+#define FLASH_OBR_IWDG_SW_Msk (0x1UL << FLASH_OBR_IWDG_SW_Pos) /*!< 0x00100000 */\r
+#define FLASH_OBR_IWDG_SW FLASH_OBR_IWDG_SW_Msk /*!< IWDG_SW */\r
+#define FLASH_OBR_nRST_STOP_Pos (21U) \r
+#define FLASH_OBR_nRST_STOP_Msk (0x1UL << FLASH_OBR_nRST_STOP_Pos) /*!< 0x00200000 */\r
+#define FLASH_OBR_nRST_STOP FLASH_OBR_nRST_STOP_Msk /*!< nRST_STOP */\r
+#define FLASH_OBR_nRST_STDBY_Pos (22U) \r
+#define FLASH_OBR_nRST_STDBY_Msk (0x1UL << FLASH_OBR_nRST_STDBY_Pos) /*!< 0x00400000 */\r
+#define FLASH_OBR_nRST_STDBY FLASH_OBR_nRST_STDBY_Msk /*!< nRST_STDBY */\r
+#define FLASH_OBR_nRST_BFB2_Pos (23U) \r
+#define FLASH_OBR_nRST_BFB2_Msk (0x1UL << FLASH_OBR_nRST_BFB2_Pos) /*!< 0x00800000 */\r
+#define FLASH_OBR_nRST_BFB2 FLASH_OBR_nRST_BFB2_Msk /*!< BFB2 */\r
+\r
+/****************** Bit definition for FLASH_WRPR register ******************/\r
+#define FLASH_WRPR1_WRP_Pos (0U) \r
+#define FLASH_WRPR1_WRP_Msk (0xFFFFFFFFUL << FLASH_WRPR1_WRP_Pos) /*!< 0xFFFFFFFF */\r
+#define FLASH_WRPR1_WRP FLASH_WRPR1_WRP_Msk /*!< Write Protect sectors 0 to 31 */\r
+#define FLASH_WRPR2_WRP_Pos (0U) \r
+#define FLASH_WRPR2_WRP_Msk (0xFFFFFFFFUL << FLASH_WRPR2_WRP_Pos) /*!< 0xFFFFFFFF */\r
+#define FLASH_WRPR2_WRP FLASH_WRPR2_WRP_Msk /*!< Write Protect sectors 32 to 63 */ \r
+#define FLASH_WRPR3_WRP_Pos (0U) \r
+#define FLASH_WRPR3_WRP_Msk (0xFFFFFFFFUL << FLASH_WRPR3_WRP_Pos) /*!< 0xFFFFFFFF */\r
+#define FLASH_WRPR3_WRP FLASH_WRPR3_WRP_Msk /*!< Write Protect sectors 64 to 95 */ \r
+#define FLASH_WRPR4_WRP_Pos (0U) \r
+#define FLASH_WRPR4_WRP_Msk (0xFFFFFFFFUL << FLASH_WRPR4_WRP_Pos) /*!< 0xFFFFFFFF */\r
+#define FLASH_WRPR4_WRP FLASH_WRPR4_WRP_Msk /*!< Write Protect sectors 96 to 127 */ \r
+\r
+/******************************************************************************/\r
+/* */\r
+/* General Purpose I/O */\r
+/* */\r
+/******************************************************************************/\r
+/****************** Bits definition for GPIO_MODER register *****************/\r
+#define GPIO_MODER_MODER0_Pos (0U) \r
+#define GPIO_MODER_MODER0_Msk (0x3UL << GPIO_MODER_MODER0_Pos) /*!< 0x00000003 */\r
+#define GPIO_MODER_MODER0 GPIO_MODER_MODER0_Msk \r
+#define GPIO_MODER_MODER0_0 (0x1UL << GPIO_MODER_MODER0_Pos) /*!< 0x00000001 */\r
+#define GPIO_MODER_MODER0_1 (0x2UL << GPIO_MODER_MODER0_Pos) /*!< 0x00000002 */\r
+\r
+#define GPIO_MODER_MODER1_Pos (2U) \r
+#define GPIO_MODER_MODER1_Msk (0x3UL << GPIO_MODER_MODER1_Pos) /*!< 0x0000000C */\r
+#define GPIO_MODER_MODER1 GPIO_MODER_MODER1_Msk \r
+#define GPIO_MODER_MODER1_0 (0x1UL << GPIO_MODER_MODER1_Pos) /*!< 0x00000004 */\r
+#define GPIO_MODER_MODER1_1 (0x2UL << GPIO_MODER_MODER1_Pos) /*!< 0x00000008 */\r
+\r
+#define GPIO_MODER_MODER2_Pos (4U) \r
+#define GPIO_MODER_MODER2_Msk (0x3UL << GPIO_MODER_MODER2_Pos) /*!< 0x00000030 */\r
+#define GPIO_MODER_MODER2 GPIO_MODER_MODER2_Msk \r
+#define GPIO_MODER_MODER2_0 (0x1UL << GPIO_MODER_MODER2_Pos) /*!< 0x00000010 */\r
+#define GPIO_MODER_MODER2_1 (0x2UL << GPIO_MODER_MODER2_Pos) /*!< 0x00000020 */\r
+\r
+#define GPIO_MODER_MODER3_Pos (6U) \r
+#define GPIO_MODER_MODER3_Msk (0x3UL << GPIO_MODER_MODER3_Pos) /*!< 0x000000C0 */\r
+#define GPIO_MODER_MODER3 GPIO_MODER_MODER3_Msk \r
+#define GPIO_MODER_MODER3_0 (0x1UL << GPIO_MODER_MODER3_Pos) /*!< 0x00000040 */\r
+#define GPIO_MODER_MODER3_1 (0x2UL << GPIO_MODER_MODER3_Pos) /*!< 0x00000080 */\r
+\r
+#define GPIO_MODER_MODER4_Pos (8U) \r
+#define GPIO_MODER_MODER4_Msk (0x3UL << GPIO_MODER_MODER4_Pos) /*!< 0x00000300 */\r
+#define GPIO_MODER_MODER4 GPIO_MODER_MODER4_Msk \r
+#define GPIO_MODER_MODER4_0 (0x1UL << GPIO_MODER_MODER4_Pos) /*!< 0x00000100 */\r
+#define GPIO_MODER_MODER4_1 (0x2UL << GPIO_MODER_MODER4_Pos) /*!< 0x00000200 */\r
+\r
+#define GPIO_MODER_MODER5_Pos (10U) \r
+#define GPIO_MODER_MODER5_Msk (0x3UL << GPIO_MODER_MODER5_Pos) /*!< 0x00000C00 */\r
+#define GPIO_MODER_MODER5 GPIO_MODER_MODER5_Msk \r
+#define GPIO_MODER_MODER5_0 (0x1UL << GPIO_MODER_MODER5_Pos) /*!< 0x00000400 */\r
+#define GPIO_MODER_MODER5_1 (0x2UL << GPIO_MODER_MODER5_Pos) /*!< 0x00000800 */\r
+\r
+#define GPIO_MODER_MODER6_Pos (12U) \r
+#define GPIO_MODER_MODER6_Msk (0x3UL << GPIO_MODER_MODER6_Pos) /*!< 0x00003000 */\r
+#define GPIO_MODER_MODER6 GPIO_MODER_MODER6_Msk \r
+#define GPIO_MODER_MODER6_0 (0x1UL << GPIO_MODER_MODER6_Pos) /*!< 0x00001000 */\r
+#define GPIO_MODER_MODER6_1 (0x2UL << GPIO_MODER_MODER6_Pos) /*!< 0x00002000 */\r
+\r
+#define GPIO_MODER_MODER7_Pos (14U) \r
+#define GPIO_MODER_MODER7_Msk (0x3UL << GPIO_MODER_MODER7_Pos) /*!< 0x0000C000 */\r
+#define GPIO_MODER_MODER7 GPIO_MODER_MODER7_Msk \r
+#define GPIO_MODER_MODER7_0 (0x1UL << GPIO_MODER_MODER7_Pos) /*!< 0x00004000 */\r
+#define GPIO_MODER_MODER7_1 (0x2UL << GPIO_MODER_MODER7_Pos) /*!< 0x00008000 */\r
+\r
+#define GPIO_MODER_MODER8_Pos (16U) \r
+#define GPIO_MODER_MODER8_Msk (0x3UL << GPIO_MODER_MODER8_Pos) /*!< 0x00030000 */\r
+#define GPIO_MODER_MODER8 GPIO_MODER_MODER8_Msk \r
+#define GPIO_MODER_MODER8_0 (0x1UL << GPIO_MODER_MODER8_Pos) /*!< 0x00010000 */\r
+#define GPIO_MODER_MODER8_1 (0x2UL << GPIO_MODER_MODER8_Pos) /*!< 0x00020000 */\r
+\r
+#define GPIO_MODER_MODER9_Pos (18U) \r
+#define GPIO_MODER_MODER9_Msk (0x3UL << GPIO_MODER_MODER9_Pos) /*!< 0x000C0000 */\r
+#define GPIO_MODER_MODER9 GPIO_MODER_MODER9_Msk \r
+#define GPIO_MODER_MODER9_0 (0x1UL << GPIO_MODER_MODER9_Pos) /*!< 0x00040000 */\r
+#define GPIO_MODER_MODER9_1 (0x2UL << GPIO_MODER_MODER9_Pos) /*!< 0x00080000 */\r
+\r
+#define GPIO_MODER_MODER10_Pos (20U) \r
+#define GPIO_MODER_MODER10_Msk (0x3UL << GPIO_MODER_MODER10_Pos) /*!< 0x00300000 */\r
+#define GPIO_MODER_MODER10 GPIO_MODER_MODER10_Msk \r
+#define GPIO_MODER_MODER10_0 (0x1UL << GPIO_MODER_MODER10_Pos) /*!< 0x00100000 */\r
+#define GPIO_MODER_MODER10_1 (0x2UL << GPIO_MODER_MODER10_Pos) /*!< 0x00200000 */\r
+\r
+#define GPIO_MODER_MODER11_Pos (22U) \r
+#define GPIO_MODER_MODER11_Msk (0x3UL << GPIO_MODER_MODER11_Pos) /*!< 0x00C00000 */\r
+#define GPIO_MODER_MODER11 GPIO_MODER_MODER11_Msk \r
+#define GPIO_MODER_MODER11_0 (0x1UL << GPIO_MODER_MODER11_Pos) /*!< 0x00400000 */\r
+#define GPIO_MODER_MODER11_1 (0x2UL << GPIO_MODER_MODER11_Pos) /*!< 0x00800000 */\r
+\r
+#define GPIO_MODER_MODER12_Pos (24U) \r
+#define GPIO_MODER_MODER12_Msk (0x3UL << GPIO_MODER_MODER12_Pos) /*!< 0x03000000 */\r
+#define GPIO_MODER_MODER12 GPIO_MODER_MODER12_Msk \r
+#define GPIO_MODER_MODER12_0 (0x1UL << GPIO_MODER_MODER12_Pos) /*!< 0x01000000 */\r
+#define GPIO_MODER_MODER12_1 (0x2UL << GPIO_MODER_MODER12_Pos) /*!< 0x02000000 */\r
+\r
+#define GPIO_MODER_MODER13_Pos (26U) \r
+#define GPIO_MODER_MODER13_Msk (0x3UL << GPIO_MODER_MODER13_Pos) /*!< 0x0C000000 */\r
+#define GPIO_MODER_MODER13 GPIO_MODER_MODER13_Msk \r
+#define GPIO_MODER_MODER13_0 (0x1UL << GPIO_MODER_MODER13_Pos) /*!< 0x04000000 */\r
+#define GPIO_MODER_MODER13_1 (0x2UL << GPIO_MODER_MODER13_Pos) /*!< 0x08000000 */\r
+\r
+#define GPIO_MODER_MODER14_Pos (28U) \r
+#define GPIO_MODER_MODER14_Msk (0x3UL << GPIO_MODER_MODER14_Pos) /*!< 0x30000000 */\r
+#define GPIO_MODER_MODER14 GPIO_MODER_MODER14_Msk \r
+#define GPIO_MODER_MODER14_0 (0x1UL << GPIO_MODER_MODER14_Pos) /*!< 0x10000000 */\r
+#define GPIO_MODER_MODER14_1 (0x2UL << GPIO_MODER_MODER14_Pos) /*!< 0x20000000 */\r
+\r
+#define GPIO_MODER_MODER15_Pos (30U) \r
+#define GPIO_MODER_MODER15_Msk (0x3UL << GPIO_MODER_MODER15_Pos) /*!< 0xC0000000 */\r
+#define GPIO_MODER_MODER15 GPIO_MODER_MODER15_Msk \r
+#define GPIO_MODER_MODER15_0 (0x1UL << GPIO_MODER_MODER15_Pos) /*!< 0x40000000 */\r
+#define GPIO_MODER_MODER15_1 (0x2UL << GPIO_MODER_MODER15_Pos) /*!< 0x80000000 */\r
+\r
+/****************** Bits definition for GPIO_OTYPER register ****************/\r
+#define GPIO_OTYPER_OT_0 (0x00000001U) \r
+#define GPIO_OTYPER_OT_1 (0x00000002U) \r
+#define GPIO_OTYPER_OT_2 (0x00000004U) \r
+#define GPIO_OTYPER_OT_3 (0x00000008U) \r
+#define GPIO_OTYPER_OT_4 (0x00000010U) \r
+#define GPIO_OTYPER_OT_5 (0x00000020U) \r
+#define GPIO_OTYPER_OT_6 (0x00000040U) \r
+#define GPIO_OTYPER_OT_7 (0x00000080U) \r
+#define GPIO_OTYPER_OT_8 (0x00000100U) \r
+#define GPIO_OTYPER_OT_9 (0x00000200U) \r
+#define GPIO_OTYPER_OT_10 (0x00000400U) \r
+#define GPIO_OTYPER_OT_11 (0x00000800U) \r
+#define GPIO_OTYPER_OT_12 (0x00001000U) \r
+#define GPIO_OTYPER_OT_13 (0x00002000U) \r
+#define GPIO_OTYPER_OT_14 (0x00004000U) \r
+#define GPIO_OTYPER_OT_15 (0x00008000U) \r
+\r
+/****************** Bits definition for GPIO_OSPEEDR register ***************/\r
+#define GPIO_OSPEEDER_OSPEEDR0_Pos (0U) \r
+#define GPIO_OSPEEDER_OSPEEDR0_Msk (0x3UL << GPIO_OSPEEDER_OSPEEDR0_Pos) /*!< 0x00000003 */\r
+#define GPIO_OSPEEDER_OSPEEDR0 GPIO_OSPEEDER_OSPEEDR0_Msk \r
+#define GPIO_OSPEEDER_OSPEEDR0_0 (0x1UL << GPIO_OSPEEDER_OSPEEDR0_Pos) /*!< 0x00000001 */\r
+#define GPIO_OSPEEDER_OSPEEDR0_1 (0x2UL << GPIO_OSPEEDER_OSPEEDR0_Pos) /*!< 0x00000002 */\r
+\r
+#define GPIO_OSPEEDER_OSPEEDR1_Pos (2U) \r
+#define GPIO_OSPEEDER_OSPEEDR1_Msk (0x3UL << GPIO_OSPEEDER_OSPEEDR1_Pos) /*!< 0x0000000C */\r
+#define GPIO_OSPEEDER_OSPEEDR1 GPIO_OSPEEDER_OSPEEDR1_Msk \r
+#define GPIO_OSPEEDER_OSPEEDR1_0 (0x1UL << GPIO_OSPEEDER_OSPEEDR1_Pos) /*!< 0x00000004 */\r
+#define GPIO_OSPEEDER_OSPEEDR1_1 (0x2UL << GPIO_OSPEEDER_OSPEEDR1_Pos) /*!< 0x00000008 */\r
+\r
+#define GPIO_OSPEEDER_OSPEEDR2_Pos (4U) \r
+#define GPIO_OSPEEDER_OSPEEDR2_Msk (0x3UL << GPIO_OSPEEDER_OSPEEDR2_Pos) /*!< 0x00000030 */\r
+#define GPIO_OSPEEDER_OSPEEDR2 GPIO_OSPEEDER_OSPEEDR2_Msk \r
+#define GPIO_OSPEEDER_OSPEEDR2_0 (0x1UL << GPIO_OSPEEDER_OSPEEDR2_Pos) /*!< 0x00000010 */\r
+#define GPIO_OSPEEDER_OSPEEDR2_1 (0x2UL << GPIO_OSPEEDER_OSPEEDR2_Pos) /*!< 0x00000020 */\r
+\r
+#define GPIO_OSPEEDER_OSPEEDR3_Pos (6U) \r
+#define GPIO_OSPEEDER_OSPEEDR3_Msk (0x3UL << GPIO_OSPEEDER_OSPEEDR3_Pos) /*!< 0x000000C0 */\r
+#define GPIO_OSPEEDER_OSPEEDR3 GPIO_OSPEEDER_OSPEEDR3_Msk \r
+#define GPIO_OSPEEDER_OSPEEDR3_0 (0x1UL << GPIO_OSPEEDER_OSPEEDR3_Pos) /*!< 0x00000040 */\r
+#define GPIO_OSPEEDER_OSPEEDR3_1 (0x2UL << GPIO_OSPEEDER_OSPEEDR3_Pos) /*!< 0x00000080 */\r
+\r
+#define GPIO_OSPEEDER_OSPEEDR4_Pos (8U) \r
+#define GPIO_OSPEEDER_OSPEEDR4_Msk (0x3UL << GPIO_OSPEEDER_OSPEEDR4_Pos) /*!< 0x00000300 */\r
+#define GPIO_OSPEEDER_OSPEEDR4 GPIO_OSPEEDER_OSPEEDR4_Msk \r
+#define GPIO_OSPEEDER_OSPEEDR4_0 (0x1UL << GPIO_OSPEEDER_OSPEEDR4_Pos) /*!< 0x00000100 */\r
+#define GPIO_OSPEEDER_OSPEEDR4_1 (0x2UL << GPIO_OSPEEDER_OSPEEDR4_Pos) /*!< 0x00000200 */\r
+\r
+#define GPIO_OSPEEDER_OSPEEDR5_Pos (10U) \r
+#define GPIO_OSPEEDER_OSPEEDR5_Msk (0x3UL << GPIO_OSPEEDER_OSPEEDR5_Pos) /*!< 0x00000C00 */\r
+#define GPIO_OSPEEDER_OSPEEDR5 GPIO_OSPEEDER_OSPEEDR5_Msk \r
+#define GPIO_OSPEEDER_OSPEEDR5_0 (0x1UL << GPIO_OSPEEDER_OSPEEDR5_Pos) /*!< 0x00000400 */\r
+#define GPIO_OSPEEDER_OSPEEDR5_1 (0x2UL << GPIO_OSPEEDER_OSPEEDR5_Pos) /*!< 0x00000800 */\r
+\r
+#define GPIO_OSPEEDER_OSPEEDR6_Pos (12U) \r
+#define GPIO_OSPEEDER_OSPEEDR6_Msk (0x3UL << GPIO_OSPEEDER_OSPEEDR6_Pos) /*!< 0x00003000 */\r
+#define GPIO_OSPEEDER_OSPEEDR6 GPIO_OSPEEDER_OSPEEDR6_Msk \r
+#define GPIO_OSPEEDER_OSPEEDR6_0 (0x1UL << GPIO_OSPEEDER_OSPEEDR6_Pos) /*!< 0x00001000 */\r
+#define GPIO_OSPEEDER_OSPEEDR6_1 (0x2UL << GPIO_OSPEEDER_OSPEEDR6_Pos) /*!< 0x00002000 */\r
+\r
+#define GPIO_OSPEEDER_OSPEEDR7_Pos (14U) \r
+#define GPIO_OSPEEDER_OSPEEDR7_Msk (0x3UL << GPIO_OSPEEDER_OSPEEDR7_Pos) /*!< 0x0000C000 */\r
+#define GPIO_OSPEEDER_OSPEEDR7 GPIO_OSPEEDER_OSPEEDR7_Msk \r
+#define GPIO_OSPEEDER_OSPEEDR7_0 (0x1UL << GPIO_OSPEEDER_OSPEEDR7_Pos) /*!< 0x00004000 */\r
+#define GPIO_OSPEEDER_OSPEEDR7_1 (0x2UL << GPIO_OSPEEDER_OSPEEDR7_Pos) /*!< 0x00008000 */\r
+\r
+#define GPIO_OSPEEDER_OSPEEDR8_Pos (16U) \r
+#define GPIO_OSPEEDER_OSPEEDR8_Msk (0x3UL << GPIO_OSPEEDER_OSPEEDR8_Pos) /*!< 0x00030000 */\r
+#define GPIO_OSPEEDER_OSPEEDR8 GPIO_OSPEEDER_OSPEEDR8_Msk \r
+#define GPIO_OSPEEDER_OSPEEDR8_0 (0x1UL << GPIO_OSPEEDER_OSPEEDR8_Pos) /*!< 0x00010000 */\r
+#define GPIO_OSPEEDER_OSPEEDR8_1 (0x2UL << GPIO_OSPEEDER_OSPEEDR8_Pos) /*!< 0x00020000 */\r
+\r
+#define GPIO_OSPEEDER_OSPEEDR9_Pos (18U) \r
+#define GPIO_OSPEEDER_OSPEEDR9_Msk (0x3UL << GPIO_OSPEEDER_OSPEEDR9_Pos) /*!< 0x000C0000 */\r
+#define GPIO_OSPEEDER_OSPEEDR9 GPIO_OSPEEDER_OSPEEDR9_Msk \r
+#define GPIO_OSPEEDER_OSPEEDR9_0 (0x1UL << GPIO_OSPEEDER_OSPEEDR9_Pos) /*!< 0x00040000 */\r
+#define GPIO_OSPEEDER_OSPEEDR9_1 (0x2UL << GPIO_OSPEEDER_OSPEEDR9_Pos) /*!< 0x00080000 */\r
+\r
+#define GPIO_OSPEEDER_OSPEEDR10_Pos (20U) \r
+#define GPIO_OSPEEDER_OSPEEDR10_Msk (0x3UL << GPIO_OSPEEDER_OSPEEDR10_Pos) /*!< 0x00300000 */\r
+#define GPIO_OSPEEDER_OSPEEDR10 GPIO_OSPEEDER_OSPEEDR10_Msk \r
+#define GPIO_OSPEEDER_OSPEEDR10_0 (0x1UL << GPIO_OSPEEDER_OSPEEDR10_Pos) /*!< 0x00100000 */\r
+#define GPIO_OSPEEDER_OSPEEDR10_1 (0x2UL << GPIO_OSPEEDER_OSPEEDR10_Pos) /*!< 0x00200000 */\r
+\r
+#define GPIO_OSPEEDER_OSPEEDR11_Pos (22U) \r
+#define GPIO_OSPEEDER_OSPEEDR11_Msk (0x3UL << GPIO_OSPEEDER_OSPEEDR11_Pos) /*!< 0x00C00000 */\r
+#define GPIO_OSPEEDER_OSPEEDR11 GPIO_OSPEEDER_OSPEEDR11_Msk \r
+#define GPIO_OSPEEDER_OSPEEDR11_0 (0x1UL << GPIO_OSPEEDER_OSPEEDR11_Pos) /*!< 0x00400000 */\r
+#define GPIO_OSPEEDER_OSPEEDR11_1 (0x2UL << GPIO_OSPEEDER_OSPEEDR11_Pos) /*!< 0x00800000 */\r
+\r
+#define GPIO_OSPEEDER_OSPEEDR12_Pos (24U) \r
+#define GPIO_OSPEEDER_OSPEEDR12_Msk (0x3UL << GPIO_OSPEEDER_OSPEEDR12_Pos) /*!< 0x03000000 */\r
+#define GPIO_OSPEEDER_OSPEEDR12 GPIO_OSPEEDER_OSPEEDR12_Msk \r
+#define GPIO_OSPEEDER_OSPEEDR12_0 (0x1UL << GPIO_OSPEEDER_OSPEEDR12_Pos) /*!< 0x01000000 */\r
+#define GPIO_OSPEEDER_OSPEEDR12_1 (0x2UL << GPIO_OSPEEDER_OSPEEDR12_Pos) /*!< 0x02000000 */\r
+\r
+#define GPIO_OSPEEDER_OSPEEDR13_Pos (26U) \r
+#define GPIO_OSPEEDER_OSPEEDR13_Msk (0x3UL << GPIO_OSPEEDER_OSPEEDR13_Pos) /*!< 0x0C000000 */\r
+#define GPIO_OSPEEDER_OSPEEDR13 GPIO_OSPEEDER_OSPEEDR13_Msk \r
+#define GPIO_OSPEEDER_OSPEEDR13_0 (0x1UL << GPIO_OSPEEDER_OSPEEDR13_Pos) /*!< 0x04000000 */\r
+#define GPIO_OSPEEDER_OSPEEDR13_1 (0x2UL << GPIO_OSPEEDER_OSPEEDR13_Pos) /*!< 0x08000000 */\r
+\r
+#define GPIO_OSPEEDER_OSPEEDR14_Pos (28U) \r
+#define GPIO_OSPEEDER_OSPEEDR14_Msk (0x3UL << GPIO_OSPEEDER_OSPEEDR14_Pos) /*!< 0x30000000 */\r
+#define GPIO_OSPEEDER_OSPEEDR14 GPIO_OSPEEDER_OSPEEDR14_Msk \r
+#define GPIO_OSPEEDER_OSPEEDR14_0 (0x1UL << GPIO_OSPEEDER_OSPEEDR14_Pos) /*!< 0x10000000 */\r
+#define GPIO_OSPEEDER_OSPEEDR14_1 (0x2UL << GPIO_OSPEEDER_OSPEEDR14_Pos) /*!< 0x20000000 */\r
+\r
+#define GPIO_OSPEEDER_OSPEEDR15_Pos (30U) \r
+#define GPIO_OSPEEDER_OSPEEDR15_Msk (0x3UL << GPIO_OSPEEDER_OSPEEDR15_Pos) /*!< 0xC0000000 */\r
+#define GPIO_OSPEEDER_OSPEEDR15 GPIO_OSPEEDER_OSPEEDR15_Msk \r
+#define GPIO_OSPEEDER_OSPEEDR15_0 (0x1UL << GPIO_OSPEEDER_OSPEEDR15_Pos) /*!< 0x40000000 */\r
+#define GPIO_OSPEEDER_OSPEEDR15_1 (0x2UL << GPIO_OSPEEDER_OSPEEDR15_Pos) /*!< 0x80000000 */\r
+\r
+/****************** Bits definition for GPIO_PUPDR register *****************/\r
+#define GPIO_PUPDR_PUPDR0_Pos (0U) \r
+#define GPIO_PUPDR_PUPDR0_Msk (0x3UL << GPIO_PUPDR_PUPDR0_Pos) /*!< 0x00000003 */\r
+#define GPIO_PUPDR_PUPDR0 GPIO_PUPDR_PUPDR0_Msk \r
+#define GPIO_PUPDR_PUPDR0_0 (0x1UL << GPIO_PUPDR_PUPDR0_Pos) /*!< 0x00000001 */\r
+#define GPIO_PUPDR_PUPDR0_1 (0x2UL << GPIO_PUPDR_PUPDR0_Pos) /*!< 0x00000002 */\r
+\r
+#define GPIO_PUPDR_PUPDR1_Pos (2U) \r
+#define GPIO_PUPDR_PUPDR1_Msk (0x3UL << GPIO_PUPDR_PUPDR1_Pos) /*!< 0x0000000C */\r
+#define GPIO_PUPDR_PUPDR1 GPIO_PUPDR_PUPDR1_Msk \r
+#define GPIO_PUPDR_PUPDR1_0 (0x1UL << GPIO_PUPDR_PUPDR1_Pos) /*!< 0x00000004 */\r
+#define GPIO_PUPDR_PUPDR1_1 (0x2UL << GPIO_PUPDR_PUPDR1_Pos) /*!< 0x00000008 */\r
+\r
+#define GPIO_PUPDR_PUPDR2_Pos (4U) \r
+#define GPIO_PUPDR_PUPDR2_Msk (0x3UL << GPIO_PUPDR_PUPDR2_Pos) /*!< 0x00000030 */\r
+#define GPIO_PUPDR_PUPDR2 GPIO_PUPDR_PUPDR2_Msk \r
+#define GPIO_PUPDR_PUPDR2_0 (0x1UL << GPIO_PUPDR_PUPDR2_Pos) /*!< 0x00000010 */\r
+#define GPIO_PUPDR_PUPDR2_1 (0x2UL << GPIO_PUPDR_PUPDR2_Pos) /*!< 0x00000020 */\r
+\r
+#define GPIO_PUPDR_PUPDR3_Pos (6U) \r
+#define GPIO_PUPDR_PUPDR3_Msk (0x3UL << GPIO_PUPDR_PUPDR3_Pos) /*!< 0x000000C0 */\r
+#define GPIO_PUPDR_PUPDR3 GPIO_PUPDR_PUPDR3_Msk \r
+#define GPIO_PUPDR_PUPDR3_0 (0x1UL << GPIO_PUPDR_PUPDR3_Pos) /*!< 0x00000040 */\r
+#define GPIO_PUPDR_PUPDR3_1 (0x2UL << GPIO_PUPDR_PUPDR3_Pos) /*!< 0x00000080 */\r
+\r
+#define GPIO_PUPDR_PUPDR4_Pos (8U) \r
+#define GPIO_PUPDR_PUPDR4_Msk (0x3UL << GPIO_PUPDR_PUPDR4_Pos) /*!< 0x00000300 */\r
+#define GPIO_PUPDR_PUPDR4 GPIO_PUPDR_PUPDR4_Msk \r
+#define GPIO_PUPDR_PUPDR4_0 (0x1UL << GPIO_PUPDR_PUPDR4_Pos) /*!< 0x00000100 */\r
+#define GPIO_PUPDR_PUPDR4_1 (0x2UL << GPIO_PUPDR_PUPDR4_Pos) /*!< 0x00000200 */\r
+\r
+#define GPIO_PUPDR_PUPDR5_Pos (10U) \r
+#define GPIO_PUPDR_PUPDR5_Msk (0x3UL << GPIO_PUPDR_PUPDR5_Pos) /*!< 0x00000C00 */\r
+#define GPIO_PUPDR_PUPDR5 GPIO_PUPDR_PUPDR5_Msk \r
+#define GPIO_PUPDR_PUPDR5_0 (0x1UL << GPIO_PUPDR_PUPDR5_Pos) /*!< 0x00000400 */\r
+#define GPIO_PUPDR_PUPDR5_1 (0x2UL << GPIO_PUPDR_PUPDR5_Pos) /*!< 0x00000800 */\r
+\r
+#define GPIO_PUPDR_PUPDR6_Pos (12U) \r
+#define GPIO_PUPDR_PUPDR6_Msk (0x3UL << GPIO_PUPDR_PUPDR6_Pos) /*!< 0x00003000 */\r
+#define GPIO_PUPDR_PUPDR6 GPIO_PUPDR_PUPDR6_Msk \r
+#define GPIO_PUPDR_PUPDR6_0 (0x1UL << GPIO_PUPDR_PUPDR6_Pos) /*!< 0x00001000 */\r
+#define GPIO_PUPDR_PUPDR6_1 (0x2UL << GPIO_PUPDR_PUPDR6_Pos) /*!< 0x00002000 */\r
+\r
+#define GPIO_PUPDR_PUPDR7_Pos (14U) \r
+#define GPIO_PUPDR_PUPDR7_Msk (0x3UL << GPIO_PUPDR_PUPDR7_Pos) /*!< 0x0000C000 */\r
+#define GPIO_PUPDR_PUPDR7 GPIO_PUPDR_PUPDR7_Msk \r
+#define GPIO_PUPDR_PUPDR7_0 (0x1UL << GPIO_PUPDR_PUPDR7_Pos) /*!< 0x00004000 */\r
+#define GPIO_PUPDR_PUPDR7_1 (0x2UL << GPIO_PUPDR_PUPDR7_Pos) /*!< 0x00008000 */\r
+\r
+#define GPIO_PUPDR_PUPDR8_Pos (16U) \r
+#define GPIO_PUPDR_PUPDR8_Msk (0x3UL << GPIO_PUPDR_PUPDR8_Pos) /*!< 0x00030000 */\r
+#define GPIO_PUPDR_PUPDR8 GPIO_PUPDR_PUPDR8_Msk \r
+#define GPIO_PUPDR_PUPDR8_0 (0x1UL << GPIO_PUPDR_PUPDR8_Pos) /*!< 0x00010000 */\r
+#define GPIO_PUPDR_PUPDR8_1 (0x2UL << GPIO_PUPDR_PUPDR8_Pos) /*!< 0x00020000 */\r
+\r
+#define GPIO_PUPDR_PUPDR9_Pos (18U) \r
+#define GPIO_PUPDR_PUPDR9_Msk (0x3UL << GPIO_PUPDR_PUPDR9_Pos) /*!< 0x000C0000 */\r
+#define GPIO_PUPDR_PUPDR9 GPIO_PUPDR_PUPDR9_Msk \r
+#define GPIO_PUPDR_PUPDR9_0 (0x1UL << GPIO_PUPDR_PUPDR9_Pos) /*!< 0x00040000 */\r
+#define GPIO_PUPDR_PUPDR9_1 (0x2UL << GPIO_PUPDR_PUPDR9_Pos) /*!< 0x00080000 */\r
+\r
+#define GPIO_PUPDR_PUPDR10_Pos (20U) \r
+#define GPIO_PUPDR_PUPDR10_Msk (0x3UL << GPIO_PUPDR_PUPDR10_Pos) /*!< 0x00300000 */\r
+#define GPIO_PUPDR_PUPDR10 GPIO_PUPDR_PUPDR10_Msk \r
+#define GPIO_PUPDR_PUPDR10_0 (0x1UL << GPIO_PUPDR_PUPDR10_Pos) /*!< 0x00100000 */\r
+#define GPIO_PUPDR_PUPDR10_1 (0x2UL << GPIO_PUPDR_PUPDR10_Pos) /*!< 0x00200000 */\r
+\r
+#define GPIO_PUPDR_PUPDR11_Pos (22U) \r
+#define GPIO_PUPDR_PUPDR11_Msk (0x3UL << GPIO_PUPDR_PUPDR11_Pos) /*!< 0x00C00000 */\r
+#define GPIO_PUPDR_PUPDR11 GPIO_PUPDR_PUPDR11_Msk \r
+#define GPIO_PUPDR_PUPDR11_0 (0x1UL << GPIO_PUPDR_PUPDR11_Pos) /*!< 0x00400000 */\r
+#define GPIO_PUPDR_PUPDR11_1 (0x2UL << GPIO_PUPDR_PUPDR11_Pos) /*!< 0x00800000 */\r
+\r
+#define GPIO_PUPDR_PUPDR12_Pos (24U) \r
+#define GPIO_PUPDR_PUPDR12_Msk (0x3UL << GPIO_PUPDR_PUPDR12_Pos) /*!< 0x03000000 */\r
+#define GPIO_PUPDR_PUPDR12 GPIO_PUPDR_PUPDR12_Msk \r
+#define GPIO_PUPDR_PUPDR12_0 (0x1UL << GPIO_PUPDR_PUPDR12_Pos) /*!< 0x01000000 */\r
+#define GPIO_PUPDR_PUPDR12_1 (0x2UL << GPIO_PUPDR_PUPDR12_Pos) /*!< 0x02000000 */\r
+\r
+#define GPIO_PUPDR_PUPDR13_Pos (26U) \r
+#define GPIO_PUPDR_PUPDR13_Msk (0x3UL << GPIO_PUPDR_PUPDR13_Pos) /*!< 0x0C000000 */\r
+#define GPIO_PUPDR_PUPDR13 GPIO_PUPDR_PUPDR13_Msk \r
+#define GPIO_PUPDR_PUPDR13_0 (0x1UL << GPIO_PUPDR_PUPDR13_Pos) /*!< 0x04000000 */\r
+#define GPIO_PUPDR_PUPDR13_1 (0x2UL << GPIO_PUPDR_PUPDR13_Pos) /*!< 0x08000000 */\r
+\r
+#define GPIO_PUPDR_PUPDR14_Pos (28U) \r
+#define GPIO_PUPDR_PUPDR14_Msk (0x3UL << GPIO_PUPDR_PUPDR14_Pos) /*!< 0x30000000 */\r
+#define GPIO_PUPDR_PUPDR14 GPIO_PUPDR_PUPDR14_Msk \r
+#define GPIO_PUPDR_PUPDR14_0 (0x1UL << GPIO_PUPDR_PUPDR14_Pos) /*!< 0x10000000 */\r
+#define GPIO_PUPDR_PUPDR14_1 (0x2UL << GPIO_PUPDR_PUPDR14_Pos) /*!< 0x20000000 */\r
+#define GPIO_PUPDR_PUPDR15_Pos (30U) \r
+#define GPIO_PUPDR_PUPDR15_Msk (0x3UL << GPIO_PUPDR_PUPDR15_Pos) /*!< 0xC0000000 */\r
+#define GPIO_PUPDR_PUPDR15 GPIO_PUPDR_PUPDR15_Msk \r
+#define GPIO_PUPDR_PUPDR15_0 (0x1UL << GPIO_PUPDR_PUPDR15_Pos) /*!< 0x40000000 */\r
+#define GPIO_PUPDR_PUPDR15_1 (0x2UL << GPIO_PUPDR_PUPDR15_Pos) /*!< 0x80000000 */\r
+\r
+/****************** Bits definition for GPIO_IDR register *******************/\r
+#define GPIO_IDR_IDR_0 (0x00000001U) \r
+#define GPIO_IDR_IDR_1 (0x00000002U) \r
+#define GPIO_IDR_IDR_2 (0x00000004U) \r
+#define GPIO_IDR_IDR_3 (0x00000008U) \r
+#define GPIO_IDR_IDR_4 (0x00000010U) \r
+#define GPIO_IDR_IDR_5 (0x00000020U) \r
+#define GPIO_IDR_IDR_6 (0x00000040U) \r
+#define GPIO_IDR_IDR_7 (0x00000080U) \r
+#define GPIO_IDR_IDR_8 (0x00000100U) \r
+#define GPIO_IDR_IDR_9 (0x00000200U) \r
+#define GPIO_IDR_IDR_10 (0x00000400U) \r
+#define GPIO_IDR_IDR_11 (0x00000800U) \r
+#define GPIO_IDR_IDR_12 (0x00001000U) \r
+#define GPIO_IDR_IDR_13 (0x00002000U) \r
+#define GPIO_IDR_IDR_14 (0x00004000U) \r
+#define GPIO_IDR_IDR_15 (0x00008000U) \r
+\r
+/****************** Bits definition for GPIO_ODR register *******************/\r
+#define GPIO_ODR_ODR_0 (0x00000001U) \r
+#define GPIO_ODR_ODR_1 (0x00000002U) \r
+#define GPIO_ODR_ODR_2 (0x00000004U) \r
+#define GPIO_ODR_ODR_3 (0x00000008U) \r
+#define GPIO_ODR_ODR_4 (0x00000010U) \r
+#define GPIO_ODR_ODR_5 (0x00000020U) \r
+#define GPIO_ODR_ODR_6 (0x00000040U) \r
+#define GPIO_ODR_ODR_7 (0x00000080U) \r
+#define GPIO_ODR_ODR_8 (0x00000100U) \r
+#define GPIO_ODR_ODR_9 (0x00000200U) \r
+#define GPIO_ODR_ODR_10 (0x00000400U) \r
+#define GPIO_ODR_ODR_11 (0x00000800U) \r
+#define GPIO_ODR_ODR_12 (0x00001000U) \r
+#define GPIO_ODR_ODR_13 (0x00002000U) \r
+#define GPIO_ODR_ODR_14 (0x00004000U) \r
+#define GPIO_ODR_ODR_15 (0x00008000U) \r
+\r
+/****************** Bits definition for GPIO_BSRR register ******************/\r
+#define GPIO_BSRR_BS_0 (0x00000001U) \r
+#define GPIO_BSRR_BS_1 (0x00000002U) \r
+#define GPIO_BSRR_BS_2 (0x00000004U) \r
+#define GPIO_BSRR_BS_3 (0x00000008U) \r
+#define GPIO_BSRR_BS_4 (0x00000010U) \r
+#define GPIO_BSRR_BS_5 (0x00000020U) \r
+#define GPIO_BSRR_BS_6 (0x00000040U) \r
+#define GPIO_BSRR_BS_7 (0x00000080U) \r
+#define GPIO_BSRR_BS_8 (0x00000100U) \r
+#define GPIO_BSRR_BS_9 (0x00000200U) \r
+#define GPIO_BSRR_BS_10 (0x00000400U) \r
+#define GPIO_BSRR_BS_11 (0x00000800U) \r
+#define GPIO_BSRR_BS_12 (0x00001000U) \r
+#define GPIO_BSRR_BS_13 (0x00002000U) \r
+#define GPIO_BSRR_BS_14 (0x00004000U) \r
+#define GPIO_BSRR_BS_15 (0x00008000U) \r
+#define GPIO_BSRR_BR_0 (0x00010000U) \r
+#define GPIO_BSRR_BR_1 (0x00020000U) \r
+#define GPIO_BSRR_BR_2 (0x00040000U) \r
+#define GPIO_BSRR_BR_3 (0x00080000U) \r
+#define GPIO_BSRR_BR_4 (0x00100000U) \r
+#define GPIO_BSRR_BR_5 (0x00200000U) \r
+#define GPIO_BSRR_BR_6 (0x00400000U) \r
+#define GPIO_BSRR_BR_7 (0x00800000U) \r
+#define GPIO_BSRR_BR_8 (0x01000000U) \r
+#define GPIO_BSRR_BR_9 (0x02000000U) \r
+#define GPIO_BSRR_BR_10 (0x04000000U) \r
+#define GPIO_BSRR_BR_11 (0x08000000U) \r
+#define GPIO_BSRR_BR_12 (0x10000000U) \r
+#define GPIO_BSRR_BR_13 (0x20000000U) \r
+#define GPIO_BSRR_BR_14 (0x40000000U) \r
+#define GPIO_BSRR_BR_15 (0x80000000U) \r
+\r
+/****************** Bit definition for GPIO_LCKR register ********************/\r
+#define GPIO_LCKR_LCK0_Pos (0U) \r
+#define GPIO_LCKR_LCK0_Msk (0x1UL << GPIO_LCKR_LCK0_Pos) /*!< 0x00000001 */\r
+#define GPIO_LCKR_LCK0 GPIO_LCKR_LCK0_Msk \r
+#define GPIO_LCKR_LCK1_Pos (1U) \r
+#define GPIO_LCKR_LCK1_Msk (0x1UL << GPIO_LCKR_LCK1_Pos) /*!< 0x00000002 */\r
+#define GPIO_LCKR_LCK1 GPIO_LCKR_LCK1_Msk \r
+#define GPIO_LCKR_LCK2_Pos (2U) \r
+#define GPIO_LCKR_LCK2_Msk (0x1UL << GPIO_LCKR_LCK2_Pos) /*!< 0x00000004 */\r
+#define GPIO_LCKR_LCK2 GPIO_LCKR_LCK2_Msk \r
+#define GPIO_LCKR_LCK3_Pos (3U) \r
+#define GPIO_LCKR_LCK3_Msk (0x1UL << GPIO_LCKR_LCK3_Pos) /*!< 0x00000008 */\r
+#define GPIO_LCKR_LCK3 GPIO_LCKR_LCK3_Msk \r
+#define GPIO_LCKR_LCK4_Pos (4U) \r
+#define GPIO_LCKR_LCK4_Msk (0x1UL << GPIO_LCKR_LCK4_Pos) /*!< 0x00000010 */\r
+#define GPIO_LCKR_LCK4 GPIO_LCKR_LCK4_Msk \r
+#define GPIO_LCKR_LCK5_Pos (5U) \r
+#define GPIO_LCKR_LCK5_Msk (0x1UL << GPIO_LCKR_LCK5_Pos) /*!< 0x00000020 */\r
+#define GPIO_LCKR_LCK5 GPIO_LCKR_LCK5_Msk \r
+#define GPIO_LCKR_LCK6_Pos (6U) \r
+#define GPIO_LCKR_LCK6_Msk (0x1UL << GPIO_LCKR_LCK6_Pos) /*!< 0x00000040 */\r
+#define GPIO_LCKR_LCK6 GPIO_LCKR_LCK6_Msk \r
+#define GPIO_LCKR_LCK7_Pos (7U) \r
+#define GPIO_LCKR_LCK7_Msk (0x1UL << GPIO_LCKR_LCK7_Pos) /*!< 0x00000080 */\r
+#define GPIO_LCKR_LCK7 GPIO_LCKR_LCK7_Msk \r
+#define GPIO_LCKR_LCK8_Pos (8U) \r
+#define GPIO_LCKR_LCK8_Msk (0x1UL << GPIO_LCKR_LCK8_Pos) /*!< 0x00000100 */\r
+#define GPIO_LCKR_LCK8 GPIO_LCKR_LCK8_Msk \r
+#define GPIO_LCKR_LCK9_Pos (9U) \r
+#define GPIO_LCKR_LCK9_Msk (0x1UL << GPIO_LCKR_LCK9_Pos) /*!< 0x00000200 */\r
+#define GPIO_LCKR_LCK9 GPIO_LCKR_LCK9_Msk \r
+#define GPIO_LCKR_LCK10_Pos (10U) \r
+#define GPIO_LCKR_LCK10_Msk (0x1UL << GPIO_LCKR_LCK10_Pos) /*!< 0x00000400 */\r
+#define GPIO_LCKR_LCK10 GPIO_LCKR_LCK10_Msk \r
+#define GPIO_LCKR_LCK11_Pos (11U) \r
+#define GPIO_LCKR_LCK11_Msk (0x1UL << GPIO_LCKR_LCK11_Pos) /*!< 0x00000800 */\r
+#define GPIO_LCKR_LCK11 GPIO_LCKR_LCK11_Msk \r
+#define GPIO_LCKR_LCK12_Pos (12U) \r
+#define GPIO_LCKR_LCK12_Msk (0x1UL << GPIO_LCKR_LCK12_Pos) /*!< 0x00001000 */\r
+#define GPIO_LCKR_LCK12 GPIO_LCKR_LCK12_Msk \r
+#define GPIO_LCKR_LCK13_Pos (13U) \r
+#define GPIO_LCKR_LCK13_Msk (0x1UL << GPIO_LCKR_LCK13_Pos) /*!< 0x00002000 */\r
+#define GPIO_LCKR_LCK13 GPIO_LCKR_LCK13_Msk \r
+#define GPIO_LCKR_LCK14_Pos (14U) \r
+#define GPIO_LCKR_LCK14_Msk (0x1UL << GPIO_LCKR_LCK14_Pos) /*!< 0x00004000 */\r
+#define GPIO_LCKR_LCK14 GPIO_LCKR_LCK14_Msk \r
+#define GPIO_LCKR_LCK15_Pos (15U) \r
+#define GPIO_LCKR_LCK15_Msk (0x1UL << GPIO_LCKR_LCK15_Pos) /*!< 0x00008000 */\r
+#define GPIO_LCKR_LCK15 GPIO_LCKR_LCK15_Msk \r
+#define GPIO_LCKR_LCKK_Pos (16U) \r
+#define GPIO_LCKR_LCKK_Msk (0x1UL << GPIO_LCKR_LCKK_Pos) /*!< 0x00010000 */\r
+#define GPIO_LCKR_LCKK GPIO_LCKR_LCKK_Msk \r
+\r
+/****************** Bit definition for GPIO_AFRL register ********************/\r
+#define GPIO_AFRL_AFSEL0_Pos (0U) \r
+#define GPIO_AFRL_AFSEL0_Msk (0xFUL << GPIO_AFRL_AFSEL0_Pos) /*!< 0x0000000F */\r
+#define GPIO_AFRL_AFSEL0 GPIO_AFRL_AFSEL0_Msk \r
+#define GPIO_AFRL_AFSEL1_Pos (4U) \r
+#define GPIO_AFRL_AFSEL1_Msk (0xFUL << GPIO_AFRL_AFSEL1_Pos) /*!< 0x000000F0 */\r
+#define GPIO_AFRL_AFSEL1 GPIO_AFRL_AFSEL1_Msk \r
+#define GPIO_AFRL_AFSEL2_Pos (8U) \r
+#define GPIO_AFRL_AFSEL2_Msk (0xFUL << GPIO_AFRL_AFSEL2_Pos) /*!< 0x00000F00 */\r
+#define GPIO_AFRL_AFSEL2 GPIO_AFRL_AFSEL2_Msk \r
+#define GPIO_AFRL_AFSEL3_Pos (12U) \r
+#define GPIO_AFRL_AFSEL3_Msk (0xFUL << GPIO_AFRL_AFSEL3_Pos) /*!< 0x0000F000 */\r
+#define GPIO_AFRL_AFSEL3 GPIO_AFRL_AFSEL3_Msk \r
+#define GPIO_AFRL_AFSEL4_Pos (16U) \r
+#define GPIO_AFRL_AFSEL4_Msk (0xFUL << GPIO_AFRL_AFSEL4_Pos) /*!< 0x000F0000 */\r
+#define GPIO_AFRL_AFSEL4 GPIO_AFRL_AFSEL4_Msk \r
+#define GPIO_AFRL_AFSEL5_Pos (20U) \r
+#define GPIO_AFRL_AFSEL5_Msk (0xFUL << GPIO_AFRL_AFSEL5_Pos) /*!< 0x00F00000 */\r
+#define GPIO_AFRL_AFSEL5 GPIO_AFRL_AFSEL5_Msk \r
+#define GPIO_AFRL_AFSEL6_Pos (24U) \r
+#define GPIO_AFRL_AFSEL6_Msk (0xFUL << GPIO_AFRL_AFSEL6_Pos) /*!< 0x0F000000 */\r
+#define GPIO_AFRL_AFSEL6 GPIO_AFRL_AFSEL6_Msk \r
+#define GPIO_AFRL_AFSEL7_Pos (28U) \r
+#define GPIO_AFRL_AFSEL7_Msk (0xFUL << GPIO_AFRL_AFSEL7_Pos) /*!< 0xF0000000 */\r
+#define GPIO_AFRL_AFSEL7 GPIO_AFRL_AFSEL7_Msk \r
+\r
+/****************** Bit definition for GPIO_AFRH register ********************/\r
+#define GPIO_AFRH_AFSEL8_Pos (0U) \r
+#define GPIO_AFRH_AFSEL8_Msk (0xFUL << GPIO_AFRH_AFSEL8_Pos) /*!< 0x0000000F */\r
+#define GPIO_AFRH_AFSEL8 GPIO_AFRH_AFSEL8_Msk \r
+#define GPIO_AFRH_AFSEL9_Pos (4U) \r
+#define GPIO_AFRH_AFSEL9_Msk (0xFUL << GPIO_AFRH_AFSEL9_Pos) /*!< 0x000000F0 */\r
+#define GPIO_AFRH_AFSEL9 GPIO_AFRH_AFSEL9_Msk \r
+#define GPIO_AFRH_AFSEL10_Pos (8U) \r
+#define GPIO_AFRH_AFSEL10_Msk (0xFUL << GPIO_AFRH_AFSEL10_Pos) /*!< 0x00000F00 */\r
+#define GPIO_AFRH_AFSEL10 GPIO_AFRH_AFSEL10_Msk \r
+#define GPIO_AFRH_AFSEL11_Pos (12U) \r
+#define GPIO_AFRH_AFSEL11_Msk (0xFUL << GPIO_AFRH_AFSEL11_Pos) /*!< 0x0000F000 */\r
+#define GPIO_AFRH_AFSEL11 GPIO_AFRH_AFSEL11_Msk \r
+#define GPIO_AFRH_AFSEL12_Pos (16U) \r
+#define GPIO_AFRH_AFSEL12_Msk (0xFUL << GPIO_AFRH_AFSEL12_Pos) /*!< 0x000F0000 */\r
+#define GPIO_AFRH_AFSEL12 GPIO_AFRH_AFSEL12_Msk \r
+#define GPIO_AFRH_AFSEL13_Pos (20U) \r
+#define GPIO_AFRH_AFSEL13_Msk (0xFUL << GPIO_AFRH_AFSEL13_Pos) /*!< 0x00F00000 */\r
+#define GPIO_AFRH_AFSEL13 GPIO_AFRH_AFSEL13_Msk \r
+#define GPIO_AFRH_AFSEL14_Pos (24U) \r
+#define GPIO_AFRH_AFSEL14_Msk (0xFUL << GPIO_AFRH_AFSEL14_Pos) /*!< 0x0F000000 */\r
+#define GPIO_AFRH_AFSEL14 GPIO_AFRH_AFSEL14_Msk \r
+#define GPIO_AFRH_AFSEL15_Pos (28U) \r
+#define GPIO_AFRH_AFSEL15_Msk (0xFUL << GPIO_AFRH_AFSEL15_Pos) /*!< 0xF0000000 */\r
+#define GPIO_AFRH_AFSEL15 GPIO_AFRH_AFSEL15_Msk \r
+\r
+/****************** Bit definition for GPIO_BRR register *********************/\r
+#define GPIO_BRR_BR_0 (0x00000001U) \r
+#define GPIO_BRR_BR_1 (0x00000002U) \r
+#define GPIO_BRR_BR_2 (0x00000004U) \r
+#define GPIO_BRR_BR_3 (0x00000008U) \r
+#define GPIO_BRR_BR_4 (0x00000010U) \r
+#define GPIO_BRR_BR_5 (0x00000020U) \r
+#define GPIO_BRR_BR_6 (0x00000040U) \r
+#define GPIO_BRR_BR_7 (0x00000080U) \r
+#define GPIO_BRR_BR_8 (0x00000100U) \r
+#define GPIO_BRR_BR_9 (0x00000200U) \r
+#define GPIO_BRR_BR_10 (0x00000400U) \r
+#define GPIO_BRR_BR_11 (0x00000800U) \r
+#define GPIO_BRR_BR_12 (0x00001000U) \r
+#define GPIO_BRR_BR_13 (0x00002000U) \r
+#define GPIO_BRR_BR_14 (0x00004000U) \r
+#define GPIO_BRR_BR_15 (0x00008000U) \r
+\r
+/******************************************************************************/\r
+/* */\r
+/* Inter-integrated Circuit Interface (I2C) */\r
+/* */\r
+/******************************************************************************/\r
+\r
+/******************* Bit definition for I2C_CR1 register ********************/\r
+#define I2C_CR1_PE_Pos (0U) \r
+#define I2C_CR1_PE_Msk (0x1UL << I2C_CR1_PE_Pos) /*!< 0x00000001 */\r
+#define I2C_CR1_PE I2C_CR1_PE_Msk /*!< Peripheral Enable */\r
+#define I2C_CR1_SMBUS_Pos (1U) \r
+#define I2C_CR1_SMBUS_Msk (0x1UL << I2C_CR1_SMBUS_Pos) /*!< 0x00000002 */\r
+#define I2C_CR1_SMBUS I2C_CR1_SMBUS_Msk /*!< SMBus Mode */\r
+#define I2C_CR1_SMBTYPE_Pos (3U) \r
+#define I2C_CR1_SMBTYPE_Msk (0x1UL << I2C_CR1_SMBTYPE_Pos) /*!< 0x00000008 */\r
+#define I2C_CR1_SMBTYPE I2C_CR1_SMBTYPE_Msk /*!< SMBus Type */\r
+#define I2C_CR1_ENARP_Pos (4U) \r
+#define I2C_CR1_ENARP_Msk (0x1UL << I2C_CR1_ENARP_Pos) /*!< 0x00000010 */\r
+#define I2C_CR1_ENARP I2C_CR1_ENARP_Msk /*!< ARP Enable */\r
+#define I2C_CR1_ENPEC_Pos (5U) \r
+#define I2C_CR1_ENPEC_Msk (0x1UL << I2C_CR1_ENPEC_Pos) /*!< 0x00000020 */\r
+#define I2C_CR1_ENPEC I2C_CR1_ENPEC_Msk /*!< PEC Enable */\r
+#define I2C_CR1_ENGC_Pos (6U) \r
+#define I2C_CR1_ENGC_Msk (0x1UL << I2C_CR1_ENGC_Pos) /*!< 0x00000040 */\r
+#define I2C_CR1_ENGC I2C_CR1_ENGC_Msk /*!< General Call Enable */\r
+#define I2C_CR1_NOSTRETCH_Pos (7U) \r
+#define I2C_CR1_NOSTRETCH_Msk (0x1UL << I2C_CR1_NOSTRETCH_Pos) /*!< 0x00000080 */\r
+#define I2C_CR1_NOSTRETCH I2C_CR1_NOSTRETCH_Msk /*!< Clock Stretching Disable (Slave mode) */\r
+#define I2C_CR1_START_Pos (8U) \r
+#define I2C_CR1_START_Msk (0x1UL << I2C_CR1_START_Pos) /*!< 0x00000100 */\r
+#define I2C_CR1_START I2C_CR1_START_Msk /*!< Start Generation */\r
+#define I2C_CR1_STOP_Pos (9U) \r
+#define I2C_CR1_STOP_Msk (0x1UL << I2C_CR1_STOP_Pos) /*!< 0x00000200 */\r
+#define I2C_CR1_STOP I2C_CR1_STOP_Msk /*!< Stop Generation */\r
+#define I2C_CR1_ACK_Pos (10U) \r
+#define I2C_CR1_ACK_Msk (0x1UL << I2C_CR1_ACK_Pos) /*!< 0x00000400 */\r
+#define I2C_CR1_ACK I2C_CR1_ACK_Msk /*!< Acknowledge Enable */\r
+#define I2C_CR1_POS_Pos (11U) \r
+#define I2C_CR1_POS_Msk (0x1UL << I2C_CR1_POS_Pos) /*!< 0x00000800 */\r
+#define I2C_CR1_POS I2C_CR1_POS_Msk /*!< Acknowledge/PEC Position (for data reception) */\r
+#define I2C_CR1_PEC_Pos (12U) \r
+#define I2C_CR1_PEC_Msk (0x1UL << I2C_CR1_PEC_Pos) /*!< 0x00001000 */\r
+#define I2C_CR1_PEC I2C_CR1_PEC_Msk /*!< Packet Error Checking */\r
+#define I2C_CR1_ALERT_Pos (13U) \r
+#define I2C_CR1_ALERT_Msk (0x1UL << I2C_CR1_ALERT_Pos) /*!< 0x00002000 */\r
+#define I2C_CR1_ALERT I2C_CR1_ALERT_Msk /*!< SMBus Alert */\r
+#define I2C_CR1_SWRST_Pos (15U) \r
+#define I2C_CR1_SWRST_Msk (0x1UL << I2C_CR1_SWRST_Pos) /*!< 0x00008000 */\r
+#define I2C_CR1_SWRST I2C_CR1_SWRST_Msk /*!< Software Reset */\r
+\r
+/******************* Bit definition for I2C_CR2 register ********************/\r
+#define I2C_CR2_FREQ_Pos (0U) \r
+#define I2C_CR2_FREQ_Msk (0x3FUL << I2C_CR2_FREQ_Pos) /*!< 0x0000003F */\r
+#define I2C_CR2_FREQ I2C_CR2_FREQ_Msk /*!< FREQ[5:0] bits (Peripheral Clock Frequency) */\r
+#define I2C_CR2_FREQ_0 (0x01UL << I2C_CR2_FREQ_Pos) /*!< 0x00000001 */\r
+#define I2C_CR2_FREQ_1 (0x02UL << I2C_CR2_FREQ_Pos) /*!< 0x00000002 */\r
+#define I2C_CR2_FREQ_2 (0x04UL << I2C_CR2_FREQ_Pos) /*!< 0x00000004 */\r
+#define I2C_CR2_FREQ_3 (0x08UL << I2C_CR2_FREQ_Pos) /*!< 0x00000008 */\r
+#define I2C_CR2_FREQ_4 (0x10UL << I2C_CR2_FREQ_Pos) /*!< 0x00000010 */\r
+#define I2C_CR2_FREQ_5 (0x20UL << I2C_CR2_FREQ_Pos) /*!< 0x00000020 */\r
+\r
+#define I2C_CR2_ITERREN_Pos (8U) \r
+#define I2C_CR2_ITERREN_Msk (0x1UL << I2C_CR2_ITERREN_Pos) /*!< 0x00000100 */\r
+#define I2C_CR2_ITERREN I2C_CR2_ITERREN_Msk /*!< Error Interrupt Enable */\r
+#define I2C_CR2_ITEVTEN_Pos (9U) \r
+#define I2C_CR2_ITEVTEN_Msk (0x1UL << I2C_CR2_ITEVTEN_Pos) /*!< 0x00000200 */\r
+#define I2C_CR2_ITEVTEN I2C_CR2_ITEVTEN_Msk /*!< Event Interrupt Enable */\r
+#define I2C_CR2_ITBUFEN_Pos (10U) \r
+#define I2C_CR2_ITBUFEN_Msk (0x1UL << I2C_CR2_ITBUFEN_Pos) /*!< 0x00000400 */\r
+#define I2C_CR2_ITBUFEN I2C_CR2_ITBUFEN_Msk /*!< Buffer Interrupt Enable */\r
+#define I2C_CR2_DMAEN_Pos (11U) \r
+#define I2C_CR2_DMAEN_Msk (0x1UL << I2C_CR2_DMAEN_Pos) /*!< 0x00000800 */\r
+#define I2C_CR2_DMAEN I2C_CR2_DMAEN_Msk /*!< DMA Requests Enable */\r
+#define I2C_CR2_LAST_Pos (12U) \r
+#define I2C_CR2_LAST_Msk (0x1UL << I2C_CR2_LAST_Pos) /*!< 0x00001000 */\r
+#define I2C_CR2_LAST I2C_CR2_LAST_Msk /*!< DMA Last Transfer */\r
+\r
+/******************* Bit definition for I2C_OAR1 register *******************/\r
+#define I2C_OAR1_ADD1_7 (0x000000FEU) /*!< Interface Address */\r
+#define I2C_OAR1_ADD8_9 (0x00000300U) /*!< Interface Address */\r
+\r
+#define I2C_OAR1_ADD0_Pos (0U) \r
+#define I2C_OAR1_ADD0_Msk (0x1UL << I2C_OAR1_ADD0_Pos) /*!< 0x00000001 */\r
+#define I2C_OAR1_ADD0 I2C_OAR1_ADD0_Msk /*!< Bit 0 */\r
+#define I2C_OAR1_ADD1_Pos (1U) \r
+#define I2C_OAR1_ADD1_Msk (0x1UL << I2C_OAR1_ADD1_Pos) /*!< 0x00000002 */\r
+#define I2C_OAR1_ADD1 I2C_OAR1_ADD1_Msk /*!< Bit 1 */\r
+#define I2C_OAR1_ADD2_Pos (2U) \r
+#define I2C_OAR1_ADD2_Msk (0x1UL << I2C_OAR1_ADD2_Pos) /*!< 0x00000004 */\r
+#define I2C_OAR1_ADD2 I2C_OAR1_ADD2_Msk /*!< Bit 2 */\r
+#define I2C_OAR1_ADD3_Pos (3U) \r
+#define I2C_OAR1_ADD3_Msk (0x1UL << I2C_OAR1_ADD3_Pos) /*!< 0x00000008 */\r
+#define I2C_OAR1_ADD3 I2C_OAR1_ADD3_Msk /*!< Bit 3 */\r
+#define I2C_OAR1_ADD4_Pos (4U) \r
+#define I2C_OAR1_ADD4_Msk (0x1UL << I2C_OAR1_ADD4_Pos) /*!< 0x00000010 */\r
+#define I2C_OAR1_ADD4 I2C_OAR1_ADD4_Msk /*!< Bit 4 */\r
+#define I2C_OAR1_ADD5_Pos (5U) \r
+#define I2C_OAR1_ADD5_Msk (0x1UL << I2C_OAR1_ADD5_Pos) /*!< 0x00000020 */\r
+#define I2C_OAR1_ADD5 I2C_OAR1_ADD5_Msk /*!< Bit 5 */\r
+#define I2C_OAR1_ADD6_Pos (6U) \r
+#define I2C_OAR1_ADD6_Msk (0x1UL << I2C_OAR1_ADD6_Pos) /*!< 0x00000040 */\r
+#define I2C_OAR1_ADD6 I2C_OAR1_ADD6_Msk /*!< Bit 6 */\r
+#define I2C_OAR1_ADD7_Pos (7U) \r
+#define I2C_OAR1_ADD7_Msk (0x1UL << I2C_OAR1_ADD7_Pos) /*!< 0x00000080 */\r
+#define I2C_OAR1_ADD7 I2C_OAR1_ADD7_Msk /*!< Bit 7 */\r
+#define I2C_OAR1_ADD8_Pos (8U) \r
+#define I2C_OAR1_ADD8_Msk (0x1UL << I2C_OAR1_ADD8_Pos) /*!< 0x00000100 */\r
+#define I2C_OAR1_ADD8 I2C_OAR1_ADD8_Msk /*!< Bit 8 */\r
+#define I2C_OAR1_ADD9_Pos (9U) \r
+#define I2C_OAR1_ADD9_Msk (0x1UL << I2C_OAR1_ADD9_Pos) /*!< 0x00000200 */\r
+#define I2C_OAR1_ADD9 I2C_OAR1_ADD9_Msk /*!< Bit 9 */\r
+\r
+#define I2C_OAR1_ADDMODE_Pos (15U) \r
+#define I2C_OAR1_ADDMODE_Msk (0x1UL << I2C_OAR1_ADDMODE_Pos) /*!< 0x00008000 */\r
+#define I2C_OAR1_ADDMODE I2C_OAR1_ADDMODE_Msk /*!< Addressing Mode (Slave mode) */\r
+\r
+/******************* Bit definition for I2C_OAR2 register *******************/\r
+#define I2C_OAR2_ENDUAL_Pos (0U) \r
+#define I2C_OAR2_ENDUAL_Msk (0x1UL << I2C_OAR2_ENDUAL_Pos) /*!< 0x00000001 */\r
+#define I2C_OAR2_ENDUAL I2C_OAR2_ENDUAL_Msk /*!< Dual addressing mode enable */\r
+#define I2C_OAR2_ADD2_Pos (1U) \r
+#define I2C_OAR2_ADD2_Msk (0x7FUL << I2C_OAR2_ADD2_Pos) /*!< 0x000000FE */\r
+#define I2C_OAR2_ADD2 I2C_OAR2_ADD2_Msk /*!< Interface address */\r
+\r
+/******************** Bit definition for I2C_DR register ********************/\r
+#define I2C_DR_DR_Pos (0U) \r
+#define I2C_DR_DR_Msk (0xFFUL << I2C_DR_DR_Pos) /*!< 0x000000FF */\r
+#define I2C_DR_DR I2C_DR_DR_Msk /*!< 8-bit Data Register */\r
+\r
+/******************* Bit definition for I2C_SR1 register ********************/\r
+#define I2C_SR1_SB_Pos (0U) \r
+#define I2C_SR1_SB_Msk (0x1UL << I2C_SR1_SB_Pos) /*!< 0x00000001 */\r
+#define I2C_SR1_SB I2C_SR1_SB_Msk /*!< Start Bit (Master mode) */\r
+#define I2C_SR1_ADDR_Pos (1U) \r
+#define I2C_SR1_ADDR_Msk (0x1UL << I2C_SR1_ADDR_Pos) /*!< 0x00000002 */\r
+#define I2C_SR1_ADDR I2C_SR1_ADDR_Msk /*!< Address sent (master mode)/matched (slave mode) */\r
+#define I2C_SR1_BTF_Pos (2U) \r
+#define I2C_SR1_BTF_Msk (0x1UL << I2C_SR1_BTF_Pos) /*!< 0x00000004 */\r
+#define I2C_SR1_BTF I2C_SR1_BTF_Msk /*!< Byte Transfer Finished */\r
+#define I2C_SR1_ADD10_Pos (3U) \r
+#define I2C_SR1_ADD10_Msk (0x1UL << I2C_SR1_ADD10_Pos) /*!< 0x00000008 */\r
+#define I2C_SR1_ADD10 I2C_SR1_ADD10_Msk /*!< 10-bit header sent (Master mode) */\r
+#define I2C_SR1_STOPF_Pos (4U) \r
+#define I2C_SR1_STOPF_Msk (0x1UL << I2C_SR1_STOPF_Pos) /*!< 0x00000010 */\r
+#define I2C_SR1_STOPF I2C_SR1_STOPF_Msk /*!< Stop detection (Slave mode) */\r
+#define I2C_SR1_RXNE_Pos (6U) \r
+#define I2C_SR1_RXNE_Msk (0x1UL << I2C_SR1_RXNE_Pos) /*!< 0x00000040 */\r
+#define I2C_SR1_RXNE I2C_SR1_RXNE_Msk /*!< Data Register not Empty (receivers) */\r
+#define I2C_SR1_TXE_Pos (7U) \r
+#define I2C_SR1_TXE_Msk (0x1UL << I2C_SR1_TXE_Pos) /*!< 0x00000080 */\r
+#define I2C_SR1_TXE I2C_SR1_TXE_Msk /*!< Data Register Empty (transmitters) */\r
+#define I2C_SR1_BERR_Pos (8U) \r
+#define I2C_SR1_BERR_Msk (0x1UL << I2C_SR1_BERR_Pos) /*!< 0x00000100 */\r
+#define I2C_SR1_BERR I2C_SR1_BERR_Msk /*!< Bus Error */\r
+#define I2C_SR1_ARLO_Pos (9U) \r
+#define I2C_SR1_ARLO_Msk (0x1UL << I2C_SR1_ARLO_Pos) /*!< 0x00000200 */\r
+#define I2C_SR1_ARLO I2C_SR1_ARLO_Msk /*!< Arbitration Lost (master mode) */\r
+#define I2C_SR1_AF_Pos (10U) \r
+#define I2C_SR1_AF_Msk (0x1UL << I2C_SR1_AF_Pos) /*!< 0x00000400 */\r
+#define I2C_SR1_AF I2C_SR1_AF_Msk /*!< Acknowledge Failure */\r
+#define I2C_SR1_OVR_Pos (11U) \r
+#define I2C_SR1_OVR_Msk (0x1UL << I2C_SR1_OVR_Pos) /*!< 0x00000800 */\r
+#define I2C_SR1_OVR I2C_SR1_OVR_Msk /*!< Overrun/Underrun */\r
+#define I2C_SR1_PECERR_Pos (12U) \r
+#define I2C_SR1_PECERR_Msk (0x1UL << I2C_SR1_PECERR_Pos) /*!< 0x00001000 */\r
+#define I2C_SR1_PECERR I2C_SR1_PECERR_Msk /*!< PEC Error in reception */\r
+#define I2C_SR1_TIMEOUT_Pos (14U) \r
+#define I2C_SR1_TIMEOUT_Msk (0x1UL << I2C_SR1_TIMEOUT_Pos) /*!< 0x00004000 */\r
+#define I2C_SR1_TIMEOUT I2C_SR1_TIMEOUT_Msk /*!< Timeout or Tlow Error */\r
+#define I2C_SR1_SMBALERT_Pos (15U) \r
+#define I2C_SR1_SMBALERT_Msk (0x1UL << I2C_SR1_SMBALERT_Pos) /*!< 0x00008000 */\r
+#define I2C_SR1_SMBALERT I2C_SR1_SMBALERT_Msk /*!< SMBus Alert */\r
+\r
+/******************* Bit definition for I2C_SR2 register ********************/\r
+#define I2C_SR2_MSL_Pos (0U) \r
+#define I2C_SR2_MSL_Msk (0x1UL << I2C_SR2_MSL_Pos) /*!< 0x00000001 */\r
+#define I2C_SR2_MSL I2C_SR2_MSL_Msk /*!< Master/Slave */\r
+#define I2C_SR2_BUSY_Pos (1U) \r
+#define I2C_SR2_BUSY_Msk (0x1UL << I2C_SR2_BUSY_Pos) /*!< 0x00000002 */\r
+#define I2C_SR2_BUSY I2C_SR2_BUSY_Msk /*!< Bus Busy */\r
+#define I2C_SR2_TRA_Pos (2U) \r
+#define I2C_SR2_TRA_Msk (0x1UL << I2C_SR2_TRA_Pos) /*!< 0x00000004 */\r
+#define I2C_SR2_TRA I2C_SR2_TRA_Msk /*!< Transmitter/Receiver */\r
+#define I2C_SR2_GENCALL_Pos (4U) \r
+#define I2C_SR2_GENCALL_Msk (0x1UL << I2C_SR2_GENCALL_Pos) /*!< 0x00000010 */\r
+#define I2C_SR2_GENCALL I2C_SR2_GENCALL_Msk /*!< General Call Address (Slave mode) */\r
+#define I2C_SR2_SMBDEFAULT_Pos (5U) \r
+#define I2C_SR2_SMBDEFAULT_Msk (0x1UL << I2C_SR2_SMBDEFAULT_Pos) /*!< 0x00000020 */\r
+#define I2C_SR2_SMBDEFAULT I2C_SR2_SMBDEFAULT_Msk /*!< SMBus Device Default Address (Slave mode) */\r
+#define I2C_SR2_SMBHOST_Pos (6U) \r
+#define I2C_SR2_SMBHOST_Msk (0x1UL << I2C_SR2_SMBHOST_Pos) /*!< 0x00000040 */\r
+#define I2C_SR2_SMBHOST I2C_SR2_SMBHOST_Msk /*!< SMBus Host Header (Slave mode) */\r
+#define I2C_SR2_DUALF_Pos (7U) \r
+#define I2C_SR2_DUALF_Msk (0x1UL << I2C_SR2_DUALF_Pos) /*!< 0x00000080 */\r
+#define I2C_SR2_DUALF I2C_SR2_DUALF_Msk /*!< Dual Flag (Slave mode) */\r
+#define I2C_SR2_PEC_Pos (8U) \r
+#define I2C_SR2_PEC_Msk (0xFFUL << I2C_SR2_PEC_Pos) /*!< 0x0000FF00 */\r
+#define I2C_SR2_PEC I2C_SR2_PEC_Msk /*!< Packet Error Checking Register */\r
+\r
+/******************* Bit definition for I2C_CCR register ********************/\r
+#define I2C_CCR_CCR_Pos (0U) \r
+#define I2C_CCR_CCR_Msk (0xFFFUL << I2C_CCR_CCR_Pos) /*!< 0x00000FFF */\r
+#define I2C_CCR_CCR I2C_CCR_CCR_Msk /*!< Clock Control Register in Fast/Standard mode (Master mode) */\r
+#define I2C_CCR_DUTY_Pos (14U) \r
+#define I2C_CCR_DUTY_Msk (0x1UL << I2C_CCR_DUTY_Pos) /*!< 0x00004000 */\r
+#define I2C_CCR_DUTY I2C_CCR_DUTY_Msk /*!< Fast Mode Duty Cycle */\r
+#define I2C_CCR_FS_Pos (15U) \r
+#define I2C_CCR_FS_Msk (0x1UL << I2C_CCR_FS_Pos) /*!< 0x00008000 */\r
+#define I2C_CCR_FS I2C_CCR_FS_Msk /*!< I2C Master Mode Selection */\r
+\r
+/****************** Bit definition for I2C_TRISE register *******************/\r
+#define I2C_TRISE_TRISE_Pos (0U) \r
+#define I2C_TRISE_TRISE_Msk (0x3FUL << I2C_TRISE_TRISE_Pos) /*!< 0x0000003F */\r
+#define I2C_TRISE_TRISE I2C_TRISE_TRISE_Msk /*!< Maximum Rise Time in Fast/Standard mode (Master mode) */\r
+\r
+/******************************************************************************/\r
+/* */\r
+/* Independent WATCHDOG (IWDG) */\r
+/* */\r
+/******************************************************************************/\r
+\r
+/******************* Bit definition for IWDG_KR register ********************/\r
+#define IWDG_KR_KEY_Pos (0U) \r
+#define IWDG_KR_KEY_Msk (0xFFFFUL << IWDG_KR_KEY_Pos) /*!< 0x0000FFFF */\r
+#define IWDG_KR_KEY IWDG_KR_KEY_Msk /*!< Key value (write only, read 0000h) */\r
+\r
+/******************* Bit definition for IWDG_PR register ********************/\r
+#define IWDG_PR_PR_Pos (0U) \r
+#define IWDG_PR_PR_Msk (0x7UL << IWDG_PR_PR_Pos) /*!< 0x00000007 */\r
+#define IWDG_PR_PR IWDG_PR_PR_Msk /*!< PR[2:0] (Prescaler divider) */\r
+#define IWDG_PR_PR_0 (0x1UL << IWDG_PR_PR_Pos) /*!< 0x00000001 */\r
+#define IWDG_PR_PR_1 (0x2UL << IWDG_PR_PR_Pos) /*!< 0x00000002 */\r
+#define IWDG_PR_PR_2 (0x4UL << IWDG_PR_PR_Pos) /*!< 0x00000004 */\r
+\r
+/******************* Bit definition for IWDG_RLR register *******************/\r
+#define IWDG_RLR_RL_Pos (0U) \r
+#define IWDG_RLR_RL_Msk (0xFFFUL << IWDG_RLR_RL_Pos) /*!< 0x00000FFF */\r
+#define IWDG_RLR_RL IWDG_RLR_RL_Msk /*!< Watchdog counter reload value */\r
+\r
+/******************* Bit definition for IWDG_SR register ********************/\r
+#define IWDG_SR_PVU_Pos (0U) \r
+#define IWDG_SR_PVU_Msk (0x1UL << IWDG_SR_PVU_Pos) /*!< 0x00000001 */\r
+#define IWDG_SR_PVU IWDG_SR_PVU_Msk /*!< Watchdog prescaler value update */\r
+#define IWDG_SR_RVU_Pos (1U) \r
+#define IWDG_SR_RVU_Msk (0x1UL << IWDG_SR_RVU_Pos) /*!< 0x00000002 */\r
+#define IWDG_SR_RVU IWDG_SR_RVU_Msk /*!< Watchdog counter reload value update */\r
+\r
+/******************************************************************************/\r
+/* */\r
+/* LCD Controller (LCD) */\r
+/* */\r
+/******************************************************************************/\r
+\r
+/******************* Bit definition for LCD_CR register *********************/\r
+#define LCD_CR_LCDEN_Pos (0U) \r
+#define LCD_CR_LCDEN_Msk (0x1UL << LCD_CR_LCDEN_Pos) /*!< 0x00000001 */\r
+#define LCD_CR_LCDEN LCD_CR_LCDEN_Msk /*!< LCD Enable Bit */\r
+#define LCD_CR_VSEL_Pos (1U) \r
+#define LCD_CR_VSEL_Msk (0x1UL << LCD_CR_VSEL_Pos) /*!< 0x00000002 */\r
+#define LCD_CR_VSEL LCD_CR_VSEL_Msk /*!< Voltage source selector Bit */\r
+\r
+#define LCD_CR_DUTY_Pos (2U) \r
+#define LCD_CR_DUTY_Msk (0x7UL << LCD_CR_DUTY_Pos) /*!< 0x0000001C */\r
+#define LCD_CR_DUTY LCD_CR_DUTY_Msk /*!< DUTY[2:0] bits (Duty selector) */\r
+#define LCD_CR_DUTY_0 (0x1UL << LCD_CR_DUTY_Pos) /*!< 0x00000004 */\r
+#define LCD_CR_DUTY_1 (0x2UL << LCD_CR_DUTY_Pos) /*!< 0x00000008 */\r
+#define LCD_CR_DUTY_2 (0x4UL << LCD_CR_DUTY_Pos) /*!< 0x00000010 */\r
+\r
+#define LCD_CR_BIAS_Pos (5U) \r
+#define LCD_CR_BIAS_Msk (0x3UL << LCD_CR_BIAS_Pos) /*!< 0x00000060 */\r
+#define LCD_CR_BIAS LCD_CR_BIAS_Msk /*!< BIAS[1:0] bits (Bias selector) */\r
+#define LCD_CR_BIAS_0 (0x1UL << LCD_CR_BIAS_Pos) /*!< 0x00000020 */\r
+#define LCD_CR_BIAS_1 (0x2UL << LCD_CR_BIAS_Pos) /*!< 0x00000040 */\r
+\r
+#define LCD_CR_MUX_SEG_Pos (7U) \r
+#define LCD_CR_MUX_SEG_Msk (0x1UL << LCD_CR_MUX_SEG_Pos) /*!< 0x00000080 */\r
+#define LCD_CR_MUX_SEG LCD_CR_MUX_SEG_Msk /*!< Mux Segment Enable Bit */\r
+\r
+/******************* Bit definition for LCD_FCR register ********************/\r
+#define LCD_FCR_HD_Pos (0U) \r
+#define LCD_FCR_HD_Msk (0x1UL << LCD_FCR_HD_Pos) /*!< 0x00000001 */\r
+#define LCD_FCR_HD LCD_FCR_HD_Msk /*!< High Drive Enable Bit */\r
+#define LCD_FCR_SOFIE_Pos (1U) \r
+#define LCD_FCR_SOFIE_Msk (0x1UL << LCD_FCR_SOFIE_Pos) /*!< 0x00000002 */\r
+#define LCD_FCR_SOFIE LCD_FCR_SOFIE_Msk /*!< Start of Frame Interrupt Enable Bit */\r
+#define LCD_FCR_UDDIE_Pos (3U) \r
+#define LCD_FCR_UDDIE_Msk (0x1UL << LCD_FCR_UDDIE_Pos) /*!< 0x00000008 */\r
+#define LCD_FCR_UDDIE LCD_FCR_UDDIE_Msk /*!< Update Display Done Interrupt Enable Bit */\r
+\r
+#define LCD_FCR_PON_Pos (4U) \r
+#define LCD_FCR_PON_Msk (0x7UL << LCD_FCR_PON_Pos) /*!< 0x00000070 */\r
+#define LCD_FCR_PON LCD_FCR_PON_Msk /*!< PON[2:0] bits (Puls ON Duration) */\r
+#define LCD_FCR_PON_0 (0x1UL << LCD_FCR_PON_Pos) /*!< 0x00000010 */\r
+#define LCD_FCR_PON_1 (0x2UL << LCD_FCR_PON_Pos) /*!< 0x00000020 */\r
+#define LCD_FCR_PON_2 (0x4UL << LCD_FCR_PON_Pos) /*!< 0x00000040 */\r
+\r
+#define LCD_FCR_DEAD_Pos (7U) \r
+#define LCD_FCR_DEAD_Msk (0x7UL << LCD_FCR_DEAD_Pos) /*!< 0x00000380 */\r
+#define LCD_FCR_DEAD LCD_FCR_DEAD_Msk /*!< DEAD[2:0] bits (DEAD Time) */\r
+#define LCD_FCR_DEAD_0 (0x1UL << LCD_FCR_DEAD_Pos) /*!< 0x00000080 */\r
+#define LCD_FCR_DEAD_1 (0x2UL << LCD_FCR_DEAD_Pos) /*!< 0x00000100 */\r
+#define LCD_FCR_DEAD_2 (0x4UL << LCD_FCR_DEAD_Pos) /*!< 0x00000200 */\r
+\r
+#define LCD_FCR_CC_Pos (10U) \r
+#define LCD_FCR_CC_Msk (0x7UL << LCD_FCR_CC_Pos) /*!< 0x00001C00 */\r
+#define LCD_FCR_CC LCD_FCR_CC_Msk /*!< CC[2:0] bits (Contrast Control) */\r
+#define LCD_FCR_CC_0 (0x1UL << LCD_FCR_CC_Pos) /*!< 0x00000400 */\r
+#define LCD_FCR_CC_1 (0x2UL << LCD_FCR_CC_Pos) /*!< 0x00000800 */\r
+#define LCD_FCR_CC_2 (0x4UL << LCD_FCR_CC_Pos) /*!< 0x00001000 */\r
+\r
+#define LCD_FCR_BLINKF_Pos (13U) \r
+#define LCD_FCR_BLINKF_Msk (0x7UL << LCD_FCR_BLINKF_Pos) /*!< 0x0000E000 */\r
+#define LCD_FCR_BLINKF LCD_FCR_BLINKF_Msk /*!< BLINKF[2:0] bits (Blink Frequency) */\r
+#define LCD_FCR_BLINKF_0 (0x1UL << LCD_FCR_BLINKF_Pos) /*!< 0x00002000 */\r
+#define LCD_FCR_BLINKF_1 (0x2UL << LCD_FCR_BLINKF_Pos) /*!< 0x00004000 */\r
+#define LCD_FCR_BLINKF_2 (0x4UL << LCD_FCR_BLINKF_Pos) /*!< 0x00008000 */\r
+\r
+#define LCD_FCR_BLINK_Pos (16U) \r
+#define LCD_FCR_BLINK_Msk (0x3UL << LCD_FCR_BLINK_Pos) /*!< 0x00030000 */\r
+#define LCD_FCR_BLINK LCD_FCR_BLINK_Msk /*!< BLINK[1:0] bits (Blink Enable) */\r
+#define LCD_FCR_BLINK_0 (0x1UL << LCD_FCR_BLINK_Pos) /*!< 0x00010000 */\r
+#define LCD_FCR_BLINK_1 (0x2UL << LCD_FCR_BLINK_Pos) /*!< 0x00020000 */\r
+\r
+#define LCD_FCR_DIV_Pos (18U) \r
+#define LCD_FCR_DIV_Msk (0xFUL << LCD_FCR_DIV_Pos) /*!< 0x003C0000 */\r
+#define LCD_FCR_DIV LCD_FCR_DIV_Msk /*!< DIV[3:0] bits (Divider) */\r
+#define LCD_FCR_PS_Pos (22U) \r
+#define LCD_FCR_PS_Msk (0xFUL << LCD_FCR_PS_Pos) /*!< 0x03C00000 */\r
+#define LCD_FCR_PS LCD_FCR_PS_Msk /*!< PS[3:0] bits (Prescaler) */\r
+\r
+/******************* Bit definition for LCD_SR register *********************/\r
+#define LCD_SR_ENS_Pos (0U) \r
+#define LCD_SR_ENS_Msk (0x1UL << LCD_SR_ENS_Pos) /*!< 0x00000001 */\r
+#define LCD_SR_ENS LCD_SR_ENS_Msk /*!< LCD Enabled Bit */\r
+#define LCD_SR_SOF_Pos (1U) \r
+#define LCD_SR_SOF_Msk (0x1UL << LCD_SR_SOF_Pos) /*!< 0x00000002 */\r
+#define LCD_SR_SOF LCD_SR_SOF_Msk /*!< Start Of Frame Flag Bit */\r
+#define LCD_SR_UDR_Pos (2U) \r
+#define LCD_SR_UDR_Msk (0x1UL << LCD_SR_UDR_Pos) /*!< 0x00000004 */\r
+#define LCD_SR_UDR LCD_SR_UDR_Msk /*!< Update Display Request Bit */\r
+#define LCD_SR_UDD_Pos (3U) \r
+#define LCD_SR_UDD_Msk (0x1UL << LCD_SR_UDD_Pos) /*!< 0x00000008 */\r
+#define LCD_SR_UDD LCD_SR_UDD_Msk /*!< Update Display Done Flag Bit */\r
+#define LCD_SR_RDY_Pos (4U) \r
+#define LCD_SR_RDY_Msk (0x1UL << LCD_SR_RDY_Pos) /*!< 0x00000010 */\r
+#define LCD_SR_RDY LCD_SR_RDY_Msk /*!< Ready Flag Bit */\r
+#define LCD_SR_FCRSR_Pos (5U) \r
+#define LCD_SR_FCRSR_Msk (0x1UL << LCD_SR_FCRSR_Pos) /*!< 0x00000020 */\r
+#define LCD_SR_FCRSR LCD_SR_FCRSR_Msk /*!< LCD FCR Register Synchronization Flag Bit */\r
+\r
+/******************* Bit definition for LCD_CLR register ********************/\r
+#define LCD_CLR_SOFC_Pos (1U) \r
+#define LCD_CLR_SOFC_Msk (0x1UL << LCD_CLR_SOFC_Pos) /*!< 0x00000002 */\r
+#define LCD_CLR_SOFC LCD_CLR_SOFC_Msk /*!< Start Of Frame Flag Clear Bit */\r
+#define LCD_CLR_UDDC_Pos (3U) \r
+#define LCD_CLR_UDDC_Msk (0x1UL << LCD_CLR_UDDC_Pos) /*!< 0x00000008 */\r
+#define LCD_CLR_UDDC LCD_CLR_UDDC_Msk /*!< Update Display Done Flag Clear Bit */\r
+\r
+/******************* Bit definition for LCD_RAM register ********************/\r
+#define LCD_RAM_SEGMENT_DATA_Pos (0U) \r
+#define LCD_RAM_SEGMENT_DATA_Msk (0xFFFFFFFFUL << LCD_RAM_SEGMENT_DATA_Pos) /*!< 0xFFFFFFFF */\r
+#define LCD_RAM_SEGMENT_DATA LCD_RAM_SEGMENT_DATA_Msk /*!< Segment Data Bits */\r
+\r
+/******************************************************************************/\r
+/* */\r
+/* Power Control (PWR) */\r
+/* */\r
+/******************************************************************************/\r
+\r
+#define PWR_PVD_SUPPORT /*!< PWR feature available only on specific devices: Power Voltage Detection feature */\r
+\r
+/******************** Bit definition for PWR_CR register ********************/\r
+#define PWR_CR_LPSDSR_Pos (0U) \r
+#define PWR_CR_LPSDSR_Msk (0x1UL << PWR_CR_LPSDSR_Pos) /*!< 0x00000001 */\r
+#define PWR_CR_LPSDSR PWR_CR_LPSDSR_Msk /*!< Low-power deepsleep/sleep/low power run */\r
+#define PWR_CR_PDDS_Pos (1U) \r
+#define PWR_CR_PDDS_Msk (0x1UL << PWR_CR_PDDS_Pos) /*!< 0x00000002 */\r
+#define PWR_CR_PDDS PWR_CR_PDDS_Msk /*!< Power Down Deepsleep */\r
+#define PWR_CR_CWUF_Pos (2U) \r
+#define PWR_CR_CWUF_Msk (0x1UL << PWR_CR_CWUF_Pos) /*!< 0x00000004 */\r
+#define PWR_CR_CWUF PWR_CR_CWUF_Msk /*!< Clear Wakeup Flag */\r
+#define PWR_CR_CSBF_Pos (3U) \r
+#define PWR_CR_CSBF_Msk (0x1UL << PWR_CR_CSBF_Pos) /*!< 0x00000008 */\r
+#define PWR_CR_CSBF PWR_CR_CSBF_Msk /*!< Clear Standby Flag */\r
+#define PWR_CR_PVDE_Pos (4U) \r
+#define PWR_CR_PVDE_Msk (0x1UL << PWR_CR_PVDE_Pos) /*!< 0x00000010 */\r
+#define PWR_CR_PVDE PWR_CR_PVDE_Msk /*!< Power Voltage Detector Enable */\r
+\r
+#define PWR_CR_PLS_Pos (5U) \r
+#define PWR_CR_PLS_Msk (0x7UL << PWR_CR_PLS_Pos) /*!< 0x000000E0 */\r
+#define PWR_CR_PLS PWR_CR_PLS_Msk /*!< PLS[2:0] bits (PVD Level Selection) */\r
+#define PWR_CR_PLS_0 (0x1UL << PWR_CR_PLS_Pos) /*!< 0x00000020 */\r
+#define PWR_CR_PLS_1 (0x2UL << PWR_CR_PLS_Pos) /*!< 0x00000040 */\r
+#define PWR_CR_PLS_2 (0x4UL << PWR_CR_PLS_Pos) /*!< 0x00000080 */\r
+\r
+/*!< PVD level configuration */\r
+#define PWR_CR_PLS_LEV0 (0x00000000U) /*!< PVD level 0 */\r
+#define PWR_CR_PLS_LEV1 (0x00000020U) /*!< PVD level 1 */\r
+#define PWR_CR_PLS_LEV2 (0x00000040U) /*!< PVD level 2 */\r
+#define PWR_CR_PLS_LEV3 (0x00000060U) /*!< PVD level 3 */\r
+#define PWR_CR_PLS_LEV4 (0x00000080U) /*!< PVD level 4 */\r
+#define PWR_CR_PLS_LEV5 (0x000000A0U) /*!< PVD level 5 */\r
+#define PWR_CR_PLS_LEV6 (0x000000C0U) /*!< PVD level 6 */\r
+#define PWR_CR_PLS_LEV7 (0x000000E0U) /*!< PVD level 7 */\r
+\r
+#define PWR_CR_DBP_Pos (8U) \r
+#define PWR_CR_DBP_Msk (0x1UL << PWR_CR_DBP_Pos) /*!< 0x00000100 */\r
+#define PWR_CR_DBP PWR_CR_DBP_Msk /*!< Disable Backup Domain write protection */\r
+#define PWR_CR_ULP_Pos (9U) \r
+#define PWR_CR_ULP_Msk (0x1UL << PWR_CR_ULP_Pos) /*!< 0x00000200 */\r
+#define PWR_CR_ULP PWR_CR_ULP_Msk /*!< Ultra Low Power mode */\r
+#define PWR_CR_FWU_Pos (10U) \r
+#define PWR_CR_FWU_Msk (0x1UL << PWR_CR_FWU_Pos) /*!< 0x00000400 */\r
+#define PWR_CR_FWU PWR_CR_FWU_Msk /*!< Fast wakeup */\r
+\r
+#define PWR_CR_VOS_Pos (11U) \r
+#define PWR_CR_VOS_Msk (0x3UL << PWR_CR_VOS_Pos) /*!< 0x00001800 */\r
+#define PWR_CR_VOS PWR_CR_VOS_Msk /*!< VOS[1:0] bits (Voltage scaling range selection) */\r
+#define PWR_CR_VOS_0 (0x1UL << PWR_CR_VOS_Pos) /*!< 0x00000800 */\r
+#define PWR_CR_VOS_1 (0x2UL << PWR_CR_VOS_Pos) /*!< 0x00001000 */\r
+#define PWR_CR_LPRUN_Pos (14U) \r
+#define PWR_CR_LPRUN_Msk (0x1UL << PWR_CR_LPRUN_Pos) /*!< 0x00004000 */\r
+#define PWR_CR_LPRUN PWR_CR_LPRUN_Msk /*!< Low power run mode */\r
+\r
+/******************* Bit definition for PWR_CSR register ********************/\r
+#define PWR_CSR_WUF_Pos (0U) \r
+#define PWR_CSR_WUF_Msk (0x1UL << PWR_CSR_WUF_Pos) /*!< 0x00000001 */\r
+#define PWR_CSR_WUF PWR_CSR_WUF_Msk /*!< Wakeup Flag */\r
+#define PWR_CSR_SBF_Pos (1U) \r
+#define PWR_CSR_SBF_Msk (0x1UL << PWR_CSR_SBF_Pos) /*!< 0x00000002 */\r
+#define PWR_CSR_SBF PWR_CSR_SBF_Msk /*!< Standby Flag */\r
+#define PWR_CSR_PVDO_Pos (2U) \r
+#define PWR_CSR_PVDO_Msk (0x1UL << PWR_CSR_PVDO_Pos) /*!< 0x00000004 */\r
+#define PWR_CSR_PVDO PWR_CSR_PVDO_Msk /*!< PVD Output */\r
+#define PWR_CSR_VREFINTRDYF_Pos (3U) \r
+#define PWR_CSR_VREFINTRDYF_Msk (0x1UL << PWR_CSR_VREFINTRDYF_Pos) /*!< 0x00000008 */\r
+#define PWR_CSR_VREFINTRDYF PWR_CSR_VREFINTRDYF_Msk /*!< Internal voltage reference (VREFINT) ready flag */\r
+#define PWR_CSR_VOSF_Pos (4U) \r
+#define PWR_CSR_VOSF_Msk (0x1UL << PWR_CSR_VOSF_Pos) /*!< 0x00000010 */\r
+#define PWR_CSR_VOSF PWR_CSR_VOSF_Msk /*!< Voltage Scaling select flag */\r
+#define PWR_CSR_REGLPF_Pos (5U) \r
+#define PWR_CSR_REGLPF_Msk (0x1UL << PWR_CSR_REGLPF_Pos) /*!< 0x00000020 */\r
+#define PWR_CSR_REGLPF PWR_CSR_REGLPF_Msk /*!< Regulator LP flag */\r
+\r
+#define PWR_CSR_EWUP1_Pos (8U) \r
+#define PWR_CSR_EWUP1_Msk (0x1UL << PWR_CSR_EWUP1_Pos) /*!< 0x00000100 */\r
+#define PWR_CSR_EWUP1 PWR_CSR_EWUP1_Msk /*!< Enable WKUP pin 1 */\r
+#define PWR_CSR_EWUP2_Pos (9U) \r
+#define PWR_CSR_EWUP2_Msk (0x1UL << PWR_CSR_EWUP2_Pos) /*!< 0x00000200 */\r
+#define PWR_CSR_EWUP2 PWR_CSR_EWUP2_Msk /*!< Enable WKUP pin 2 */\r
+#define PWR_CSR_EWUP3_Pos (10U) \r
+#define PWR_CSR_EWUP3_Msk (0x1UL << PWR_CSR_EWUP3_Pos) /*!< 0x00000400 */\r
+#define PWR_CSR_EWUP3 PWR_CSR_EWUP3_Msk /*!< Enable WKUP pin 3 */\r
+\r
+/******************************************************************************/\r
+/* */\r
+/* Reset and Clock Control (RCC) */\r
+/* */\r
+/******************************************************************************/\r
+/*\r
+* @brief Specific device feature definitions (not present on all devices in the STM32F0 serie)\r
+*/\r
+#define RCC_LSECSS_SUPPORT /*!< LSE CSS feature support */\r
+\r
+/******************** Bit definition for RCC_CR register ********************/\r
+#define RCC_CR_HSION_Pos (0U) \r
+#define RCC_CR_HSION_Msk (0x1UL << RCC_CR_HSION_Pos) /*!< 0x00000001 */\r
+#define RCC_CR_HSION RCC_CR_HSION_Msk /*!< Internal High Speed clock enable */\r
+#define RCC_CR_HSIRDY_Pos (1U) \r
+#define RCC_CR_HSIRDY_Msk (0x1UL << RCC_CR_HSIRDY_Pos) /*!< 0x00000002 */\r
+#define RCC_CR_HSIRDY RCC_CR_HSIRDY_Msk /*!< Internal High Speed clock ready flag */\r
+\r
+#define RCC_CR_MSION_Pos (8U) \r
+#define RCC_CR_MSION_Msk (0x1UL << RCC_CR_MSION_Pos) /*!< 0x00000100 */\r
+#define RCC_CR_MSION RCC_CR_MSION_Msk /*!< Internal Multi Speed clock enable */\r
+#define RCC_CR_MSIRDY_Pos (9U) \r
+#define RCC_CR_MSIRDY_Msk (0x1UL << RCC_CR_MSIRDY_Pos) /*!< 0x00000200 */\r
+#define RCC_CR_MSIRDY RCC_CR_MSIRDY_Msk /*!< Internal Multi Speed clock ready flag */\r
+\r
+#define RCC_CR_HSEON_Pos (16U) \r
+#define RCC_CR_HSEON_Msk (0x1UL << RCC_CR_HSEON_Pos) /*!< 0x00010000 */\r
+#define RCC_CR_HSEON RCC_CR_HSEON_Msk /*!< External High Speed clock enable */\r
+#define RCC_CR_HSERDY_Pos (17U) \r
+#define RCC_CR_HSERDY_Msk (0x1UL << RCC_CR_HSERDY_Pos) /*!< 0x00020000 */\r
+#define RCC_CR_HSERDY RCC_CR_HSERDY_Msk /*!< External High Speed clock ready flag */\r
+#define RCC_CR_HSEBYP_Pos (18U) \r
+#define RCC_CR_HSEBYP_Msk (0x1UL << RCC_CR_HSEBYP_Pos) /*!< 0x00040000 */\r
+#define RCC_CR_HSEBYP RCC_CR_HSEBYP_Msk /*!< External High Speed clock Bypass */\r
+\r
+#define RCC_CR_PLLON_Pos (24U) \r
+#define RCC_CR_PLLON_Msk (0x1UL << RCC_CR_PLLON_Pos) /*!< 0x01000000 */\r
+#define RCC_CR_PLLON RCC_CR_PLLON_Msk /*!< PLL enable */\r
+#define RCC_CR_PLLRDY_Pos (25U) \r
+#define RCC_CR_PLLRDY_Msk (0x1UL << RCC_CR_PLLRDY_Pos) /*!< 0x02000000 */\r
+#define RCC_CR_PLLRDY RCC_CR_PLLRDY_Msk /*!< PLL clock ready flag */\r
+#define RCC_CR_CSSON_Pos (28U) \r
+#define RCC_CR_CSSON_Msk (0x1UL << RCC_CR_CSSON_Pos) /*!< 0x10000000 */\r
+#define RCC_CR_CSSON RCC_CR_CSSON_Msk /*!< Clock Security System enable */\r
+\r
+#define RCC_CR_RTCPRE_Pos (29U) \r
+#define RCC_CR_RTCPRE_Msk (0x3UL << RCC_CR_RTCPRE_Pos) /*!< 0x60000000 */\r
+#define RCC_CR_RTCPRE RCC_CR_RTCPRE_Msk /*!< RTC/LCD Prescaler */\r
+#define RCC_CR_RTCPRE_0 (0x20000000U) /*!< Bit0 */\r
+#define RCC_CR_RTCPRE_1 (0x40000000U) /*!< Bit1 */\r
+\r
+/******************** Bit definition for RCC_ICSCR register *****************/\r
+#define RCC_ICSCR_HSICAL_Pos (0U) \r
+#define RCC_ICSCR_HSICAL_Msk (0xFFUL << RCC_ICSCR_HSICAL_Pos) /*!< 0x000000FF */\r
+#define RCC_ICSCR_HSICAL RCC_ICSCR_HSICAL_Msk /*!< Internal High Speed clock Calibration */\r
+#define RCC_ICSCR_HSITRIM_Pos (8U) \r
+#define RCC_ICSCR_HSITRIM_Msk (0x1FUL << RCC_ICSCR_HSITRIM_Pos) /*!< 0x00001F00 */\r
+#define RCC_ICSCR_HSITRIM RCC_ICSCR_HSITRIM_Msk /*!< Internal High Speed clock trimming */\r
+\r
+#define RCC_ICSCR_MSIRANGE_Pos (13U) \r
+#define RCC_ICSCR_MSIRANGE_Msk (0x7UL << RCC_ICSCR_MSIRANGE_Pos) /*!< 0x0000E000 */\r
+#define RCC_ICSCR_MSIRANGE RCC_ICSCR_MSIRANGE_Msk /*!< Internal Multi Speed clock Range */\r
+#define RCC_ICSCR_MSIRANGE_0 (0x0UL << RCC_ICSCR_MSIRANGE_Pos) /*!< 0x00000000 */\r
+#define RCC_ICSCR_MSIRANGE_1 (0x1UL << RCC_ICSCR_MSIRANGE_Pos) /*!< 0x00002000 */\r
+#define RCC_ICSCR_MSIRANGE_2 (0x2UL << RCC_ICSCR_MSIRANGE_Pos) /*!< 0x00004000 */\r
+#define RCC_ICSCR_MSIRANGE_3 (0x3UL << RCC_ICSCR_MSIRANGE_Pos) /*!< 0x00006000 */\r
+#define RCC_ICSCR_MSIRANGE_4 (0x4UL << RCC_ICSCR_MSIRANGE_Pos) /*!< 0x00008000 */\r
+#define RCC_ICSCR_MSIRANGE_5 (0x5UL << RCC_ICSCR_MSIRANGE_Pos) /*!< 0x0000A000 */\r
+#define RCC_ICSCR_MSIRANGE_6 (0x6UL << RCC_ICSCR_MSIRANGE_Pos) /*!< 0x0000C000 */\r
+#define RCC_ICSCR_MSICAL_Pos (16U) \r
+#define RCC_ICSCR_MSICAL_Msk (0xFFUL << RCC_ICSCR_MSICAL_Pos) /*!< 0x00FF0000 */\r
+#define RCC_ICSCR_MSICAL RCC_ICSCR_MSICAL_Msk /*!< Internal Multi Speed clock Calibration */\r
+#define RCC_ICSCR_MSITRIM_Pos (24U) \r
+#define RCC_ICSCR_MSITRIM_Msk (0xFFUL << RCC_ICSCR_MSITRIM_Pos) /*!< 0xFF000000 */\r
+#define RCC_ICSCR_MSITRIM RCC_ICSCR_MSITRIM_Msk /*!< Internal Multi Speed clock trimming */\r
+\r
+/******************** Bit definition for RCC_CFGR register ******************/\r
+#define RCC_CFGR_SW_Pos (0U) \r
+#define RCC_CFGR_SW_Msk (0x3UL << RCC_CFGR_SW_Pos) /*!< 0x00000003 */\r
+#define RCC_CFGR_SW RCC_CFGR_SW_Msk /*!< SW[1:0] bits (System clock Switch) */\r
+#define RCC_CFGR_SW_0 (0x1UL << RCC_CFGR_SW_Pos) /*!< 0x00000001 */\r
+#define RCC_CFGR_SW_1 (0x2UL << RCC_CFGR_SW_Pos) /*!< 0x00000002 */\r
+\r
+/*!< SW configuration */\r
+#define RCC_CFGR_SW_MSI (0x00000000U) /*!< MSI selected as system clock */\r
+#define RCC_CFGR_SW_HSI (0x00000001U) /*!< HSI selected as system clock */\r
+#define RCC_CFGR_SW_HSE (0x00000002U) /*!< HSE selected as system clock */\r
+#define RCC_CFGR_SW_PLL (0x00000003U) /*!< PLL selected as system clock */\r
+\r
+#define RCC_CFGR_SWS_Pos (2U) \r
+#define RCC_CFGR_SWS_Msk (0x3UL << RCC_CFGR_SWS_Pos) /*!< 0x0000000C */\r
+#define RCC_CFGR_SWS RCC_CFGR_SWS_Msk /*!< SWS[1:0] bits (System Clock Switch Status) */\r
+#define RCC_CFGR_SWS_0 (0x1UL << RCC_CFGR_SWS_Pos) /*!< 0x00000004 */\r
+#define RCC_CFGR_SWS_1 (0x2UL << RCC_CFGR_SWS_Pos) /*!< 0x00000008 */\r
+\r
+/*!< SWS configuration */\r
+#define RCC_CFGR_SWS_MSI (0x00000000U) /*!< MSI oscillator used as system clock */\r
+#define RCC_CFGR_SWS_HSI (0x00000004U) /*!< HSI oscillator used as system clock */\r
+#define RCC_CFGR_SWS_HSE (0x00000008U) /*!< HSE oscillator used as system clock */\r
+#define RCC_CFGR_SWS_PLL (0x0000000CU) /*!< PLL used as system clock */\r
+\r
+#define RCC_CFGR_HPRE_Pos (4U) \r
+#define RCC_CFGR_HPRE_Msk (0xFUL << RCC_CFGR_HPRE_Pos) /*!< 0x000000F0 */\r
+#define RCC_CFGR_HPRE RCC_CFGR_HPRE_Msk /*!< HPRE[3:0] bits (AHB prescaler) */\r
+#define RCC_CFGR_HPRE_0 (0x1UL << RCC_CFGR_HPRE_Pos) /*!< 0x00000010 */\r
+#define RCC_CFGR_HPRE_1 (0x2UL << RCC_CFGR_HPRE_Pos) /*!< 0x00000020 */\r
+#define RCC_CFGR_HPRE_2 (0x4UL << RCC_CFGR_HPRE_Pos) /*!< 0x00000040 */\r
+#define RCC_CFGR_HPRE_3 (0x8UL << RCC_CFGR_HPRE_Pos) /*!< 0x00000080 */\r
+\r
+/*!< HPRE configuration */\r
+#define RCC_CFGR_HPRE_DIV1 (0x00000000U) /*!< SYSCLK not divided */\r
+#define RCC_CFGR_HPRE_DIV2 (0x00000080U) /*!< SYSCLK divided by 2 */\r
+#define RCC_CFGR_HPRE_DIV4 (0x00000090U) /*!< SYSCLK divided by 4 */\r
+#define RCC_CFGR_HPRE_DIV8 (0x000000A0U) /*!< SYSCLK divided by 8 */\r
+#define RCC_CFGR_HPRE_DIV16 (0x000000B0U) /*!< SYSCLK divided by 16 */\r
+#define RCC_CFGR_HPRE_DIV64 (0x000000C0U) /*!< SYSCLK divided by 64 */\r
+#define RCC_CFGR_HPRE_DIV128 (0x000000D0U) /*!< SYSCLK divided by 128 */\r
+#define RCC_CFGR_HPRE_DIV256 (0x000000E0U) /*!< SYSCLK divided by 256 */\r
+#define RCC_CFGR_HPRE_DIV512 (0x000000F0U) /*!< SYSCLK divided by 512 */\r
+\r
+#define RCC_CFGR_PPRE1_Pos (8U) \r
+#define RCC_CFGR_PPRE1_Msk (0x7UL << RCC_CFGR_PPRE1_Pos) /*!< 0x00000700 */\r
+#define RCC_CFGR_PPRE1 RCC_CFGR_PPRE1_Msk /*!< PRE1[2:0] bits (APB1 prescaler) */\r
+#define RCC_CFGR_PPRE1_0 (0x1UL << RCC_CFGR_PPRE1_Pos) /*!< 0x00000100 */\r
+#define RCC_CFGR_PPRE1_1 (0x2UL << RCC_CFGR_PPRE1_Pos) /*!< 0x00000200 */\r
+#define RCC_CFGR_PPRE1_2 (0x4UL << RCC_CFGR_PPRE1_Pos) /*!< 0x00000400 */\r
+\r
+/*!< PPRE1 configuration */\r
+#define RCC_CFGR_PPRE1_DIV1 (0x00000000U) /*!< HCLK not divided */\r
+#define RCC_CFGR_PPRE1_DIV2 (0x00000400U) /*!< HCLK divided by 2 */\r
+#define RCC_CFGR_PPRE1_DIV4 (0x00000500U) /*!< HCLK divided by 4 */\r
+#define RCC_CFGR_PPRE1_DIV8 (0x00000600U) /*!< HCLK divided by 8 */\r
+#define RCC_CFGR_PPRE1_DIV16 (0x00000700U) /*!< HCLK divided by 16 */\r
+\r
+#define RCC_CFGR_PPRE2_Pos (11U) \r
+#define RCC_CFGR_PPRE2_Msk (0x7UL << RCC_CFGR_PPRE2_Pos) /*!< 0x00003800 */\r
+#define RCC_CFGR_PPRE2 RCC_CFGR_PPRE2_Msk /*!< PRE2[2:0] bits (APB2 prescaler) */\r
+#define RCC_CFGR_PPRE2_0 (0x1UL << RCC_CFGR_PPRE2_Pos) /*!< 0x00000800 */\r
+#define RCC_CFGR_PPRE2_1 (0x2UL << RCC_CFGR_PPRE2_Pos) /*!< 0x00001000 */\r
+#define RCC_CFGR_PPRE2_2 (0x4UL << RCC_CFGR_PPRE2_Pos) /*!< 0x00002000 */\r
+\r
+/*!< PPRE2 configuration */\r
+#define RCC_CFGR_PPRE2_DIV1 (0x00000000U) /*!< HCLK not divided */\r
+#define RCC_CFGR_PPRE2_DIV2 (0x00002000U) /*!< HCLK divided by 2 */\r
+#define RCC_CFGR_PPRE2_DIV4 (0x00002800U) /*!< HCLK divided by 4 */\r
+#define RCC_CFGR_PPRE2_DIV8 (0x00003000U) /*!< HCLK divided by 8 */\r
+#define RCC_CFGR_PPRE2_DIV16 (0x00003800U) /*!< HCLK divided by 16 */\r
+\r
+/*!< PLL entry clock source*/\r
+#define RCC_CFGR_PLLSRC_Pos (16U) \r
+#define RCC_CFGR_PLLSRC_Msk (0x1UL << RCC_CFGR_PLLSRC_Pos) /*!< 0x00010000 */\r
+#define RCC_CFGR_PLLSRC RCC_CFGR_PLLSRC_Msk /*!< PLL entry clock source */\r
+\r
+#define RCC_CFGR_PLLSRC_HSI (0x00000000U) /*!< HSI as PLL entry clock source */\r
+#define RCC_CFGR_PLLSRC_HSE (0x00010000U) /*!< HSE as PLL entry clock source */\r
+\r
+\r
+/*!< PLLMUL configuration */\r
+#define RCC_CFGR_PLLMUL_Pos (18U) \r
+#define RCC_CFGR_PLLMUL_Msk (0xFUL << RCC_CFGR_PLLMUL_Pos) /*!< 0x003C0000 */\r
+#define RCC_CFGR_PLLMUL RCC_CFGR_PLLMUL_Msk /*!< PLLMUL[3:0] bits (PLL multiplication factor) */\r
+#define RCC_CFGR_PLLMUL_0 (0x1UL << RCC_CFGR_PLLMUL_Pos) /*!< 0x00040000 */\r
+#define RCC_CFGR_PLLMUL_1 (0x2UL << RCC_CFGR_PLLMUL_Pos) /*!< 0x00080000 */\r
+#define RCC_CFGR_PLLMUL_2 (0x4UL << RCC_CFGR_PLLMUL_Pos) /*!< 0x00100000 */\r
+#define RCC_CFGR_PLLMUL_3 (0x8UL << RCC_CFGR_PLLMUL_Pos) /*!< 0x00200000 */\r
+\r
+/*!< PLLMUL configuration */\r
+#define RCC_CFGR_PLLMUL3 (0x00000000U) /*!< PLL input clock * 3 */\r
+#define RCC_CFGR_PLLMUL4 (0x00040000U) /*!< PLL input clock * 4 */\r
+#define RCC_CFGR_PLLMUL6 (0x00080000U) /*!< PLL input clock * 6 */\r
+#define RCC_CFGR_PLLMUL8 (0x000C0000U) /*!< PLL input clock * 8 */\r
+#define RCC_CFGR_PLLMUL12 (0x00100000U) /*!< PLL input clock * 12 */\r
+#define RCC_CFGR_PLLMUL16 (0x00140000U) /*!< PLL input clock * 16 */\r
+#define RCC_CFGR_PLLMUL24 (0x00180000U) /*!< PLL input clock * 24 */\r
+#define RCC_CFGR_PLLMUL32 (0x001C0000U) /*!< PLL input clock * 32 */\r
+#define RCC_CFGR_PLLMUL48 (0x00200000U) /*!< PLL input clock * 48 */\r
+\r
+/*!< PLLDIV configuration */\r
+#define RCC_CFGR_PLLDIV_Pos (22U) \r
+#define RCC_CFGR_PLLDIV_Msk (0x3UL << RCC_CFGR_PLLDIV_Pos) /*!< 0x00C00000 */\r
+#define RCC_CFGR_PLLDIV RCC_CFGR_PLLDIV_Msk /*!< PLLDIV[1:0] bits (PLL Output Division) */\r
+#define RCC_CFGR_PLLDIV_0 (0x1UL << RCC_CFGR_PLLDIV_Pos) /*!< 0x00400000 */\r
+#define RCC_CFGR_PLLDIV_1 (0x2UL << RCC_CFGR_PLLDIV_Pos) /*!< 0x00800000 */\r
+\r
+\r
+/*!< PLLDIV configuration */\r
+#define RCC_CFGR_PLLDIV1 (0x00000000U) /*!< PLL clock output = CKVCO / 1 */\r
+#define RCC_CFGR_PLLDIV2_Pos (22U) \r
+#define RCC_CFGR_PLLDIV2_Msk (0x1UL << RCC_CFGR_PLLDIV2_Pos) /*!< 0x00400000 */\r
+#define RCC_CFGR_PLLDIV2 RCC_CFGR_PLLDIV2_Msk /*!< PLL clock output = CKVCO / 2 */\r
+#define RCC_CFGR_PLLDIV3_Pos (23U) \r
+#define RCC_CFGR_PLLDIV3_Msk (0x1UL << RCC_CFGR_PLLDIV3_Pos) /*!< 0x00800000 */\r
+#define RCC_CFGR_PLLDIV3 RCC_CFGR_PLLDIV3_Msk /*!< PLL clock output = CKVCO / 3 */\r
+#define RCC_CFGR_PLLDIV4_Pos (22U) \r
+#define RCC_CFGR_PLLDIV4_Msk (0x3UL << RCC_CFGR_PLLDIV4_Pos) /*!< 0x00C00000 */\r
+#define RCC_CFGR_PLLDIV4 RCC_CFGR_PLLDIV4_Msk /*!< PLL clock output = CKVCO / 4 */\r
+\r
+\r
+#define RCC_CFGR_MCOSEL_Pos (24U) \r
+#define RCC_CFGR_MCOSEL_Msk (0x7UL << RCC_CFGR_MCOSEL_Pos) /*!< 0x07000000 */\r
+#define RCC_CFGR_MCOSEL RCC_CFGR_MCOSEL_Msk /*!< MCO[2:0] bits (Microcontroller Clock Output) */\r
+#define RCC_CFGR_MCOSEL_0 (0x1UL << RCC_CFGR_MCOSEL_Pos) /*!< 0x01000000 */\r
+#define RCC_CFGR_MCOSEL_1 (0x2UL << RCC_CFGR_MCOSEL_Pos) /*!< 0x02000000 */\r
+#define RCC_CFGR_MCOSEL_2 (0x4UL << RCC_CFGR_MCOSEL_Pos) /*!< 0x04000000 */\r
+\r
+/*!< MCO configuration */\r
+#define RCC_CFGR_MCOSEL_NOCLOCK (0x00000000U) /*!< No clock */\r
+#define RCC_CFGR_MCOSEL_SYSCLK_Pos (24U) \r
+#define RCC_CFGR_MCOSEL_SYSCLK_Msk (0x1UL << RCC_CFGR_MCOSEL_SYSCLK_Pos) /*!< 0x01000000 */\r
+#define RCC_CFGR_MCOSEL_SYSCLK RCC_CFGR_MCOSEL_SYSCLK_Msk /*!< System clock selected */\r
+#define RCC_CFGR_MCOSEL_HSI_Pos (25U) \r
+#define RCC_CFGR_MCOSEL_HSI_Msk (0x1UL << RCC_CFGR_MCOSEL_HSI_Pos) /*!< 0x02000000 */\r
+#define RCC_CFGR_MCOSEL_HSI RCC_CFGR_MCOSEL_HSI_Msk /*!< Internal 16 MHz RC oscillator clock selected */\r
+#define RCC_CFGR_MCOSEL_MSI_Pos (24U) \r
+#define RCC_CFGR_MCOSEL_MSI_Msk (0x3UL << RCC_CFGR_MCOSEL_MSI_Pos) /*!< 0x03000000 */\r
+#define RCC_CFGR_MCOSEL_MSI RCC_CFGR_MCOSEL_MSI_Msk /*!< Internal Medium Speed RC oscillator clock selected */\r
+#define RCC_CFGR_MCOSEL_HSE_Pos (26U) \r
+#define RCC_CFGR_MCOSEL_HSE_Msk (0x1UL << RCC_CFGR_MCOSEL_HSE_Pos) /*!< 0x04000000 */\r
+#define RCC_CFGR_MCOSEL_HSE RCC_CFGR_MCOSEL_HSE_Msk /*!< External 1-25 MHz oscillator clock selected */\r
+#define RCC_CFGR_MCOSEL_PLL_Pos (24U) \r
+#define RCC_CFGR_MCOSEL_PLL_Msk (0x5UL << RCC_CFGR_MCOSEL_PLL_Pos) /*!< 0x05000000 */\r
+#define RCC_CFGR_MCOSEL_PLL RCC_CFGR_MCOSEL_PLL_Msk /*!< PLL clock divided */\r
+#define RCC_CFGR_MCOSEL_LSI_Pos (25U) \r
+#define RCC_CFGR_MCOSEL_LSI_Msk (0x3UL << RCC_CFGR_MCOSEL_LSI_Pos) /*!< 0x06000000 */\r
+#define RCC_CFGR_MCOSEL_LSI RCC_CFGR_MCOSEL_LSI_Msk /*!< LSI selected */\r
+#define RCC_CFGR_MCOSEL_LSE_Pos (24U) \r
+#define RCC_CFGR_MCOSEL_LSE_Msk (0x7UL << RCC_CFGR_MCOSEL_LSE_Pos) /*!< 0x07000000 */\r
+#define RCC_CFGR_MCOSEL_LSE RCC_CFGR_MCOSEL_LSE_Msk /*!< LSE selected */\r
+\r
+#define RCC_CFGR_MCOPRE_Pos (28U) \r
+#define RCC_CFGR_MCOPRE_Msk (0x7UL << RCC_CFGR_MCOPRE_Pos) /*!< 0x70000000 */\r
+#define RCC_CFGR_MCOPRE RCC_CFGR_MCOPRE_Msk /*!< MCOPRE[2:0] bits (Microcontroller Clock Output Prescaler) */\r
+#define RCC_CFGR_MCOPRE_0 (0x1UL << RCC_CFGR_MCOPRE_Pos) /*!< 0x10000000 */\r
+#define RCC_CFGR_MCOPRE_1 (0x2UL << RCC_CFGR_MCOPRE_Pos) /*!< 0x20000000 */\r
+#define RCC_CFGR_MCOPRE_2 (0x4UL << RCC_CFGR_MCOPRE_Pos) /*!< 0x40000000 */\r
+\r
+/*!< MCO Prescaler configuration */ \r
+#define RCC_CFGR_MCOPRE_DIV1 (0x00000000U) /*!< MCO is divided by 1 */\r
+#define RCC_CFGR_MCOPRE_DIV2 (0x10000000U) /*!< MCO is divided by 2 */\r
+#define RCC_CFGR_MCOPRE_DIV4 (0x20000000U) /*!< MCO is divided by 4 */\r
+#define RCC_CFGR_MCOPRE_DIV8 (0x30000000U) /*!< MCO is divided by 8 */\r
+#define RCC_CFGR_MCOPRE_DIV16 (0x40000000U) /*!< MCO is divided by 16 */\r
+ \r
+/* Legacy aliases */\r
+#define RCC_CFGR_MCO_DIV1 RCC_CFGR_MCOPRE_DIV1\r
+#define RCC_CFGR_MCO_DIV2 RCC_CFGR_MCOPRE_DIV2\r
+#define RCC_CFGR_MCO_DIV4 RCC_CFGR_MCOPRE_DIV4\r
+#define RCC_CFGR_MCO_DIV8 RCC_CFGR_MCOPRE_DIV8\r
+#define RCC_CFGR_MCO_DIV16 RCC_CFGR_MCOPRE_DIV16\r
+#define RCC_CFGR_MCO_NOCLOCK RCC_CFGR_MCOSEL_NOCLOCK\r
+#define RCC_CFGR_MCO_SYSCLK RCC_CFGR_MCOSEL_SYSCLK\r
+#define RCC_CFGR_MCO_HSI RCC_CFGR_MCOSEL_HSI\r
+#define RCC_CFGR_MCO_MSI RCC_CFGR_MCOSEL_MSI\r
+#define RCC_CFGR_MCO_HSE RCC_CFGR_MCOSEL_HSE\r
+#define RCC_CFGR_MCO_PLL RCC_CFGR_MCOSEL_PLL\r
+#define RCC_CFGR_MCO_LSI RCC_CFGR_MCOSEL_LSI\r
+#define RCC_CFGR_MCO_LSE RCC_CFGR_MCOSEL_LSE\r
+\r
+/*!<****************** Bit definition for RCC_CIR register ********************/\r
+#define RCC_CIR_LSIRDYF_Pos (0U) \r
+#define RCC_CIR_LSIRDYF_Msk (0x1UL << RCC_CIR_LSIRDYF_Pos) /*!< 0x00000001 */\r
+#define RCC_CIR_LSIRDYF RCC_CIR_LSIRDYF_Msk /*!< LSI Ready Interrupt flag */\r
+#define RCC_CIR_LSERDYF_Pos (1U) \r
+#define RCC_CIR_LSERDYF_Msk (0x1UL << RCC_CIR_LSERDYF_Pos) /*!< 0x00000002 */\r
+#define RCC_CIR_LSERDYF RCC_CIR_LSERDYF_Msk /*!< LSE Ready Interrupt flag */\r
+#define RCC_CIR_HSIRDYF_Pos (2U) \r
+#define RCC_CIR_HSIRDYF_Msk (0x1UL << RCC_CIR_HSIRDYF_Pos) /*!< 0x00000004 */\r
+#define RCC_CIR_HSIRDYF RCC_CIR_HSIRDYF_Msk /*!< HSI Ready Interrupt flag */\r
+#define RCC_CIR_HSERDYF_Pos (3U) \r
+#define RCC_CIR_HSERDYF_Msk (0x1UL << RCC_CIR_HSERDYF_Pos) /*!< 0x00000008 */\r
+#define RCC_CIR_HSERDYF RCC_CIR_HSERDYF_Msk /*!< HSE Ready Interrupt flag */\r
+#define RCC_CIR_PLLRDYF_Pos (4U) \r
+#define RCC_CIR_PLLRDYF_Msk (0x1UL << RCC_CIR_PLLRDYF_Pos) /*!< 0x00000010 */\r
+#define RCC_CIR_PLLRDYF RCC_CIR_PLLRDYF_Msk /*!< PLL Ready Interrupt flag */\r
+#define RCC_CIR_MSIRDYF_Pos (5U) \r
+#define RCC_CIR_MSIRDYF_Msk (0x1UL << RCC_CIR_MSIRDYF_Pos) /*!< 0x00000020 */\r
+#define RCC_CIR_MSIRDYF RCC_CIR_MSIRDYF_Msk /*!< MSI Ready Interrupt flag */\r
+#define RCC_CIR_LSECSSF_Pos (6U) \r
+#define RCC_CIR_LSECSSF_Msk (0x1UL << RCC_CIR_LSECSSF_Pos) /*!< 0x00000040 */\r
+#define RCC_CIR_LSECSSF RCC_CIR_LSECSSF_Msk /*!< LSE CSS Interrupt flag */\r
+#define RCC_CIR_CSSF_Pos (7U) \r
+#define RCC_CIR_CSSF_Msk (0x1UL << RCC_CIR_CSSF_Pos) /*!< 0x00000080 */\r
+#define RCC_CIR_CSSF RCC_CIR_CSSF_Msk /*!< Clock Security System Interrupt flag */\r
+\r
+#define RCC_CIR_LSIRDYIE_Pos (8U) \r
+#define RCC_CIR_LSIRDYIE_Msk (0x1UL << RCC_CIR_LSIRDYIE_Pos) /*!< 0x00000100 */\r
+#define RCC_CIR_LSIRDYIE RCC_CIR_LSIRDYIE_Msk /*!< LSI Ready Interrupt Enable */\r
+#define RCC_CIR_LSERDYIE_Pos (9U) \r
+#define RCC_CIR_LSERDYIE_Msk (0x1UL << RCC_CIR_LSERDYIE_Pos) /*!< 0x00000200 */\r
+#define RCC_CIR_LSERDYIE RCC_CIR_LSERDYIE_Msk /*!< LSE Ready Interrupt Enable */\r
+#define RCC_CIR_HSIRDYIE_Pos (10U) \r
+#define RCC_CIR_HSIRDYIE_Msk (0x1UL << RCC_CIR_HSIRDYIE_Pos) /*!< 0x00000400 */\r
+#define RCC_CIR_HSIRDYIE RCC_CIR_HSIRDYIE_Msk /*!< HSI Ready Interrupt Enable */\r
+#define RCC_CIR_HSERDYIE_Pos (11U) \r
+#define RCC_CIR_HSERDYIE_Msk (0x1UL << RCC_CIR_HSERDYIE_Pos) /*!< 0x00000800 */\r
+#define RCC_CIR_HSERDYIE RCC_CIR_HSERDYIE_Msk /*!< HSE Ready Interrupt Enable */\r
+#define RCC_CIR_PLLRDYIE_Pos (12U) \r
+#define RCC_CIR_PLLRDYIE_Msk (0x1UL << RCC_CIR_PLLRDYIE_Pos) /*!< 0x00001000 */\r
+#define RCC_CIR_PLLRDYIE RCC_CIR_PLLRDYIE_Msk /*!< PLL Ready Interrupt Enable */\r
+#define RCC_CIR_MSIRDYIE_Pos (13U) \r
+#define RCC_CIR_MSIRDYIE_Msk (0x1UL << RCC_CIR_MSIRDYIE_Pos) /*!< 0x00002000 */\r
+#define RCC_CIR_MSIRDYIE RCC_CIR_MSIRDYIE_Msk /*!< MSI Ready Interrupt Enable */\r
+#define RCC_CIR_LSECSSIE_Pos (14U) \r
+#define RCC_CIR_LSECSSIE_Msk (0x1UL << RCC_CIR_LSECSSIE_Pos) /*!< 0x00004000 */\r
+#define RCC_CIR_LSECSSIE RCC_CIR_LSECSSIE_Msk /*!< LSE CSS Interrupt Enable */\r
+\r
+#define RCC_CIR_LSIRDYC_Pos (16U) \r
+#define RCC_CIR_LSIRDYC_Msk (0x1UL << RCC_CIR_LSIRDYC_Pos) /*!< 0x00010000 */\r
+#define RCC_CIR_LSIRDYC RCC_CIR_LSIRDYC_Msk /*!< LSI Ready Interrupt Clear */\r
+#define RCC_CIR_LSERDYC_Pos (17U) \r
+#define RCC_CIR_LSERDYC_Msk (0x1UL << RCC_CIR_LSERDYC_Pos) /*!< 0x00020000 */\r
+#define RCC_CIR_LSERDYC RCC_CIR_LSERDYC_Msk /*!< LSE Ready Interrupt Clear */\r
+#define RCC_CIR_HSIRDYC_Pos (18U) \r
+#define RCC_CIR_HSIRDYC_Msk (0x1UL << RCC_CIR_HSIRDYC_Pos) /*!< 0x00040000 */\r
+#define RCC_CIR_HSIRDYC RCC_CIR_HSIRDYC_Msk /*!< HSI Ready Interrupt Clear */\r
+#define RCC_CIR_HSERDYC_Pos (19U) \r
+#define RCC_CIR_HSERDYC_Msk (0x1UL << RCC_CIR_HSERDYC_Pos) /*!< 0x00080000 */\r
+#define RCC_CIR_HSERDYC RCC_CIR_HSERDYC_Msk /*!< HSE Ready Interrupt Clear */\r
+#define RCC_CIR_PLLRDYC_Pos (20U) \r
+#define RCC_CIR_PLLRDYC_Msk (0x1UL << RCC_CIR_PLLRDYC_Pos) /*!< 0x00100000 */\r
+#define RCC_CIR_PLLRDYC RCC_CIR_PLLRDYC_Msk /*!< PLL Ready Interrupt Clear */\r
+#define RCC_CIR_MSIRDYC_Pos (21U) \r
+#define RCC_CIR_MSIRDYC_Msk (0x1UL << RCC_CIR_MSIRDYC_Pos) /*!< 0x00200000 */\r
+#define RCC_CIR_MSIRDYC RCC_CIR_MSIRDYC_Msk /*!< MSI Ready Interrupt Clear */\r
+#define RCC_CIR_LSECSSC_Pos (22U) \r
+#define RCC_CIR_LSECSSC_Msk (0x1UL << RCC_CIR_LSECSSC_Pos) /*!< 0x00400000 */\r
+#define RCC_CIR_LSECSSC RCC_CIR_LSECSSC_Msk /*!< LSE CSS Interrupt Clear */\r
+#define RCC_CIR_CSSC_Pos (23U) \r
+#define RCC_CIR_CSSC_Msk (0x1UL << RCC_CIR_CSSC_Pos) /*!< 0x00800000 */\r
+#define RCC_CIR_CSSC RCC_CIR_CSSC_Msk /*!< Clock Security System Interrupt Clear */\r
+\r
+/***************** Bit definition for RCC_AHBRSTR register ******************/\r
+#define RCC_AHBRSTR_GPIOARST_Pos (0U) \r
+#define RCC_AHBRSTR_GPIOARST_Msk (0x1UL << RCC_AHBRSTR_GPIOARST_Pos) /*!< 0x00000001 */\r
+#define RCC_AHBRSTR_GPIOARST RCC_AHBRSTR_GPIOARST_Msk /*!< GPIO port A reset */\r
+#define RCC_AHBRSTR_GPIOBRST_Pos (1U) \r
+#define RCC_AHBRSTR_GPIOBRST_Msk (0x1UL << RCC_AHBRSTR_GPIOBRST_Pos) /*!< 0x00000002 */\r
+#define RCC_AHBRSTR_GPIOBRST RCC_AHBRSTR_GPIOBRST_Msk /*!< GPIO port B reset */\r
+#define RCC_AHBRSTR_GPIOCRST_Pos (2U) \r
+#define RCC_AHBRSTR_GPIOCRST_Msk (0x1UL << RCC_AHBRSTR_GPIOCRST_Pos) /*!< 0x00000004 */\r
+#define RCC_AHBRSTR_GPIOCRST RCC_AHBRSTR_GPIOCRST_Msk /*!< GPIO port C reset */\r
+#define RCC_AHBRSTR_GPIODRST_Pos (3U) \r
+#define RCC_AHBRSTR_GPIODRST_Msk (0x1UL << RCC_AHBRSTR_GPIODRST_Pos) /*!< 0x00000008 */\r
+#define RCC_AHBRSTR_GPIODRST RCC_AHBRSTR_GPIODRST_Msk /*!< GPIO port D reset */\r
+#define RCC_AHBRSTR_GPIOERST_Pos (4U) \r
+#define RCC_AHBRSTR_GPIOERST_Msk (0x1UL << RCC_AHBRSTR_GPIOERST_Pos) /*!< 0x00000010 */\r
+#define RCC_AHBRSTR_GPIOERST RCC_AHBRSTR_GPIOERST_Msk /*!< GPIO port E reset */\r
+#define RCC_AHBRSTR_GPIOHRST_Pos (5U) \r
+#define RCC_AHBRSTR_GPIOHRST_Msk (0x1UL << RCC_AHBRSTR_GPIOHRST_Pos) /*!< 0x00000020 */\r
+#define RCC_AHBRSTR_GPIOHRST RCC_AHBRSTR_GPIOHRST_Msk /*!< GPIO port H reset */\r
+#define RCC_AHBRSTR_GPIOFRST_Pos (6U) \r
+#define RCC_AHBRSTR_GPIOFRST_Msk (0x1UL << RCC_AHBRSTR_GPIOFRST_Pos) /*!< 0x00000040 */\r
+#define RCC_AHBRSTR_GPIOFRST RCC_AHBRSTR_GPIOFRST_Msk /*!< GPIO port F reset */\r
+#define RCC_AHBRSTR_GPIOGRST_Pos (7U) \r
+#define RCC_AHBRSTR_GPIOGRST_Msk (0x1UL << RCC_AHBRSTR_GPIOGRST_Pos) /*!< 0x00000080 */\r
+#define RCC_AHBRSTR_GPIOGRST RCC_AHBRSTR_GPIOGRST_Msk /*!< GPIO port G reset */\r
+#define RCC_AHBRSTR_CRCRST_Pos (12U) \r
+#define RCC_AHBRSTR_CRCRST_Msk (0x1UL << RCC_AHBRSTR_CRCRST_Pos) /*!< 0x00001000 */\r
+#define RCC_AHBRSTR_CRCRST RCC_AHBRSTR_CRCRST_Msk /*!< CRC reset */\r
+#define RCC_AHBRSTR_FLITFRST_Pos (15U) \r
+#define RCC_AHBRSTR_FLITFRST_Msk (0x1UL << RCC_AHBRSTR_FLITFRST_Pos) /*!< 0x00008000 */\r
+#define RCC_AHBRSTR_FLITFRST RCC_AHBRSTR_FLITFRST_Msk /*!< FLITF reset */\r
+#define RCC_AHBRSTR_DMA1RST_Pos (24U) \r
+#define RCC_AHBRSTR_DMA1RST_Msk (0x1UL << RCC_AHBRSTR_DMA1RST_Pos) /*!< 0x01000000 */\r
+#define RCC_AHBRSTR_DMA1RST RCC_AHBRSTR_DMA1RST_Msk /*!< DMA1 reset */\r
+#define RCC_AHBRSTR_DMA2RST_Pos (25U) \r
+#define RCC_AHBRSTR_DMA2RST_Msk (0x1UL << RCC_AHBRSTR_DMA2RST_Pos) /*!< 0x02000000 */\r
+#define RCC_AHBRSTR_DMA2RST RCC_AHBRSTR_DMA2RST_Msk /*!< DMA2 reset */\r
+ \r
+/***************** Bit definition for RCC_APB2RSTR register *****************/\r
+#define RCC_APB2RSTR_SYSCFGRST_Pos (0U) \r
+#define RCC_APB2RSTR_SYSCFGRST_Msk (0x1UL << RCC_APB2RSTR_SYSCFGRST_Pos) /*!< 0x00000001 */\r
+#define RCC_APB2RSTR_SYSCFGRST RCC_APB2RSTR_SYSCFGRST_Msk /*!< System Configuration SYSCFG reset */\r
+#define RCC_APB2RSTR_TIM9RST_Pos (2U) \r
+#define RCC_APB2RSTR_TIM9RST_Msk (0x1UL << RCC_APB2RSTR_TIM9RST_Pos) /*!< 0x00000004 */\r
+#define RCC_APB2RSTR_TIM9RST RCC_APB2RSTR_TIM9RST_Msk /*!< TIM9 reset */\r
+#define RCC_APB2RSTR_TIM10RST_Pos (3U) \r
+#define RCC_APB2RSTR_TIM10RST_Msk (0x1UL << RCC_APB2RSTR_TIM10RST_Pos) /*!< 0x00000008 */\r
+#define RCC_APB2RSTR_TIM10RST RCC_APB2RSTR_TIM10RST_Msk /*!< TIM10 reset */\r
+#define RCC_APB2RSTR_TIM11RST_Pos (4U) \r
+#define RCC_APB2RSTR_TIM11RST_Msk (0x1UL << RCC_APB2RSTR_TIM11RST_Pos) /*!< 0x00000010 */\r
+#define RCC_APB2RSTR_TIM11RST RCC_APB2RSTR_TIM11RST_Msk /*!< TIM11 reset */\r
+#define RCC_APB2RSTR_ADC1RST_Pos (9U) \r
+#define RCC_APB2RSTR_ADC1RST_Msk (0x1UL << RCC_APB2RSTR_ADC1RST_Pos) /*!< 0x00000200 */\r
+#define RCC_APB2RSTR_ADC1RST RCC_APB2RSTR_ADC1RST_Msk /*!< ADC1 reset */\r
+#define RCC_APB2RSTR_SPI1RST_Pos (12U) \r
+#define RCC_APB2RSTR_SPI1RST_Msk (0x1UL << RCC_APB2RSTR_SPI1RST_Pos) /*!< 0x00001000 */\r
+#define RCC_APB2RSTR_SPI1RST RCC_APB2RSTR_SPI1RST_Msk /*!< SPI1 reset */\r
+#define RCC_APB2RSTR_USART1RST_Pos (14U) \r
+#define RCC_APB2RSTR_USART1RST_Msk (0x1UL << RCC_APB2RSTR_USART1RST_Pos) /*!< 0x00004000 */\r
+#define RCC_APB2RSTR_USART1RST RCC_APB2RSTR_USART1RST_Msk /*!< USART1 reset */\r
+\r
+/***************** Bit definition for RCC_APB1RSTR register *****************/\r
+#define RCC_APB1RSTR_TIM2RST_Pos (0U) \r
+#define RCC_APB1RSTR_TIM2RST_Msk (0x1UL << RCC_APB1RSTR_TIM2RST_Pos) /*!< 0x00000001 */\r
+#define RCC_APB1RSTR_TIM2RST RCC_APB1RSTR_TIM2RST_Msk /*!< Timer 2 reset */\r
+#define RCC_APB1RSTR_TIM3RST_Pos (1U) \r
+#define RCC_APB1RSTR_TIM3RST_Msk (0x1UL << RCC_APB1RSTR_TIM3RST_Pos) /*!< 0x00000002 */\r
+#define RCC_APB1RSTR_TIM3RST RCC_APB1RSTR_TIM3RST_Msk /*!< Timer 3 reset */\r
+#define RCC_APB1RSTR_TIM4RST_Pos (2U) \r
+#define RCC_APB1RSTR_TIM4RST_Msk (0x1UL << RCC_APB1RSTR_TIM4RST_Pos) /*!< 0x00000004 */\r
+#define RCC_APB1RSTR_TIM4RST RCC_APB1RSTR_TIM4RST_Msk /*!< Timer 4 reset */\r
+#define RCC_APB1RSTR_TIM5RST_Pos (3U) \r
+#define RCC_APB1RSTR_TIM5RST_Msk (0x1UL << RCC_APB1RSTR_TIM5RST_Pos) /*!< 0x00000008 */\r
+#define RCC_APB1RSTR_TIM5RST RCC_APB1RSTR_TIM5RST_Msk /*!< Timer 5 reset */\r
+#define RCC_APB1RSTR_TIM6RST_Pos (4U) \r
+#define RCC_APB1RSTR_TIM6RST_Msk (0x1UL << RCC_APB1RSTR_TIM6RST_Pos) /*!< 0x00000010 */\r
+#define RCC_APB1RSTR_TIM6RST RCC_APB1RSTR_TIM6RST_Msk /*!< Timer 6 reset */\r
+#define RCC_APB1RSTR_TIM7RST_Pos (5U) \r
+#define RCC_APB1RSTR_TIM7RST_Msk (0x1UL << RCC_APB1RSTR_TIM7RST_Pos) /*!< 0x00000020 */\r
+#define RCC_APB1RSTR_TIM7RST RCC_APB1RSTR_TIM7RST_Msk /*!< Timer 7 reset */\r
+#define RCC_APB1RSTR_LCDRST_Pos (9U) \r
+#define RCC_APB1RSTR_LCDRST_Msk (0x1UL << RCC_APB1RSTR_LCDRST_Pos) /*!< 0x00000200 */\r
+#define RCC_APB1RSTR_LCDRST RCC_APB1RSTR_LCDRST_Msk /*!< LCD reset */\r
+#define RCC_APB1RSTR_WWDGRST_Pos (11U) \r
+#define RCC_APB1RSTR_WWDGRST_Msk (0x1UL << RCC_APB1RSTR_WWDGRST_Pos) /*!< 0x00000800 */\r
+#define RCC_APB1RSTR_WWDGRST RCC_APB1RSTR_WWDGRST_Msk /*!< Window Watchdog reset */\r
+#define RCC_APB1RSTR_SPI2RST_Pos (14U) \r
+#define RCC_APB1RSTR_SPI2RST_Msk (0x1UL << RCC_APB1RSTR_SPI2RST_Pos) /*!< 0x00004000 */\r
+#define RCC_APB1RSTR_SPI2RST RCC_APB1RSTR_SPI2RST_Msk /*!< SPI 2 reset */\r
+#define RCC_APB1RSTR_SPI3RST_Pos (15U) \r
+#define RCC_APB1RSTR_SPI3RST_Msk (0x1UL << RCC_APB1RSTR_SPI3RST_Pos) /*!< 0x00008000 */\r
+#define RCC_APB1RSTR_SPI3RST RCC_APB1RSTR_SPI3RST_Msk /*!< SPI 3 reset */\r
+#define RCC_APB1RSTR_USART2RST_Pos (17U) \r
+#define RCC_APB1RSTR_USART2RST_Msk (0x1UL << RCC_APB1RSTR_USART2RST_Pos) /*!< 0x00020000 */\r
+#define RCC_APB1RSTR_USART2RST RCC_APB1RSTR_USART2RST_Msk /*!< USART 2 reset */\r
+#define RCC_APB1RSTR_USART3RST_Pos (18U) \r
+#define RCC_APB1RSTR_USART3RST_Msk (0x1UL << RCC_APB1RSTR_USART3RST_Pos) /*!< 0x00040000 */\r
+#define RCC_APB1RSTR_USART3RST RCC_APB1RSTR_USART3RST_Msk /*!< USART 3 reset */\r
+#define RCC_APB1RSTR_UART4RST_Pos (19U) \r
+#define RCC_APB1RSTR_UART4RST_Msk (0x1UL << RCC_APB1RSTR_UART4RST_Pos) /*!< 0x00080000 */\r
+#define RCC_APB1RSTR_UART4RST RCC_APB1RSTR_UART4RST_Msk /*!< UART 4 reset */\r
+#define RCC_APB1RSTR_UART5RST_Pos (20U) \r
+#define RCC_APB1RSTR_UART5RST_Msk (0x1UL << RCC_APB1RSTR_UART5RST_Pos) /*!< 0x00100000 */\r
+#define RCC_APB1RSTR_UART5RST RCC_APB1RSTR_UART5RST_Msk /*!< UART 5 reset */\r
+#define RCC_APB1RSTR_I2C1RST_Pos (21U) \r
+#define RCC_APB1RSTR_I2C1RST_Msk (0x1UL << RCC_APB1RSTR_I2C1RST_Pos) /*!< 0x00200000 */\r
+#define RCC_APB1RSTR_I2C1RST RCC_APB1RSTR_I2C1RST_Msk /*!< I2C 1 reset */\r
+#define RCC_APB1RSTR_I2C2RST_Pos (22U) \r
+#define RCC_APB1RSTR_I2C2RST_Msk (0x1UL << RCC_APB1RSTR_I2C2RST_Pos) /*!< 0x00400000 */\r
+#define RCC_APB1RSTR_I2C2RST RCC_APB1RSTR_I2C2RST_Msk /*!< I2C 2 reset */\r
+#define RCC_APB1RSTR_USBRST_Pos (23U) \r
+#define RCC_APB1RSTR_USBRST_Msk (0x1UL << RCC_APB1RSTR_USBRST_Pos) /*!< 0x00800000 */\r
+#define RCC_APB1RSTR_USBRST RCC_APB1RSTR_USBRST_Msk /*!< USB reset */\r
+#define RCC_APB1RSTR_PWRRST_Pos (28U) \r
+#define RCC_APB1RSTR_PWRRST_Msk (0x1UL << RCC_APB1RSTR_PWRRST_Pos) /*!< 0x10000000 */\r
+#define RCC_APB1RSTR_PWRRST RCC_APB1RSTR_PWRRST_Msk /*!< Power interface reset */\r
+#define RCC_APB1RSTR_DACRST_Pos (29U) \r
+#define RCC_APB1RSTR_DACRST_Msk (0x1UL << RCC_APB1RSTR_DACRST_Pos) /*!< 0x20000000 */\r
+#define RCC_APB1RSTR_DACRST RCC_APB1RSTR_DACRST_Msk /*!< DAC interface reset */\r
+#define RCC_APB1RSTR_COMPRST_Pos (31U) \r
+#define RCC_APB1RSTR_COMPRST_Msk (0x1UL << RCC_APB1RSTR_COMPRST_Pos) /*!< 0x80000000 */\r
+#define RCC_APB1RSTR_COMPRST RCC_APB1RSTR_COMPRST_Msk /*!< Comparator interface reset */\r
+\r
+/****************** Bit definition for RCC_AHBENR register ******************/\r
+#define RCC_AHBENR_GPIOAEN_Pos (0U) \r
+#define RCC_AHBENR_GPIOAEN_Msk (0x1UL << RCC_AHBENR_GPIOAEN_Pos) /*!< 0x00000001 */\r
+#define RCC_AHBENR_GPIOAEN RCC_AHBENR_GPIOAEN_Msk /*!< GPIO port A clock enable */\r
+#define RCC_AHBENR_GPIOBEN_Pos (1U) \r
+#define RCC_AHBENR_GPIOBEN_Msk (0x1UL << RCC_AHBENR_GPIOBEN_Pos) /*!< 0x00000002 */\r
+#define RCC_AHBENR_GPIOBEN RCC_AHBENR_GPIOBEN_Msk /*!< GPIO port B clock enable */\r
+#define RCC_AHBENR_GPIOCEN_Pos (2U) \r
+#define RCC_AHBENR_GPIOCEN_Msk (0x1UL << RCC_AHBENR_GPIOCEN_Pos) /*!< 0x00000004 */\r
+#define RCC_AHBENR_GPIOCEN RCC_AHBENR_GPIOCEN_Msk /*!< GPIO port C clock enable */\r
+#define RCC_AHBENR_GPIODEN_Pos (3U) \r
+#define RCC_AHBENR_GPIODEN_Msk (0x1UL << RCC_AHBENR_GPIODEN_Pos) /*!< 0x00000008 */\r
+#define RCC_AHBENR_GPIODEN RCC_AHBENR_GPIODEN_Msk /*!< GPIO port D clock enable */\r
+#define RCC_AHBENR_GPIOEEN_Pos (4U) \r
+#define RCC_AHBENR_GPIOEEN_Msk (0x1UL << RCC_AHBENR_GPIOEEN_Pos) /*!< 0x00000010 */\r
+#define RCC_AHBENR_GPIOEEN RCC_AHBENR_GPIOEEN_Msk /*!< GPIO port E clock enable */\r
+#define RCC_AHBENR_GPIOHEN_Pos (5U) \r
+#define RCC_AHBENR_GPIOHEN_Msk (0x1UL << RCC_AHBENR_GPIOHEN_Pos) /*!< 0x00000020 */\r
+#define RCC_AHBENR_GPIOHEN RCC_AHBENR_GPIOHEN_Msk /*!< GPIO port H clock enable */\r
+#define RCC_AHBENR_GPIOFEN_Pos (6U) \r
+#define RCC_AHBENR_GPIOFEN_Msk (0x1UL << RCC_AHBENR_GPIOFEN_Pos) /*!< 0x00000040 */\r
+#define RCC_AHBENR_GPIOFEN RCC_AHBENR_GPIOFEN_Msk /*!< GPIO port F clock enable */\r
+#define RCC_AHBENR_GPIOGEN_Pos (7U) \r
+#define RCC_AHBENR_GPIOGEN_Msk (0x1UL << RCC_AHBENR_GPIOGEN_Pos) /*!< 0x00000080 */\r
+#define RCC_AHBENR_GPIOGEN RCC_AHBENR_GPIOGEN_Msk /*!< GPIO port G clock enable */\r
+#define RCC_AHBENR_CRCEN_Pos (12U) \r
+#define RCC_AHBENR_CRCEN_Msk (0x1UL << RCC_AHBENR_CRCEN_Pos) /*!< 0x00001000 */\r
+#define RCC_AHBENR_CRCEN RCC_AHBENR_CRCEN_Msk /*!< CRC clock enable */\r
+#define RCC_AHBENR_FLITFEN_Pos (15U) \r
+#define RCC_AHBENR_FLITFEN_Msk (0x1UL << RCC_AHBENR_FLITFEN_Pos) /*!< 0x00008000 */\r
+#define RCC_AHBENR_FLITFEN RCC_AHBENR_FLITFEN_Msk /*!< FLITF clock enable (has effect only when\r
+ the Flash memory is in power down mode) */\r
+#define RCC_AHBENR_DMA1EN_Pos (24U) \r
+#define RCC_AHBENR_DMA1EN_Msk (0x1UL << RCC_AHBENR_DMA1EN_Pos) /*!< 0x01000000 */\r
+#define RCC_AHBENR_DMA1EN RCC_AHBENR_DMA1EN_Msk /*!< DMA1 clock enable */\r
+#define RCC_AHBENR_DMA2EN_Pos (25U) \r
+#define RCC_AHBENR_DMA2EN_Msk (0x1UL << RCC_AHBENR_DMA2EN_Pos) /*!< 0x02000000 */\r
+#define RCC_AHBENR_DMA2EN RCC_AHBENR_DMA2EN_Msk /*!< DMA2 clock enable */\r
+\r
+/****************** Bit definition for RCC_APB2ENR register *****************/\r
+#define RCC_APB2ENR_SYSCFGEN_Pos (0U) \r
+#define RCC_APB2ENR_SYSCFGEN_Msk (0x1UL << RCC_APB2ENR_SYSCFGEN_Pos) /*!< 0x00000001 */\r
+#define RCC_APB2ENR_SYSCFGEN RCC_APB2ENR_SYSCFGEN_Msk /*!< System Configuration SYSCFG clock enable */\r
+#define RCC_APB2ENR_TIM9EN_Pos (2U) \r
+#define RCC_APB2ENR_TIM9EN_Msk (0x1UL << RCC_APB2ENR_TIM9EN_Pos) /*!< 0x00000004 */\r
+#define RCC_APB2ENR_TIM9EN RCC_APB2ENR_TIM9EN_Msk /*!< TIM9 interface clock enable */\r
+#define RCC_APB2ENR_TIM10EN_Pos (3U) \r
+#define RCC_APB2ENR_TIM10EN_Msk (0x1UL << RCC_APB2ENR_TIM10EN_Pos) /*!< 0x00000008 */\r
+#define RCC_APB2ENR_TIM10EN RCC_APB2ENR_TIM10EN_Msk /*!< TIM10 interface clock enable */\r
+#define RCC_APB2ENR_TIM11EN_Pos (4U) \r
+#define RCC_APB2ENR_TIM11EN_Msk (0x1UL << RCC_APB2ENR_TIM11EN_Pos) /*!< 0x00000010 */\r
+#define RCC_APB2ENR_TIM11EN RCC_APB2ENR_TIM11EN_Msk /*!< TIM11 Timer clock enable */\r
+#define RCC_APB2ENR_ADC1EN_Pos (9U) \r
+#define RCC_APB2ENR_ADC1EN_Msk (0x1UL << RCC_APB2ENR_ADC1EN_Pos) /*!< 0x00000200 */\r
+#define RCC_APB2ENR_ADC1EN RCC_APB2ENR_ADC1EN_Msk /*!< ADC1 clock enable */\r
+#define RCC_APB2ENR_SPI1EN_Pos (12U) \r
+#define RCC_APB2ENR_SPI1EN_Msk (0x1UL << RCC_APB2ENR_SPI1EN_Pos) /*!< 0x00001000 */\r
+#define RCC_APB2ENR_SPI1EN RCC_APB2ENR_SPI1EN_Msk /*!< SPI1 clock enable */\r
+#define RCC_APB2ENR_USART1EN_Pos (14U) \r
+#define RCC_APB2ENR_USART1EN_Msk (0x1UL << RCC_APB2ENR_USART1EN_Pos) /*!< 0x00004000 */\r
+#define RCC_APB2ENR_USART1EN RCC_APB2ENR_USART1EN_Msk /*!< USART1 clock enable */\r
+\r
+/***************** Bit definition for RCC_APB1ENR register ******************/\r
+#define RCC_APB1ENR_TIM2EN_Pos (0U) \r
+#define RCC_APB1ENR_TIM2EN_Msk (0x1UL << RCC_APB1ENR_TIM2EN_Pos) /*!< 0x00000001 */\r
+#define RCC_APB1ENR_TIM2EN RCC_APB1ENR_TIM2EN_Msk /*!< Timer 2 clock enabled*/\r
+#define RCC_APB1ENR_TIM3EN_Pos (1U) \r
+#define RCC_APB1ENR_TIM3EN_Msk (0x1UL << RCC_APB1ENR_TIM3EN_Pos) /*!< 0x00000002 */\r
+#define RCC_APB1ENR_TIM3EN RCC_APB1ENR_TIM3EN_Msk /*!< Timer 3 clock enable */\r
+#define RCC_APB1ENR_TIM4EN_Pos (2U) \r
+#define RCC_APB1ENR_TIM4EN_Msk (0x1UL << RCC_APB1ENR_TIM4EN_Pos) /*!< 0x00000004 */\r
+#define RCC_APB1ENR_TIM4EN RCC_APB1ENR_TIM4EN_Msk /*!< Timer 4 clock enable */\r
+#define RCC_APB1ENR_TIM5EN_Pos (3U) \r
+#define RCC_APB1ENR_TIM5EN_Msk (0x1UL << RCC_APB1ENR_TIM5EN_Pos) /*!< 0x00000008 */\r
+#define RCC_APB1ENR_TIM5EN RCC_APB1ENR_TIM5EN_Msk /*!< Timer 5 clock enable */\r
+#define RCC_APB1ENR_TIM6EN_Pos (4U) \r
+#define RCC_APB1ENR_TIM6EN_Msk (0x1UL << RCC_APB1ENR_TIM6EN_Pos) /*!< 0x00000010 */\r
+#define RCC_APB1ENR_TIM6EN RCC_APB1ENR_TIM6EN_Msk /*!< Timer 6 clock enable */\r
+#define RCC_APB1ENR_TIM7EN_Pos (5U) \r
+#define RCC_APB1ENR_TIM7EN_Msk (0x1UL << RCC_APB1ENR_TIM7EN_Pos) /*!< 0x00000020 */\r
+#define RCC_APB1ENR_TIM7EN RCC_APB1ENR_TIM7EN_Msk /*!< Timer 7 clock enable */\r
+#define RCC_APB1ENR_LCDEN_Pos (9U) \r
+#define RCC_APB1ENR_LCDEN_Msk (0x1UL << RCC_APB1ENR_LCDEN_Pos) /*!< 0x00000200 */\r
+#define RCC_APB1ENR_LCDEN RCC_APB1ENR_LCDEN_Msk /*!< LCD clock enable */\r
+#define RCC_APB1ENR_WWDGEN_Pos (11U) \r
+#define RCC_APB1ENR_WWDGEN_Msk (0x1UL << RCC_APB1ENR_WWDGEN_Pos) /*!< 0x00000800 */\r
+#define RCC_APB1ENR_WWDGEN RCC_APB1ENR_WWDGEN_Msk /*!< Window Watchdog clock enable */\r
+#define RCC_APB1ENR_SPI2EN_Pos (14U) \r
+#define RCC_APB1ENR_SPI2EN_Msk (0x1UL << RCC_APB1ENR_SPI2EN_Pos) /*!< 0x00004000 */\r
+#define RCC_APB1ENR_SPI2EN RCC_APB1ENR_SPI2EN_Msk /*!< SPI 2 clock enable */\r
+#define RCC_APB1ENR_SPI3EN_Pos (15U) \r
+#define RCC_APB1ENR_SPI3EN_Msk (0x1UL << RCC_APB1ENR_SPI3EN_Pos) /*!< 0x00008000 */\r
+#define RCC_APB1ENR_SPI3EN RCC_APB1ENR_SPI3EN_Msk /*!< SPI 3 clock enable */\r
+#define RCC_APB1ENR_USART2EN_Pos (17U) \r
+#define RCC_APB1ENR_USART2EN_Msk (0x1UL << RCC_APB1ENR_USART2EN_Pos) /*!< 0x00020000 */\r
+#define RCC_APB1ENR_USART2EN RCC_APB1ENR_USART2EN_Msk /*!< USART 2 clock enable */\r
+#define RCC_APB1ENR_USART3EN_Pos (18U) \r
+#define RCC_APB1ENR_USART3EN_Msk (0x1UL << RCC_APB1ENR_USART3EN_Pos) /*!< 0x00040000 */\r
+#define RCC_APB1ENR_USART3EN RCC_APB1ENR_USART3EN_Msk /*!< USART 3 clock enable */\r
+#define RCC_APB1ENR_UART4EN_Pos (19U) \r
+#define RCC_APB1ENR_UART4EN_Msk (0x1UL << RCC_APB1ENR_UART4EN_Pos) /*!< 0x00080000 */\r
+#define RCC_APB1ENR_UART4EN RCC_APB1ENR_UART4EN_Msk /*!< UART 4 clock enable */\r
+#define RCC_APB1ENR_UART5EN_Pos (20U) \r
+#define RCC_APB1ENR_UART5EN_Msk (0x1UL << RCC_APB1ENR_UART5EN_Pos) /*!< 0x00100000 */\r
+#define RCC_APB1ENR_UART5EN RCC_APB1ENR_UART5EN_Msk /*!< UART 5 clock enable */\r
+#define RCC_APB1ENR_I2C1EN_Pos (21U) \r
+#define RCC_APB1ENR_I2C1EN_Msk (0x1UL << RCC_APB1ENR_I2C1EN_Pos) /*!< 0x00200000 */\r
+#define RCC_APB1ENR_I2C1EN RCC_APB1ENR_I2C1EN_Msk /*!< I2C 1 clock enable */\r
+#define RCC_APB1ENR_I2C2EN_Pos (22U) \r
+#define RCC_APB1ENR_I2C2EN_Msk (0x1UL << RCC_APB1ENR_I2C2EN_Pos) /*!< 0x00400000 */\r
+#define RCC_APB1ENR_I2C2EN RCC_APB1ENR_I2C2EN_Msk /*!< I2C 2 clock enable */\r
+#define RCC_APB1ENR_USBEN_Pos (23U) \r
+#define RCC_APB1ENR_USBEN_Msk (0x1UL << RCC_APB1ENR_USBEN_Pos) /*!< 0x00800000 */\r
+#define RCC_APB1ENR_USBEN RCC_APB1ENR_USBEN_Msk /*!< USB clock enable */\r
+#define RCC_APB1ENR_PWREN_Pos (28U) \r
+#define RCC_APB1ENR_PWREN_Msk (0x1UL << RCC_APB1ENR_PWREN_Pos) /*!< 0x10000000 */\r
+#define RCC_APB1ENR_PWREN RCC_APB1ENR_PWREN_Msk /*!< Power interface clock enable */\r
+#define RCC_APB1ENR_DACEN_Pos (29U) \r
+#define RCC_APB1ENR_DACEN_Msk (0x1UL << RCC_APB1ENR_DACEN_Pos) /*!< 0x20000000 */\r
+#define RCC_APB1ENR_DACEN RCC_APB1ENR_DACEN_Msk /*!< DAC interface clock enable */\r
+#define RCC_APB1ENR_COMPEN_Pos (31U) \r
+#define RCC_APB1ENR_COMPEN_Msk (0x1UL << RCC_APB1ENR_COMPEN_Pos) /*!< 0x80000000 */\r
+#define RCC_APB1ENR_COMPEN RCC_APB1ENR_COMPEN_Msk /*!< Comparator interface clock enable */\r
+\r
+/****************** Bit definition for RCC_AHBLPENR register ****************/\r
+#define RCC_AHBLPENR_GPIOALPEN_Pos (0U) \r
+#define RCC_AHBLPENR_GPIOALPEN_Msk (0x1UL << RCC_AHBLPENR_GPIOALPEN_Pos) /*!< 0x00000001 */\r
+#define RCC_AHBLPENR_GPIOALPEN RCC_AHBLPENR_GPIOALPEN_Msk /*!< GPIO port A clock enabled in sleep mode */\r
+#define RCC_AHBLPENR_GPIOBLPEN_Pos (1U) \r
+#define RCC_AHBLPENR_GPIOBLPEN_Msk (0x1UL << RCC_AHBLPENR_GPIOBLPEN_Pos) /*!< 0x00000002 */\r
+#define RCC_AHBLPENR_GPIOBLPEN RCC_AHBLPENR_GPIOBLPEN_Msk /*!< GPIO port B clock enabled in sleep mode */\r
+#define RCC_AHBLPENR_GPIOCLPEN_Pos (2U) \r
+#define RCC_AHBLPENR_GPIOCLPEN_Msk (0x1UL << RCC_AHBLPENR_GPIOCLPEN_Pos) /*!< 0x00000004 */\r
+#define RCC_AHBLPENR_GPIOCLPEN RCC_AHBLPENR_GPIOCLPEN_Msk /*!< GPIO port C clock enabled in sleep mode */\r
+#define RCC_AHBLPENR_GPIODLPEN_Pos (3U) \r
+#define RCC_AHBLPENR_GPIODLPEN_Msk (0x1UL << RCC_AHBLPENR_GPIODLPEN_Pos) /*!< 0x00000008 */\r
+#define RCC_AHBLPENR_GPIODLPEN RCC_AHBLPENR_GPIODLPEN_Msk /*!< GPIO port D clock enabled in sleep mode */\r
+#define RCC_AHBLPENR_GPIOELPEN_Pos (4U) \r
+#define RCC_AHBLPENR_GPIOELPEN_Msk (0x1UL << RCC_AHBLPENR_GPIOELPEN_Pos) /*!< 0x00000010 */\r
+#define RCC_AHBLPENR_GPIOELPEN RCC_AHBLPENR_GPIOELPEN_Msk /*!< GPIO port E clock enabled in sleep mode */\r
+#define RCC_AHBLPENR_GPIOHLPEN_Pos (5U) \r
+#define RCC_AHBLPENR_GPIOHLPEN_Msk (0x1UL << RCC_AHBLPENR_GPIOHLPEN_Pos) /*!< 0x00000020 */\r
+#define RCC_AHBLPENR_GPIOHLPEN RCC_AHBLPENR_GPIOHLPEN_Msk /*!< GPIO port H clock enabled in sleep mode */\r
+#define RCC_AHBLPENR_GPIOFLPEN_Pos (6U) \r
+#define RCC_AHBLPENR_GPIOFLPEN_Msk (0x1UL << RCC_AHBLPENR_GPIOFLPEN_Pos) /*!< 0x00000040 */\r
+#define RCC_AHBLPENR_GPIOFLPEN RCC_AHBLPENR_GPIOFLPEN_Msk /*!< GPIO port F clock enabled in sleep mode */\r
+#define RCC_AHBLPENR_GPIOGLPEN_Pos (7U) \r
+#define RCC_AHBLPENR_GPIOGLPEN_Msk (0x1UL << RCC_AHBLPENR_GPIOGLPEN_Pos) /*!< 0x00000080 */\r
+#define RCC_AHBLPENR_GPIOGLPEN RCC_AHBLPENR_GPIOGLPEN_Msk /*!< GPIO port G clock enabled in sleep mode */\r
+#define RCC_AHBLPENR_CRCLPEN_Pos (12U) \r
+#define RCC_AHBLPENR_CRCLPEN_Msk (0x1UL << RCC_AHBLPENR_CRCLPEN_Pos) /*!< 0x00001000 */\r
+#define RCC_AHBLPENR_CRCLPEN RCC_AHBLPENR_CRCLPEN_Msk /*!< CRC clock enabled in sleep mode */\r
+#define RCC_AHBLPENR_FLITFLPEN_Pos (15U) \r
+#define RCC_AHBLPENR_FLITFLPEN_Msk (0x1UL << RCC_AHBLPENR_FLITFLPEN_Pos) /*!< 0x00008000 */\r
+#define RCC_AHBLPENR_FLITFLPEN RCC_AHBLPENR_FLITFLPEN_Msk /*!< Flash Interface clock enabled in sleep mode\r
+ (has effect only when the Flash memory is\r
+ in power down mode) */\r
+#define RCC_AHBLPENR_SRAMLPEN_Pos (16U) \r
+#define RCC_AHBLPENR_SRAMLPEN_Msk (0x1UL << RCC_AHBLPENR_SRAMLPEN_Pos) /*!< 0x00010000 */\r
+#define RCC_AHBLPENR_SRAMLPEN RCC_AHBLPENR_SRAMLPEN_Msk /*!< SRAM clock enabled in sleep mode */\r
+#define RCC_AHBLPENR_DMA1LPEN_Pos (24U) \r
+#define RCC_AHBLPENR_DMA1LPEN_Msk (0x1UL << RCC_AHBLPENR_DMA1LPEN_Pos) /*!< 0x01000000 */\r
+#define RCC_AHBLPENR_DMA1LPEN RCC_AHBLPENR_DMA1LPEN_Msk /*!< DMA1 clock enabled in sleep mode */\r
+#define RCC_AHBLPENR_DMA2LPEN_Pos (25U) \r
+#define RCC_AHBLPENR_DMA2LPEN_Msk (0x1UL << RCC_AHBLPENR_DMA2LPEN_Pos) /*!< 0x02000000 */\r
+#define RCC_AHBLPENR_DMA2LPEN RCC_AHBLPENR_DMA2LPEN_Msk /*!< DMA2 clock enabled in sleep mode */\r
+\r
+/****************** Bit definition for RCC_APB2LPENR register ***************/\r
+#define RCC_APB2LPENR_SYSCFGLPEN_Pos (0U) \r
+#define RCC_APB2LPENR_SYSCFGLPEN_Msk (0x1UL << RCC_APB2LPENR_SYSCFGLPEN_Pos) /*!< 0x00000001 */\r
+#define RCC_APB2LPENR_SYSCFGLPEN RCC_APB2LPENR_SYSCFGLPEN_Msk /*!< System Configuration SYSCFG clock enabled in sleep mode */\r
+#define RCC_APB2LPENR_TIM9LPEN_Pos (2U) \r
+#define RCC_APB2LPENR_TIM9LPEN_Msk (0x1UL << RCC_APB2LPENR_TIM9LPEN_Pos) /*!< 0x00000004 */\r
+#define RCC_APB2LPENR_TIM9LPEN RCC_APB2LPENR_TIM9LPEN_Msk /*!< TIM9 interface clock enabled in sleep mode */\r
+#define RCC_APB2LPENR_TIM10LPEN_Pos (3U) \r
+#define RCC_APB2LPENR_TIM10LPEN_Msk (0x1UL << RCC_APB2LPENR_TIM10LPEN_Pos) /*!< 0x00000008 */\r
+#define RCC_APB2LPENR_TIM10LPEN RCC_APB2LPENR_TIM10LPEN_Msk /*!< TIM10 interface clock enabled in sleep mode */\r
+#define RCC_APB2LPENR_TIM11LPEN_Pos (4U) \r
+#define RCC_APB2LPENR_TIM11LPEN_Msk (0x1UL << RCC_APB2LPENR_TIM11LPEN_Pos) /*!< 0x00000010 */\r
+#define RCC_APB2LPENR_TIM11LPEN RCC_APB2LPENR_TIM11LPEN_Msk /*!< TIM11 Timer clock enabled in sleep mode */\r
+#define RCC_APB2LPENR_ADC1LPEN_Pos (9U) \r
+#define RCC_APB2LPENR_ADC1LPEN_Msk (0x1UL << RCC_APB2LPENR_ADC1LPEN_Pos) /*!< 0x00000200 */\r
+#define RCC_APB2LPENR_ADC1LPEN RCC_APB2LPENR_ADC1LPEN_Msk /*!< ADC1 clock enabled in sleep mode */\r
+#define RCC_APB2LPENR_SPI1LPEN_Pos (12U) \r
+#define RCC_APB2LPENR_SPI1LPEN_Msk (0x1UL << RCC_APB2LPENR_SPI1LPEN_Pos) /*!< 0x00001000 */\r
+#define RCC_APB2LPENR_SPI1LPEN RCC_APB2LPENR_SPI1LPEN_Msk /*!< SPI1 clock enabled in sleep mode */\r
+#define RCC_APB2LPENR_USART1LPEN_Pos (14U) \r
+#define RCC_APB2LPENR_USART1LPEN_Msk (0x1UL << RCC_APB2LPENR_USART1LPEN_Pos) /*!< 0x00004000 */\r
+#define RCC_APB2LPENR_USART1LPEN RCC_APB2LPENR_USART1LPEN_Msk /*!< USART1 clock enabled in sleep mode */\r
+\r
+/***************** Bit definition for RCC_APB1LPENR register ****************/\r
+#define RCC_APB1LPENR_TIM2LPEN_Pos (0U) \r
+#define RCC_APB1LPENR_TIM2LPEN_Msk (0x1UL << RCC_APB1LPENR_TIM2LPEN_Pos) /*!< 0x00000001 */\r
+#define RCC_APB1LPENR_TIM2LPEN RCC_APB1LPENR_TIM2LPEN_Msk /*!< Timer 2 clock enabled in sleep mode */\r
+#define RCC_APB1LPENR_TIM3LPEN_Pos (1U) \r
+#define RCC_APB1LPENR_TIM3LPEN_Msk (0x1UL << RCC_APB1LPENR_TIM3LPEN_Pos) /*!< 0x00000002 */\r
+#define RCC_APB1LPENR_TIM3LPEN RCC_APB1LPENR_TIM3LPEN_Msk /*!< Timer 3 clock enabled in sleep mode */\r
+#define RCC_APB1LPENR_TIM4LPEN_Pos (2U) \r
+#define RCC_APB1LPENR_TIM4LPEN_Msk (0x1UL << RCC_APB1LPENR_TIM4LPEN_Pos) /*!< 0x00000004 */\r
+#define RCC_APB1LPENR_TIM4LPEN RCC_APB1LPENR_TIM4LPEN_Msk /*!< Timer 4 clock enabled in sleep mode */\r
+#define RCC_APB1LPENR_TIM5LPEN_Pos (3U) \r
+#define RCC_APB1LPENR_TIM5LPEN_Msk (0x1UL << RCC_APB1LPENR_TIM5LPEN_Pos) /*!< 0x00000008 */\r
+#define RCC_APB1LPENR_TIM5LPEN RCC_APB1LPENR_TIM5LPEN_Msk /*!< Timer 5 clock enabled in sleep mode */\r
+#define RCC_APB1LPENR_TIM6LPEN_Pos (4U) \r
+#define RCC_APB1LPENR_TIM6LPEN_Msk (0x1UL << RCC_APB1LPENR_TIM6LPEN_Pos) /*!< 0x00000010 */\r
+#define RCC_APB1LPENR_TIM6LPEN RCC_APB1LPENR_TIM6LPEN_Msk /*!< Timer 6 clock enabled in sleep mode */\r
+#define RCC_APB1LPENR_TIM7LPEN_Pos (5U) \r
+#define RCC_APB1LPENR_TIM7LPEN_Msk (0x1UL << RCC_APB1LPENR_TIM7LPEN_Pos) /*!< 0x00000020 */\r
+#define RCC_APB1LPENR_TIM7LPEN RCC_APB1LPENR_TIM7LPEN_Msk /*!< Timer 7 clock enabled in sleep mode */\r
+#define RCC_APB1LPENR_LCDLPEN_Pos (9U) \r
+#define RCC_APB1LPENR_LCDLPEN_Msk (0x1UL << RCC_APB1LPENR_LCDLPEN_Pos) /*!< 0x00000200 */\r
+#define RCC_APB1LPENR_LCDLPEN RCC_APB1LPENR_LCDLPEN_Msk /*!< LCD clock enabled in sleep mode */\r
+#define RCC_APB1LPENR_WWDGLPEN_Pos (11U) \r
+#define RCC_APB1LPENR_WWDGLPEN_Msk (0x1UL << RCC_APB1LPENR_WWDGLPEN_Pos) /*!< 0x00000800 */\r
+#define RCC_APB1LPENR_WWDGLPEN RCC_APB1LPENR_WWDGLPEN_Msk /*!< Window Watchdog clock enabled in sleep mode */\r
+#define RCC_APB1LPENR_SPI2LPEN_Pos (14U) \r
+#define RCC_APB1LPENR_SPI2LPEN_Msk (0x1UL << RCC_APB1LPENR_SPI2LPEN_Pos) /*!< 0x00004000 */\r
+#define RCC_APB1LPENR_SPI2LPEN RCC_APB1LPENR_SPI2LPEN_Msk /*!< SPI 2 clock enabled in sleep mode */\r
+#define RCC_APB1LPENR_SPI3LPEN_Pos (15U) \r
+#define RCC_APB1LPENR_SPI3LPEN_Msk (0x1UL << RCC_APB1LPENR_SPI3LPEN_Pos) /*!< 0x00008000 */\r
+#define RCC_APB1LPENR_SPI3LPEN RCC_APB1LPENR_SPI3LPEN_Msk /*!< SPI 3 clock enabled in sleep mode */\r
+#define RCC_APB1LPENR_USART2LPEN_Pos (17U) \r
+#define RCC_APB1LPENR_USART2LPEN_Msk (0x1UL << RCC_APB1LPENR_USART2LPEN_Pos) /*!< 0x00020000 */\r
+#define RCC_APB1LPENR_USART2LPEN RCC_APB1LPENR_USART2LPEN_Msk /*!< USART 2 clock enabled in sleep mode */\r
+#define RCC_APB1LPENR_USART3LPEN_Pos (18U) \r
+#define RCC_APB1LPENR_USART3LPEN_Msk (0x1UL << RCC_APB1LPENR_USART3LPEN_Pos) /*!< 0x00040000 */\r
+#define RCC_APB1LPENR_USART3LPEN RCC_APB1LPENR_USART3LPEN_Msk /*!< USART 3 clock enabled in sleep mode */\r
+#define RCC_APB1LPENR_UART4LPEN_Pos (19U) \r
+#define RCC_APB1LPENR_UART4LPEN_Msk (0x1UL << RCC_APB1LPENR_UART4LPEN_Pos) /*!< 0x00080000 */\r
+#define RCC_APB1LPENR_UART4LPEN RCC_APB1LPENR_UART4LPEN_Msk /*!< UART 4 clock enabled in sleep mode */\r
+#define RCC_APB1LPENR_UART5LPEN_Pos (20U) \r
+#define RCC_APB1LPENR_UART5LPEN_Msk (0x1UL << RCC_APB1LPENR_UART5LPEN_Pos) /*!< 0x00100000 */\r
+#define RCC_APB1LPENR_UART5LPEN RCC_APB1LPENR_UART5LPEN_Msk /*!< UART 5 clock enabled in sleep mode */\r
+#define RCC_APB1LPENR_I2C1LPEN_Pos (21U) \r
+#define RCC_APB1LPENR_I2C1LPEN_Msk (0x1UL << RCC_APB1LPENR_I2C1LPEN_Pos) /*!< 0x00200000 */\r
+#define RCC_APB1LPENR_I2C1LPEN RCC_APB1LPENR_I2C1LPEN_Msk /*!< I2C 1 clock enabled in sleep mode */\r
+#define RCC_APB1LPENR_I2C2LPEN_Pos (22U) \r
+#define RCC_APB1LPENR_I2C2LPEN_Msk (0x1UL << RCC_APB1LPENR_I2C2LPEN_Pos) /*!< 0x00400000 */\r
+#define RCC_APB1LPENR_I2C2LPEN RCC_APB1LPENR_I2C2LPEN_Msk /*!< I2C 2 clock enabled in sleep mode */\r
+#define RCC_APB1LPENR_USBLPEN_Pos (23U) \r
+#define RCC_APB1LPENR_USBLPEN_Msk (0x1UL << RCC_APB1LPENR_USBLPEN_Pos) /*!< 0x00800000 */\r
+#define RCC_APB1LPENR_USBLPEN RCC_APB1LPENR_USBLPEN_Msk /*!< USB clock enabled in sleep mode */\r
+#define RCC_APB1LPENR_PWRLPEN_Pos (28U) \r
+#define RCC_APB1LPENR_PWRLPEN_Msk (0x1UL << RCC_APB1LPENR_PWRLPEN_Pos) /*!< 0x10000000 */\r
+#define RCC_APB1LPENR_PWRLPEN RCC_APB1LPENR_PWRLPEN_Msk /*!< Power interface clock enabled in sleep mode */\r
+#define RCC_APB1LPENR_DACLPEN_Pos (29U) \r
+#define RCC_APB1LPENR_DACLPEN_Msk (0x1UL << RCC_APB1LPENR_DACLPEN_Pos) /*!< 0x20000000 */\r
+#define RCC_APB1LPENR_DACLPEN RCC_APB1LPENR_DACLPEN_Msk /*!< DAC interface clock enabled in sleep mode */\r
+#define RCC_APB1LPENR_COMPLPEN_Pos (31U) \r
+#define RCC_APB1LPENR_COMPLPEN_Msk (0x1UL << RCC_APB1LPENR_COMPLPEN_Pos) /*!< 0x80000000 */\r
+#define RCC_APB1LPENR_COMPLPEN RCC_APB1LPENR_COMPLPEN_Msk /*!< Comparator interface clock enabled in sleep mode*/\r
+\r
+/******************* Bit definition for RCC_CSR register ********************/\r
+#define RCC_CSR_LSION_Pos (0U) \r
+#define RCC_CSR_LSION_Msk (0x1UL << RCC_CSR_LSION_Pos) /*!< 0x00000001 */\r
+#define RCC_CSR_LSION RCC_CSR_LSION_Msk /*!< Internal Low Speed oscillator enable */\r
+#define RCC_CSR_LSIRDY_Pos (1U) \r
+#define RCC_CSR_LSIRDY_Msk (0x1UL << RCC_CSR_LSIRDY_Pos) /*!< 0x00000002 */\r
+#define RCC_CSR_LSIRDY RCC_CSR_LSIRDY_Msk /*!< Internal Low Speed oscillator Ready */\r
+\r
+#define RCC_CSR_LSEON_Pos (8U) \r
+#define RCC_CSR_LSEON_Msk (0x1UL << RCC_CSR_LSEON_Pos) /*!< 0x00000100 */\r
+#define RCC_CSR_LSEON RCC_CSR_LSEON_Msk /*!< External Low Speed oscillator enable */\r
+#define RCC_CSR_LSERDY_Pos (9U) \r
+#define RCC_CSR_LSERDY_Msk (0x1UL << RCC_CSR_LSERDY_Pos) /*!< 0x00000200 */\r
+#define RCC_CSR_LSERDY RCC_CSR_LSERDY_Msk /*!< External Low Speed oscillator Ready */\r
+#define RCC_CSR_LSEBYP_Pos (10U) \r
+#define RCC_CSR_LSEBYP_Msk (0x1UL << RCC_CSR_LSEBYP_Pos) /*!< 0x00000400 */\r
+#define RCC_CSR_LSEBYP RCC_CSR_LSEBYP_Msk /*!< External Low Speed oscillator Bypass */\r
+\r
+#define RCC_CSR_LSECSSON_Pos (11U) \r
+#define RCC_CSR_LSECSSON_Msk (0x1UL << RCC_CSR_LSECSSON_Pos) /*!< 0x00000800 */\r
+#define RCC_CSR_LSECSSON RCC_CSR_LSECSSON_Msk /*!< External Low Speed oscillator CSS Enable */\r
+#define RCC_CSR_LSECSSD_Pos (12U) \r
+#define RCC_CSR_LSECSSD_Msk (0x1UL << RCC_CSR_LSECSSD_Pos) /*!< 0x00001000 */\r
+#define RCC_CSR_LSECSSD RCC_CSR_LSECSSD_Msk /*!< External Low Speed oscillator CSS Detected */\r
+\r
+#define RCC_CSR_RTCSEL_Pos (16U) \r
+#define RCC_CSR_RTCSEL_Msk (0x3UL << RCC_CSR_RTCSEL_Pos) /*!< 0x00030000 */\r
+#define RCC_CSR_RTCSEL RCC_CSR_RTCSEL_Msk /*!< RTCSEL[1:0] bits (RTC clock source selection) */\r
+#define RCC_CSR_RTCSEL_0 (0x1UL << RCC_CSR_RTCSEL_Pos) /*!< 0x00010000 */\r
+#define RCC_CSR_RTCSEL_1 (0x2UL << RCC_CSR_RTCSEL_Pos) /*!< 0x00020000 */\r
+\r
+/*!< RTC congiguration */\r
+#define RCC_CSR_RTCSEL_NOCLOCK (0x00000000U) /*!< No clock */\r
+#define RCC_CSR_RTCSEL_LSE_Pos (16U) \r
+#define RCC_CSR_RTCSEL_LSE_Msk (0x1UL << RCC_CSR_RTCSEL_LSE_Pos) /*!< 0x00010000 */\r
+#define RCC_CSR_RTCSEL_LSE RCC_CSR_RTCSEL_LSE_Msk /*!< LSE oscillator clock used as RTC clock */\r
+#define RCC_CSR_RTCSEL_LSI_Pos (17U) \r
+#define RCC_CSR_RTCSEL_LSI_Msk (0x1UL << RCC_CSR_RTCSEL_LSI_Pos) /*!< 0x00020000 */\r
+#define RCC_CSR_RTCSEL_LSI RCC_CSR_RTCSEL_LSI_Msk /*!< LSI oscillator clock used as RTC clock */\r
+#define RCC_CSR_RTCSEL_HSE_Pos (16U) \r
+#define RCC_CSR_RTCSEL_HSE_Msk (0x3UL << RCC_CSR_RTCSEL_HSE_Pos) /*!< 0x00030000 */\r
+#define RCC_CSR_RTCSEL_HSE RCC_CSR_RTCSEL_HSE_Msk /*!< HSE oscillator clock divided by 2, 4, 8 or 16 by RTCPRE used as RTC clock */\r
+\r
+#define RCC_CSR_RTCEN_Pos (22U) \r
+#define RCC_CSR_RTCEN_Msk (0x1UL << RCC_CSR_RTCEN_Pos) /*!< 0x00400000 */\r
+#define RCC_CSR_RTCEN RCC_CSR_RTCEN_Msk /*!< RTC clock enable */\r
+#define RCC_CSR_RTCRST_Pos (23U) \r
+#define RCC_CSR_RTCRST_Msk (0x1UL << RCC_CSR_RTCRST_Pos) /*!< 0x00800000 */\r
+#define RCC_CSR_RTCRST RCC_CSR_RTCRST_Msk /*!< RTC reset */\r
+ \r
+#define RCC_CSR_RMVF_Pos (24U) \r
+#define RCC_CSR_RMVF_Msk (0x1UL << RCC_CSR_RMVF_Pos) /*!< 0x01000000 */\r
+#define RCC_CSR_RMVF RCC_CSR_RMVF_Msk /*!< Remove reset flag */\r
+#define RCC_CSR_OBLRSTF_Pos (25U) \r
+#define RCC_CSR_OBLRSTF_Msk (0x1UL << RCC_CSR_OBLRSTF_Pos) /*!< 0x02000000 */\r
+#define RCC_CSR_OBLRSTF RCC_CSR_OBLRSTF_Msk /*!< Option Bytes Loader reset flag */\r
+#define RCC_CSR_PINRSTF_Pos (26U) \r
+#define RCC_CSR_PINRSTF_Msk (0x1UL << RCC_CSR_PINRSTF_Pos) /*!< 0x04000000 */\r
+#define RCC_CSR_PINRSTF RCC_CSR_PINRSTF_Msk /*!< PIN reset flag */\r
+#define RCC_CSR_PORRSTF_Pos (27U) \r
+#define RCC_CSR_PORRSTF_Msk (0x1UL << RCC_CSR_PORRSTF_Pos) /*!< 0x08000000 */\r
+#define RCC_CSR_PORRSTF RCC_CSR_PORRSTF_Msk /*!< POR/PDR reset flag */\r
+#define RCC_CSR_SFTRSTF_Pos (28U) \r
+#define RCC_CSR_SFTRSTF_Msk (0x1UL << RCC_CSR_SFTRSTF_Pos) /*!< 0x10000000 */\r
+#define RCC_CSR_SFTRSTF RCC_CSR_SFTRSTF_Msk /*!< Software Reset flag */\r
+#define RCC_CSR_IWDGRSTF_Pos (29U) \r
+#define RCC_CSR_IWDGRSTF_Msk (0x1UL << RCC_CSR_IWDGRSTF_Pos) /*!< 0x20000000 */\r
+#define RCC_CSR_IWDGRSTF RCC_CSR_IWDGRSTF_Msk /*!< Independent Watchdog reset flag */\r
+#define RCC_CSR_WWDGRSTF_Pos (30U) \r
+#define RCC_CSR_WWDGRSTF_Msk (0x1UL << RCC_CSR_WWDGRSTF_Pos) /*!< 0x40000000 */\r
+#define RCC_CSR_WWDGRSTF RCC_CSR_WWDGRSTF_Msk /*!< Window watchdog reset flag */\r
+#define RCC_CSR_LPWRRSTF_Pos (31U) \r
+#define RCC_CSR_LPWRRSTF_Msk (0x1UL << RCC_CSR_LPWRRSTF_Pos) /*!< 0x80000000 */\r
+#define RCC_CSR_LPWRRSTF RCC_CSR_LPWRRSTF_Msk /*!< Low-Power reset flag */\r
+\r
+/******************************************************************************/\r
+/* */\r
+/* Real-Time Clock (RTC) */\r
+/* */\r
+/******************************************************************************/\r
+/*\r
+* @brief Specific device feature definitions (not present on all devices in the STM32F0 serie)\r
+*/\r
+#define RTC_TAMPER1_SUPPORT /*!< TAMPER 1 feature support */\r
+#define RTC_TAMPER2_SUPPORT /*!< TAMPER 2 feature support */\r
+#define RTC_TAMPER3_SUPPORT /*!< TAMPER 3 feature support */\r
+#define RTC_BACKUP_SUPPORT /*!< BACKUP register feature support */\r
+#define RTC_WAKEUP_SUPPORT /*!< WAKEUP feature support */\r
+#define RTC_SMOOTHCALIB_SUPPORT /*!< Smooth digital calibration feature support */\r
+#define RTC_SUBSECOND_SUPPORT /*!< Sub-second feature support */\r
+\r
+/******************** Bits definition for RTC_TR register *******************/\r
+#define RTC_TR_PM_Pos (22U) \r
+#define RTC_TR_PM_Msk (0x1UL << RTC_TR_PM_Pos) /*!< 0x00400000 */\r
+#define RTC_TR_PM RTC_TR_PM_Msk \r
+#define RTC_TR_HT_Pos (20U) \r
+#define RTC_TR_HT_Msk (0x3UL << RTC_TR_HT_Pos) /*!< 0x00300000 */\r
+#define RTC_TR_HT RTC_TR_HT_Msk \r
+#define RTC_TR_HT_0 (0x1UL << RTC_TR_HT_Pos) /*!< 0x00100000 */\r
+#define RTC_TR_HT_1 (0x2UL << RTC_TR_HT_Pos) /*!< 0x00200000 */\r
+#define RTC_TR_HU_Pos (16U) \r
+#define RTC_TR_HU_Msk (0xFUL << RTC_TR_HU_Pos) /*!< 0x000F0000 */\r
+#define RTC_TR_HU RTC_TR_HU_Msk \r
+#define RTC_TR_HU_0 (0x1UL << RTC_TR_HU_Pos) /*!< 0x00010000 */\r
+#define RTC_TR_HU_1 (0x2UL << RTC_TR_HU_Pos) /*!< 0x00020000 */\r
+#define RTC_TR_HU_2 (0x4UL << RTC_TR_HU_Pos) /*!< 0x00040000 */\r
+#define RTC_TR_HU_3 (0x8UL << RTC_TR_HU_Pos) /*!< 0x00080000 */\r
+#define RTC_TR_MNT_Pos (12U) \r
+#define RTC_TR_MNT_Msk (0x7UL << RTC_TR_MNT_Pos) /*!< 0x00007000 */\r
+#define RTC_TR_MNT RTC_TR_MNT_Msk \r
+#define RTC_TR_MNT_0 (0x1UL << RTC_TR_MNT_Pos) /*!< 0x00001000 */\r
+#define RTC_TR_MNT_1 (0x2UL << RTC_TR_MNT_Pos) /*!< 0x00002000 */\r
+#define RTC_TR_MNT_2 (0x4UL << RTC_TR_MNT_Pos) /*!< 0x00004000 */\r
+#define RTC_TR_MNU_Pos (8U) \r
+#define RTC_TR_MNU_Msk (0xFUL << RTC_TR_MNU_Pos) /*!< 0x00000F00 */\r
+#define RTC_TR_MNU RTC_TR_MNU_Msk \r
+#define RTC_TR_MNU_0 (0x1UL << RTC_TR_MNU_Pos) /*!< 0x00000100 */\r
+#define RTC_TR_MNU_1 (0x2UL << RTC_TR_MNU_Pos) /*!< 0x00000200 */\r
+#define RTC_TR_MNU_2 (0x4UL << RTC_TR_MNU_Pos) /*!< 0x00000400 */\r
+#define RTC_TR_MNU_3 (0x8UL << RTC_TR_MNU_Pos) /*!< 0x00000800 */\r
+#define RTC_TR_ST_Pos (4U) \r
+#define RTC_TR_ST_Msk (0x7UL << RTC_TR_ST_Pos) /*!< 0x00000070 */\r
+#define RTC_TR_ST RTC_TR_ST_Msk \r
+#define RTC_TR_ST_0 (0x1UL << RTC_TR_ST_Pos) /*!< 0x00000010 */\r
+#define RTC_TR_ST_1 (0x2UL << RTC_TR_ST_Pos) /*!< 0x00000020 */\r
+#define RTC_TR_ST_2 (0x4UL << RTC_TR_ST_Pos) /*!< 0x00000040 */\r
+#define RTC_TR_SU_Pos (0U) \r
+#define RTC_TR_SU_Msk (0xFUL << RTC_TR_SU_Pos) /*!< 0x0000000F */\r
+#define RTC_TR_SU RTC_TR_SU_Msk \r
+#define RTC_TR_SU_0 (0x1UL << RTC_TR_SU_Pos) /*!< 0x00000001 */\r
+#define RTC_TR_SU_1 (0x2UL << RTC_TR_SU_Pos) /*!< 0x00000002 */\r
+#define RTC_TR_SU_2 (0x4UL << RTC_TR_SU_Pos) /*!< 0x00000004 */\r
+#define RTC_TR_SU_3 (0x8UL << RTC_TR_SU_Pos) /*!< 0x00000008 */\r
+\r
+/******************** Bits definition for RTC_DR register *******************/\r
+#define RTC_DR_YT_Pos (20U) \r
+#define RTC_DR_YT_Msk (0xFUL << RTC_DR_YT_Pos) /*!< 0x00F00000 */\r
+#define RTC_DR_YT RTC_DR_YT_Msk \r
+#define RTC_DR_YT_0 (0x1UL << RTC_DR_YT_Pos) /*!< 0x00100000 */\r
+#define RTC_DR_YT_1 (0x2UL << RTC_DR_YT_Pos) /*!< 0x00200000 */\r
+#define RTC_DR_YT_2 (0x4UL << RTC_DR_YT_Pos) /*!< 0x00400000 */\r
+#define RTC_DR_YT_3 (0x8UL << RTC_DR_YT_Pos) /*!< 0x00800000 */\r
+#define RTC_DR_YU_Pos (16U) \r
+#define RTC_DR_YU_Msk (0xFUL << RTC_DR_YU_Pos) /*!< 0x000F0000 */\r
+#define RTC_DR_YU RTC_DR_YU_Msk \r
+#define RTC_DR_YU_0 (0x1UL << RTC_DR_YU_Pos) /*!< 0x00010000 */\r
+#define RTC_DR_YU_1 (0x2UL << RTC_DR_YU_Pos) /*!< 0x00020000 */\r
+#define RTC_DR_YU_2 (0x4UL << RTC_DR_YU_Pos) /*!< 0x00040000 */\r
+#define RTC_DR_YU_3 (0x8UL << RTC_DR_YU_Pos) /*!< 0x00080000 */\r
+#define RTC_DR_WDU_Pos (13U) \r
+#define RTC_DR_WDU_Msk (0x7UL << RTC_DR_WDU_Pos) /*!< 0x0000E000 */\r
+#define RTC_DR_WDU RTC_DR_WDU_Msk \r
+#define RTC_DR_WDU_0 (0x1UL << RTC_DR_WDU_Pos) /*!< 0x00002000 */\r
+#define RTC_DR_WDU_1 (0x2UL << RTC_DR_WDU_Pos) /*!< 0x00004000 */\r
+#define RTC_DR_WDU_2 (0x4UL << RTC_DR_WDU_Pos) /*!< 0x00008000 */\r
+#define RTC_DR_MT_Pos (12U) \r
+#define RTC_DR_MT_Msk (0x1UL << RTC_DR_MT_Pos) /*!< 0x00001000 */\r
+#define RTC_DR_MT RTC_DR_MT_Msk \r
+#define RTC_DR_MU_Pos (8U) \r
+#define RTC_DR_MU_Msk (0xFUL << RTC_DR_MU_Pos) /*!< 0x00000F00 */\r
+#define RTC_DR_MU RTC_DR_MU_Msk \r
+#define RTC_DR_MU_0 (0x1UL << RTC_DR_MU_Pos) /*!< 0x00000100 */\r
+#define RTC_DR_MU_1 (0x2UL << RTC_DR_MU_Pos) /*!< 0x00000200 */\r
+#define RTC_DR_MU_2 (0x4UL << RTC_DR_MU_Pos) /*!< 0x00000400 */\r
+#define RTC_DR_MU_3 (0x8UL << RTC_DR_MU_Pos) /*!< 0x00000800 */\r
+#define RTC_DR_DT_Pos (4U) \r
+#define RTC_DR_DT_Msk (0x3UL << RTC_DR_DT_Pos) /*!< 0x00000030 */\r
+#define RTC_DR_DT RTC_DR_DT_Msk \r
+#define RTC_DR_DT_0 (0x1UL << RTC_DR_DT_Pos) /*!< 0x00000010 */\r
+#define RTC_DR_DT_1 (0x2UL << RTC_DR_DT_Pos) /*!< 0x00000020 */\r
+#define RTC_DR_DU_Pos (0U) \r
+#define RTC_DR_DU_Msk (0xFUL << RTC_DR_DU_Pos) /*!< 0x0000000F */\r
+#define RTC_DR_DU RTC_DR_DU_Msk \r
+#define RTC_DR_DU_0 (0x1UL << RTC_DR_DU_Pos) /*!< 0x00000001 */\r
+#define RTC_DR_DU_1 (0x2UL << RTC_DR_DU_Pos) /*!< 0x00000002 */\r
+#define RTC_DR_DU_2 (0x4UL << RTC_DR_DU_Pos) /*!< 0x00000004 */\r
+#define RTC_DR_DU_3 (0x8UL << RTC_DR_DU_Pos) /*!< 0x00000008 */\r
+\r
+/******************** Bits definition for RTC_CR register *******************/\r
+#define RTC_CR_COE_Pos (23U) \r
+#define RTC_CR_COE_Msk (0x1UL << RTC_CR_COE_Pos) /*!< 0x00800000 */\r
+#define RTC_CR_COE RTC_CR_COE_Msk \r
+#define RTC_CR_OSEL_Pos (21U) \r
+#define RTC_CR_OSEL_Msk (0x3UL << RTC_CR_OSEL_Pos) /*!< 0x00600000 */\r
+#define RTC_CR_OSEL RTC_CR_OSEL_Msk \r
+#define RTC_CR_OSEL_0 (0x1UL << RTC_CR_OSEL_Pos) /*!< 0x00200000 */\r
+#define RTC_CR_OSEL_1 (0x2UL << RTC_CR_OSEL_Pos) /*!< 0x00400000 */\r
+#define RTC_CR_POL_Pos (20U) \r
+#define RTC_CR_POL_Msk (0x1UL << RTC_CR_POL_Pos) /*!< 0x00100000 */\r
+#define RTC_CR_POL RTC_CR_POL_Msk \r
+#define RTC_CR_COSEL_Pos (19U) \r
+#define RTC_CR_COSEL_Msk (0x1UL << RTC_CR_COSEL_Pos) /*!< 0x00080000 */\r
+#define RTC_CR_COSEL RTC_CR_COSEL_Msk \r
+#define RTC_CR_BKP_Pos (18U) \r
+#define RTC_CR_BKP_Msk (0x1UL << RTC_CR_BKP_Pos) /*!< 0x00040000 */\r
+#define RTC_CR_BKP RTC_CR_BKP_Msk \r
+#define RTC_CR_SUB1H_Pos (17U) \r
+#define RTC_CR_SUB1H_Msk (0x1UL << RTC_CR_SUB1H_Pos) /*!< 0x00020000 */\r
+#define RTC_CR_SUB1H RTC_CR_SUB1H_Msk \r
+#define RTC_CR_ADD1H_Pos (16U) \r
+#define RTC_CR_ADD1H_Msk (0x1UL << RTC_CR_ADD1H_Pos) /*!< 0x00010000 */\r
+#define RTC_CR_ADD1H RTC_CR_ADD1H_Msk \r
+#define RTC_CR_TSIE_Pos (15U) \r
+#define RTC_CR_TSIE_Msk (0x1UL << RTC_CR_TSIE_Pos) /*!< 0x00008000 */\r
+#define RTC_CR_TSIE RTC_CR_TSIE_Msk \r
+#define RTC_CR_WUTIE_Pos (14U) \r
+#define RTC_CR_WUTIE_Msk (0x1UL << RTC_CR_WUTIE_Pos) /*!< 0x00004000 */\r
+#define RTC_CR_WUTIE RTC_CR_WUTIE_Msk \r
+#define RTC_CR_ALRBIE_Pos (13U) \r
+#define RTC_CR_ALRBIE_Msk (0x1UL << RTC_CR_ALRBIE_Pos) /*!< 0x00002000 */\r
+#define RTC_CR_ALRBIE RTC_CR_ALRBIE_Msk \r
+#define RTC_CR_ALRAIE_Pos (12U) \r
+#define RTC_CR_ALRAIE_Msk (0x1UL << RTC_CR_ALRAIE_Pos) /*!< 0x00001000 */\r
+#define RTC_CR_ALRAIE RTC_CR_ALRAIE_Msk \r
+#define RTC_CR_TSE_Pos (11U) \r
+#define RTC_CR_TSE_Msk (0x1UL << RTC_CR_TSE_Pos) /*!< 0x00000800 */\r
+#define RTC_CR_TSE RTC_CR_TSE_Msk \r
+#define RTC_CR_WUTE_Pos (10U) \r
+#define RTC_CR_WUTE_Msk (0x1UL << RTC_CR_WUTE_Pos) /*!< 0x00000400 */\r
+#define RTC_CR_WUTE RTC_CR_WUTE_Msk \r
+#define RTC_CR_ALRBE_Pos (9U) \r
+#define RTC_CR_ALRBE_Msk (0x1UL << RTC_CR_ALRBE_Pos) /*!< 0x00000200 */\r
+#define RTC_CR_ALRBE RTC_CR_ALRBE_Msk \r
+#define RTC_CR_ALRAE_Pos (8U) \r
+#define RTC_CR_ALRAE_Msk (0x1UL << RTC_CR_ALRAE_Pos) /*!< 0x00000100 */\r
+#define RTC_CR_ALRAE RTC_CR_ALRAE_Msk \r
+#define RTC_CR_DCE_Pos (7U) \r
+#define RTC_CR_DCE_Msk (0x1UL << RTC_CR_DCE_Pos) /*!< 0x00000080 */\r
+#define RTC_CR_DCE RTC_CR_DCE_Msk \r
+#define RTC_CR_FMT_Pos (6U) \r
+#define RTC_CR_FMT_Msk (0x1UL << RTC_CR_FMT_Pos) /*!< 0x00000040 */\r
+#define RTC_CR_FMT RTC_CR_FMT_Msk \r
+#define RTC_CR_BYPSHAD_Pos (5U) \r
+#define RTC_CR_BYPSHAD_Msk (0x1UL << RTC_CR_BYPSHAD_Pos) /*!< 0x00000020 */\r
+#define RTC_CR_BYPSHAD RTC_CR_BYPSHAD_Msk \r
+#define RTC_CR_REFCKON_Pos (4U) \r
+#define RTC_CR_REFCKON_Msk (0x1UL << RTC_CR_REFCKON_Pos) /*!< 0x00000010 */\r
+#define RTC_CR_REFCKON RTC_CR_REFCKON_Msk \r
+#define RTC_CR_TSEDGE_Pos (3U) \r
+#define RTC_CR_TSEDGE_Msk (0x1UL << RTC_CR_TSEDGE_Pos) /*!< 0x00000008 */\r
+#define RTC_CR_TSEDGE RTC_CR_TSEDGE_Msk \r
+#define RTC_CR_WUCKSEL_Pos (0U) \r
+#define RTC_CR_WUCKSEL_Msk (0x7UL << RTC_CR_WUCKSEL_Pos) /*!< 0x00000007 */\r
+#define RTC_CR_WUCKSEL RTC_CR_WUCKSEL_Msk \r
+#define RTC_CR_WUCKSEL_0 (0x1UL << RTC_CR_WUCKSEL_Pos) /*!< 0x00000001 */\r
+#define RTC_CR_WUCKSEL_1 (0x2UL << RTC_CR_WUCKSEL_Pos) /*!< 0x00000002 */\r
+#define RTC_CR_WUCKSEL_2 (0x4UL << RTC_CR_WUCKSEL_Pos) /*!< 0x00000004 */\r
+\r
+/* Legacy defines */\r
+#define RTC_CR_BCK_Pos RTC_CR_BKP_Pos\r
+#define RTC_CR_BCK_Msk RTC_CR_BKP_Msk\r
+#define RTC_CR_BCK RTC_CR_BKP\r
+\r
+/******************** Bits definition for RTC_ISR register ******************/\r
+#define RTC_ISR_RECALPF_Pos (16U) \r
+#define RTC_ISR_RECALPF_Msk (0x1UL << RTC_ISR_RECALPF_Pos) /*!< 0x00010000 */\r
+#define RTC_ISR_RECALPF RTC_ISR_RECALPF_Msk \r
+#define RTC_ISR_TAMP3F_Pos (15U) \r
+#define RTC_ISR_TAMP3F_Msk (0x1UL << RTC_ISR_TAMP3F_Pos) /*!< 0x00008000 */\r
+#define RTC_ISR_TAMP3F RTC_ISR_TAMP3F_Msk \r
+#define RTC_ISR_TAMP2F_Pos (14U) \r
+#define RTC_ISR_TAMP2F_Msk (0x1UL << RTC_ISR_TAMP2F_Pos) /*!< 0x00004000 */\r
+#define RTC_ISR_TAMP2F RTC_ISR_TAMP2F_Msk \r
+#define RTC_ISR_TAMP1F_Pos (13U) \r
+#define RTC_ISR_TAMP1F_Msk (0x1UL << RTC_ISR_TAMP1F_Pos) /*!< 0x00002000 */\r
+#define RTC_ISR_TAMP1F RTC_ISR_TAMP1F_Msk \r
+#define RTC_ISR_TSOVF_Pos (12U) \r
+#define RTC_ISR_TSOVF_Msk (0x1UL << RTC_ISR_TSOVF_Pos) /*!< 0x00001000 */\r
+#define RTC_ISR_TSOVF RTC_ISR_TSOVF_Msk \r
+#define RTC_ISR_TSF_Pos (11U) \r
+#define RTC_ISR_TSF_Msk (0x1UL << RTC_ISR_TSF_Pos) /*!< 0x00000800 */\r
+#define RTC_ISR_TSF RTC_ISR_TSF_Msk \r
+#define RTC_ISR_WUTF_Pos (10U) \r
+#define RTC_ISR_WUTF_Msk (0x1UL << RTC_ISR_WUTF_Pos) /*!< 0x00000400 */\r
+#define RTC_ISR_WUTF RTC_ISR_WUTF_Msk \r
+#define RTC_ISR_ALRBF_Pos (9U) \r
+#define RTC_ISR_ALRBF_Msk (0x1UL << RTC_ISR_ALRBF_Pos) /*!< 0x00000200 */\r
+#define RTC_ISR_ALRBF RTC_ISR_ALRBF_Msk \r
+#define RTC_ISR_ALRAF_Pos (8U) \r
+#define RTC_ISR_ALRAF_Msk (0x1UL << RTC_ISR_ALRAF_Pos) /*!< 0x00000100 */\r
+#define RTC_ISR_ALRAF RTC_ISR_ALRAF_Msk \r
+#define RTC_ISR_INIT_Pos (7U) \r
+#define RTC_ISR_INIT_Msk (0x1UL << RTC_ISR_INIT_Pos) /*!< 0x00000080 */\r
+#define RTC_ISR_INIT RTC_ISR_INIT_Msk \r
+#define RTC_ISR_INITF_Pos (6U) \r
+#define RTC_ISR_INITF_Msk (0x1UL << RTC_ISR_INITF_Pos) /*!< 0x00000040 */\r
+#define RTC_ISR_INITF RTC_ISR_INITF_Msk \r
+#define RTC_ISR_RSF_Pos (5U) \r
+#define RTC_ISR_RSF_Msk (0x1UL << RTC_ISR_RSF_Pos) /*!< 0x00000020 */\r
+#define RTC_ISR_RSF RTC_ISR_RSF_Msk \r
+#define RTC_ISR_INITS_Pos (4U) \r
+#define RTC_ISR_INITS_Msk (0x1UL << RTC_ISR_INITS_Pos) /*!< 0x00000010 */\r
+#define RTC_ISR_INITS RTC_ISR_INITS_Msk \r
+#define RTC_ISR_SHPF_Pos (3U) \r
+#define RTC_ISR_SHPF_Msk (0x1UL << RTC_ISR_SHPF_Pos) /*!< 0x00000008 */\r
+#define RTC_ISR_SHPF RTC_ISR_SHPF_Msk \r
+#define RTC_ISR_WUTWF_Pos (2U) \r
+#define RTC_ISR_WUTWF_Msk (0x1UL << RTC_ISR_WUTWF_Pos) /*!< 0x00000004 */\r
+#define RTC_ISR_WUTWF RTC_ISR_WUTWF_Msk \r
+#define RTC_ISR_ALRBWF_Pos (1U) \r
+#define RTC_ISR_ALRBWF_Msk (0x1UL << RTC_ISR_ALRBWF_Pos) /*!< 0x00000002 */\r
+#define RTC_ISR_ALRBWF RTC_ISR_ALRBWF_Msk \r
+#define RTC_ISR_ALRAWF_Pos (0U) \r
+#define RTC_ISR_ALRAWF_Msk (0x1UL << RTC_ISR_ALRAWF_Pos) /*!< 0x00000001 */\r
+#define RTC_ISR_ALRAWF RTC_ISR_ALRAWF_Msk \r
+\r
+/******************** Bits definition for RTC_PRER register *****************/\r
+#define RTC_PRER_PREDIV_A_Pos (16U) \r
+#define RTC_PRER_PREDIV_A_Msk (0x7FUL << RTC_PRER_PREDIV_A_Pos) /*!< 0x007F0000 */\r
+#define RTC_PRER_PREDIV_A RTC_PRER_PREDIV_A_Msk \r
+#define RTC_PRER_PREDIV_S_Pos (0U) \r
+#define RTC_PRER_PREDIV_S_Msk (0x7FFFUL << RTC_PRER_PREDIV_S_Pos) /*!< 0x00007FFF */\r
+#define RTC_PRER_PREDIV_S RTC_PRER_PREDIV_S_Msk \r
+\r
+/******************** Bits definition for RTC_WUTR register *****************/\r
+#define RTC_WUTR_WUT_Pos (0U) \r
+#define RTC_WUTR_WUT_Msk (0xFFFFUL << RTC_WUTR_WUT_Pos) /*!< 0x0000FFFF */\r
+#define RTC_WUTR_WUT RTC_WUTR_WUT_Msk \r
+\r
+/******************** Bits definition for RTC_CALIBR register ***************/\r
+#define RTC_CALIBR_DCS_Pos (7U) \r
+#define RTC_CALIBR_DCS_Msk (0x1UL << RTC_CALIBR_DCS_Pos) /*!< 0x00000080 */\r
+#define RTC_CALIBR_DCS RTC_CALIBR_DCS_Msk \r
+#define RTC_CALIBR_DC_Pos (0U) \r
+#define RTC_CALIBR_DC_Msk (0x1FUL << RTC_CALIBR_DC_Pos) /*!< 0x0000001F */\r
+#define RTC_CALIBR_DC RTC_CALIBR_DC_Msk \r
+\r
+/******************** Bits definition for RTC_ALRMAR register ***************/\r
+#define RTC_ALRMAR_MSK4_Pos (31U) \r
+#define RTC_ALRMAR_MSK4_Msk (0x1UL << RTC_ALRMAR_MSK4_Pos) /*!< 0x80000000 */\r
+#define RTC_ALRMAR_MSK4 RTC_ALRMAR_MSK4_Msk \r
+#define RTC_ALRMAR_WDSEL_Pos (30U) \r
+#define RTC_ALRMAR_WDSEL_Msk (0x1UL << RTC_ALRMAR_WDSEL_Pos) /*!< 0x40000000 */\r
+#define RTC_ALRMAR_WDSEL RTC_ALRMAR_WDSEL_Msk \r
+#define RTC_ALRMAR_DT_Pos (28U) \r
+#define RTC_ALRMAR_DT_Msk (0x3UL << RTC_ALRMAR_DT_Pos) /*!< 0x30000000 */\r
+#define RTC_ALRMAR_DT RTC_ALRMAR_DT_Msk \r
+#define RTC_ALRMAR_DT_0 (0x1UL << RTC_ALRMAR_DT_Pos) /*!< 0x10000000 */\r
+#define RTC_ALRMAR_DT_1 (0x2UL << RTC_ALRMAR_DT_Pos) /*!< 0x20000000 */\r
+#define RTC_ALRMAR_DU_Pos (24U) \r
+#define RTC_ALRMAR_DU_Msk (0xFUL << RTC_ALRMAR_DU_Pos) /*!< 0x0F000000 */\r
+#define RTC_ALRMAR_DU RTC_ALRMAR_DU_Msk \r
+#define RTC_ALRMAR_DU_0 (0x1UL << RTC_ALRMAR_DU_Pos) /*!< 0x01000000 */\r
+#define RTC_ALRMAR_DU_1 (0x2UL << RTC_ALRMAR_DU_Pos) /*!< 0x02000000 */\r
+#define RTC_ALRMAR_DU_2 (0x4UL << RTC_ALRMAR_DU_Pos) /*!< 0x04000000 */\r
+#define RTC_ALRMAR_DU_3 (0x8UL << RTC_ALRMAR_DU_Pos) /*!< 0x08000000 */\r
+#define RTC_ALRMAR_MSK3_Pos (23U) \r
+#define RTC_ALRMAR_MSK3_Msk (0x1UL << RTC_ALRMAR_MSK3_Pos) /*!< 0x00800000 */\r
+#define RTC_ALRMAR_MSK3 RTC_ALRMAR_MSK3_Msk \r
+#define RTC_ALRMAR_PM_Pos (22U) \r
+#define RTC_ALRMAR_PM_Msk (0x1UL << RTC_ALRMAR_PM_Pos) /*!< 0x00400000 */\r
+#define RTC_ALRMAR_PM RTC_ALRMAR_PM_Msk \r
+#define RTC_ALRMAR_HT_Pos (20U) \r
+#define RTC_ALRMAR_HT_Msk (0x3UL << RTC_ALRMAR_HT_Pos) /*!< 0x00300000 */\r
+#define RTC_ALRMAR_HT RTC_ALRMAR_HT_Msk \r
+#define RTC_ALRMAR_HT_0 (0x1UL << RTC_ALRMAR_HT_Pos) /*!< 0x00100000 */\r
+#define RTC_ALRMAR_HT_1 (0x2UL << RTC_ALRMAR_HT_Pos) /*!< 0x00200000 */\r
+#define RTC_ALRMAR_HU_Pos (16U) \r
+#define RTC_ALRMAR_HU_Msk (0xFUL << RTC_ALRMAR_HU_Pos) /*!< 0x000F0000 */\r
+#define RTC_ALRMAR_HU RTC_ALRMAR_HU_Msk \r
+#define RTC_ALRMAR_HU_0 (0x1UL << RTC_ALRMAR_HU_Pos) /*!< 0x00010000 */\r
+#define RTC_ALRMAR_HU_1 (0x2UL << RTC_ALRMAR_HU_Pos) /*!< 0x00020000 */\r
+#define RTC_ALRMAR_HU_2 (0x4UL << RTC_ALRMAR_HU_Pos) /*!< 0x00040000 */\r
+#define RTC_ALRMAR_HU_3 (0x8UL << RTC_ALRMAR_HU_Pos) /*!< 0x00080000 */\r
+#define RTC_ALRMAR_MSK2_Pos (15U) \r
+#define RTC_ALRMAR_MSK2_Msk (0x1UL << RTC_ALRMAR_MSK2_Pos) /*!< 0x00008000 */\r
+#define RTC_ALRMAR_MSK2 RTC_ALRMAR_MSK2_Msk \r
+#define RTC_ALRMAR_MNT_Pos (12U) \r
+#define RTC_ALRMAR_MNT_Msk (0x7UL << RTC_ALRMAR_MNT_Pos) /*!< 0x00007000 */\r
+#define RTC_ALRMAR_MNT RTC_ALRMAR_MNT_Msk \r
+#define RTC_ALRMAR_MNT_0 (0x1UL << RTC_ALRMAR_MNT_Pos) /*!< 0x00001000 */\r
+#define RTC_ALRMAR_MNT_1 (0x2UL << RTC_ALRMAR_MNT_Pos) /*!< 0x00002000 */\r
+#define RTC_ALRMAR_MNT_2 (0x4UL << RTC_ALRMAR_MNT_Pos) /*!< 0x00004000 */\r
+#define RTC_ALRMAR_MNU_Pos (8U) \r
+#define RTC_ALRMAR_MNU_Msk (0xFUL << RTC_ALRMAR_MNU_Pos) /*!< 0x00000F00 */\r
+#define RTC_ALRMAR_MNU RTC_ALRMAR_MNU_Msk \r
+#define RTC_ALRMAR_MNU_0 (0x1UL << RTC_ALRMAR_MNU_Pos) /*!< 0x00000100 */\r
+#define RTC_ALRMAR_MNU_1 (0x2UL << RTC_ALRMAR_MNU_Pos) /*!< 0x00000200 */\r
+#define RTC_ALRMAR_MNU_2 (0x4UL << RTC_ALRMAR_MNU_Pos) /*!< 0x00000400 */\r
+#define RTC_ALRMAR_MNU_3 (0x8UL << RTC_ALRMAR_MNU_Pos) /*!< 0x00000800 */\r
+#define RTC_ALRMAR_MSK1_Pos (7U) \r
+#define RTC_ALRMAR_MSK1_Msk (0x1UL << RTC_ALRMAR_MSK1_Pos) /*!< 0x00000080 */\r
+#define RTC_ALRMAR_MSK1 RTC_ALRMAR_MSK1_Msk \r
+#define RTC_ALRMAR_ST_Pos (4U) \r
+#define RTC_ALRMAR_ST_Msk (0x7UL << RTC_ALRMAR_ST_Pos) /*!< 0x00000070 */\r
+#define RTC_ALRMAR_ST RTC_ALRMAR_ST_Msk \r
+#define RTC_ALRMAR_ST_0 (0x1UL << RTC_ALRMAR_ST_Pos) /*!< 0x00000010 */\r
+#define RTC_ALRMAR_ST_1 (0x2UL << RTC_ALRMAR_ST_Pos) /*!< 0x00000020 */\r
+#define RTC_ALRMAR_ST_2 (0x4UL << RTC_ALRMAR_ST_Pos) /*!< 0x00000040 */\r
+#define RTC_ALRMAR_SU_Pos (0U) \r
+#define RTC_ALRMAR_SU_Msk (0xFUL << RTC_ALRMAR_SU_Pos) /*!< 0x0000000F */\r
+#define RTC_ALRMAR_SU RTC_ALRMAR_SU_Msk \r
+#define RTC_ALRMAR_SU_0 (0x1UL << RTC_ALRMAR_SU_Pos) /*!< 0x00000001 */\r
+#define RTC_ALRMAR_SU_1 (0x2UL << RTC_ALRMAR_SU_Pos) /*!< 0x00000002 */\r
+#define RTC_ALRMAR_SU_2 (0x4UL << RTC_ALRMAR_SU_Pos) /*!< 0x00000004 */\r
+#define RTC_ALRMAR_SU_3 (0x8UL << RTC_ALRMAR_SU_Pos) /*!< 0x00000008 */\r
+\r
+/******************** Bits definition for RTC_ALRMBR register ***************/\r
+#define RTC_ALRMBR_MSK4_Pos (31U) \r
+#define RTC_ALRMBR_MSK4_Msk (0x1UL << RTC_ALRMBR_MSK4_Pos) /*!< 0x80000000 */\r
+#define RTC_ALRMBR_MSK4 RTC_ALRMBR_MSK4_Msk \r
+#define RTC_ALRMBR_WDSEL_Pos (30U) \r
+#define RTC_ALRMBR_WDSEL_Msk (0x1UL << RTC_ALRMBR_WDSEL_Pos) /*!< 0x40000000 */\r
+#define RTC_ALRMBR_WDSEL RTC_ALRMBR_WDSEL_Msk \r
+#define RTC_ALRMBR_DT_Pos (28U) \r
+#define RTC_ALRMBR_DT_Msk (0x3UL << RTC_ALRMBR_DT_Pos) /*!< 0x30000000 */\r
+#define RTC_ALRMBR_DT RTC_ALRMBR_DT_Msk \r
+#define RTC_ALRMBR_DT_0 (0x1UL << RTC_ALRMBR_DT_Pos) /*!< 0x10000000 */\r
+#define RTC_ALRMBR_DT_1 (0x2UL << RTC_ALRMBR_DT_Pos) /*!< 0x20000000 */\r
+#define RTC_ALRMBR_DU_Pos (24U) \r
+#define RTC_ALRMBR_DU_Msk (0xFUL << RTC_ALRMBR_DU_Pos) /*!< 0x0F000000 */\r
+#define RTC_ALRMBR_DU RTC_ALRMBR_DU_Msk \r
+#define RTC_ALRMBR_DU_0 (0x1UL << RTC_ALRMBR_DU_Pos) /*!< 0x01000000 */\r
+#define RTC_ALRMBR_DU_1 (0x2UL << RTC_ALRMBR_DU_Pos) /*!< 0x02000000 */\r
+#define RTC_ALRMBR_DU_2 (0x4UL << RTC_ALRMBR_DU_Pos) /*!< 0x04000000 */\r
+#define RTC_ALRMBR_DU_3 (0x8UL << RTC_ALRMBR_DU_Pos) /*!< 0x08000000 */\r
+#define RTC_ALRMBR_MSK3_Pos (23U) \r
+#define RTC_ALRMBR_MSK3_Msk (0x1UL << RTC_ALRMBR_MSK3_Pos) /*!< 0x00800000 */\r
+#define RTC_ALRMBR_MSK3 RTC_ALRMBR_MSK3_Msk \r
+#define RTC_ALRMBR_PM_Pos (22U) \r
+#define RTC_ALRMBR_PM_Msk (0x1UL << RTC_ALRMBR_PM_Pos) /*!< 0x00400000 */\r
+#define RTC_ALRMBR_PM RTC_ALRMBR_PM_Msk \r
+#define RTC_ALRMBR_HT_Pos (20U) \r
+#define RTC_ALRMBR_HT_Msk (0x3UL << RTC_ALRMBR_HT_Pos) /*!< 0x00300000 */\r
+#define RTC_ALRMBR_HT RTC_ALRMBR_HT_Msk \r
+#define RTC_ALRMBR_HT_0 (0x1UL << RTC_ALRMBR_HT_Pos) /*!< 0x00100000 */\r
+#define RTC_ALRMBR_HT_1 (0x2UL << RTC_ALRMBR_HT_Pos) /*!< 0x00200000 */\r
+#define RTC_ALRMBR_HU_Pos (16U) \r
+#define RTC_ALRMBR_HU_Msk (0xFUL << RTC_ALRMBR_HU_Pos) /*!< 0x000F0000 */\r
+#define RTC_ALRMBR_HU RTC_ALRMBR_HU_Msk \r
+#define RTC_ALRMBR_HU_0 (0x1UL << RTC_ALRMBR_HU_Pos) /*!< 0x00010000 */\r
+#define RTC_ALRMBR_HU_1 (0x2UL << RTC_ALRMBR_HU_Pos) /*!< 0x00020000 */\r
+#define RTC_ALRMBR_HU_2 (0x4UL << RTC_ALRMBR_HU_Pos) /*!< 0x00040000 */\r
+#define RTC_ALRMBR_HU_3 (0x8UL << RTC_ALRMBR_HU_Pos) /*!< 0x00080000 */\r
+#define RTC_ALRMBR_MSK2_Pos (15U) \r
+#define RTC_ALRMBR_MSK2_Msk (0x1UL << RTC_ALRMBR_MSK2_Pos) /*!< 0x00008000 */\r
+#define RTC_ALRMBR_MSK2 RTC_ALRMBR_MSK2_Msk \r
+#define RTC_ALRMBR_MNT_Pos (12U) \r
+#define RTC_ALRMBR_MNT_Msk (0x7UL << RTC_ALRMBR_MNT_Pos) /*!< 0x00007000 */\r
+#define RTC_ALRMBR_MNT RTC_ALRMBR_MNT_Msk \r
+#define RTC_ALRMBR_MNT_0 (0x1UL << RTC_ALRMBR_MNT_Pos) /*!< 0x00001000 */\r
+#define RTC_ALRMBR_MNT_1 (0x2UL << RTC_ALRMBR_MNT_Pos) /*!< 0x00002000 */\r
+#define RTC_ALRMBR_MNT_2 (0x4UL << RTC_ALRMBR_MNT_Pos) /*!< 0x00004000 */\r
+#define RTC_ALRMBR_MNU_Pos (8U) \r
+#define RTC_ALRMBR_MNU_Msk (0xFUL << RTC_ALRMBR_MNU_Pos) /*!< 0x00000F00 */\r
+#define RTC_ALRMBR_MNU RTC_ALRMBR_MNU_Msk \r
+#define RTC_ALRMBR_MNU_0 (0x1UL << RTC_ALRMBR_MNU_Pos) /*!< 0x00000100 */\r
+#define RTC_ALRMBR_MNU_1 (0x2UL << RTC_ALRMBR_MNU_Pos) /*!< 0x00000200 */\r
+#define RTC_ALRMBR_MNU_2 (0x4UL << RTC_ALRMBR_MNU_Pos) /*!< 0x00000400 */\r
+#define RTC_ALRMBR_MNU_3 (0x8UL << RTC_ALRMBR_MNU_Pos) /*!< 0x00000800 */\r
+#define RTC_ALRMBR_MSK1_Pos (7U) \r
+#define RTC_ALRMBR_MSK1_Msk (0x1UL << RTC_ALRMBR_MSK1_Pos) /*!< 0x00000080 */\r
+#define RTC_ALRMBR_MSK1 RTC_ALRMBR_MSK1_Msk \r
+#define RTC_ALRMBR_ST_Pos (4U) \r
+#define RTC_ALRMBR_ST_Msk (0x7UL << RTC_ALRMBR_ST_Pos) /*!< 0x00000070 */\r
+#define RTC_ALRMBR_ST RTC_ALRMBR_ST_Msk \r
+#define RTC_ALRMBR_ST_0 (0x1UL << RTC_ALRMBR_ST_Pos) /*!< 0x00000010 */\r
+#define RTC_ALRMBR_ST_1 (0x2UL << RTC_ALRMBR_ST_Pos) /*!< 0x00000020 */\r
+#define RTC_ALRMBR_ST_2 (0x4UL << RTC_ALRMBR_ST_Pos) /*!< 0x00000040 */\r
+#define RTC_ALRMBR_SU_Pos (0U) \r
+#define RTC_ALRMBR_SU_Msk (0xFUL << RTC_ALRMBR_SU_Pos) /*!< 0x0000000F */\r
+#define RTC_ALRMBR_SU RTC_ALRMBR_SU_Msk \r
+#define RTC_ALRMBR_SU_0 (0x1UL << RTC_ALRMBR_SU_Pos) /*!< 0x00000001 */\r
+#define RTC_ALRMBR_SU_1 (0x2UL << RTC_ALRMBR_SU_Pos) /*!< 0x00000002 */\r
+#define RTC_ALRMBR_SU_2 (0x4UL << RTC_ALRMBR_SU_Pos) /*!< 0x00000004 */\r
+#define RTC_ALRMBR_SU_3 (0x8UL << RTC_ALRMBR_SU_Pos) /*!< 0x00000008 */\r
+\r
+/******************** Bits definition for RTC_WPR register ******************/\r
+#define RTC_WPR_KEY_Pos (0U) \r
+#define RTC_WPR_KEY_Msk (0xFFUL << RTC_WPR_KEY_Pos) /*!< 0x000000FF */\r
+#define RTC_WPR_KEY RTC_WPR_KEY_Msk \r
+\r
+/******************** Bits definition for RTC_SSR register ******************/\r
+#define RTC_SSR_SS_Pos (0U) \r
+#define RTC_SSR_SS_Msk (0xFFFFUL << RTC_SSR_SS_Pos) /*!< 0x0000FFFF */\r
+#define RTC_SSR_SS RTC_SSR_SS_Msk \r
+\r
+/******************** Bits definition for RTC_SHIFTR register ***************/\r
+#define RTC_SHIFTR_SUBFS_Pos (0U) \r
+#define RTC_SHIFTR_SUBFS_Msk (0x7FFFUL << RTC_SHIFTR_SUBFS_Pos) /*!< 0x00007FFF */\r
+#define RTC_SHIFTR_SUBFS RTC_SHIFTR_SUBFS_Msk \r
+#define RTC_SHIFTR_ADD1S_Pos (31U) \r
+#define RTC_SHIFTR_ADD1S_Msk (0x1UL << RTC_SHIFTR_ADD1S_Pos) /*!< 0x80000000 */\r
+#define RTC_SHIFTR_ADD1S RTC_SHIFTR_ADD1S_Msk \r
+\r
+/******************** Bits definition for RTC_TSTR register *****************/\r
+#define RTC_TSTR_PM_Pos (22U) \r
+#define RTC_TSTR_PM_Msk (0x1UL << RTC_TSTR_PM_Pos) /*!< 0x00400000 */\r
+#define RTC_TSTR_PM RTC_TSTR_PM_Msk \r
+#define RTC_TSTR_HT_Pos (20U) \r
+#define RTC_TSTR_HT_Msk (0x3UL << RTC_TSTR_HT_Pos) /*!< 0x00300000 */\r
+#define RTC_TSTR_HT RTC_TSTR_HT_Msk \r
+#define RTC_TSTR_HT_0 (0x1UL << RTC_TSTR_HT_Pos) /*!< 0x00100000 */\r
+#define RTC_TSTR_HT_1 (0x2UL << RTC_TSTR_HT_Pos) /*!< 0x00200000 */\r
+#define RTC_TSTR_HU_Pos (16U) \r
+#define RTC_TSTR_HU_Msk (0xFUL << RTC_TSTR_HU_Pos) /*!< 0x000F0000 */\r
+#define RTC_TSTR_HU RTC_TSTR_HU_Msk \r
+#define RTC_TSTR_HU_0 (0x1UL << RTC_TSTR_HU_Pos) /*!< 0x00010000 */\r
+#define RTC_TSTR_HU_1 (0x2UL << RTC_TSTR_HU_Pos) /*!< 0x00020000 */\r
+#define RTC_TSTR_HU_2 (0x4UL << RTC_TSTR_HU_Pos) /*!< 0x00040000 */\r
+#define RTC_TSTR_HU_3 (0x8UL << RTC_TSTR_HU_Pos) /*!< 0x00080000 */\r
+#define RTC_TSTR_MNT_Pos (12U) \r
+#define RTC_TSTR_MNT_Msk (0x7UL << RTC_TSTR_MNT_Pos) /*!< 0x00007000 */\r
+#define RTC_TSTR_MNT RTC_TSTR_MNT_Msk \r
+#define RTC_TSTR_MNT_0 (0x1UL << RTC_TSTR_MNT_Pos) /*!< 0x00001000 */\r
+#define RTC_TSTR_MNT_1 (0x2UL << RTC_TSTR_MNT_Pos) /*!< 0x00002000 */\r
+#define RTC_TSTR_MNT_2 (0x4UL << RTC_TSTR_MNT_Pos) /*!< 0x00004000 */\r
+#define RTC_TSTR_MNU_Pos (8U) \r
+#define RTC_TSTR_MNU_Msk (0xFUL << RTC_TSTR_MNU_Pos) /*!< 0x00000F00 */\r
+#define RTC_TSTR_MNU RTC_TSTR_MNU_Msk \r
+#define RTC_TSTR_MNU_0 (0x1UL << RTC_TSTR_MNU_Pos) /*!< 0x00000100 */\r
+#define RTC_TSTR_MNU_1 (0x2UL << RTC_TSTR_MNU_Pos) /*!< 0x00000200 */\r
+#define RTC_TSTR_MNU_2 (0x4UL << RTC_TSTR_MNU_Pos) /*!< 0x00000400 */\r
+#define RTC_TSTR_MNU_3 (0x8UL << RTC_TSTR_MNU_Pos) /*!< 0x00000800 */\r
+#define RTC_TSTR_ST_Pos (4U) \r
+#define RTC_TSTR_ST_Msk (0x7UL << RTC_TSTR_ST_Pos) /*!< 0x00000070 */\r
+#define RTC_TSTR_ST RTC_TSTR_ST_Msk \r
+#define RTC_TSTR_ST_0 (0x1UL << RTC_TSTR_ST_Pos) /*!< 0x00000010 */\r
+#define RTC_TSTR_ST_1 (0x2UL << RTC_TSTR_ST_Pos) /*!< 0x00000020 */\r
+#define RTC_TSTR_ST_2 (0x4UL << RTC_TSTR_ST_Pos) /*!< 0x00000040 */\r
+#define RTC_TSTR_SU_Pos (0U) \r
+#define RTC_TSTR_SU_Msk (0xFUL << RTC_TSTR_SU_Pos) /*!< 0x0000000F */\r
+#define RTC_TSTR_SU RTC_TSTR_SU_Msk \r
+#define RTC_TSTR_SU_0 (0x1UL << RTC_TSTR_SU_Pos) /*!< 0x00000001 */\r
+#define RTC_TSTR_SU_1 (0x2UL << RTC_TSTR_SU_Pos) /*!< 0x00000002 */\r
+#define RTC_TSTR_SU_2 (0x4UL << RTC_TSTR_SU_Pos) /*!< 0x00000004 */\r
+#define RTC_TSTR_SU_3 (0x8UL << RTC_TSTR_SU_Pos) /*!< 0x00000008 */\r
+\r
+/******************** Bits definition for RTC_TSDR register *****************/\r
+#define RTC_TSDR_WDU_Pos (13U) \r
+#define RTC_TSDR_WDU_Msk (0x7UL << RTC_TSDR_WDU_Pos) /*!< 0x0000E000 */\r
+#define RTC_TSDR_WDU RTC_TSDR_WDU_Msk \r
+#define RTC_TSDR_WDU_0 (0x1UL << RTC_TSDR_WDU_Pos) /*!< 0x00002000 */\r
+#define RTC_TSDR_WDU_1 (0x2UL << RTC_TSDR_WDU_Pos) /*!< 0x00004000 */\r
+#define RTC_TSDR_WDU_2 (0x4UL << RTC_TSDR_WDU_Pos) /*!< 0x00008000 */\r
+#define RTC_TSDR_MT_Pos (12U) \r
+#define RTC_TSDR_MT_Msk (0x1UL << RTC_TSDR_MT_Pos) /*!< 0x00001000 */\r
+#define RTC_TSDR_MT RTC_TSDR_MT_Msk \r
+#define RTC_TSDR_MU_Pos (8U) \r
+#define RTC_TSDR_MU_Msk (0xFUL << RTC_TSDR_MU_Pos) /*!< 0x00000F00 */\r
+#define RTC_TSDR_MU RTC_TSDR_MU_Msk \r
+#define RTC_TSDR_MU_0 (0x1UL << RTC_TSDR_MU_Pos) /*!< 0x00000100 */\r
+#define RTC_TSDR_MU_1 (0x2UL << RTC_TSDR_MU_Pos) /*!< 0x00000200 */\r
+#define RTC_TSDR_MU_2 (0x4UL << RTC_TSDR_MU_Pos) /*!< 0x00000400 */\r
+#define RTC_TSDR_MU_3 (0x8UL << RTC_TSDR_MU_Pos) /*!< 0x00000800 */\r
+#define RTC_TSDR_DT_Pos (4U) \r
+#define RTC_TSDR_DT_Msk (0x3UL << RTC_TSDR_DT_Pos) /*!< 0x00000030 */\r
+#define RTC_TSDR_DT RTC_TSDR_DT_Msk \r
+#define RTC_TSDR_DT_0 (0x1UL << RTC_TSDR_DT_Pos) /*!< 0x00000010 */\r
+#define RTC_TSDR_DT_1 (0x2UL << RTC_TSDR_DT_Pos) /*!< 0x00000020 */\r
+#define RTC_TSDR_DU_Pos (0U) \r
+#define RTC_TSDR_DU_Msk (0xFUL << RTC_TSDR_DU_Pos) /*!< 0x0000000F */\r
+#define RTC_TSDR_DU RTC_TSDR_DU_Msk \r
+#define RTC_TSDR_DU_0 (0x1UL << RTC_TSDR_DU_Pos) /*!< 0x00000001 */\r
+#define RTC_TSDR_DU_1 (0x2UL << RTC_TSDR_DU_Pos) /*!< 0x00000002 */\r
+#define RTC_TSDR_DU_2 (0x4UL << RTC_TSDR_DU_Pos) /*!< 0x00000004 */\r
+#define RTC_TSDR_DU_3 (0x8UL << RTC_TSDR_DU_Pos) /*!< 0x00000008 */\r
+\r
+/******************** Bits definition for RTC_TSSSR register ****************/\r
+#define RTC_TSSSR_SS_Pos (0U) \r
+#define RTC_TSSSR_SS_Msk (0xFFFFUL << RTC_TSSSR_SS_Pos) /*!< 0x0000FFFF */\r
+#define RTC_TSSSR_SS RTC_TSSSR_SS_Msk \r
+\r
+/******************** Bits definition for RTC_CAL register *****************/\r
+#define RTC_CALR_CALP_Pos (15U) \r
+#define RTC_CALR_CALP_Msk (0x1UL << RTC_CALR_CALP_Pos) /*!< 0x00008000 */\r
+#define RTC_CALR_CALP RTC_CALR_CALP_Msk \r
+#define RTC_CALR_CALW8_Pos (14U) \r
+#define RTC_CALR_CALW8_Msk (0x1UL << RTC_CALR_CALW8_Pos) /*!< 0x00004000 */\r
+#define RTC_CALR_CALW8 RTC_CALR_CALW8_Msk \r
+#define RTC_CALR_CALW16_Pos (13U) \r
+#define RTC_CALR_CALW16_Msk (0x1UL << RTC_CALR_CALW16_Pos) /*!< 0x00002000 */\r
+#define RTC_CALR_CALW16 RTC_CALR_CALW16_Msk \r
+#define RTC_CALR_CALM_Pos (0U) \r
+#define RTC_CALR_CALM_Msk (0x1FFUL << RTC_CALR_CALM_Pos) /*!< 0x000001FF */\r
+#define RTC_CALR_CALM RTC_CALR_CALM_Msk \r
+#define RTC_CALR_CALM_0 (0x001UL << RTC_CALR_CALM_Pos) /*!< 0x00000001 */\r
+#define RTC_CALR_CALM_1 (0x002UL << RTC_CALR_CALM_Pos) /*!< 0x00000002 */\r
+#define RTC_CALR_CALM_2 (0x004UL << RTC_CALR_CALM_Pos) /*!< 0x00000004 */\r
+#define RTC_CALR_CALM_3 (0x008UL << RTC_CALR_CALM_Pos) /*!< 0x00000008 */\r
+#define RTC_CALR_CALM_4 (0x010UL << RTC_CALR_CALM_Pos) /*!< 0x00000010 */\r
+#define RTC_CALR_CALM_5 (0x020UL << RTC_CALR_CALM_Pos) /*!< 0x00000020 */\r
+#define RTC_CALR_CALM_6 (0x040UL << RTC_CALR_CALM_Pos) /*!< 0x00000040 */\r
+#define RTC_CALR_CALM_7 (0x080UL << RTC_CALR_CALM_Pos) /*!< 0x00000080 */\r
+#define RTC_CALR_CALM_8 (0x100UL << RTC_CALR_CALM_Pos) /*!< 0x00000100 */\r
+\r
+/******************** Bits definition for RTC_TAFCR register ****************/\r
+#define RTC_TAFCR_ALARMOUTTYPE_Pos (18U) \r
+#define RTC_TAFCR_ALARMOUTTYPE_Msk (0x1UL << RTC_TAFCR_ALARMOUTTYPE_Pos) /*!< 0x00040000 */\r
+#define RTC_TAFCR_ALARMOUTTYPE RTC_TAFCR_ALARMOUTTYPE_Msk \r
+#define RTC_TAFCR_TAMPPUDIS_Pos (15U) \r
+#define RTC_TAFCR_TAMPPUDIS_Msk (0x1UL << RTC_TAFCR_TAMPPUDIS_Pos) /*!< 0x00008000 */\r
+#define RTC_TAFCR_TAMPPUDIS RTC_TAFCR_TAMPPUDIS_Msk \r
+#define RTC_TAFCR_TAMPPRCH_Pos (13U) \r
+#define RTC_TAFCR_TAMPPRCH_Msk (0x3UL << RTC_TAFCR_TAMPPRCH_Pos) /*!< 0x00006000 */\r
+#define RTC_TAFCR_TAMPPRCH RTC_TAFCR_TAMPPRCH_Msk \r
+#define RTC_TAFCR_TAMPPRCH_0 (0x1UL << RTC_TAFCR_TAMPPRCH_Pos) /*!< 0x00002000 */\r
+#define RTC_TAFCR_TAMPPRCH_1 (0x2UL << RTC_TAFCR_TAMPPRCH_Pos) /*!< 0x00004000 */\r
+#define RTC_TAFCR_TAMPFLT_Pos (11U) \r
+#define RTC_TAFCR_TAMPFLT_Msk (0x3UL << RTC_TAFCR_TAMPFLT_Pos) /*!< 0x00001800 */\r
+#define RTC_TAFCR_TAMPFLT RTC_TAFCR_TAMPFLT_Msk \r
+#define RTC_TAFCR_TAMPFLT_0 (0x1UL << RTC_TAFCR_TAMPFLT_Pos) /*!< 0x00000800 */\r
+#define RTC_TAFCR_TAMPFLT_1 (0x2UL << RTC_TAFCR_TAMPFLT_Pos) /*!< 0x00001000 */\r
+#define RTC_TAFCR_TAMPFREQ_Pos (8U) \r
+#define RTC_TAFCR_TAMPFREQ_Msk (0x7UL << RTC_TAFCR_TAMPFREQ_Pos) /*!< 0x00000700 */\r
+#define RTC_TAFCR_TAMPFREQ RTC_TAFCR_TAMPFREQ_Msk \r
+#define RTC_TAFCR_TAMPFREQ_0 (0x1UL << RTC_TAFCR_TAMPFREQ_Pos) /*!< 0x00000100 */\r
+#define RTC_TAFCR_TAMPFREQ_1 (0x2UL << RTC_TAFCR_TAMPFREQ_Pos) /*!< 0x00000200 */\r
+#define RTC_TAFCR_TAMPFREQ_2 (0x4UL << RTC_TAFCR_TAMPFREQ_Pos) /*!< 0x00000400 */\r
+#define RTC_TAFCR_TAMPTS_Pos (7U) \r
+#define RTC_TAFCR_TAMPTS_Msk (0x1UL << RTC_TAFCR_TAMPTS_Pos) /*!< 0x00000080 */\r
+#define RTC_TAFCR_TAMPTS RTC_TAFCR_TAMPTS_Msk \r
+#define RTC_TAFCR_TAMP3TRG_Pos (6U) \r
+#define RTC_TAFCR_TAMP3TRG_Msk (0x1UL << RTC_TAFCR_TAMP3TRG_Pos) /*!< 0x00000040 */\r
+#define RTC_TAFCR_TAMP3TRG RTC_TAFCR_TAMP3TRG_Msk \r
+#define RTC_TAFCR_TAMP3E_Pos (5U) \r
+#define RTC_TAFCR_TAMP3E_Msk (0x1UL << RTC_TAFCR_TAMP3E_Pos) /*!< 0x00000020 */\r
+#define RTC_TAFCR_TAMP3E RTC_TAFCR_TAMP3E_Msk \r
+#define RTC_TAFCR_TAMP2TRG_Pos (4U) \r
+#define RTC_TAFCR_TAMP2TRG_Msk (0x1UL << RTC_TAFCR_TAMP2TRG_Pos) /*!< 0x00000010 */\r
+#define RTC_TAFCR_TAMP2TRG RTC_TAFCR_TAMP2TRG_Msk \r
+#define RTC_TAFCR_TAMP2E_Pos (3U) \r
+#define RTC_TAFCR_TAMP2E_Msk (0x1UL << RTC_TAFCR_TAMP2E_Pos) /*!< 0x00000008 */\r
+#define RTC_TAFCR_TAMP2E RTC_TAFCR_TAMP2E_Msk \r
+#define RTC_TAFCR_TAMPIE_Pos (2U) \r
+#define RTC_TAFCR_TAMPIE_Msk (0x1UL << RTC_TAFCR_TAMPIE_Pos) /*!< 0x00000004 */\r
+#define RTC_TAFCR_TAMPIE RTC_TAFCR_TAMPIE_Msk \r
+#define RTC_TAFCR_TAMP1TRG_Pos (1U) \r
+#define RTC_TAFCR_TAMP1TRG_Msk (0x1UL << RTC_TAFCR_TAMP1TRG_Pos) /*!< 0x00000002 */\r
+#define RTC_TAFCR_TAMP1TRG RTC_TAFCR_TAMP1TRG_Msk \r
+#define RTC_TAFCR_TAMP1E_Pos (0U) \r
+#define RTC_TAFCR_TAMP1E_Msk (0x1UL << RTC_TAFCR_TAMP1E_Pos) /*!< 0x00000001 */\r
+#define RTC_TAFCR_TAMP1E RTC_TAFCR_TAMP1E_Msk \r
+\r
+/******************** Bits definition for RTC_ALRMASSR register *************/\r
+#define RTC_ALRMASSR_MASKSS_Pos (24U) \r
+#define RTC_ALRMASSR_MASKSS_Msk (0xFUL << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x0F000000 */\r
+#define RTC_ALRMASSR_MASKSS RTC_ALRMASSR_MASKSS_Msk \r
+#define RTC_ALRMASSR_MASKSS_0 (0x1UL << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x01000000 */\r
+#define RTC_ALRMASSR_MASKSS_1 (0x2UL << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x02000000 */\r
+#define RTC_ALRMASSR_MASKSS_2 (0x4UL << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x04000000 */\r
+#define RTC_ALRMASSR_MASKSS_3 (0x8UL << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x08000000 */\r
+#define RTC_ALRMASSR_SS_Pos (0U) \r
+#define RTC_ALRMASSR_SS_Msk (0x7FFFUL << RTC_ALRMASSR_SS_Pos) /*!< 0x00007FFF */\r
+#define RTC_ALRMASSR_SS RTC_ALRMASSR_SS_Msk \r
+\r
+/******************** Bits definition for RTC_ALRMBSSR register *************/\r
+#define RTC_ALRMBSSR_MASKSS_Pos (24U) \r
+#define RTC_ALRMBSSR_MASKSS_Msk (0xFUL << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x0F000000 */\r
+#define RTC_ALRMBSSR_MASKSS RTC_ALRMBSSR_MASKSS_Msk \r
+#define RTC_ALRMBSSR_MASKSS_0 (0x1UL << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x01000000 */\r
+#define RTC_ALRMBSSR_MASKSS_1 (0x2UL << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x02000000 */\r
+#define RTC_ALRMBSSR_MASKSS_2 (0x4UL << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x04000000 */\r
+#define RTC_ALRMBSSR_MASKSS_3 (0x8UL << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x08000000 */\r
+#define RTC_ALRMBSSR_SS_Pos (0U) \r
+#define RTC_ALRMBSSR_SS_Msk (0x7FFFUL << RTC_ALRMBSSR_SS_Pos) /*!< 0x00007FFF */\r
+#define RTC_ALRMBSSR_SS RTC_ALRMBSSR_SS_Msk \r
+\r
+/******************** Bits definition for RTC_BKP0R register ****************/\r
+#define RTC_BKP0R_Pos (0U) \r
+#define RTC_BKP0R_Msk (0xFFFFFFFFUL << RTC_BKP0R_Pos) /*!< 0xFFFFFFFF */\r
+#define RTC_BKP0R RTC_BKP0R_Msk \r
+\r
+/******************** Bits definition for RTC_BKP1R register ****************/\r
+#define RTC_BKP1R_Pos (0U) \r
+#define RTC_BKP1R_Msk (0xFFFFFFFFUL << RTC_BKP1R_Pos) /*!< 0xFFFFFFFF */\r
+#define RTC_BKP1R RTC_BKP1R_Msk \r
+\r
+/******************** Bits definition for RTC_BKP2R register ****************/\r
+#define RTC_BKP2R_Pos (0U) \r
+#define RTC_BKP2R_Msk (0xFFFFFFFFUL << RTC_BKP2R_Pos) /*!< 0xFFFFFFFF */\r
+#define RTC_BKP2R RTC_BKP2R_Msk \r
+\r
+/******************** Bits definition for RTC_BKP3R register ****************/\r
+#define RTC_BKP3R_Pos (0U) \r
+#define RTC_BKP3R_Msk (0xFFFFFFFFUL << RTC_BKP3R_Pos) /*!< 0xFFFFFFFF */\r
+#define RTC_BKP3R RTC_BKP3R_Msk \r
+\r
+/******************** Bits definition for RTC_BKP4R register ****************/\r
+#define RTC_BKP4R_Pos (0U) \r
+#define RTC_BKP4R_Msk (0xFFFFFFFFUL << RTC_BKP4R_Pos) /*!< 0xFFFFFFFF */\r
+#define RTC_BKP4R RTC_BKP4R_Msk \r
+\r
+/******************** Bits definition for RTC_BKP5R register ****************/\r
+#define RTC_BKP5R_Pos (0U) \r
+#define RTC_BKP5R_Msk (0xFFFFFFFFUL << RTC_BKP5R_Pos) /*!< 0xFFFFFFFF */\r
+#define RTC_BKP5R RTC_BKP5R_Msk \r
+\r
+/******************** Bits definition for RTC_BKP6R register ****************/\r
+#define RTC_BKP6R_Pos (0U) \r
+#define RTC_BKP6R_Msk (0xFFFFFFFFUL << RTC_BKP6R_Pos) /*!< 0xFFFFFFFF */\r
+#define RTC_BKP6R RTC_BKP6R_Msk \r
+\r
+/******************** Bits definition for RTC_BKP7R register ****************/\r
+#define RTC_BKP7R_Pos (0U) \r
+#define RTC_BKP7R_Msk (0xFFFFFFFFUL << RTC_BKP7R_Pos) /*!< 0xFFFFFFFF */\r
+#define RTC_BKP7R RTC_BKP7R_Msk \r
+\r
+/******************** Bits definition for RTC_BKP8R register ****************/\r
+#define RTC_BKP8R_Pos (0U) \r
+#define RTC_BKP8R_Msk (0xFFFFFFFFUL << RTC_BKP8R_Pos) /*!< 0xFFFFFFFF */\r
+#define RTC_BKP8R RTC_BKP8R_Msk \r
+\r
+/******************** Bits definition for RTC_BKP9R register ****************/\r
+#define RTC_BKP9R_Pos (0U) \r
+#define RTC_BKP9R_Msk (0xFFFFFFFFUL << RTC_BKP9R_Pos) /*!< 0xFFFFFFFF */\r
+#define RTC_BKP9R RTC_BKP9R_Msk \r
+\r
+/******************** Bits definition for RTC_BKP10R register ***************/\r
+#define RTC_BKP10R_Pos (0U) \r
+#define RTC_BKP10R_Msk (0xFFFFFFFFUL << RTC_BKP10R_Pos) /*!< 0xFFFFFFFF */\r
+#define RTC_BKP10R RTC_BKP10R_Msk \r
+\r
+/******************** Bits definition for RTC_BKP11R register ***************/\r
+#define RTC_BKP11R_Pos (0U) \r
+#define RTC_BKP11R_Msk (0xFFFFFFFFUL << RTC_BKP11R_Pos) /*!< 0xFFFFFFFF */\r
+#define RTC_BKP11R RTC_BKP11R_Msk \r
+\r
+/******************** Bits definition for RTC_BKP12R register ***************/\r
+#define RTC_BKP12R_Pos (0U) \r
+#define RTC_BKP12R_Msk (0xFFFFFFFFUL << RTC_BKP12R_Pos) /*!< 0xFFFFFFFF */\r
+#define RTC_BKP12R RTC_BKP12R_Msk \r
+\r
+/******************** Bits definition for RTC_BKP13R register ***************/\r
+#define RTC_BKP13R_Pos (0U) \r
+#define RTC_BKP13R_Msk (0xFFFFFFFFUL << RTC_BKP13R_Pos) /*!< 0xFFFFFFFF */\r
+#define RTC_BKP13R RTC_BKP13R_Msk \r
+\r
+/******************** Bits definition for RTC_BKP14R register ***************/\r
+#define RTC_BKP14R_Pos (0U) \r
+#define RTC_BKP14R_Msk (0xFFFFFFFFUL << RTC_BKP14R_Pos) /*!< 0xFFFFFFFF */\r
+#define RTC_BKP14R RTC_BKP14R_Msk \r
+\r
+/******************** Bits definition for RTC_BKP15R register ***************/\r
+#define RTC_BKP15R_Pos (0U) \r
+#define RTC_BKP15R_Msk (0xFFFFFFFFUL << RTC_BKP15R_Pos) /*!< 0xFFFFFFFF */\r
+#define RTC_BKP15R RTC_BKP15R_Msk \r
+\r
+/******************** Bits definition for RTC_BKP16R register ***************/\r
+#define RTC_BKP16R_Pos (0U) \r
+#define RTC_BKP16R_Msk (0xFFFFFFFFUL << RTC_BKP16R_Pos) /*!< 0xFFFFFFFF */\r
+#define RTC_BKP16R RTC_BKP16R_Msk \r
+\r
+/******************** Bits definition for RTC_BKP17R register ***************/\r
+#define RTC_BKP17R_Pos (0U) \r
+#define RTC_BKP17R_Msk (0xFFFFFFFFUL << RTC_BKP17R_Pos) /*!< 0xFFFFFFFF */\r
+#define RTC_BKP17R RTC_BKP17R_Msk \r
+\r
+/******************** Bits definition for RTC_BKP18R register ***************/\r
+#define RTC_BKP18R_Pos (0U) \r
+#define RTC_BKP18R_Msk (0xFFFFFFFFUL << RTC_BKP18R_Pos) /*!< 0xFFFFFFFF */\r
+#define RTC_BKP18R RTC_BKP18R_Msk \r
+\r
+/******************** Bits definition for RTC_BKP19R register ***************/\r
+#define RTC_BKP19R_Pos (0U) \r
+#define RTC_BKP19R_Msk (0xFFFFFFFFUL << RTC_BKP19R_Pos) /*!< 0xFFFFFFFF */\r
+#define RTC_BKP19R RTC_BKP19R_Msk \r
+\r
+/******************** Bits definition for RTC_BKP20R register ***************/\r
+#define RTC_BKP20R_Pos (0U) \r
+#define RTC_BKP20R_Msk (0xFFFFFFFFUL << RTC_BKP20R_Pos) /*!< 0xFFFFFFFF */\r
+#define RTC_BKP20R RTC_BKP20R_Msk \r
+\r
+/******************** Bits definition for RTC_BKP21R register ***************/\r
+#define RTC_BKP21R_Pos (0U) \r
+#define RTC_BKP21R_Msk (0xFFFFFFFFUL << RTC_BKP21R_Pos) /*!< 0xFFFFFFFF */\r
+#define RTC_BKP21R RTC_BKP21R_Msk \r
+\r
+/******************** Bits definition for RTC_BKP22R register ***************/\r
+#define RTC_BKP22R_Pos (0U) \r
+#define RTC_BKP22R_Msk (0xFFFFFFFFUL << RTC_BKP22R_Pos) /*!< 0xFFFFFFFF */\r
+#define RTC_BKP22R RTC_BKP22R_Msk \r
+\r
+/******************** Bits definition for RTC_BKP23R register ***************/\r
+#define RTC_BKP23R_Pos (0U) \r
+#define RTC_BKP23R_Msk (0xFFFFFFFFUL << RTC_BKP23R_Pos) /*!< 0xFFFFFFFF */\r
+#define RTC_BKP23R RTC_BKP23R_Msk \r
+\r
+/******************** Bits definition for RTC_BKP24R register ***************/\r
+#define RTC_BKP24R_Pos (0U) \r
+#define RTC_BKP24R_Msk (0xFFFFFFFFUL << RTC_BKP24R_Pos) /*!< 0xFFFFFFFF */\r
+#define RTC_BKP24R RTC_BKP24R_Msk \r
+\r
+/******************** Bits definition for RTC_BKP25R register ***************/\r
+#define RTC_BKP25R_Pos (0U) \r
+#define RTC_BKP25R_Msk (0xFFFFFFFFUL << RTC_BKP25R_Pos) /*!< 0xFFFFFFFF */\r
+#define RTC_BKP25R RTC_BKP25R_Msk \r
+\r
+/******************** Bits definition for RTC_BKP26R register ***************/\r
+#define RTC_BKP26R_Pos (0U) \r
+#define RTC_BKP26R_Msk (0xFFFFFFFFUL << RTC_BKP26R_Pos) /*!< 0xFFFFFFFF */\r
+#define RTC_BKP26R RTC_BKP26R_Msk \r
+\r
+/******************** Bits definition for RTC_BKP27R register ***************/\r
+#define RTC_BKP27R_Pos (0U) \r
+#define RTC_BKP27R_Msk (0xFFFFFFFFUL << RTC_BKP27R_Pos) /*!< 0xFFFFFFFF */\r
+#define RTC_BKP27R RTC_BKP27R_Msk \r
+\r
+/******************** Bits definition for RTC_BKP28R register ***************/\r
+#define RTC_BKP28R_Pos (0U) \r
+#define RTC_BKP28R_Msk (0xFFFFFFFFUL << RTC_BKP28R_Pos) /*!< 0xFFFFFFFF */\r
+#define RTC_BKP28R RTC_BKP28R_Msk \r
+\r
+/******************** Bits definition for RTC_BKP29R register ***************/\r
+#define RTC_BKP29R_Pos (0U) \r
+#define RTC_BKP29R_Msk (0xFFFFFFFFUL << RTC_BKP29R_Pos) /*!< 0xFFFFFFFF */\r
+#define RTC_BKP29R RTC_BKP29R_Msk \r
+\r
+/******************** Bits definition for RTC_BKP30R register ***************/\r
+#define RTC_BKP30R_Pos (0U) \r
+#define RTC_BKP30R_Msk (0xFFFFFFFFUL << RTC_BKP30R_Pos) /*!< 0xFFFFFFFF */\r
+#define RTC_BKP30R RTC_BKP30R_Msk \r
+\r
+/******************** Bits definition for RTC_BKP31R register ***************/\r
+#define RTC_BKP31R_Pos (0U) \r
+#define RTC_BKP31R_Msk (0xFFFFFFFFUL << RTC_BKP31R_Pos) /*!< 0xFFFFFFFF */\r
+#define RTC_BKP31R RTC_BKP31R_Msk \r
+\r
+/******************** Number of backup registers ******************************/\r
+#define RTC_BKP_NUMBER 32\r
+\r
+/******************************************************************************/\r
+/* */\r
+/* Serial Peripheral Interface (SPI) */\r
+/* */\r
+/******************************************************************************/\r
+\r
+/*\r
+ * @brief Specific device feature definitions (not present on all devices in the STM32F3 serie)\r
+ */\r
+#define SPI_I2S_SUPPORT \r
+\r
+/******************* Bit definition for SPI_CR1 register ********************/\r
+#define SPI_CR1_CPHA_Pos (0U) \r
+#define SPI_CR1_CPHA_Msk (0x1UL << SPI_CR1_CPHA_Pos) /*!< 0x00000001 */\r
+#define SPI_CR1_CPHA SPI_CR1_CPHA_Msk /*!< Clock Phase */\r
+#define SPI_CR1_CPOL_Pos (1U) \r
+#define SPI_CR1_CPOL_Msk (0x1UL << SPI_CR1_CPOL_Pos) /*!< 0x00000002 */\r
+#define SPI_CR1_CPOL SPI_CR1_CPOL_Msk /*!< Clock Polarity */\r
+#define SPI_CR1_MSTR_Pos (2U) \r
+#define SPI_CR1_MSTR_Msk (0x1UL << SPI_CR1_MSTR_Pos) /*!< 0x00000004 */\r
+#define SPI_CR1_MSTR SPI_CR1_MSTR_Msk /*!< Master Selection */\r
+\r
+#define SPI_CR1_BR_Pos (3U) \r
+#define SPI_CR1_BR_Msk (0x7UL << SPI_CR1_BR_Pos) /*!< 0x00000038 */\r
+#define SPI_CR1_BR SPI_CR1_BR_Msk /*!< BR[2:0] bits (Baud Rate Control) */\r
+#define SPI_CR1_BR_0 (0x1UL << SPI_CR1_BR_Pos) /*!< 0x00000008 */\r
+#define SPI_CR1_BR_1 (0x2UL << SPI_CR1_BR_Pos) /*!< 0x00000010 */\r
+#define SPI_CR1_BR_2 (0x4UL << SPI_CR1_BR_Pos) /*!< 0x00000020 */\r
+\r
+#define SPI_CR1_SPE_Pos (6U) \r
+#define SPI_CR1_SPE_Msk (0x1UL << SPI_CR1_SPE_Pos) /*!< 0x00000040 */\r
+#define SPI_CR1_SPE SPI_CR1_SPE_Msk /*!< SPI Enable */\r
+#define SPI_CR1_LSBFIRST_Pos (7U) \r
+#define SPI_CR1_LSBFIRST_Msk (0x1UL << SPI_CR1_LSBFIRST_Pos) /*!< 0x00000080 */\r
+#define SPI_CR1_LSBFIRST SPI_CR1_LSBFIRST_Msk /*!< Frame Format */\r
+#define SPI_CR1_SSI_Pos (8U) \r
+#define SPI_CR1_SSI_Msk (0x1UL << SPI_CR1_SSI_Pos) /*!< 0x00000100 */\r
+#define SPI_CR1_SSI SPI_CR1_SSI_Msk /*!< Internal slave select */\r
+#define SPI_CR1_SSM_Pos (9U) \r
+#define SPI_CR1_SSM_Msk (0x1UL << SPI_CR1_SSM_Pos) /*!< 0x00000200 */\r
+#define SPI_CR1_SSM SPI_CR1_SSM_Msk /*!< Software slave management */\r
+#define SPI_CR1_RXONLY_Pos (10U) \r
+#define SPI_CR1_RXONLY_Msk (0x1UL << SPI_CR1_RXONLY_Pos) /*!< 0x00000400 */\r
+#define SPI_CR1_RXONLY SPI_CR1_RXONLY_Msk /*!< Receive only */\r
+#define SPI_CR1_DFF_Pos (11U) \r
+#define SPI_CR1_DFF_Msk (0x1UL << SPI_CR1_DFF_Pos) /*!< 0x00000800 */\r
+#define SPI_CR1_DFF SPI_CR1_DFF_Msk /*!< Data Frame Format */\r
+#define SPI_CR1_CRCNEXT_Pos (12U) \r
+#define SPI_CR1_CRCNEXT_Msk (0x1UL << SPI_CR1_CRCNEXT_Pos) /*!< 0x00001000 */\r
+#define SPI_CR1_CRCNEXT SPI_CR1_CRCNEXT_Msk /*!< Transmit CRC next */\r
+#define SPI_CR1_CRCEN_Pos (13U) \r
+#define SPI_CR1_CRCEN_Msk (0x1UL << SPI_CR1_CRCEN_Pos) /*!< 0x00002000 */\r
+#define SPI_CR1_CRCEN SPI_CR1_CRCEN_Msk /*!< Hardware CRC calculation enable */\r
+#define SPI_CR1_BIDIOE_Pos (14U) \r
+#define SPI_CR1_BIDIOE_Msk (0x1UL << SPI_CR1_BIDIOE_Pos) /*!< 0x00004000 */\r
+#define SPI_CR1_BIDIOE SPI_CR1_BIDIOE_Msk /*!< Output enable in bidirectional mode */\r
+#define SPI_CR1_BIDIMODE_Pos (15U) \r
+#define SPI_CR1_BIDIMODE_Msk (0x1UL << SPI_CR1_BIDIMODE_Pos) /*!< 0x00008000 */\r
+#define SPI_CR1_BIDIMODE SPI_CR1_BIDIMODE_Msk /*!< Bidirectional data mode enable */\r
+\r
+/******************* Bit definition for SPI_CR2 register ********************/\r
+#define SPI_CR2_RXDMAEN_Pos (0U) \r
+#define SPI_CR2_RXDMAEN_Msk (0x1UL << SPI_CR2_RXDMAEN_Pos) /*!< 0x00000001 */\r
+#define SPI_CR2_RXDMAEN SPI_CR2_RXDMAEN_Msk /*!< Rx Buffer DMA Enable */\r
+#define SPI_CR2_TXDMAEN_Pos (1U) \r
+#define SPI_CR2_TXDMAEN_Msk (0x1UL << SPI_CR2_TXDMAEN_Pos) /*!< 0x00000002 */\r
+#define SPI_CR2_TXDMAEN SPI_CR2_TXDMAEN_Msk /*!< Tx Buffer DMA Enable */\r
+#define SPI_CR2_SSOE_Pos (2U) \r
+#define SPI_CR2_SSOE_Msk (0x1UL << SPI_CR2_SSOE_Pos) /*!< 0x00000004 */\r
+#define SPI_CR2_SSOE SPI_CR2_SSOE_Msk /*!< SS Output Enable */\r
+#define SPI_CR2_FRF_Pos (4U) \r
+#define SPI_CR2_FRF_Msk (0x1UL << SPI_CR2_FRF_Pos) /*!< 0x00000010 */\r
+#define SPI_CR2_FRF SPI_CR2_FRF_Msk /*!< Frame format */\r
+#define SPI_CR2_ERRIE_Pos (5U) \r
+#define SPI_CR2_ERRIE_Msk (0x1UL << SPI_CR2_ERRIE_Pos) /*!< 0x00000020 */\r
+#define SPI_CR2_ERRIE SPI_CR2_ERRIE_Msk /*!< Error Interrupt Enable */\r
+#define SPI_CR2_RXNEIE_Pos (6U) \r
+#define SPI_CR2_RXNEIE_Msk (0x1UL << SPI_CR2_RXNEIE_Pos) /*!< 0x00000040 */\r
+#define SPI_CR2_RXNEIE SPI_CR2_RXNEIE_Msk /*!< RX buffer Not Empty Interrupt Enable */\r
+#define SPI_CR2_TXEIE_Pos (7U) \r
+#define SPI_CR2_TXEIE_Msk (0x1UL << SPI_CR2_TXEIE_Pos) /*!< 0x00000080 */\r
+#define SPI_CR2_TXEIE SPI_CR2_TXEIE_Msk /*!< Tx buffer Empty Interrupt Enable */\r
+\r
+/******************** Bit definition for SPI_SR register ********************/\r
+#define SPI_SR_RXNE_Pos (0U) \r
+#define SPI_SR_RXNE_Msk (0x1UL << SPI_SR_RXNE_Pos) /*!< 0x00000001 */\r
+#define SPI_SR_RXNE SPI_SR_RXNE_Msk /*!< Receive buffer Not Empty */\r
+#define SPI_SR_TXE_Pos (1U) \r
+#define SPI_SR_TXE_Msk (0x1UL << SPI_SR_TXE_Pos) /*!< 0x00000002 */\r
+#define SPI_SR_TXE SPI_SR_TXE_Msk /*!< Transmit buffer Empty */\r
+#define SPI_SR_CHSIDE_Pos (2U) \r
+#define SPI_SR_CHSIDE_Msk (0x1UL << SPI_SR_CHSIDE_Pos) /*!< 0x00000004 */\r
+#define SPI_SR_CHSIDE SPI_SR_CHSIDE_Msk /*!< Channel side */\r
+#define SPI_SR_UDR_Pos (3U) \r
+#define SPI_SR_UDR_Msk (0x1UL << SPI_SR_UDR_Pos) /*!< 0x00000008 */\r
+#define SPI_SR_UDR SPI_SR_UDR_Msk /*!< Underrun flag */\r
+#define SPI_SR_CRCERR_Pos (4U) \r
+#define SPI_SR_CRCERR_Msk (0x1UL << SPI_SR_CRCERR_Pos) /*!< 0x00000010 */\r
+#define SPI_SR_CRCERR SPI_SR_CRCERR_Msk /*!< CRC Error flag */\r
+#define SPI_SR_MODF_Pos (5U) \r
+#define SPI_SR_MODF_Msk (0x1UL << SPI_SR_MODF_Pos) /*!< 0x00000020 */\r
+#define SPI_SR_MODF SPI_SR_MODF_Msk /*!< Mode fault */\r
+#define SPI_SR_OVR_Pos (6U) \r
+#define SPI_SR_OVR_Msk (0x1UL << SPI_SR_OVR_Pos) /*!< 0x00000040 */\r
+#define SPI_SR_OVR SPI_SR_OVR_Msk /*!< Overrun flag */\r
+#define SPI_SR_BSY_Pos (7U) \r
+#define SPI_SR_BSY_Msk (0x1UL << SPI_SR_BSY_Pos) /*!< 0x00000080 */\r
+#define SPI_SR_BSY SPI_SR_BSY_Msk /*!< Busy flag */\r
+#define SPI_SR_FRE_Pos (8U) \r
+#define SPI_SR_FRE_Msk (0x1UL << SPI_SR_FRE_Pos) /*!< 0x00000100 */\r
+#define SPI_SR_FRE SPI_SR_FRE_Msk /*!<Frame format error flag */\r
+\r
+/******************** Bit definition for SPI_DR register ********************/\r
+#define SPI_DR_DR_Pos (0U) \r
+#define SPI_DR_DR_Msk (0xFFFFUL << SPI_DR_DR_Pos) /*!< 0x0000FFFF */\r
+#define SPI_DR_DR SPI_DR_DR_Msk /*!< Data Register */\r
+\r
+/******************* Bit definition for SPI_CRCPR register ******************/\r
+#define SPI_CRCPR_CRCPOLY_Pos (0U) \r
+#define SPI_CRCPR_CRCPOLY_Msk (0xFFFFUL << SPI_CRCPR_CRCPOLY_Pos) /*!< 0x0000FFFF */\r
+#define SPI_CRCPR_CRCPOLY SPI_CRCPR_CRCPOLY_Msk /*!< CRC polynomial register */\r
+\r
+/****************** Bit definition for SPI_RXCRCR register ******************/\r
+#define SPI_RXCRCR_RXCRC_Pos (0U) \r
+#define SPI_RXCRCR_RXCRC_Msk (0xFFFFUL << SPI_RXCRCR_RXCRC_Pos) /*!< 0x0000FFFF */\r
+#define SPI_RXCRCR_RXCRC SPI_RXCRCR_RXCRC_Msk /*!< Rx CRC Register */\r
+\r
+/****************** Bit definition for SPI_TXCRCR register ******************/\r
+#define SPI_TXCRCR_TXCRC_Pos (0U) \r
+#define SPI_TXCRCR_TXCRC_Msk (0xFFFFUL << SPI_TXCRCR_TXCRC_Pos) /*!< 0x0000FFFF */\r
+#define SPI_TXCRCR_TXCRC SPI_TXCRCR_TXCRC_Msk /*!< Tx CRC Register */\r
+\r
+/****************** Bit definition for SPI_I2SCFGR register *****************/\r
+#define SPI_I2SCFGR_CHLEN_Pos (0U) \r
+#define SPI_I2SCFGR_CHLEN_Msk (0x1UL << SPI_I2SCFGR_CHLEN_Pos) /*!< 0x00000001 */\r
+#define SPI_I2SCFGR_CHLEN SPI_I2SCFGR_CHLEN_Msk /*!<Channel length (number of bits per audio channel) */\r
+\r
+#define SPI_I2SCFGR_DATLEN_Pos (1U) \r
+#define SPI_I2SCFGR_DATLEN_Msk (0x3UL << SPI_I2SCFGR_DATLEN_Pos) /*!< 0x00000006 */\r
+#define SPI_I2SCFGR_DATLEN SPI_I2SCFGR_DATLEN_Msk /*!<DATLEN[1:0] bits (Data length to be transferred) */\r
+#define SPI_I2SCFGR_DATLEN_0 (0x1UL << SPI_I2SCFGR_DATLEN_Pos) /*!< 0x00000002 */\r
+#define SPI_I2SCFGR_DATLEN_1 (0x2UL << SPI_I2SCFGR_DATLEN_Pos) /*!< 0x00000004 */\r
+\r
+#define SPI_I2SCFGR_CKPOL_Pos (3U) \r
+#define SPI_I2SCFGR_CKPOL_Msk (0x1UL << SPI_I2SCFGR_CKPOL_Pos) /*!< 0x00000008 */\r
+#define SPI_I2SCFGR_CKPOL SPI_I2SCFGR_CKPOL_Msk /*!<steady state clock polarity */\r
+\r
+#define SPI_I2SCFGR_I2SSTD_Pos (4U) \r
+#define SPI_I2SCFGR_I2SSTD_Msk (0x3UL << SPI_I2SCFGR_I2SSTD_Pos) /*!< 0x00000030 */\r
+#define SPI_I2SCFGR_I2SSTD SPI_I2SCFGR_I2SSTD_Msk /*!<I2SSTD[1:0] bits (I2S standard selection) */\r
+#define SPI_I2SCFGR_I2SSTD_0 (0x1UL << SPI_I2SCFGR_I2SSTD_Pos) /*!< 0x00000010 */\r
+#define SPI_I2SCFGR_I2SSTD_1 (0x2UL << SPI_I2SCFGR_I2SSTD_Pos) /*!< 0x00000020 */\r
+\r
+#define SPI_I2SCFGR_PCMSYNC_Pos (7U) \r
+#define SPI_I2SCFGR_PCMSYNC_Msk (0x1UL << SPI_I2SCFGR_PCMSYNC_Pos) /*!< 0x00000080 */\r
+#define SPI_I2SCFGR_PCMSYNC SPI_I2SCFGR_PCMSYNC_Msk /*!<PCM frame synchronization */\r
+\r
+#define SPI_I2SCFGR_I2SCFG_Pos (8U) \r
+#define SPI_I2SCFGR_I2SCFG_Msk (0x3UL << SPI_I2SCFGR_I2SCFG_Pos) /*!< 0x00000300 */\r
+#define SPI_I2SCFGR_I2SCFG SPI_I2SCFGR_I2SCFG_Msk /*!<I2SCFG[1:0] bits (I2S configuration mode) */\r
+#define SPI_I2SCFGR_I2SCFG_0 (0x1UL << SPI_I2SCFGR_I2SCFG_Pos) /*!< 0x00000100 */\r
+#define SPI_I2SCFGR_I2SCFG_1 (0x2UL << SPI_I2SCFGR_I2SCFG_Pos) /*!< 0x00000200 */\r
+\r
+#define SPI_I2SCFGR_I2SE_Pos (10U) \r
+#define SPI_I2SCFGR_I2SE_Msk (0x1UL << SPI_I2SCFGR_I2SE_Pos) /*!< 0x00000400 */\r
+#define SPI_I2SCFGR_I2SE SPI_I2SCFGR_I2SE_Msk /*!<I2S Enable */\r
+#define SPI_I2SCFGR_I2SMOD_Pos (11U) \r
+#define SPI_I2SCFGR_I2SMOD_Msk (0x1UL << SPI_I2SCFGR_I2SMOD_Pos) /*!< 0x00000800 */\r
+#define SPI_I2SCFGR_I2SMOD SPI_I2SCFGR_I2SMOD_Msk /*!<I2S mode selection */\r
+\r
+/****************** Bit definition for SPI_I2SPR register *******************/\r
+#define SPI_I2SPR_I2SDIV_Pos (0U) \r
+#define SPI_I2SPR_I2SDIV_Msk (0xFFUL << SPI_I2SPR_I2SDIV_Pos) /*!< 0x000000FF */\r
+#define SPI_I2SPR_I2SDIV SPI_I2SPR_I2SDIV_Msk /*!<I2S Linear prescaler */\r
+#define SPI_I2SPR_ODD_Pos (8U) \r
+#define SPI_I2SPR_ODD_Msk (0x1UL << SPI_I2SPR_ODD_Pos) /*!< 0x00000100 */\r
+#define SPI_I2SPR_ODD SPI_I2SPR_ODD_Msk /*!<Odd factor for the prescaler */\r
+#define SPI_I2SPR_MCKOE_Pos (9U) \r
+#define SPI_I2SPR_MCKOE_Msk (0x1UL << SPI_I2SPR_MCKOE_Pos) /*!< 0x00000200 */\r
+#define SPI_I2SPR_MCKOE SPI_I2SPR_MCKOE_Msk /*!<Master Clock Output Enable */\r
+\r
+/******************************************************************************/\r
+/* */\r
+/* System Configuration (SYSCFG) */\r
+/* */\r
+/******************************************************************************/\r
+/***************** Bit definition for SYSCFG_MEMRMP register ****************/\r
+#define SYSCFG_MEMRMP_MEM_MODE_Pos (0U) \r
+#define SYSCFG_MEMRMP_MEM_MODE_Msk (0x3UL << SYSCFG_MEMRMP_MEM_MODE_Pos) /*!< 0x00000003 */\r
+#define SYSCFG_MEMRMP_MEM_MODE SYSCFG_MEMRMP_MEM_MODE_Msk /*!< SYSCFG_Memory Remap Config */\r
+#define SYSCFG_MEMRMP_MEM_MODE_0 (0x1UL << SYSCFG_MEMRMP_MEM_MODE_Pos) /*!< 0x00000001 */\r
+#define SYSCFG_MEMRMP_MEM_MODE_1 (0x2UL << SYSCFG_MEMRMP_MEM_MODE_Pos) /*!< 0x00000002 */\r
+#define SYSCFG_MEMRMP_BOOT_MODE_Pos (8U) \r
+#define SYSCFG_MEMRMP_BOOT_MODE_Msk (0x3UL << SYSCFG_MEMRMP_BOOT_MODE_Pos) /*!< 0x00000300 */\r
+#define SYSCFG_MEMRMP_BOOT_MODE SYSCFG_MEMRMP_BOOT_MODE_Msk /*!< Boot mode Config */\r
+#define SYSCFG_MEMRMP_BOOT_MODE_0 (0x1UL << SYSCFG_MEMRMP_BOOT_MODE_Pos) /*!< 0x00000100 */\r
+#define SYSCFG_MEMRMP_BOOT_MODE_1 (0x2UL << SYSCFG_MEMRMP_BOOT_MODE_Pos) /*!< 0x00000200 */\r
+\r
+/***************** Bit definition for SYSCFG_PMC register *******************/\r
+#define SYSCFG_PMC_USB_PU_Pos (0U) \r
+#define SYSCFG_PMC_USB_PU_Msk (0x1UL << SYSCFG_PMC_USB_PU_Pos) /*!< 0x00000001 */\r
+#define SYSCFG_PMC_USB_PU SYSCFG_PMC_USB_PU_Msk /*!< SYSCFG PMC */\r
+#define SYSCFG_PMC_LCD_CAPA_Pos (1U) \r
+#define SYSCFG_PMC_LCD_CAPA_Msk (0x1FUL << SYSCFG_PMC_LCD_CAPA_Pos) /*!< 0x0000003E */\r
+#define SYSCFG_PMC_LCD_CAPA SYSCFG_PMC_LCD_CAPA_Msk /*!< LCD_CAPA decoupling capacitance connection */\r
+#define SYSCFG_PMC_LCD_CAPA_0 (0x01UL << SYSCFG_PMC_LCD_CAPA_Pos) /*!< 0x00000002 */\r
+#define SYSCFG_PMC_LCD_CAPA_1 (0x02UL << SYSCFG_PMC_LCD_CAPA_Pos) /*!< 0x00000004 */\r
+#define SYSCFG_PMC_LCD_CAPA_2 (0x04UL << SYSCFG_PMC_LCD_CAPA_Pos) /*!< 0x00000008 */\r
+#define SYSCFG_PMC_LCD_CAPA_3 (0x08UL << SYSCFG_PMC_LCD_CAPA_Pos) /*!< 0x00000010 */\r
+#define SYSCFG_PMC_LCD_CAPA_4 (0x10UL << SYSCFG_PMC_LCD_CAPA_Pos) /*!< 0x00000020 */\r
+\r
+/***************** Bit definition for SYSCFG_EXTICR1 register ***************/\r
+#define SYSCFG_EXTICR1_EXTI0_Pos (0U) \r
+#define SYSCFG_EXTICR1_EXTI0_Msk (0xFUL << SYSCFG_EXTICR1_EXTI0_Pos) /*!< 0x0000000F */\r
+#define SYSCFG_EXTICR1_EXTI0 SYSCFG_EXTICR1_EXTI0_Msk /*!< EXTI 0 configuration */\r
+#define SYSCFG_EXTICR1_EXTI1_Pos (4U) \r
+#define SYSCFG_EXTICR1_EXTI1_Msk (0xFUL << SYSCFG_EXTICR1_EXTI1_Pos) /*!< 0x000000F0 */\r
+#define SYSCFG_EXTICR1_EXTI1 SYSCFG_EXTICR1_EXTI1_Msk /*!< EXTI 1 configuration */\r
+#define SYSCFG_EXTICR1_EXTI2_Pos (8U) \r
+#define SYSCFG_EXTICR1_EXTI2_Msk (0xFUL << SYSCFG_EXTICR1_EXTI2_Pos) /*!< 0x00000F00 */\r
+#define SYSCFG_EXTICR1_EXTI2 SYSCFG_EXTICR1_EXTI2_Msk /*!< EXTI 2 configuration */\r
+#define SYSCFG_EXTICR1_EXTI3_Pos (12U) \r
+#define SYSCFG_EXTICR1_EXTI3_Msk (0xFUL << SYSCFG_EXTICR1_EXTI3_Pos) /*!< 0x0000F000 */\r
+#define SYSCFG_EXTICR1_EXTI3 SYSCFG_EXTICR1_EXTI3_Msk /*!< EXTI 3 configuration */\r
+\r
+/** \r
+ * @brief EXTI0 configuration \r
+ */ \r
+#define SYSCFG_EXTICR1_EXTI0_PA (0x00000000U) /*!< PA[0] pin */\r
+#define SYSCFG_EXTICR1_EXTI0_PB (0x00000001U) /*!< PB[0] pin */\r
+#define SYSCFG_EXTICR1_EXTI0_PC (0x00000002U) /*!< PC[0] pin */\r
+#define SYSCFG_EXTICR1_EXTI0_PD (0x00000003U) /*!< PD[0] pin */\r
+#define SYSCFG_EXTICR1_EXTI0_PE (0x00000004U) /*!< PE[0] pin */\r
+#define SYSCFG_EXTICR1_EXTI0_PH (0x00000005U) /*!< PH[0] pin */\r
+#define SYSCFG_EXTICR1_EXTI0_PF (0x00000006U) /*!< PF[0] pin */\r
+#define SYSCFG_EXTICR1_EXTI0_PG (0x00000007U) /*!< PG[0] pin */\r
+\r
+/** \r
+ * @brief EXTI1 configuration \r
+ */ \r
+#define SYSCFG_EXTICR1_EXTI1_PA (0x00000000U) /*!< PA[1] pin */\r
+#define SYSCFG_EXTICR1_EXTI1_PB (0x00000010U) /*!< PB[1] pin */\r
+#define SYSCFG_EXTICR1_EXTI1_PC (0x00000020U) /*!< PC[1] pin */\r
+#define SYSCFG_EXTICR1_EXTI1_PD (0x00000030U) /*!< PD[1] pin */\r
+#define SYSCFG_EXTICR1_EXTI1_PE (0x00000040U) /*!< PE[1] pin */\r
+#define SYSCFG_EXTICR1_EXTI1_PH (0x00000050U) /*!< PH[1] pin */\r
+#define SYSCFG_EXTICR1_EXTI1_PF (0x00000060U) /*!< PF[1] pin */\r
+#define SYSCFG_EXTICR1_EXTI1_PG (0x00000070U) /*!< PG[1] pin */\r
+\r
+/** \r
+ * @brief EXTI2 configuration \r
+ */ \r
+#define SYSCFG_EXTICR1_EXTI2_PA (0x00000000U) /*!< PA[2] pin */\r
+#define SYSCFG_EXTICR1_EXTI2_PB (0x00000100U) /*!< PB[2] pin */\r
+#define SYSCFG_EXTICR1_EXTI2_PC (0x00000200U) /*!< PC[2] pin */\r
+#define SYSCFG_EXTICR1_EXTI2_PD (0x00000300U) /*!< PD[2] pin */\r
+#define SYSCFG_EXTICR1_EXTI2_PE (0x00000400U) /*!< PE[2] pin */\r
+#define SYSCFG_EXTICR1_EXTI2_PH (0x00000500U) /*!< PH[2] pin */\r
+#define SYSCFG_EXTICR1_EXTI2_PF (0x00000600U) /*!< PF[2] pin */\r
+#define SYSCFG_EXTICR1_EXTI2_PG (0x00000700U) /*!< PG[2] pin */\r
+\r
+/** \r
+ * @brief EXTI3 configuration \r
+ */ \r
+#define SYSCFG_EXTICR1_EXTI3_PA (0x00000000U) /*!< PA[3] pin */\r
+#define SYSCFG_EXTICR1_EXTI3_PB (0x00001000U) /*!< PB[3] pin */\r
+#define SYSCFG_EXTICR1_EXTI3_PC (0x00002000U) /*!< PC[3] pin */\r
+#define SYSCFG_EXTICR1_EXTI3_PD (0x00003000U) /*!< PD[3] pin */\r
+#define SYSCFG_EXTICR1_EXTI3_PE (0x00004000U) /*!< PE[3] pin */\r
+#define SYSCFG_EXTICR1_EXTI3_PF (0x00003000U) /*!< PF[3] pin */\r
+#define SYSCFG_EXTICR1_EXTI3_PG (0x00004000U) /*!< PG[3] pin */\r
+\r
+/***************** Bit definition for SYSCFG_EXTICR2 register *****************/\r
+#define SYSCFG_EXTICR2_EXTI4_Pos (0U) \r
+#define SYSCFG_EXTICR2_EXTI4_Msk (0xFUL << SYSCFG_EXTICR2_EXTI4_Pos) /*!< 0x0000000F */\r
+#define SYSCFG_EXTICR2_EXTI4 SYSCFG_EXTICR2_EXTI4_Msk /*!< EXTI 4 configuration */\r
+#define SYSCFG_EXTICR2_EXTI5_Pos (4U) \r
+#define SYSCFG_EXTICR2_EXTI5_Msk (0xFUL << SYSCFG_EXTICR2_EXTI5_Pos) /*!< 0x000000F0 */\r
+#define SYSCFG_EXTICR2_EXTI5 SYSCFG_EXTICR2_EXTI5_Msk /*!< EXTI 5 configuration */\r
+#define SYSCFG_EXTICR2_EXTI6_Pos (8U) \r
+#define SYSCFG_EXTICR2_EXTI6_Msk (0xFUL << SYSCFG_EXTICR2_EXTI6_Pos) /*!< 0x00000F00 */\r
+#define SYSCFG_EXTICR2_EXTI6 SYSCFG_EXTICR2_EXTI6_Msk /*!< EXTI 6 configuration */\r
+#define SYSCFG_EXTICR2_EXTI7_Pos (12U) \r
+#define SYSCFG_EXTICR2_EXTI7_Msk (0xFUL << SYSCFG_EXTICR2_EXTI7_Pos) /*!< 0x0000F000 */\r
+#define SYSCFG_EXTICR2_EXTI7 SYSCFG_EXTICR2_EXTI7_Msk /*!< EXTI 7 configuration */\r
+\r
+/** \r
+ * @brief EXTI4 configuration \r
+ */ \r
+#define SYSCFG_EXTICR2_EXTI4_PA (0x00000000U) /*!< PA[4] pin */\r
+#define SYSCFG_EXTICR2_EXTI4_PB (0x00000001U) /*!< PB[4] pin */\r
+#define SYSCFG_EXTICR2_EXTI4_PC (0x00000002U) /*!< PC[4] pin */\r
+#define SYSCFG_EXTICR2_EXTI4_PD (0x00000003U) /*!< PD[4] pin */\r
+#define SYSCFG_EXTICR2_EXTI4_PE (0x00000004U) /*!< PE[4] pin */\r
+#define SYSCFG_EXTICR2_EXTI4_PF (0x00000006U) /*!< PF[4] pin */\r
+#define SYSCFG_EXTICR2_EXTI4_PG (0x00000007U) /*!< PG[4] pin */\r
+\r
+/** \r
+ * @brief EXTI5 configuration \r
+ */ \r
+#define SYSCFG_EXTICR2_EXTI5_PA (0x00000000U) /*!< PA[5] pin */\r
+#define SYSCFG_EXTICR2_EXTI5_PB (0x00000010U) /*!< PB[5] pin */\r
+#define SYSCFG_EXTICR2_EXTI5_PC (0x00000020U) /*!< PC[5] pin */\r
+#define SYSCFG_EXTICR2_EXTI5_PD (0x00000030U) /*!< PD[5] pin */\r
+#define SYSCFG_EXTICR2_EXTI5_PE (0x00000040U) /*!< PE[5] pin */\r
+#define SYSCFG_EXTICR2_EXTI5_PF (0x00000060U) /*!< PF[5] pin */\r
+#define SYSCFG_EXTICR2_EXTI5_PG (0x00000070U) /*!< PG[5] pin */\r
+\r
+/** \r
+ * @brief EXTI6 configuration \r
+ */ \r
+#define SYSCFG_EXTICR2_EXTI6_PA (0x00000000U) /*!< PA[6] pin */\r
+#define SYSCFG_EXTICR2_EXTI6_PB (0x00000100U) /*!< PB[6] pin */\r
+#define SYSCFG_EXTICR2_EXTI6_PC (0x00000200U) /*!< PC[6] pin */\r
+#define SYSCFG_EXTICR2_EXTI6_PD (0x00000300U) /*!< PD[6] pin */\r
+#define SYSCFG_EXTICR2_EXTI6_PE (0x00000400U) /*!< PE[6] pin */\r
+#define SYSCFG_EXTICR2_EXTI6_PF (0x00000600U) /*!< PF[6] pin */\r
+#define SYSCFG_EXTICR2_EXTI6_PG (0x00000700U) /*!< PG[6] pin */\r
+\r
+/** \r
+ * @brief EXTI7 configuration \r
+ */ \r
+#define SYSCFG_EXTICR2_EXTI7_PA (0x00000000U) /*!< PA[7] pin */\r
+#define SYSCFG_EXTICR2_EXTI7_PB (0x00001000U) /*!< PB[7] pin */\r
+#define SYSCFG_EXTICR2_EXTI7_PC (0x00002000U) /*!< PC[7] pin */\r
+#define SYSCFG_EXTICR2_EXTI7_PD (0x00003000U) /*!< PD[7] pin */\r
+#define SYSCFG_EXTICR2_EXTI7_PE (0x00004000U) /*!< PE[7] pin */\r
+#define SYSCFG_EXTICR2_EXTI7_PF (0x00006000U) /*!< PF[7] pin */\r
+#define SYSCFG_EXTICR2_EXTI7_PG (0x00007000U) /*!< PG[7] pin */\r
+\r
+/***************** Bit definition for SYSCFG_EXTICR3 register *****************/\r
+#define SYSCFG_EXTICR3_EXTI8_Pos (0U) \r
+#define SYSCFG_EXTICR3_EXTI8_Msk (0xFUL << SYSCFG_EXTICR3_EXTI8_Pos) /*!< 0x0000000F */\r
+#define SYSCFG_EXTICR3_EXTI8 SYSCFG_EXTICR3_EXTI8_Msk /*!< EXTI 8 configuration */\r
+#define SYSCFG_EXTICR3_EXTI9_Pos (4U) \r
+#define SYSCFG_EXTICR3_EXTI9_Msk (0xFUL << SYSCFG_EXTICR3_EXTI9_Pos) /*!< 0x000000F0 */\r
+#define SYSCFG_EXTICR3_EXTI9 SYSCFG_EXTICR3_EXTI9_Msk /*!< EXTI 9 configuration */\r
+#define SYSCFG_EXTICR3_EXTI10_Pos (8U) \r
+#define SYSCFG_EXTICR3_EXTI10_Msk (0xFUL << SYSCFG_EXTICR3_EXTI10_Pos) /*!< 0x00000F00 */\r
+#define SYSCFG_EXTICR3_EXTI10 SYSCFG_EXTICR3_EXTI10_Msk /*!< EXTI 10 configuration */\r
+#define SYSCFG_EXTICR3_EXTI11_Pos (12U) \r
+#define SYSCFG_EXTICR3_EXTI11_Msk (0xFUL << SYSCFG_EXTICR3_EXTI11_Pos) /*!< 0x0000F000 */\r
+#define SYSCFG_EXTICR3_EXTI11 SYSCFG_EXTICR3_EXTI11_Msk /*!< EXTI 11 configuration */\r
+\r
+/** \r
+ * @brief EXTI8 configuration \r
+ */ \r
+#define SYSCFG_EXTICR3_EXTI8_PA (0x00000000U) /*!< PA[8] pin */\r
+#define SYSCFG_EXTICR3_EXTI8_PB (0x00000001U) /*!< PB[8] pin */\r
+#define SYSCFG_EXTICR3_EXTI8_PC (0x00000002U) /*!< PC[8] pin */\r
+#define SYSCFG_EXTICR3_EXTI8_PD (0x00000003U) /*!< PD[8] pin */\r
+#define SYSCFG_EXTICR3_EXTI8_PE (0x00000004U) /*!< PE[8] pin */\r
+#define SYSCFG_EXTICR3_EXTI8_PF (0x00000006U) /*!< PF[8] pin */\r
+#define SYSCFG_EXTICR3_EXTI8_PG (0x00000007U) /*!< PG[8] pin */\r
+\r
+/** \r
+ * @brief EXTI9 configuration \r
+ */ \r
+#define SYSCFG_EXTICR3_EXTI9_PA (0x00000000U) /*!< PA[9] pin */\r
+#define SYSCFG_EXTICR3_EXTI9_PB (0x00000010U) /*!< PB[9] pin */\r
+#define SYSCFG_EXTICR3_EXTI9_PC (0x00000020U) /*!< PC[9] pin */\r
+#define SYSCFG_EXTICR3_EXTI9_PD (0x00000030U) /*!< PD[9] pin */\r
+#define SYSCFG_EXTICR3_EXTI9_PE (0x00000040U) /*!< PE[9] pin */\r
+#define SYSCFG_EXTICR3_EXTI9_PF (0x00000060U) /*!< PF[9] pin */\r
+#define SYSCFG_EXTICR3_EXTI9_PG (0x00000070U) /*!< PG[9] pin */\r
+\r
+/** \r
+ * @brief EXTI10 configuration \r
+ */ \r
+#define SYSCFG_EXTICR3_EXTI10_PA (0x00000000U) /*!< PA[10] pin */\r
+#define SYSCFG_EXTICR3_EXTI10_PB (0x00000100U) /*!< PB[10] pin */\r
+#define SYSCFG_EXTICR3_EXTI10_PC (0x00000200U) /*!< PC[10] pin */\r
+#define SYSCFG_EXTICR3_EXTI10_PD (0x00000300U) /*!< PD[10] pin */\r
+#define SYSCFG_EXTICR3_EXTI10_PE (0x00000400U) /*!< PE[10] pin */\r
+#define SYSCFG_EXTICR3_EXTI10_PF (0x00000600U) /*!< PF[10] pin */\r
+#define SYSCFG_EXTICR3_EXTI10_PG (0x00000700U) /*!< PG[10] pin */\r
+\r
+/** \r
+ * @brief EXTI11 configuration \r
+ */ \r
+#define SYSCFG_EXTICR3_EXTI11_PA (0x00000000U) /*!< PA[11] pin */\r
+#define SYSCFG_EXTICR3_EXTI11_PB (0x00001000U) /*!< PB[11] pin */\r
+#define SYSCFG_EXTICR3_EXTI11_PC (0x00002000U) /*!< PC[11] pin */\r
+#define SYSCFG_EXTICR3_EXTI11_PD (0x00003000U) /*!< PD[11] pin */\r
+#define SYSCFG_EXTICR3_EXTI11_PE (0x00004000U) /*!< PE[11] pin */\r
+#define SYSCFG_EXTICR3_EXTI11_PF (0x00006000U) /*!< PF[11] pin */\r
+#define SYSCFG_EXTICR3_EXTI11_PG (0x00007000U) /*!< PG[11] pin */\r
+\r
+/***************** Bit definition for SYSCFG_EXTICR4 register *****************/\r
+#define SYSCFG_EXTICR4_EXTI12_Pos (0U) \r
+#define SYSCFG_EXTICR4_EXTI12_Msk (0xFUL << SYSCFG_EXTICR4_EXTI12_Pos) /*!< 0x0000000F */\r
+#define SYSCFG_EXTICR4_EXTI12 SYSCFG_EXTICR4_EXTI12_Msk /*!< EXTI 12 configuration */\r
+#define SYSCFG_EXTICR4_EXTI13_Pos (4U) \r
+#define SYSCFG_EXTICR4_EXTI13_Msk (0xFUL << SYSCFG_EXTICR4_EXTI13_Pos) /*!< 0x000000F0 */\r
+#define SYSCFG_EXTICR4_EXTI13 SYSCFG_EXTICR4_EXTI13_Msk /*!< EXTI 13 configuration */\r
+#define SYSCFG_EXTICR4_EXTI14_Pos (8U) \r
+#define SYSCFG_EXTICR4_EXTI14_Msk (0xFUL << SYSCFG_EXTICR4_EXTI14_Pos) /*!< 0x00000F00 */\r
+#define SYSCFG_EXTICR4_EXTI14 SYSCFG_EXTICR4_EXTI14_Msk /*!< EXTI 14 configuration */\r
+#define SYSCFG_EXTICR4_EXTI15_Pos (12U) \r
+#define SYSCFG_EXTICR4_EXTI15_Msk (0xFUL << SYSCFG_EXTICR4_EXTI15_Pos) /*!< 0x0000F000 */\r
+#define SYSCFG_EXTICR4_EXTI15 SYSCFG_EXTICR4_EXTI15_Msk /*!< EXTI 15 configuration */\r
+\r
+/** \r
+ * @brief EXTI12 configuration \r
+ */ \r
+#define SYSCFG_EXTICR4_EXTI12_PA (0x00000000U) /*!< PA[12] pin */\r
+#define SYSCFG_EXTICR4_EXTI12_PB (0x00000001U) /*!< PB[12] pin */\r
+#define SYSCFG_EXTICR4_EXTI12_PC (0x00000002U) /*!< PC[12] pin */\r
+#define SYSCFG_EXTICR4_EXTI12_PD (0x00000003U) /*!< PD[12] pin */\r
+#define SYSCFG_EXTICR4_EXTI12_PE (0x00000004U) /*!< PE[12] pin */\r
+#define SYSCFG_EXTICR4_EXTI12_PF (0x00000006U) /*!< PF[12] pin */\r
+#define SYSCFG_EXTICR4_EXTI12_PG (0x00000007U) /*!< PG[12] pin */\r
+\r
+/** \r
+ * @brief EXTI13 configuration \r
+ */ \r
+#define SYSCFG_EXTICR4_EXTI13_PA (0x00000000U) /*!< PA[13] pin */\r
+#define SYSCFG_EXTICR4_EXTI13_PB (0x00000010U) /*!< PB[13] pin */\r
+#define SYSCFG_EXTICR4_EXTI13_PC (0x00000020U) /*!< PC[13] pin */\r
+#define SYSCFG_EXTICR4_EXTI13_PD (0x00000030U) /*!< PD[13] pin */\r
+#define SYSCFG_EXTICR4_EXTI13_PE (0x00000040U) /*!< PE[13] pin */\r
+#define SYSCFG_EXTICR4_EXTI13_PF (0x00000060U) /*!< PF[13] pin */\r
+#define SYSCFG_EXTICR4_EXTI13_PG (0x00000070U) /*!< PG[13] pin */\r
+\r
+/** \r
+ * @brief EXTI14 configuration \r
+ */ \r
+#define SYSCFG_EXTICR4_EXTI14_PA (0x00000000U) /*!< PA[14] pin */\r
+#define SYSCFG_EXTICR4_EXTI14_PB (0x00000100U) /*!< PB[14] pin */\r
+#define SYSCFG_EXTICR4_EXTI14_PC (0x00000200U) /*!< PC[14] pin */\r
+#define SYSCFG_EXTICR4_EXTI14_PD (0x00000300U) /*!< PD[14] pin */\r
+#define SYSCFG_EXTICR4_EXTI14_PE (0x00000400U) /*!< PE[14] pin */\r
+#define SYSCFG_EXTICR4_EXTI14_PF (0x00000600U) /*!< PF[14] pin */\r
+#define SYSCFG_EXTICR4_EXTI14_PG (0x00000700U) /*!< PG[14] pin */\r
+\r
+/** \r
+ * @brief EXTI15 configuration \r
+ */ \r
+#define SYSCFG_EXTICR4_EXTI15_PA (0x00000000U) /*!< PA[15] pin */\r
+#define SYSCFG_EXTICR4_EXTI15_PB (0x00001000U) /*!< PB[15] pin */\r
+#define SYSCFG_EXTICR4_EXTI15_PC (0x00002000U) /*!< PC[15] pin */\r
+#define SYSCFG_EXTICR4_EXTI15_PD (0x00003000U) /*!< PD[15] pin */\r
+#define SYSCFG_EXTICR4_EXTI15_PE (0x00004000U) /*!< PE[15] pin */\r
+#define SYSCFG_EXTICR4_EXTI15_PF (0x00006000U) /*!< PF[15] pin */\r
+#define SYSCFG_EXTICR4_EXTI15_PG (0x00007000U) /*!< PG[15] pin */\r
+ \r
+/******************************************************************************/\r
+/* */\r
+/* Routing Interface (RI) */\r
+/* */\r
+/******************************************************************************/\r
+\r
+/******************** Bit definition for RI_ICR register ********************/\r
+#define RI_ICR_IC1OS_Pos (0U) \r
+#define RI_ICR_IC1OS_Msk (0xFUL << RI_ICR_IC1OS_Pos) /*!< 0x0000000F */\r
+#define RI_ICR_IC1OS RI_ICR_IC1OS_Msk /*!< IC1OS[3:0] bits (Input Capture 1 select bits) */\r
+#define RI_ICR_IC1OS_0 (0x1UL << RI_ICR_IC1OS_Pos) /*!< 0x00000001 */\r
+#define RI_ICR_IC1OS_1 (0x2UL << RI_ICR_IC1OS_Pos) /*!< 0x00000002 */\r
+#define RI_ICR_IC1OS_2 (0x4UL << RI_ICR_IC1OS_Pos) /*!< 0x00000004 */\r
+#define RI_ICR_IC1OS_3 (0x8UL << RI_ICR_IC1OS_Pos) /*!< 0x00000008 */\r
+\r
+#define RI_ICR_IC2OS_Pos (4U) \r
+#define RI_ICR_IC2OS_Msk (0xFUL << RI_ICR_IC2OS_Pos) /*!< 0x000000F0 */\r
+#define RI_ICR_IC2OS RI_ICR_IC2OS_Msk /*!< IC2OS[3:0] bits (Input Capture 2 select bits) */\r
+#define RI_ICR_IC2OS_0 (0x1UL << RI_ICR_IC2OS_Pos) /*!< 0x00000010 */\r
+#define RI_ICR_IC2OS_1 (0x2UL << RI_ICR_IC2OS_Pos) /*!< 0x00000020 */\r
+#define RI_ICR_IC2OS_2 (0x4UL << RI_ICR_IC2OS_Pos) /*!< 0x00000040 */\r
+#define RI_ICR_IC2OS_3 (0x8UL << RI_ICR_IC2OS_Pos) /*!< 0x00000080 */\r
+\r
+#define RI_ICR_IC3OS_Pos (8U) \r
+#define RI_ICR_IC3OS_Msk (0xFUL << RI_ICR_IC3OS_Pos) /*!< 0x00000F00 */\r
+#define RI_ICR_IC3OS RI_ICR_IC3OS_Msk /*!< IC3OS[3:0] bits (Input Capture 3 select bits) */\r
+#define RI_ICR_IC3OS_0 (0x1UL << RI_ICR_IC3OS_Pos) /*!< 0x00000100 */\r
+#define RI_ICR_IC3OS_1 (0x2UL << RI_ICR_IC3OS_Pos) /*!< 0x00000200 */\r
+#define RI_ICR_IC3OS_2 (0x4UL << RI_ICR_IC3OS_Pos) /*!< 0x00000400 */\r
+#define RI_ICR_IC3OS_3 (0x8UL << RI_ICR_IC3OS_Pos) /*!< 0x00000800 */\r
+\r
+#define RI_ICR_IC4OS_Pos (12U) \r
+#define RI_ICR_IC4OS_Msk (0xFUL << RI_ICR_IC4OS_Pos) /*!< 0x0000F000 */\r
+#define RI_ICR_IC4OS RI_ICR_IC4OS_Msk /*!< IC4OS[3:0] bits (Input Capture 4 select bits) */\r
+#define RI_ICR_IC4OS_0 (0x1UL << RI_ICR_IC4OS_Pos) /*!< 0x00001000 */\r
+#define RI_ICR_IC4OS_1 (0x2UL << RI_ICR_IC4OS_Pos) /*!< 0x00002000 */\r
+#define RI_ICR_IC4OS_2 (0x4UL << RI_ICR_IC4OS_Pos) /*!< 0x00004000 */\r
+#define RI_ICR_IC4OS_3 (0x8UL << RI_ICR_IC4OS_Pos) /*!< 0x00008000 */\r
+\r
+#define RI_ICR_TIM_Pos (16U) \r
+#define RI_ICR_TIM_Msk (0x3UL << RI_ICR_TIM_Pos) /*!< 0x00030000 */\r
+#define RI_ICR_TIM RI_ICR_TIM_Msk /*!< TIM[3:0] bits (Timers select bits) */\r
+#define RI_ICR_TIM_0 (0x1UL << RI_ICR_TIM_Pos) /*!< 0x00010000 */\r
+#define RI_ICR_TIM_1 (0x2UL << RI_ICR_TIM_Pos) /*!< 0x00020000 */\r
+\r
+#define RI_ICR_IC1_Pos (18U) \r
+#define RI_ICR_IC1_Msk (0x1UL << RI_ICR_IC1_Pos) /*!< 0x00040000 */\r
+#define RI_ICR_IC1 RI_ICR_IC1_Msk /*!< Input capture 1 */\r
+#define RI_ICR_IC2_Pos (19U) \r
+#define RI_ICR_IC2_Msk (0x1UL << RI_ICR_IC2_Pos) /*!< 0x00080000 */\r
+#define RI_ICR_IC2 RI_ICR_IC2_Msk /*!< Input capture 2 */\r
+#define RI_ICR_IC3_Pos (20U) \r
+#define RI_ICR_IC3_Msk (0x1UL << RI_ICR_IC3_Pos) /*!< 0x00100000 */\r
+#define RI_ICR_IC3 RI_ICR_IC3_Msk /*!< Input capture 3 */\r
+#define RI_ICR_IC4_Pos (21U) \r
+#define RI_ICR_IC4_Msk (0x1UL << RI_ICR_IC4_Pos) /*!< 0x00200000 */\r
+#define RI_ICR_IC4 RI_ICR_IC4_Msk /*!< Input capture 4 */\r
+\r
+/******************** Bit definition for RI_ASCR1 register ********************/\r
+#define RI_ASCR1_CH_Pos (0U) \r
+#define RI_ASCR1_CH_Msk (0x7BFDFFFFUL << RI_ASCR1_CH_Pos) /*!< 0x7BFDFFFF */\r
+#define RI_ASCR1_CH RI_ASCR1_CH_Msk /*!< AS_CH[25:18] & AS_CH[15:0] bits ( Analog switches selection bits) */\r
+#define RI_ASCR1_CH_0 (0x00000001U) /*!< Bit 0 */\r
+#define RI_ASCR1_CH_1 (0x00000002U) /*!< Bit 1 */\r
+#define RI_ASCR1_CH_2 (0x00000004U) /*!< Bit 2 */\r
+#define RI_ASCR1_CH_3 (0x00000008U) /*!< Bit 3 */\r
+#define RI_ASCR1_CH_4 (0x00000010U) /*!< Bit 4 */\r
+#define RI_ASCR1_CH_5 (0x00000020U) /*!< Bit 5 */\r
+#define RI_ASCR1_CH_6 (0x00000040U) /*!< Bit 6 */\r
+#define RI_ASCR1_CH_7 (0x00000080U) /*!< Bit 7 */\r
+#define RI_ASCR1_CH_8 (0x00000100U) /*!< Bit 8 */\r
+#define RI_ASCR1_CH_9 (0x00000200U) /*!< Bit 9 */\r
+#define RI_ASCR1_CH_10 (0x00000400U) /*!< Bit 10 */\r
+#define RI_ASCR1_CH_11 (0x00000800U) /*!< Bit 11 */\r
+#define RI_ASCR1_CH_12 (0x00001000U) /*!< Bit 12 */\r
+#define RI_ASCR1_CH_13 (0x00002000U) /*!< Bit 13 */\r
+#define RI_ASCR1_CH_14 (0x00004000U) /*!< Bit 14 */\r
+#define RI_ASCR1_CH_15 (0x00008000U) /*!< Bit 15 */\r
+#define RI_ASCR1_CH_31 (0x00010000U) /*!< Bit 16 */\r
+#define RI_ASCR1_CH_18 (0x00040000U) /*!< Bit 18 */\r
+#define RI_ASCR1_CH_19 (0x00080000U) /*!< Bit 19 */\r
+#define RI_ASCR1_CH_20 (0x00100000U) /*!< Bit 20 */\r
+#define RI_ASCR1_CH_21 (0x00200000U) /*!< Bit 21 */\r
+#define RI_ASCR1_CH_22 (0x00400000U) /*!< Bit 22 */\r
+#define RI_ASCR1_CH_23 (0x00800000U) /*!< Bit 23 */\r
+#define RI_ASCR1_CH_24 (0x01000000U) /*!< Bit 24 */\r
+#define RI_ASCR1_CH_25 (0x02000000U) /*!< Bit 25 */\r
+#define RI_ASCR1_VCOMP_Pos (26U) \r
+#define RI_ASCR1_VCOMP_Msk (0x1UL << RI_ASCR1_VCOMP_Pos) /*!< 0x04000000 */\r
+#define RI_ASCR1_VCOMP RI_ASCR1_VCOMP_Msk /*!< ADC analog switch selection for internal node to COMP1 */\r
+#define RI_ASCR1_CH_27 (0x08000000U) /*!< Bit 27 */\r
+#define RI_ASCR1_CH_28 (0x10000000U) /*!< Bit 28 */\r
+#define RI_ASCR1_CH_29 (0x20000000U) /*!< Bit 29 */\r
+#define RI_ASCR1_CH_30 (0x40000000U) /*!< Bit 30 */\r
+#define RI_ASCR1_SCM_Pos (31U) \r
+#define RI_ASCR1_SCM_Msk (0x1UL << RI_ASCR1_SCM_Pos) /*!< 0x80000000 */\r
+#define RI_ASCR1_SCM RI_ASCR1_SCM_Msk /*!< I/O Switch control mode */\r
+\r
+/******************** Bit definition for RI_ASCR2 register ********************/\r
+#define RI_ASCR2_GR10_1 (0x00000001U) /*!< GR10-1 selection bit */\r
+#define RI_ASCR2_GR10_2 (0x00000002U) /*!< GR10-2 selection bit */\r
+#define RI_ASCR2_GR10_3 (0x00000004U) /*!< GR10-3 selection bit */\r
+#define RI_ASCR2_GR10_4 (0x00000008U) /*!< GR10-4 selection bit */\r
+#define RI_ASCR2_GR6_Pos (4U) \r
+#define RI_ASCR2_GR6_Msk (0x1800003UL << RI_ASCR2_GR6_Pos) /*!< 0x18000030 */\r
+#define RI_ASCR2_GR6 RI_ASCR2_GR6_Msk /*!< GR6 selection bits */\r
+#define RI_ASCR2_GR6_1 (0x0000001UL << RI_ASCR2_GR6_Pos) /*!< 0x00000010 */\r
+#define RI_ASCR2_GR6_2 (0x0000002UL << RI_ASCR2_GR6_Pos) /*!< 0x00000020 */\r
+#define RI_ASCR2_GR6_3 (0x0800000UL << RI_ASCR2_GR6_Pos) /*!< 0x08000000 */\r
+#define RI_ASCR2_GR6_4 (0x1000000UL << RI_ASCR2_GR6_Pos) /*!< 0x10000000 */\r
+#define RI_ASCR2_GR5_1 (0x00000040U) /*!< GR5-1 selection bit */\r
+#define RI_ASCR2_GR5_2 (0x00000080U) /*!< GR5-2 selection bit */\r
+#define RI_ASCR2_GR5_3 (0x00000100U) /*!< GR5-3 selection bit */\r
+#define RI_ASCR2_GR4_1 (0x00000200U) /*!< GR4-1 selection bit */\r
+#define RI_ASCR2_GR4_2 (0x00000400U) /*!< GR4-2 selection bit */\r
+#define RI_ASCR2_GR4_3 (0x00000800U) /*!< GR4-3 selection bit */\r
+#define RI_ASCR2_GR4_4 (0x00008000U) /*!< GR4-4 selection bit */\r
+#define RI_ASCR2_CH0b_Pos (16U) \r
+#define RI_ASCR2_CH0b_Msk (0x1UL << RI_ASCR2_CH0b_Pos) /*!< 0x00010000 */\r
+#define RI_ASCR2_CH0b RI_ASCR2_CH0b_Msk /*!< CH0b selection bit */\r
+#define RI_ASCR2_CH1b_Pos (17U) \r
+#define RI_ASCR2_CH1b_Msk (0x1UL << RI_ASCR2_CH1b_Pos) /*!< 0x00020000 */\r
+#define RI_ASCR2_CH1b RI_ASCR2_CH1b_Msk /*!< CH1b selection bit */\r
+#define RI_ASCR2_CH2b_Pos (18U) \r
+#define RI_ASCR2_CH2b_Msk (0x1UL << RI_ASCR2_CH2b_Pos) /*!< 0x00040000 */\r
+#define RI_ASCR2_CH2b RI_ASCR2_CH2b_Msk /*!< CH2b selection bit */\r
+#define RI_ASCR2_CH3b_Pos (19U) \r
+#define RI_ASCR2_CH3b_Msk (0x1UL << RI_ASCR2_CH3b_Pos) /*!< 0x00080000 */\r
+#define RI_ASCR2_CH3b RI_ASCR2_CH3b_Msk /*!< CH3b selection bit */\r
+#define RI_ASCR2_CH6b_Pos (20U) \r
+#define RI_ASCR2_CH6b_Msk (0x1UL << RI_ASCR2_CH6b_Pos) /*!< 0x00100000 */\r
+#define RI_ASCR2_CH6b RI_ASCR2_CH6b_Msk /*!< CH6b selection bit */\r
+#define RI_ASCR2_CH7b_Pos (21U) \r
+#define RI_ASCR2_CH7b_Msk (0x1UL << RI_ASCR2_CH7b_Pos) /*!< 0x00200000 */\r
+#define RI_ASCR2_CH7b RI_ASCR2_CH7b_Msk /*!< CH7b selection bit */\r
+#define RI_ASCR2_CH8b_Pos (22U) \r
+#define RI_ASCR2_CH8b_Msk (0x1UL << RI_ASCR2_CH8b_Pos) /*!< 0x00400000 */\r
+#define RI_ASCR2_CH8b RI_ASCR2_CH8b_Msk /*!< CH8b selection bit */\r
+#define RI_ASCR2_CH9b_Pos (23U) \r
+#define RI_ASCR2_CH9b_Msk (0x1UL << RI_ASCR2_CH9b_Pos) /*!< 0x00800000 */\r
+#define RI_ASCR2_CH9b RI_ASCR2_CH9b_Msk /*!< CH9b selection bit */\r
+#define RI_ASCR2_CH10b_Pos (24U) \r
+#define RI_ASCR2_CH10b_Msk (0x1UL << RI_ASCR2_CH10b_Pos) /*!< 0x01000000 */\r
+#define RI_ASCR2_CH10b RI_ASCR2_CH10b_Msk /*!< CH10b selection bit */\r
+#define RI_ASCR2_CH11b_Pos (25U) \r
+#define RI_ASCR2_CH11b_Msk (0x1UL << RI_ASCR2_CH11b_Pos) /*!< 0x02000000 */\r
+#define RI_ASCR2_CH11b RI_ASCR2_CH11b_Msk /*!< CH11b selection bit */\r
+#define RI_ASCR2_CH12b_Pos (26U) \r
+#define RI_ASCR2_CH12b_Msk (0x1UL << RI_ASCR2_CH12b_Pos) /*!< 0x04000000 */\r
+#define RI_ASCR2_CH12b RI_ASCR2_CH12b_Msk /*!< CH12b selection bit */\r
+\r
+/******************** Bit definition for RI_HYSCR1 register ********************/\r
+#define RI_HYSCR1_PA_Pos (0U) \r
+#define RI_HYSCR1_PA_Msk (0xFFFFUL << RI_HYSCR1_PA_Pos) /*!< 0x0000FFFF */\r
+#define RI_HYSCR1_PA RI_HYSCR1_PA_Msk /*!< PA[15:0] Port A Hysteresis selection */\r
+#define RI_HYSCR1_PA_0 (0x0001UL << RI_HYSCR1_PA_Pos) /*!< 0x00000001 */\r
+#define RI_HYSCR1_PA_1 (0x0002UL << RI_HYSCR1_PA_Pos) /*!< 0x00000002 */\r
+#define RI_HYSCR1_PA_2 (0x0004UL << RI_HYSCR1_PA_Pos) /*!< 0x00000004 */\r
+#define RI_HYSCR1_PA_3 (0x0008UL << RI_HYSCR1_PA_Pos) /*!< 0x00000008 */\r
+#define RI_HYSCR1_PA_4 (0x0010UL << RI_HYSCR1_PA_Pos) /*!< 0x00000010 */\r
+#define RI_HYSCR1_PA_5 (0x0020UL << RI_HYSCR1_PA_Pos) /*!< 0x00000020 */\r
+#define RI_HYSCR1_PA_6 (0x0040UL << RI_HYSCR1_PA_Pos) /*!< 0x00000040 */\r
+#define RI_HYSCR1_PA_7 (0x0080UL << RI_HYSCR1_PA_Pos) /*!< 0x00000080 */\r
+#define RI_HYSCR1_PA_8 (0x0100UL << RI_HYSCR1_PA_Pos) /*!< 0x00000100 */\r
+#define RI_HYSCR1_PA_9 (0x0200UL << RI_HYSCR1_PA_Pos) /*!< 0x00000200 */\r
+#define RI_HYSCR1_PA_10 (0x0400UL << RI_HYSCR1_PA_Pos) /*!< 0x00000400 */\r
+#define RI_HYSCR1_PA_11 (0x0800UL << RI_HYSCR1_PA_Pos) /*!< 0x00000800 */\r
+#define RI_HYSCR1_PA_12 (0x1000UL << RI_HYSCR1_PA_Pos) /*!< 0x00001000 */\r
+#define RI_HYSCR1_PA_13 (0x2000UL << RI_HYSCR1_PA_Pos) /*!< 0x00002000 */\r
+#define RI_HYSCR1_PA_14 (0x4000UL << RI_HYSCR1_PA_Pos) /*!< 0x00004000 */\r
+#define RI_HYSCR1_PA_15 (0x8000UL << RI_HYSCR1_PA_Pos) /*!< 0x00008000 */\r
+\r
+#define RI_HYSCR1_PB_Pos (16U) \r
+#define RI_HYSCR1_PB_Msk (0xFFFFUL << RI_HYSCR1_PB_Pos) /*!< 0xFFFF0000 */\r
+#define RI_HYSCR1_PB RI_HYSCR1_PB_Msk /*!< PB[15:0] Port B Hysteresis selection */\r
+#define RI_HYSCR1_PB_0 (0x0001UL << RI_HYSCR1_PB_Pos) /*!< 0x00010000 */\r
+#define RI_HYSCR1_PB_1 (0x0002UL << RI_HYSCR1_PB_Pos) /*!< 0x00020000 */\r
+#define RI_HYSCR1_PB_2 (0x0004UL << RI_HYSCR1_PB_Pos) /*!< 0x00040000 */\r
+#define RI_HYSCR1_PB_3 (0x0008UL << RI_HYSCR1_PB_Pos) /*!< 0x00080000 */\r
+#define RI_HYSCR1_PB_4 (0x0010UL << RI_HYSCR1_PB_Pos) /*!< 0x00100000 */\r
+#define RI_HYSCR1_PB_5 (0x0020UL << RI_HYSCR1_PB_Pos) /*!< 0x00200000 */\r
+#define RI_HYSCR1_PB_6 (0x0040UL << RI_HYSCR1_PB_Pos) /*!< 0x00400000 */\r
+#define RI_HYSCR1_PB_7 (0x0080UL << RI_HYSCR1_PB_Pos) /*!< 0x00800000 */\r
+#define RI_HYSCR1_PB_8 (0x0100UL << RI_HYSCR1_PB_Pos) /*!< 0x01000000 */\r
+#define RI_HYSCR1_PB_9 (0x0200UL << RI_HYSCR1_PB_Pos) /*!< 0x02000000 */\r
+#define RI_HYSCR1_PB_10 (0x0400UL << RI_HYSCR1_PB_Pos) /*!< 0x04000000 */\r
+#define RI_HYSCR1_PB_11 (0x0800UL << RI_HYSCR1_PB_Pos) /*!< 0x08000000 */\r
+#define RI_HYSCR1_PB_12 (0x1000UL << RI_HYSCR1_PB_Pos) /*!< 0x10000000 */\r
+#define RI_HYSCR1_PB_13 (0x2000UL << RI_HYSCR1_PB_Pos) /*!< 0x20000000 */\r
+#define RI_HYSCR1_PB_14 (0x4000UL << RI_HYSCR1_PB_Pos) /*!< 0x40000000 */\r
+#define RI_HYSCR1_PB_15 (0x8000UL << RI_HYSCR1_PB_Pos) /*!< 0x80000000 */\r
+\r
+/******************** Bit definition for RI_HYSCR2 register ********************/\r
+#define RI_HYSCR2_PC_Pos (0U) \r
+#define RI_HYSCR2_PC_Msk (0xFFFFUL << RI_HYSCR2_PC_Pos) /*!< 0x0000FFFF */\r
+#define RI_HYSCR2_PC RI_HYSCR2_PC_Msk /*!< PC[15:0] Port C Hysteresis selection */\r
+#define RI_HYSCR2_PC_0 (0x0001UL << RI_HYSCR2_PC_Pos) /*!< 0x00000001 */\r
+#define RI_HYSCR2_PC_1 (0x0002UL << RI_HYSCR2_PC_Pos) /*!< 0x00000002 */\r
+#define RI_HYSCR2_PC_2 (0x0004UL << RI_HYSCR2_PC_Pos) /*!< 0x00000004 */\r
+#define RI_HYSCR2_PC_3 (0x0008UL << RI_HYSCR2_PC_Pos) /*!< 0x00000008 */\r
+#define RI_HYSCR2_PC_4 (0x0010UL << RI_HYSCR2_PC_Pos) /*!< 0x00000010 */\r
+#define RI_HYSCR2_PC_5 (0x0020UL << RI_HYSCR2_PC_Pos) /*!< 0x00000020 */\r
+#define RI_HYSCR2_PC_6 (0x0040UL << RI_HYSCR2_PC_Pos) /*!< 0x00000040 */\r
+#define RI_HYSCR2_PC_7 (0x0080UL << RI_HYSCR2_PC_Pos) /*!< 0x00000080 */\r
+#define RI_HYSCR2_PC_8 (0x0100UL << RI_HYSCR2_PC_Pos) /*!< 0x00000100 */\r
+#define RI_HYSCR2_PC_9 (0x0200UL << RI_HYSCR2_PC_Pos) /*!< 0x00000200 */\r
+#define RI_HYSCR2_PC_10 (0x0400UL << RI_HYSCR2_PC_Pos) /*!< 0x00000400 */\r
+#define RI_HYSCR2_PC_11 (0x0800UL << RI_HYSCR2_PC_Pos) /*!< 0x00000800 */\r
+#define RI_HYSCR2_PC_12 (0x1000UL << RI_HYSCR2_PC_Pos) /*!< 0x00001000 */\r
+#define RI_HYSCR2_PC_13 (0x2000UL << RI_HYSCR2_PC_Pos) /*!< 0x00002000 */\r
+#define RI_HYSCR2_PC_14 (0x4000UL << RI_HYSCR2_PC_Pos) /*!< 0x00004000 */\r
+#define RI_HYSCR2_PC_15 (0x8000UL << RI_HYSCR2_PC_Pos) /*!< 0x00008000 */\r
+\r
+#define RI_HYSCR2_PD_Pos (16U) \r
+#define RI_HYSCR2_PD_Msk (0xFFFFUL << RI_HYSCR2_PD_Pos) /*!< 0xFFFF0000 */\r
+#define RI_HYSCR2_PD RI_HYSCR2_PD_Msk /*!< PD[15:0] Port D Hysteresis selection */\r
+#define RI_HYSCR2_PD_0 (0x0001UL << RI_HYSCR2_PD_Pos) /*!< 0x00010000 */\r
+#define RI_HYSCR2_PD_1 (0x0002UL << RI_HYSCR2_PD_Pos) /*!< 0x00020000 */\r
+#define RI_HYSCR2_PD_2 (0x0004UL << RI_HYSCR2_PD_Pos) /*!< 0x00040000 */\r
+#define RI_HYSCR2_PD_3 (0x0008UL << RI_HYSCR2_PD_Pos) /*!< 0x00080000 */\r
+#define RI_HYSCR2_PD_4 (0x0010UL << RI_HYSCR2_PD_Pos) /*!< 0x00100000 */\r
+#define RI_HYSCR2_PD_5 (0x0020UL << RI_HYSCR2_PD_Pos) /*!< 0x00200000 */\r
+#define RI_HYSCR2_PD_6 (0x0040UL << RI_HYSCR2_PD_Pos) /*!< 0x00400000 */\r
+#define RI_HYSCR2_PD_7 (0x0080UL << RI_HYSCR2_PD_Pos) /*!< 0x00800000 */\r
+#define RI_HYSCR2_PD_8 (0x0100UL << RI_HYSCR2_PD_Pos) /*!< 0x01000000 */\r
+#define RI_HYSCR2_PD_9 (0x0200UL << RI_HYSCR2_PD_Pos) /*!< 0x02000000 */\r
+#define RI_HYSCR2_PD_10 (0x0400UL << RI_HYSCR2_PD_Pos) /*!< 0x04000000 */\r
+#define RI_HYSCR2_PD_11 (0x0800UL << RI_HYSCR2_PD_Pos) /*!< 0x08000000 */\r
+#define RI_HYSCR2_PD_12 (0x1000UL << RI_HYSCR2_PD_Pos) /*!< 0x10000000 */\r
+#define RI_HYSCR2_PD_13 (0x2000UL << RI_HYSCR2_PD_Pos) /*!< 0x20000000 */\r
+#define RI_HYSCR2_PD_14 (0x4000UL << RI_HYSCR2_PD_Pos) /*!< 0x40000000 */\r
+#define RI_HYSCR2_PD_15 (0x8000UL << RI_HYSCR2_PD_Pos) /*!< 0x80000000 */\r
+\r
+/******************** Bit definition for RI_HYSCR3 register ********************/\r
+#define RI_HYSCR3_PE_Pos (0U) \r
+#define RI_HYSCR3_PE_Msk (0xFFFFUL << RI_HYSCR3_PE_Pos) /*!< 0x0000FFFF */\r
+#define RI_HYSCR3_PE RI_HYSCR3_PE_Msk /*!< PE[15:0] Port E Hysteresis selection */\r
+#define RI_HYSCR3_PE_0 (0x0001UL << RI_HYSCR3_PE_Pos) /*!< 0x00000001 */\r
+#define RI_HYSCR3_PE_1 (0x0002UL << RI_HYSCR3_PE_Pos) /*!< 0x00000002 */\r
+#define RI_HYSCR3_PE_2 (0x0004UL << RI_HYSCR3_PE_Pos) /*!< 0x00000004 */\r
+#define RI_HYSCR3_PE_3 (0x0008UL << RI_HYSCR3_PE_Pos) /*!< 0x00000008 */\r
+#define RI_HYSCR3_PE_4 (0x0010UL << RI_HYSCR3_PE_Pos) /*!< 0x00000010 */\r
+#define RI_HYSCR3_PE_5 (0x0020UL << RI_HYSCR3_PE_Pos) /*!< 0x00000020 */\r
+#define RI_HYSCR3_PE_6 (0x0040UL << RI_HYSCR3_PE_Pos) /*!< 0x00000040 */\r
+#define RI_HYSCR3_PE_7 (0x0080UL << RI_HYSCR3_PE_Pos) /*!< 0x00000080 */\r
+#define RI_HYSCR3_PE_8 (0x0100UL << RI_HYSCR3_PE_Pos) /*!< 0x00000100 */\r
+#define RI_HYSCR3_PE_9 (0x0200UL << RI_HYSCR3_PE_Pos) /*!< 0x00000200 */\r
+#define RI_HYSCR3_PE_10 (0x0400UL << RI_HYSCR3_PE_Pos) /*!< 0x00000400 */\r
+#define RI_HYSCR3_PE_11 (0x0800UL << RI_HYSCR3_PE_Pos) /*!< 0x00000800 */\r
+#define RI_HYSCR3_PE_12 (0x1000UL << RI_HYSCR3_PE_Pos) /*!< 0x00001000 */\r
+#define RI_HYSCR3_PE_13 (0x2000UL << RI_HYSCR3_PE_Pos) /*!< 0x00002000 */\r
+#define RI_HYSCR3_PE_14 (0x4000UL << RI_HYSCR3_PE_Pos) /*!< 0x00004000 */\r
+#define RI_HYSCR3_PE_15 (0x8000UL << RI_HYSCR3_PE_Pos) /*!< 0x00008000 */\r
+#define RI_HYSCR3_PF_Pos (16U) \r
+#define RI_HYSCR3_PF_Msk (0xFFFFUL << RI_HYSCR3_PF_Pos) /*!< 0xFFFF0000 */\r
+#define RI_HYSCR3_PF RI_HYSCR3_PF_Msk /*!< PF[15:0] Port F Hysteresis selection */\r
+#define RI_HYSCR3_PF_0 (0x0001UL << RI_HYSCR3_PF_Pos) /*!< 0x00010000 */\r
+#define RI_HYSCR3_PF_1 (0x0002UL << RI_HYSCR3_PF_Pos) /*!< 0x00020000 */\r
+#define RI_HYSCR3_PF_2 (0x0004UL << RI_HYSCR3_PF_Pos) /*!< 0x00040000 */\r
+#define RI_HYSCR3_PF_3 (0x0008UL << RI_HYSCR3_PF_Pos) /*!< 0x00080000 */\r
+#define RI_HYSCR3_PF_4 (0x0010UL << RI_HYSCR3_PF_Pos) /*!< 0x00100000 */\r
+#define RI_HYSCR3_PF_5 (0x0020UL << RI_HYSCR3_PF_Pos) /*!< 0x00200000 */\r
+#define RI_HYSCR3_PF_6 (0x0040UL << RI_HYSCR3_PF_Pos) /*!< 0x00400000 */\r
+#define RI_HYSCR3_PF_7 (0x0080UL << RI_HYSCR3_PF_Pos) /*!< 0x00800000 */\r
+#define RI_HYSCR3_PF_8 (0x0100UL << RI_HYSCR3_PF_Pos) /*!< 0x01000000 */\r
+#define RI_HYSCR3_PF_9 (0x0200UL << RI_HYSCR3_PF_Pos) /*!< 0x02000000 */\r
+#define RI_HYSCR3_PF_10 (0x0400UL << RI_HYSCR3_PF_Pos) /*!< 0x04000000 */\r
+#define RI_HYSCR3_PF_11 (0x0800UL << RI_HYSCR3_PF_Pos) /*!< 0x08000000 */\r
+#define RI_HYSCR3_PF_12 (0x1000UL << RI_HYSCR3_PF_Pos) /*!< 0x10000000 */\r
+#define RI_HYSCR3_PF_13 (0x2000UL << RI_HYSCR3_PF_Pos) /*!< 0x20000000 */\r
+#define RI_HYSCR3_PF_14 (0x4000UL << RI_HYSCR3_PF_Pos) /*!< 0x40000000 */\r
+#define RI_HYSCR3_PF_15 (0x8000UL << RI_HYSCR3_PF_Pos) /*!< 0x80000000 */\r
+/******************** Bit definition for RI_HYSCR4 register ********************/\r
+#define RI_HYSCR4_PG_Pos (0U) \r
+#define RI_HYSCR4_PG_Msk (0xFFFFUL << RI_HYSCR4_PG_Pos) /*!< 0x0000FFFF */\r
+#define RI_HYSCR4_PG RI_HYSCR4_PG_Msk /*!< PG[15:0] Port G Hysteresis selection */\r
+#define RI_HYSCR4_PG_0 (0x0001UL << RI_HYSCR4_PG_Pos) /*!< 0x00000001 */\r
+#define RI_HYSCR4_PG_1 (0x0002UL << RI_HYSCR4_PG_Pos) /*!< 0x00000002 */\r
+#define RI_HYSCR4_PG_2 (0x0004UL << RI_HYSCR4_PG_Pos) /*!< 0x00000004 */\r
+#define RI_HYSCR4_PG_3 (0x0008UL << RI_HYSCR4_PG_Pos) /*!< 0x00000008 */\r
+#define RI_HYSCR4_PG_4 (0x0010UL << RI_HYSCR4_PG_Pos) /*!< 0x00000010 */\r
+#define RI_HYSCR4_PG_5 (0x0020UL << RI_HYSCR4_PG_Pos) /*!< 0x00000020 */\r
+#define RI_HYSCR4_PG_6 (0x0040UL << RI_HYSCR4_PG_Pos) /*!< 0x00000040 */\r
+#define RI_HYSCR4_PG_7 (0x0080UL << RI_HYSCR4_PG_Pos) /*!< 0x00000080 */\r
+#define RI_HYSCR4_PG_8 (0x0100UL << RI_HYSCR4_PG_Pos) /*!< 0x00000100 */\r
+#define RI_HYSCR4_PG_9 (0x0200UL << RI_HYSCR4_PG_Pos) /*!< 0x00000200 */\r
+#define RI_HYSCR4_PG_10 (0x0400UL << RI_HYSCR4_PG_Pos) /*!< 0x00000400 */\r
+#define RI_HYSCR4_PG_11 (0x0800UL << RI_HYSCR4_PG_Pos) /*!< 0x00000800 */\r
+#define RI_HYSCR4_PG_12 (0x1000UL << RI_HYSCR4_PG_Pos) /*!< 0x00001000 */\r
+#define RI_HYSCR4_PG_13 (0x2000UL << RI_HYSCR4_PG_Pos) /*!< 0x00002000 */\r
+#define RI_HYSCR4_PG_14 (0x4000UL << RI_HYSCR4_PG_Pos) /*!< 0x00004000 */\r
+#define RI_HYSCR4_PG_15 (0x8000UL << RI_HYSCR4_PG_Pos) /*!< 0x00008000 */\r
+\r
+/******************** Bit definition for RI_ASMR1 register ********************/\r
+#define RI_ASMR1_PA_Pos (0U) \r
+#define RI_ASMR1_PA_Msk (0xFFFFUL << RI_ASMR1_PA_Pos) /*!< 0x0000FFFF */\r
+#define RI_ASMR1_PA RI_ASMR1_PA_Msk /*!< PA[15:0] Port A selection*/\r
+#define RI_ASMR1_PA_0 (0x0001UL << RI_ASMR1_PA_Pos) /*!< 0x00000001 */\r
+#define RI_ASMR1_PA_1 (0x0002UL << RI_ASMR1_PA_Pos) /*!< 0x00000002 */\r
+#define RI_ASMR1_PA_2 (0x0004UL << RI_ASMR1_PA_Pos) /*!< 0x00000004 */\r
+#define RI_ASMR1_PA_3 (0x0008UL << RI_ASMR1_PA_Pos) /*!< 0x00000008 */\r
+#define RI_ASMR1_PA_4 (0x0010UL << RI_ASMR1_PA_Pos) /*!< 0x00000010 */\r
+#define RI_ASMR1_PA_5 (0x0020UL << RI_ASMR1_PA_Pos) /*!< 0x00000020 */\r
+#define RI_ASMR1_PA_6 (0x0040UL << RI_ASMR1_PA_Pos) /*!< 0x00000040 */\r
+#define RI_ASMR1_PA_7 (0x0080UL << RI_ASMR1_PA_Pos) /*!< 0x00000080 */\r
+#define RI_ASMR1_PA_8 (0x0100UL << RI_ASMR1_PA_Pos) /*!< 0x00000100 */\r
+#define RI_ASMR1_PA_9 (0x0200UL << RI_ASMR1_PA_Pos) /*!< 0x00000200 */\r
+#define RI_ASMR1_PA_10 (0x0400UL << RI_ASMR1_PA_Pos) /*!< 0x00000400 */\r
+#define RI_ASMR1_PA_11 (0x0800UL << RI_ASMR1_PA_Pos) /*!< 0x00000800 */\r
+#define RI_ASMR1_PA_12 (0x1000UL << RI_ASMR1_PA_Pos) /*!< 0x00001000 */\r
+#define RI_ASMR1_PA_13 (0x2000UL << RI_ASMR1_PA_Pos) /*!< 0x00002000 */\r
+#define RI_ASMR1_PA_14 (0x4000UL << RI_ASMR1_PA_Pos) /*!< 0x00004000 */\r
+#define RI_ASMR1_PA_15 (0x8000UL << RI_ASMR1_PA_Pos) /*!< 0x00008000 */\r
+\r
+/******************** Bit definition for RI_CMR1 register ********************/\r
+#define RI_CMR1_PA_Pos (0U) \r
+#define RI_CMR1_PA_Msk (0xFFFFUL << RI_CMR1_PA_Pos) /*!< 0x0000FFFF */\r
+#define RI_CMR1_PA RI_CMR1_PA_Msk /*!< PA[15:0] Port A selection*/\r
+#define RI_CMR1_PA_0 (0x0001UL << RI_CMR1_PA_Pos) /*!< 0x00000001 */\r
+#define RI_CMR1_PA_1 (0x0002UL << RI_CMR1_PA_Pos) /*!< 0x00000002 */\r
+#define RI_CMR1_PA_2 (0x0004UL << RI_CMR1_PA_Pos) /*!< 0x00000004 */\r
+#define RI_CMR1_PA_3 (0x0008UL << RI_CMR1_PA_Pos) /*!< 0x00000008 */\r
+#define RI_CMR1_PA_4 (0x0010UL << RI_CMR1_PA_Pos) /*!< 0x00000010 */\r
+#define RI_CMR1_PA_5 (0x0020UL << RI_CMR1_PA_Pos) /*!< 0x00000020 */\r
+#define RI_CMR1_PA_6 (0x0040UL << RI_CMR1_PA_Pos) /*!< 0x00000040 */\r
+#define RI_CMR1_PA_7 (0x0080UL << RI_CMR1_PA_Pos) /*!< 0x00000080 */\r
+#define RI_CMR1_PA_8 (0x0100UL << RI_CMR1_PA_Pos) /*!< 0x00000100 */\r
+#define RI_CMR1_PA_9 (0x0200UL << RI_CMR1_PA_Pos) /*!< 0x00000200 */\r
+#define RI_CMR1_PA_10 (0x0400UL << RI_CMR1_PA_Pos) /*!< 0x00000400 */\r
+#define RI_CMR1_PA_11 (0x0800UL << RI_CMR1_PA_Pos) /*!< 0x00000800 */\r
+#define RI_CMR1_PA_12 (0x1000UL << RI_CMR1_PA_Pos) /*!< 0x00001000 */\r
+#define RI_CMR1_PA_13 (0x2000UL << RI_CMR1_PA_Pos) /*!< 0x00002000 */\r
+#define RI_CMR1_PA_14 (0x4000UL << RI_CMR1_PA_Pos) /*!< 0x00004000 */\r
+#define RI_CMR1_PA_15 (0x8000UL << RI_CMR1_PA_Pos) /*!< 0x00008000 */\r
+\r
+/******************** Bit definition for RI_CICR1 register ********************/\r
+#define RI_CICR1_PA_Pos (0U) \r
+#define RI_CICR1_PA_Msk (0xFFFFUL << RI_CICR1_PA_Pos) /*!< 0x0000FFFF */\r
+#define RI_CICR1_PA RI_CICR1_PA_Msk /*!< PA[15:0] Port A selection*/\r
+#define RI_CICR1_PA_0 (0x0001UL << RI_CICR1_PA_Pos) /*!< 0x00000001 */\r
+#define RI_CICR1_PA_1 (0x0002UL << RI_CICR1_PA_Pos) /*!< 0x00000002 */\r
+#define RI_CICR1_PA_2 (0x0004UL << RI_CICR1_PA_Pos) /*!< 0x00000004 */\r
+#define RI_CICR1_PA_3 (0x0008UL << RI_CICR1_PA_Pos) /*!< 0x00000008 */\r
+#define RI_CICR1_PA_4 (0x0010UL << RI_CICR1_PA_Pos) /*!< 0x00000010 */\r
+#define RI_CICR1_PA_5 (0x0020UL << RI_CICR1_PA_Pos) /*!< 0x00000020 */\r
+#define RI_CICR1_PA_6 (0x0040UL << RI_CICR1_PA_Pos) /*!< 0x00000040 */\r
+#define RI_CICR1_PA_7 (0x0080UL << RI_CICR1_PA_Pos) /*!< 0x00000080 */\r
+#define RI_CICR1_PA_8 (0x0100UL << RI_CICR1_PA_Pos) /*!< 0x00000100 */\r
+#define RI_CICR1_PA_9 (0x0200UL << RI_CICR1_PA_Pos) /*!< 0x00000200 */\r
+#define RI_CICR1_PA_10 (0x0400UL << RI_CICR1_PA_Pos) /*!< 0x00000400 */\r
+#define RI_CICR1_PA_11 (0x0800UL << RI_CICR1_PA_Pos) /*!< 0x00000800 */\r
+#define RI_CICR1_PA_12 (0x1000UL << RI_CICR1_PA_Pos) /*!< 0x00001000 */\r
+#define RI_CICR1_PA_13 (0x2000UL << RI_CICR1_PA_Pos) /*!< 0x00002000 */\r
+#define RI_CICR1_PA_14 (0x4000UL << RI_CICR1_PA_Pos) /*!< 0x00004000 */\r
+#define RI_CICR1_PA_15 (0x8000UL << RI_CICR1_PA_Pos) /*!< 0x00008000 */\r
+\r
+/******************** Bit definition for RI_ASMR2 register ********************/\r
+#define RI_ASMR2_PB_Pos (0U) \r
+#define RI_ASMR2_PB_Msk (0xFFFFUL << RI_ASMR2_PB_Pos) /*!< 0x0000FFFF */\r
+#define RI_ASMR2_PB RI_ASMR2_PB_Msk /*!< PB[15:0] Port B selection */\r
+#define RI_ASMR2_PB_0 (0x0001UL << RI_ASMR2_PB_Pos) /*!< 0x00000001 */\r
+#define RI_ASMR2_PB_1 (0x0002UL << RI_ASMR2_PB_Pos) /*!< 0x00000002 */\r
+#define RI_ASMR2_PB_2 (0x0004UL << RI_ASMR2_PB_Pos) /*!< 0x00000004 */\r
+#define RI_ASMR2_PB_3 (0x0008UL << RI_ASMR2_PB_Pos) /*!< 0x00000008 */\r
+#define RI_ASMR2_PB_4 (0x0010UL << RI_ASMR2_PB_Pos) /*!< 0x00000010 */\r
+#define RI_ASMR2_PB_5 (0x0020UL << RI_ASMR2_PB_Pos) /*!< 0x00000020 */\r
+#define RI_ASMR2_PB_6 (0x0040UL << RI_ASMR2_PB_Pos) /*!< 0x00000040 */\r
+#define RI_ASMR2_PB_7 (0x0080UL << RI_ASMR2_PB_Pos) /*!< 0x00000080 */\r
+#define RI_ASMR2_PB_8 (0x0100UL << RI_ASMR2_PB_Pos) /*!< 0x00000100 */\r
+#define RI_ASMR2_PB_9 (0x0200UL << RI_ASMR2_PB_Pos) /*!< 0x00000200 */\r
+#define RI_ASMR2_PB_10 (0x0400UL << RI_ASMR2_PB_Pos) /*!< 0x00000400 */\r
+#define RI_ASMR2_PB_11 (0x0800UL << RI_ASMR2_PB_Pos) /*!< 0x00000800 */\r
+#define RI_ASMR2_PB_12 (0x1000UL << RI_ASMR2_PB_Pos) /*!< 0x00001000 */\r
+#define RI_ASMR2_PB_13 (0x2000UL << RI_ASMR2_PB_Pos) /*!< 0x00002000 */\r
+#define RI_ASMR2_PB_14 (0x4000UL << RI_ASMR2_PB_Pos) /*!< 0x00004000 */\r
+#define RI_ASMR2_PB_15 (0x8000UL << RI_ASMR2_PB_Pos) /*!< 0x00008000 */\r
+\r
+/******************** Bit definition for RI_CMR2 register ********************/\r
+#define RI_CMR2_PB_Pos (0U) \r
+#define RI_CMR2_PB_Msk (0xFFFFUL << RI_CMR2_PB_Pos) /*!< 0x0000FFFF */\r
+#define RI_CMR2_PB RI_CMR2_PB_Msk /*!< PB[15:0] Port B selection */\r
+#define RI_CMR2_PB_0 (0x0001UL << RI_CMR2_PB_Pos) /*!< 0x00000001 */\r
+#define RI_CMR2_PB_1 (0x0002UL << RI_CMR2_PB_Pos) /*!< 0x00000002 */\r
+#define RI_CMR2_PB_2 (0x0004UL << RI_CMR2_PB_Pos) /*!< 0x00000004 */\r
+#define RI_CMR2_PB_3 (0x0008UL << RI_CMR2_PB_Pos) /*!< 0x00000008 */\r
+#define RI_CMR2_PB_4 (0x0010UL << RI_CMR2_PB_Pos) /*!< 0x00000010 */\r
+#define RI_CMR2_PB_5 (0x0020UL << RI_CMR2_PB_Pos) /*!< 0x00000020 */\r
+#define RI_CMR2_PB_6 (0x0040UL << RI_CMR2_PB_Pos) /*!< 0x00000040 */\r
+#define RI_CMR2_PB_7 (0x0080UL << RI_CMR2_PB_Pos) /*!< 0x00000080 */\r
+#define RI_CMR2_PB_8 (0x0100UL << RI_CMR2_PB_Pos) /*!< 0x00000100 */\r
+#define RI_CMR2_PB_9 (0x0200UL << RI_CMR2_PB_Pos) /*!< 0x00000200 */\r
+#define RI_CMR2_PB_10 (0x0400UL << RI_CMR2_PB_Pos) /*!< 0x00000400 */\r
+#define RI_CMR2_PB_11 (0x0800UL << RI_CMR2_PB_Pos) /*!< 0x00000800 */\r
+#define RI_CMR2_PB_12 (0x1000UL << RI_CMR2_PB_Pos) /*!< 0x00001000 */\r
+#define RI_CMR2_PB_13 (0x2000UL << RI_CMR2_PB_Pos) /*!< 0x00002000 */\r
+#define RI_CMR2_PB_14 (0x4000UL << RI_CMR2_PB_Pos) /*!< 0x00004000 */\r
+#define RI_CMR2_PB_15 (0x8000UL << RI_CMR2_PB_Pos) /*!< 0x00008000 */\r
+\r
+/******************** Bit definition for RI_CICR2 register ********************/\r
+#define RI_CICR2_PB_Pos (0U) \r
+#define RI_CICR2_PB_Msk (0xFFFFUL << RI_CICR2_PB_Pos) /*!< 0x0000FFFF */\r
+#define RI_CICR2_PB RI_CICR2_PB_Msk /*!< PB[15:0] Port B selection */\r
+#define RI_CICR2_PB_0 (0x0001UL << RI_CICR2_PB_Pos) /*!< 0x00000001 */\r
+#define RI_CICR2_PB_1 (0x0002UL << RI_CICR2_PB_Pos) /*!< 0x00000002 */\r
+#define RI_CICR2_PB_2 (0x0004UL << RI_CICR2_PB_Pos) /*!< 0x00000004 */\r
+#define RI_CICR2_PB_3 (0x0008UL << RI_CICR2_PB_Pos) /*!< 0x00000008 */\r
+#define RI_CICR2_PB_4 (0x0010UL << RI_CICR2_PB_Pos) /*!< 0x00000010 */\r
+#define RI_CICR2_PB_5 (0x0020UL << RI_CICR2_PB_Pos) /*!< 0x00000020 */\r
+#define RI_CICR2_PB_6 (0x0040UL << RI_CICR2_PB_Pos) /*!< 0x00000040 */\r
+#define RI_CICR2_PB_7 (0x0080UL << RI_CICR2_PB_Pos) /*!< 0x00000080 */\r
+#define RI_CICR2_PB_8 (0x0100UL << RI_CICR2_PB_Pos) /*!< 0x00000100 */\r
+#define RI_CICR2_PB_9 (0x0200UL << RI_CICR2_PB_Pos) /*!< 0x00000200 */\r
+#define RI_CICR2_PB_10 (0x0400UL << RI_CICR2_PB_Pos) /*!< 0x00000400 */\r
+#define RI_CICR2_PB_11 (0x0800UL << RI_CICR2_PB_Pos) /*!< 0x00000800 */\r
+#define RI_CICR2_PB_12 (0x1000UL << RI_CICR2_PB_Pos) /*!< 0x00001000 */\r
+#define RI_CICR2_PB_13 (0x2000UL << RI_CICR2_PB_Pos) /*!< 0x00002000 */\r
+#define RI_CICR2_PB_14 (0x4000UL << RI_CICR2_PB_Pos) /*!< 0x00004000 */\r
+#define RI_CICR2_PB_15 (0x8000UL << RI_CICR2_PB_Pos) /*!< 0x00008000 */\r
+\r
+/******************** Bit definition for RI_ASMR3 register ********************/\r
+#define RI_ASMR3_PC_Pos (0U) \r
+#define RI_ASMR3_PC_Msk (0xFFFFUL << RI_ASMR3_PC_Pos) /*!< 0x0000FFFF */\r
+#define RI_ASMR3_PC RI_ASMR3_PC_Msk /*!< PC[15:0] Port C selection */\r
+#define RI_ASMR3_PC_0 (0x0001UL << RI_ASMR3_PC_Pos) /*!< 0x00000001 */\r
+#define RI_ASMR3_PC_1 (0x0002UL << RI_ASMR3_PC_Pos) /*!< 0x00000002 */\r
+#define RI_ASMR3_PC_2 (0x0004UL << RI_ASMR3_PC_Pos) /*!< 0x00000004 */\r
+#define RI_ASMR3_PC_3 (0x0008UL << RI_ASMR3_PC_Pos) /*!< 0x00000008 */\r
+#define RI_ASMR3_PC_4 (0x0010UL << RI_ASMR3_PC_Pos) /*!< 0x00000010 */\r
+#define RI_ASMR3_PC_5 (0x0020UL << RI_ASMR3_PC_Pos) /*!< 0x00000020 */\r
+#define RI_ASMR3_PC_6 (0x0040UL << RI_ASMR3_PC_Pos) /*!< 0x00000040 */\r
+#define RI_ASMR3_PC_7 (0x0080UL << RI_ASMR3_PC_Pos) /*!< 0x00000080 */\r
+#define RI_ASMR3_PC_8 (0x0100UL << RI_ASMR3_PC_Pos) /*!< 0x00000100 */\r
+#define RI_ASMR3_PC_9 (0x0200UL << RI_ASMR3_PC_Pos) /*!< 0x00000200 */\r
+#define RI_ASMR3_PC_10 (0x0400UL << RI_ASMR3_PC_Pos) /*!< 0x00000400 */\r
+#define RI_ASMR3_PC_11 (0x0800UL << RI_ASMR3_PC_Pos) /*!< 0x00000800 */\r
+#define RI_ASMR3_PC_12 (0x1000UL << RI_ASMR3_PC_Pos) /*!< 0x00001000 */\r
+#define RI_ASMR3_PC_13 (0x2000UL << RI_ASMR3_PC_Pos) /*!< 0x00002000 */\r
+#define RI_ASMR3_PC_14 (0x4000UL << RI_ASMR3_PC_Pos) /*!< 0x00004000 */\r
+#define RI_ASMR3_PC_15 (0x8000UL << RI_ASMR3_PC_Pos) /*!< 0x00008000 */\r
+\r
+/******************** Bit definition for RI_CMR3 register ********************/\r
+#define RI_CMR3_PC_Pos (0U) \r
+#define RI_CMR3_PC_Msk (0xFFFFUL << RI_CMR3_PC_Pos) /*!< 0x0000FFFF */\r
+#define RI_CMR3_PC RI_CMR3_PC_Msk /*!< PC[15:0] Port C selection */\r
+#define RI_CMR3_PC_0 (0x0001UL << RI_CMR3_PC_Pos) /*!< 0x00000001 */\r
+#define RI_CMR3_PC_1 (0x0002UL << RI_CMR3_PC_Pos) /*!< 0x00000002 */\r
+#define RI_CMR3_PC_2 (0x0004UL << RI_CMR3_PC_Pos) /*!< 0x00000004 */\r
+#define RI_CMR3_PC_3 (0x0008UL << RI_CMR3_PC_Pos) /*!< 0x00000008 */\r
+#define RI_CMR3_PC_4 (0x0010UL << RI_CMR3_PC_Pos) /*!< 0x00000010 */\r
+#define RI_CMR3_PC_5 (0x0020UL << RI_CMR3_PC_Pos) /*!< 0x00000020 */\r
+#define RI_CMR3_PC_6 (0x0040UL << RI_CMR3_PC_Pos) /*!< 0x00000040 */\r
+#define RI_CMR3_PC_7 (0x0080UL << RI_CMR3_PC_Pos) /*!< 0x00000080 */\r
+#define RI_CMR3_PC_8 (0x0100UL << RI_CMR3_PC_Pos) /*!< 0x00000100 */\r
+#define RI_CMR3_PC_9 (0x0200UL << RI_CMR3_PC_Pos) /*!< 0x00000200 */\r
+#define RI_CMR3_PC_10 (0x0400UL << RI_CMR3_PC_Pos) /*!< 0x00000400 */\r
+#define RI_CMR3_PC_11 (0x0800UL << RI_CMR3_PC_Pos) /*!< 0x00000800 */\r
+#define RI_CMR3_PC_12 (0x1000UL << RI_CMR3_PC_Pos) /*!< 0x00001000 */\r
+#define RI_CMR3_PC_13 (0x2000UL << RI_CMR3_PC_Pos) /*!< 0x00002000 */\r
+#define RI_CMR3_PC_14 (0x4000UL << RI_CMR3_PC_Pos) /*!< 0x00004000 */\r
+#define RI_CMR3_PC_15 (0x8000UL << RI_CMR3_PC_Pos) /*!< 0x00008000 */\r
+\r
+/******************** Bit definition for RI_CICR3 register ********************/\r
+#define RI_CICR3_PC_Pos (0U) \r
+#define RI_CICR3_PC_Msk (0xFFFFUL << RI_CICR3_PC_Pos) /*!< 0x0000FFFF */\r
+#define RI_CICR3_PC RI_CICR3_PC_Msk /*!< PC[15:0] Port C selection */\r
+#define RI_CICR3_PC_0 (0x0001UL << RI_CICR3_PC_Pos) /*!< 0x00000001 */\r
+#define RI_CICR3_PC_1 (0x0002UL << RI_CICR3_PC_Pos) /*!< 0x00000002 */\r
+#define RI_CICR3_PC_2 (0x0004UL << RI_CICR3_PC_Pos) /*!< 0x00000004 */\r
+#define RI_CICR3_PC_3 (0x0008UL << RI_CICR3_PC_Pos) /*!< 0x00000008 */\r
+#define RI_CICR3_PC_4 (0x0010UL << RI_CICR3_PC_Pos) /*!< 0x00000010 */\r
+#define RI_CICR3_PC_5 (0x0020UL << RI_CICR3_PC_Pos) /*!< 0x00000020 */\r
+#define RI_CICR3_PC_6 (0x0040UL << RI_CICR3_PC_Pos) /*!< 0x00000040 */\r
+#define RI_CICR3_PC_7 (0x0080UL << RI_CICR3_PC_Pos) /*!< 0x00000080 */\r
+#define RI_CICR3_PC_8 (0x0100UL << RI_CICR3_PC_Pos) /*!< 0x00000100 */\r
+#define RI_CICR3_PC_9 (0x0200UL << RI_CICR3_PC_Pos) /*!< 0x00000200 */\r
+#define RI_CICR3_PC_10 (0x0400UL << RI_CICR3_PC_Pos) /*!< 0x00000400 */\r
+#define RI_CICR3_PC_11 (0x0800UL << RI_CICR3_PC_Pos) /*!< 0x00000800 */\r
+#define RI_CICR3_PC_12 (0x1000UL << RI_CICR3_PC_Pos) /*!< 0x00001000 */\r
+#define RI_CICR3_PC_13 (0x2000UL << RI_CICR3_PC_Pos) /*!< 0x00002000 */\r
+#define RI_CICR3_PC_14 (0x4000UL << RI_CICR3_PC_Pos) /*!< 0x00004000 */\r
+#define RI_CICR3_PC_15 (0x8000UL << RI_CICR3_PC_Pos) /*!< 0x00008000 */\r
+\r
+/******************** Bit definition for RI_ASMR4 register ********************/\r
+#define RI_ASMR4_PF_Pos (0U) \r
+#define RI_ASMR4_PF_Msk (0xFFFFUL << RI_ASMR4_PF_Pos) /*!< 0x0000FFFF */\r
+#define RI_ASMR4_PF RI_ASMR4_PF_Msk /*!< PF[15:0] Port F selection */\r
+#define RI_ASMR4_PF_0 (0x0001UL << RI_ASMR4_PF_Pos) /*!< 0x00000001 */\r
+#define RI_ASMR4_PF_1 (0x0002UL << RI_ASMR4_PF_Pos) /*!< 0x00000002 */\r
+#define RI_ASMR4_PF_2 (0x0004UL << RI_ASMR4_PF_Pos) /*!< 0x00000004 */\r
+#define RI_ASMR4_PF_3 (0x0008UL << RI_ASMR4_PF_Pos) /*!< 0x00000008 */\r
+#define RI_ASMR4_PF_4 (0x0010UL << RI_ASMR4_PF_Pos) /*!< 0x00000010 */\r
+#define RI_ASMR4_PF_5 (0x0020UL << RI_ASMR4_PF_Pos) /*!< 0x00000020 */\r
+#define RI_ASMR4_PF_6 (0x0040UL << RI_ASMR4_PF_Pos) /*!< 0x00000040 */\r
+#define RI_ASMR4_PF_7 (0x0080UL << RI_ASMR4_PF_Pos) /*!< 0x00000080 */\r
+#define RI_ASMR4_PF_8 (0x0100UL << RI_ASMR4_PF_Pos) /*!< 0x00000100 */\r
+#define RI_ASMR4_PF_9 (0x0200UL << RI_ASMR4_PF_Pos) /*!< 0x00000200 */\r
+#define RI_ASMR4_PF_10 (0x0400UL << RI_ASMR4_PF_Pos) /*!< 0x00000400 */\r
+#define RI_ASMR4_PF_11 (0x0800UL << RI_ASMR4_PF_Pos) /*!< 0x00000800 */\r
+#define RI_ASMR4_PF_12 (0x1000UL << RI_ASMR4_PF_Pos) /*!< 0x00001000 */\r
+#define RI_ASMR4_PF_13 (0x2000UL << RI_ASMR4_PF_Pos) /*!< 0x00002000 */\r
+#define RI_ASMR4_PF_14 (0x4000UL << RI_ASMR4_PF_Pos) /*!< 0x00004000 */\r
+#define RI_ASMR4_PF_15 (0x8000UL << RI_ASMR4_PF_Pos) /*!< 0x00008000 */\r
+\r
+/******************** Bit definition for RI_CMR4 register ********************/\r
+#define RI_CMR4_PF_Pos (0U) \r
+#define RI_CMR4_PF_Msk (0xFFFFUL << RI_CMR4_PF_Pos) /*!< 0x0000FFFF */\r
+#define RI_CMR4_PF RI_CMR4_PF_Msk /*!< PF[15:0] Port F selection */\r
+#define RI_CMR4_PF_0 (0x0001UL << RI_CMR4_PF_Pos) /*!< 0x00000001 */\r
+#define RI_CMR4_PF_1 (0x0002UL << RI_CMR4_PF_Pos) /*!< 0x00000002 */\r
+#define RI_CMR4_PF_2 (0x0004UL << RI_CMR4_PF_Pos) /*!< 0x00000004 */\r
+#define RI_CMR4_PF_3 (0x0008UL << RI_CMR4_PF_Pos) /*!< 0x00000008 */\r
+#define RI_CMR4_PF_4 (0x0010UL << RI_CMR4_PF_Pos) /*!< 0x00000010 */\r
+#define RI_CMR4_PF_5 (0x0020UL << RI_CMR4_PF_Pos) /*!< 0x00000020 */\r
+#define RI_CMR4_PF_6 (0x0040UL << RI_CMR4_PF_Pos) /*!< 0x00000040 */\r
+#define RI_CMR4_PF_7 (0x0080UL << RI_CMR4_PF_Pos) /*!< 0x00000080 */\r
+#define RI_CMR4_PF_8 (0x0100UL << RI_CMR4_PF_Pos) /*!< 0x00000100 */\r
+#define RI_CMR4_PF_9 (0x0200UL << RI_CMR4_PF_Pos) /*!< 0x00000200 */\r
+#define RI_CMR4_PF_10 (0x0400UL << RI_CMR4_PF_Pos) /*!< 0x00000400 */\r
+#define RI_CMR4_PF_11 (0x0800UL << RI_CMR4_PF_Pos) /*!< 0x00000800 */\r
+#define RI_CMR4_PF_12 (0x1000UL << RI_CMR4_PF_Pos) /*!< 0x00001000 */\r
+#define RI_CMR4_PF_13 (0x2000UL << RI_CMR4_PF_Pos) /*!< 0x00002000 */\r
+#define RI_CMR4_PF_14 (0x4000UL << RI_CMR4_PF_Pos) /*!< 0x00004000 */\r
+#define RI_CMR4_PF_15 (0x8000UL << RI_CMR4_PF_Pos) /*!< 0x00008000 */\r
+\r
+/******************** Bit definition for RI_CICR4 register ********************/\r
+#define RI_CICR4_PF_Pos (0U) \r
+#define RI_CICR4_PF_Msk (0xFFFFUL << RI_CICR4_PF_Pos) /*!< 0x0000FFFF */\r
+#define RI_CICR4_PF RI_CICR4_PF_Msk /*!< PF[15:0] Port F selection */\r
+#define RI_CICR4_PF_0 (0x0001UL << RI_CICR4_PF_Pos) /*!< 0x00000001 */\r
+#define RI_CICR4_PF_1 (0x0002UL << RI_CICR4_PF_Pos) /*!< 0x00000002 */\r
+#define RI_CICR4_PF_2 (0x0004UL << RI_CICR4_PF_Pos) /*!< 0x00000004 */\r
+#define RI_CICR4_PF_3 (0x0008UL << RI_CICR4_PF_Pos) /*!< 0x00000008 */\r
+#define RI_CICR4_PF_4 (0x0010UL << RI_CICR4_PF_Pos) /*!< 0x00000010 */\r
+#define RI_CICR4_PF_5 (0x0020UL << RI_CICR4_PF_Pos) /*!< 0x00000020 */\r
+#define RI_CICR4_PF_6 (0x0040UL << RI_CICR4_PF_Pos) /*!< 0x00000040 */\r
+#define RI_CICR4_PF_7 (0x0080UL << RI_CICR4_PF_Pos) /*!< 0x00000080 */\r
+#define RI_CICR4_PF_8 (0x0100UL << RI_CICR4_PF_Pos) /*!< 0x00000100 */\r
+#define RI_CICR4_PF_9 (0x0200UL << RI_CICR4_PF_Pos) /*!< 0x00000200 */\r
+#define RI_CICR4_PF_10 (0x0400UL << RI_CICR4_PF_Pos) /*!< 0x00000400 */\r
+#define RI_CICR4_PF_11 (0x0800UL << RI_CICR4_PF_Pos) /*!< 0x00000800 */\r
+#define RI_CICR4_PF_12 (0x1000UL << RI_CICR4_PF_Pos) /*!< 0x00001000 */\r
+#define RI_CICR4_PF_13 (0x2000UL << RI_CICR4_PF_Pos) /*!< 0x00002000 */\r
+#define RI_CICR4_PF_14 (0x4000UL << RI_CICR4_PF_Pos) /*!< 0x00004000 */\r
+#define RI_CICR4_PF_15 (0x8000UL << RI_CICR4_PF_Pos) /*!< 0x00008000 */\r
+\r
+/******************** Bit definition for RI_ASMR5 register ********************/\r
+#define RI_ASMR5_PG_Pos (0U) \r
+#define RI_ASMR5_PG_Msk (0xFFFFUL << RI_ASMR5_PG_Pos) /*!< 0x0000FFFF */\r
+#define RI_ASMR5_PG RI_ASMR5_PG_Msk /*!< PG[15:0] Port G selection */\r
+#define RI_ASMR5_PG_0 (0x0001UL << RI_ASMR5_PG_Pos) /*!< 0x00000001 */\r
+#define RI_ASMR5_PG_1 (0x0002UL << RI_ASMR5_PG_Pos) /*!< 0x00000002 */\r
+#define RI_ASMR5_PG_2 (0x0004UL << RI_ASMR5_PG_Pos) /*!< 0x00000004 */\r
+#define RI_ASMR5_PG_3 (0x0008UL << RI_ASMR5_PG_Pos) /*!< 0x00000008 */\r
+#define RI_ASMR5_PG_4 (0x0010UL << RI_ASMR5_PG_Pos) /*!< 0x00000010 */\r
+#define RI_ASMR5_PG_5 (0x0020UL << RI_ASMR5_PG_Pos) /*!< 0x00000020 */\r
+#define RI_ASMR5_PG_6 (0x0040UL << RI_ASMR5_PG_Pos) /*!< 0x00000040 */\r
+#define RI_ASMR5_PG_7 (0x0080UL << RI_ASMR5_PG_Pos) /*!< 0x00000080 */\r
+#define RI_ASMR5_PG_8 (0x0100UL << RI_ASMR5_PG_Pos) /*!< 0x00000100 */\r
+#define RI_ASMR5_PG_9 (0x0200UL << RI_ASMR5_PG_Pos) /*!< 0x00000200 */\r
+#define RI_ASMR5_PG_10 (0x0400UL << RI_ASMR5_PG_Pos) /*!< 0x00000400 */\r
+#define RI_ASMR5_PG_11 (0x0800UL << RI_ASMR5_PG_Pos) /*!< 0x00000800 */\r
+#define RI_ASMR5_PG_12 (0x1000UL << RI_ASMR5_PG_Pos) /*!< 0x00001000 */\r
+#define RI_ASMR5_PG_13 (0x2000UL << RI_ASMR5_PG_Pos) /*!< 0x00002000 */\r
+#define RI_ASMR5_PG_14 (0x4000UL << RI_ASMR5_PG_Pos) /*!< 0x00004000 */\r
+#define RI_ASMR5_PG_15 (0x8000UL << RI_ASMR5_PG_Pos) /*!< 0x00008000 */\r
+\r
+/******************** Bit definition for RI_CMR5 register ********************/\r
+#define RI_CMR5_PG_Pos (0U) \r
+#define RI_CMR5_PG_Msk (0xFFFFUL << RI_CMR5_PG_Pos) /*!< 0x0000FFFF */\r
+#define RI_CMR5_PG RI_CMR5_PG_Msk /*!< PG[15:0] Port G selection */\r
+#define RI_CMR5_PG_0 (0x0001UL << RI_CMR5_PG_Pos) /*!< 0x00000001 */\r
+#define RI_CMR5_PG_1 (0x0002UL << RI_CMR5_PG_Pos) /*!< 0x00000002 */\r
+#define RI_CMR5_PG_2 (0x0004UL << RI_CMR5_PG_Pos) /*!< 0x00000004 */\r
+#define RI_CMR5_PG_3 (0x0008UL << RI_CMR5_PG_Pos) /*!< 0x00000008 */\r
+#define RI_CMR5_PG_4 (0x0010UL << RI_CMR5_PG_Pos) /*!< 0x00000010 */\r
+#define RI_CMR5_PG_5 (0x0020UL << RI_CMR5_PG_Pos) /*!< 0x00000020 */\r
+#define RI_CMR5_PG_6 (0x0040UL << RI_CMR5_PG_Pos) /*!< 0x00000040 */\r
+#define RI_CMR5_PG_7 (0x0080UL << RI_CMR5_PG_Pos) /*!< 0x00000080 */\r
+#define RI_CMR5_PG_8 (0x0100UL << RI_CMR5_PG_Pos) /*!< 0x00000100 */\r
+#define RI_CMR5_PG_9 (0x0200UL << RI_CMR5_PG_Pos) /*!< 0x00000200 */\r
+#define RI_CMR5_PG_10 (0x0400UL << RI_CMR5_PG_Pos) /*!< 0x00000400 */\r
+#define RI_CMR5_PG_11 (0x0800UL << RI_CMR5_PG_Pos) /*!< 0x00000800 */\r
+#define RI_CMR5_PG_12 (0x1000UL << RI_CMR5_PG_Pos) /*!< 0x00001000 */\r
+#define RI_CMR5_PG_13 (0x2000UL << RI_CMR5_PG_Pos) /*!< 0x00002000 */\r
+#define RI_CMR5_PG_14 (0x4000UL << RI_CMR5_PG_Pos) /*!< 0x00004000 */\r
+#define RI_CMR5_PG_15 (0x8000UL << RI_CMR5_PG_Pos) /*!< 0x00008000 */\r
+\r
+/******************** Bit definition for RI_CICR5 register ********************/\r
+#define RI_CICR5_PG_Pos (0U) \r
+#define RI_CICR5_PG_Msk (0xFFFFUL << RI_CICR5_PG_Pos) /*!< 0x0000FFFF */\r
+#define RI_CICR5_PG RI_CICR5_PG_Msk /*!< PG[15:0] Port G selection */\r
+#define RI_CICR5_PG_0 (0x0001UL << RI_CICR5_PG_Pos) /*!< 0x00000001 */\r
+#define RI_CICR5_PG_1 (0x0002UL << RI_CICR5_PG_Pos) /*!< 0x00000002 */\r
+#define RI_CICR5_PG_2 (0x0004UL << RI_CICR5_PG_Pos) /*!< 0x00000004 */\r
+#define RI_CICR5_PG_3 (0x0008UL << RI_CICR5_PG_Pos) /*!< 0x00000008 */\r
+#define RI_CICR5_PG_4 (0x0010UL << RI_CICR5_PG_Pos) /*!< 0x00000010 */\r
+#define RI_CICR5_PG_5 (0x0020UL << RI_CICR5_PG_Pos) /*!< 0x00000020 */\r
+#define RI_CICR5_PG_6 (0x0040UL << RI_CICR5_PG_Pos) /*!< 0x00000040 */\r
+#define RI_CICR5_PG_7 (0x0080UL << RI_CICR5_PG_Pos) /*!< 0x00000080 */\r
+#define RI_CICR5_PG_8 (0x0100UL << RI_CICR5_PG_Pos) /*!< 0x00000100 */\r
+#define RI_CICR5_PG_9 (0x0200UL << RI_CICR5_PG_Pos) /*!< 0x00000200 */\r
+#define RI_CICR5_PG_10 (0x0400UL << RI_CICR5_PG_Pos) /*!< 0x00000400 */\r
+#define RI_CICR5_PG_11 (0x0800UL << RI_CICR5_PG_Pos) /*!< 0x00000800 */\r
+#define RI_CICR5_PG_12 (0x1000UL << RI_CICR5_PG_Pos) /*!< 0x00001000 */\r
+#define RI_CICR5_PG_13 (0x2000UL << RI_CICR5_PG_Pos) /*!< 0x00002000 */\r
+#define RI_CICR5_PG_14 (0x4000UL << RI_CICR5_PG_Pos) /*!< 0x00004000 */\r
+#define RI_CICR5_PG_15 (0x8000UL << RI_CICR5_PG_Pos) /*!< 0x00008000 */\r
+\r
+/******************************************************************************/\r
+/* */\r
+/* Timers (TIM) */\r
+/* */\r
+/******************************************************************************/\r
+\r
+/******************* Bit definition for TIM_CR1 register ********************/\r
+#define TIM_CR1_CEN_Pos (0U) \r
+#define TIM_CR1_CEN_Msk (0x1UL << TIM_CR1_CEN_Pos) /*!< 0x00000001 */\r
+#define TIM_CR1_CEN TIM_CR1_CEN_Msk /*!<Counter enable */\r
+#define TIM_CR1_UDIS_Pos (1U) \r
+#define TIM_CR1_UDIS_Msk (0x1UL << TIM_CR1_UDIS_Pos) /*!< 0x00000002 */\r
+#define TIM_CR1_UDIS TIM_CR1_UDIS_Msk /*!<Update disable */\r
+#define TIM_CR1_URS_Pos (2U) \r
+#define TIM_CR1_URS_Msk (0x1UL << TIM_CR1_URS_Pos) /*!< 0x00000004 */\r
+#define TIM_CR1_URS TIM_CR1_URS_Msk /*!<Update request source */\r
+#define TIM_CR1_OPM_Pos (3U) \r
+#define TIM_CR1_OPM_Msk (0x1UL << TIM_CR1_OPM_Pos) /*!< 0x00000008 */\r
+#define TIM_CR1_OPM TIM_CR1_OPM_Msk /*!<One pulse mode */\r
+#define TIM_CR1_DIR_Pos (4U) \r
+#define TIM_CR1_DIR_Msk (0x1UL << TIM_CR1_DIR_Pos) /*!< 0x00000010 */\r
+#define TIM_CR1_DIR TIM_CR1_DIR_Msk /*!<Direction */\r
+\r
+#define TIM_CR1_CMS_Pos (5U) \r
+#define TIM_CR1_CMS_Msk (0x3UL << TIM_CR1_CMS_Pos) /*!< 0x00000060 */\r
+#define TIM_CR1_CMS TIM_CR1_CMS_Msk /*!<CMS[1:0] bits (Center-aligned mode selection) */\r
+#define TIM_CR1_CMS_0 (0x1UL << TIM_CR1_CMS_Pos) /*!< 0x00000020 */\r
+#define TIM_CR1_CMS_1 (0x2UL << TIM_CR1_CMS_Pos) /*!< 0x00000040 */\r
+\r
+#define TIM_CR1_ARPE_Pos (7U) \r
+#define TIM_CR1_ARPE_Msk (0x1UL << TIM_CR1_ARPE_Pos) /*!< 0x00000080 */\r
+#define TIM_CR1_ARPE TIM_CR1_ARPE_Msk /*!<Auto-reload preload enable */\r
+\r
+#define TIM_CR1_CKD_Pos (8U) \r
+#define TIM_CR1_CKD_Msk (0x3UL << TIM_CR1_CKD_Pos) /*!< 0x00000300 */\r
+#define TIM_CR1_CKD TIM_CR1_CKD_Msk /*!<CKD[1:0] bits (clock division) */\r
+#define TIM_CR1_CKD_0 (0x1UL << TIM_CR1_CKD_Pos) /*!< 0x00000100 */\r
+#define TIM_CR1_CKD_1 (0x2UL << TIM_CR1_CKD_Pos) /*!< 0x00000200 */\r
+\r
+/******************* Bit definition for TIM_CR2 register ********************/\r
+#define TIM_CR2_CCDS_Pos (3U) \r
+#define TIM_CR2_CCDS_Msk (0x1UL << TIM_CR2_CCDS_Pos) /*!< 0x00000008 */\r
+#define TIM_CR2_CCDS TIM_CR2_CCDS_Msk /*!<Capture/Compare DMA Selection */\r
+\r
+#define TIM_CR2_MMS_Pos (4U) \r
+#define TIM_CR2_MMS_Msk (0x7UL << TIM_CR2_MMS_Pos) /*!< 0x00000070 */\r
+#define TIM_CR2_MMS TIM_CR2_MMS_Msk /*!<MMS[2:0] bits (Master Mode Selection) */\r
+#define TIM_CR2_MMS_0 (0x1UL << TIM_CR2_MMS_Pos) /*!< 0x00000010 */\r
+#define TIM_CR2_MMS_1 (0x2UL << TIM_CR2_MMS_Pos) /*!< 0x00000020 */\r
+#define TIM_CR2_MMS_2 (0x4UL << TIM_CR2_MMS_Pos) /*!< 0x00000040 */\r
+\r
+#define TIM_CR2_TI1S_Pos (7U) \r
+#define TIM_CR2_TI1S_Msk (0x1UL << TIM_CR2_TI1S_Pos) /*!< 0x00000080 */\r
+#define TIM_CR2_TI1S TIM_CR2_TI1S_Msk /*!<TI1 Selection */\r
+\r
+/******************* Bit definition for TIM_SMCR register *******************/\r
+#define TIM_SMCR_SMS_Pos (0U) \r
+#define TIM_SMCR_SMS_Msk (0x7UL << TIM_SMCR_SMS_Pos) /*!< 0x00000007 */\r
+#define TIM_SMCR_SMS TIM_SMCR_SMS_Msk /*!<SMS[2:0] bits (Slave mode selection) */\r
+#define TIM_SMCR_SMS_0 (0x1UL << TIM_SMCR_SMS_Pos) /*!< 0x00000001 */\r
+#define TIM_SMCR_SMS_1 (0x2UL << TIM_SMCR_SMS_Pos) /*!< 0x00000002 */\r
+#define TIM_SMCR_SMS_2 (0x4UL << TIM_SMCR_SMS_Pos) /*!< 0x00000004 */\r
+\r
+#define TIM_SMCR_OCCS_Pos (3U) \r
+#define TIM_SMCR_OCCS_Msk (0x1UL << TIM_SMCR_OCCS_Pos) /*!< 0x00000008 */\r
+#define TIM_SMCR_OCCS TIM_SMCR_OCCS_Msk /*!< OCREF clear selection */\r
+\r
+#define TIM_SMCR_TS_Pos (4U) \r
+#define TIM_SMCR_TS_Msk (0x7UL << TIM_SMCR_TS_Pos) /*!< 0x00000070 */\r
+#define TIM_SMCR_TS TIM_SMCR_TS_Msk /*!<TS[2:0] bits (Trigger selection) */\r
+#define TIM_SMCR_TS_0 (0x1UL << TIM_SMCR_TS_Pos) /*!< 0x00000010 */\r
+#define TIM_SMCR_TS_1 (0x2UL << TIM_SMCR_TS_Pos) /*!< 0x00000020 */\r
+#define TIM_SMCR_TS_2 (0x4UL << TIM_SMCR_TS_Pos) /*!< 0x00000040 */\r
+\r
+#define TIM_SMCR_MSM_Pos (7U) \r
+#define TIM_SMCR_MSM_Msk (0x1UL << TIM_SMCR_MSM_Pos) /*!< 0x00000080 */\r
+#define TIM_SMCR_MSM TIM_SMCR_MSM_Msk /*!<Master/slave mode */\r
+\r
+#define TIM_SMCR_ETF_Pos (8U) \r
+#define TIM_SMCR_ETF_Msk (0xFUL << TIM_SMCR_ETF_Pos) /*!< 0x00000F00 */\r
+#define TIM_SMCR_ETF TIM_SMCR_ETF_Msk /*!<ETF[3:0] bits (External trigger filter) */\r
+#define TIM_SMCR_ETF_0 (0x1UL << TIM_SMCR_ETF_Pos) /*!< 0x00000100 */\r
+#define TIM_SMCR_ETF_1 (0x2UL << TIM_SMCR_ETF_Pos) /*!< 0x00000200 */\r
+#define TIM_SMCR_ETF_2 (0x4UL << TIM_SMCR_ETF_Pos) /*!< 0x00000400 */\r
+#define TIM_SMCR_ETF_3 (0x8UL << TIM_SMCR_ETF_Pos) /*!< 0x00000800 */\r
+\r
+#define TIM_SMCR_ETPS_Pos (12U) \r
+#define TIM_SMCR_ETPS_Msk (0x3UL << TIM_SMCR_ETPS_Pos) /*!< 0x00003000 */\r
+#define TIM_SMCR_ETPS TIM_SMCR_ETPS_Msk /*!<ETPS[1:0] bits (External trigger prescaler) */\r
+#define TIM_SMCR_ETPS_0 (0x1UL << TIM_SMCR_ETPS_Pos) /*!< 0x00001000 */\r
+#define TIM_SMCR_ETPS_1 (0x2UL << TIM_SMCR_ETPS_Pos) /*!< 0x00002000 */\r
+\r
+#define TIM_SMCR_ECE_Pos (14U) \r
+#define TIM_SMCR_ECE_Msk (0x1UL << TIM_SMCR_ECE_Pos) /*!< 0x00004000 */\r
+#define TIM_SMCR_ECE TIM_SMCR_ECE_Msk /*!<External clock enable */\r
+#define TIM_SMCR_ETP_Pos (15U) \r
+#define TIM_SMCR_ETP_Msk (0x1UL << TIM_SMCR_ETP_Pos) /*!< 0x00008000 */\r
+#define TIM_SMCR_ETP TIM_SMCR_ETP_Msk /*!<External trigger polarity */\r
+\r
+/******************* Bit definition for TIM_DIER register *******************/\r
+#define TIM_DIER_UIE_Pos (0U) \r
+#define TIM_DIER_UIE_Msk (0x1UL << TIM_DIER_UIE_Pos) /*!< 0x00000001 */\r
+#define TIM_DIER_UIE TIM_DIER_UIE_Msk /*!<Update interrupt enable */\r
+#define TIM_DIER_CC1IE_Pos (1U) \r
+#define TIM_DIER_CC1IE_Msk (0x1UL << TIM_DIER_CC1IE_Pos) /*!< 0x00000002 */\r
+#define TIM_DIER_CC1IE TIM_DIER_CC1IE_Msk /*!<Capture/Compare 1 interrupt enable */\r
+#define TIM_DIER_CC2IE_Pos (2U) \r
+#define TIM_DIER_CC2IE_Msk (0x1UL << TIM_DIER_CC2IE_Pos) /*!< 0x00000004 */\r
+#define TIM_DIER_CC2IE TIM_DIER_CC2IE_Msk /*!<Capture/Compare 2 interrupt enable */\r
+#define TIM_DIER_CC3IE_Pos (3U) \r
+#define TIM_DIER_CC3IE_Msk (0x1UL << TIM_DIER_CC3IE_Pos) /*!< 0x00000008 */\r
+#define TIM_DIER_CC3IE TIM_DIER_CC3IE_Msk /*!<Capture/Compare 3 interrupt enable */\r
+#define TIM_DIER_CC4IE_Pos (4U) \r
+#define TIM_DIER_CC4IE_Msk (0x1UL << TIM_DIER_CC4IE_Pos) /*!< 0x00000010 */\r
+#define TIM_DIER_CC4IE TIM_DIER_CC4IE_Msk /*!<Capture/Compare 4 interrupt enable */\r
+#define TIM_DIER_TIE_Pos (6U) \r
+#define TIM_DIER_TIE_Msk (0x1UL << TIM_DIER_TIE_Pos) /*!< 0x00000040 */\r
+#define TIM_DIER_TIE TIM_DIER_TIE_Msk /*!<Trigger interrupt enable */\r
+#define TIM_DIER_UDE_Pos (8U) \r
+#define TIM_DIER_UDE_Msk (0x1UL << TIM_DIER_UDE_Pos) /*!< 0x00000100 */\r
+#define TIM_DIER_UDE TIM_DIER_UDE_Msk /*!<Update DMA request enable */\r
+#define TIM_DIER_CC1DE_Pos (9U) \r
+#define TIM_DIER_CC1DE_Msk (0x1UL << TIM_DIER_CC1DE_Pos) /*!< 0x00000200 */\r
+#define TIM_DIER_CC1DE TIM_DIER_CC1DE_Msk /*!<Capture/Compare 1 DMA request enable */\r
+#define TIM_DIER_CC2DE_Pos (10U) \r
+#define TIM_DIER_CC2DE_Msk (0x1UL << TIM_DIER_CC2DE_Pos) /*!< 0x00000400 */\r
+#define TIM_DIER_CC2DE TIM_DIER_CC2DE_Msk /*!<Capture/Compare 2 DMA request enable */\r
+#define TIM_DIER_CC3DE_Pos (11U) \r
+#define TIM_DIER_CC3DE_Msk (0x1UL << TIM_DIER_CC3DE_Pos) /*!< 0x00000800 */\r
+#define TIM_DIER_CC3DE TIM_DIER_CC3DE_Msk /*!<Capture/Compare 3 DMA request enable */\r
+#define TIM_DIER_CC4DE_Pos (12U) \r
+#define TIM_DIER_CC4DE_Msk (0x1UL << TIM_DIER_CC4DE_Pos) /*!< 0x00001000 */\r
+#define TIM_DIER_CC4DE TIM_DIER_CC4DE_Msk /*!<Capture/Compare 4 DMA request enable */\r
+#define TIM_DIER_COMDE ((uint16_t)0x2000U) /*!<COM DMA request enable */\r
+#define TIM_DIER_TDE_Pos (14U) \r
+#define TIM_DIER_TDE_Msk (0x1UL << TIM_DIER_TDE_Pos) /*!< 0x00004000 */\r
+#define TIM_DIER_TDE TIM_DIER_TDE_Msk /*!<Trigger DMA request enable */\r
+\r
+/******************** Bit definition for TIM_SR register ********************/\r
+#define TIM_SR_UIF_Pos (0U) \r
+#define TIM_SR_UIF_Msk (0x1UL << TIM_SR_UIF_Pos) /*!< 0x00000001 */\r
+#define TIM_SR_UIF TIM_SR_UIF_Msk /*!<Update interrupt Flag */\r
+#define TIM_SR_CC1IF_Pos (1U) \r
+#define TIM_SR_CC1IF_Msk (0x1UL << TIM_SR_CC1IF_Pos) /*!< 0x00000002 */\r
+#define TIM_SR_CC1IF TIM_SR_CC1IF_Msk /*!<Capture/Compare 1 interrupt Flag */\r
+#define TIM_SR_CC2IF_Pos (2U) \r
+#define TIM_SR_CC2IF_Msk (0x1UL << TIM_SR_CC2IF_Pos) /*!< 0x00000004 */\r
+#define TIM_SR_CC2IF TIM_SR_CC2IF_Msk /*!<Capture/Compare 2 interrupt Flag */\r
+#define TIM_SR_CC3IF_Pos (3U) \r
+#define TIM_SR_CC3IF_Msk (0x1UL << TIM_SR_CC3IF_Pos) /*!< 0x00000008 */\r
+#define TIM_SR_CC3IF TIM_SR_CC3IF_Msk /*!<Capture/Compare 3 interrupt Flag */\r
+#define TIM_SR_CC4IF_Pos (4U) \r
+#define TIM_SR_CC4IF_Msk (0x1UL << TIM_SR_CC4IF_Pos) /*!< 0x00000010 */\r
+#define TIM_SR_CC4IF TIM_SR_CC4IF_Msk /*!<Capture/Compare 4 interrupt Flag */\r
+#define TIM_SR_TIF_Pos (6U) \r
+#define TIM_SR_TIF_Msk (0x1UL << TIM_SR_TIF_Pos) /*!< 0x00000040 */\r
+#define TIM_SR_TIF TIM_SR_TIF_Msk /*!<Trigger interrupt Flag */\r
+#define TIM_SR_CC1OF_Pos (9U) \r
+#define TIM_SR_CC1OF_Msk (0x1UL << TIM_SR_CC1OF_Pos) /*!< 0x00000200 */\r
+#define TIM_SR_CC1OF TIM_SR_CC1OF_Msk /*!<Capture/Compare 1 Overcapture Flag */\r
+#define TIM_SR_CC2OF_Pos (10U) \r
+#define TIM_SR_CC2OF_Msk (0x1UL << TIM_SR_CC2OF_Pos) /*!< 0x00000400 */\r
+#define TIM_SR_CC2OF TIM_SR_CC2OF_Msk /*!<Capture/Compare 2 Overcapture Flag */\r
+#define TIM_SR_CC3OF_Pos (11U) \r
+#define TIM_SR_CC3OF_Msk (0x1UL << TIM_SR_CC3OF_Pos) /*!< 0x00000800 */\r
+#define TIM_SR_CC3OF TIM_SR_CC3OF_Msk /*!<Capture/Compare 3 Overcapture Flag */\r
+#define TIM_SR_CC4OF_Pos (12U) \r
+#define TIM_SR_CC4OF_Msk (0x1UL << TIM_SR_CC4OF_Pos) /*!< 0x00001000 */\r
+#define TIM_SR_CC4OF TIM_SR_CC4OF_Msk /*!<Capture/Compare 4 Overcapture Flag */\r
+\r
+/******************* Bit definition for TIM_EGR register ********************/\r
+#define TIM_EGR_UG_Pos (0U) \r
+#define TIM_EGR_UG_Msk (0x1UL << TIM_EGR_UG_Pos) /*!< 0x00000001 */\r
+#define TIM_EGR_UG TIM_EGR_UG_Msk /*!<Update Generation */\r
+#define TIM_EGR_CC1G_Pos (1U) \r
+#define TIM_EGR_CC1G_Msk (0x1UL << TIM_EGR_CC1G_Pos) /*!< 0x00000002 */\r
+#define TIM_EGR_CC1G TIM_EGR_CC1G_Msk /*!<Capture/Compare 1 Generation */\r
+#define TIM_EGR_CC2G_Pos (2U) \r
+#define TIM_EGR_CC2G_Msk (0x1UL << TIM_EGR_CC2G_Pos) /*!< 0x00000004 */\r
+#define TIM_EGR_CC2G TIM_EGR_CC2G_Msk /*!<Capture/Compare 2 Generation */\r
+#define TIM_EGR_CC3G_Pos (3U) \r
+#define TIM_EGR_CC3G_Msk (0x1UL << TIM_EGR_CC3G_Pos) /*!< 0x00000008 */\r
+#define TIM_EGR_CC3G TIM_EGR_CC3G_Msk /*!<Capture/Compare 3 Generation */\r
+#define TIM_EGR_CC4G_Pos (4U) \r
+#define TIM_EGR_CC4G_Msk (0x1UL << TIM_EGR_CC4G_Pos) /*!< 0x00000010 */\r
+#define TIM_EGR_CC4G TIM_EGR_CC4G_Msk /*!<Capture/Compare 4 Generation */\r
+#define TIM_EGR_TG_Pos (6U) \r
+#define TIM_EGR_TG_Msk (0x1UL << TIM_EGR_TG_Pos) /*!< 0x00000040 */\r
+#define TIM_EGR_TG TIM_EGR_TG_Msk /*!<Trigger Generation */\r
+ \r
+/****************** Bit definition for TIM_CCMR1 register *******************/\r
+#define TIM_CCMR1_CC1S_Pos (0U) \r
+#define TIM_CCMR1_CC1S_Msk (0x3UL << TIM_CCMR1_CC1S_Pos) /*!< 0x00000003 */\r
+#define TIM_CCMR1_CC1S TIM_CCMR1_CC1S_Msk /*!<CC1S[1:0] bits (Capture/Compare 1 Selection) */\r
+#define TIM_CCMR1_CC1S_0 (0x1UL << TIM_CCMR1_CC1S_Pos) /*!< 0x00000001 */\r
+#define TIM_CCMR1_CC1S_1 (0x2UL << TIM_CCMR1_CC1S_Pos) /*!< 0x00000002 */\r
+\r
+#define TIM_CCMR1_OC1FE_Pos (2U) \r
+#define TIM_CCMR1_OC1FE_Msk (0x1UL << TIM_CCMR1_OC1FE_Pos) /*!< 0x00000004 */\r
+#define TIM_CCMR1_OC1FE TIM_CCMR1_OC1FE_Msk /*!<Output Compare 1 Fast enable */\r
+#define TIM_CCMR1_OC1PE_Pos (3U) \r
+#define TIM_CCMR1_OC1PE_Msk (0x1UL << TIM_CCMR1_OC1PE_Pos) /*!< 0x00000008 */\r
+#define TIM_CCMR1_OC1PE TIM_CCMR1_OC1PE_Msk /*!<Output Compare 1 Preload enable */\r
+\r
+#define TIM_CCMR1_OC1M_Pos (4U) \r
+#define TIM_CCMR1_OC1M_Msk (0x7UL << TIM_CCMR1_OC1M_Pos) /*!< 0x00000070 */\r
+#define TIM_CCMR1_OC1M TIM_CCMR1_OC1M_Msk /*!<OC1M[2:0] bits (Output Compare 1 Mode) */\r
+#define TIM_CCMR1_OC1M_0 (0x1UL << TIM_CCMR1_OC1M_Pos) /*!< 0x00000010 */\r
+#define TIM_CCMR1_OC1M_1 (0x2UL << TIM_CCMR1_OC1M_Pos) /*!< 0x00000020 */\r
+#define TIM_CCMR1_OC1M_2 (0x4UL << TIM_CCMR1_OC1M_Pos) /*!< 0x00000040 */\r
+\r
+#define TIM_CCMR1_OC1CE_Pos (7U) \r
+#define TIM_CCMR1_OC1CE_Msk (0x1UL << TIM_CCMR1_OC1CE_Pos) /*!< 0x00000080 */\r
+#define TIM_CCMR1_OC1CE TIM_CCMR1_OC1CE_Msk /*!<Output Compare 1Clear Enable */\r
+\r
+#define TIM_CCMR1_CC2S_Pos (8U) \r
+#define TIM_CCMR1_CC2S_Msk (0x3UL << TIM_CCMR1_CC2S_Pos) /*!< 0x00000300 */\r
+#define TIM_CCMR1_CC2S TIM_CCMR1_CC2S_Msk /*!<CC2S[1:0] bits (Capture/Compare 2 Selection) */\r
+#define TIM_CCMR1_CC2S_0 (0x1UL << TIM_CCMR1_CC2S_Pos) /*!< 0x00000100 */\r
+#define TIM_CCMR1_CC2S_1 (0x2UL << TIM_CCMR1_CC2S_Pos) /*!< 0x00000200 */\r
+\r
+#define TIM_CCMR1_OC2FE_Pos (10U) \r
+#define TIM_CCMR1_OC2FE_Msk (0x1UL << TIM_CCMR1_OC2FE_Pos) /*!< 0x00000400 */\r
+#define TIM_CCMR1_OC2FE TIM_CCMR1_OC2FE_Msk /*!<Output Compare 2 Fast enable */\r
+#define TIM_CCMR1_OC2PE_Pos (11U) \r
+#define TIM_CCMR1_OC2PE_Msk (0x1UL << TIM_CCMR1_OC2PE_Pos) /*!< 0x00000800 */\r
+#define TIM_CCMR1_OC2PE TIM_CCMR1_OC2PE_Msk /*!<Output Compare 2 Preload enable */\r
+\r
+#define TIM_CCMR1_OC2M_Pos (12U) \r
+#define TIM_CCMR1_OC2M_Msk (0x7UL << TIM_CCMR1_OC2M_Pos) /*!< 0x00007000 */\r
+#define TIM_CCMR1_OC2M TIM_CCMR1_OC2M_Msk /*!<OC2M[2:0] bits (Output Compare 2 Mode) */\r
+#define TIM_CCMR1_OC2M_0 (0x1UL << TIM_CCMR1_OC2M_Pos) /*!< 0x00001000 */\r
+#define TIM_CCMR1_OC2M_1 (0x2UL << TIM_CCMR1_OC2M_Pos) /*!< 0x00002000 */\r
+#define TIM_CCMR1_OC2M_2 (0x4UL << TIM_CCMR1_OC2M_Pos) /*!< 0x00004000 */\r
+\r
+#define TIM_CCMR1_OC2CE_Pos (15U) \r
+#define TIM_CCMR1_OC2CE_Msk (0x1UL << TIM_CCMR1_OC2CE_Pos) /*!< 0x00008000 */\r
+#define TIM_CCMR1_OC2CE TIM_CCMR1_OC2CE_Msk /*!<Output Compare 2 Clear Enable */\r
+\r
+/*----------------------------------------------------------------------------*/\r
+\r
+#define TIM_CCMR1_IC1PSC_Pos (2U) \r
+#define TIM_CCMR1_IC1PSC_Msk (0x3UL << TIM_CCMR1_IC1PSC_Pos) /*!< 0x0000000C */\r
+#define TIM_CCMR1_IC1PSC TIM_CCMR1_IC1PSC_Msk /*!<IC1PSC[1:0] bits (Input Capture 1 Prescaler) */\r
+#define TIM_CCMR1_IC1PSC_0 (0x1UL << TIM_CCMR1_IC1PSC_Pos) /*!< 0x00000004 */\r
+#define TIM_CCMR1_IC1PSC_1 (0x2UL << TIM_CCMR1_IC1PSC_Pos) /*!< 0x00000008 */\r
+\r
+#define TIM_CCMR1_IC1F_Pos (4U) \r
+#define TIM_CCMR1_IC1F_Msk (0xFUL << TIM_CCMR1_IC1F_Pos) /*!< 0x000000F0 */\r
+#define TIM_CCMR1_IC1F TIM_CCMR1_IC1F_Msk /*!<IC1F[3:0] bits (Input Capture 1 Filter) */\r
+#define TIM_CCMR1_IC1F_0 (0x1UL << TIM_CCMR1_IC1F_Pos) /*!< 0x00000010 */\r
+#define TIM_CCMR1_IC1F_1 (0x2UL << TIM_CCMR1_IC1F_Pos) /*!< 0x00000020 */\r
+#define TIM_CCMR1_IC1F_2 (0x4UL << TIM_CCMR1_IC1F_Pos) /*!< 0x00000040 */\r
+#define TIM_CCMR1_IC1F_3 (0x8UL << TIM_CCMR1_IC1F_Pos) /*!< 0x00000080 */\r
+\r
+#define TIM_CCMR1_IC2PSC_Pos (10U) \r
+#define TIM_CCMR1_IC2PSC_Msk (0x3UL << TIM_CCMR1_IC2PSC_Pos) /*!< 0x00000C00 */\r
+#define TIM_CCMR1_IC2PSC TIM_CCMR1_IC2PSC_Msk /*!<IC2PSC[1:0] bits (Input Capture 2 Prescaler) */\r
+#define TIM_CCMR1_IC2PSC_0 (0x1UL << TIM_CCMR1_IC2PSC_Pos) /*!< 0x00000400 */\r
+#define TIM_CCMR1_IC2PSC_1 (0x2UL << TIM_CCMR1_IC2PSC_Pos) /*!< 0x00000800 */\r
+\r
+#define TIM_CCMR1_IC2F_Pos (12U) \r
+#define TIM_CCMR1_IC2F_Msk (0xFUL << TIM_CCMR1_IC2F_Pos) /*!< 0x0000F000 */\r
+#define TIM_CCMR1_IC2F TIM_CCMR1_IC2F_Msk /*!<IC2F[3:0] bits (Input Capture 2 Filter) */\r
+#define TIM_CCMR1_IC2F_0 (0x1UL << TIM_CCMR1_IC2F_Pos) /*!< 0x00001000 */\r
+#define TIM_CCMR1_IC2F_1 (0x2UL << TIM_CCMR1_IC2F_Pos) /*!< 0x00002000 */\r
+#define TIM_CCMR1_IC2F_2 (0x4UL << TIM_CCMR1_IC2F_Pos) /*!< 0x00004000 */\r
+#define TIM_CCMR1_IC2F_3 (0x8UL << TIM_CCMR1_IC2F_Pos) /*!< 0x00008000 */\r
+\r
+/****************** Bit definition for TIM_CCMR2 register *******************/\r
+#define TIM_CCMR2_CC3S_Pos (0U) \r
+#define TIM_CCMR2_CC3S_Msk (0x3UL << TIM_CCMR2_CC3S_Pos) /*!< 0x00000003 */\r
+#define TIM_CCMR2_CC3S TIM_CCMR2_CC3S_Msk /*!<CC3S[1:0] bits (Capture/Compare 3 Selection) */\r
+#define TIM_CCMR2_CC3S_0 (0x1UL << TIM_CCMR2_CC3S_Pos) /*!< 0x00000001 */\r
+#define TIM_CCMR2_CC3S_1 (0x2UL << TIM_CCMR2_CC3S_Pos) /*!< 0x00000002 */\r
+\r
+#define TIM_CCMR2_OC3FE_Pos (2U) \r
+#define TIM_CCMR2_OC3FE_Msk (0x1UL << TIM_CCMR2_OC3FE_Pos) /*!< 0x00000004 */\r
+#define TIM_CCMR2_OC3FE TIM_CCMR2_OC3FE_Msk /*!<Output Compare 3 Fast enable */\r
+#define TIM_CCMR2_OC3PE_Pos (3U) \r
+#define TIM_CCMR2_OC3PE_Msk (0x1UL << TIM_CCMR2_OC3PE_Pos) /*!< 0x00000008 */\r
+#define TIM_CCMR2_OC3PE TIM_CCMR2_OC3PE_Msk /*!<Output Compare 3 Preload enable */\r
+\r
+#define TIM_CCMR2_OC3M_Pos (4U) \r
+#define TIM_CCMR2_OC3M_Msk (0x7UL << TIM_CCMR2_OC3M_Pos) /*!< 0x00000070 */\r
+#define TIM_CCMR2_OC3M TIM_CCMR2_OC3M_Msk /*!<OC3M[2:0] bits (Output Compare 3 Mode) */\r
+#define TIM_CCMR2_OC3M_0 (0x1UL << TIM_CCMR2_OC3M_Pos) /*!< 0x00000010 */\r
+#define TIM_CCMR2_OC3M_1 (0x2UL << TIM_CCMR2_OC3M_Pos) /*!< 0x00000020 */\r
+#define TIM_CCMR2_OC3M_2 (0x4UL << TIM_CCMR2_OC3M_Pos) /*!< 0x00000040 */\r
+\r
+#define TIM_CCMR2_OC3CE_Pos (7U) \r
+#define TIM_CCMR2_OC3CE_Msk (0x1UL << TIM_CCMR2_OC3CE_Pos) /*!< 0x00000080 */\r
+#define TIM_CCMR2_OC3CE TIM_CCMR2_OC3CE_Msk /*!<Output Compare 3 Clear Enable */\r
+\r
+#define TIM_CCMR2_CC4S_Pos (8U) \r
+#define TIM_CCMR2_CC4S_Msk (0x3UL << TIM_CCMR2_CC4S_Pos) /*!< 0x00000300 */\r
+#define TIM_CCMR2_CC4S TIM_CCMR2_CC4S_Msk /*!<CC4S[1:0] bits (Capture/Compare 4 Selection) */\r
+#define TIM_CCMR2_CC4S_0 (0x1UL << TIM_CCMR2_CC4S_Pos) /*!< 0x00000100 */\r
+#define TIM_CCMR2_CC4S_1 (0x2UL << TIM_CCMR2_CC4S_Pos) /*!< 0x00000200 */\r
+\r
+#define TIM_CCMR2_OC4FE_Pos (10U) \r
+#define TIM_CCMR2_OC4FE_Msk (0x1UL << TIM_CCMR2_OC4FE_Pos) /*!< 0x00000400 */\r
+#define TIM_CCMR2_OC4FE TIM_CCMR2_OC4FE_Msk /*!<Output Compare 4 Fast enable */\r
+#define TIM_CCMR2_OC4PE_Pos (11U) \r
+#define TIM_CCMR2_OC4PE_Msk (0x1UL << TIM_CCMR2_OC4PE_Pos) /*!< 0x00000800 */\r
+#define TIM_CCMR2_OC4PE TIM_CCMR2_OC4PE_Msk /*!<Output Compare 4 Preload enable */\r
+\r
+#define TIM_CCMR2_OC4M_Pos (12U) \r
+#define TIM_CCMR2_OC4M_Msk (0x7UL << TIM_CCMR2_OC4M_Pos) /*!< 0x00007000 */\r
+#define TIM_CCMR2_OC4M TIM_CCMR2_OC4M_Msk /*!<OC4M[2:0] bits (Output Compare 4 Mode) */\r
+#define TIM_CCMR2_OC4M_0 (0x1UL << TIM_CCMR2_OC4M_Pos) /*!< 0x00001000 */\r
+#define TIM_CCMR2_OC4M_1 (0x2UL << TIM_CCMR2_OC4M_Pos) /*!< 0x00002000 */\r
+#define TIM_CCMR2_OC4M_2 (0x4UL << TIM_CCMR2_OC4M_Pos) /*!< 0x00004000 */\r
+\r
+#define TIM_CCMR2_OC4CE_Pos (15U) \r
+#define TIM_CCMR2_OC4CE_Msk (0x1UL << TIM_CCMR2_OC4CE_Pos) /*!< 0x00008000 */\r
+#define TIM_CCMR2_OC4CE TIM_CCMR2_OC4CE_Msk /*!<Output Compare 4 Clear Enable */\r
+\r
+/*----------------------------------------------------------------------------*/\r
+\r
+#define TIM_CCMR2_IC3PSC_Pos (2U) \r
+#define TIM_CCMR2_IC3PSC_Msk (0x3UL << TIM_CCMR2_IC3PSC_Pos) /*!< 0x0000000C */\r
+#define TIM_CCMR2_IC3PSC TIM_CCMR2_IC3PSC_Msk /*!<IC3PSC[1:0] bits (Input Capture 3 Prescaler) */\r
+#define TIM_CCMR2_IC3PSC_0 (0x1UL << TIM_CCMR2_IC3PSC_Pos) /*!< 0x00000004 */\r
+#define TIM_CCMR2_IC3PSC_1 (0x2UL << TIM_CCMR2_IC3PSC_Pos) /*!< 0x00000008 */\r
+\r
+#define TIM_CCMR2_IC3F_Pos (4U) \r
+#define TIM_CCMR2_IC3F_Msk (0xFUL << TIM_CCMR2_IC3F_Pos) /*!< 0x000000F0 */\r
+#define TIM_CCMR2_IC3F TIM_CCMR2_IC3F_Msk /*!<IC3F[3:0] bits (Input Capture 3 Filter) */\r
+#define TIM_CCMR2_IC3F_0 (0x1UL << TIM_CCMR2_IC3F_Pos) /*!< 0x00000010 */\r
+#define TIM_CCMR2_IC3F_1 (0x2UL << TIM_CCMR2_IC3F_Pos) /*!< 0x00000020 */\r
+#define TIM_CCMR2_IC3F_2 (0x4UL << TIM_CCMR2_IC3F_Pos) /*!< 0x00000040 */\r
+#define TIM_CCMR2_IC3F_3 (0x8UL << TIM_CCMR2_IC3F_Pos) /*!< 0x00000080 */\r
+\r
+#define TIM_CCMR2_IC4PSC_Pos (10U) \r
+#define TIM_CCMR2_IC4PSC_Msk (0x3UL << TIM_CCMR2_IC4PSC_Pos) /*!< 0x00000C00 */\r
+#define TIM_CCMR2_IC4PSC TIM_CCMR2_IC4PSC_Msk /*!<IC4PSC[1:0] bits (Input Capture 4 Prescaler) */\r
+#define TIM_CCMR2_IC4PSC_0 (0x1UL << TIM_CCMR2_IC4PSC_Pos) /*!< 0x00000400 */\r
+#define TIM_CCMR2_IC4PSC_1 (0x2UL << TIM_CCMR2_IC4PSC_Pos) /*!< 0x00000800 */\r
+\r
+#define TIM_CCMR2_IC4F_Pos (12U) \r
+#define TIM_CCMR2_IC4F_Msk (0xFUL << TIM_CCMR2_IC4F_Pos) /*!< 0x0000F000 */\r
+#define TIM_CCMR2_IC4F TIM_CCMR2_IC4F_Msk /*!<IC4F[3:0] bits (Input Capture 4 Filter) */\r
+#define TIM_CCMR2_IC4F_0 (0x1UL << TIM_CCMR2_IC4F_Pos) /*!< 0x00001000 */\r
+#define TIM_CCMR2_IC4F_1 (0x2UL << TIM_CCMR2_IC4F_Pos) /*!< 0x00002000 */\r
+#define TIM_CCMR2_IC4F_2 (0x4UL << TIM_CCMR2_IC4F_Pos) /*!< 0x00004000 */\r
+#define TIM_CCMR2_IC4F_3 (0x8UL << TIM_CCMR2_IC4F_Pos) /*!< 0x00008000 */\r
+\r
+/******************* Bit definition for TIM_CCER register *******************/\r
+#define TIM_CCER_CC1E_Pos (0U) \r
+#define TIM_CCER_CC1E_Msk (0x1UL << TIM_CCER_CC1E_Pos) /*!< 0x00000001 */\r
+#define TIM_CCER_CC1E TIM_CCER_CC1E_Msk /*!<Capture/Compare 1 output enable */\r
+#define TIM_CCER_CC1P_Pos (1U) \r
+#define TIM_CCER_CC1P_Msk (0x1UL << TIM_CCER_CC1P_Pos) /*!< 0x00000002 */\r
+#define TIM_CCER_CC1P TIM_CCER_CC1P_Msk /*!<Capture/Compare 1 output Polarity */\r
+#define TIM_CCER_CC1NP_Pos (3U) \r
+#define TIM_CCER_CC1NP_Msk (0x1UL << TIM_CCER_CC1NP_Pos) /*!< 0x00000008 */\r
+#define TIM_CCER_CC1NP TIM_CCER_CC1NP_Msk /*!<Capture/Compare 1 Complementary output Polarity */\r
+#define TIM_CCER_CC2E_Pos (4U) \r
+#define TIM_CCER_CC2E_Msk (0x1UL << TIM_CCER_CC2E_Pos) /*!< 0x00000010 */\r
+#define TIM_CCER_CC2E TIM_CCER_CC2E_Msk /*!<Capture/Compare 2 output enable */\r
+#define TIM_CCER_CC2P_Pos (5U) \r
+#define TIM_CCER_CC2P_Msk (0x1UL << TIM_CCER_CC2P_Pos) /*!< 0x00000020 */\r
+#define TIM_CCER_CC2P TIM_CCER_CC2P_Msk /*!<Capture/Compare 2 output Polarity */\r
+#define TIM_CCER_CC2NP_Pos (7U) \r
+#define TIM_CCER_CC2NP_Msk (0x1UL << TIM_CCER_CC2NP_Pos) /*!< 0x00000080 */\r
+#define TIM_CCER_CC2NP TIM_CCER_CC2NP_Msk /*!<Capture/Compare 2 Complementary output Polarity */\r
+#define TIM_CCER_CC3E_Pos (8U) \r
+#define TIM_CCER_CC3E_Msk (0x1UL << TIM_CCER_CC3E_Pos) /*!< 0x00000100 */\r
+#define TIM_CCER_CC3E TIM_CCER_CC3E_Msk /*!<Capture/Compare 3 output enable */\r
+#define TIM_CCER_CC3P_Pos (9U) \r
+#define TIM_CCER_CC3P_Msk (0x1UL << TIM_CCER_CC3P_Pos) /*!< 0x00000200 */\r
+#define TIM_CCER_CC3P TIM_CCER_CC3P_Msk /*!<Capture/Compare 3 output Polarity */\r
+#define TIM_CCER_CC3NP_Pos (11U) \r
+#define TIM_CCER_CC3NP_Msk (0x1UL << TIM_CCER_CC3NP_Pos) /*!< 0x00000800 */\r
+#define TIM_CCER_CC3NP TIM_CCER_CC3NP_Msk /*!<Capture/Compare 3 Complementary output Polarity */\r
+#define TIM_CCER_CC4E_Pos (12U) \r
+#define TIM_CCER_CC4E_Msk (0x1UL << TIM_CCER_CC4E_Pos) /*!< 0x00001000 */\r
+#define TIM_CCER_CC4E TIM_CCER_CC4E_Msk /*!<Capture/Compare 4 output enable */\r
+#define TIM_CCER_CC4P_Pos (13U) \r
+#define TIM_CCER_CC4P_Msk (0x1UL << TIM_CCER_CC4P_Pos) /*!< 0x00002000 */\r
+#define TIM_CCER_CC4P TIM_CCER_CC4P_Msk /*!<Capture/Compare 4 output Polarity */\r
+#define TIM_CCER_CC4NP_Pos (15U) \r
+#define TIM_CCER_CC4NP_Msk (0x1UL << TIM_CCER_CC4NP_Pos) /*!< 0x00008000 */\r
+#define TIM_CCER_CC4NP TIM_CCER_CC4NP_Msk /*!<Capture/Compare 4 Complementary output Polarity */\r
+\r
+/******************* Bit definition for TIM_CNT register ********************/\r
+#define TIM_CNT_CNT_Pos (0U) \r
+#define TIM_CNT_CNT_Msk (0xFFFFFFFFUL << TIM_CNT_CNT_Pos) /*!< 0xFFFFFFFF */\r
+#define TIM_CNT_CNT TIM_CNT_CNT_Msk /*!<Counter Value */\r
+\r
+/******************* Bit definition for TIM_PSC register ********************/\r
+#define TIM_PSC_PSC_Pos (0U) \r
+#define TIM_PSC_PSC_Msk (0xFFFFUL << TIM_PSC_PSC_Pos) /*!< 0x0000FFFF */\r
+#define TIM_PSC_PSC TIM_PSC_PSC_Msk /*!<Prescaler Value */\r
+\r
+/******************* Bit definition for TIM_ARR register ********************/\r
+#define TIM_ARR_ARR_Pos (0U) \r
+#define TIM_ARR_ARR_Msk (0xFFFFFFFFUL << TIM_ARR_ARR_Pos) /*!< 0xFFFFFFFF */\r
+#define TIM_ARR_ARR TIM_ARR_ARR_Msk /*!<actual auto-reload Value */\r
+ \r
+/******************* Bit definition for TIM_CCR1 register *******************/\r
+#define TIM_CCR1_CCR1_Pos (0U) \r
+#define TIM_CCR1_CCR1_Msk (0xFFFFUL << TIM_CCR1_CCR1_Pos) /*!< 0x0000FFFF */\r
+#define TIM_CCR1_CCR1 TIM_CCR1_CCR1_Msk /*!<Capture/Compare 1 Value */\r
+\r
+/******************* Bit definition for TIM_CCR2 register *******************/\r
+#define TIM_CCR2_CCR2_Pos (0U) \r
+#define TIM_CCR2_CCR2_Msk (0xFFFFUL << TIM_CCR2_CCR2_Pos) /*!< 0x0000FFFF */\r
+#define TIM_CCR2_CCR2 TIM_CCR2_CCR2_Msk /*!<Capture/Compare 2 Value */\r
+\r
+/******************* Bit definition for TIM_CCR3 register *******************/\r
+#define TIM_CCR3_CCR3_Pos (0U) \r
+#define TIM_CCR3_CCR3_Msk (0xFFFFUL << TIM_CCR3_CCR3_Pos) /*!< 0x0000FFFF */\r
+#define TIM_CCR3_CCR3 TIM_CCR3_CCR3_Msk /*!<Capture/Compare 3 Value */\r
+\r
+/******************* Bit definition for TIM_CCR4 register *******************/\r
+#define TIM_CCR4_CCR4_Pos (0U) \r
+#define TIM_CCR4_CCR4_Msk (0xFFFFUL << TIM_CCR4_CCR4_Pos) /*!< 0x0000FFFF */\r
+#define TIM_CCR4_CCR4 TIM_CCR4_CCR4_Msk /*!<Capture/Compare 4 Value */\r
+\r
+/******************* Bit definition for TIM_DCR register ********************/\r
+#define TIM_DCR_DBA_Pos (0U) \r
+#define TIM_DCR_DBA_Msk (0x1FUL << TIM_DCR_DBA_Pos) /*!< 0x0000001F */\r
+#define TIM_DCR_DBA TIM_DCR_DBA_Msk /*!<DBA[4:0] bits (DMA Base Address) */\r
+#define TIM_DCR_DBA_0 (0x01UL << TIM_DCR_DBA_Pos) /*!< 0x00000001 */\r
+#define TIM_DCR_DBA_1 (0x02UL << TIM_DCR_DBA_Pos) /*!< 0x00000002 */\r
+#define TIM_DCR_DBA_2 (0x04UL << TIM_DCR_DBA_Pos) /*!< 0x00000004 */\r
+#define TIM_DCR_DBA_3 (0x08UL << TIM_DCR_DBA_Pos) /*!< 0x00000008 */\r
+#define TIM_DCR_DBA_4 (0x10UL << TIM_DCR_DBA_Pos) /*!< 0x00000010 */\r
+\r
+#define TIM_DCR_DBL_Pos (8U) \r
+#define TIM_DCR_DBL_Msk (0x1FUL << TIM_DCR_DBL_Pos) /*!< 0x00001F00 */\r
+#define TIM_DCR_DBL TIM_DCR_DBL_Msk /*!<DBL[4:0] bits (DMA Burst Length) */\r
+#define TIM_DCR_DBL_0 (0x01UL << TIM_DCR_DBL_Pos) /*!< 0x00000100 */\r
+#define TIM_DCR_DBL_1 (0x02UL << TIM_DCR_DBL_Pos) /*!< 0x00000200 */\r
+#define TIM_DCR_DBL_2 (0x04UL << TIM_DCR_DBL_Pos) /*!< 0x00000400 */\r
+#define TIM_DCR_DBL_3 (0x08UL << TIM_DCR_DBL_Pos) /*!< 0x00000800 */\r
+#define TIM_DCR_DBL_4 (0x10UL << TIM_DCR_DBL_Pos) /*!< 0x00001000 */\r
+\r
+/******************* Bit definition for TIM_DMAR register *******************/\r
+#define TIM_DMAR_DMAB_Pos (0U) \r
+#define TIM_DMAR_DMAB_Msk (0xFFFFUL << TIM_DMAR_DMAB_Pos) /*!< 0x0000FFFF */\r
+#define TIM_DMAR_DMAB TIM_DMAR_DMAB_Msk /*!<DMA register for burst accesses */\r
+\r
+/******************* Bit definition for TIM_OR register *********************/\r
+#define TIM_OR_TI1RMP_Pos (0U) \r
+#define TIM_OR_TI1RMP_Msk (0x3UL << TIM_OR_TI1RMP_Pos) /*!< 0x00000003 */\r
+#define TIM_OR_TI1RMP TIM_OR_TI1RMP_Msk /*!<TI1_RMP[1:0] bits (TIM Input 1 remap) */\r
+#define TIM_OR_TI1RMP_0 (0x1UL << TIM_OR_TI1RMP_Pos) /*!< 0x00000001 */\r
+#define TIM_OR_TI1RMP_1 (0x2UL << TIM_OR_TI1RMP_Pos) /*!< 0x00000002 */\r
+\r
+#define TIM_OR_ETR_RMP_Pos (2U) \r
+#define TIM_OR_ETR_RMP_Msk (0x1UL << TIM_OR_ETR_RMP_Pos) /*!< 0x00000004 */\r
+#define TIM_OR_ETR_RMP TIM_OR_ETR_RMP_Msk /*!<ETR_RMP bit (TIM10/11 ETR remap)*/\r
+#define TIM_OR_TI1_RMP_RI_Pos (3U) \r
+#define TIM_OR_TI1_RMP_RI_Msk (0x1UL << TIM_OR_TI1_RMP_RI_Pos) /*!< 0x00000008 */\r
+#define TIM_OR_TI1_RMP_RI TIM_OR_TI1_RMP_RI_Msk /*!<TI1_RMP_RI bit (TIM10/11 Input 1 remap for Routing interface) */\r
+\r
+/*----------------------------------------------------------------------------*/\r
+#define TIM9_OR_ITR1_RMP_Pos (2U) \r
+#define TIM9_OR_ITR1_RMP_Msk (0x1UL << TIM9_OR_ITR1_RMP_Pos) /*!< 0x00000004 */\r
+#define TIM9_OR_ITR1_RMP TIM9_OR_ITR1_RMP_Msk /*!<ITR1_RMP bit (TIM9 Internal trigger 1 remap) */\r
+\r
+/*----------------------------------------------------------------------------*/\r
+#define TIM2_OR_ITR1_RMP_Pos (0U) \r
+#define TIM2_OR_ITR1_RMP_Msk (0x1UL << TIM2_OR_ITR1_RMP_Pos) /*!< 0x00000001 */\r
+#define TIM2_OR_ITR1_RMP TIM2_OR_ITR1_RMP_Msk /*!<ITR1_RMP bit (TIM2 Internal trigger 1 remap) */\r
+\r
+/*----------------------------------------------------------------------------*/\r
+#define TIM3_OR_ITR2_RMP_Pos (0U) \r
+#define TIM3_OR_ITR2_RMP_Msk (0x1UL << TIM3_OR_ITR2_RMP_Pos) /*!< 0x00000001 */\r
+#define TIM3_OR_ITR2_RMP TIM3_OR_ITR2_RMP_Msk /*!<ITR2_RMP bit (TIM3 Internal trigger 2 remap) */\r
+\r
+/*----------------------------------------------------------------------------*/\r
+\r
+/******************************************************************************/\r
+/* */\r
+/* Universal Synchronous Asynchronous Receiver Transmitter (USART) */\r
+/* */\r
+/******************************************************************************/\r
+\r
+/******************* Bit definition for USART_SR register *******************/\r
+#define USART_SR_PE_Pos (0U) \r
+#define USART_SR_PE_Msk (0x1UL << USART_SR_PE_Pos) /*!< 0x00000001 */\r
+#define USART_SR_PE USART_SR_PE_Msk /*!< Parity Error */\r
+#define USART_SR_FE_Pos (1U) \r
+#define USART_SR_FE_Msk (0x1UL << USART_SR_FE_Pos) /*!< 0x00000002 */\r
+#define USART_SR_FE USART_SR_FE_Msk /*!< Framing Error */\r
+#define USART_SR_NE_Pos (2U) \r
+#define USART_SR_NE_Msk (0x1UL << USART_SR_NE_Pos) /*!< 0x00000004 */\r
+#define USART_SR_NE USART_SR_NE_Msk /*!< Noise Error Flag */\r
+#define USART_SR_ORE_Pos (3U) \r
+#define USART_SR_ORE_Msk (0x1UL << USART_SR_ORE_Pos) /*!< 0x00000008 */\r
+#define USART_SR_ORE USART_SR_ORE_Msk /*!< OverRun Error */\r
+#define USART_SR_IDLE_Pos (4U) \r
+#define USART_SR_IDLE_Msk (0x1UL << USART_SR_IDLE_Pos) /*!< 0x00000010 */\r
+#define USART_SR_IDLE USART_SR_IDLE_Msk /*!< IDLE line detected */\r
+#define USART_SR_RXNE_Pos (5U) \r
+#define USART_SR_RXNE_Msk (0x1UL << USART_SR_RXNE_Pos) /*!< 0x00000020 */\r
+#define USART_SR_RXNE USART_SR_RXNE_Msk /*!< Read Data Register Not Empty */\r
+#define USART_SR_TC_Pos (6U) \r
+#define USART_SR_TC_Msk (0x1UL << USART_SR_TC_Pos) /*!< 0x00000040 */\r
+#define USART_SR_TC USART_SR_TC_Msk /*!< Transmission Complete */\r
+#define USART_SR_TXE_Pos (7U) \r
+#define USART_SR_TXE_Msk (0x1UL << USART_SR_TXE_Pos) /*!< 0x00000080 */\r
+#define USART_SR_TXE USART_SR_TXE_Msk /*!< Transmit Data Register Empty */\r
+#define USART_SR_LBD_Pos (8U) \r
+#define USART_SR_LBD_Msk (0x1UL << USART_SR_LBD_Pos) /*!< 0x00000100 */\r
+#define USART_SR_LBD USART_SR_LBD_Msk /*!< LIN Break Detection Flag */\r
+#define USART_SR_CTS_Pos (9U) \r
+#define USART_SR_CTS_Msk (0x1UL << USART_SR_CTS_Pos) /*!< 0x00000200 */\r
+#define USART_SR_CTS USART_SR_CTS_Msk /*!< CTS Flag */\r
+\r
+/******************* Bit definition for USART_DR register *******************/\r
+#define USART_DR_DR_Pos (0U) \r
+#define USART_DR_DR_Msk (0x1FFUL << USART_DR_DR_Pos) /*!< 0x000001FF */\r
+#define USART_DR_DR USART_DR_DR_Msk /*!< Data value */\r
+\r
+/****************** Bit definition for USART_BRR register *******************/\r
+#define USART_BRR_DIV_FRACTION_Pos (0U) \r
+#define USART_BRR_DIV_FRACTION_Msk (0xFUL << USART_BRR_DIV_FRACTION_Pos) /*!< 0x0000000F */\r
+#define USART_BRR_DIV_FRACTION USART_BRR_DIV_FRACTION_Msk /*!< Fraction of USARTDIV */\r
+#define USART_BRR_DIV_MANTISSA_Pos (4U) \r
+#define USART_BRR_DIV_MANTISSA_Msk (0xFFFUL << USART_BRR_DIV_MANTISSA_Pos) /*!< 0x0000FFF0 */\r
+#define USART_BRR_DIV_MANTISSA USART_BRR_DIV_MANTISSA_Msk /*!< Mantissa of USARTDIV */\r
+\r
+/****************** Bit definition for USART_CR1 register *******************/\r
+#define USART_CR1_SBK_Pos (0U) \r
+#define USART_CR1_SBK_Msk (0x1UL << USART_CR1_SBK_Pos) /*!< 0x00000001 */\r
+#define USART_CR1_SBK USART_CR1_SBK_Msk /*!< Send Break */\r
+#define USART_CR1_RWU_Pos (1U) \r
+#define USART_CR1_RWU_Msk (0x1UL << USART_CR1_RWU_Pos) /*!< 0x00000002 */\r
+#define USART_CR1_RWU USART_CR1_RWU_Msk /*!< Receiver wakeup */\r
+#define USART_CR1_RE_Pos (2U) \r
+#define USART_CR1_RE_Msk (0x1UL << USART_CR1_RE_Pos) /*!< 0x00000004 */\r
+#define USART_CR1_RE USART_CR1_RE_Msk /*!< Receiver Enable */\r
+#define USART_CR1_TE_Pos (3U) \r
+#define USART_CR1_TE_Msk (0x1UL << USART_CR1_TE_Pos) /*!< 0x00000008 */\r
+#define USART_CR1_TE USART_CR1_TE_Msk /*!< Transmitter Enable */\r
+#define USART_CR1_IDLEIE_Pos (4U) \r
+#define USART_CR1_IDLEIE_Msk (0x1UL << USART_CR1_IDLEIE_Pos) /*!< 0x00000010 */\r
+#define USART_CR1_IDLEIE USART_CR1_IDLEIE_Msk /*!< IDLE Interrupt Enable */\r
+#define USART_CR1_RXNEIE_Pos (5U) \r
+#define USART_CR1_RXNEIE_Msk (0x1UL << USART_CR1_RXNEIE_Pos) /*!< 0x00000020 */\r
+#define USART_CR1_RXNEIE USART_CR1_RXNEIE_Msk /*!< RXNE Interrupt Enable */\r
+#define USART_CR1_TCIE_Pos (6U) \r
+#define USART_CR1_TCIE_Msk (0x1UL << USART_CR1_TCIE_Pos) /*!< 0x00000040 */\r
+#define USART_CR1_TCIE USART_CR1_TCIE_Msk /*!< Transmission Complete Interrupt Enable */\r
+#define USART_CR1_TXEIE_Pos (7U) \r
+#define USART_CR1_TXEIE_Msk (0x1UL << USART_CR1_TXEIE_Pos) /*!< 0x00000080 */\r
+#define USART_CR1_TXEIE USART_CR1_TXEIE_Msk /*!< PE Interrupt Enable */\r
+#define USART_CR1_PEIE_Pos (8U) \r
+#define USART_CR1_PEIE_Msk (0x1UL << USART_CR1_PEIE_Pos) /*!< 0x00000100 */\r
+#define USART_CR1_PEIE USART_CR1_PEIE_Msk /*!< PE Interrupt Enable */\r
+#define USART_CR1_PS_Pos (9U) \r
+#define USART_CR1_PS_Msk (0x1UL << USART_CR1_PS_Pos) /*!< 0x00000200 */\r
+#define USART_CR1_PS USART_CR1_PS_Msk /*!< Parity Selection */\r
+#define USART_CR1_PCE_Pos (10U) \r
+#define USART_CR1_PCE_Msk (0x1UL << USART_CR1_PCE_Pos) /*!< 0x00000400 */\r
+#define USART_CR1_PCE USART_CR1_PCE_Msk /*!< Parity Control Enable */\r
+#define USART_CR1_WAKE_Pos (11U) \r
+#define USART_CR1_WAKE_Msk (0x1UL << USART_CR1_WAKE_Pos) /*!< 0x00000800 */\r
+#define USART_CR1_WAKE USART_CR1_WAKE_Msk /*!< Wakeup method */\r
+#define USART_CR1_M_Pos (12U) \r
+#define USART_CR1_M_Msk (0x1UL << USART_CR1_M_Pos) /*!< 0x00001000 */\r
+#define USART_CR1_M USART_CR1_M_Msk /*!< Word length */\r
+#define USART_CR1_UE_Pos (13U) \r
+#define USART_CR1_UE_Msk (0x1UL << USART_CR1_UE_Pos) /*!< 0x00002000 */\r
+#define USART_CR1_UE USART_CR1_UE_Msk /*!< USART Enable */\r
+#define USART_CR1_OVER8_Pos (15U) \r
+#define USART_CR1_OVER8_Msk (0x1UL << USART_CR1_OVER8_Pos) /*!< 0x00008000 */\r
+#define USART_CR1_OVER8 USART_CR1_OVER8_Msk /*!< Oversampling by 8-bit mode */\r
+\r
+/****************** Bit definition for USART_CR2 register *******************/\r
+#define USART_CR2_ADD_Pos (0U) \r
+#define USART_CR2_ADD_Msk (0xFUL << USART_CR2_ADD_Pos) /*!< 0x0000000F */\r
+#define USART_CR2_ADD USART_CR2_ADD_Msk /*!< Address of the USART node */\r
+#define USART_CR2_LBDL_Pos (5U) \r
+#define USART_CR2_LBDL_Msk (0x1UL << USART_CR2_LBDL_Pos) /*!< 0x00000020 */\r
+#define USART_CR2_LBDL USART_CR2_LBDL_Msk /*!< LIN Break Detection Length */\r
+#define USART_CR2_LBDIE_Pos (6U) \r
+#define USART_CR2_LBDIE_Msk (0x1UL << USART_CR2_LBDIE_Pos) /*!< 0x00000040 */\r
+#define USART_CR2_LBDIE USART_CR2_LBDIE_Msk /*!< LIN Break Detection Interrupt Enable */\r
+#define USART_CR2_LBCL_Pos (8U) \r
+#define USART_CR2_LBCL_Msk (0x1UL << USART_CR2_LBCL_Pos) /*!< 0x00000100 */\r
+#define USART_CR2_LBCL USART_CR2_LBCL_Msk /*!< Last Bit Clock pulse */\r
+#define USART_CR2_CPHA_Pos (9U) \r
+#define USART_CR2_CPHA_Msk (0x1UL << USART_CR2_CPHA_Pos) /*!< 0x00000200 */\r
+#define USART_CR2_CPHA USART_CR2_CPHA_Msk /*!< Clock Phase */\r
+#define USART_CR2_CPOL_Pos (10U) \r
+#define USART_CR2_CPOL_Msk (0x1UL << USART_CR2_CPOL_Pos) /*!< 0x00000400 */\r
+#define USART_CR2_CPOL USART_CR2_CPOL_Msk /*!< Clock Polarity */\r
+#define USART_CR2_CLKEN_Pos (11U) \r
+#define USART_CR2_CLKEN_Msk (0x1UL << USART_CR2_CLKEN_Pos) /*!< 0x00000800 */\r
+#define USART_CR2_CLKEN USART_CR2_CLKEN_Msk /*!< Clock Enable */\r
+\r
+#define USART_CR2_STOP_Pos (12U) \r
+#define USART_CR2_STOP_Msk (0x3UL << USART_CR2_STOP_Pos) /*!< 0x00003000 */\r
+#define USART_CR2_STOP USART_CR2_STOP_Msk /*!< STOP[1:0] bits (STOP bits) */\r
+#define USART_CR2_STOP_0 (0x1UL << USART_CR2_STOP_Pos) /*!< 0x00001000 */\r
+#define USART_CR2_STOP_1 (0x2UL << USART_CR2_STOP_Pos) /*!< 0x00002000 */\r
+\r
+#define USART_CR2_LINEN_Pos (14U) \r
+#define USART_CR2_LINEN_Msk (0x1UL << USART_CR2_LINEN_Pos) /*!< 0x00004000 */\r
+#define USART_CR2_LINEN USART_CR2_LINEN_Msk /*!< LIN mode enable */\r
+\r
+/****************** Bit definition for USART_CR3 register *******************/\r
+#define USART_CR3_EIE_Pos (0U) \r
+#define USART_CR3_EIE_Msk (0x1UL << USART_CR3_EIE_Pos) /*!< 0x00000001 */\r
+#define USART_CR3_EIE USART_CR3_EIE_Msk /*!< Error Interrupt Enable */\r
+#define USART_CR3_IREN_Pos (1U) \r
+#define USART_CR3_IREN_Msk (0x1UL << USART_CR3_IREN_Pos) /*!< 0x00000002 */\r
+#define USART_CR3_IREN USART_CR3_IREN_Msk /*!< IrDA mode Enable */\r
+#define USART_CR3_IRLP_Pos (2U) \r
+#define USART_CR3_IRLP_Msk (0x1UL << USART_CR3_IRLP_Pos) /*!< 0x00000004 */\r
+#define USART_CR3_IRLP USART_CR3_IRLP_Msk /*!< IrDA Low-Power */\r
+#define USART_CR3_HDSEL_Pos (3U) \r
+#define USART_CR3_HDSEL_Msk (0x1UL << USART_CR3_HDSEL_Pos) /*!< 0x00000008 */\r
+#define USART_CR3_HDSEL USART_CR3_HDSEL_Msk /*!< Half-Duplex Selection */\r
+#define USART_CR3_NACK_Pos (4U) \r
+#define USART_CR3_NACK_Msk (0x1UL << USART_CR3_NACK_Pos) /*!< 0x00000010 */\r
+#define USART_CR3_NACK USART_CR3_NACK_Msk /*!< Smartcard NACK enable */\r
+#define USART_CR3_SCEN_Pos (5U) \r
+#define USART_CR3_SCEN_Msk (0x1UL << USART_CR3_SCEN_Pos) /*!< 0x00000020 */\r
+#define USART_CR3_SCEN USART_CR3_SCEN_Msk /*!< Smartcard mode enable */\r
+#define USART_CR3_DMAR_Pos (6U) \r
+#define USART_CR3_DMAR_Msk (0x1UL << USART_CR3_DMAR_Pos) /*!< 0x00000040 */\r
+#define USART_CR3_DMAR USART_CR3_DMAR_Msk /*!< DMA Enable Receiver */\r
+#define USART_CR3_DMAT_Pos (7U) \r
+#define USART_CR3_DMAT_Msk (0x1UL << USART_CR3_DMAT_Pos) /*!< 0x00000080 */\r
+#define USART_CR3_DMAT USART_CR3_DMAT_Msk /*!< DMA Enable Transmitter */\r
+#define USART_CR3_RTSE_Pos (8U) \r
+#define USART_CR3_RTSE_Msk (0x1UL << USART_CR3_RTSE_Pos) /*!< 0x00000100 */\r
+#define USART_CR3_RTSE USART_CR3_RTSE_Msk /*!< RTS Enable */\r
+#define USART_CR3_CTSE_Pos (9U) \r
+#define USART_CR3_CTSE_Msk (0x1UL << USART_CR3_CTSE_Pos) /*!< 0x00000200 */\r
+#define USART_CR3_CTSE USART_CR3_CTSE_Msk /*!< CTS Enable */\r
+#define USART_CR3_CTSIE_Pos (10U) \r
+#define USART_CR3_CTSIE_Msk (0x1UL << USART_CR3_CTSIE_Pos) /*!< 0x00000400 */\r
+#define USART_CR3_CTSIE USART_CR3_CTSIE_Msk /*!< CTS Interrupt Enable */\r
+#define USART_CR3_ONEBIT_Pos (11U) \r
+#define USART_CR3_ONEBIT_Msk (0x1UL << USART_CR3_ONEBIT_Pos) /*!< 0x00000800 */\r
+#define USART_CR3_ONEBIT USART_CR3_ONEBIT_Msk /*!< One sample bit method enable */\r
+\r
+/****************** Bit definition for USART_GTPR register ******************/\r
+#define USART_GTPR_PSC_Pos (0U) \r
+#define USART_GTPR_PSC_Msk (0xFFUL << USART_GTPR_PSC_Pos) /*!< 0x000000FF */\r
+#define USART_GTPR_PSC USART_GTPR_PSC_Msk /*!< PSC[7:0] bits (Prescaler value) */\r
+#define USART_GTPR_PSC_0 (0x01UL << USART_GTPR_PSC_Pos) /*!< 0x00000001 */\r
+#define USART_GTPR_PSC_1 (0x02UL << USART_GTPR_PSC_Pos) /*!< 0x00000002 */\r
+#define USART_GTPR_PSC_2 (0x04UL << USART_GTPR_PSC_Pos) /*!< 0x00000004 */\r
+#define USART_GTPR_PSC_3 (0x08UL << USART_GTPR_PSC_Pos) /*!< 0x00000008 */\r
+#define USART_GTPR_PSC_4 (0x10UL << USART_GTPR_PSC_Pos) /*!< 0x00000010 */\r
+#define USART_GTPR_PSC_5 (0x20UL << USART_GTPR_PSC_Pos) /*!< 0x00000020 */\r
+#define USART_GTPR_PSC_6 (0x40UL << USART_GTPR_PSC_Pos) /*!< 0x00000040 */\r
+#define USART_GTPR_PSC_7 (0x80UL << USART_GTPR_PSC_Pos) /*!< 0x00000080 */\r
+\r
+#define USART_GTPR_GT_Pos (8U) \r
+#define USART_GTPR_GT_Msk (0xFFUL << USART_GTPR_GT_Pos) /*!< 0x0000FF00 */\r
+#define USART_GTPR_GT USART_GTPR_GT_Msk /*!< Guard time value */\r
+\r
+/******************************************************************************/\r
+/* */\r
+/* Universal Serial Bus (USB) */\r
+/* */\r
+/******************************************************************************/\r
+\r
+/*!<Endpoint-specific registers */\r
+\r
+#define USB_EP0R USB_BASE /*!< endpoint 0 register address */\r
+#define USB_EP1R (USB_BASE + 0x00000004U) /*!< endpoint 1 register address */\r
+#define USB_EP2R (USB_BASE + 0x00000008U) /*!< endpoint 2 register address */\r
+#define USB_EP3R (USB_BASE + 0x0000000CU) /*!< endpoint 3 register address */\r
+#define USB_EP4R (USB_BASE + 0x00000010U) /*!< endpoint 4 register address */\r
+#define USB_EP5R (USB_BASE + 0x00000014U) /*!< endpoint 5 register address */\r
+#define USB_EP6R (USB_BASE + 0x00000018U) /*!< endpoint 6 register address */\r
+#define USB_EP7R (USB_BASE + 0x0000001CU) /*!< endpoint 7 register address */\r
+\r
+/* bit positions */ \r
+#define USB_EP_CTR_RX_Pos (15U) \r
+#define USB_EP_CTR_RX_Msk (0x1UL << USB_EP_CTR_RX_Pos) /*!< 0x00008000 */\r
+#define USB_EP_CTR_RX USB_EP_CTR_RX_Msk /*!< EndPoint Correct TRansfer RX */\r
+#define USB_EP_DTOG_RX_Pos (14U) \r
+#define USB_EP_DTOG_RX_Msk (0x1UL << USB_EP_DTOG_RX_Pos) /*!< 0x00004000 */\r
+#define USB_EP_DTOG_RX USB_EP_DTOG_RX_Msk /*!< EndPoint Data TOGGLE RX */\r
+#define USB_EPRX_STAT_Pos (12U) \r
+#define USB_EPRX_STAT_Msk (0x3UL << USB_EPRX_STAT_Pos) /*!< 0x00003000 */\r
+#define USB_EPRX_STAT USB_EPRX_STAT_Msk /*!< EndPoint RX STATus bit field */\r
+#define USB_EP_SETUP_Pos (11U) \r
+#define USB_EP_SETUP_Msk (0x1UL << USB_EP_SETUP_Pos) /*!< 0x00000800 */\r
+#define USB_EP_SETUP USB_EP_SETUP_Msk /*!< EndPoint SETUP */\r
+#define USB_EP_T_FIELD_Pos (9U) \r
+#define USB_EP_T_FIELD_Msk (0x3UL << USB_EP_T_FIELD_Pos) /*!< 0x00000600 */\r
+#define USB_EP_T_FIELD USB_EP_T_FIELD_Msk /*!< EndPoint TYPE */\r
+#define USB_EP_KIND_Pos (8U) \r
+#define USB_EP_KIND_Msk (0x1UL << USB_EP_KIND_Pos) /*!< 0x00000100 */\r
+#define USB_EP_KIND USB_EP_KIND_Msk /*!< EndPoint KIND */\r
+#define USB_EP_CTR_TX_Pos (7U) \r
+#define USB_EP_CTR_TX_Msk (0x1UL << USB_EP_CTR_TX_Pos) /*!< 0x00000080 */\r
+#define USB_EP_CTR_TX USB_EP_CTR_TX_Msk /*!< EndPoint Correct TRansfer TX */\r
+#define USB_EP_DTOG_TX_Pos (6U) \r
+#define USB_EP_DTOG_TX_Msk (0x1UL << USB_EP_DTOG_TX_Pos) /*!< 0x00000040 */\r
+#define USB_EP_DTOG_TX USB_EP_DTOG_TX_Msk /*!< EndPoint Data TOGGLE TX */\r
+#define USB_EPTX_STAT_Pos (4U) \r
+#define USB_EPTX_STAT_Msk (0x3UL << USB_EPTX_STAT_Pos) /*!< 0x00000030 */\r
+#define USB_EPTX_STAT USB_EPTX_STAT_Msk /*!< EndPoint TX STATus bit field */\r
+#define USB_EPADDR_FIELD_Pos (0U) \r
+#define USB_EPADDR_FIELD_Msk (0xFUL << USB_EPADDR_FIELD_Pos) /*!< 0x0000000F */\r
+#define USB_EPADDR_FIELD USB_EPADDR_FIELD_Msk /*!< EndPoint ADDRess FIELD */\r
+\r
+/* EndPoint REGister MASK (no toggle fields) */\r
+#define USB_EPREG_MASK (USB_EP_CTR_RX|USB_EP_SETUP|USB_EP_T_FIELD|USB_EP_KIND|USB_EP_CTR_TX|USB_EPADDR_FIELD)\r
+ /*!< EP_TYPE[1:0] EndPoint TYPE */\r
+#define USB_EP_TYPE_MASK_Pos (9U) \r
+#define USB_EP_TYPE_MASK_Msk (0x3UL << USB_EP_TYPE_MASK_Pos) /*!< 0x00000600 */\r
+#define USB_EP_TYPE_MASK USB_EP_TYPE_MASK_Msk /*!< EndPoint TYPE Mask */\r
+#define USB_EP_BULK (0x00000000U) /*!< EndPoint BULK */\r
+#define USB_EP_CONTROL (0x00000200U) /*!< EndPoint CONTROL */\r
+#define USB_EP_ISOCHRONOUS (0x00000400U) /*!< EndPoint ISOCHRONOUS */\r
+#define USB_EP_INTERRUPT (0x00000600U) /*!< EndPoint INTERRUPT */\r
+#define USB_EP_T_MASK (~USB_EP_T_FIELD & USB_EPREG_MASK)\r
+ \r
+#define USB_EPKIND_MASK (~USB_EP_KIND & USB_EPREG_MASK) /*!< EP_KIND EndPoint KIND */\r
+ /*!< STAT_TX[1:0] STATus for TX transfer */\r
+#define USB_EP_TX_DIS (0x00000000U) /*!< EndPoint TX DISabled */\r
+#define USB_EP_TX_STALL (0x00000010U) /*!< EndPoint TX STALLed */\r
+#define USB_EP_TX_NAK (0x00000020U) /*!< EndPoint TX NAKed */\r
+#define USB_EP_TX_VALID (0x00000030U) /*!< EndPoint TX VALID */\r
+#define USB_EPTX_DTOG1 (0x00000010U) /*!< EndPoint TX Data TOGgle bit1 */\r
+#define USB_EPTX_DTOG2 (0x00000020U) /*!< EndPoint TX Data TOGgle bit2 */\r
+#define USB_EPTX_DTOGMASK (USB_EPTX_STAT|USB_EPREG_MASK)\r
+ /*!< STAT_RX[1:0] STATus for RX transfer */\r
+#define USB_EP_RX_DIS (0x00000000U) /*!< EndPoint RX DISabled */\r
+#define USB_EP_RX_STALL (0x00001000U) /*!< EndPoint RX STALLed */\r
+#define USB_EP_RX_NAK (0x00002000U) /*!< EndPoint RX NAKed */\r
+#define USB_EP_RX_VALID (0x00003000U) /*!< EndPoint RX VALID */\r
+#define USB_EPRX_DTOG1 (0x00001000U) /*!< EndPoint RX Data TOGgle bit1 */\r
+#define USB_EPRX_DTOG2 (0x00002000U) /*!< EndPoint RX Data TOGgle bit1 */\r
+#define USB_EPRX_DTOGMASK (USB_EPRX_STAT|USB_EPREG_MASK)\r
+\r
+/******************* Bit definition for USB_EP0R register *******************/\r
+#define USB_EP0R_EA_Pos (0U) \r
+#define USB_EP0R_EA_Msk (0xFUL << USB_EP0R_EA_Pos) /*!< 0x0000000F */\r
+#define USB_EP0R_EA USB_EP0R_EA_Msk /*!<Endpoint Address */\r
+\r
+#define USB_EP0R_STAT_TX_Pos (4U) \r
+#define USB_EP0R_STAT_TX_Msk (0x3UL << USB_EP0R_STAT_TX_Pos) /*!< 0x00000030 */\r
+#define USB_EP0R_STAT_TX USB_EP0R_STAT_TX_Msk /*!<STAT_TX[1:0] bits (Status bits, for transmission transfers) */\r
+#define USB_EP0R_STAT_TX_0 (0x1UL << USB_EP0R_STAT_TX_Pos) /*!< 0x00000010 */\r
+#define USB_EP0R_STAT_TX_1 (0x2UL << USB_EP0R_STAT_TX_Pos) /*!< 0x00000020 */\r
+\r
+#define USB_EP0R_DTOG_TX_Pos (6U) \r
+#define USB_EP0R_DTOG_TX_Msk (0x1UL << USB_EP0R_DTOG_TX_Pos) /*!< 0x00000040 */\r
+#define USB_EP0R_DTOG_TX USB_EP0R_DTOG_TX_Msk /*!<Data Toggle, for transmission transfers */\r
+#define USB_EP0R_CTR_TX_Pos (7U) \r
+#define USB_EP0R_CTR_TX_Msk (0x1UL << USB_EP0R_CTR_TX_Pos) /*!< 0x00000080 */\r
+#define USB_EP0R_CTR_TX USB_EP0R_CTR_TX_Msk /*!<Correct Transfer for transmission */\r
+#define USB_EP0R_EP_KIND_Pos (8U) \r
+#define USB_EP0R_EP_KIND_Msk (0x1UL << USB_EP0R_EP_KIND_Pos) /*!< 0x00000100 */\r
+#define USB_EP0R_EP_KIND USB_EP0R_EP_KIND_Msk /*!<Endpoint Kind */\r
+\r
+#define USB_EP0R_EP_TYPE_Pos (9U) \r
+#define USB_EP0R_EP_TYPE_Msk (0x3UL << USB_EP0R_EP_TYPE_Pos) /*!< 0x00000600 */\r
+#define USB_EP0R_EP_TYPE USB_EP0R_EP_TYPE_Msk /*!<EP_TYPE[1:0] bits (Endpoint type) */\r
+#define USB_EP0R_EP_TYPE_0 (0x1UL << USB_EP0R_EP_TYPE_Pos) /*!< 0x00000200 */\r
+#define USB_EP0R_EP_TYPE_1 (0x2UL << USB_EP0R_EP_TYPE_Pos) /*!< 0x00000400 */\r
+\r
+#define USB_EP0R_SETUP_Pos (11U) \r
+#define USB_EP0R_SETUP_Msk (0x1UL << USB_EP0R_SETUP_Pos) /*!< 0x00000800 */\r
+#define USB_EP0R_SETUP USB_EP0R_SETUP_Msk /*!<Setup transaction completed */\r
+\r
+#define USB_EP0R_STAT_RX_Pos (12U) \r
+#define USB_EP0R_STAT_RX_Msk (0x3UL << USB_EP0R_STAT_RX_Pos) /*!< 0x00003000 */\r
+#define USB_EP0R_STAT_RX USB_EP0R_STAT_RX_Msk /*!<STAT_RX[1:0] bits (Status bits, for reception transfers) */\r
+#define USB_EP0R_STAT_RX_0 (0x1UL << USB_EP0R_STAT_RX_Pos) /*!< 0x00001000 */\r
+#define USB_EP0R_STAT_RX_1 (0x2UL << USB_EP0R_STAT_RX_Pos) /*!< 0x00002000 */\r
+\r
+#define USB_EP0R_DTOG_RX_Pos (14U) \r
+#define USB_EP0R_DTOG_RX_Msk (0x1UL << USB_EP0R_DTOG_RX_Pos) /*!< 0x00004000 */\r
+#define USB_EP0R_DTOG_RX USB_EP0R_DTOG_RX_Msk /*!<Data Toggle, for reception transfers */\r
+#define USB_EP0R_CTR_RX_Pos (15U) \r
+#define USB_EP0R_CTR_RX_Msk (0x1UL << USB_EP0R_CTR_RX_Pos) /*!< 0x00008000 */\r
+#define USB_EP0R_CTR_RX USB_EP0R_CTR_RX_Msk /*!<Correct Transfer for reception */\r
+\r
+/******************* Bit definition for USB_EP1R register *******************/\r
+#define USB_EP1R_EA_Pos (0U) \r
+#define USB_EP1R_EA_Msk (0xFUL << USB_EP1R_EA_Pos) /*!< 0x0000000F */\r
+#define USB_EP1R_EA USB_EP1R_EA_Msk /*!<Endpoint Address */\r
+\r
+#define USB_EP1R_STAT_TX_Pos (4U) \r
+#define USB_EP1R_STAT_TX_Msk (0x3UL << USB_EP1R_STAT_TX_Pos) /*!< 0x00000030 */\r
+#define USB_EP1R_STAT_TX USB_EP1R_STAT_TX_Msk /*!<STAT_TX[1:0] bits (Status bits, for transmission transfers) */\r
+#define USB_EP1R_STAT_TX_0 (0x1UL << USB_EP1R_STAT_TX_Pos) /*!< 0x00000010 */\r
+#define USB_EP1R_STAT_TX_1 (0x2UL << USB_EP1R_STAT_TX_Pos) /*!< 0x00000020 */\r
+\r
+#define USB_EP1R_DTOG_TX_Pos (6U) \r
+#define USB_EP1R_DTOG_TX_Msk (0x1UL << USB_EP1R_DTOG_TX_Pos) /*!< 0x00000040 */\r
+#define USB_EP1R_DTOG_TX USB_EP1R_DTOG_TX_Msk /*!<Data Toggle, for transmission transfers */\r
+#define USB_EP1R_CTR_TX_Pos (7U) \r
+#define USB_EP1R_CTR_TX_Msk (0x1UL << USB_EP1R_CTR_TX_Pos) /*!< 0x00000080 */\r
+#define USB_EP1R_CTR_TX USB_EP1R_CTR_TX_Msk /*!<Correct Transfer for transmission */\r
+#define USB_EP1R_EP_KIND_Pos (8U) \r
+#define USB_EP1R_EP_KIND_Msk (0x1UL << USB_EP1R_EP_KIND_Pos) /*!< 0x00000100 */\r
+#define USB_EP1R_EP_KIND USB_EP1R_EP_KIND_Msk /*!<Endpoint Kind */\r
+\r
+#define USB_EP1R_EP_TYPE_Pos (9U) \r
+#define USB_EP1R_EP_TYPE_Msk (0x3UL << USB_EP1R_EP_TYPE_Pos) /*!< 0x00000600 */\r
+#define USB_EP1R_EP_TYPE USB_EP1R_EP_TYPE_Msk /*!<EP_TYPE[1:0] bits (Endpoint type) */\r
+#define USB_EP1R_EP_TYPE_0 (0x1UL << USB_EP1R_EP_TYPE_Pos) /*!< 0x00000200 */\r
+#define USB_EP1R_EP_TYPE_1 (0x2UL << USB_EP1R_EP_TYPE_Pos) /*!< 0x00000400 */\r
+\r
+#define USB_EP1R_SETUP_Pos (11U) \r
+#define USB_EP1R_SETUP_Msk (0x1UL << USB_EP1R_SETUP_Pos) /*!< 0x00000800 */\r
+#define USB_EP1R_SETUP USB_EP1R_SETUP_Msk /*!<Setup transaction completed */\r
+\r
+#define USB_EP1R_STAT_RX_Pos (12U) \r
+#define USB_EP1R_STAT_RX_Msk (0x3UL << USB_EP1R_STAT_RX_Pos) /*!< 0x00003000 */\r
+#define USB_EP1R_STAT_RX USB_EP1R_STAT_RX_Msk /*!<STAT_RX[1:0] bits (Status bits, for reception transfers) */\r
+#define USB_EP1R_STAT_RX_0 (0x1UL << USB_EP1R_STAT_RX_Pos) /*!< 0x00001000 */\r
+#define USB_EP1R_STAT_RX_1 (0x2UL << USB_EP1R_STAT_RX_Pos) /*!< 0x00002000 */\r
+\r
+#define USB_EP1R_DTOG_RX_Pos (14U) \r
+#define USB_EP1R_DTOG_RX_Msk (0x1UL << USB_EP1R_DTOG_RX_Pos) /*!< 0x00004000 */\r
+#define USB_EP1R_DTOG_RX USB_EP1R_DTOG_RX_Msk /*!<Data Toggle, for reception transfers */\r
+#define USB_EP1R_CTR_RX_Pos (15U) \r
+#define USB_EP1R_CTR_RX_Msk (0x1UL << USB_EP1R_CTR_RX_Pos) /*!< 0x00008000 */\r
+#define USB_EP1R_CTR_RX USB_EP1R_CTR_RX_Msk /*!<Correct Transfer for reception */\r
+\r
+/******************* Bit definition for USB_EP2R register *******************/\r
+#define USB_EP2R_EA_Pos (0U) \r
+#define USB_EP2R_EA_Msk (0xFUL << USB_EP2R_EA_Pos) /*!< 0x0000000F */\r
+#define USB_EP2R_EA USB_EP2R_EA_Msk /*!<Endpoint Address */\r
+\r
+#define USB_EP2R_STAT_TX_Pos (4U) \r
+#define USB_EP2R_STAT_TX_Msk (0x3UL << USB_EP2R_STAT_TX_Pos) /*!< 0x00000030 */\r
+#define USB_EP2R_STAT_TX USB_EP2R_STAT_TX_Msk /*!<STAT_TX[1:0] bits (Status bits, for transmission transfers) */\r
+#define USB_EP2R_STAT_TX_0 (0x1UL << USB_EP2R_STAT_TX_Pos) /*!< 0x00000010 */\r
+#define USB_EP2R_STAT_TX_1 (0x2UL << USB_EP2R_STAT_TX_Pos) /*!< 0x00000020 */\r
+\r
+#define USB_EP2R_DTOG_TX_Pos (6U) \r
+#define USB_EP2R_DTOG_TX_Msk (0x1UL << USB_EP2R_DTOG_TX_Pos) /*!< 0x00000040 */\r
+#define USB_EP2R_DTOG_TX USB_EP2R_DTOG_TX_Msk /*!<Data Toggle, for transmission transfers */\r
+#define USB_EP2R_CTR_TX_Pos (7U) \r
+#define USB_EP2R_CTR_TX_Msk (0x1UL << USB_EP2R_CTR_TX_Pos) /*!< 0x00000080 */\r
+#define USB_EP2R_CTR_TX USB_EP2R_CTR_TX_Msk /*!<Correct Transfer for transmission */\r
+#define USB_EP2R_EP_KIND_Pos (8U) \r
+#define USB_EP2R_EP_KIND_Msk (0x1UL << USB_EP2R_EP_KIND_Pos) /*!< 0x00000100 */\r
+#define USB_EP2R_EP_KIND USB_EP2R_EP_KIND_Msk /*!<Endpoint Kind */\r
+\r
+#define USB_EP2R_EP_TYPE_Pos (9U) \r
+#define USB_EP2R_EP_TYPE_Msk (0x3UL << USB_EP2R_EP_TYPE_Pos) /*!< 0x00000600 */\r
+#define USB_EP2R_EP_TYPE USB_EP2R_EP_TYPE_Msk /*!<EP_TYPE[1:0] bits (Endpoint type) */\r
+#define USB_EP2R_EP_TYPE_0 (0x1UL << USB_EP2R_EP_TYPE_Pos) /*!< 0x00000200 */\r
+#define USB_EP2R_EP_TYPE_1 (0x2UL << USB_EP2R_EP_TYPE_Pos) /*!< 0x00000400 */\r
+\r
+#define USB_EP2R_SETUP_Pos (11U) \r
+#define USB_EP2R_SETUP_Msk (0x1UL << USB_EP2R_SETUP_Pos) /*!< 0x00000800 */\r
+#define USB_EP2R_SETUP USB_EP2R_SETUP_Msk /*!<Setup transaction completed */\r
+\r
+#define USB_EP2R_STAT_RX_Pos (12U) \r
+#define USB_EP2R_STAT_RX_Msk (0x3UL << USB_EP2R_STAT_RX_Pos) /*!< 0x00003000 */\r
+#define USB_EP2R_STAT_RX USB_EP2R_STAT_RX_Msk /*!<STAT_RX[1:0] bits (Status bits, for reception transfers) */\r
+#define USB_EP2R_STAT_RX_0 (0x1UL << USB_EP2R_STAT_RX_Pos) /*!< 0x00001000 */\r
+#define USB_EP2R_STAT_RX_1 (0x2UL << USB_EP2R_STAT_RX_Pos) /*!< 0x00002000 */\r
+\r
+#define USB_EP2R_DTOG_RX_Pos (14U) \r
+#define USB_EP2R_DTOG_RX_Msk (0x1UL << USB_EP2R_DTOG_RX_Pos) /*!< 0x00004000 */\r
+#define USB_EP2R_DTOG_RX USB_EP2R_DTOG_RX_Msk /*!<Data Toggle, for reception transfers */\r
+#define USB_EP2R_CTR_RX_Pos (15U) \r
+#define USB_EP2R_CTR_RX_Msk (0x1UL << USB_EP2R_CTR_RX_Pos) /*!< 0x00008000 */\r
+#define USB_EP2R_CTR_RX USB_EP2R_CTR_RX_Msk /*!<Correct Transfer for reception */\r
+\r
+/******************* Bit definition for USB_EP3R register *******************/\r
+#define USB_EP3R_EA_Pos (0U) \r
+#define USB_EP3R_EA_Msk (0xFUL << USB_EP3R_EA_Pos) /*!< 0x0000000F */\r
+#define USB_EP3R_EA USB_EP3R_EA_Msk /*!<Endpoint Address */\r
+\r
+#define USB_EP3R_STAT_TX_Pos (4U) \r
+#define USB_EP3R_STAT_TX_Msk (0x3UL << USB_EP3R_STAT_TX_Pos) /*!< 0x00000030 */\r
+#define USB_EP3R_STAT_TX USB_EP3R_STAT_TX_Msk /*!<STAT_TX[1:0] bits (Status bits, for transmission transfers) */\r
+#define USB_EP3R_STAT_TX_0 (0x1UL << USB_EP3R_STAT_TX_Pos) /*!< 0x00000010 */\r
+#define USB_EP3R_STAT_TX_1 (0x2UL << USB_EP3R_STAT_TX_Pos) /*!< 0x00000020 */\r
+\r
+#define USB_EP3R_DTOG_TX_Pos (6U) \r
+#define USB_EP3R_DTOG_TX_Msk (0x1UL << USB_EP3R_DTOG_TX_Pos) /*!< 0x00000040 */\r
+#define USB_EP3R_DTOG_TX USB_EP3R_DTOG_TX_Msk /*!<Data Toggle, for transmission transfers */\r
+#define USB_EP3R_CTR_TX_Pos (7U) \r
+#define USB_EP3R_CTR_TX_Msk (0x1UL << USB_EP3R_CTR_TX_Pos) /*!< 0x00000080 */\r
+#define USB_EP3R_CTR_TX USB_EP3R_CTR_TX_Msk /*!<Correct Transfer for transmission */\r
+#define USB_EP3R_EP_KIND_Pos (8U) \r
+#define USB_EP3R_EP_KIND_Msk (0x1UL << USB_EP3R_EP_KIND_Pos) /*!< 0x00000100 */\r
+#define USB_EP3R_EP_KIND USB_EP3R_EP_KIND_Msk /*!<Endpoint Kind */\r
+\r
+#define USB_EP3R_EP_TYPE_Pos (9U) \r
+#define USB_EP3R_EP_TYPE_Msk (0x3UL << USB_EP3R_EP_TYPE_Pos) /*!< 0x00000600 */\r
+#define USB_EP3R_EP_TYPE USB_EP3R_EP_TYPE_Msk /*!<EP_TYPE[1:0] bits (Endpoint type) */\r
+#define USB_EP3R_EP_TYPE_0 (0x1UL << USB_EP3R_EP_TYPE_Pos) /*!< 0x00000200 */\r
+#define USB_EP3R_EP_TYPE_1 (0x2UL << USB_EP3R_EP_TYPE_Pos) /*!< 0x00000400 */\r
+\r
+#define USB_EP3R_SETUP_Pos (11U) \r
+#define USB_EP3R_SETUP_Msk (0x1UL << USB_EP3R_SETUP_Pos) /*!< 0x00000800 */\r
+#define USB_EP3R_SETUP USB_EP3R_SETUP_Msk /*!<Setup transaction completed */\r
+\r
+#define USB_EP3R_STAT_RX_Pos (12U) \r
+#define USB_EP3R_STAT_RX_Msk (0x3UL << USB_EP3R_STAT_RX_Pos) /*!< 0x00003000 */\r
+#define USB_EP3R_STAT_RX USB_EP3R_STAT_RX_Msk /*!<STAT_RX[1:0] bits (Status bits, for reception transfers) */\r
+#define USB_EP3R_STAT_RX_0 (0x1UL << USB_EP3R_STAT_RX_Pos) /*!< 0x00001000 */\r
+#define USB_EP3R_STAT_RX_1 (0x2UL << USB_EP3R_STAT_RX_Pos) /*!< 0x00002000 */\r
+\r
+#define USB_EP3R_DTOG_RX_Pos (14U) \r
+#define USB_EP3R_DTOG_RX_Msk (0x1UL << USB_EP3R_DTOG_RX_Pos) /*!< 0x00004000 */\r
+#define USB_EP3R_DTOG_RX USB_EP3R_DTOG_RX_Msk /*!<Data Toggle, for reception transfers */\r
+#define USB_EP3R_CTR_RX_Pos (15U) \r
+#define USB_EP3R_CTR_RX_Msk (0x1UL << USB_EP3R_CTR_RX_Pos) /*!< 0x00008000 */\r
+#define USB_EP3R_CTR_RX USB_EP3R_CTR_RX_Msk /*!<Correct Transfer for reception */\r
+\r
+/******************* Bit definition for USB_EP4R register *******************/\r
+#define USB_EP4R_EA_Pos (0U) \r
+#define USB_EP4R_EA_Msk (0xFUL << USB_EP4R_EA_Pos) /*!< 0x0000000F */\r
+#define USB_EP4R_EA USB_EP4R_EA_Msk /*!<Endpoint Address */\r
+\r
+#define USB_EP4R_STAT_TX_Pos (4U) \r
+#define USB_EP4R_STAT_TX_Msk (0x3UL << USB_EP4R_STAT_TX_Pos) /*!< 0x00000030 */\r
+#define USB_EP4R_STAT_TX USB_EP4R_STAT_TX_Msk /*!<STAT_TX[1:0] bits (Status bits, for transmission transfers) */\r
+#define USB_EP4R_STAT_TX_0 (0x1UL << USB_EP4R_STAT_TX_Pos) /*!< 0x00000010 */\r
+#define USB_EP4R_STAT_TX_1 (0x2UL << USB_EP4R_STAT_TX_Pos) /*!< 0x00000020 */\r
+\r
+#define USB_EP4R_DTOG_TX_Pos (6U) \r
+#define USB_EP4R_DTOG_TX_Msk (0x1UL << USB_EP4R_DTOG_TX_Pos) /*!< 0x00000040 */\r
+#define USB_EP4R_DTOG_TX USB_EP4R_DTOG_TX_Msk /*!<Data Toggle, for transmission transfers */\r
+#define USB_EP4R_CTR_TX_Pos (7U) \r
+#define USB_EP4R_CTR_TX_Msk (0x1UL << USB_EP4R_CTR_TX_Pos) /*!< 0x00000080 */\r
+#define USB_EP4R_CTR_TX USB_EP4R_CTR_TX_Msk /*!<Correct Transfer for transmission */\r
+#define USB_EP4R_EP_KIND_Pos (8U) \r
+#define USB_EP4R_EP_KIND_Msk (0x1UL << USB_EP4R_EP_KIND_Pos) /*!< 0x00000100 */\r
+#define USB_EP4R_EP_KIND USB_EP4R_EP_KIND_Msk /*!<Endpoint Kind */\r
+\r
+#define USB_EP4R_EP_TYPE_Pos (9U) \r
+#define USB_EP4R_EP_TYPE_Msk (0x3UL << USB_EP4R_EP_TYPE_Pos) /*!< 0x00000600 */\r
+#define USB_EP4R_EP_TYPE USB_EP4R_EP_TYPE_Msk /*!<EP_TYPE[1:0] bits (Endpoint type) */\r
+#define USB_EP4R_EP_TYPE_0 (0x1UL << USB_EP4R_EP_TYPE_Pos) /*!< 0x00000200 */\r
+#define USB_EP4R_EP_TYPE_1 (0x2UL << USB_EP4R_EP_TYPE_Pos) /*!< 0x00000400 */\r
+\r
+#define USB_EP4R_SETUP_Pos (11U) \r
+#define USB_EP4R_SETUP_Msk (0x1UL << USB_EP4R_SETUP_Pos) /*!< 0x00000800 */\r
+#define USB_EP4R_SETUP USB_EP4R_SETUP_Msk /*!<Setup transaction completed */\r
+\r
+#define USB_EP4R_STAT_RX_Pos (12U) \r
+#define USB_EP4R_STAT_RX_Msk (0x3UL << USB_EP4R_STAT_RX_Pos) /*!< 0x00003000 */\r
+#define USB_EP4R_STAT_RX USB_EP4R_STAT_RX_Msk /*!<STAT_RX[1:0] bits (Status bits, for reception transfers) */\r
+#define USB_EP4R_STAT_RX_0 (0x1UL << USB_EP4R_STAT_RX_Pos) /*!< 0x00001000 */\r
+#define USB_EP4R_STAT_RX_1 (0x2UL << USB_EP4R_STAT_RX_Pos) /*!< 0x00002000 */\r
+\r
+#define USB_EP4R_DTOG_RX_Pos (14U) \r
+#define USB_EP4R_DTOG_RX_Msk (0x1UL << USB_EP4R_DTOG_RX_Pos) /*!< 0x00004000 */\r
+#define USB_EP4R_DTOG_RX USB_EP4R_DTOG_RX_Msk /*!<Data Toggle, for reception transfers */\r
+#define USB_EP4R_CTR_RX_Pos (15U) \r
+#define USB_EP4R_CTR_RX_Msk (0x1UL << USB_EP4R_CTR_RX_Pos) /*!< 0x00008000 */\r
+#define USB_EP4R_CTR_RX USB_EP4R_CTR_RX_Msk /*!<Correct Transfer for reception */\r
+\r
+/******************* Bit definition for USB_EP5R register *******************/\r
+#define USB_EP5R_EA_Pos (0U) \r
+#define USB_EP5R_EA_Msk (0xFUL << USB_EP5R_EA_Pos) /*!< 0x0000000F */\r
+#define USB_EP5R_EA USB_EP5R_EA_Msk /*!<Endpoint Address */\r
+\r
+#define USB_EP5R_STAT_TX_Pos (4U) \r
+#define USB_EP5R_STAT_TX_Msk (0x3UL << USB_EP5R_STAT_TX_Pos) /*!< 0x00000030 */\r
+#define USB_EP5R_STAT_TX USB_EP5R_STAT_TX_Msk /*!<STAT_TX[1:0] bits (Status bits, for transmission transfers) */\r
+#define USB_EP5R_STAT_TX_0 (0x1UL << USB_EP5R_STAT_TX_Pos) /*!< 0x00000010 */\r
+#define USB_EP5R_STAT_TX_1 (0x2UL << USB_EP5R_STAT_TX_Pos) /*!< 0x00000020 */\r
+\r
+#define USB_EP5R_DTOG_TX_Pos (6U) \r
+#define USB_EP5R_DTOG_TX_Msk (0x1UL << USB_EP5R_DTOG_TX_Pos) /*!< 0x00000040 */\r
+#define USB_EP5R_DTOG_TX USB_EP5R_DTOG_TX_Msk /*!<Data Toggle, for transmission transfers */\r
+#define USB_EP5R_CTR_TX_Pos (7U) \r
+#define USB_EP5R_CTR_TX_Msk (0x1UL << USB_EP5R_CTR_TX_Pos) /*!< 0x00000080 */\r
+#define USB_EP5R_CTR_TX USB_EP5R_CTR_TX_Msk /*!<Correct Transfer for transmission */\r
+#define USB_EP5R_EP_KIND_Pos (8U) \r
+#define USB_EP5R_EP_KIND_Msk (0x1UL << USB_EP5R_EP_KIND_Pos) /*!< 0x00000100 */\r
+#define USB_EP5R_EP_KIND USB_EP5R_EP_KIND_Msk /*!<Endpoint Kind */\r
+\r
+#define USB_EP5R_EP_TYPE_Pos (9U) \r
+#define USB_EP5R_EP_TYPE_Msk (0x3UL << USB_EP5R_EP_TYPE_Pos) /*!< 0x00000600 */\r
+#define USB_EP5R_EP_TYPE USB_EP5R_EP_TYPE_Msk /*!<EP_TYPE[1:0] bits (Endpoint type) */\r
+#define USB_EP5R_EP_TYPE_0 (0x1UL << USB_EP5R_EP_TYPE_Pos) /*!< 0x00000200 */\r
+#define USB_EP5R_EP_TYPE_1 (0x2UL << USB_EP5R_EP_TYPE_Pos) /*!< 0x00000400 */\r
+\r
+#define USB_EP5R_SETUP_Pos (11U) \r
+#define USB_EP5R_SETUP_Msk (0x1UL << USB_EP5R_SETUP_Pos) /*!< 0x00000800 */\r
+#define USB_EP5R_SETUP USB_EP5R_SETUP_Msk /*!<Setup transaction completed */\r
+\r
+#define USB_EP5R_STAT_RX_Pos (12U) \r
+#define USB_EP5R_STAT_RX_Msk (0x3UL << USB_EP5R_STAT_RX_Pos) /*!< 0x00003000 */\r
+#define USB_EP5R_STAT_RX USB_EP5R_STAT_RX_Msk /*!<STAT_RX[1:0] bits (Status bits, for reception transfers) */\r
+#define USB_EP5R_STAT_RX_0 (0x1UL << USB_EP5R_STAT_RX_Pos) /*!< 0x00001000 */\r
+#define USB_EP5R_STAT_RX_1 (0x2UL << USB_EP5R_STAT_RX_Pos) /*!< 0x00002000 */\r
+\r
+#define USB_EP5R_DTOG_RX_Pos (14U) \r
+#define USB_EP5R_DTOG_RX_Msk (0x1UL << USB_EP5R_DTOG_RX_Pos) /*!< 0x00004000 */\r
+#define USB_EP5R_DTOG_RX USB_EP5R_DTOG_RX_Msk /*!<Data Toggle, for reception transfers */\r
+#define USB_EP5R_CTR_RX_Pos (15U) \r
+#define USB_EP5R_CTR_RX_Msk (0x1UL << USB_EP5R_CTR_RX_Pos) /*!< 0x00008000 */\r
+#define USB_EP5R_CTR_RX USB_EP5R_CTR_RX_Msk /*!<Correct Transfer for reception */\r
+\r
+/******************* Bit definition for USB_EP6R register *******************/\r
+#define USB_EP6R_EA_Pos (0U) \r
+#define USB_EP6R_EA_Msk (0xFUL << USB_EP6R_EA_Pos) /*!< 0x0000000F */\r
+#define USB_EP6R_EA USB_EP6R_EA_Msk /*!<Endpoint Address */\r
+\r
+#define USB_EP6R_STAT_TX_Pos (4U) \r
+#define USB_EP6R_STAT_TX_Msk (0x3UL << USB_EP6R_STAT_TX_Pos) /*!< 0x00000030 */\r
+#define USB_EP6R_STAT_TX USB_EP6R_STAT_TX_Msk /*!<STAT_TX[1:0] bits (Status bits, for transmission transfers) */\r
+#define USB_EP6R_STAT_TX_0 (0x1UL << USB_EP6R_STAT_TX_Pos) /*!< 0x00000010 */\r
+#define USB_EP6R_STAT_TX_1 (0x2UL << USB_EP6R_STAT_TX_Pos) /*!< 0x00000020 */\r
+\r
+#define USB_EP6R_DTOG_TX_Pos (6U) \r
+#define USB_EP6R_DTOG_TX_Msk (0x1UL << USB_EP6R_DTOG_TX_Pos) /*!< 0x00000040 */\r
+#define USB_EP6R_DTOG_TX USB_EP6R_DTOG_TX_Msk /*!<Data Toggle, for transmission transfers */\r
+#define USB_EP6R_CTR_TX_Pos (7U) \r
+#define USB_EP6R_CTR_TX_Msk (0x1UL << USB_EP6R_CTR_TX_Pos) /*!< 0x00000080 */\r
+#define USB_EP6R_CTR_TX USB_EP6R_CTR_TX_Msk /*!<Correct Transfer for transmission */\r
+#define USB_EP6R_EP_KIND_Pos (8U) \r
+#define USB_EP6R_EP_KIND_Msk (0x1UL << USB_EP6R_EP_KIND_Pos) /*!< 0x00000100 */\r
+#define USB_EP6R_EP_KIND USB_EP6R_EP_KIND_Msk /*!<Endpoint Kind */\r
+\r
+#define USB_EP6R_EP_TYPE_Pos (9U) \r
+#define USB_EP6R_EP_TYPE_Msk (0x3UL << USB_EP6R_EP_TYPE_Pos) /*!< 0x00000600 */\r
+#define USB_EP6R_EP_TYPE USB_EP6R_EP_TYPE_Msk /*!<EP_TYPE[1:0] bits (Endpoint type) */\r
+#define USB_EP6R_EP_TYPE_0 (0x1UL << USB_EP6R_EP_TYPE_Pos) /*!< 0x00000200 */\r
+#define USB_EP6R_EP_TYPE_1 (0x2UL << USB_EP6R_EP_TYPE_Pos) /*!< 0x00000400 */\r
+\r
+#define USB_EP6R_SETUP_Pos (11U) \r
+#define USB_EP6R_SETUP_Msk (0x1UL << USB_EP6R_SETUP_Pos) /*!< 0x00000800 */\r
+#define USB_EP6R_SETUP USB_EP6R_SETUP_Msk /*!<Setup transaction completed */\r
+\r
+#define USB_EP6R_STAT_RX_Pos (12U) \r
+#define USB_EP6R_STAT_RX_Msk (0x3UL << USB_EP6R_STAT_RX_Pos) /*!< 0x00003000 */\r
+#define USB_EP6R_STAT_RX USB_EP6R_STAT_RX_Msk /*!<STAT_RX[1:0] bits (Status bits, for reception transfers) */\r
+#define USB_EP6R_STAT_RX_0 (0x1UL << USB_EP6R_STAT_RX_Pos) /*!< 0x00001000 */\r
+#define USB_EP6R_STAT_RX_1 (0x2UL << USB_EP6R_STAT_RX_Pos) /*!< 0x00002000 */\r
+\r
+#define USB_EP6R_DTOG_RX_Pos (14U) \r
+#define USB_EP6R_DTOG_RX_Msk (0x1UL << USB_EP6R_DTOG_RX_Pos) /*!< 0x00004000 */\r
+#define USB_EP6R_DTOG_RX USB_EP6R_DTOG_RX_Msk /*!<Data Toggle, for reception transfers */\r
+#define USB_EP6R_CTR_RX_Pos (15U) \r
+#define USB_EP6R_CTR_RX_Msk (0x1UL << USB_EP6R_CTR_RX_Pos) /*!< 0x00008000 */\r
+#define USB_EP6R_CTR_RX USB_EP6R_CTR_RX_Msk /*!<Correct Transfer for reception */\r
+\r
+/******************* Bit definition for USB_EP7R register *******************/\r
+#define USB_EP7R_EA_Pos (0U) \r
+#define USB_EP7R_EA_Msk (0xFUL << USB_EP7R_EA_Pos) /*!< 0x0000000F */\r
+#define USB_EP7R_EA USB_EP7R_EA_Msk /*!<Endpoint Address */\r
+\r
+#define USB_EP7R_STAT_TX_Pos (4U) \r
+#define USB_EP7R_STAT_TX_Msk (0x3UL << USB_EP7R_STAT_TX_Pos) /*!< 0x00000030 */\r
+#define USB_EP7R_STAT_TX USB_EP7R_STAT_TX_Msk /*!<STAT_TX[1:0] bits (Status bits, for transmission transfers) */\r
+#define USB_EP7R_STAT_TX_0 (0x1UL << USB_EP7R_STAT_TX_Pos) /*!< 0x00000010 */\r
+#define USB_EP7R_STAT_TX_1 (0x2UL << USB_EP7R_STAT_TX_Pos) /*!< 0x00000020 */\r
+\r
+#define USB_EP7R_DTOG_TX_Pos (6U) \r
+#define USB_EP7R_DTOG_TX_Msk (0x1UL << USB_EP7R_DTOG_TX_Pos) /*!< 0x00000040 */\r
+#define USB_EP7R_DTOG_TX USB_EP7R_DTOG_TX_Msk /*!<Data Toggle, for transmission transfers */\r
+#define USB_EP7R_CTR_TX_Pos (7U) \r
+#define USB_EP7R_CTR_TX_Msk (0x1UL << USB_EP7R_CTR_TX_Pos) /*!< 0x00000080 */\r
+#define USB_EP7R_CTR_TX USB_EP7R_CTR_TX_Msk /*!<Correct Transfer for transmission */\r
+#define USB_EP7R_EP_KIND_Pos (8U) \r
+#define USB_EP7R_EP_KIND_Msk (0x1UL << USB_EP7R_EP_KIND_Pos) /*!< 0x00000100 */\r
+#define USB_EP7R_EP_KIND USB_EP7R_EP_KIND_Msk /*!<Endpoint Kind */\r
+\r
+#define USB_EP7R_EP_TYPE_Pos (9U) \r
+#define USB_EP7R_EP_TYPE_Msk (0x3UL << USB_EP7R_EP_TYPE_Pos) /*!< 0x00000600 */\r
+#define USB_EP7R_EP_TYPE USB_EP7R_EP_TYPE_Msk /*!<EP_TYPE[1:0] bits (Endpoint type) */\r
+#define USB_EP7R_EP_TYPE_0 (0x1UL << USB_EP7R_EP_TYPE_Pos) /*!< 0x00000200 */\r
+#define USB_EP7R_EP_TYPE_1 (0x2UL << USB_EP7R_EP_TYPE_Pos) /*!< 0x00000400 */\r
+\r
+#define USB_EP7R_SETUP_Pos (11U) \r
+#define USB_EP7R_SETUP_Msk (0x1UL << USB_EP7R_SETUP_Pos) /*!< 0x00000800 */\r
+#define USB_EP7R_SETUP USB_EP7R_SETUP_Msk /*!<Setup transaction completed */\r
+\r
+#define USB_EP7R_STAT_RX_Pos (12U) \r
+#define USB_EP7R_STAT_RX_Msk (0x3UL << USB_EP7R_STAT_RX_Pos) /*!< 0x00003000 */\r
+#define USB_EP7R_STAT_RX USB_EP7R_STAT_RX_Msk /*!<STAT_RX[1:0] bits (Status bits, for reception transfers) */\r
+#define USB_EP7R_STAT_RX_0 (0x1UL << USB_EP7R_STAT_RX_Pos) /*!< 0x00001000 */\r
+#define USB_EP7R_STAT_RX_1 (0x2UL << USB_EP7R_STAT_RX_Pos) /*!< 0x00002000 */\r
+\r
+#define USB_EP7R_DTOG_RX_Pos (14U) \r
+#define USB_EP7R_DTOG_RX_Msk (0x1UL << USB_EP7R_DTOG_RX_Pos) /*!< 0x00004000 */\r
+#define USB_EP7R_DTOG_RX USB_EP7R_DTOG_RX_Msk /*!<Data Toggle, for reception transfers */\r
+#define USB_EP7R_CTR_RX_Pos (15U) \r
+#define USB_EP7R_CTR_RX_Msk (0x1UL << USB_EP7R_CTR_RX_Pos) /*!< 0x00008000 */\r
+#define USB_EP7R_CTR_RX USB_EP7R_CTR_RX_Msk /*!<Correct Transfer for reception */\r
+\r
+/*!<Common registers */\r
+\r
+#define USB_CNTR (USB_BASE + 0x00000040U) /*!< Control register */\r
+#define USB_ISTR (USB_BASE + 0x00000044U) /*!< Interrupt status register */\r
+#define USB_FNR (USB_BASE + 0x00000048U) /*!< Frame number register */\r
+#define USB_DADDR (USB_BASE + 0x0000004CU) /*!< Device address register */\r
+#define USB_BTABLE (USB_BASE + 0x00000050U) /*!< Buffer Table address register */\r
+\r
+\r
+\r
+/******************* Bit definition for USB_CNTR register *******************/\r
+#define USB_CNTR_FRES_Pos (0U) \r
+#define USB_CNTR_FRES_Msk (0x1UL << USB_CNTR_FRES_Pos) /*!< 0x00000001 */\r
+#define USB_CNTR_FRES USB_CNTR_FRES_Msk /*!<Force USB Reset */\r
+#define USB_CNTR_PDWN_Pos (1U) \r
+#define USB_CNTR_PDWN_Msk (0x1UL << USB_CNTR_PDWN_Pos) /*!< 0x00000002 */\r
+#define USB_CNTR_PDWN USB_CNTR_PDWN_Msk /*!<Power down */\r
+#define USB_CNTR_LPMODE_Pos (2U) \r
+#define USB_CNTR_LPMODE_Msk (0x1UL << USB_CNTR_LPMODE_Pos) /*!< 0x00000004 */\r
+#define USB_CNTR_LPMODE USB_CNTR_LPMODE_Msk /*!<Low-power mode */\r
+#define USB_CNTR_FSUSP_Pos (3U) \r
+#define USB_CNTR_FSUSP_Msk (0x1UL << USB_CNTR_FSUSP_Pos) /*!< 0x00000008 */\r
+#define USB_CNTR_FSUSP USB_CNTR_FSUSP_Msk /*!<Force suspend */\r
+#define USB_CNTR_RESUME_Pos (4U) \r
+#define USB_CNTR_RESUME_Msk (0x1UL << USB_CNTR_RESUME_Pos) /*!< 0x00000010 */\r
+#define USB_CNTR_RESUME USB_CNTR_RESUME_Msk /*!<Resume request */\r
+#define USB_CNTR_ESOFM_Pos (8U) \r
+#define USB_CNTR_ESOFM_Msk (0x1UL << USB_CNTR_ESOFM_Pos) /*!< 0x00000100 */\r
+#define USB_CNTR_ESOFM USB_CNTR_ESOFM_Msk /*!<Expected Start Of Frame Interrupt Mask */\r
+#define USB_CNTR_SOFM_Pos (9U) \r
+#define USB_CNTR_SOFM_Msk (0x1UL << USB_CNTR_SOFM_Pos) /*!< 0x00000200 */\r
+#define USB_CNTR_SOFM USB_CNTR_SOFM_Msk /*!<Start Of Frame Interrupt Mask */\r
+#define USB_CNTR_RESETM_Pos (10U) \r
+#define USB_CNTR_RESETM_Msk (0x1UL << USB_CNTR_RESETM_Pos) /*!< 0x00000400 */\r
+#define USB_CNTR_RESETM USB_CNTR_RESETM_Msk /*!<RESET Interrupt Mask */\r
+#define USB_CNTR_SUSPM_Pos (11U) \r
+#define USB_CNTR_SUSPM_Msk (0x1UL << USB_CNTR_SUSPM_Pos) /*!< 0x00000800 */\r
+#define USB_CNTR_SUSPM USB_CNTR_SUSPM_Msk /*!<Suspend mode Interrupt Mask */\r
+#define USB_CNTR_WKUPM_Pos (12U) \r
+#define USB_CNTR_WKUPM_Msk (0x1UL << USB_CNTR_WKUPM_Pos) /*!< 0x00001000 */\r
+#define USB_CNTR_WKUPM USB_CNTR_WKUPM_Msk /*!<Wakeup Interrupt Mask */\r
+#define USB_CNTR_ERRM_Pos (13U) \r
+#define USB_CNTR_ERRM_Msk (0x1UL << USB_CNTR_ERRM_Pos) /*!< 0x00002000 */\r
+#define USB_CNTR_ERRM USB_CNTR_ERRM_Msk /*!<Error Interrupt Mask */\r
+#define USB_CNTR_PMAOVRM_Pos (14U) \r
+#define USB_CNTR_PMAOVRM_Msk (0x1UL << USB_CNTR_PMAOVRM_Pos) /*!< 0x00004000 */\r
+#define USB_CNTR_PMAOVRM USB_CNTR_PMAOVRM_Msk /*!<Packet Memory Area Over / Underrun Interrupt Mask */\r
+#define USB_CNTR_CTRM_Pos (15U) \r
+#define USB_CNTR_CTRM_Msk (0x1UL << USB_CNTR_CTRM_Pos) /*!< 0x00008000 */\r
+#define USB_CNTR_CTRM USB_CNTR_CTRM_Msk /*!<Correct Transfer Interrupt Mask */\r
+\r
+/******************* Bit definition for USB_ISTR register *******************/\r
+#define USB_ISTR_EP_ID_Pos (0U) \r
+#define USB_ISTR_EP_ID_Msk (0xFUL << USB_ISTR_EP_ID_Pos) /*!< 0x0000000F */\r
+#define USB_ISTR_EP_ID USB_ISTR_EP_ID_Msk /*!<Endpoint Identifier */\r
+#define USB_ISTR_DIR_Pos (4U) \r
+#define USB_ISTR_DIR_Msk (0x1UL << USB_ISTR_DIR_Pos) /*!< 0x00000010 */\r
+#define USB_ISTR_DIR USB_ISTR_DIR_Msk /*!<Direction of transaction */\r
+#define USB_ISTR_ESOF_Pos (8U) \r
+#define USB_ISTR_ESOF_Msk (0x1UL << USB_ISTR_ESOF_Pos) /*!< 0x00000100 */\r
+#define USB_ISTR_ESOF USB_ISTR_ESOF_Msk /*!<Expected Start Of Frame */\r
+#define USB_ISTR_SOF_Pos (9U) \r
+#define USB_ISTR_SOF_Msk (0x1UL << USB_ISTR_SOF_Pos) /*!< 0x00000200 */\r
+#define USB_ISTR_SOF USB_ISTR_SOF_Msk /*!<Start Of Frame */\r
+#define USB_ISTR_RESET_Pos (10U) \r
+#define USB_ISTR_RESET_Msk (0x1UL << USB_ISTR_RESET_Pos) /*!< 0x00000400 */\r
+#define USB_ISTR_RESET USB_ISTR_RESET_Msk /*!<USB RESET request */\r
+#define USB_ISTR_SUSP_Pos (11U) \r
+#define USB_ISTR_SUSP_Msk (0x1UL << USB_ISTR_SUSP_Pos) /*!< 0x00000800 */\r
+#define USB_ISTR_SUSP USB_ISTR_SUSP_Msk /*!<Suspend mode request */\r
+#define USB_ISTR_WKUP_Pos (12U) \r
+#define USB_ISTR_WKUP_Msk (0x1UL << USB_ISTR_WKUP_Pos) /*!< 0x00001000 */\r
+#define USB_ISTR_WKUP USB_ISTR_WKUP_Msk /*!<Wake up */\r
+#define USB_ISTR_ERR_Pos (13U) \r
+#define USB_ISTR_ERR_Msk (0x1UL << USB_ISTR_ERR_Pos) /*!< 0x00002000 */\r
+#define USB_ISTR_ERR USB_ISTR_ERR_Msk /*!<Error */\r
+#define USB_ISTR_PMAOVR_Pos (14U) \r
+#define USB_ISTR_PMAOVR_Msk (0x1UL << USB_ISTR_PMAOVR_Pos) /*!< 0x00004000 */\r
+#define USB_ISTR_PMAOVR USB_ISTR_PMAOVR_Msk /*!<Packet Memory Area Over / Underrun */\r
+#define USB_ISTR_CTR_Pos (15U) \r
+#define USB_ISTR_CTR_Msk (0x1UL << USB_ISTR_CTR_Pos) /*!< 0x00008000 */\r
+#define USB_ISTR_CTR USB_ISTR_CTR_Msk /*!<Correct Transfer */\r
+\r
+#define USB_CLR_CTR (~USB_ISTR_CTR) /*!< clear Correct TRansfer bit */\r
+#define USB_CLR_PMAOVRM (~USB_ISTR_PMAOVR) /*!< clear DMA OVeR/underrun bit*/\r
+#define USB_CLR_ERR (~USB_ISTR_ERR) /*!< clear ERRor bit */\r
+#define USB_CLR_WKUP (~USB_ISTR_WKUP) /*!< clear WaKe UP bit */\r
+#define USB_CLR_SUSP (~USB_ISTR_SUSP) /*!< clear SUSPend bit */\r
+#define USB_CLR_RESET (~USB_ISTR_RESET) /*!< clear RESET bit */\r
+#define USB_CLR_SOF (~USB_ISTR_SOF) /*!< clear Start Of Frame bit */\r
+#define USB_CLR_ESOF (~USB_ISTR_ESOF) /*!< clear Expected Start Of Frame bit */\r
+\r
+\r
+/******************* Bit definition for USB_FNR register ********************/\r
+#define USB_FNR_FN_Pos (0U) \r
+#define USB_FNR_FN_Msk (0x7FFUL << USB_FNR_FN_Pos) /*!< 0x000007FF */\r
+#define USB_FNR_FN USB_FNR_FN_Msk /*!<Frame Number */\r
+#define USB_FNR_LSOF_Pos (11U) \r
+#define USB_FNR_LSOF_Msk (0x3UL << USB_FNR_LSOF_Pos) /*!< 0x00001800 */\r
+#define USB_FNR_LSOF USB_FNR_LSOF_Msk /*!<Lost SOF */\r
+#define USB_FNR_LCK_Pos (13U) \r
+#define USB_FNR_LCK_Msk (0x1UL << USB_FNR_LCK_Pos) /*!< 0x00002000 */\r
+#define USB_FNR_LCK USB_FNR_LCK_Msk /*!<Locked */\r
+#define USB_FNR_RXDM_Pos (14U) \r
+#define USB_FNR_RXDM_Msk (0x1UL << USB_FNR_RXDM_Pos) /*!< 0x00004000 */\r
+#define USB_FNR_RXDM USB_FNR_RXDM_Msk /*!<Receive Data - Line Status */\r
+#define USB_FNR_RXDP_Pos (15U) \r
+#define USB_FNR_RXDP_Msk (0x1UL << USB_FNR_RXDP_Pos) /*!< 0x00008000 */\r
+#define USB_FNR_RXDP USB_FNR_RXDP_Msk /*!<Receive Data + Line Status */\r
+\r
+/****************** Bit definition for USB_DADDR register *******************/\r
+#define USB_DADDR_ADD_Pos (0U) \r
+#define USB_DADDR_ADD_Msk (0x7FUL << USB_DADDR_ADD_Pos) /*!< 0x0000007F */\r
+#define USB_DADDR_ADD USB_DADDR_ADD_Msk /*!<ADD[6:0] bits (Device Address) */\r
+#define USB_DADDR_ADD0_Pos (0U) \r
+#define USB_DADDR_ADD0_Msk (0x1UL << USB_DADDR_ADD0_Pos) /*!< 0x00000001 */\r
+#define USB_DADDR_ADD0 USB_DADDR_ADD0_Msk /*!<Bit 0 */\r
+#define USB_DADDR_ADD1_Pos (1U) \r
+#define USB_DADDR_ADD1_Msk (0x1UL << USB_DADDR_ADD1_Pos) /*!< 0x00000002 */\r
+#define USB_DADDR_ADD1 USB_DADDR_ADD1_Msk /*!<Bit 1 */\r
+#define USB_DADDR_ADD2_Pos (2U) \r
+#define USB_DADDR_ADD2_Msk (0x1UL << USB_DADDR_ADD2_Pos) /*!< 0x00000004 */\r
+#define USB_DADDR_ADD2 USB_DADDR_ADD2_Msk /*!<Bit 2 */\r
+#define USB_DADDR_ADD3_Pos (3U) \r
+#define USB_DADDR_ADD3_Msk (0x1UL << USB_DADDR_ADD3_Pos) /*!< 0x00000008 */\r
+#define USB_DADDR_ADD3 USB_DADDR_ADD3_Msk /*!<Bit 3 */\r
+#define USB_DADDR_ADD4_Pos (4U) \r
+#define USB_DADDR_ADD4_Msk (0x1UL << USB_DADDR_ADD4_Pos) /*!< 0x00000010 */\r
+#define USB_DADDR_ADD4 USB_DADDR_ADD4_Msk /*!<Bit 4 */\r
+#define USB_DADDR_ADD5_Pos (5U) \r
+#define USB_DADDR_ADD5_Msk (0x1UL << USB_DADDR_ADD5_Pos) /*!< 0x00000020 */\r
+#define USB_DADDR_ADD5 USB_DADDR_ADD5_Msk /*!<Bit 5 */\r
+#define USB_DADDR_ADD6_Pos (6U) \r
+#define USB_DADDR_ADD6_Msk (0x1UL << USB_DADDR_ADD6_Pos) /*!< 0x00000040 */\r
+#define USB_DADDR_ADD6 USB_DADDR_ADD6_Msk /*!<Bit 6 */\r
+\r
+#define USB_DADDR_EF_Pos (7U) \r
+#define USB_DADDR_EF_Msk (0x1UL << USB_DADDR_EF_Pos) /*!< 0x00000080 */\r
+#define USB_DADDR_EF USB_DADDR_EF_Msk /*!<Enable Function */\r
+\r
+/****************** Bit definition for USB_BTABLE register ******************/ \r
+#define USB_BTABLE_BTABLE_Pos (3U) \r
+#define USB_BTABLE_BTABLE_Msk (0x1FFFUL << USB_BTABLE_BTABLE_Pos) /*!< 0x0000FFF8 */\r
+#define USB_BTABLE_BTABLE USB_BTABLE_BTABLE_Msk /*!<Buffer Table */\r
+\r
+/*!< Buffer descriptor table */\r
+/***************** Bit definition for USB_ADDR0_TX register *****************/\r
+#define USB_ADDR0_TX_ADDR0_TX_Pos (1U) \r
+#define USB_ADDR0_TX_ADDR0_TX_Msk (0x7FFFUL << USB_ADDR0_TX_ADDR0_TX_Pos) /*!< 0x0000FFFE */\r
+#define USB_ADDR0_TX_ADDR0_TX USB_ADDR0_TX_ADDR0_TX_Msk /*!< Transmission Buffer Address 0 */\r
+\r
+/***************** Bit definition for USB_ADDR1_TX register *****************/\r
+#define USB_ADDR1_TX_ADDR1_TX_Pos (1U) \r
+#define USB_ADDR1_TX_ADDR1_TX_Msk (0x7FFFUL << USB_ADDR1_TX_ADDR1_TX_Pos) /*!< 0x0000FFFE */\r
+#define USB_ADDR1_TX_ADDR1_TX USB_ADDR1_TX_ADDR1_TX_Msk /*!< Transmission Buffer Address 1 */\r
+\r
+/***************** Bit definition for USB_ADDR2_TX register *****************/\r
+#define USB_ADDR2_TX_ADDR2_TX_Pos (1U) \r
+#define USB_ADDR2_TX_ADDR2_TX_Msk (0x7FFFUL << USB_ADDR2_TX_ADDR2_TX_Pos) /*!< 0x0000FFFE */\r
+#define USB_ADDR2_TX_ADDR2_TX USB_ADDR2_TX_ADDR2_TX_Msk /*!< Transmission Buffer Address 2 */\r
+\r
+/***************** Bit definition for USB_ADDR3_TX register *****************/\r
+#define USB_ADDR3_TX_ADDR3_TX_Pos (1U) \r
+#define USB_ADDR3_TX_ADDR3_TX_Msk (0x7FFFUL << USB_ADDR3_TX_ADDR3_TX_Pos) /*!< 0x0000FFFE */\r
+#define USB_ADDR3_TX_ADDR3_TX USB_ADDR3_TX_ADDR3_TX_Msk /*!< Transmission Buffer Address 3 */\r
+\r
+/***************** Bit definition for USB_ADDR4_TX register *****************/\r
+#define USB_ADDR4_TX_ADDR4_TX_Pos (1U) \r
+#define USB_ADDR4_TX_ADDR4_TX_Msk (0x7FFFUL << USB_ADDR4_TX_ADDR4_TX_Pos) /*!< 0x0000FFFE */\r
+#define USB_ADDR4_TX_ADDR4_TX USB_ADDR4_TX_ADDR4_TX_Msk /*!< Transmission Buffer Address 4 */\r
+\r
+/***************** Bit definition for USB_ADDR5_TX register *****************/\r
+#define USB_ADDR5_TX_ADDR5_TX_Pos (1U) \r
+#define USB_ADDR5_TX_ADDR5_TX_Msk (0x7FFFUL << USB_ADDR5_TX_ADDR5_TX_Pos) /*!< 0x0000FFFE */\r
+#define USB_ADDR5_TX_ADDR5_TX USB_ADDR5_TX_ADDR5_TX_Msk /*!< Transmission Buffer Address 5 */\r
+\r
+/***************** Bit definition for USB_ADDR6_TX register *****************/\r
+#define USB_ADDR6_TX_ADDR6_TX_Pos (1U) \r
+#define USB_ADDR6_TX_ADDR6_TX_Msk (0x7FFFUL << USB_ADDR6_TX_ADDR6_TX_Pos) /*!< 0x0000FFFE */\r
+#define USB_ADDR6_TX_ADDR6_TX USB_ADDR6_TX_ADDR6_TX_Msk /*!< Transmission Buffer Address 6 */\r
+\r
+/***************** Bit definition for USB_ADDR7_TX register *****************/\r
+#define USB_ADDR7_TX_ADDR7_TX_Pos (1U) \r
+#define USB_ADDR7_TX_ADDR7_TX_Msk (0x7FFFUL << USB_ADDR7_TX_ADDR7_TX_Pos) /*!< 0x0000FFFE */\r
+#define USB_ADDR7_TX_ADDR7_TX USB_ADDR7_TX_ADDR7_TX_Msk /*!< Transmission Buffer Address 7 */\r
+\r
+/*----------------------------------------------------------------------------*/\r
+\r
+/***************** Bit definition for USB_COUNT0_TX register ****************/\r
+#define USB_COUNT0_TX_COUNT0_TX_Pos (0U) \r
+#define USB_COUNT0_TX_COUNT0_TX_Msk (0x3FFUL << USB_COUNT0_TX_COUNT0_TX_Pos) /*!< 0x000003FF */\r
+#define USB_COUNT0_TX_COUNT0_TX USB_COUNT0_TX_COUNT0_TX_Msk /*!< Transmission Byte Count 0 */\r
+\r
+/***************** Bit definition for USB_COUNT1_TX register ****************/\r
+#define USB_COUNT1_TX_COUNT1_TX_Pos (0U) \r
+#define USB_COUNT1_TX_COUNT1_TX_Msk (0x3FFUL << USB_COUNT1_TX_COUNT1_TX_Pos) /*!< 0x000003FF */\r
+#define USB_COUNT1_TX_COUNT1_TX USB_COUNT1_TX_COUNT1_TX_Msk /*!< Transmission Byte Count 1 */\r
+\r
+/***************** Bit definition for USB_COUNT2_TX register ****************/\r
+#define USB_COUNT2_TX_COUNT2_TX_Pos (0U) \r
+#define USB_COUNT2_TX_COUNT2_TX_Msk (0x3FFUL << USB_COUNT2_TX_COUNT2_TX_Pos) /*!< 0x000003FF */\r
+#define USB_COUNT2_TX_COUNT2_TX USB_COUNT2_TX_COUNT2_TX_Msk /*!< Transmission Byte Count 2 */\r
+\r
+/***************** Bit definition for USB_COUNT3_TX register ****************/\r
+#define USB_COUNT3_TX_COUNT3_TX_Pos (0U) \r
+#define USB_COUNT3_TX_COUNT3_TX_Msk (0x3FFUL << USB_COUNT3_TX_COUNT3_TX_Pos) /*!< 0x000003FF */\r
+#define USB_COUNT3_TX_COUNT3_TX USB_COUNT3_TX_COUNT3_TX_Msk /*!< Transmission Byte Count 3 */\r
+\r
+/***************** Bit definition for USB_COUNT4_TX register ****************/\r
+#define USB_COUNT4_TX_COUNT4_TX_Pos (0U) \r
+#define USB_COUNT4_TX_COUNT4_TX_Msk (0x3FFUL << USB_COUNT4_TX_COUNT4_TX_Pos) /*!< 0x000003FF */\r
+#define USB_COUNT4_TX_COUNT4_TX USB_COUNT4_TX_COUNT4_TX_Msk /*!< Transmission Byte Count 4 */\r
+\r
+/***************** Bit definition for USB_COUNT5_TX register ****************/\r
+#define USB_COUNT5_TX_COUNT5_TX_Pos (0U) \r
+#define USB_COUNT5_TX_COUNT5_TX_Msk (0x3FFUL << USB_COUNT5_TX_COUNT5_TX_Pos) /*!< 0x000003FF */\r
+#define USB_COUNT5_TX_COUNT5_TX USB_COUNT5_TX_COUNT5_TX_Msk /*!< Transmission Byte Count 5 */\r
+\r
+/***************** Bit definition for USB_COUNT6_TX register ****************/\r
+#define USB_COUNT6_TX_COUNT6_TX_Pos (0U) \r
+#define USB_COUNT6_TX_COUNT6_TX_Msk (0x3FFUL << USB_COUNT6_TX_COUNT6_TX_Pos) /*!< 0x000003FF */\r
+#define USB_COUNT6_TX_COUNT6_TX USB_COUNT6_TX_COUNT6_TX_Msk /*!< Transmission Byte Count 6 */\r
+\r
+/***************** Bit definition for USB_COUNT7_TX register ****************/\r
+#define USB_COUNT7_TX_COUNT7_TX_Pos (0U) \r
+#define USB_COUNT7_TX_COUNT7_TX_Msk (0x3FFUL << USB_COUNT7_TX_COUNT7_TX_Pos) /*!< 0x000003FF */\r
+#define USB_COUNT7_TX_COUNT7_TX USB_COUNT7_TX_COUNT7_TX_Msk /*!< Transmission Byte Count 7 */\r
+\r
+/*----------------------------------------------------------------------------*/\r
+\r
+/**************** Bit definition for USB_COUNT0_TX_0 register ***************/\r
+#define USB_COUNT0_TX_0_COUNT0_TX_0 (0x000003FFU) /*!< Transmission Byte Count 0 (low) */\r
+\r
+/**************** Bit definition for USB_COUNT0_TX_1 register ***************/\r
+#define USB_COUNT0_TX_1_COUNT0_TX_1 (0x03FF0000U) /*!< Transmission Byte Count 0 (high) */\r
+\r
+/**************** Bit definition for USB_COUNT1_TX_0 register ***************/\r
+#define USB_COUNT1_TX_0_COUNT1_TX_0 (0x000003FFU) /*!< Transmission Byte Count 1 (low) */\r
+\r
+/**************** Bit definition for USB_COUNT1_TX_1 register ***************/\r
+#define USB_COUNT1_TX_1_COUNT1_TX_1 (0x03FF0000U) /*!< Transmission Byte Count 1 (high) */\r
+\r
+/**************** Bit definition for USB_COUNT2_TX_0 register ***************/\r
+#define USB_COUNT2_TX_0_COUNT2_TX_0 (0x000003FFU) /*!< Transmission Byte Count 2 (low) */\r
+\r
+/**************** Bit definition for USB_COUNT2_TX_1 register ***************/\r
+#define USB_COUNT2_TX_1_COUNT2_TX_1 (0x03FF0000U) /*!< Transmission Byte Count 2 (high) */\r
+\r
+/**************** Bit definition for USB_COUNT3_TX_0 register ***************/\r
+#define USB_COUNT3_TX_0_COUNT3_TX_0 (0x000003FFU) /*!< Transmission Byte Count 3 (low) */\r
+\r
+/**************** Bit definition for USB_COUNT3_TX_1 register ***************/\r
+#define USB_COUNT3_TX_1_COUNT3_TX_1 (0x03FF0000U) /*!< Transmission Byte Count 3 (high) */\r
+\r
+/**************** Bit definition for USB_COUNT4_TX_0 register ***************/\r
+#define USB_COUNT4_TX_0_COUNT4_TX_0 (0x000003FFU) /*!< Transmission Byte Count 4 (low) */\r
+\r
+/**************** Bit definition for USB_COUNT4_TX_1 register ***************/\r
+#define USB_COUNT4_TX_1_COUNT4_TX_1 (0x03FF0000U) /*!< Transmission Byte Count 4 (high) */\r
+\r
+/**************** Bit definition for USB_COUNT5_TX_0 register ***************/\r
+#define USB_COUNT5_TX_0_COUNT5_TX_0 (0x000003FFU) /*!< Transmission Byte Count 5 (low) */\r
+\r
+/**************** Bit definition for USB_COUNT5_TX_1 register ***************/\r
+#define USB_COUNT5_TX_1_COUNT5_TX_1 (0x03FF0000U) /*!< Transmission Byte Count 5 (high) */\r
+\r
+/**************** Bit definition for USB_COUNT6_TX_0 register ***************/\r
+#define USB_COUNT6_TX_0_COUNT6_TX_0 (0x000003FFU) /*!< Transmission Byte Count 6 (low) */\r
+\r
+/**************** Bit definition for USB_COUNT6_TX_1 register ***************/\r
+#define USB_COUNT6_TX_1_COUNT6_TX_1 (0x03FF0000U) /*!< Transmission Byte Count 6 (high) */\r
+\r
+/**************** Bit definition for USB_COUNT7_TX_0 register ***************/\r
+#define USB_COUNT7_TX_0_COUNT7_TX_0 (0x000003FFU) /*!< Transmission Byte Count 7 (low) */\r
+\r
+/**************** Bit definition for USB_COUNT7_TX_1 register ***************/\r
+#define USB_COUNT7_TX_1_COUNT7_TX_1 (0x03FF0000U) /*!< Transmission Byte Count 7 (high) */\r
+\r
+/*----------------------------------------------------------------------------*/\r
+\r
+/***************** Bit definition for USB_ADDR0_RX register *****************/\r
+#define USB_ADDR0_RX_ADDR0_RX_Pos (1U) \r
+#define USB_ADDR0_RX_ADDR0_RX_Msk (0x7FFFUL << USB_ADDR0_RX_ADDR0_RX_Pos) /*!< 0x0000FFFE */\r
+#define USB_ADDR0_RX_ADDR0_RX USB_ADDR0_RX_ADDR0_RX_Msk /*!< Reception Buffer Address 0 */\r
+\r
+/***************** Bit definition for USB_ADDR1_RX register *****************/\r
+#define USB_ADDR1_RX_ADDR1_RX_Pos (1U) \r
+#define USB_ADDR1_RX_ADDR1_RX_Msk (0x7FFFUL << USB_ADDR1_RX_ADDR1_RX_Pos) /*!< 0x0000FFFE */\r
+#define USB_ADDR1_RX_ADDR1_RX USB_ADDR1_RX_ADDR1_RX_Msk /*!< Reception Buffer Address 1 */\r
+\r
+/***************** Bit definition for USB_ADDR2_RX register *****************/\r
+#define USB_ADDR2_RX_ADDR2_RX_Pos (1U) \r
+#define USB_ADDR2_RX_ADDR2_RX_Msk (0x7FFFUL << USB_ADDR2_RX_ADDR2_RX_Pos) /*!< 0x0000FFFE */\r
+#define USB_ADDR2_RX_ADDR2_RX USB_ADDR2_RX_ADDR2_RX_Msk /*!< Reception Buffer Address 2 */\r
+\r
+/***************** Bit definition for USB_ADDR3_RX register *****************/\r
+#define USB_ADDR3_RX_ADDR3_RX_Pos (1U) \r
+#define USB_ADDR3_RX_ADDR3_RX_Msk (0x7FFFUL << USB_ADDR3_RX_ADDR3_RX_Pos) /*!< 0x0000FFFE */\r
+#define USB_ADDR3_RX_ADDR3_RX USB_ADDR3_RX_ADDR3_RX_Msk /*!< Reception Buffer Address 3 */\r
+\r
+/***************** Bit definition for USB_ADDR4_RX register *****************/\r
+#define USB_ADDR4_RX_ADDR4_RX_Pos (1U) \r
+#define USB_ADDR4_RX_ADDR4_RX_Msk (0x7FFFUL << USB_ADDR4_RX_ADDR4_RX_Pos) /*!< 0x0000FFFE */\r
+#define USB_ADDR4_RX_ADDR4_RX USB_ADDR4_RX_ADDR4_RX_Msk /*!< Reception Buffer Address 4 */\r
+\r
+/***************** Bit definition for USB_ADDR5_RX register *****************/\r
+#define USB_ADDR5_RX_ADDR5_RX_Pos (1U) \r
+#define USB_ADDR5_RX_ADDR5_RX_Msk (0x7FFFUL << USB_ADDR5_RX_ADDR5_RX_Pos) /*!< 0x0000FFFE */\r
+#define USB_ADDR5_RX_ADDR5_RX USB_ADDR5_RX_ADDR5_RX_Msk /*!< Reception Buffer Address 5 */\r
+\r
+/***************** Bit definition for USB_ADDR6_RX register *****************/\r
+#define USB_ADDR6_RX_ADDR6_RX_Pos (1U) \r
+#define USB_ADDR6_RX_ADDR6_RX_Msk (0x7FFFUL << USB_ADDR6_RX_ADDR6_RX_Pos) /*!< 0x0000FFFE */\r
+#define USB_ADDR6_RX_ADDR6_RX USB_ADDR6_RX_ADDR6_RX_Msk /*!< Reception Buffer Address 6 */\r
+\r
+/***************** Bit definition for USB_ADDR7_RX register *****************/\r
+#define USB_ADDR7_RX_ADDR7_RX_Pos (1U) \r
+#define USB_ADDR7_RX_ADDR7_RX_Msk (0x7FFFUL << USB_ADDR7_RX_ADDR7_RX_Pos) /*!< 0x0000FFFE */\r
+#define USB_ADDR7_RX_ADDR7_RX USB_ADDR7_RX_ADDR7_RX_Msk /*!< Reception Buffer Address 7 */\r
+\r
+/*----------------------------------------------------------------------------*/\r
+\r
+/***************** Bit definition for USB_COUNT0_RX register ****************/\r
+#define USB_COUNT0_RX_COUNT0_RX_Pos (0U) \r
+#define USB_COUNT0_RX_COUNT0_RX_Msk (0x3FFUL << USB_COUNT0_RX_COUNT0_RX_Pos) /*!< 0x000003FF */\r
+#define USB_COUNT0_RX_COUNT0_RX USB_COUNT0_RX_COUNT0_RX_Msk /*!< Reception Byte Count */\r
+\r
+#define USB_COUNT0_RX_NUM_BLOCK_Pos (10U) \r
+#define USB_COUNT0_RX_NUM_BLOCK_Msk (0x1FUL << USB_COUNT0_RX_NUM_BLOCK_Pos) /*!< 0x00007C00 */\r
+#define USB_COUNT0_RX_NUM_BLOCK USB_COUNT0_RX_NUM_BLOCK_Msk /*!< NUM_BLOCK[4:0] bits (Number of blocks) */\r
+#define USB_COUNT0_RX_NUM_BLOCK_0 (0x01UL << USB_COUNT0_RX_NUM_BLOCK_Pos) /*!< 0x00000400 */\r
+#define USB_COUNT0_RX_NUM_BLOCK_1 (0x02UL << USB_COUNT0_RX_NUM_BLOCK_Pos) /*!< 0x00000800 */\r
+#define USB_COUNT0_RX_NUM_BLOCK_2 (0x04UL << USB_COUNT0_RX_NUM_BLOCK_Pos) /*!< 0x00001000 */\r
+#define USB_COUNT0_RX_NUM_BLOCK_3 (0x08UL << USB_COUNT0_RX_NUM_BLOCK_Pos) /*!< 0x00002000 */\r
+#define USB_COUNT0_RX_NUM_BLOCK_4 (0x10UL << USB_COUNT0_RX_NUM_BLOCK_Pos) /*!< 0x00004000 */\r
+\r
+#define USB_COUNT0_RX_BLSIZE_Pos (15U) \r
+#define USB_COUNT0_RX_BLSIZE_Msk (0x1UL << USB_COUNT0_RX_BLSIZE_Pos) /*!< 0x00008000 */\r
+#define USB_COUNT0_RX_BLSIZE USB_COUNT0_RX_BLSIZE_Msk /*!< BLock SIZE */\r
+\r
+/***************** Bit definition for USB_COUNT1_RX register ****************/\r
+#define USB_COUNT1_RX_COUNT1_RX_Pos (0U) \r
+#define USB_COUNT1_RX_COUNT1_RX_Msk (0x3FFUL << USB_COUNT1_RX_COUNT1_RX_Pos) /*!< 0x000003FF */\r
+#define USB_COUNT1_RX_COUNT1_RX USB_COUNT1_RX_COUNT1_RX_Msk /*!< Reception Byte Count */\r
+\r
+#define USB_COUNT1_RX_NUM_BLOCK_Pos (10U) \r
+#define USB_COUNT1_RX_NUM_BLOCK_Msk (0x1FUL << USB_COUNT1_RX_NUM_BLOCK_Pos) /*!< 0x00007C00 */\r
+#define USB_COUNT1_RX_NUM_BLOCK USB_COUNT1_RX_NUM_BLOCK_Msk /*!< NUM_BLOCK[4:0] bits (Number of blocks) */\r
+#define USB_COUNT1_RX_NUM_BLOCK_0 (0x01UL << USB_COUNT1_RX_NUM_BLOCK_Pos) /*!< 0x00000400 */\r
+#define USB_COUNT1_RX_NUM_BLOCK_1 (0x02UL << USB_COUNT1_RX_NUM_BLOCK_Pos) /*!< 0x00000800 */\r
+#define USB_COUNT1_RX_NUM_BLOCK_2 (0x04UL << USB_COUNT1_RX_NUM_BLOCK_Pos) /*!< 0x00001000 */\r
+#define USB_COUNT1_RX_NUM_BLOCK_3 (0x08UL << USB_COUNT1_RX_NUM_BLOCK_Pos) /*!< 0x00002000 */\r
+#define USB_COUNT1_RX_NUM_BLOCK_4 (0x10UL << USB_COUNT1_RX_NUM_BLOCK_Pos) /*!< 0x00004000 */\r
+\r
+#define USB_COUNT1_RX_BLSIZE_Pos (15U) \r
+#define USB_COUNT1_RX_BLSIZE_Msk (0x1UL << USB_COUNT1_RX_BLSIZE_Pos) /*!< 0x00008000 */\r
+#define USB_COUNT1_RX_BLSIZE USB_COUNT1_RX_BLSIZE_Msk /*!< BLock SIZE */\r
+\r
+/***************** Bit definition for USB_COUNT2_RX register ****************/\r
+#define USB_COUNT2_RX_COUNT2_RX_Pos (0U) \r
+#define USB_COUNT2_RX_COUNT2_RX_Msk (0x3FFUL << USB_COUNT2_RX_COUNT2_RX_Pos) /*!< 0x000003FF */\r
+#define USB_COUNT2_RX_COUNT2_RX USB_COUNT2_RX_COUNT2_RX_Msk /*!< Reception Byte Count */\r
+\r
+#define USB_COUNT2_RX_NUM_BLOCK_Pos (10U) \r
+#define USB_COUNT2_RX_NUM_BLOCK_Msk (0x1FUL << USB_COUNT2_RX_NUM_BLOCK_Pos) /*!< 0x00007C00 */\r
+#define USB_COUNT2_RX_NUM_BLOCK USB_COUNT2_RX_NUM_BLOCK_Msk /*!< NUM_BLOCK[4:0] bits (Number of blocks) */\r
+#define USB_COUNT2_RX_NUM_BLOCK_0 (0x01UL << USB_COUNT2_RX_NUM_BLOCK_Pos) /*!< 0x00000400 */\r
+#define USB_COUNT2_RX_NUM_BLOCK_1 (0x02UL << USB_COUNT2_RX_NUM_BLOCK_Pos) /*!< 0x00000800 */\r
+#define USB_COUNT2_RX_NUM_BLOCK_2 (0x04UL << USB_COUNT2_RX_NUM_BLOCK_Pos) /*!< 0x00001000 */\r
+#define USB_COUNT2_RX_NUM_BLOCK_3 (0x08UL << USB_COUNT2_RX_NUM_BLOCK_Pos) /*!< 0x00002000 */\r
+#define USB_COUNT2_RX_NUM_BLOCK_4 (0x10UL << USB_COUNT2_RX_NUM_BLOCK_Pos) /*!< 0x00004000 */\r
+\r
+#define USB_COUNT2_RX_BLSIZE_Pos (15U) \r
+#define USB_COUNT2_RX_BLSIZE_Msk (0x1UL << USB_COUNT2_RX_BLSIZE_Pos) /*!< 0x00008000 */\r
+#define USB_COUNT2_RX_BLSIZE USB_COUNT2_RX_BLSIZE_Msk /*!< BLock SIZE */\r
+\r
+/***************** Bit definition for USB_COUNT3_RX register ****************/\r
+#define USB_COUNT3_RX_COUNT3_RX_Pos (0U) \r
+#define USB_COUNT3_RX_COUNT3_RX_Msk (0x3FFUL << USB_COUNT3_RX_COUNT3_RX_Pos) /*!< 0x000003FF */\r
+#define USB_COUNT3_RX_COUNT3_RX USB_COUNT3_RX_COUNT3_RX_Msk /*!< Reception Byte Count */\r
+\r
+#define USB_COUNT3_RX_NUM_BLOCK_Pos (10U) \r
+#define USB_COUNT3_RX_NUM_BLOCK_Msk (0x1FUL << USB_COUNT3_RX_NUM_BLOCK_Pos) /*!< 0x00007C00 */\r
+#define USB_COUNT3_RX_NUM_BLOCK USB_COUNT3_RX_NUM_BLOCK_Msk /*!< NUM_BLOCK[4:0] bits (Number of blocks) */\r
+#define USB_COUNT3_RX_NUM_BLOCK_0 (0x01UL << USB_COUNT3_RX_NUM_BLOCK_Pos) /*!< 0x00000400 */\r
+#define USB_COUNT3_RX_NUM_BLOCK_1 (0x02UL << USB_COUNT3_RX_NUM_BLOCK_Pos) /*!< 0x00000800 */\r
+#define USB_COUNT3_RX_NUM_BLOCK_2 (0x04UL << USB_COUNT3_RX_NUM_BLOCK_Pos) /*!< 0x00001000 */\r
+#define USB_COUNT3_RX_NUM_BLOCK_3 (0x08UL << USB_COUNT3_RX_NUM_BLOCK_Pos) /*!< 0x00002000 */\r
+#define USB_COUNT3_RX_NUM_BLOCK_4 (0x10UL << USB_COUNT3_RX_NUM_BLOCK_Pos) /*!< 0x00004000 */\r
+\r
+#define USB_COUNT3_RX_BLSIZE_Pos (15U) \r
+#define USB_COUNT3_RX_BLSIZE_Msk (0x1UL << USB_COUNT3_RX_BLSIZE_Pos) /*!< 0x00008000 */\r
+#define USB_COUNT3_RX_BLSIZE USB_COUNT3_RX_BLSIZE_Msk /*!< BLock SIZE */\r
+\r
+/***************** Bit definition for USB_COUNT4_RX register ****************/\r
+#define USB_COUNT4_RX_COUNT4_RX_Pos (0U) \r
+#define USB_COUNT4_RX_COUNT4_RX_Msk (0x3FFUL << USB_COUNT4_RX_COUNT4_RX_Pos) /*!< 0x000003FF */\r
+#define USB_COUNT4_RX_COUNT4_RX USB_COUNT4_RX_COUNT4_RX_Msk /*!< Reception Byte Count */\r
+\r
+#define USB_COUNT4_RX_NUM_BLOCK_Pos (10U) \r
+#define USB_COUNT4_RX_NUM_BLOCK_Msk (0x1FUL << USB_COUNT4_RX_NUM_BLOCK_Pos) /*!< 0x00007C00 */\r
+#define USB_COUNT4_RX_NUM_BLOCK USB_COUNT4_RX_NUM_BLOCK_Msk /*!< NUM_BLOCK[4:0] bits (Number of blocks) */\r
+#define USB_COUNT4_RX_NUM_BLOCK_0 (0x01UL << USB_COUNT4_RX_NUM_BLOCK_Pos) /*!< 0x00000400 */\r
+#define USB_COUNT4_RX_NUM_BLOCK_1 (0x02UL << USB_COUNT4_RX_NUM_BLOCK_Pos) /*!< 0x00000800 */\r
+#define USB_COUNT4_RX_NUM_BLOCK_2 (0x04UL << USB_COUNT4_RX_NUM_BLOCK_Pos) /*!< 0x00001000 */\r
+#define USB_COUNT4_RX_NUM_BLOCK_3 (0x08UL << USB_COUNT4_RX_NUM_BLOCK_Pos) /*!< 0x00002000 */\r
+#define USB_COUNT4_RX_NUM_BLOCK_4 (0x10UL << USB_COUNT4_RX_NUM_BLOCK_Pos) /*!< 0x00004000 */\r
+\r
+#define USB_COUNT4_RX_BLSIZE_Pos (15U) \r
+#define USB_COUNT4_RX_BLSIZE_Msk (0x1UL << USB_COUNT4_RX_BLSIZE_Pos) /*!< 0x00008000 */\r
+#define USB_COUNT4_RX_BLSIZE USB_COUNT4_RX_BLSIZE_Msk /*!< BLock SIZE */\r
+\r
+/***************** Bit definition for USB_COUNT5_RX register ****************/\r
+#define USB_COUNT5_RX_COUNT5_RX_Pos (0U) \r
+#define USB_COUNT5_RX_COUNT5_RX_Msk (0x3FFUL << USB_COUNT5_RX_COUNT5_RX_Pos) /*!< 0x000003FF */\r
+#define USB_COUNT5_RX_COUNT5_RX USB_COUNT5_RX_COUNT5_RX_Msk /*!< Reception Byte Count */\r
+\r
+#define USB_COUNT5_RX_NUM_BLOCK_Pos (10U) \r
+#define USB_COUNT5_RX_NUM_BLOCK_Msk (0x1FUL << USB_COUNT5_RX_NUM_BLOCK_Pos) /*!< 0x00007C00 */\r
+#define USB_COUNT5_RX_NUM_BLOCK USB_COUNT5_RX_NUM_BLOCK_Msk /*!< NUM_BLOCK[4:0] bits (Number of blocks) */\r
+#define USB_COUNT5_RX_NUM_BLOCK_0 (0x01UL << USB_COUNT5_RX_NUM_BLOCK_Pos) /*!< 0x00000400 */\r
+#define USB_COUNT5_RX_NUM_BLOCK_1 (0x02UL << USB_COUNT5_RX_NUM_BLOCK_Pos) /*!< 0x00000800 */\r
+#define USB_COUNT5_RX_NUM_BLOCK_2 (0x04UL << USB_COUNT5_RX_NUM_BLOCK_Pos) /*!< 0x00001000 */\r
+#define USB_COUNT5_RX_NUM_BLOCK_3 (0x08UL << USB_COUNT5_RX_NUM_BLOCK_Pos) /*!< 0x00002000 */\r
+#define USB_COUNT5_RX_NUM_BLOCK_4 (0x10UL << USB_COUNT5_RX_NUM_BLOCK_Pos) /*!< 0x00004000 */\r
+\r
+#define USB_COUNT5_RX_BLSIZE_Pos (15U) \r
+#define USB_COUNT5_RX_BLSIZE_Msk (0x1UL << USB_COUNT5_RX_BLSIZE_Pos) /*!< 0x00008000 */\r
+#define USB_COUNT5_RX_BLSIZE USB_COUNT5_RX_BLSIZE_Msk /*!< BLock SIZE */\r
+\r
+/***************** Bit definition for USB_COUNT6_RX register ****************/\r
+#define USB_COUNT6_RX_COUNT6_RX_Pos (0U) \r
+#define USB_COUNT6_RX_COUNT6_RX_Msk (0x3FFUL << USB_COUNT6_RX_COUNT6_RX_Pos) /*!< 0x000003FF */\r
+#define USB_COUNT6_RX_COUNT6_RX USB_COUNT6_RX_COUNT6_RX_Msk /*!< Reception Byte Count */\r
+\r
+#define USB_COUNT6_RX_NUM_BLOCK_Pos (10U) \r
+#define USB_COUNT6_RX_NUM_BLOCK_Msk (0x1FUL << USB_COUNT6_RX_NUM_BLOCK_Pos) /*!< 0x00007C00 */\r
+#define USB_COUNT6_RX_NUM_BLOCK USB_COUNT6_RX_NUM_BLOCK_Msk /*!< NUM_BLOCK[4:0] bits (Number of blocks) */\r
+#define USB_COUNT6_RX_NUM_BLOCK_0 (0x01UL << USB_COUNT6_RX_NUM_BLOCK_Pos) /*!< 0x00000400 */\r
+#define USB_COUNT6_RX_NUM_BLOCK_1 (0x02UL << USB_COUNT6_RX_NUM_BLOCK_Pos) /*!< 0x00000800 */\r
+#define USB_COUNT6_RX_NUM_BLOCK_2 (0x04UL << USB_COUNT6_RX_NUM_BLOCK_Pos) /*!< 0x00001000 */\r
+#define USB_COUNT6_RX_NUM_BLOCK_3 (0x08UL << USB_COUNT6_RX_NUM_BLOCK_Pos) /*!< 0x00002000 */\r
+#define USB_COUNT6_RX_NUM_BLOCK_4 (0x10UL << USB_COUNT6_RX_NUM_BLOCK_Pos) /*!< 0x00004000 */\r
+\r
+#define USB_COUNT6_RX_BLSIZE_Pos (15U) \r
+#define USB_COUNT6_RX_BLSIZE_Msk (0x1UL << USB_COUNT6_RX_BLSIZE_Pos) /*!< 0x00008000 */\r
+#define USB_COUNT6_RX_BLSIZE USB_COUNT6_RX_BLSIZE_Msk /*!< BLock SIZE */\r
+\r
+/***************** Bit definition for USB_COUNT7_RX register ****************/\r
+#define USB_COUNT7_RX_COUNT7_RX_Pos (0U) \r
+#define USB_COUNT7_RX_COUNT7_RX_Msk (0x3FFUL << USB_COUNT7_RX_COUNT7_RX_Pos) /*!< 0x000003FF */\r
+#define USB_COUNT7_RX_COUNT7_RX USB_COUNT7_RX_COUNT7_RX_Msk /*!< Reception Byte Count */\r
+\r
+#define USB_COUNT7_RX_NUM_BLOCK_Pos (10U) \r
+#define USB_COUNT7_RX_NUM_BLOCK_Msk (0x1FUL << USB_COUNT7_RX_NUM_BLOCK_Pos) /*!< 0x00007C00 */\r
+#define USB_COUNT7_RX_NUM_BLOCK USB_COUNT7_RX_NUM_BLOCK_Msk /*!< NUM_BLOCK[4:0] bits (Number of blocks) */\r
+#define USB_COUNT7_RX_NUM_BLOCK_0 (0x01UL << USB_COUNT7_RX_NUM_BLOCK_Pos) /*!< 0x00000400 */\r
+#define USB_COUNT7_RX_NUM_BLOCK_1 (0x02UL << USB_COUNT7_RX_NUM_BLOCK_Pos) /*!< 0x00000800 */\r
+#define USB_COUNT7_RX_NUM_BLOCK_2 (0x04UL << USB_COUNT7_RX_NUM_BLOCK_Pos) /*!< 0x00001000 */\r
+#define USB_COUNT7_RX_NUM_BLOCK_3 (0x08UL << USB_COUNT7_RX_NUM_BLOCK_Pos) /*!< 0x00002000 */\r
+#define USB_COUNT7_RX_NUM_BLOCK_4 (0x10UL << USB_COUNT7_RX_NUM_BLOCK_Pos) /*!< 0x00004000 */\r
+\r
+#define USB_COUNT7_RX_BLSIZE_Pos (15U) \r
+#define USB_COUNT7_RX_BLSIZE_Msk (0x1UL << USB_COUNT7_RX_BLSIZE_Pos) /*!< 0x00008000 */\r
+#define USB_COUNT7_RX_BLSIZE USB_COUNT7_RX_BLSIZE_Msk /*!< BLock SIZE */\r
+\r
+/*----------------------------------------------------------------------------*/\r
+\r
+/**************** Bit definition for USB_COUNT0_RX_0 register ***************/\r
+#define USB_COUNT0_RX_0_COUNT0_RX_0 (0x000003FFU) /*!< Reception Byte Count (low) */\r
+\r
+#define USB_COUNT0_RX_0_NUM_BLOCK_0 (0x00007C00U) /*!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */\r
+#define USB_COUNT0_RX_0_NUM_BLOCK_0_0 (0x00000400U) /*!< Bit 0 */\r
+#define USB_COUNT0_RX_0_NUM_BLOCK_0_1 (0x00000800U) /*!< Bit 1 */\r
+#define USB_COUNT0_RX_0_NUM_BLOCK_0_2 (0x00001000U) /*!< Bit 2 */\r
+#define USB_COUNT0_RX_0_NUM_BLOCK_0_3 (0x00002000U) /*!< Bit 3 */\r
+#define USB_COUNT0_RX_0_NUM_BLOCK_0_4 (0x00004000U) /*!< Bit 4 */\r
+\r
+#define USB_COUNT0_RX_0_BLSIZE_0 (0x00008000U) /*!< BLock SIZE (low) */\r
+\r
+/**************** Bit definition for USB_COUNT0_RX_1 register ***************/\r
+#define USB_COUNT0_RX_1_COUNT0_RX_1 (0x03FF0000U) /*!< Reception Byte Count (high) */\r
+\r
+#define USB_COUNT0_RX_1_NUM_BLOCK_1 (0x7C000000U) /*!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */\r
+#define USB_COUNT0_RX_1_NUM_BLOCK_1_0 (0x04000000U) /*!< Bit 1 */\r
+#define USB_COUNT0_RX_1_NUM_BLOCK_1_1 (0x08000000U) /*!< Bit 1 */\r
+#define USB_COUNT0_RX_1_NUM_BLOCK_1_2 (0x10000000U) /*!< Bit 2 */\r
+#define USB_COUNT0_RX_1_NUM_BLOCK_1_3 (0x20000000U) /*!< Bit 3 */\r
+#define USB_COUNT0_RX_1_NUM_BLOCK_1_4 (0x40000000U) /*!< Bit 4 */\r
+\r
+#define USB_COUNT0_RX_1_BLSIZE_1 (0x80000000U) /*!< BLock SIZE (high) */\r
+\r
+/**************** Bit definition for USB_COUNT1_RX_0 register ***************/\r
+#define USB_COUNT1_RX_0_COUNT1_RX_0 (0x000003FFU) /*!< Reception Byte Count (low) */\r
+\r
+#define USB_COUNT1_RX_0_NUM_BLOCK_0 (0x00007C00U) /*!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */\r
+#define USB_COUNT1_RX_0_NUM_BLOCK_0_0 (0x00000400U) /*!< Bit 0 */\r
+#define USB_COUNT1_RX_0_NUM_BLOCK_0_1 (0x00000800U) /*!< Bit 1 */\r
+#define USB_COUNT1_RX_0_NUM_BLOCK_0_2 (0x00001000U) /*!< Bit 2 */\r
+#define USB_COUNT1_RX_0_NUM_BLOCK_0_3 (0x00002000U) /*!< Bit 3 */\r
+#define USB_COUNT1_RX_0_NUM_BLOCK_0_4 (0x00004000U) /*!< Bit 4 */\r
+\r
+#define USB_COUNT1_RX_0_BLSIZE_0 (0x00008000U) /*!< BLock SIZE (low) */\r
+\r
+/**************** Bit definition for USB_COUNT1_RX_1 register ***************/\r
+#define USB_COUNT1_RX_1_COUNT1_RX_1 (0x03FF0000U) /*!< Reception Byte Count (high) */\r
+\r
+#define USB_COUNT1_RX_1_NUM_BLOCK_1 (0x7C000000U) /*!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */\r
+#define USB_COUNT1_RX_1_NUM_BLOCK_1_0 (0x04000000U) /*!< Bit 0 */\r
+#define USB_COUNT1_RX_1_NUM_BLOCK_1_1 (0x08000000U) /*!< Bit 1 */\r
+#define USB_COUNT1_RX_1_NUM_BLOCK_1_2 (0x10000000U) /*!< Bit 2 */\r
+#define USB_COUNT1_RX_1_NUM_BLOCK_1_3 (0x20000000U) /*!< Bit 3 */\r
+#define USB_COUNT1_RX_1_NUM_BLOCK_1_4 (0x40000000U) /*!< Bit 4 */\r
+\r
+#define USB_COUNT1_RX_1_BLSIZE_1 (0x80000000U) /*!< BLock SIZE (high) */\r
+\r
+/**************** Bit definition for USB_COUNT2_RX_0 register ***************/\r
+#define USB_COUNT2_RX_0_COUNT2_RX_0 (0x000003FFU) /*!< Reception Byte Count (low) */\r
+\r
+#define USB_COUNT2_RX_0_NUM_BLOCK_0 (0x00007C00U) /*!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */\r
+#define USB_COUNT2_RX_0_NUM_BLOCK_0_0 (0x00000400U) /*!< Bit 0 */\r
+#define USB_COUNT2_RX_0_NUM_BLOCK_0_1 (0x00000800U) /*!< Bit 1 */\r
+#define USB_COUNT2_RX_0_NUM_BLOCK_0_2 (0x00001000U) /*!< Bit 2 */\r
+#define USB_COUNT2_RX_0_NUM_BLOCK_0_3 (0x00002000U) /*!< Bit 3 */\r
+#define USB_COUNT2_RX_0_NUM_BLOCK_0_4 (0x00004000U) /*!< Bit 4 */\r
+\r
+#define USB_COUNT2_RX_0_BLSIZE_0 (0x00008000U) /*!< BLock SIZE (low) */\r
+\r
+/**************** Bit definition for USB_COUNT2_RX_1 register ***************/\r
+#define USB_COUNT2_RX_1_COUNT2_RX_1 (0x03FF0000U) /*!< Reception Byte Count (high) */\r
+\r
+#define USB_COUNT2_RX_1_NUM_BLOCK_1 (0x7C000000U) /*!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */\r
+#define USB_COUNT2_RX_1_NUM_BLOCK_1_0 (0x04000000U) /*!< Bit 0 */\r
+#define USB_COUNT2_RX_1_NUM_BLOCK_1_1 (0x08000000U) /*!< Bit 1 */\r
+#define USB_COUNT2_RX_1_NUM_BLOCK_1_2 (0x10000000U) /*!< Bit 2 */\r
+#define USB_COUNT2_RX_1_NUM_BLOCK_1_3 (0x20000000U) /*!< Bit 3 */\r
+#define USB_COUNT2_RX_1_NUM_BLOCK_1_4 (0x40000000U) /*!< Bit 4 */\r
+\r
+#define USB_COUNT2_RX_1_BLSIZE_1 (0x80000000U) /*!< BLock SIZE (high) */\r
+\r
+/**************** Bit definition for USB_COUNT3_RX_0 register ***************/\r
+#define USB_COUNT3_RX_0_COUNT3_RX_0 (0x000003FFU) /*!< Reception Byte Count (low) */\r
+\r
+#define USB_COUNT3_RX_0_NUM_BLOCK_0 (0x00007C00U) /*!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */\r
+#define USB_COUNT3_RX_0_NUM_BLOCK_0_0 (0x00000400U) /*!< Bit 0 */\r
+#define USB_COUNT3_RX_0_NUM_BLOCK_0_1 (0x00000800U) /*!< Bit 1 */\r
+#define USB_COUNT3_RX_0_NUM_BLOCK_0_2 (0x00001000U) /*!< Bit 2 */\r
+#define USB_COUNT3_RX_0_NUM_BLOCK_0_3 (0x00002000U) /*!< Bit 3 */\r
+#define USB_COUNT3_RX_0_NUM_BLOCK_0_4 (0x00004000U) /*!< Bit 4 */\r
+\r
+#define USB_COUNT3_RX_0_BLSIZE_0 (0x00008000U) /*!< BLock SIZE (low) */\r
+\r
+/**************** Bit definition for USB_COUNT3_RX_1 register ***************/\r
+#define USB_COUNT3_RX_1_COUNT3_RX_1 (0x03FF0000U) /*!< Reception Byte Count (high) */\r
+\r
+#define USB_COUNT3_RX_1_NUM_BLOCK_1 (0x7C000000U) /*!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */\r
+#define USB_COUNT3_RX_1_NUM_BLOCK_1_0 (0x04000000U) /*!< Bit 0 */\r
+#define USB_COUNT3_RX_1_NUM_BLOCK_1_1 (0x08000000U) /*!< Bit 1 */\r
+#define USB_COUNT3_RX_1_NUM_BLOCK_1_2 (0x10000000U) /*!< Bit 2 */\r
+#define USB_COUNT3_RX_1_NUM_BLOCK_1_3 (0x20000000U) /*!< Bit 3 */\r
+#define USB_COUNT3_RX_1_NUM_BLOCK_1_4 (0x40000000U) /*!< Bit 4 */\r
+\r
+#define USB_COUNT3_RX_1_BLSIZE_1 (0x80000000U) /*!< BLock SIZE (high) */\r
+\r
+/**************** Bit definition for USB_COUNT4_RX_0 register ***************/\r
+#define USB_COUNT4_RX_0_COUNT4_RX_0 (0x000003FFU) /*!< Reception Byte Count (low) */\r
+\r
+#define USB_COUNT4_RX_0_NUM_BLOCK_0 (0x00007C00U) /*!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */\r
+#define USB_COUNT4_RX_0_NUM_BLOCK_0_0 (0x00000400U) /*!< Bit 0 */\r
+#define USB_COUNT4_RX_0_NUM_BLOCK_0_1 (0x00000800U) /*!< Bit 1 */\r
+#define USB_COUNT4_RX_0_NUM_BLOCK_0_2 (0x00001000U) /*!< Bit 2 */\r
+#define USB_COUNT4_RX_0_NUM_BLOCK_0_3 (0x00002000U) /*!< Bit 3 */\r
+#define USB_COUNT4_RX_0_NUM_BLOCK_0_4 (0x00004000U) /*!< Bit 4 */\r
+\r
+#define USB_COUNT4_RX_0_BLSIZE_0 (0x00008000U) /*!< BLock SIZE (low) */\r
+\r
+/**************** Bit definition for USB_COUNT4_RX_1 register ***************/\r
+#define USB_COUNT4_RX_1_COUNT4_RX_1 (0x03FF0000U) /*!< Reception Byte Count (high) */\r
+\r
+#define USB_COUNT4_RX_1_NUM_BLOCK_1 (0x7C000000U) /*!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */\r
+#define USB_COUNT4_RX_1_NUM_BLOCK_1_0 (0x04000000U) /*!< Bit 0 */\r
+#define USB_COUNT4_RX_1_NUM_BLOCK_1_1 (0x08000000U) /*!< Bit 1 */\r
+#define USB_COUNT4_RX_1_NUM_BLOCK_1_2 (0x10000000U) /*!< Bit 2 */\r
+#define USB_COUNT4_RX_1_NUM_BLOCK_1_3 (0x20000000U) /*!< Bit 3 */\r
+#define USB_COUNT4_RX_1_NUM_BLOCK_1_4 (0x40000000U) /*!< Bit 4 */\r
+\r
+#define USB_COUNT4_RX_1_BLSIZE_1 (0x80000000U) /*!< BLock SIZE (high) */\r
+\r
+/**************** Bit definition for USB_COUNT5_RX_0 register ***************/\r
+#define USB_COUNT5_RX_0_COUNT5_RX_0 (0x000003FFU) /*!< Reception Byte Count (low) */\r
+\r
+#define USB_COUNT5_RX_0_NUM_BLOCK_0 (0x00007C00U) /*!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */\r
+#define USB_COUNT5_RX_0_NUM_BLOCK_0_0 (0x00000400U) /*!< Bit 0 */\r
+#define USB_COUNT5_RX_0_NUM_BLOCK_0_1 (0x00000800U) /*!< Bit 1 */\r
+#define USB_COUNT5_RX_0_NUM_BLOCK_0_2 (0x00001000U) /*!< Bit 2 */\r
+#define USB_COUNT5_RX_0_NUM_BLOCK_0_3 (0x00002000U) /*!< Bit 3 */\r
+#define USB_COUNT5_RX_0_NUM_BLOCK_0_4 (0x00004000U) /*!< Bit 4 */\r
+\r
+#define USB_COUNT5_RX_0_BLSIZE_0 (0x00008000U) /*!< BLock SIZE (low) */\r
+\r
+/**************** Bit definition for USB_COUNT5_RX_1 register ***************/\r
+#define USB_COUNT5_RX_1_COUNT5_RX_1 (0x03FF0000U) /*!< Reception Byte Count (high) */\r
+\r
+#define USB_COUNT5_RX_1_NUM_BLOCK_1 (0x7C000000U) /*!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */\r
+#define USB_COUNT5_RX_1_NUM_BLOCK_1_0 (0x04000000U) /*!< Bit 0 */\r
+#define USB_COUNT5_RX_1_NUM_BLOCK_1_1 (0x08000000U) /*!< Bit 1 */\r
+#define USB_COUNT5_RX_1_NUM_BLOCK_1_2 (0x10000000U) /*!< Bit 2 */\r
+#define USB_COUNT5_RX_1_NUM_BLOCK_1_3 (0x20000000U) /*!< Bit 3 */\r
+#define USB_COUNT5_RX_1_NUM_BLOCK_1_4 (0x40000000U) /*!< Bit 4 */\r
+\r
+#define USB_COUNT5_RX_1_BLSIZE_1 (0x80000000U) /*!< BLock SIZE (high) */\r
+\r
+/*************** Bit definition for USB_COUNT6_RX_0 register ***************/\r
+#define USB_COUNT6_RX_0_COUNT6_RX_0 (0x000003FFU) /*!< Reception Byte Count (low) */\r
+\r
+#define USB_COUNT6_RX_0_NUM_BLOCK_0 (0x00007C00U) /*!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */\r
+#define USB_COUNT6_RX_0_NUM_BLOCK_0_0 (0x00000400U) /*!< Bit 0 */\r
+#define USB_COUNT6_RX_0_NUM_BLOCK_0_1 (0x00000800U) /*!< Bit 1 */\r
+#define USB_COUNT6_RX_0_NUM_BLOCK_0_2 (0x00001000U) /*!< Bit 2 */\r
+#define USB_COUNT6_RX_0_NUM_BLOCK_0_3 (0x00002000U) /*!< Bit 3 */\r
+#define USB_COUNT6_RX_0_NUM_BLOCK_0_4 (0x00004000U) /*!< Bit 4 */\r
+\r
+#define USB_COUNT6_RX_0_BLSIZE_0 (0x00008000U) /*!< BLock SIZE (low) */\r
+\r
+/**************** Bit definition for USB_COUNT6_RX_1 register ***************/\r
+#define USB_COUNT6_RX_1_COUNT6_RX_1 (0x03FF0000U) /*!< Reception Byte Count (high) */\r
+\r
+#define USB_COUNT6_RX_1_NUM_BLOCK_1 (0x7C000000U) /*!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */\r
+#define USB_COUNT6_RX_1_NUM_BLOCK_1_0 (0x04000000U) /*!< Bit 0 */\r
+#define USB_COUNT6_RX_1_NUM_BLOCK_1_1 (0x08000000U) /*!< Bit 1 */\r
+#define USB_COUNT6_RX_1_NUM_BLOCK_1_2 (0x10000000U) /*!< Bit 2 */\r
+#define USB_COUNT6_RX_1_NUM_BLOCK_1_3 (0x20000000U) /*!< Bit 3 */\r
+#define USB_COUNT6_RX_1_NUM_BLOCK_1_4 (0x40000000U) /*!< Bit 4 */\r
+\r
+#define USB_COUNT6_RX_1_BLSIZE_1 (0x80000000U) /*!< BLock SIZE (high) */\r
+\r
+/*************** Bit definition for USB_COUNT7_RX_0 register ****************/\r
+#define USB_COUNT7_RX_0_COUNT7_RX_0 (0x000003FFU) /*!< Reception Byte Count (low) */\r
+\r
+#define USB_COUNT7_RX_0_NUM_BLOCK_0 (0x00007C00U) /*!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */\r
+#define USB_COUNT7_RX_0_NUM_BLOCK_0_0 (0x00000400U) /*!< Bit 0 */\r
+#define USB_COUNT7_RX_0_NUM_BLOCK_0_1 (0x00000800U) /*!< Bit 1 */\r
+#define USB_COUNT7_RX_0_NUM_BLOCK_0_2 (0x00001000U) /*!< Bit 2 */\r
+#define USB_COUNT7_RX_0_NUM_BLOCK_0_3 (0x00002000U) /*!< Bit 3 */\r
+#define USB_COUNT7_RX_0_NUM_BLOCK_0_4 (0x00004000U) /*!< Bit 4 */\r
+\r
+#define USB_COUNT7_RX_0_BLSIZE_0 (0x00008000U) /*!< BLock SIZE (low) */\r
+\r
+/*************** Bit definition for USB_COUNT7_RX_1 register ****************/\r
+#define USB_COUNT7_RX_1_COUNT7_RX_1 (0x03FF0000U) /*!< Reception Byte Count (high) */\r
+\r
+#define USB_COUNT7_RX_1_NUM_BLOCK_1 (0x7C000000U) /*!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */\r
+#define USB_COUNT7_RX_1_NUM_BLOCK_1_0 (0x04000000U) /*!< Bit 0 */\r
+#define USB_COUNT7_RX_1_NUM_BLOCK_1_1 (0x08000000U) /*!< Bit 1 */\r
+#define USB_COUNT7_RX_1_NUM_BLOCK_1_2 (0x10000000U) /*!< Bit 2 */\r
+#define USB_COUNT7_RX_1_NUM_BLOCK_1_3 (0x20000000U) /*!< Bit 3 */\r
+#define USB_COUNT7_RX_1_NUM_BLOCK_1_4 (0x40000000U) /*!< Bit 4 */\r
+\r
+#define USB_COUNT7_RX_1_BLSIZE_1 (0x80000000U) /*!< BLock SIZE (high) */\r
+\r
+/******************************************************************************/\r
+/* */\r
+/* Window WATCHDOG (WWDG) */\r
+/* */\r
+/******************************************************************************/\r
+\r
+/******************* Bit definition for WWDG_CR register ********************/\r
+#define WWDG_CR_T_Pos (0U) \r
+#define WWDG_CR_T_Msk (0x7FUL << WWDG_CR_T_Pos) /*!< 0x0000007F */\r
+#define WWDG_CR_T WWDG_CR_T_Msk /*!< T[6:0] bits (7-Bit counter (MSB to LSB)) */\r
+#define WWDG_CR_T_0 (0x01UL << WWDG_CR_T_Pos) /*!< 0x00000001 */\r
+#define WWDG_CR_T_1 (0x02UL << WWDG_CR_T_Pos) /*!< 0x00000002 */\r
+#define WWDG_CR_T_2 (0x04UL << WWDG_CR_T_Pos) /*!< 0x00000004 */\r
+#define WWDG_CR_T_3 (0x08UL << WWDG_CR_T_Pos) /*!< 0x00000008 */\r
+#define WWDG_CR_T_4 (0x10UL << WWDG_CR_T_Pos) /*!< 0x00000010 */\r
+#define WWDG_CR_T_5 (0x20UL << WWDG_CR_T_Pos) /*!< 0x00000020 */\r
+#define WWDG_CR_T_6 (0x40UL << WWDG_CR_T_Pos) /*!< 0x00000040 */\r
+\r
+/* Legacy defines */\r
+#define WWDG_CR_T0 WWDG_CR_T_0\r
+#define WWDG_CR_T1 WWDG_CR_T_1\r
+#define WWDG_CR_T2 WWDG_CR_T_2\r
+#define WWDG_CR_T3 WWDG_CR_T_3\r
+#define WWDG_CR_T4 WWDG_CR_T_4\r
+#define WWDG_CR_T5 WWDG_CR_T_5\r
+#define WWDG_CR_T6 WWDG_CR_T_6\r
+\r
+#define WWDG_CR_WDGA_Pos (7U) \r
+#define WWDG_CR_WDGA_Msk (0x1UL << WWDG_CR_WDGA_Pos) /*!< 0x00000080 */\r
+#define WWDG_CR_WDGA WWDG_CR_WDGA_Msk /*!< Activation bit */\r
+\r
+/******************* Bit definition for WWDG_CFR register *******************/\r
+#define WWDG_CFR_W_Pos (0U) \r
+#define WWDG_CFR_W_Msk (0x7FUL << WWDG_CFR_W_Pos) /*!< 0x0000007F */\r
+#define WWDG_CFR_W WWDG_CFR_W_Msk /*!< W[6:0] bits (7-bit window value) */\r
+#define WWDG_CFR_W_0 (0x01UL << WWDG_CFR_W_Pos) /*!< 0x00000001 */\r
+#define WWDG_CFR_W_1 (0x02UL << WWDG_CFR_W_Pos) /*!< 0x00000002 */\r
+#define WWDG_CFR_W_2 (0x04UL << WWDG_CFR_W_Pos) /*!< 0x00000004 */\r
+#define WWDG_CFR_W_3 (0x08UL << WWDG_CFR_W_Pos) /*!< 0x00000008 */\r
+#define WWDG_CFR_W_4 (0x10UL << WWDG_CFR_W_Pos) /*!< 0x00000010 */\r
+#define WWDG_CFR_W_5 (0x20UL << WWDG_CFR_W_Pos) /*!< 0x00000020 */\r
+#define WWDG_CFR_W_6 (0x40UL << WWDG_CFR_W_Pos) /*!< 0x00000040 */\r
+\r
+/* Legacy defines */\r
+#define WWDG_CFR_W0 WWDG_CFR_W_0\r
+#define WWDG_CFR_W1 WWDG_CFR_W_1\r
+#define WWDG_CFR_W2 WWDG_CFR_W_2\r
+#define WWDG_CFR_W3 WWDG_CFR_W_3\r
+#define WWDG_CFR_W4 WWDG_CFR_W_4\r
+#define WWDG_CFR_W5 WWDG_CFR_W_5\r
+#define WWDG_CFR_W6 WWDG_CFR_W_6\r
+\r
+#define WWDG_CFR_WDGTB_Pos (7U) \r
+#define WWDG_CFR_WDGTB_Msk (0x3UL << WWDG_CFR_WDGTB_Pos) /*!< 0x00000180 */\r
+#define WWDG_CFR_WDGTB WWDG_CFR_WDGTB_Msk /*!< WDGTB[1:0] bits (Timer Base) */\r
+#define WWDG_CFR_WDGTB_0 (0x1UL << WWDG_CFR_WDGTB_Pos) /*!< 0x00000080 */\r
+#define WWDG_CFR_WDGTB_1 (0x2UL << WWDG_CFR_WDGTB_Pos) /*!< 0x00000100 */\r
+\r
+/* Legacy defines */\r
+#define WWDG_CFR_WDGTB0 WWDG_CFR_WDGTB_0\r
+#define WWDG_CFR_WDGTB1 WWDG_CFR_WDGTB_1\r
+\r
+#define WWDG_CFR_EWI_Pos (9U) \r
+#define WWDG_CFR_EWI_Msk (0x1UL << WWDG_CFR_EWI_Pos) /*!< 0x00000200 */\r
+#define WWDG_CFR_EWI WWDG_CFR_EWI_Msk /*!< Early Wakeup Interrupt */\r
+\r
+/******************* Bit definition for WWDG_SR register ********************/\r
+#define WWDG_SR_EWIF_Pos (0U) \r
+#define WWDG_SR_EWIF_Msk (0x1UL << WWDG_SR_EWIF_Pos) /*!< 0x00000001 */\r
+#define WWDG_SR_EWIF WWDG_SR_EWIF_Msk /*!< Early Wakeup Interrupt Flag */\r
+\r
+/******************************************************************************/\r
+/* */\r
+/* SystemTick (SysTick) */\r
+/* */\r
+/******************************************************************************/\r
+\r
+/***************** Bit definition for SysTick_CTRL register *****************/\r
+#define SysTick_CTRL_ENABLE (0x00000001U) /*!< Counter enable */\r
+#define SysTick_CTRL_TICKINT (0x00000002U) /*!< Counting down to 0 pends the SysTick handler */\r
+#define SysTick_CTRL_CLKSOURCE (0x00000004U) /*!< Clock source */\r
+#define SysTick_CTRL_COUNTFLAG (0x00010000U) /*!< Count Flag */\r
+\r
+/***************** Bit definition for SysTick_LOAD register *****************/\r
+#define SysTick_LOAD_RELOAD (0x00FFFFFFU) /*!< Value to load into the SysTick Current Value Register when the counter reaches 0 */\r
+\r
+/***************** Bit definition for SysTick_VAL register ******************/\r
+#define SysTick_VAL_CURRENT (0x00FFFFFFU) /*!< Current value at the time the register is accessed */\r
+\r
+/***************** Bit definition for SysTick_CALIB register ****************/\r
+#define SysTick_CALIB_TENMS (0x00FFFFFFU) /*!< Reload value to use for 10ms timing */\r
+#define SysTick_CALIB_SKEW (0x40000000U) /*!< Calibration value is not exactly 10 ms */\r
+#define SysTick_CALIB_NOREF (0x80000000U) /*!< The reference clock is not provided */\r
+\r
+/******************************************************************************/\r
+/* */\r
+/* Nested Vectored Interrupt Controller (NVIC) */\r
+/* */\r
+/******************************************************************************/\r
+\r
+/****************** Bit definition for NVIC_ISER register *******************/\r
+#define NVIC_ISER_SETENA_Pos (0U) \r
+#define NVIC_ISER_SETENA_Msk (0xFFFFFFFFUL << NVIC_ISER_SETENA_Pos) /*!< 0xFFFFFFFF */\r
+#define NVIC_ISER_SETENA NVIC_ISER_SETENA_Msk /*!< Interrupt set enable bits */\r
+#define NVIC_ISER_SETENA_0 (0x00000001UL << NVIC_ISER_SETENA_Pos) /*!< 0x00000001 */\r
+#define NVIC_ISER_SETENA_1 (0x00000002UL << NVIC_ISER_SETENA_Pos) /*!< 0x00000002 */\r
+#define NVIC_ISER_SETENA_2 (0x00000004UL << NVIC_ISER_SETENA_Pos) /*!< 0x00000004 */\r
+#define NVIC_ISER_SETENA_3 (0x00000008UL << NVIC_ISER_SETENA_Pos) /*!< 0x00000008 */\r
+#define NVIC_ISER_SETENA_4 (0x00000010UL << NVIC_ISER_SETENA_Pos) /*!< 0x00000010 */\r
+#define NVIC_ISER_SETENA_5 (0x00000020UL << NVIC_ISER_SETENA_Pos) /*!< 0x00000020 */\r
+#define NVIC_ISER_SETENA_6 (0x00000040UL << NVIC_ISER_SETENA_Pos) /*!< 0x00000040 */\r
+#define NVIC_ISER_SETENA_7 (0x00000080UL << NVIC_ISER_SETENA_Pos) /*!< 0x00000080 */\r
+#define NVIC_ISER_SETENA_8 (0x00000100UL << NVIC_ISER_SETENA_Pos) /*!< 0x00000100 */\r
+#define NVIC_ISER_SETENA_9 (0x00000200UL << NVIC_ISER_SETENA_Pos) /*!< 0x00000200 */\r
+#define NVIC_ISER_SETENA_10 (0x00000400UL << NVIC_ISER_SETENA_Pos) /*!< 0x00000400 */\r
+#define NVIC_ISER_SETENA_11 (0x00000800UL << NVIC_ISER_SETENA_Pos) /*!< 0x00000800 */\r
+#define NVIC_ISER_SETENA_12 (0x00001000UL << NVIC_ISER_SETENA_Pos) /*!< 0x00001000 */\r
+#define NVIC_ISER_SETENA_13 (0x00002000UL << NVIC_ISER_SETENA_Pos) /*!< 0x00002000 */\r
+#define NVIC_ISER_SETENA_14 (0x00004000UL << NVIC_ISER_SETENA_Pos) /*!< 0x00004000 */\r
+#define NVIC_ISER_SETENA_15 (0x00008000UL << NVIC_ISER_SETENA_Pos) /*!< 0x00008000 */\r
+#define NVIC_ISER_SETENA_16 (0x00010000UL << NVIC_ISER_SETENA_Pos) /*!< 0x00010000 */\r
+#define NVIC_ISER_SETENA_17 (0x00020000UL << NVIC_ISER_SETENA_Pos) /*!< 0x00020000 */\r
+#define NVIC_ISER_SETENA_18 (0x00040000UL << NVIC_ISER_SETENA_Pos) /*!< 0x00040000 */\r
+#define NVIC_ISER_SETENA_19 (0x00080000UL << NVIC_ISER_SETENA_Pos) /*!< 0x00080000 */\r
+#define NVIC_ISER_SETENA_20 (0x00100000UL << NVIC_ISER_SETENA_Pos) /*!< 0x00100000 */\r
+#define NVIC_ISER_SETENA_21 (0x00200000UL << NVIC_ISER_SETENA_Pos) /*!< 0x00200000 */\r
+#define NVIC_ISER_SETENA_22 (0x00400000UL << NVIC_ISER_SETENA_Pos) /*!< 0x00400000 */\r
+#define NVIC_ISER_SETENA_23 (0x00800000UL << NVIC_ISER_SETENA_Pos) /*!< 0x00800000 */\r
+#define NVIC_ISER_SETENA_24 (0x01000000UL << NVIC_ISER_SETENA_Pos) /*!< 0x01000000 */\r
+#define NVIC_ISER_SETENA_25 (0x02000000UL << NVIC_ISER_SETENA_Pos) /*!< 0x02000000 */\r
+#define NVIC_ISER_SETENA_26 (0x04000000UL << NVIC_ISER_SETENA_Pos) /*!< 0x04000000 */\r
+#define NVIC_ISER_SETENA_27 (0x08000000UL << NVIC_ISER_SETENA_Pos) /*!< 0x08000000 */\r
+#define NVIC_ISER_SETENA_28 (0x10000000UL << NVIC_ISER_SETENA_Pos) /*!< 0x10000000 */\r
+#define NVIC_ISER_SETENA_29 (0x20000000UL << NVIC_ISER_SETENA_Pos) /*!< 0x20000000 */\r
+#define NVIC_ISER_SETENA_30 (0x40000000UL << NVIC_ISER_SETENA_Pos) /*!< 0x40000000 */\r
+#define NVIC_ISER_SETENA_31 (0x80000000UL << NVIC_ISER_SETENA_Pos) /*!< 0x80000000 */\r
+\r
+/****************** Bit definition for NVIC_ICER register *******************/\r
+#define NVIC_ICER_CLRENA_Pos (0U) \r
+#define NVIC_ICER_CLRENA_Msk (0xFFFFFFFFUL << NVIC_ICER_CLRENA_Pos) /*!< 0xFFFFFFFF */\r
+#define NVIC_ICER_CLRENA NVIC_ICER_CLRENA_Msk /*!< Interrupt clear-enable bits */\r
+#define NVIC_ICER_CLRENA_0 (0x00000001UL << NVIC_ICER_CLRENA_Pos) /*!< 0x00000001 */\r
+#define NVIC_ICER_CLRENA_1 (0x00000002UL << NVIC_ICER_CLRENA_Pos) /*!< 0x00000002 */\r
+#define NVIC_ICER_CLRENA_2 (0x00000004UL << NVIC_ICER_CLRENA_Pos) /*!< 0x00000004 */\r
+#define NVIC_ICER_CLRENA_3 (0x00000008UL << NVIC_ICER_CLRENA_Pos) /*!< 0x00000008 */\r
+#define NVIC_ICER_CLRENA_4 (0x00000010UL << NVIC_ICER_CLRENA_Pos) /*!< 0x00000010 */\r
+#define NVIC_ICER_CLRENA_5 (0x00000020UL << NVIC_ICER_CLRENA_Pos) /*!< 0x00000020 */\r
+#define NVIC_ICER_CLRENA_6 (0x00000040UL << NVIC_ICER_CLRENA_Pos) /*!< 0x00000040 */\r
+#define NVIC_ICER_CLRENA_7 (0x00000080UL << NVIC_ICER_CLRENA_Pos) /*!< 0x00000080 */\r
+#define NVIC_ICER_CLRENA_8 (0x00000100UL << NVIC_ICER_CLRENA_Pos) /*!< 0x00000100 */\r
+#define NVIC_ICER_CLRENA_9 (0x00000200UL << NVIC_ICER_CLRENA_Pos) /*!< 0x00000200 */\r
+#define NVIC_ICER_CLRENA_10 (0x00000400UL << NVIC_ICER_CLRENA_Pos) /*!< 0x00000400 */\r
+#define NVIC_ICER_CLRENA_11 (0x00000800UL << NVIC_ICER_CLRENA_Pos) /*!< 0x00000800 */\r
+#define NVIC_ICER_CLRENA_12 (0x00001000UL << NVIC_ICER_CLRENA_Pos) /*!< 0x00001000 */\r
+#define NVIC_ICER_CLRENA_13 (0x00002000UL << NVIC_ICER_CLRENA_Pos) /*!< 0x00002000 */\r
+#define NVIC_ICER_CLRENA_14 (0x00004000UL << NVIC_ICER_CLRENA_Pos) /*!< 0x00004000 */\r
+#define NVIC_ICER_CLRENA_15 (0x00008000UL << NVIC_ICER_CLRENA_Pos) /*!< 0x00008000 */\r
+#define NVIC_ICER_CLRENA_16 (0x00010000UL << NVIC_ICER_CLRENA_Pos) /*!< 0x00010000 */\r
+#define NVIC_ICER_CLRENA_17 (0x00020000UL << NVIC_ICER_CLRENA_Pos) /*!< 0x00020000 */\r
+#define NVIC_ICER_CLRENA_18 (0x00040000UL << NVIC_ICER_CLRENA_Pos) /*!< 0x00040000 */\r
+#define NVIC_ICER_CLRENA_19 (0x00080000UL << NVIC_ICER_CLRENA_Pos) /*!< 0x00080000 */\r
+#define NVIC_ICER_CLRENA_20 (0x00100000UL << NVIC_ICER_CLRENA_Pos) /*!< 0x00100000 */\r
+#define NVIC_ICER_CLRENA_21 (0x00200000UL << NVIC_ICER_CLRENA_Pos) /*!< 0x00200000 */\r
+#define NVIC_ICER_CLRENA_22 (0x00400000UL << NVIC_ICER_CLRENA_Pos) /*!< 0x00400000 */\r
+#define NVIC_ICER_CLRENA_23 (0x00800000UL << NVIC_ICER_CLRENA_Pos) /*!< 0x00800000 */\r
+#define NVIC_ICER_CLRENA_24 (0x01000000UL << NVIC_ICER_CLRENA_Pos) /*!< 0x01000000 */\r
+#define NVIC_ICER_CLRENA_25 (0x02000000UL << NVIC_ICER_CLRENA_Pos) /*!< 0x02000000 */\r
+#define NVIC_ICER_CLRENA_26 (0x04000000UL << NVIC_ICER_CLRENA_Pos) /*!< 0x04000000 */\r
+#define NVIC_ICER_CLRENA_27 (0x08000000UL << NVIC_ICER_CLRENA_Pos) /*!< 0x08000000 */\r
+#define NVIC_ICER_CLRENA_28 (0x10000000UL << NVIC_ICER_CLRENA_Pos) /*!< 0x10000000 */\r
+#define NVIC_ICER_CLRENA_29 (0x20000000UL << NVIC_ICER_CLRENA_Pos) /*!< 0x20000000 */\r
+#define NVIC_ICER_CLRENA_30 (0x40000000UL << NVIC_ICER_CLRENA_Pos) /*!< 0x40000000 */\r
+#define NVIC_ICER_CLRENA_31 (0x80000000UL << NVIC_ICER_CLRENA_Pos) /*!< 0x80000000 */\r
+\r
+/****************** Bit definition for NVIC_ISPR register *******************/\r
+#define NVIC_ISPR_SETPEND_Pos (0U) \r
+#define NVIC_ISPR_SETPEND_Msk (0xFFFFFFFFUL << NVIC_ISPR_SETPEND_Pos) /*!< 0xFFFFFFFF */\r
+#define NVIC_ISPR_SETPEND NVIC_ISPR_SETPEND_Msk /*!< Interrupt set-pending bits */\r
+#define NVIC_ISPR_SETPEND_0 (0x00000001UL << NVIC_ISPR_SETPEND_Pos) /*!< 0x00000001 */\r
+#define NVIC_ISPR_SETPEND_1 (0x00000002UL << NVIC_ISPR_SETPEND_Pos) /*!< 0x00000002 */\r
+#define NVIC_ISPR_SETPEND_2 (0x00000004UL << NVIC_ISPR_SETPEND_Pos) /*!< 0x00000004 */\r
+#define NVIC_ISPR_SETPEND_3 (0x00000008UL << NVIC_ISPR_SETPEND_Pos) /*!< 0x00000008 */\r
+#define NVIC_ISPR_SETPEND_4 (0x00000010UL << NVIC_ISPR_SETPEND_Pos) /*!< 0x00000010 */\r
+#define NVIC_ISPR_SETPEND_5 (0x00000020UL << NVIC_ISPR_SETPEND_Pos) /*!< 0x00000020 */\r
+#define NVIC_ISPR_SETPEND_6 (0x00000040UL << NVIC_ISPR_SETPEND_Pos) /*!< 0x00000040 */\r
+#define NVIC_ISPR_SETPEND_7 (0x00000080UL << NVIC_ISPR_SETPEND_Pos) /*!< 0x00000080 */\r
+#define NVIC_ISPR_SETPEND_8 (0x00000100UL << NVIC_ISPR_SETPEND_Pos) /*!< 0x00000100 */\r
+#define NVIC_ISPR_SETPEND_9 (0x00000200UL << NVIC_ISPR_SETPEND_Pos) /*!< 0x00000200 */\r
+#define NVIC_ISPR_SETPEND_10 (0x00000400UL << NVIC_ISPR_SETPEND_Pos) /*!< 0x00000400 */\r
+#define NVIC_ISPR_SETPEND_11 (0x00000800UL << NVIC_ISPR_SETPEND_Pos) /*!< 0x00000800 */\r
+#define NVIC_ISPR_SETPEND_12 (0x00001000UL << NVIC_ISPR_SETPEND_Pos) /*!< 0x00001000 */\r
+#define NVIC_ISPR_SETPEND_13 (0x00002000UL << NVIC_ISPR_SETPEND_Pos) /*!< 0x00002000 */\r
+#define NVIC_ISPR_SETPEND_14 (0x00004000UL << NVIC_ISPR_SETPEND_Pos) /*!< 0x00004000 */\r
+#define NVIC_ISPR_SETPEND_15 (0x00008000UL << NVIC_ISPR_SETPEND_Pos) /*!< 0x00008000 */\r
+#define NVIC_ISPR_SETPEND_16 (0x00010000UL << NVIC_ISPR_SETPEND_Pos) /*!< 0x00010000 */\r
+#define NVIC_ISPR_SETPEND_17 (0x00020000UL << NVIC_ISPR_SETPEND_Pos) /*!< 0x00020000 */\r
+#define NVIC_ISPR_SETPEND_18 (0x00040000UL << NVIC_ISPR_SETPEND_Pos) /*!< 0x00040000 */\r
+#define NVIC_ISPR_SETPEND_19 (0x00080000UL << NVIC_ISPR_SETPEND_Pos) /*!< 0x00080000 */\r
+#define NVIC_ISPR_SETPEND_20 (0x00100000UL << NVIC_ISPR_SETPEND_Pos) /*!< 0x00100000 */\r
+#define NVIC_ISPR_SETPEND_21 (0x00200000UL << NVIC_ISPR_SETPEND_Pos) /*!< 0x00200000 */\r
+#define NVIC_ISPR_SETPEND_22 (0x00400000UL << NVIC_ISPR_SETPEND_Pos) /*!< 0x00400000 */\r
+#define NVIC_ISPR_SETPEND_23 (0x00800000UL << NVIC_ISPR_SETPEND_Pos) /*!< 0x00800000 */\r
+#define NVIC_ISPR_SETPEND_24 (0x01000000UL << NVIC_ISPR_SETPEND_Pos) /*!< 0x01000000 */\r
+#define NVIC_ISPR_SETPEND_25 (0x02000000UL << NVIC_ISPR_SETPEND_Pos) /*!< 0x02000000 */\r
+#define NVIC_ISPR_SETPEND_26 (0x04000000UL << NVIC_ISPR_SETPEND_Pos) /*!< 0x04000000 */\r
+#define NVIC_ISPR_SETPEND_27 (0x08000000UL << NVIC_ISPR_SETPEND_Pos) /*!< 0x08000000 */\r
+#define NVIC_ISPR_SETPEND_28 (0x10000000UL << NVIC_ISPR_SETPEND_Pos) /*!< 0x10000000 */\r
+#define NVIC_ISPR_SETPEND_29 (0x20000000UL << NVIC_ISPR_SETPEND_Pos) /*!< 0x20000000 */\r
+#define NVIC_ISPR_SETPEND_30 (0x40000000UL << NVIC_ISPR_SETPEND_Pos) /*!< 0x40000000 */\r
+#define NVIC_ISPR_SETPEND_31 (0x80000000UL << NVIC_ISPR_SETPEND_Pos) /*!< 0x80000000 */\r
+\r
+/****************** Bit definition for NVIC_ICPR register *******************/\r
+#define NVIC_ICPR_CLRPEND_Pos (0U) \r
+#define NVIC_ICPR_CLRPEND_Msk (0xFFFFFFFFUL << NVIC_ICPR_CLRPEND_Pos) /*!< 0xFFFFFFFF */\r
+#define NVIC_ICPR_CLRPEND NVIC_ICPR_CLRPEND_Msk /*!< Interrupt clear-pending bits */\r
+#define NVIC_ICPR_CLRPEND_0 (0x00000001UL << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00000001 */\r
+#define NVIC_ICPR_CLRPEND_1 (0x00000002UL << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00000002 */\r
+#define NVIC_ICPR_CLRPEND_2 (0x00000004UL << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00000004 */\r
+#define NVIC_ICPR_CLRPEND_3 (0x00000008UL << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00000008 */\r
+#define NVIC_ICPR_CLRPEND_4 (0x00000010UL << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00000010 */\r
+#define NVIC_ICPR_CLRPEND_5 (0x00000020UL << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00000020 */\r
+#define NVIC_ICPR_CLRPEND_6 (0x00000040UL << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00000040 */\r
+#define NVIC_ICPR_CLRPEND_7 (0x00000080UL << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00000080 */\r
+#define NVIC_ICPR_CLRPEND_8 (0x00000100UL << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00000100 */\r
+#define NVIC_ICPR_CLRPEND_9 (0x00000200UL << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00000200 */\r
+#define NVIC_ICPR_CLRPEND_10 (0x00000400UL << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00000400 */\r
+#define NVIC_ICPR_CLRPEND_11 (0x00000800UL << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00000800 */\r
+#define NVIC_ICPR_CLRPEND_12 (0x00001000UL << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00001000 */\r
+#define NVIC_ICPR_CLRPEND_13 (0x00002000UL << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00002000 */\r
+#define NVIC_ICPR_CLRPEND_14 (0x00004000UL << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00004000 */\r
+#define NVIC_ICPR_CLRPEND_15 (0x00008000UL << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00008000 */\r
+#define NVIC_ICPR_CLRPEND_16 (0x00010000UL << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00010000 */\r
+#define NVIC_ICPR_CLRPEND_17 (0x00020000UL << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00020000 */\r
+#define NVIC_ICPR_CLRPEND_18 (0x00040000UL << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00040000 */\r
+#define NVIC_ICPR_CLRPEND_19 (0x00080000UL << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00080000 */\r
+#define NVIC_ICPR_CLRPEND_20 (0x00100000UL << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00100000 */\r
+#define NVIC_ICPR_CLRPEND_21 (0x00200000UL << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00200000 */\r
+#define NVIC_ICPR_CLRPEND_22 (0x00400000UL << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00400000 */\r
+#define NVIC_ICPR_CLRPEND_23 (0x00800000UL << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00800000 */\r
+#define NVIC_ICPR_CLRPEND_24 (0x01000000UL << NVIC_ICPR_CLRPEND_Pos) /*!< 0x01000000 */\r
+#define NVIC_ICPR_CLRPEND_25 (0x02000000UL << NVIC_ICPR_CLRPEND_Pos) /*!< 0x02000000 */\r
+#define NVIC_ICPR_CLRPEND_26 (0x04000000UL << NVIC_ICPR_CLRPEND_Pos) /*!< 0x04000000 */\r
+#define NVIC_ICPR_CLRPEND_27 (0x08000000UL << NVIC_ICPR_CLRPEND_Pos) /*!< 0x08000000 */\r
+#define NVIC_ICPR_CLRPEND_28 (0x10000000UL << NVIC_ICPR_CLRPEND_Pos) /*!< 0x10000000 */\r
+#define NVIC_ICPR_CLRPEND_29 (0x20000000UL << NVIC_ICPR_CLRPEND_Pos) /*!< 0x20000000 */\r
+#define NVIC_ICPR_CLRPEND_30 (0x40000000UL << NVIC_ICPR_CLRPEND_Pos) /*!< 0x40000000 */\r
+#define NVIC_ICPR_CLRPEND_31 (0x80000000UL << NVIC_ICPR_CLRPEND_Pos) /*!< 0x80000000 */\r
+\r
+/****************** Bit definition for NVIC_IABR register *******************/\r
+#define NVIC_IABR_ACTIVE_Pos (0U) \r
+#define NVIC_IABR_ACTIVE_Msk (0xFFFFFFFFUL << NVIC_IABR_ACTIVE_Pos) /*!< 0xFFFFFFFF */\r
+#define NVIC_IABR_ACTIVE NVIC_IABR_ACTIVE_Msk /*!< Interrupt active flags */\r
+#define NVIC_IABR_ACTIVE_0 (0x00000001UL << NVIC_IABR_ACTIVE_Pos) /*!< 0x00000001 */\r
+#define NVIC_IABR_ACTIVE_1 (0x00000002UL << NVIC_IABR_ACTIVE_Pos) /*!< 0x00000002 */\r
+#define NVIC_IABR_ACTIVE_2 (0x00000004UL << NVIC_IABR_ACTIVE_Pos) /*!< 0x00000004 */\r
+#define NVIC_IABR_ACTIVE_3 (0x00000008UL << NVIC_IABR_ACTIVE_Pos) /*!< 0x00000008 */\r
+#define NVIC_IABR_ACTIVE_4 (0x00000010UL << NVIC_IABR_ACTIVE_Pos) /*!< 0x00000010 */\r
+#define NVIC_IABR_ACTIVE_5 (0x00000020UL << NVIC_IABR_ACTIVE_Pos) /*!< 0x00000020 */\r
+#define NVIC_IABR_ACTIVE_6 (0x00000040UL << NVIC_IABR_ACTIVE_Pos) /*!< 0x00000040 */\r
+#define NVIC_IABR_ACTIVE_7 (0x00000080UL << NVIC_IABR_ACTIVE_Pos) /*!< 0x00000080 */\r
+#define NVIC_IABR_ACTIVE_8 (0x00000100UL << NVIC_IABR_ACTIVE_Pos) /*!< 0x00000100 */\r
+#define NVIC_IABR_ACTIVE_9 (0x00000200UL << NVIC_IABR_ACTIVE_Pos) /*!< 0x00000200 */\r
+#define NVIC_IABR_ACTIVE_10 (0x00000400UL << NVIC_IABR_ACTIVE_Pos) /*!< 0x00000400 */\r
+#define NVIC_IABR_ACTIVE_11 (0x00000800UL << NVIC_IABR_ACTIVE_Pos) /*!< 0x00000800 */\r
+#define NVIC_IABR_ACTIVE_12 (0x00001000UL << NVIC_IABR_ACTIVE_Pos) /*!< 0x00001000 */\r
+#define NVIC_IABR_ACTIVE_13 (0x00002000UL << NVIC_IABR_ACTIVE_Pos) /*!< 0x00002000 */\r
+#define NVIC_IABR_ACTIVE_14 (0x00004000UL << NVIC_IABR_ACTIVE_Pos) /*!< 0x00004000 */\r
+#define NVIC_IABR_ACTIVE_15 (0x00008000UL << NVIC_IABR_ACTIVE_Pos) /*!< 0x00008000 */\r
+#define NVIC_IABR_ACTIVE_16 (0x00010000UL << NVIC_IABR_ACTIVE_Pos) /*!< 0x00010000 */\r
+#define NVIC_IABR_ACTIVE_17 (0x00020000UL << NVIC_IABR_ACTIVE_Pos) /*!< 0x00020000 */\r
+#define NVIC_IABR_ACTIVE_18 (0x00040000UL << NVIC_IABR_ACTIVE_Pos) /*!< 0x00040000 */\r
+#define NVIC_IABR_ACTIVE_19 (0x00080000UL << NVIC_IABR_ACTIVE_Pos) /*!< 0x00080000 */\r
+#define NVIC_IABR_ACTIVE_20 (0x00100000UL << NVIC_IABR_ACTIVE_Pos) /*!< 0x00100000 */\r
+#define NVIC_IABR_ACTIVE_21 (0x00200000UL << NVIC_IABR_ACTIVE_Pos) /*!< 0x00200000 */\r
+#define NVIC_IABR_ACTIVE_22 (0x00400000UL << NVIC_IABR_ACTIVE_Pos) /*!< 0x00400000 */\r
+#define NVIC_IABR_ACTIVE_23 (0x00800000UL << NVIC_IABR_ACTIVE_Pos) /*!< 0x00800000 */\r
+#define NVIC_IABR_ACTIVE_24 (0x01000000UL << NVIC_IABR_ACTIVE_Pos) /*!< 0x01000000 */\r
+#define NVIC_IABR_ACTIVE_25 (0x02000000UL << NVIC_IABR_ACTIVE_Pos) /*!< 0x02000000 */\r
+#define NVIC_IABR_ACTIVE_26 (0x04000000UL << NVIC_IABR_ACTIVE_Pos) /*!< 0x04000000 */\r
+#define NVIC_IABR_ACTIVE_27 (0x08000000UL << NVIC_IABR_ACTIVE_Pos) /*!< 0x08000000 */\r
+#define NVIC_IABR_ACTIVE_28 (0x10000000UL << NVIC_IABR_ACTIVE_Pos) /*!< 0x10000000 */\r
+#define NVIC_IABR_ACTIVE_29 (0x20000000UL << NVIC_IABR_ACTIVE_Pos) /*!< 0x20000000 */\r
+#define NVIC_IABR_ACTIVE_30 (0x40000000UL << NVIC_IABR_ACTIVE_Pos) /*!< 0x40000000 */\r
+#define NVIC_IABR_ACTIVE_31 (0x80000000UL << NVIC_IABR_ACTIVE_Pos) /*!< 0x80000000 */\r
+\r
+/****************** Bit definition for NVIC_PRI0 register *******************/\r
+#define NVIC_IPR0_PRI_0 (0x000000FFU) /*!< Priority of interrupt 0 */\r
+#define NVIC_IPR0_PRI_1 (0x0000FF00U) /*!< Priority of interrupt 1 */\r
+#define NVIC_IPR0_PRI_2 (0x00FF0000U) /*!< Priority of interrupt 2 */\r
+#define NVIC_IPR0_PRI_3 (0xFF000000U) /*!< Priority of interrupt 3 */\r
+\r
+/****************** Bit definition for NVIC_PRI1 register *******************/\r
+#define NVIC_IPR1_PRI_4 (0x000000FFU) /*!< Priority of interrupt 4 */\r
+#define NVIC_IPR1_PRI_5 (0x0000FF00U) /*!< Priority of interrupt 5 */\r
+#define NVIC_IPR1_PRI_6 (0x00FF0000U) /*!< Priority of interrupt 6 */\r
+#define NVIC_IPR1_PRI_7 (0xFF000000U) /*!< Priority of interrupt 7 */\r
+\r
+/****************** Bit definition for NVIC_PRI2 register *******************/\r
+#define NVIC_IPR2_PRI_8 (0x000000FFU) /*!< Priority of interrupt 8 */\r
+#define NVIC_IPR2_PRI_9 (0x0000FF00U) /*!< Priority of interrupt 9 */\r
+#define NVIC_IPR2_PRI_10 (0x00FF0000U) /*!< Priority of interrupt 10 */\r
+#define NVIC_IPR2_PRI_11 (0xFF000000U) /*!< Priority of interrupt 11 */\r
+\r
+/****************** Bit definition for NVIC_PRI3 register *******************/\r
+#define NVIC_IPR3_PRI_12 (0x000000FFU) /*!< Priority of interrupt 12 */\r
+#define NVIC_IPR3_PRI_13 (0x0000FF00U) /*!< Priority of interrupt 13 */\r
+#define NVIC_IPR3_PRI_14 (0x00FF0000U) /*!< Priority of interrupt 14 */\r
+#define NVIC_IPR3_PRI_15 (0xFF000000U) /*!< Priority of interrupt 15 */\r
+\r
+/****************** Bit definition for NVIC_PRI4 register *******************/\r
+#define NVIC_IPR4_PRI_16 (0x000000FFU) /*!< Priority of interrupt 16 */\r
+#define NVIC_IPR4_PRI_17 (0x0000FF00U) /*!< Priority of interrupt 17 */\r
+#define NVIC_IPR4_PRI_18 (0x00FF0000U) /*!< Priority of interrupt 18 */\r
+#define NVIC_IPR4_PRI_19 (0xFF000000U) /*!< Priority of interrupt 19 */\r
+\r
+/****************** Bit definition for NVIC_PRI5 register *******************/\r
+#define NVIC_IPR5_PRI_20 (0x000000FFU) /*!< Priority of interrupt 20 */\r
+#define NVIC_IPR5_PRI_21 (0x0000FF00U) /*!< Priority of interrupt 21 */\r
+#define NVIC_IPR5_PRI_22 (0x00FF0000U) /*!< Priority of interrupt 22 */\r
+#define NVIC_IPR5_PRI_23 (0xFF000000U) /*!< Priority of interrupt 23 */\r
+\r
+/****************** Bit definition for NVIC_PRI6 register *******************/\r
+#define NVIC_IPR6_PRI_24 (0x000000FFU) /*!< Priority of interrupt 24 */\r
+#define NVIC_IPR6_PRI_25 (0x0000FF00U) /*!< Priority of interrupt 25 */\r
+#define NVIC_IPR6_PRI_26 (0x00FF0000U) /*!< Priority of interrupt 26 */\r
+#define NVIC_IPR6_PRI_27 (0xFF000000U) /*!< Priority of interrupt 27 */\r
+\r
+/****************** Bit definition for NVIC_PRI7 register *******************/\r
+#define NVIC_IPR7_PRI_28 (0x000000FFU) /*!< Priority of interrupt 28 */\r
+#define NVIC_IPR7_PRI_29 (0x0000FF00U) /*!< Priority of interrupt 29 */\r
+#define NVIC_IPR7_PRI_30 (0x00FF0000U) /*!< Priority of interrupt 30 */\r
+#define NVIC_IPR7_PRI_31 (0xFF000000U) /*!< Priority of interrupt 31 */\r
+\r
+/****************** Bit definition for SCB_CPUID register *******************/\r
+#define SCB_CPUID_REVISION (0x0000000FU) /*!< Implementation defined revision number */\r
+#define SCB_CPUID_PARTNO (0x0000FFF0U) /*!< Number of processor within serie */\r
+#define SCB_CPUID_Constant (0x000F0000U) /*!< Reads as 0x0F */\r
+#define SCB_CPUID_VARIANT (0x00F00000U) /*!< Implementation defined variant number */\r
+#define SCB_CPUID_IMPLEMENTER (0xFF000000U) /*!< Implementer code. ARM is 0x41 */\r
+\r
+/******************* Bit definition for SCB_ICSR register *******************/\r
+#define SCB_ICSR_VECTACTIVE (0x000001FFU) /*!< Active ISR number field */\r
+#define SCB_ICSR_RETTOBASE (0x00000800U) /*!< All active exceptions minus the IPSR_current_exception yields the empty set */\r
+#define SCB_ICSR_VECTPENDING (0x003FF000U) /*!< Pending ISR number field */\r
+#define SCB_ICSR_ISRPENDING (0x00400000U) /*!< Interrupt pending flag */\r
+#define SCB_ICSR_ISRPREEMPT (0x00800000U) /*!< It indicates that a pending interrupt becomes active in the next running cycle */\r
+#define SCB_ICSR_PENDSTCLR (0x02000000U) /*!< Clear pending SysTick bit */\r
+#define SCB_ICSR_PENDSTSET (0x04000000U) /*!< Set pending SysTick bit */\r
+#define SCB_ICSR_PENDSVCLR (0x08000000U) /*!< Clear pending pendSV bit */\r
+#define SCB_ICSR_PENDSVSET (0x10000000U) /*!< Set pending pendSV bit */\r
+#define SCB_ICSR_NMIPENDSET (0x80000000U) /*!< Set pending NMI bit */\r
+\r
+/******************* Bit definition for SCB_VTOR register *******************/\r
+#define SCB_VTOR_TBLOFF (0x1FFFFF80U) /*!< Vector table base offset field */\r
+#define SCB_VTOR_TBLBASE (0x20000000U) /*!< Table base in code(0) or RAM(1) */\r
+\r
+/*!<***************** Bit definition for SCB_AIRCR register *******************/\r
+#define SCB_AIRCR_VECTRESET (0x00000001U) /*!< System Reset bit */\r
+#define SCB_AIRCR_VECTCLRACTIVE (0x00000002U) /*!< Clear active vector bit */\r
+#define SCB_AIRCR_SYSRESETREQ (0x00000004U) /*!< Requests chip control logic to generate a reset */\r
+\r
+#define SCB_AIRCR_PRIGROUP (0x00000700U) /*!< PRIGROUP[2:0] bits (Priority group) */\r
+#define SCB_AIRCR_PRIGROUP_0 (0x00000100U) /*!< Bit 0 */\r
+#define SCB_AIRCR_PRIGROUP_1 (0x00000200U) /*!< Bit 1 */\r
+#define SCB_AIRCR_PRIGROUP_2 (0x00000400U) /*!< Bit 2 */\r
+\r
+/* prority group configuration */\r
+#define SCB_AIRCR_PRIGROUP0 (0x00000000U) /*!< Priority group=0 (7 bits of pre-emption priority, 1 bit of subpriority) */\r
+#define SCB_AIRCR_PRIGROUP1 (0x00000100U) /*!< Priority group=1 (6 bits of pre-emption priority, 2 bits of subpriority) */\r
+#define SCB_AIRCR_PRIGROUP2 (0x00000200U) /*!< Priority group=2 (5 bits of pre-emption priority, 3 bits of subpriority) */\r
+#define SCB_AIRCR_PRIGROUP3 (0x00000300U) /*!< Priority group=3 (4 bits of pre-emption priority, 4 bits of subpriority) */\r
+#define SCB_AIRCR_PRIGROUP4 (0x00000400U) /*!< Priority group=4 (3 bits of pre-emption priority, 5 bits of subpriority) */\r
+#define SCB_AIRCR_PRIGROUP5 (0x00000500U) /*!< Priority group=5 (2 bits of pre-emption priority, 6 bits of subpriority) */\r
+#define SCB_AIRCR_PRIGROUP6 (0x00000600U) /*!< Priority group=6 (1 bit of pre-emption priority, 7 bits of subpriority) */\r
+#define SCB_AIRCR_PRIGROUP7 (0x00000700U) /*!< Priority group=7 (no pre-emption priority, 8 bits of subpriority) */\r
+\r
+#define SCB_AIRCR_ENDIANESS (0x00008000U) /*!< Data endianness bit */\r
+#define SCB_AIRCR_VECTKEY (0xFFFF0000U) /*!< Register key (VECTKEY) - Reads as 0xFA05 (VECTKEYSTAT) */\r
+\r
+/******************* Bit definition for SCB_SCR register ********************/\r
+#define SCB_SCR_SLEEPONEXIT (0x00000002U) /*!< Sleep on exit bit */\r
+#define SCB_SCR_SLEEPDEEP (0x00000004U) /*!< Sleep deep bit */\r
+#define SCB_SCR_SEVONPEND (0x00000010U) /*!< Wake up from WFE */\r
+\r
+/******************** Bit definition for SCB_CCR register *******************/\r
+#define SCB_CCR_NONBASETHRDENA (0x00000001U) /*!< Thread mode can be entered from any level in Handler mode by controlled return value */\r
+#define SCB_CCR_USERSETMPEND (0x00000002U) /*!< Enables user code to write the Software Trigger Interrupt register to trigger (pend) a Main exception */\r
+#define SCB_CCR_UNALIGN_TRP (0x00000008U) /*!< Trap for unaligned access */\r
+#define SCB_CCR_DIV_0_TRP (0x00000010U) /*!< Trap on Divide by 0 */\r
+#define SCB_CCR_BFHFNMIGN (0x00000100U) /*!< Handlers running at priority -1 and -2 */\r
+#define SCB_CCR_STKALIGN (0x00000200U) /*!< On exception entry, the SP used prior to the exception is adjusted to be 8-byte aligned */\r
+\r
+/******************* Bit definition for SCB_SHPR register ********************/\r
+#define SCB_SHPR_PRI_N_Pos (0U) \r
+#define SCB_SHPR_PRI_N_Msk (0xFFUL << SCB_SHPR_PRI_N_Pos) /*!< 0x000000FF */\r
+#define SCB_SHPR_PRI_N SCB_SHPR_PRI_N_Msk /*!< Priority of system handler 4,8, and 12. Mem Manage, reserved and Debug Monitor */\r
+#define SCB_SHPR_PRI_N1_Pos (8U) \r
+#define SCB_SHPR_PRI_N1_Msk (0xFFUL << SCB_SHPR_PRI_N1_Pos) /*!< 0x0000FF00 */\r
+#define SCB_SHPR_PRI_N1 SCB_SHPR_PRI_N1_Msk /*!< Priority of system handler 5,9, and 13. Bus Fault, reserved and reserved */\r
+#define SCB_SHPR_PRI_N2_Pos (16U) \r
+#define SCB_SHPR_PRI_N2_Msk (0xFFUL << SCB_SHPR_PRI_N2_Pos) /*!< 0x00FF0000 */\r
+#define SCB_SHPR_PRI_N2 SCB_SHPR_PRI_N2_Msk /*!< Priority of system handler 6,10, and 14. Usage Fault, reserved and PendSV */\r
+#define SCB_SHPR_PRI_N3_Pos (24U) \r
+#define SCB_SHPR_PRI_N3_Msk (0xFFUL << SCB_SHPR_PRI_N3_Pos) /*!< 0xFF000000 */\r
+#define SCB_SHPR_PRI_N3 SCB_SHPR_PRI_N3_Msk /*!< Priority of system handler 7,11, and 15. Reserved, SVCall and SysTick */\r
+\r
+/****************** Bit definition for SCB_SHCSR register *******************/\r
+#define SCB_SHCSR_MEMFAULTACT (0x00000001U) /*!< MemManage is active */\r
+#define SCB_SHCSR_BUSFAULTACT (0x00000002U) /*!< BusFault is active */\r
+#define SCB_SHCSR_USGFAULTACT (0x00000008U) /*!< UsageFault is active */\r
+#define SCB_SHCSR_SVCALLACT (0x00000080U) /*!< SVCall is active */\r
+#define SCB_SHCSR_MONITORACT (0x00000100U) /*!< Monitor is active */\r
+#define SCB_SHCSR_PENDSVACT (0x00000400U) /*!< PendSV is active */\r
+#define SCB_SHCSR_SYSTICKACT (0x00000800U) /*!< SysTick is active */\r
+#define SCB_SHCSR_USGFAULTPENDED (0x00001000U) /*!< Usage Fault is pended */\r
+#define SCB_SHCSR_MEMFAULTPENDED (0x00002000U) /*!< MemManage is pended */\r
+#define SCB_SHCSR_BUSFAULTPENDED (0x00004000U) /*!< Bus Fault is pended */\r
+#define SCB_SHCSR_SVCALLPENDED (0x00008000U) /*!< SVCall is pended */\r
+#define SCB_SHCSR_MEMFAULTENA (0x00010000U) /*!< MemManage enable */\r
+#define SCB_SHCSR_BUSFAULTENA (0x00020000U) /*!< Bus Fault enable */\r
+#define SCB_SHCSR_USGFAULTENA (0x00040000U) /*!< UsageFault enable */\r
+\r
+/******************* Bit definition for SCB_CFSR register *******************/\r
+/*!< MFSR */\r
+#define SCB_CFSR_IACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 0U) /*!< SCB CFSR (MMFSR): IACCVIOL Position */\r
+#define SCB_CFSR_IACCVIOL_Msk (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/) /*!< SCB CFSR (MMFSR): IACCVIOL Mask */\r
+#define SCB_CFSR_IACCVIOL SCB_CFSR_IACCVIOL_Msk /*!< Instruction access violation */\r
+#define SCB_CFSR_DACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 1U) /*!< SCB CFSR (MMFSR): DACCVIOL Position */\r
+#define SCB_CFSR_DACCVIOL_Msk (1UL << SCB_CFSR_DACCVIOL_Pos) /*!< SCB CFSR (MMFSR): DACCVIOL Mask */\r
+#define SCB_CFSR_DACCVIOL SCB_CFSR_DACCVIOL_Msk /*!< Data access violation */\r
+#define SCB_CFSR_MUNSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 3U) /*!< SCB CFSR (MMFSR): MUNSTKERR Position */\r
+#define SCB_CFSR_MUNSTKERR_Msk (1UL << SCB_CFSR_MUNSTKERR_Pos) /*!< SCB CFSR (MMFSR): MUNSTKERR Mask */\r
+#define SCB_CFSR_MUNSTKERR SCB_CFSR_MUNSTKERR_Msk /*!< Unstacking error */\r
+#define SCB_CFSR_MSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 4U) /*!< SCB CFSR (MMFSR): MSTKERR Position */\r
+#define SCB_CFSR_MSTKERR_Msk (1UL << SCB_CFSR_MSTKERR_Pos) /*!< SCB CFSR (MMFSR): MSTKERR Mask */\r
+#define SCB_CFSR_MSTKERR SCB_CFSR_MSTKERR_Msk /*!< Stacking error */\r
+#define SCB_CFSR_MMARVALID_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 7U) /*!< SCB CFSR (MMFSR): MMARVALID Position */\r
+#define SCB_CFSR_MMARVALID_Msk (1UL << SCB_CFSR_MMARVALID_Pos) /*!< SCB CFSR (MMFSR): MMARVALID Mask */\r
+#define SCB_CFSR_MMARVALID SCB_CFSR_MMARVALID_Msk /*!< Memory Manage Address Register address valid flag */\r
+/*!< BFSR */\r
+#define SCB_CFSR_IBUSERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 0U) /*!< SCB CFSR (BFSR): IBUSERR Position */\r
+#define SCB_CFSR_IBUSERR_Msk (1UL << SCB_CFSR_IBUSERR_Pos) /*!< SCB CFSR (BFSR): IBUSERR Mask */\r
+#define SCB_CFSR_IBUSERR SCB_CFSR_IBUSERR_Msk /*!< Instruction bus error flag */\r
+#define SCB_CFSR_PRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 1U) /*!< SCB CFSR (BFSR): PRECISERR Position */\r
+#define SCB_CFSR_PRECISERR_Msk (1UL << SCB_CFSR_PRECISERR_Pos) /*!< SCB CFSR (BFSR): PRECISERR Mask */\r
+#define SCB_CFSR_PRECISERR SCB_CFSR_PRECISERR_Msk /*!< Precise data bus error */\r
+#define SCB_CFSR_IMPRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 2U) /*!< SCB CFSR (BFSR): IMPRECISERR Position */\r
+#define SCB_CFSR_IMPRECISERR_Msk (1UL << SCB_CFSR_IMPRECISERR_Pos) /*!< SCB CFSR (BFSR): IMPRECISERR Mask */\r
+#define SCB_CFSR_IMPRECISERR SCB_CFSR_IMPRECISERR_Msk /*!< Imprecise data bus error */\r
+#define SCB_CFSR_UNSTKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 3U) /*!< SCB CFSR (BFSR): UNSTKERR Position */\r
+#define SCB_CFSR_UNSTKERR_Msk (1UL << SCB_CFSR_UNSTKERR_Pos) /*!< SCB CFSR (BFSR): UNSTKERR Mask */\r
+#define SCB_CFSR_UNSTKERR SCB_CFSR_UNSTKERR_Msk /*!< Unstacking error */\r
+#define SCB_CFSR_STKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 4U) /*!< SCB CFSR (BFSR): STKERR Position */\r
+#define SCB_CFSR_STKERR_Msk (1UL << SCB_CFSR_STKERR_Pos) /*!< SCB CFSR (BFSR): STKERR Mask */\r
+#define SCB_CFSR_STKERR SCB_CFSR_STKERR_Msk /*!< Stacking error */\r
+#define SCB_CFSR_BFARVALID_Pos (SCB_CFSR_BUSFAULTSR_Pos + 7U) /*!< SCB CFSR (BFSR): BFARVALID Position */\r
+#define SCB_CFSR_BFARVALID_Msk (1UL << SCB_CFSR_BFARVALID_Pos) /*!< SCB CFSR (BFSR): BFARVALID Mask */\r
+#define SCB_CFSR_BFARVALID SCB_CFSR_BFARVALID_Msk /*!< Bus Fault Address Register address valid flag */\r
+/*!< UFSR */\r
+#define SCB_CFSR_UNDEFINSTR_Pos (SCB_CFSR_USGFAULTSR_Pos + 0U) /*!< SCB CFSR (UFSR): UNDEFINSTR Position */\r
+#define SCB_CFSR_UNDEFINSTR_Msk (1UL << SCB_CFSR_UNDEFINSTR_Pos) /*!< SCB CFSR (UFSR): UNDEFINSTR Mask */\r
+#define SCB_CFSR_UNDEFINSTR SCB_CFSR_UNDEFINSTR_Msk /*!< The processor attempt to excecute an undefined instruction */\r
+#define SCB_CFSR_INVSTATE_Pos (SCB_CFSR_USGFAULTSR_Pos + 1U) /*!< SCB CFSR (UFSR): INVSTATE Position */\r
+#define SCB_CFSR_INVSTATE_Msk (1UL << SCB_CFSR_INVSTATE_Pos) /*!< SCB CFSR (UFSR): INVSTATE Mask */\r
+#define SCB_CFSR_INVSTATE SCB_CFSR_INVSTATE_Msk /*!< Invalid combination of EPSR and instruction */\r
+#define SCB_CFSR_INVPC_Pos (SCB_CFSR_USGFAULTSR_Pos + 2U) /*!< SCB CFSR (UFSR): INVPC Position */\r
+#define SCB_CFSR_INVPC_Msk (1UL << SCB_CFSR_INVPC_Pos) /*!< SCB CFSR (UFSR): INVPC Mask */\r
+#define SCB_CFSR_INVPC SCB_CFSR_INVPC_Msk /*!< Attempt to load EXC_RETURN into pc illegally */\r
+#define SCB_CFSR_NOCP_Pos (SCB_CFSR_USGFAULTSR_Pos + 3U) /*!< SCB CFSR (UFSR): NOCP Position */\r
+#define SCB_CFSR_NOCP_Msk (1UL << SCB_CFSR_NOCP_Pos) /*!< SCB CFSR (UFSR): NOCP Mask */\r
+#define SCB_CFSR_NOCP SCB_CFSR_NOCP_Msk /*!< Attempt to use a coprocessor instruction */\r
+#define SCB_CFSR_UNALIGNED_Pos (SCB_CFSR_USGFAULTSR_Pos + 8U) /*!< SCB CFSR (UFSR): UNALIGNED Position */\r
+#define SCB_CFSR_UNALIGNED_Msk (1UL << SCB_CFSR_UNALIGNED_Pos) /*!< SCB CFSR (UFSR): UNALIGNED Mask */\r
+#define SCB_CFSR_UNALIGNED SCB_CFSR_UNALIGNED_Msk /*!< Fault occurs when there is an attempt to make an unaligned memory access */\r
+#define SCB_CFSR_DIVBYZERO_Pos (SCB_CFSR_USGFAULTSR_Pos + 9U) /*!< SCB CFSR (UFSR): DIVBYZERO Position */\r
+#define SCB_CFSR_DIVBYZERO_Msk (1UL << SCB_CFSR_DIVBYZERO_Pos) /*!< SCB CFSR (UFSR): DIVBYZERO Mask */\r
+#define SCB_CFSR_DIVBYZERO SCB_CFSR_DIVBYZERO_Msk /*!< Fault occurs when SDIV or DIV instruction is used with a divisor of 0 */\r
+\r
+/******************* Bit definition for SCB_HFSR register *******************/\r
+#define SCB_HFSR_VECTTBL (0x00000002U) /*!< Fault occures because of vector table read on exception processing */\r
+#define SCB_HFSR_FORCED (0x40000000U) /*!< Hard Fault activated when a configurable Fault was received and cannot activate */\r
+#define SCB_HFSR_DEBUGEVT (0x80000000U) /*!< Fault related to debug */\r
+\r
+/******************* Bit definition for SCB_DFSR register *******************/\r
+#define SCB_DFSR_HALTED (0x00000001U) /*!< Halt request flag */\r
+#define SCB_DFSR_BKPT (0x00000002U) /*!< BKPT flag */\r
+#define SCB_DFSR_DWTTRAP (0x00000004U) /*!< Data Watchpoint and Trace (DWT) flag */\r
+#define SCB_DFSR_VCATCH (0x00000008U) /*!< Vector catch flag */\r
+#define SCB_DFSR_EXTERNAL (0x00000010U) /*!< External debug request flag */\r
+\r
+/******************* Bit definition for SCB_MMFAR register ******************/\r
+#define SCB_MMFAR_ADDRESS_Pos (0U) \r
+#define SCB_MMFAR_ADDRESS_Msk (0xFFFFFFFFUL << SCB_MMFAR_ADDRESS_Pos) /*!< 0xFFFFFFFF */\r
+#define SCB_MMFAR_ADDRESS SCB_MMFAR_ADDRESS_Msk /*!< Mem Manage fault address field */\r
+\r
+/******************* Bit definition for SCB_BFAR register *******************/\r
+#define SCB_BFAR_ADDRESS_Pos (0U) \r
+#define SCB_BFAR_ADDRESS_Msk (0xFFFFFFFFUL << SCB_BFAR_ADDRESS_Pos) /*!< 0xFFFFFFFF */\r
+#define SCB_BFAR_ADDRESS SCB_BFAR_ADDRESS_Msk /*!< Bus fault address field */\r
+\r
+/******************* Bit definition for SCB_afsr register *******************/\r
+#define SCB_AFSR_IMPDEF_Pos (0U) \r
+#define SCB_AFSR_IMPDEF_Msk (0xFFFFFFFFUL << SCB_AFSR_IMPDEF_Pos) /*!< 0xFFFFFFFF */\r
+#define SCB_AFSR_IMPDEF SCB_AFSR_IMPDEF_Msk /*!< Implementation defined */\r
+/**\r
+ * @}\r
+ */\r
+\r
+ /**\r
+ * @}\r
+ */ \r
+/** @addtogroup Exported_macro\r
+ * @{\r
+ */\r
+ \r
+/****************************** ADC Instances *********************************/\r
+#define IS_ADC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == ADC1)\r
+\r
+#define IS_ADC_COMMON_INSTANCE(INSTANCE) ((INSTANCE) == ADC1_COMMON)\r
+\r
+/******************************** COMP Instances ******************************/\r
+#define IS_COMP_ALL_INSTANCE(INSTANCE) (((INSTANCE) == COMP1) || \\r
+ ((INSTANCE) == COMP2))\r
+\r
+#define IS_COMP_COMMON_INSTANCE(COMMON_INSTANCE) ((COMMON_INSTANCE) == COMP12_COMMON)\r
+\r
+/****************************** CRC Instances *********************************/\r
+#define IS_CRC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == CRC)\r
+\r
+/****************************** DAC Instances *********************************/\r
+#define IS_DAC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == DAC)\r
+\r
+/****************************** DMA Instances *********************************/\r
+#define IS_DMA_ALL_INSTANCE(INSTANCE) (((INSTANCE) == DMA1_Channel1) || \\r
+ ((INSTANCE) == DMA1_Channel2) || \\r
+ ((INSTANCE) == DMA1_Channel3) || \\r
+ ((INSTANCE) == DMA1_Channel4) || \\r
+ ((INSTANCE) == DMA1_Channel5) || \\r
+ ((INSTANCE) == DMA1_Channel6) || \\r
+ ((INSTANCE) == DMA1_Channel7) || \\r
+ ((INSTANCE) == DMA2_Channel1) || \\r
+ ((INSTANCE) == DMA2_Channel2) || \\r
+ ((INSTANCE) == DMA2_Channel3) || \\r
+ ((INSTANCE) == DMA2_Channel4) || \\r
+ ((INSTANCE) == DMA2_Channel5))\r
+\r
+/******************************* GPIO Instances *******************************/\r
+#define IS_GPIO_ALL_INSTANCE(INSTANCE) (((INSTANCE) == GPIOA) || \\r
+ ((INSTANCE) == GPIOB) || \\r
+ ((INSTANCE) == GPIOC) || \\r
+ ((INSTANCE) == GPIOD) || \\r
+ ((INSTANCE) == GPIOE) || \\r
+ ((INSTANCE) == GPIOF) || \\r
+ ((INSTANCE) == GPIOG) || \\r
+ ((INSTANCE) == GPIOH))\r
+\r
+/**************************** GPIO Alternate Function Instances ***************/\r
+#define IS_GPIO_AF_INSTANCE(INSTANCE) IS_GPIO_ALL_INSTANCE(INSTANCE)\r
+\r
+/**************************** GPIO Lock Instances *****************************/\r
+/* On L1, all GPIO Bank support the Lock mechanism */\r
+#define IS_GPIO_LOCK_INSTANCE(INSTANCE) IS_GPIO_ALL_INSTANCE(INSTANCE)\r
+\r
+/******************************** I2C Instances *******************************/\r
+#define IS_I2C_ALL_INSTANCE(INSTANCE) (((INSTANCE) == I2C1) || \\r
+ ((INSTANCE) == I2C2))\r
+\r
+/****************************** SMBUS Instances *******************************/\r
+#define IS_SMBUS_ALL_INSTANCE(INSTANCE) IS_I2C_ALL_INSTANCE(INSTANCE)\r
+\r
+/******************************** I2S Instances *******************************/\r
+#define IS_I2S_ALL_INSTANCE(INSTANCE) (((INSTANCE) == SPI2) || \\r
+ ((INSTANCE) == SPI3))\r
+/****************************** IWDG Instances ********************************/\r
+#define IS_IWDG_ALL_INSTANCE(INSTANCE) ((INSTANCE) == IWDG)\r
+\r
+/****************************** OPAMP Instances *******************************/\r
+#define IS_OPAMP_ALL_INSTANCE(INSTANCE) (((INSTANCE) == OPAMP1) || \\r
+ ((INSTANCE) == OPAMP2))\r
+\r
+#define IS_OPAMP_COMMON_INSTANCE(COMMON_INSTANCE) ((COMMON_INSTANCE) == OPAMP12_COMMON)\r
+\r
+/****************************** RTC Instances *********************************/\r
+#define IS_RTC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == RTC)\r
+\r
+/******************************** SPI Instances *******************************/\r
+#define IS_SPI_ALL_INSTANCE(INSTANCE) (((INSTANCE) == SPI1) || \\r
+ ((INSTANCE) == SPI2) || \\r
+ ((INSTANCE) == SPI3))\r
+\r
+/****************************** TIM Instances *********************************/ \r
+#define IS_TIM_INSTANCE(INSTANCE) (((INSTANCE) == TIM2) || \\r
+ ((INSTANCE) == TIM3) || \\r
+ ((INSTANCE) == TIM4) || \\r
+ ((INSTANCE) == TIM5) || \\r
+ ((INSTANCE) == TIM6) || \\r
+ ((INSTANCE) == TIM7) || \\r
+ ((INSTANCE) == TIM9) || \\r
+ ((INSTANCE) == TIM10) || \\r
+ ((INSTANCE) == TIM11))\r
+\r
+#define IS_TIM_CC1_INSTANCE(INSTANCE) (((INSTANCE) == TIM2) || \\r
+ ((INSTANCE) == TIM3) || \\r
+ ((INSTANCE) == TIM4) || \\r
+ ((INSTANCE) == TIM5) || \\r
+ ((INSTANCE) == TIM9) || \\r
+ ((INSTANCE) == TIM10) || \\r
+ ((INSTANCE) == TIM11))\r
+\r
+#define IS_TIM_CC2_INSTANCE(INSTANCE) (((INSTANCE) == TIM2) || \\r
+ ((INSTANCE) == TIM3) || \\r
+ ((INSTANCE) == TIM4) || \\r
+ ((INSTANCE) == TIM5) || \\r
+ ((INSTANCE) == TIM9))\r
+\r
+#define IS_TIM_CC3_INSTANCE(INSTANCE) (((INSTANCE) == TIM2) || \\r
+ ((INSTANCE) == TIM3) || \\r
+ ((INSTANCE) == TIM4) || \\r
+ ((INSTANCE) == TIM5))\r
+\r
+#define IS_TIM_CC4_INSTANCE(INSTANCE) (((INSTANCE) == TIM2) || \\r
+ ((INSTANCE) == TIM3) || \\r
+ ((INSTANCE) == TIM4) || \\r
+ ((INSTANCE) == TIM5))\r
+\r
+#define IS_TIM_CLOCKSOURCE_ETRMODE1_INSTANCE(INSTANCE) (((INSTANCE) == TIM2) || \\r
+ ((INSTANCE) == TIM3) || \\r
+ ((INSTANCE) == TIM4) || \\r
+ ((INSTANCE) == TIM5) || \\r
+ ((INSTANCE) == TIM9))\r
+\r
+#define IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(INSTANCE) (((INSTANCE) == TIM2) || \\r
+ ((INSTANCE) == TIM3) || \\r
+ ((INSTANCE) == TIM4) || \\r
+ ((INSTANCE) == TIM5) || \\r
+ ((INSTANCE) == TIM9) || \\r
+ ((INSTANCE) == TIM10) || \\r
+ ((INSTANCE) == TIM11))\r
+\r
+#define IS_TIM_CLOCKSOURCE_TIX_INSTANCE(INSTANCE) (((INSTANCE) == TIM2) || \\r
+ ((INSTANCE) == TIM3) || \\r
+ ((INSTANCE) == TIM4) || \\r
+ ((INSTANCE) == TIM5) || \\r
+ ((INSTANCE) == TIM9))\r
+\r
+#define IS_TIM_CLOCKSOURCE_ITRX_INSTANCE(INSTANCE) (((INSTANCE) == TIM2) || \\r
+ ((INSTANCE) == TIM3) || \\r
+ ((INSTANCE) == TIM4) || \\r
+ ((INSTANCE) == TIM5) || \\r
+ ((INSTANCE) == TIM9))\r
+\r
+#define IS_TIM_OCXREF_CLEAR_INSTANCE(INSTANCE) (((INSTANCE) == TIM2) || \\r
+ ((INSTANCE) == TIM3) || \\r
+ ((INSTANCE) == TIM4))\r
+\r
+#define IS_TIM_XOR_INSTANCE(INSTANCE) (((INSTANCE) == TIM2) || \\r
+ ((INSTANCE) == TIM3) || \\r
+ ((INSTANCE) == TIM4) || \\r
+ ((INSTANCE) == TIM5))\r
+ \r
+#define IS_TIM_ETR_INSTANCE(INSTANCE) (((INSTANCE) == TIM2) || \\r
+ ((INSTANCE) == TIM3) || \\r
+ ((INSTANCE) == TIM4) || \\r
+ ((INSTANCE) == TIM5) || \\r
+ ((INSTANCE) == TIM9))\r
+\r
+\r
+#define IS_TIM_MASTER_INSTANCE(INSTANCE) (((INSTANCE) == TIM2) || \\r
+ ((INSTANCE) == TIM3) || \\r
+ ((INSTANCE) == TIM4) || \\r
+ ((INSTANCE) == TIM5) || \\r
+ ((INSTANCE) == TIM9))\r
+\r
+#define IS_TIM_SYNCHRO_INSTANCE(INSTANCE) IS_TIM_MASTER_INSTANCE(INSTANCE)\r
+\r
+#define IS_TIM_SLAVE_INSTANCE(INSTANCE) (((INSTANCE) == TIM2) || \\r
+ ((INSTANCE) == TIM3) || \\r
+ ((INSTANCE) == TIM4) || \\r
+ ((INSTANCE) == TIM9))\r
+\r
+#define IS_TIM_32B_COUNTER_INSTANCE(INSTANCE) ((INSTANCE) == TIM5)\r
+\r
+#define IS_TIM_DMABURST_INSTANCE(INSTANCE) (((INSTANCE) == TIM2) || \\r
+ ((INSTANCE) == TIM3) || \\r
+ ((INSTANCE) == TIM4) || \\r
+ ((INSTANCE) == TIM5))\r
+\r
+#define IS_TIM_CCX_INSTANCE(INSTANCE, CHANNEL) \\r
+ ((((INSTANCE) == TIM2) && \\r
+ (((CHANNEL) == TIM_CHANNEL_1) || \\r
+ ((CHANNEL) == TIM_CHANNEL_2) || \\r
+ ((CHANNEL) == TIM_CHANNEL_3) || \\r
+ ((CHANNEL) == TIM_CHANNEL_4))) \\r
+ || \\r
+ (((INSTANCE) == TIM3) && \\r
+ (((CHANNEL) == TIM_CHANNEL_1) || \\r
+ ((CHANNEL) == TIM_CHANNEL_2) || \\r
+ ((CHANNEL) == TIM_CHANNEL_3) || \\r
+ ((CHANNEL) == TIM_CHANNEL_4))) \\r
+ || \\r
+ (((INSTANCE) == TIM4) && \\r
+ (((CHANNEL) == TIM_CHANNEL_1) || \\r
+ ((CHANNEL) == TIM_CHANNEL_2) || \\r
+ ((CHANNEL) == TIM_CHANNEL_3) || \\r
+ ((CHANNEL) == TIM_CHANNEL_4))) \\r
+ || \\r
+ (((INSTANCE) == TIM5) && \\r
+ (((CHANNEL) == TIM_CHANNEL_1) || \\r
+ ((CHANNEL) == TIM_CHANNEL_2) || \\r
+ ((CHANNEL) == TIM_CHANNEL_3) || \\r
+ ((CHANNEL) == TIM_CHANNEL_4))) \\r
+ || \\r
+ (((INSTANCE) == TIM9) && \\r
+ (((CHANNEL) == TIM_CHANNEL_1) || \\r
+ ((CHANNEL) == TIM_CHANNEL_2))) \\r
+ || \\r
+ (((INSTANCE) == TIM10) && \\r
+ (((CHANNEL) == TIM_CHANNEL_1))) \\r
+ || \\r
+ (((INSTANCE) == TIM11) && \\r
+ (((CHANNEL) == TIM_CHANNEL_1))))\r
+\r
+#define IS_TIM_CLOCK_DIVISION_INSTANCE(INSTANCE) (((INSTANCE) == TIM2) || \\r
+ ((INSTANCE) == TIM3) || \\r
+ ((INSTANCE) == TIM4) || \\r
+ ((INSTANCE) == TIM5) || \\r
+ ((INSTANCE) == TIM9) || \\r
+ ((INSTANCE) == TIM10) || \\r
+ ((INSTANCE) == TIM11))\r
+\r
+#define IS_TIM_DMA_INSTANCE(INSTANCE) (((INSTANCE) == TIM2) || \\r
+ ((INSTANCE) == TIM3) || \\r
+ ((INSTANCE) == TIM4) || \\r
+ ((INSTANCE) == TIM5) || \\r
+ ((INSTANCE) == TIM6) || \\r
+ ((INSTANCE) == TIM7))\r
+ \r
+#define IS_TIM_DMA_CC_INSTANCE(INSTANCE) (((INSTANCE) == TIM2) || \\r
+ ((INSTANCE) == TIM3) || \\r
+ ((INSTANCE) == TIM4) || \\r
+ ((INSTANCE) == TIM5))\r
+\r
+#define IS_TIM_COUNTER_MODE_SELECT_INSTANCE(INSTANCE) (((INSTANCE) == TIM2) || \\r
+ ((INSTANCE) == TIM3) || \\r
+ ((INSTANCE) == TIM4) || \\r
+ ((INSTANCE) == TIM5) || \\r
+ ((INSTANCE) == TIM9))\r
+\r
+#define IS_TIM_ENCODER_INTERFACE_INSTANCE(INSTANCE) (((INSTANCE) == TIM2) || \\r
+ ((INSTANCE) == TIM3) || \\r
+ ((INSTANCE) == TIM4) || \\r
+ ((INSTANCE) == TIM5) || \\r
+ ((INSTANCE) == TIM9))\r
+\r
+#define IS_TIM_REMAP_INSTANCE(INSTANCE) (((INSTANCE) == TIM2) || \\r
+ ((INSTANCE) == TIM3) || \\r
+ ((INSTANCE) == TIM9) || \\r
+ ((INSTANCE) == TIM10) || \\r
+ ((INSTANCE) == TIM11))\r
+\r
+/******************** USART Instances : Synchronous mode **********************/ \r
+#define IS_USART_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \\r
+ ((INSTANCE) == USART2) || \\r
+ ((INSTANCE) == USART3))\r
+\r
+/******************** UART Instances : Asynchronous mode **********************/\r
+#define IS_UART_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \\r
+ ((INSTANCE) == USART2) || \\r
+ ((INSTANCE) == USART3) || \\r
+ ((INSTANCE) == UART4) || \\r
+ ((INSTANCE) == UART5))\r
+\r
+/******************** UART Instances : Half-Duplex mode **********************/\r
+#define IS_UART_HALFDUPLEX_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \\r
+ ((INSTANCE) == USART2) || \\r
+ ((INSTANCE) == USART3) || \\r
+ ((INSTANCE) == UART4) || \\r
+ ((INSTANCE) == UART5)) \r
+\r
+/******************** UART Instances : LIN mode **********************/\r
+#define IS_UART_LIN_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \\r
+ ((INSTANCE) == USART2) || \\r
+ ((INSTANCE) == USART3) || \\r
+ ((INSTANCE) == UART4) || \\r
+ ((INSTANCE) == UART5)) \r
+\r
+/****************** UART Instances : Hardware Flow control ********************/ \r
+#define IS_UART_HWFLOW_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \\r
+ ((INSTANCE) == USART2) || \\r
+ ((INSTANCE) == USART3))\r
+\r
+/********************* UART Instances : Smard card mode ***********************/\r
+#define IS_SMARTCARD_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \\r
+ ((INSTANCE) == USART2) || \\r
+ ((INSTANCE) == USART3))\r
+\r
+/*********************** UART Instances : IRDA mode ***************************/\r
+#define IS_IRDA_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \\r
+ ((INSTANCE) == USART2) || \\r
+ ((INSTANCE) == USART3) || \\r
+ ((INSTANCE) == UART4) || \\r
+ ((INSTANCE) == UART5))\r
+\r
+/***************** UART Instances : Multi-Processor mode **********************/\r
+#define IS_UART_MULTIPROCESSOR_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \\r
+ ((INSTANCE) == USART2) || \\r
+ ((INSTANCE) == USART3) || \\r
+ ((INSTANCE) == UART4) || \\r
+ ((INSTANCE) == UART5)) \r
+\r
+/****************************** WWDG Instances ********************************/\r
+#define IS_WWDG_ALL_INSTANCE(INSTANCE) ((INSTANCE) == WWDG)\r
+\r
+\r
+/****************************** LCD Instances ********************************/\r
+#define IS_LCD_ALL_INSTANCE(INSTANCE) ((INSTANCE) == LCD)\r
+\r
+/****************************** USB Instances ********************************/\r
+#define IS_USB_ALL_INSTANCE(INSTANCE) ((INSTANCE) == USB)\r
+#define IS_PCD_ALL_INSTANCE IS_USB_ALL_INSTANCE\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/******************************************************************************/\r
+/* For a painless codes migration between the STM32L1xx device product */\r
+/* lines, the aliases defined below are put in place to overcome the */\r
+/* differences in the interrupt handlers and IRQn definitions. */\r
+/* No need to update developed interrupt code when moving across */ \r
+/* product lines within the same STM32L1 Family */\r
+/******************************************************************************/\r
+\r
+/* Aliases for __IRQn */\r
+\r
+/* Aliases for __IRQHandler */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+#ifdef __cplusplus\r
+}\r
+#endif /* __cplusplus */\r
+\r
+#endif /* __STM32L152xE_H */\r
+\r
+\r
+\r
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\r
--- /dev/null
+/**\r
+ ******************************************************************************\r
+ * @file stm32l1xx.h\r
+ * @author MCD Application Team\r
+ * @brief CMSIS STM32L1xx Device Peripheral Access Layer Header File. \r
+ *\r
+ * The file is the unique include file that the application programmer\r
+ * is using in the C source code, usually in main.c. This file contains:\r
+ * - Configuration section that allows to select:\r
+ * - The STM32L1xx device used in the target application\r
+ * - To use or not the peripheral\92s drivers in application code(i.e. \r
+ * code will be based on direct access to peripheral\92s registers \r
+ * rather than drivers API), this option is controlled by \r
+ * "#define USE_HAL_DRIVER"\r
+ * \r
+ ******************************************************************************\r
+ * @attention\r
+ *\r
+ * <h2><center>© Copyright (c) 2017 STMicroelectronics.\r
+ * All rights reserved.</center></h2>\r
+ *\r
+ * This software component is licensed by ST under BSD 3-Clause license,\r
+ * the "License"; You may not use this file except in compliance with the\r
+ * License. You may obtain a copy of the License at:\r
+ * opensource.org/licenses/BSD-3-Clause\r
+ *\r
+ ******************************************************************************\r
+ */\r
+\r
+/** @addtogroup CMSIS\r
+ * @{\r
+ */\r
+\r
+/** @addtogroup stm32l1xx\r
+ * @{\r
+ */\r
+ \r
+#ifndef __STM32L1XX_H\r
+#define __STM32L1XX_H\r
+\r
+#ifdef __cplusplus\r
+ extern "C" {\r
+#endif /* __cplusplus */\r
+ \r
+/** @addtogroup Library_configuration_section\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @brief STM32 Family\r
+ */\r
+#if !defined (STM32L1)\r
+#define STM32L1\r
+#endif /* STM32L1 */\r
+\r
+\r
+/* Uncomment the line below according to the target STM32L device used in your \r
+ application \r
+ */\r
+\r
+#if !defined (STM32L100xB) && !defined (STM32L100xBA) && !defined (STM32L100xC) && \\r
+ !defined (STM32L151xB) && !defined (STM32L151xBA) && !defined (STM32L151xC) && !defined (STM32L151xCA) && !defined (STM32L151xD) && !defined (STM32L151xDX) && !defined (STM32L151xE) && \\r
+ !defined (STM32L152xB) && !defined (STM32L152xBA) && !defined (STM32L152xC) && !defined (STM32L152xCA) && !defined (STM32L152xD) && !defined (STM32L152xDX) && !defined (STM32L152xE) && \\r
+ !defined (STM32L162xC) && !defined (STM32L162xCA) && !defined (STM32L162xD) && !defined (STM32L162xDX) && !defined (STM32L162xE)\r
+ /* #define STM32L100xB */ /*!< STM32L100C6, STM32L100R and STM32L100RB Devices */\r
+ /* #define STM32L100xBA */ /*!< STM32L100C6-A, STM32L100R8-A and STM32L100RB-A Devices */\r
+ /* #define STM32L100xC */ /*!< STM32L100RC Devices */\r
+ /* #define STM32L151xB */ /*!< STM32L151C6, STM32L151R6, STM32L151C8, STM32L151R8, STM32L151V8, STM32L151CB, STM32L151RB and STM32L151VB */\r
+ /* #define STM32L151xBA */ /*!< STM32L151C6-A, STM32L151R6-A, STM32L151C8-A, STM32L151R8-A, STM32L151V8-A, STM32L151CB-A, STM32L151RB-A and STM32L151VB-A */ \r
+ /* #define STM32L151xC */ /*!< STM32L151CC, STM32L151UC, STM32L151RC and STM32L151VC */\r
+ /* #define STM32L151xCA */ /*!< STM32L151RC-A, STM32L151VC-A, STM32L151QC and STM32L151ZC */\r
+ /* #define STM32L151xD */ /*!< STM32L151QD, STM32L151RD, STM32L151VD & STM32L151ZD */\r
+ /* #define STM32L151xDX */ /*!< STM32L151VD-X Devices */\r
+ /* #define STM32L151xE */ /*!< STM32L151QE, STM32L151RE, STM32L151VE and STM32L151ZE */\r
+ /* #define STM32L152xB */ /*!< STM32L152C6, STM32L152R6, STM32L152C8, STM32L152R8, STM32L152V8, STM32L152CB, STM32L152RB and STM32L152VB */\r
+ /* #define STM32L152xBA */ /*!< STM32L152C6-A, STM32L152R6-A, STM32L152C8-A, STM32L152R8-A, STM32L152V8-A, STM32L152CB-A, STM32L152RB-A and STM32L152VB-A */\r
+ /* #define STM32L152xC */ /*!< STM32L152CC, STM32L152UC, STM32L152RC and STM32L152VC */\r
+ /* #define STM32L152xCA */ /*!< STM32L152RC-A, STM32L152VC-A, STM32L152QC and STM32L152ZC */\r
+ /* #define STM32L152xD */ /*!< STM32L152QD, STM32L152RD, STM32L152VD and STM32L152ZD */\r
+ /* #define STM32L152xDX */ /*!< STM32L152VD-X Devices */\r
+ /* #define STM32L152xE */ /*!< STM32L152QE, STM32L152RE, STM32L152VE and STM32L152ZE */\r
+ /* #define STM32L162xC */ /*!< STM32L162RC and STM32L162VC */\r
+ /* #define STM32L162xCA */ /*!< STM32L162RC-A, STM32L162VC-A, STM32L162QC and STM32L162ZC */\r
+ /* #define STM32L162xD */ /*!< STM32L162QD, STM32L162RD, STM32L162VD and STM32L162ZD */\r
+ /* #define STM32L162xDX */ /*!< STM32L162VD-X Devices */\r
+ /* #define STM32L162xE */ /*!< STM32L162RE, STM32L162VE and STM32L162ZE */\r
+#endif\r
+\r
+/* Tip: To avoid modifying this file each time you need to switch between these\r
+ devices, you can define the device in your toolchain compiler preprocessor.\r
+ */\r
+ \r
+#if !defined (USE_HAL_DRIVER)\r
+/**\r
+ * @brief Comment the line below if you will not use the peripherals drivers.\r
+ In this case, these drivers will not be included and the application code will \r
+ be based on direct access to peripherals registers \r
+ */\r
+ /*#define USE_HAL_DRIVER */\r
+#endif /* USE_HAL_DRIVER */\r
+\r
+/**\r
+ * @brief CMSIS Device version number\r
+ */\r
+#define __STM32L1xx_CMSIS_VERSION_MAIN (0x02) /*!< [31:24] main version */ \r
+#define __STM32L1xx_CMSIS_VERSION_SUB1 (0x03) /*!< [23:16] sub1 version */\r
+#define __STM32L1xx_CMSIS_VERSION_SUB2 (0x00) /*!< [15:8] sub2 version */\r
+#define __STM32L1xx_CMSIS_VERSION_RC (0x00) /*!< [7:0] release candidate */ \r
+#define __STM32L1xx_CMSIS_VERSION ((__STM32L1xx_CMSIS_VERSION_MAIN << 24)\\r
+ |(__STM32L1xx_CMSIS_VERSION_SUB1 << 16)\\r
+ |(__STM32L1xx_CMSIS_VERSION_SUB2 << 8 )\\r
+ |(__STM32L1xx_CMSIS_VERSION_RC))\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @addtogroup Device_Included\r
+ * @{\r
+ */\r
+\r
+#if defined(STM32L100xB)\r
+ #include "stm32l100xb.h"\r
+#elif defined(STM32L100xBA)\r
+ #include "stm32l100xba.h"\r
+#elif defined(STM32L100xC)\r
+ #include "stm32l100xc.h"\r
+#elif defined(STM32L151xB)\r
+ #include "stm32l151xb.h"\r
+#elif defined(STM32L151xBA)\r
+ #include "stm32l151xba.h"\r
+#elif defined(STM32L151xC)\r
+ #include "stm32l151xc.h"\r
+#elif defined(STM32L151xCA)\r
+ #include "stm32l151xca.h"\r
+#elif defined(STM32L151xD)\r
+ #include "stm32l151xd.h"\r
+#elif defined(STM32L151xDX)\r
+ #include "stm32l151xdx.h"\r
+#elif defined(STM32L151xE)\r
+ #include "stm32l151xe.h"\r
+#elif defined(STM32L152xB)\r
+ #include "stm32l152xb.h"\r
+#elif defined(STM32L152xBA)\r
+ #include "stm32l152xba.h"\r
+#elif defined(STM32L152xC)\r
+ #include "stm32l152xc.h"\r
+#elif defined(STM32L152xCA)\r
+ #include "stm32l152xca.h"\r
+#elif defined(STM32L152xD)\r
+ #include "stm32l152xd.h"\r
+#elif defined(STM32L152xDX)\r
+ #include "stm32l152xdx.h"\r
+#elif defined(STM32L152xE)\r
+ #include "stm32l152xe.h"\r
+#elif defined(STM32L162xC)\r
+ #include "stm32l162xc.h"\r
+#elif defined(STM32L162xCA)\r
+ #include "stm32l162xca.h"\r
+#elif defined(STM32L162xD)\r
+ #include "stm32l162xd.h"\r
+#elif defined(STM32L162xDX)\r
+ #include "stm32l162xdx.h"\r
+#elif defined(STM32L162xE)\r
+ #include "stm32l162xe.h"\r
+#else\r
+ #error "Please select first the target STM32L1xx device used in your application (in stm32l1xx.h file)"\r
+#endif\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @addtogroup Exported_types\r
+ * @{\r
+ */ \r
+typedef enum \r
+{\r
+ RESET = 0, \r
+ SET = !RESET\r
+} FlagStatus, ITStatus;\r
+\r
+typedef enum \r
+{\r
+ DISABLE = 0, \r
+ ENABLE = !DISABLE\r
+} FunctionalState;\r
+#define IS_FUNCTIONAL_STATE(STATE) (((STATE) == DISABLE) || ((STATE) == ENABLE))\r
+\r
+typedef enum \r
+{\r
+ SUCCESS = 0,\r
+ ERROR = !SUCCESS\r
+} ErrorStatus;\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+\r
+/** @addtogroup Exported_macros\r
+ * @{\r
+ */\r
+#define SET_BIT(REG, BIT) ((REG) |= (BIT))\r
+\r
+#define CLEAR_BIT(REG, BIT) ((REG) &= ~(BIT))\r
+\r
+#define READ_BIT(REG, BIT) ((REG) & (BIT))\r
+\r
+#define CLEAR_REG(REG) ((REG) = (0x0))\r
+\r
+#define WRITE_REG(REG, VAL) ((REG) = (VAL))\r
+\r
+#define READ_REG(REG) ((REG))\r
+\r
+#define MODIFY_REG(REG, CLEARMASK, SETMASK) WRITE_REG((REG), (((READ_REG(REG)) & (~(CLEARMASK))) | (SETMASK)))\r
+\r
+#define POSITION_VAL(VAL) (__CLZ(__RBIT(VAL))) \r
+\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+#if defined (USE_HAL_DRIVER)\r
+ #include "stm32l1xx_hal.h"\r
+#endif /* USE_HAL_DRIVER */\r
+\r
+\r
+#ifdef __cplusplus\r
+}\r
+#endif /* __cplusplus */\r
+\r
+#endif /* __STM32L1xx_H */\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+ \r
+\r
+\r
+\r
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\r
--- /dev/null
+/**\r
+ ******************************************************************************\r
+ * @file system_stm32l1xx.h\r
+ * @author MCD Application Team\r
+ * @brief CMSIS Cortex-M3 Device System Source File for STM32L1xx devices. \r
+ ******************************************************************************\r
+ * @attention\r
+ *\r
+ * <h2><center>© Copyright (c) 2017 STMicroelectronics.\r
+ * All rights reserved.</center></h2>\r
+ *\r
+ * This software component is licensed by ST under BSD 3-Clause license,\r
+ * the "License"; You may not use this file except in compliance with the\r
+ * License. You may obtain a copy of the License at:\r
+ * opensource.org/licenses/BSD-3-Clause\r
+ *\r
+ ******************************************************************************\r
+ */\r
+\r
+/** @addtogroup CMSIS\r
+ * @{\r
+ */\r
+\r
+/** @addtogroup stm32l1xx_system\r
+ * @{\r
+ */ \r
+ \r
+/**\r
+ * @brief Define to prevent recursive inclusion\r
+ */\r
+#ifndef __SYSTEM_STM32L1XX_H\r
+#define __SYSTEM_STM32L1XX_H\r
+\r
+#ifdef __cplusplus\r
+ extern "C" {\r
+#endif \r
+\r
+/** @addtogroup STM32L1xx_System_Includes\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+\r
+/** @addtogroup STM32L1xx_System_Exported_types\r
+ * @{\r
+ */\r
+ /* This variable is updated in three ways:\r
+ 1) by calling CMSIS function SystemCoreClockUpdate()\r
+ 2) by calling HAL API function HAL_RCC_GetSysClockFreq()\r
+ 3) each time HAL_RCC_ClockConfig() is called to configure the system clock frequency \r
+ Note: If you use this function to configure the system clock; then there\r
+ is no need to call the 2 first functions listed above, since SystemCoreClock\r
+ variable is updated automatically.\r
+ */\r
+extern uint32_t SystemCoreClock; /*!< System Clock Frequency (Core Clock) */\r
+/*\r
+*/\r
+extern const uint8_t AHBPrescTable[16]; /*!< AHB prescalers table values */\r
+extern const uint8_t APBPrescTable[8]; /*!< APB prescalers table values */\r
+extern const uint8_t PLLMulTable[9]; /*!< PLL multipiers table values */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @addtogroup STM32L1xx_System_Exported_Constants\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @addtogroup STM32L1xx_System_Exported_Macros\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @addtogroup STM32L1xx_System_Exported_Functions\r
+ * @{\r
+ */\r
+ \r
+extern void SystemInit(void);\r
+extern void SystemCoreClockUpdate(void);\r
+/**\r
+ * @}\r
+ */\r
+\r
+#ifdef __cplusplus\r
+}\r
+#endif\r
+\r
+#endif /*__SYSTEM_STM32L1XX_H */\r
+\r
+/**\r
+ * @}\r
+ */\r
+ \r
+/**\r
+ * @}\r
+ */ \r
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\r
--- /dev/null
+/**************************************************************************//**\r
+ * @file cmsis_armcc.h\r
+ * @brief CMSIS compiler ARMCC (Arm Compiler 5) header file\r
+ * @version V5.0.4\r
+ * @date 10. January 2018\r
+ ******************************************************************************/\r
+/*\r
+ * Copyright (c) 2009-2018 Arm Limited. All rights reserved.\r
+ *\r
+ * SPDX-License-Identifier: Apache-2.0\r
+ *\r
+ * Licensed under the Apache License, Version 2.0 (the License); you may\r
+ * not use this file except in compliance with the License.\r
+ * You may obtain a copy of the License at\r
+ *\r
+ * www.apache.org/licenses/LICENSE-2.0\r
+ *\r
+ * Unless required by applicable law or agreed to in writing, software\r
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT\r
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\r
+ * See the License for the specific language governing permissions and\r
+ * limitations under the License.\r
+ */\r
+\r
+#ifndef __CMSIS_ARMCC_H\r
+#define __CMSIS_ARMCC_H\r
+\r
+\r
+#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 400677)\r
+ #error "Please use Arm Compiler Toolchain V4.0.677 or later!"\r
+#endif\r
+\r
+/* CMSIS compiler control architecture macros */\r
+#if ((defined (__TARGET_ARCH_6_M ) && (__TARGET_ARCH_6_M == 1)) || \\r
+ (defined (__TARGET_ARCH_6S_M ) && (__TARGET_ARCH_6S_M == 1)) )\r
+ #define __ARM_ARCH_6M__ 1\r
+#endif\r
+\r
+#if (defined (__TARGET_ARCH_7_M ) && (__TARGET_ARCH_7_M == 1))\r
+ #define __ARM_ARCH_7M__ 1\r
+#endif\r
+\r
+#if (defined (__TARGET_ARCH_7E_M) && (__TARGET_ARCH_7E_M == 1))\r
+ #define __ARM_ARCH_7EM__ 1\r
+#endif\r
+\r
+ /* __ARM_ARCH_8M_BASE__ not applicable */\r
+ /* __ARM_ARCH_8M_MAIN__ not applicable */\r
+\r
+\r
+/* CMSIS compiler specific defines */\r
+#ifndef __ASM\r
+ #define __ASM __asm\r
+#endif\r
+#ifndef __INLINE\r
+ #define __INLINE __inline\r
+#endif\r
+#ifndef __STATIC_INLINE\r
+ #define __STATIC_INLINE static __inline\r
+#endif\r
+#ifndef __STATIC_FORCEINLINE \r
+ #define __STATIC_FORCEINLINE static __forceinline\r
+#endif \r
+#ifndef __NO_RETURN\r
+ #define __NO_RETURN __declspec(noreturn)\r
+#endif\r
+#ifndef __USED\r
+ #define __USED __attribute__((used))\r
+#endif\r
+#ifndef __WEAK\r
+ #define __WEAK __attribute__((weak))\r
+#endif\r
+#ifndef __PACKED\r
+ #define __PACKED __attribute__((packed))\r
+#endif\r
+#ifndef __PACKED_STRUCT\r
+ #define __PACKED_STRUCT __packed struct\r
+#endif\r
+#ifndef __PACKED_UNION\r
+ #define __PACKED_UNION __packed union\r
+#endif\r
+#ifndef __UNALIGNED_UINT32 /* deprecated */\r
+ #define __UNALIGNED_UINT32(x) (*((__packed uint32_t *)(x)))\r
+#endif\r
+#ifndef __UNALIGNED_UINT16_WRITE\r
+ #define __UNALIGNED_UINT16_WRITE(addr, val) ((*((__packed uint16_t *)(addr))) = (val))\r
+#endif\r
+#ifndef __UNALIGNED_UINT16_READ\r
+ #define __UNALIGNED_UINT16_READ(addr) (*((const __packed uint16_t *)(addr)))\r
+#endif\r
+#ifndef __UNALIGNED_UINT32_WRITE\r
+ #define __UNALIGNED_UINT32_WRITE(addr, val) ((*((__packed uint32_t *)(addr))) = (val))\r
+#endif\r
+#ifndef __UNALIGNED_UINT32_READ\r
+ #define __UNALIGNED_UINT32_READ(addr) (*((const __packed uint32_t *)(addr)))\r
+#endif\r
+#ifndef __ALIGNED\r
+ #define __ALIGNED(x) __attribute__((aligned(x)))\r
+#endif\r
+#ifndef __RESTRICT\r
+ #define __RESTRICT __restrict\r
+#endif\r
+\r
+/* ########################### Core Function Access ########################### */\r
+/** \ingroup CMSIS_Core_FunctionInterface\r
+ \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions\r
+ @{\r
+ */\r
+\r
+/**\r
+ \brief Enable IRQ Interrupts\r
+ \details Enables IRQ interrupts by clearing the I-bit in the CPSR.\r
+ Can only be executed in Privileged modes.\r
+ */\r
+/* intrinsic void __enable_irq(); */\r
+\r
+\r
+/**\r
+ \brief Disable IRQ Interrupts\r
+ \details Disables IRQ interrupts by setting the I-bit in the CPSR.\r
+ Can only be executed in Privileged modes.\r
+ */\r
+/* intrinsic void __disable_irq(); */\r
+\r
+/**\r
+ \brief Get Control Register\r
+ \details Returns the content of the Control Register.\r
+ \return Control Register value\r
+ */\r
+__STATIC_INLINE uint32_t __get_CONTROL(void)\r
+{\r
+ register uint32_t __regControl __ASM("control");\r
+ return(__regControl);\r
+}\r
+\r
+\r
+/**\r
+ \brief Set Control Register\r
+ \details Writes the given value to the Control Register.\r
+ \param [in] control Control Register value to set\r
+ */\r
+__STATIC_INLINE void __set_CONTROL(uint32_t control)\r
+{\r
+ register uint32_t __regControl __ASM("control");\r
+ __regControl = control;\r
+}\r
+\r
+\r
+/**\r
+ \brief Get IPSR Register\r
+ \details Returns the content of the IPSR Register.\r
+ \return IPSR Register value\r
+ */\r
+__STATIC_INLINE uint32_t __get_IPSR(void)\r
+{\r
+ register uint32_t __regIPSR __ASM("ipsr");\r
+ return(__regIPSR);\r
+}\r
+\r
+\r
+/**\r
+ \brief Get APSR Register\r
+ \details Returns the content of the APSR Register.\r
+ \return APSR Register value\r
+ */\r
+__STATIC_INLINE uint32_t __get_APSR(void)\r
+{\r
+ register uint32_t __regAPSR __ASM("apsr");\r
+ return(__regAPSR);\r
+}\r
+\r
+\r
+/**\r
+ \brief Get xPSR Register\r
+ \details Returns the content of the xPSR Register.\r
+ \return xPSR Register value\r
+ */\r
+__STATIC_INLINE uint32_t __get_xPSR(void)\r
+{\r
+ register uint32_t __regXPSR __ASM("xpsr");\r
+ return(__regXPSR);\r
+}\r
+\r
+\r
+/**\r
+ \brief Get Process Stack Pointer\r
+ \details Returns the current value of the Process Stack Pointer (PSP).\r
+ \return PSP Register value\r
+ */\r
+__STATIC_INLINE uint32_t __get_PSP(void)\r
+{\r
+ register uint32_t __regProcessStackPointer __ASM("psp");\r
+ return(__regProcessStackPointer);\r
+}\r
+\r
+\r
+/**\r
+ \brief Set Process Stack Pointer\r
+ \details Assigns the given value to the Process Stack Pointer (PSP).\r
+ \param [in] topOfProcStack Process Stack Pointer value to set\r
+ */\r
+__STATIC_INLINE void __set_PSP(uint32_t topOfProcStack)\r
+{\r
+ register uint32_t __regProcessStackPointer __ASM("psp");\r
+ __regProcessStackPointer = topOfProcStack;\r
+}\r
+\r
+\r
+/**\r
+ \brief Get Main Stack Pointer\r
+ \details Returns the current value of the Main Stack Pointer (MSP).\r
+ \return MSP Register value\r
+ */\r
+__STATIC_INLINE uint32_t __get_MSP(void)\r
+{\r
+ register uint32_t __regMainStackPointer __ASM("msp");\r
+ return(__regMainStackPointer);\r
+}\r
+\r
+\r
+/**\r
+ \brief Set Main Stack Pointer\r
+ \details Assigns the given value to the Main Stack Pointer (MSP).\r
+ \param [in] topOfMainStack Main Stack Pointer value to set\r
+ */\r
+__STATIC_INLINE void __set_MSP(uint32_t topOfMainStack)\r
+{\r
+ register uint32_t __regMainStackPointer __ASM("msp");\r
+ __regMainStackPointer = topOfMainStack;\r
+}\r
+\r
+\r
+/**\r
+ \brief Get Priority Mask\r
+ \details Returns the current state of the priority mask bit from the Priority Mask Register.\r
+ \return Priority Mask value\r
+ */\r
+__STATIC_INLINE uint32_t __get_PRIMASK(void)\r
+{\r
+ register uint32_t __regPriMask __ASM("primask");\r
+ return(__regPriMask);\r
+}\r
+\r
+\r
+/**\r
+ \brief Set Priority Mask\r
+ \details Assigns the given value to the Priority Mask Register.\r
+ \param [in] priMask Priority Mask\r
+ */\r
+__STATIC_INLINE void __set_PRIMASK(uint32_t priMask)\r
+{\r
+ register uint32_t __regPriMask __ASM("primask");\r
+ __regPriMask = (priMask);\r
+}\r
+\r
+\r
+#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \\r
+ (defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) )\r
+\r
+/**\r
+ \brief Enable FIQ\r
+ \details Enables FIQ interrupts by clearing the F-bit in the CPSR.\r
+ Can only be executed in Privileged modes.\r
+ */\r
+#define __enable_fault_irq __enable_fiq\r
+\r
+\r
+/**\r
+ \brief Disable FIQ\r
+ \details Disables FIQ interrupts by setting the F-bit in the CPSR.\r
+ Can only be executed in Privileged modes.\r
+ */\r
+#define __disable_fault_irq __disable_fiq\r
+\r
+\r
+/**\r
+ \brief Get Base Priority\r
+ \details Returns the current value of the Base Priority register.\r
+ \return Base Priority register value\r
+ */\r
+__STATIC_INLINE uint32_t __get_BASEPRI(void)\r
+{\r
+ register uint32_t __regBasePri __ASM("basepri");\r
+ return(__regBasePri);\r
+}\r
+\r
+\r
+/**\r
+ \brief Set Base Priority\r
+ \details Assigns the given value to the Base Priority register.\r
+ \param [in] basePri Base Priority value to set\r
+ */\r
+__STATIC_INLINE void __set_BASEPRI(uint32_t basePri)\r
+{\r
+ register uint32_t __regBasePri __ASM("basepri");\r
+ __regBasePri = (basePri & 0xFFU);\r
+}\r
+\r
+\r
+/**\r
+ \brief Set Base Priority with condition\r
+ \details Assigns the given value to the Base Priority register only if BASEPRI masking is disabled,\r
+ or the new value increases the BASEPRI priority level.\r
+ \param [in] basePri Base Priority value to set\r
+ */\r
+__STATIC_INLINE void __set_BASEPRI_MAX(uint32_t basePri)\r
+{\r
+ register uint32_t __regBasePriMax __ASM("basepri_max");\r
+ __regBasePriMax = (basePri & 0xFFU);\r
+}\r
+\r
+\r
+/**\r
+ \brief Get Fault Mask\r
+ \details Returns the current value of the Fault Mask register.\r
+ \return Fault Mask register value\r
+ */\r
+__STATIC_INLINE uint32_t __get_FAULTMASK(void)\r
+{\r
+ register uint32_t __regFaultMask __ASM("faultmask");\r
+ return(__regFaultMask);\r
+}\r
+\r
+\r
+/**\r
+ \brief Set Fault Mask\r
+ \details Assigns the given value to the Fault Mask register.\r
+ \param [in] faultMask Fault Mask value to set\r
+ */\r
+__STATIC_INLINE void __set_FAULTMASK(uint32_t faultMask)\r
+{\r
+ register uint32_t __regFaultMask __ASM("faultmask");\r
+ __regFaultMask = (faultMask & (uint32_t)1U);\r
+}\r
+\r
+#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \\r
+ (defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) */\r
+\r
+\r
+/**\r
+ \brief Get FPSCR\r
+ \details Returns the current value of the Floating Point Status/Control register.\r
+ \return Floating Point Status/Control register value\r
+ */\r
+__STATIC_INLINE uint32_t __get_FPSCR(void)\r
+{\r
+#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \\r
+ (defined (__FPU_USED ) && (__FPU_USED == 1U)) )\r
+ register uint32_t __regfpscr __ASM("fpscr");\r
+ return(__regfpscr);\r
+#else\r
+ return(0U);\r
+#endif\r
+}\r
+\r
+\r
+/**\r
+ \brief Set FPSCR\r
+ \details Assigns the given value to the Floating Point Status/Control register.\r
+ \param [in] fpscr Floating Point Status/Control value to set\r
+ */\r
+__STATIC_INLINE void __set_FPSCR(uint32_t fpscr)\r
+{\r
+#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \\r
+ (defined (__FPU_USED ) && (__FPU_USED == 1U)) )\r
+ register uint32_t __regfpscr __ASM("fpscr");\r
+ __regfpscr = (fpscr);\r
+#else\r
+ (void)fpscr;\r
+#endif\r
+}\r
+\r
+\r
+/*@} end of CMSIS_Core_RegAccFunctions */\r
+\r
+\r
+/* ########################## Core Instruction Access ######################### */\r
+/** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface\r
+ Access to dedicated instructions\r
+ @{\r
+*/\r
+\r
+/**\r
+ \brief No Operation\r
+ \details No Operation does nothing. This instruction can be used for code alignment purposes.\r
+ */\r
+#define __NOP __nop\r
+\r
+\r
+/**\r
+ \brief Wait For Interrupt\r
+ \details Wait For Interrupt is a hint instruction that suspends execution until one of a number of events occurs.\r
+ */\r
+#define __WFI __wfi\r
+\r
+\r
+/**\r
+ \brief Wait For Event\r
+ \details Wait For Event is a hint instruction that permits the processor to enter\r
+ a low-power state until one of a number of events occurs.\r
+ */\r
+#define __WFE __wfe\r
+\r
+\r
+/**\r
+ \brief Send Event\r
+ \details Send Event is a hint instruction. It causes an event to be signaled to the CPU.\r
+ */\r
+#define __SEV __sev\r
+\r
+\r
+/**\r
+ \brief Instruction Synchronization Barrier\r
+ \details Instruction Synchronization Barrier flushes the pipeline in the processor,\r
+ so that all instructions following the ISB are fetched from cache or memory,\r
+ after the instruction has been completed.\r
+ */\r
+#define __ISB() do {\\r
+ __schedule_barrier();\\r
+ __isb(0xF);\\r
+ __schedule_barrier();\\r
+ } while (0U)\r
+\r
+/**\r
+ \brief Data Synchronization Barrier\r
+ \details Acts as a special kind of Data Memory Barrier.\r
+ It completes when all explicit memory accesses before this instruction complete.\r
+ */\r
+#define __DSB() do {\\r
+ __schedule_barrier();\\r
+ __dsb(0xF);\\r
+ __schedule_barrier();\\r
+ } while (0U)\r
+\r
+/**\r
+ \brief Data Memory Barrier\r
+ \details Ensures the apparent order of the explicit memory operations before\r
+ and after the instruction, without ensuring their completion.\r
+ */\r
+#define __DMB() do {\\r
+ __schedule_barrier();\\r
+ __dmb(0xF);\\r
+ __schedule_barrier();\\r
+ } while (0U)\r
+\r
+ \r
+/**\r
+ \brief Reverse byte order (32 bit)\r
+ \details Reverses the byte order in unsigned integer value. For example, 0x12345678 becomes 0x78563412.\r
+ \param [in] value Value to reverse\r
+ \return Reversed value\r
+ */\r
+#define __REV __rev\r
+\r
+\r
+/**\r
+ \brief Reverse byte order (16 bit)\r
+ \details Reverses the byte order within each halfword of a word. For example, 0x12345678 becomes 0x34127856.\r
+ \param [in] value Value to reverse\r
+ \return Reversed value\r
+ */\r
+#ifndef __NO_EMBEDDED_ASM\r
+__attribute__((section(".rev16_text"))) __STATIC_INLINE __ASM uint32_t __REV16(uint32_t value)\r
+{\r
+ rev16 r0, r0\r
+ bx lr\r
+}\r
+#endif\r
+\r
+\r
+/**\r
+ \brief Reverse byte order (16 bit)\r
+ \details Reverses the byte order in a 16-bit value and returns the signed 16-bit result. For example, 0x0080 becomes 0x8000.\r
+ \param [in] value Value to reverse\r
+ \return Reversed value\r
+ */\r
+#ifndef __NO_EMBEDDED_ASM\r
+__attribute__((section(".revsh_text"))) __STATIC_INLINE __ASM int16_t __REVSH(int16_t value)\r
+{\r
+ revsh r0, r0\r
+ bx lr\r
+}\r
+#endif\r
+\r
+\r
+/**\r
+ \brief Rotate Right in unsigned value (32 bit)\r
+ \details Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits.\r
+ \param [in] op1 Value to rotate\r
+ \param [in] op2 Number of Bits to rotate\r
+ \return Rotated value\r
+ */\r
+#define __ROR __ror\r
+\r
+\r
+/**\r
+ \brief Breakpoint\r
+ \details Causes the processor to enter Debug state.\r
+ Debug tools can use this to investigate system state when the instruction at a particular address is reached.\r
+ \param [in] value is ignored by the processor.\r
+ If required, a debugger can use it to store additional information about the breakpoint.\r
+ */\r
+#define __BKPT(value) __breakpoint(value)\r
+\r
+\r
+/**\r
+ \brief Reverse bit order of value\r
+ \details Reverses the bit order of the given value.\r
+ \param [in] value Value to reverse\r
+ \return Reversed value\r
+ */\r
+#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \\r
+ (defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) )\r
+ #define __RBIT __rbit\r
+#else\r
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __RBIT(uint32_t value)\r
+{\r
+ uint32_t result;\r
+ uint32_t s = (4U /*sizeof(v)*/ * 8U) - 1U; /* extra shift needed at end */\r
+\r
+ result = value; /* r will be reversed bits of v; first get LSB of v */\r
+ for (value >>= 1U; value != 0U; value >>= 1U)\r
+ {\r
+ result <<= 1U;\r
+ result |= value & 1U;\r
+ s--;\r
+ }\r
+ result <<= s; /* shift when v's highest bits are zero */\r
+ return result;\r
+}\r
+#endif\r
+\r
+\r
+/**\r
+ \brief Count leading zeros\r
+ \details Counts the number of leading zeros of a data value.\r
+ \param [in] value Value to count the leading zeros\r
+ \return number of leading zeros in value\r
+ */\r
+#define __CLZ __clz\r
+\r
+\r
+#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \\r
+ (defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) )\r
+\r
+/**\r
+ \brief LDR Exclusive (8 bit)\r
+ \details Executes a exclusive LDR instruction for 8 bit value.\r
+ \param [in] ptr Pointer to data\r
+ \return value of type uint8_t at (*ptr)\r
+ */\r
+#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020)\r
+ #define __LDREXB(ptr) ((uint8_t ) __ldrex(ptr))\r
+#else\r
+ #define __LDREXB(ptr) _Pragma("push") _Pragma("diag_suppress 3731") ((uint8_t ) __ldrex(ptr)) _Pragma("pop")\r
+#endif\r
+\r
+\r
+/**\r
+ \brief LDR Exclusive (16 bit)\r
+ \details Executes a exclusive LDR instruction for 16 bit values.\r
+ \param [in] ptr Pointer to data\r
+ \return value of type uint16_t at (*ptr)\r
+ */\r
+#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020)\r
+ #define __LDREXH(ptr) ((uint16_t) __ldrex(ptr))\r
+#else\r
+ #define __LDREXH(ptr) _Pragma("push") _Pragma("diag_suppress 3731") ((uint16_t) __ldrex(ptr)) _Pragma("pop")\r
+#endif\r
+\r
+\r
+/**\r
+ \brief LDR Exclusive (32 bit)\r
+ \details Executes a exclusive LDR instruction for 32 bit values.\r
+ \param [in] ptr Pointer to data\r
+ \return value of type uint32_t at (*ptr)\r
+ */\r
+#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020)\r
+ #define __LDREXW(ptr) ((uint32_t ) __ldrex(ptr))\r
+#else\r
+ #define __LDREXW(ptr) _Pragma("push") _Pragma("diag_suppress 3731") ((uint32_t ) __ldrex(ptr)) _Pragma("pop")\r
+#endif\r
+\r
+\r
+/**\r
+ \brief STR Exclusive (8 bit)\r
+ \details Executes a exclusive STR instruction for 8 bit values.\r
+ \param [in] value Value to store\r
+ \param [in] ptr Pointer to location\r
+ \return 0 Function succeeded\r
+ \return 1 Function failed\r
+ */\r
+#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020)\r
+ #define __STREXB(value, ptr) __strex(value, ptr)\r
+#else\r
+ #define __STREXB(value, ptr) _Pragma("push") _Pragma("diag_suppress 3731") __strex(value, ptr) _Pragma("pop")\r
+#endif\r
+\r
+\r
+/**\r
+ \brief STR Exclusive (16 bit)\r
+ \details Executes a exclusive STR instruction for 16 bit values.\r
+ \param [in] value Value to store\r
+ \param [in] ptr Pointer to location\r
+ \return 0 Function succeeded\r
+ \return 1 Function failed\r
+ */\r
+#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020)\r
+ #define __STREXH(value, ptr) __strex(value, ptr)\r
+#else\r
+ #define __STREXH(value, ptr) _Pragma("push") _Pragma("diag_suppress 3731") __strex(value, ptr) _Pragma("pop")\r
+#endif\r
+\r
+\r
+/**\r
+ \brief STR Exclusive (32 bit)\r
+ \details Executes a exclusive STR instruction for 32 bit values.\r
+ \param [in] value Value to store\r
+ \param [in] ptr Pointer to location\r
+ \return 0 Function succeeded\r
+ \return 1 Function failed\r
+ */\r
+#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020)\r
+ #define __STREXW(value, ptr) __strex(value, ptr)\r
+#else\r
+ #define __STREXW(value, ptr) _Pragma("push") _Pragma("diag_suppress 3731") __strex(value, ptr) _Pragma("pop")\r
+#endif\r
+\r
+\r
+/**\r
+ \brief Remove the exclusive lock\r
+ \details Removes the exclusive lock which is created by LDREX.\r
+ */\r
+#define __CLREX __clrex\r
+\r
+\r
+/**\r
+ \brief Signed Saturate\r
+ \details Saturates a signed value.\r
+ \param [in] value Value to be saturated\r
+ \param [in] sat Bit position to saturate to (1..32)\r
+ \return Saturated value\r
+ */\r
+#define __SSAT __ssat\r
+\r
+\r
+/**\r
+ \brief Unsigned Saturate\r
+ \details Saturates an unsigned value.\r
+ \param [in] value Value to be saturated\r
+ \param [in] sat Bit position to saturate to (0..31)\r
+ \return Saturated value\r
+ */\r
+#define __USAT __usat\r
+\r
+\r
+/**\r
+ \brief Rotate Right with Extend (32 bit)\r
+ \details Moves each bit of a bitstring right by one bit.\r
+ The carry input is shifted in at the left end of the bitstring.\r
+ \param [in] value Value to rotate\r
+ \return Rotated value\r
+ */\r
+#ifndef __NO_EMBEDDED_ASM\r
+__attribute__((section(".rrx_text"))) __STATIC_INLINE __ASM uint32_t __RRX(uint32_t value)\r
+{\r
+ rrx r0, r0\r
+ bx lr\r
+}\r
+#endif\r
+\r
+\r
+/**\r
+ \brief LDRT Unprivileged (8 bit)\r
+ \details Executes a Unprivileged LDRT instruction for 8 bit value.\r
+ \param [in] ptr Pointer to data\r
+ \return value of type uint8_t at (*ptr)\r
+ */\r
+#define __LDRBT(ptr) ((uint8_t ) __ldrt(ptr))\r
+\r
+\r
+/**\r
+ \brief LDRT Unprivileged (16 bit)\r
+ \details Executes a Unprivileged LDRT instruction for 16 bit values.\r
+ \param [in] ptr Pointer to data\r
+ \return value of type uint16_t at (*ptr)\r
+ */\r
+#define __LDRHT(ptr) ((uint16_t) __ldrt(ptr))\r
+\r
+\r
+/**\r
+ \brief LDRT Unprivileged (32 bit)\r
+ \details Executes a Unprivileged LDRT instruction for 32 bit values.\r
+ \param [in] ptr Pointer to data\r
+ \return value of type uint32_t at (*ptr)\r
+ */\r
+#define __LDRT(ptr) ((uint32_t ) __ldrt(ptr))\r
+\r
+\r
+/**\r
+ \brief STRT Unprivileged (8 bit)\r
+ \details Executes a Unprivileged STRT instruction for 8 bit values.\r
+ \param [in] value Value to store\r
+ \param [in] ptr Pointer to location\r
+ */\r
+#define __STRBT(value, ptr) __strt(value, ptr)\r
+\r
+\r
+/**\r
+ \brief STRT Unprivileged (16 bit)\r
+ \details Executes a Unprivileged STRT instruction for 16 bit values.\r
+ \param [in] value Value to store\r
+ \param [in] ptr Pointer to location\r
+ */\r
+#define __STRHT(value, ptr) __strt(value, ptr)\r
+\r
+\r
+/**\r
+ \brief STRT Unprivileged (32 bit)\r
+ \details Executes a Unprivileged STRT instruction for 32 bit values.\r
+ \param [in] value Value to store\r
+ \param [in] ptr Pointer to location\r
+ */\r
+#define __STRT(value, ptr) __strt(value, ptr)\r
+\r
+#else /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \\r
+ (defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) */\r
+\r
+/**\r
+ \brief Signed Saturate\r
+ \details Saturates a signed value.\r
+ \param [in] value Value to be saturated\r
+ \param [in] sat Bit position to saturate to (1..32)\r
+ \return Saturated value\r
+ */\r
+__attribute__((always_inline)) __STATIC_INLINE int32_t __SSAT(int32_t val, uint32_t sat)\r
+{\r
+ if ((sat >= 1U) && (sat <= 32U))\r
+ {\r
+ const int32_t max = (int32_t)((1U << (sat - 1U)) - 1U);\r
+ const int32_t min = -1 - max ;\r
+ if (val > max)\r
+ {\r
+ return max;\r
+ }\r
+ else if (val < min)\r
+ {\r
+ return min;\r
+ }\r
+ }\r
+ return val;\r
+}\r
+\r
+/**\r
+ \brief Unsigned Saturate\r
+ \details Saturates an unsigned value.\r
+ \param [in] value Value to be saturated\r
+ \param [in] sat Bit position to saturate to (0..31)\r
+ \return Saturated value\r
+ */\r
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __USAT(int32_t val, uint32_t sat)\r
+{\r
+ if (sat <= 31U)\r
+ {\r
+ const uint32_t max = ((1U << sat) - 1U);\r
+ if (val > (int32_t)max)\r
+ {\r
+ return max;\r
+ }\r
+ else if (val < 0)\r
+ {\r
+ return 0U;\r
+ }\r
+ }\r
+ return (uint32_t)val;\r
+}\r
+\r
+#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \\r
+ (defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) */\r
+\r
+/*@}*/ /* end of group CMSIS_Core_InstructionInterface */\r
+\r
+\r
+/* ################### Compiler specific Intrinsics ########################### */\r
+/** \defgroup CMSIS_SIMD_intrinsics CMSIS SIMD Intrinsics\r
+ Access to dedicated SIMD instructions\r
+ @{\r
+*/\r
+\r
+#if ((defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) )\r
+\r
+#define __SADD8 __sadd8\r
+#define __QADD8 __qadd8\r
+#define __SHADD8 __shadd8\r
+#define __UADD8 __uadd8\r
+#define __UQADD8 __uqadd8\r
+#define __UHADD8 __uhadd8\r
+#define __SSUB8 __ssub8\r
+#define __QSUB8 __qsub8\r
+#define __SHSUB8 __shsub8\r
+#define __USUB8 __usub8\r
+#define __UQSUB8 __uqsub8\r
+#define __UHSUB8 __uhsub8\r
+#define __SADD16 __sadd16\r
+#define __QADD16 __qadd16\r
+#define __SHADD16 __shadd16\r
+#define __UADD16 __uadd16\r
+#define __UQADD16 __uqadd16\r
+#define __UHADD16 __uhadd16\r
+#define __SSUB16 __ssub16\r
+#define __QSUB16 __qsub16\r
+#define __SHSUB16 __shsub16\r
+#define __USUB16 __usub16\r
+#define __UQSUB16 __uqsub16\r
+#define __UHSUB16 __uhsub16\r
+#define __SASX __sasx\r
+#define __QASX __qasx\r
+#define __SHASX __shasx\r
+#define __UASX __uasx\r
+#define __UQASX __uqasx\r
+#define __UHASX __uhasx\r
+#define __SSAX __ssax\r
+#define __QSAX __qsax\r
+#define __SHSAX __shsax\r
+#define __USAX __usax\r
+#define __UQSAX __uqsax\r
+#define __UHSAX __uhsax\r
+#define __USAD8 __usad8\r
+#define __USADA8 __usada8\r
+#define __SSAT16 __ssat16\r
+#define __USAT16 __usat16\r
+#define __UXTB16 __uxtb16\r
+#define __UXTAB16 __uxtab16\r
+#define __SXTB16 __sxtb16\r
+#define __SXTAB16 __sxtab16\r
+#define __SMUAD __smuad\r
+#define __SMUADX __smuadx\r
+#define __SMLAD __smlad\r
+#define __SMLADX __smladx\r
+#define __SMLALD __smlald\r
+#define __SMLALDX __smlaldx\r
+#define __SMUSD __smusd\r
+#define __SMUSDX __smusdx\r
+#define __SMLSD __smlsd\r
+#define __SMLSDX __smlsdx\r
+#define __SMLSLD __smlsld\r
+#define __SMLSLDX __smlsldx\r
+#define __SEL __sel\r
+#define __QADD __qadd\r
+#define __QSUB __qsub\r
+\r
+#define __PKHBT(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0x0000FFFFUL) | \\r
+ ((((uint32_t)(ARG2)) << (ARG3)) & 0xFFFF0000UL) )\r
+\r
+#define __PKHTB(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0xFFFF0000UL) | \\r
+ ((((uint32_t)(ARG2)) >> (ARG3)) & 0x0000FFFFUL) )\r
+\r
+#define __SMMLA(ARG1,ARG2,ARG3) ( (int32_t)((((int64_t)(ARG1) * (ARG2)) + \\r
+ ((int64_t)(ARG3) << 32U) ) >> 32U))\r
+\r
+#endif /* ((defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) */\r
+/*@} end of group CMSIS_SIMD_intrinsics */\r
+\r
+\r
+#endif /* __CMSIS_ARMCC_H */\r
--- /dev/null
+/**************************************************************************//**\r
+ * @file cmsis_armclang.h\r
+ * @brief CMSIS compiler armclang (Arm Compiler 6) header file\r
+ * @version V5.0.4\r
+ * @date 10. January 2018\r
+ ******************************************************************************/\r
+/*\r
+ * Copyright (c) 2009-2018 Arm Limited. All rights reserved.\r
+ *\r
+ * SPDX-License-Identifier: Apache-2.0\r
+ *\r
+ * Licensed under the Apache License, Version 2.0 (the License); you may\r
+ * not use this file except in compliance with the License.\r
+ * You may obtain a copy of the License at\r
+ *\r
+ * www.apache.org/licenses/LICENSE-2.0\r
+ *\r
+ * Unless required by applicable law or agreed to in writing, software\r
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT\r
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\r
+ * See the License for the specific language governing permissions and\r
+ * limitations under the License.\r
+ */\r
+\r
+/*lint -esym(9058, IRQn)*/ /* disable MISRA 2012 Rule 2.4 for IRQn */\r
+\r
+#ifndef __CMSIS_ARMCLANG_H\r
+#define __CMSIS_ARMCLANG_H\r
+\r
+#pragma clang system_header /* treat file as system include file */\r
+\r
+#ifndef __ARM_COMPAT_H\r
+#include <arm_compat.h> /* Compatibility header for Arm Compiler 5 intrinsics */\r
+#endif\r
+\r
+/* CMSIS compiler specific defines */\r
+#ifndef __ASM\r
+ #define __ASM __asm\r
+#endif\r
+#ifndef __INLINE\r
+ #define __INLINE __inline\r
+#endif\r
+#ifndef __STATIC_INLINE\r
+ #define __STATIC_INLINE static __inline\r
+#endif\r
+#ifndef __STATIC_FORCEINLINE \r
+ #define __STATIC_FORCEINLINE __attribute__((always_inline)) static __inline\r
+#endif \r
+#ifndef __NO_RETURN\r
+ #define __NO_RETURN __attribute__((__noreturn__))\r
+#endif\r
+#ifndef __USED\r
+ #define __USED __attribute__((used))\r
+#endif\r
+#ifndef __WEAK\r
+ #define __WEAK __attribute__((weak))\r
+#endif\r
+#ifndef __PACKED\r
+ #define __PACKED __attribute__((packed, aligned(1)))\r
+#endif\r
+#ifndef __PACKED_STRUCT\r
+ #define __PACKED_STRUCT struct __attribute__((packed, aligned(1)))\r
+#endif\r
+#ifndef __PACKED_UNION\r
+ #define __PACKED_UNION union __attribute__((packed, aligned(1)))\r
+#endif\r
+#ifndef __UNALIGNED_UINT32 /* deprecated */\r
+ #pragma clang diagnostic push\r
+ #pragma clang diagnostic ignored "-Wpacked"\r
+/*lint -esym(9058, T_UINT32)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT32 */\r
+ struct __attribute__((packed)) T_UINT32 { uint32_t v; };\r
+ #pragma clang diagnostic pop\r
+ #define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v)\r
+#endif\r
+#ifndef __UNALIGNED_UINT16_WRITE\r
+ #pragma clang diagnostic push\r
+ #pragma clang diagnostic ignored "-Wpacked"\r
+/*lint -esym(9058, T_UINT16_WRITE)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT16_WRITE */\r
+ __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; };\r
+ #pragma clang diagnostic pop\r
+ #define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val))\r
+#endif\r
+#ifndef __UNALIGNED_UINT16_READ\r
+ #pragma clang diagnostic push\r
+ #pragma clang diagnostic ignored "-Wpacked"\r
+/*lint -esym(9058, T_UINT16_READ)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT16_READ */\r
+ __PACKED_STRUCT T_UINT16_READ { uint16_t v; };\r
+ #pragma clang diagnostic pop\r
+ #define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v)\r
+#endif\r
+#ifndef __UNALIGNED_UINT32_WRITE\r
+ #pragma clang diagnostic push\r
+ #pragma clang diagnostic ignored "-Wpacked"\r
+/*lint -esym(9058, T_UINT32_WRITE)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT32_WRITE */\r
+ __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; };\r
+ #pragma clang diagnostic pop\r
+ #define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val))\r
+#endif\r
+#ifndef __UNALIGNED_UINT32_READ\r
+ #pragma clang diagnostic push\r
+ #pragma clang diagnostic ignored "-Wpacked"\r
+/*lint -esym(9058, T_UINT32_READ)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT32_READ */\r
+ __PACKED_STRUCT T_UINT32_READ { uint32_t v; };\r
+ #pragma clang diagnostic pop\r
+ #define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v)\r
+#endif\r
+#ifndef __ALIGNED\r
+ #define __ALIGNED(x) __attribute__((aligned(x)))\r
+#endif\r
+#ifndef __RESTRICT\r
+ #define __RESTRICT __restrict\r
+#endif\r
+\r
+\r
+/* ########################### Core Function Access ########################### */\r
+/** \ingroup CMSIS_Core_FunctionInterface\r
+ \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions\r
+ @{\r
+ */\r
+\r
+/**\r
+ \brief Enable IRQ Interrupts\r
+ \details Enables IRQ interrupts by clearing the I-bit in the CPSR.\r
+ Can only be executed in Privileged modes.\r
+ */\r
+/* intrinsic void __enable_irq(); see arm_compat.h */\r
+\r
+\r
+/**\r
+ \brief Disable IRQ Interrupts\r
+ \details Disables IRQ interrupts by setting the I-bit in the CPSR.\r
+ Can only be executed in Privileged modes.\r
+ */\r
+/* intrinsic void __disable_irq(); see arm_compat.h */\r
+\r
+\r
+/**\r
+ \brief Get Control Register\r
+ \details Returns the content of the Control Register.\r
+ \return Control Register value\r
+ */\r
+__STATIC_FORCEINLINE uint32_t __get_CONTROL(void)\r
+{\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("MRS %0, control" : "=r" (result) );\r
+ return(result);\r
+}\r
+\r
+\r
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))\r
+/**\r
+ \brief Get Control Register (non-secure)\r
+ \details Returns the content of the non-secure Control Register when in secure mode.\r
+ \return non-secure Control Register value\r
+ */\r
+__STATIC_FORCEINLINE uint32_t __TZ_get_CONTROL_NS(void)\r
+{\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("MRS %0, control_ns" : "=r" (result) );\r
+ return(result);\r
+}\r
+#endif\r
+\r
+\r
+/**\r
+ \brief Set Control Register\r
+ \details Writes the given value to the Control Register.\r
+ \param [in] control Control Register value to set\r
+ */\r
+__STATIC_FORCEINLINE void __set_CONTROL(uint32_t control)\r
+{\r
+ __ASM volatile ("MSR control, %0" : : "r" (control) : "memory");\r
+}\r
+\r
+\r
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))\r
+/**\r
+ \brief Set Control Register (non-secure)\r
+ \details Writes the given value to the non-secure Control Register when in secure state.\r
+ \param [in] control Control Register value to set\r
+ */\r
+__STATIC_FORCEINLINE void __TZ_set_CONTROL_NS(uint32_t control)\r
+{\r
+ __ASM volatile ("MSR control_ns, %0" : : "r" (control) : "memory");\r
+}\r
+#endif\r
+\r
+\r
+/**\r
+ \brief Get IPSR Register\r
+ \details Returns the content of the IPSR Register.\r
+ \return IPSR Register value\r
+ */\r
+__STATIC_FORCEINLINE uint32_t __get_IPSR(void)\r
+{\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("MRS %0, ipsr" : "=r" (result) );\r
+ return(result);\r
+}\r
+\r
+\r
+/**\r
+ \brief Get APSR Register\r
+ \details Returns the content of the APSR Register.\r
+ \return APSR Register value\r
+ */\r
+__STATIC_FORCEINLINE uint32_t __get_APSR(void)\r
+{\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("MRS %0, apsr" : "=r" (result) );\r
+ return(result);\r
+}\r
+\r
+\r
+/**\r
+ \brief Get xPSR Register\r
+ \details Returns the content of the xPSR Register.\r
+ \return xPSR Register value\r
+ */\r
+__STATIC_FORCEINLINE uint32_t __get_xPSR(void)\r
+{\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("MRS %0, xpsr" : "=r" (result) );\r
+ return(result);\r
+}\r
+\r
+\r
+/**\r
+ \brief Get Process Stack Pointer\r
+ \details Returns the current value of the Process Stack Pointer (PSP).\r
+ \return PSP Register value\r
+ */\r
+__STATIC_FORCEINLINE uint32_t __get_PSP(void)\r
+{\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("MRS %0, psp" : "=r" (result) );\r
+ return(result);\r
+}\r
+\r
+\r
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))\r
+/**\r
+ \brief Get Process Stack Pointer (non-secure)\r
+ \details Returns the current value of the non-secure Process Stack Pointer (PSP) when in secure state.\r
+ \return PSP Register value\r
+ */\r
+__STATIC_FORCEINLINE uint32_t __TZ_get_PSP_NS(void)\r
+{\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("MRS %0, psp_ns" : "=r" (result) );\r
+ return(result);\r
+}\r
+#endif\r
+\r
+\r
+/**\r
+ \brief Set Process Stack Pointer\r
+ \details Assigns the given value to the Process Stack Pointer (PSP).\r
+ \param [in] topOfProcStack Process Stack Pointer value to set\r
+ */\r
+__STATIC_FORCEINLINE void __set_PSP(uint32_t topOfProcStack)\r
+{\r
+ __ASM volatile ("MSR psp, %0" : : "r" (topOfProcStack) : );\r
+}\r
+\r
+\r
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))\r
+/**\r
+ \brief Set Process Stack Pointer (non-secure)\r
+ \details Assigns the given value to the non-secure Process Stack Pointer (PSP) when in secure state.\r
+ \param [in] topOfProcStack Process Stack Pointer value to set\r
+ */\r
+__STATIC_FORCEINLINE void __TZ_set_PSP_NS(uint32_t topOfProcStack)\r
+{\r
+ __ASM volatile ("MSR psp_ns, %0" : : "r" (topOfProcStack) : );\r
+}\r
+#endif\r
+\r
+\r
+/**\r
+ \brief Get Main Stack Pointer\r
+ \details Returns the current value of the Main Stack Pointer (MSP).\r
+ \return MSP Register value\r
+ */\r
+__STATIC_FORCEINLINE uint32_t __get_MSP(void)\r
+{\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("MRS %0, msp" : "=r" (result) );\r
+ return(result);\r
+}\r
+\r
+\r
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))\r
+/**\r
+ \brief Get Main Stack Pointer (non-secure)\r
+ \details Returns the current value of the non-secure Main Stack Pointer (MSP) when in secure state.\r
+ \return MSP Register value\r
+ */\r
+__STATIC_FORCEINLINE uint32_t __TZ_get_MSP_NS(void)\r
+{\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("MRS %0, msp_ns" : "=r" (result) );\r
+ return(result);\r
+}\r
+#endif\r
+\r
+\r
+/**\r
+ \brief Set Main Stack Pointer\r
+ \details Assigns the given value to the Main Stack Pointer (MSP).\r
+ \param [in] topOfMainStack Main Stack Pointer value to set\r
+ */\r
+__STATIC_FORCEINLINE void __set_MSP(uint32_t topOfMainStack)\r
+{\r
+ __ASM volatile ("MSR msp, %0" : : "r" (topOfMainStack) : );\r
+}\r
+\r
+\r
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))\r
+/**\r
+ \brief Set Main Stack Pointer (non-secure)\r
+ \details Assigns the given value to the non-secure Main Stack Pointer (MSP) when in secure state.\r
+ \param [in] topOfMainStack Main Stack Pointer value to set\r
+ */\r
+__STATIC_FORCEINLINE void __TZ_set_MSP_NS(uint32_t topOfMainStack)\r
+{\r
+ __ASM volatile ("MSR msp_ns, %0" : : "r" (topOfMainStack) : );\r
+}\r
+#endif\r
+\r
+\r
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))\r
+/**\r
+ \brief Get Stack Pointer (non-secure)\r
+ \details Returns the current value of the non-secure Stack Pointer (SP) when in secure state.\r
+ \return SP Register value\r
+ */\r
+__STATIC_FORCEINLINE uint32_t __TZ_get_SP_NS(void)\r
+{\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("MRS %0, sp_ns" : "=r" (result) );\r
+ return(result);\r
+}\r
+\r
+\r
+/**\r
+ \brief Set Stack Pointer (non-secure)\r
+ \details Assigns the given value to the non-secure Stack Pointer (SP) when in secure state.\r
+ \param [in] topOfStack Stack Pointer value to set\r
+ */\r
+__STATIC_FORCEINLINE void __TZ_set_SP_NS(uint32_t topOfStack)\r
+{\r
+ __ASM volatile ("MSR sp_ns, %0" : : "r" (topOfStack) : );\r
+}\r
+#endif\r
+\r
+\r
+/**\r
+ \brief Get Priority Mask\r
+ \details Returns the current state of the priority mask bit from the Priority Mask Register.\r
+ \return Priority Mask value\r
+ */\r
+__STATIC_FORCEINLINE uint32_t __get_PRIMASK(void)\r
+{\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("MRS %0, primask" : "=r" (result) );\r
+ return(result);\r
+}\r
+\r
+\r
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))\r
+/**\r
+ \brief Get Priority Mask (non-secure)\r
+ \details Returns the current state of the non-secure priority mask bit from the Priority Mask Register when in secure state.\r
+ \return Priority Mask value\r
+ */\r
+__STATIC_FORCEINLINE uint32_t __TZ_get_PRIMASK_NS(void)\r
+{\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("MRS %0, primask_ns" : "=r" (result) );\r
+ return(result);\r
+}\r
+#endif\r
+\r
+\r
+/**\r
+ \brief Set Priority Mask\r
+ \details Assigns the given value to the Priority Mask Register.\r
+ \param [in] priMask Priority Mask\r
+ */\r
+__STATIC_FORCEINLINE void __set_PRIMASK(uint32_t priMask)\r
+{\r
+ __ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory");\r
+}\r
+\r
+\r
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))\r
+/**\r
+ \brief Set Priority Mask (non-secure)\r
+ \details Assigns the given value to the non-secure Priority Mask Register when in secure state.\r
+ \param [in] priMask Priority Mask\r
+ */\r
+__STATIC_FORCEINLINE void __TZ_set_PRIMASK_NS(uint32_t priMask)\r
+{\r
+ __ASM volatile ("MSR primask_ns, %0" : : "r" (priMask) : "memory");\r
+}\r
+#endif\r
+\r
+\r
+#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \\r
+ (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \\r
+ (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) )\r
+/**\r
+ \brief Enable FIQ\r
+ \details Enables FIQ interrupts by clearing the F-bit in the CPSR.\r
+ Can only be executed in Privileged modes.\r
+ */\r
+#define __enable_fault_irq __enable_fiq /* see arm_compat.h */\r
+\r
+\r
+/**\r
+ \brief Disable FIQ\r
+ \details Disables FIQ interrupts by setting the F-bit in the CPSR.\r
+ Can only be executed in Privileged modes.\r
+ */\r
+#define __disable_fault_irq __disable_fiq /* see arm_compat.h */\r
+\r
+\r
+/**\r
+ \brief Get Base Priority\r
+ \details Returns the current value of the Base Priority register.\r
+ \return Base Priority register value\r
+ */\r
+__STATIC_FORCEINLINE uint32_t __get_BASEPRI(void)\r
+{\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("MRS %0, basepri" : "=r" (result) );\r
+ return(result);\r
+}\r
+\r
+\r
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))\r
+/**\r
+ \brief Get Base Priority (non-secure)\r
+ \details Returns the current value of the non-secure Base Priority register when in secure state.\r
+ \return Base Priority register value\r
+ */\r
+__STATIC_FORCEINLINE uint32_t __TZ_get_BASEPRI_NS(void)\r
+{\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("MRS %0, basepri_ns" : "=r" (result) );\r
+ return(result);\r
+}\r
+#endif\r
+\r
+\r
+/**\r
+ \brief Set Base Priority\r
+ \details Assigns the given value to the Base Priority register.\r
+ \param [in] basePri Base Priority value to set\r
+ */\r
+__STATIC_FORCEINLINE void __set_BASEPRI(uint32_t basePri)\r
+{\r
+ __ASM volatile ("MSR basepri, %0" : : "r" (basePri) : "memory");\r
+}\r
+\r
+\r
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))\r
+/**\r
+ \brief Set Base Priority (non-secure)\r
+ \details Assigns the given value to the non-secure Base Priority register when in secure state.\r
+ \param [in] basePri Base Priority value to set\r
+ */\r
+__STATIC_FORCEINLINE void __TZ_set_BASEPRI_NS(uint32_t basePri)\r
+{\r
+ __ASM volatile ("MSR basepri_ns, %0" : : "r" (basePri) : "memory");\r
+}\r
+#endif\r
+\r
+\r
+/**\r
+ \brief Set Base Priority with condition\r
+ \details Assigns the given value to the Base Priority register only if BASEPRI masking is disabled,\r
+ or the new value increases the BASEPRI priority level.\r
+ \param [in] basePri Base Priority value to set\r
+ */\r
+__STATIC_FORCEINLINE void __set_BASEPRI_MAX(uint32_t basePri)\r
+{\r
+ __ASM volatile ("MSR basepri_max, %0" : : "r" (basePri) : "memory");\r
+}\r
+\r
+\r
+/**\r
+ \brief Get Fault Mask\r
+ \details Returns the current value of the Fault Mask register.\r
+ \return Fault Mask register value\r
+ */\r
+__STATIC_FORCEINLINE uint32_t __get_FAULTMASK(void)\r
+{\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("MRS %0, faultmask" : "=r" (result) );\r
+ return(result);\r
+}\r
+\r
+\r
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))\r
+/**\r
+ \brief Get Fault Mask (non-secure)\r
+ \details Returns the current value of the non-secure Fault Mask register when in secure state.\r
+ \return Fault Mask register value\r
+ */\r
+__STATIC_FORCEINLINE uint32_t __TZ_get_FAULTMASK_NS(void)\r
+{\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("MRS %0, faultmask_ns" : "=r" (result) );\r
+ return(result);\r
+}\r
+#endif\r
+\r
+\r
+/**\r
+ \brief Set Fault Mask\r
+ \details Assigns the given value to the Fault Mask register.\r
+ \param [in] faultMask Fault Mask value to set\r
+ */\r
+__STATIC_FORCEINLINE void __set_FAULTMASK(uint32_t faultMask)\r
+{\r
+ __ASM volatile ("MSR faultmask, %0" : : "r" (faultMask) : "memory");\r
+}\r
+\r
+\r
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))\r
+/**\r
+ \brief Set Fault Mask (non-secure)\r
+ \details Assigns the given value to the non-secure Fault Mask register when in secure state.\r
+ \param [in] faultMask Fault Mask value to set\r
+ */\r
+__STATIC_FORCEINLINE void __TZ_set_FAULTMASK_NS(uint32_t faultMask)\r
+{\r
+ __ASM volatile ("MSR faultmask_ns, %0" : : "r" (faultMask) : "memory");\r
+}\r
+#endif\r
+\r
+#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \\r
+ (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \\r
+ (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) */\r
+\r
+\r
+#if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \\r
+ (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) )\r
+\r
+/**\r
+ \brief Get Process Stack Pointer Limit\r
+ Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure\r
+ Stack Pointer Limit register hence zero is returned always in non-secure\r
+ mode.\r
+ \r
+ \details Returns the current value of the Process Stack Pointer Limit (PSPLIM).\r
+ \return PSPLIM Register value\r
+ */\r
+__STATIC_FORCEINLINE uint32_t __get_PSPLIM(void)\r
+{\r
+#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \\r
+ (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))\r
+ // without main extensions, the non-secure PSPLIM is RAZ/WI\r
+ return 0U;\r
+#else\r
+ uint32_t result;\r
+ __ASM volatile ("MRS %0, psplim" : "=r" (result) );\r
+ return result;\r
+#endif\r
+}\r
+\r
+#if (defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3))\r
+/**\r
+ \brief Get Process Stack Pointer Limit (non-secure)\r
+ Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure\r
+ Stack Pointer Limit register hence zero is returned always in non-secure\r
+ mode.\r
+\r
+ \details Returns the current value of the non-secure Process Stack Pointer Limit (PSPLIM) when in secure state.\r
+ \return PSPLIM Register value\r
+ */\r
+__STATIC_FORCEINLINE uint32_t __TZ_get_PSPLIM_NS(void)\r
+{\r
+#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)))\r
+ // without main extensions, the non-secure PSPLIM is RAZ/WI\r
+ return 0U;\r
+#else\r
+ uint32_t result;\r
+ __ASM volatile ("MRS %0, psplim_ns" : "=r" (result) );\r
+ return result;\r
+#endif\r
+}\r
+#endif\r
+\r
+\r
+/**\r
+ \brief Set Process Stack Pointer Limit\r
+ Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure\r
+ Stack Pointer Limit register hence the write is silently ignored in non-secure\r
+ mode.\r
+ \r
+ \details Assigns the given value to the Process Stack Pointer Limit (PSPLIM).\r
+ \param [in] ProcStackPtrLimit Process Stack Pointer Limit value to set\r
+ */\r
+__STATIC_FORCEINLINE void __set_PSPLIM(uint32_t ProcStackPtrLimit)\r
+{\r
+#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \\r
+ (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))\r
+ // without main extensions, the non-secure PSPLIM is RAZ/WI\r
+ (void)ProcStackPtrLimit;\r
+#else\r
+ __ASM volatile ("MSR psplim, %0" : : "r" (ProcStackPtrLimit));\r
+#endif\r
+}\r
+\r
+\r
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))\r
+/**\r
+ \brief Set Process Stack Pointer (non-secure)\r
+ Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure\r
+ Stack Pointer Limit register hence the write is silently ignored in non-secure\r
+ mode.\r
+\r
+ \details Assigns the given value to the non-secure Process Stack Pointer Limit (PSPLIM) when in secure state.\r
+ \param [in] ProcStackPtrLimit Process Stack Pointer Limit value to set\r
+ */\r
+__STATIC_FORCEINLINE void __TZ_set_PSPLIM_NS(uint32_t ProcStackPtrLimit)\r
+{\r
+#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)))\r
+ // without main extensions, the non-secure PSPLIM is RAZ/WI\r
+ (void)ProcStackPtrLimit;\r
+#else\r
+ __ASM volatile ("MSR psplim_ns, %0\n" : : "r" (ProcStackPtrLimit));\r
+#endif\r
+}\r
+#endif\r
+\r
+\r
+/**\r
+ \brief Get Main Stack Pointer Limit\r
+ Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure\r
+ Stack Pointer Limit register hence zero is returned always.\r
+\r
+ \details Returns the current value of the Main Stack Pointer Limit (MSPLIM).\r
+ \return MSPLIM Register value\r
+ */\r
+__STATIC_FORCEINLINE uint32_t __get_MSPLIM(void)\r
+{\r
+#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \\r
+ (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))\r
+ // without main extensions, the non-secure MSPLIM is RAZ/WI\r
+ return 0U;\r
+#else\r
+ uint32_t result;\r
+ __ASM volatile ("MRS %0, msplim" : "=r" (result) );\r
+ return result;\r
+#endif\r
+}\r
+\r
+\r
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))\r
+/**\r
+ \brief Get Main Stack Pointer Limit (non-secure)\r
+ Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure\r
+ Stack Pointer Limit register hence zero is returned always.\r
+\r
+ \details Returns the current value of the non-secure Main Stack Pointer Limit(MSPLIM) when in secure state.\r
+ \return MSPLIM Register value\r
+ */\r
+__STATIC_FORCEINLINE uint32_t __TZ_get_MSPLIM_NS(void)\r
+{\r
+#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)))\r
+ // without main extensions, the non-secure MSPLIM is RAZ/WI\r
+ return 0U;\r
+#else\r
+ uint32_t result;\r
+ __ASM volatile ("MRS %0, msplim_ns" : "=r" (result) );\r
+ return result;\r
+#endif\r
+}\r
+#endif\r
+\r
+\r
+/**\r
+ \brief Set Main Stack Pointer Limit\r
+ Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure\r
+ Stack Pointer Limit register hence the write is silently ignored.\r
+\r
+ \details Assigns the given value to the Main Stack Pointer Limit (MSPLIM).\r
+ \param [in] MainStackPtrLimit Main Stack Pointer Limit value to set\r
+ */\r
+__STATIC_FORCEINLINE void __set_MSPLIM(uint32_t MainStackPtrLimit)\r
+{\r
+#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \\r
+ (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))\r
+ // without main extensions, the non-secure MSPLIM is RAZ/WI\r
+ (void)MainStackPtrLimit;\r
+#else\r
+ __ASM volatile ("MSR msplim, %0" : : "r" (MainStackPtrLimit));\r
+#endif\r
+}\r
+\r
+\r
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))\r
+/**\r
+ \brief Set Main Stack Pointer Limit (non-secure)\r
+ Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure\r
+ Stack Pointer Limit register hence the write is silently ignored.\r
+\r
+ \details Assigns the given value to the non-secure Main Stack Pointer Limit (MSPLIM) when in secure state.\r
+ \param [in] MainStackPtrLimit Main Stack Pointer value to set\r
+ */\r
+__STATIC_FORCEINLINE void __TZ_set_MSPLIM_NS(uint32_t MainStackPtrLimit)\r
+{\r
+#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)))\r
+ // without main extensions, the non-secure MSPLIM is RAZ/WI\r
+ (void)MainStackPtrLimit;\r
+#else\r
+ __ASM volatile ("MSR msplim_ns, %0" : : "r" (MainStackPtrLimit));\r
+#endif\r
+}\r
+#endif\r
+\r
+#endif /* ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \\r
+ (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) */\r
+\r
+/**\r
+ \brief Get FPSCR\r
+ \details Returns the current value of the Floating Point Status/Control register.\r
+ \return Floating Point Status/Control register value\r
+ */\r
+#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \\r
+ (defined (__FPU_USED ) && (__FPU_USED == 1U)) )\r
+#define __get_FPSCR (uint32_t)__builtin_arm_get_fpscr\r
+#else\r
+#define __get_FPSCR() ((uint32_t)0U)\r
+#endif\r
+\r
+/**\r
+ \brief Set FPSCR\r
+ \details Assigns the given value to the Floating Point Status/Control register.\r
+ \param [in] fpscr Floating Point Status/Control value to set\r
+ */\r
+#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \\r
+ (defined (__FPU_USED ) && (__FPU_USED == 1U)) )\r
+#define __set_FPSCR __builtin_arm_set_fpscr\r
+#else\r
+#define __set_FPSCR(x) ((void)(x))\r
+#endif\r
+\r
+\r
+/*@} end of CMSIS_Core_RegAccFunctions */\r
+\r
+\r
+/* ########################## Core Instruction Access ######################### */\r
+/** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface\r
+ Access to dedicated instructions\r
+ @{\r
+*/\r
+\r
+/* Define macros for porting to both thumb1 and thumb2.\r
+ * For thumb1, use low register (r0-r7), specified by constraint "l"\r
+ * Otherwise, use general registers, specified by constraint "r" */\r
+#if defined (__thumb__) && !defined (__thumb2__)\r
+#define __CMSIS_GCC_OUT_REG(r) "=l" (r)\r
+#define __CMSIS_GCC_USE_REG(r) "l" (r)\r
+#else\r
+#define __CMSIS_GCC_OUT_REG(r) "=r" (r)\r
+#define __CMSIS_GCC_USE_REG(r) "r" (r)\r
+#endif\r
+\r
+/**\r
+ \brief No Operation\r
+ \details No Operation does nothing. This instruction can be used for code alignment purposes.\r
+ */\r
+#define __NOP __builtin_arm_nop\r
+\r
+/**\r
+ \brief Wait For Interrupt\r
+ \details Wait For Interrupt is a hint instruction that suspends execution until one of a number of events occurs.\r
+ */\r
+#define __WFI __builtin_arm_wfi\r
+\r
+\r
+/**\r
+ \brief Wait For Event\r
+ \details Wait For Event is a hint instruction that permits the processor to enter\r
+ a low-power state until one of a number of events occurs.\r
+ */\r
+#define __WFE __builtin_arm_wfe\r
+\r
+\r
+/**\r
+ \brief Send Event\r
+ \details Send Event is a hint instruction. It causes an event to be signaled to the CPU.\r
+ */\r
+#define __SEV __builtin_arm_sev\r
+\r
+\r
+/**\r
+ \brief Instruction Synchronization Barrier\r
+ \details Instruction Synchronization Barrier flushes the pipeline in the processor,\r
+ so that all instructions following the ISB are fetched from cache or memory,\r
+ after the instruction has been completed.\r
+ */\r
+#define __ISB() __builtin_arm_isb(0xF);\r
+\r
+/**\r
+ \brief Data Synchronization Barrier\r
+ \details Acts as a special kind of Data Memory Barrier.\r
+ It completes when all explicit memory accesses before this instruction complete.\r
+ */\r
+#define __DSB() __builtin_arm_dsb(0xF);\r
+\r
+\r
+/**\r
+ \brief Data Memory Barrier\r
+ \details Ensures the apparent order of the explicit memory operations before\r
+ and after the instruction, without ensuring their completion.\r
+ */\r
+#define __DMB() __builtin_arm_dmb(0xF);\r
+\r
+\r
+/**\r
+ \brief Reverse byte order (32 bit)\r
+ \details Reverses the byte order in unsigned integer value. For example, 0x12345678 becomes 0x78563412.\r
+ \param [in] value Value to reverse\r
+ \return Reversed value\r
+ */\r
+#define __REV(value) __builtin_bswap32(value)\r
+\r
+\r
+/**\r
+ \brief Reverse byte order (16 bit)\r
+ \details Reverses the byte order within each halfword of a word. For example, 0x12345678 becomes 0x34127856.\r
+ \param [in] value Value to reverse\r
+ \return Reversed value\r
+ */\r
+#define __REV16(value) __ROR(__REV(value), 16)\r
+\r
+\r
+/**\r
+ \brief Reverse byte order (16 bit)\r
+ \details Reverses the byte order in a 16-bit value and returns the signed 16-bit result. For example, 0x0080 becomes 0x8000.\r
+ \param [in] value Value to reverse\r
+ \return Reversed value\r
+ */\r
+#define __REVSH(value) (int16_t)__builtin_bswap16(value)\r
+\r
+\r
+/**\r
+ \brief Rotate Right in unsigned value (32 bit)\r
+ \details Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits.\r
+ \param [in] op1 Value to rotate\r
+ \param [in] op2 Number of Bits to rotate\r
+ \return Rotated value\r
+ */\r
+__STATIC_FORCEINLINE uint32_t __ROR(uint32_t op1, uint32_t op2)\r
+{\r
+ op2 %= 32U;\r
+ if (op2 == 0U)\r
+ {\r
+ return op1;\r
+ }\r
+ return (op1 >> op2) | (op1 << (32U - op2));\r
+}\r
+\r
+\r
+/**\r
+ \brief Breakpoint\r
+ \details Causes the processor to enter Debug state.\r
+ Debug tools can use this to investigate system state when the instruction at a particular address is reached.\r
+ \param [in] value is ignored by the processor.\r
+ If required, a debugger can use it to store additional information about the breakpoint.\r
+ */\r
+#define __BKPT(value) __ASM volatile ("bkpt "#value)\r
+\r
+\r
+/**\r
+ \brief Reverse bit order of value\r
+ \details Reverses the bit order of the given value.\r
+ \param [in] value Value to reverse\r
+ \return Reversed value\r
+ */\r
+#define __RBIT __builtin_arm_rbit\r
+\r
+/**\r
+ \brief Count leading zeros\r
+ \details Counts the number of leading zeros of a data value.\r
+ \param [in] value Value to count the leading zeros\r
+ \return number of leading zeros in value\r
+ */\r
+#define __CLZ (uint8_t)__builtin_clz\r
+\r
+\r
+#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \\r
+ (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \\r
+ (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \\r
+ (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) )\r
+/**\r
+ \brief LDR Exclusive (8 bit)\r
+ \details Executes a exclusive LDR instruction for 8 bit value.\r
+ \param [in] ptr Pointer to data\r
+ \return value of type uint8_t at (*ptr)\r
+ */\r
+#define __LDREXB (uint8_t)__builtin_arm_ldrex\r
+\r
+\r
+/**\r
+ \brief LDR Exclusive (16 bit)\r
+ \details Executes a exclusive LDR instruction for 16 bit values.\r
+ \param [in] ptr Pointer to data\r
+ \return value of type uint16_t at (*ptr)\r
+ */\r
+#define __LDREXH (uint16_t)__builtin_arm_ldrex\r
+\r
+\r
+/**\r
+ \brief LDR Exclusive (32 bit)\r
+ \details Executes a exclusive LDR instruction for 32 bit values.\r
+ \param [in] ptr Pointer to data\r
+ \return value of type uint32_t at (*ptr)\r
+ */\r
+#define __LDREXW (uint32_t)__builtin_arm_ldrex\r
+\r
+\r
+/**\r
+ \brief STR Exclusive (8 bit)\r
+ \details Executes a exclusive STR instruction for 8 bit values.\r
+ \param [in] value Value to store\r
+ \param [in] ptr Pointer to location\r
+ \return 0 Function succeeded\r
+ \return 1 Function failed\r
+ */\r
+#define __STREXB (uint32_t)__builtin_arm_strex\r
+\r
+\r
+/**\r
+ \brief STR Exclusive (16 bit)\r
+ \details Executes a exclusive STR instruction for 16 bit values.\r
+ \param [in] value Value to store\r
+ \param [in] ptr Pointer to location\r
+ \return 0 Function succeeded\r
+ \return 1 Function failed\r
+ */\r
+#define __STREXH (uint32_t)__builtin_arm_strex\r
+\r
+\r
+/**\r
+ \brief STR Exclusive (32 bit)\r
+ \details Executes a exclusive STR instruction for 32 bit values.\r
+ \param [in] value Value to store\r
+ \param [in] ptr Pointer to location\r
+ \return 0 Function succeeded\r
+ \return 1 Function failed\r
+ */\r
+#define __STREXW (uint32_t)__builtin_arm_strex\r
+\r
+\r
+/**\r
+ \brief Remove the exclusive lock\r
+ \details Removes the exclusive lock which is created by LDREX.\r
+ */\r
+#define __CLREX __builtin_arm_clrex\r
+\r
+#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \\r
+ (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \\r
+ (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \\r
+ (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) */\r
+\r
+\r
+#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \\r
+ (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \\r
+ (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) )\r
+\r
+/**\r
+ \brief Signed Saturate\r
+ \details Saturates a signed value.\r
+ \param [in] value Value to be saturated\r
+ \param [in] sat Bit position to saturate to (1..32)\r
+ \return Saturated value\r
+ */\r
+#define __SSAT __builtin_arm_ssat\r
+\r
+\r
+/**\r
+ \brief Unsigned Saturate\r
+ \details Saturates an unsigned value.\r
+ \param [in] value Value to be saturated\r
+ \param [in] sat Bit position to saturate to (0..31)\r
+ \return Saturated value\r
+ */\r
+#define __USAT __builtin_arm_usat\r
+\r
+\r
+/**\r
+ \brief Rotate Right with Extend (32 bit)\r
+ \details Moves each bit of a bitstring right by one bit.\r
+ The carry input is shifted in at the left end of the bitstring.\r
+ \param [in] value Value to rotate\r
+ \return Rotated value\r
+ */\r
+__STATIC_FORCEINLINE uint32_t __RRX(uint32_t value)\r
+{\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("rrx %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) );\r
+ return(result);\r
+}\r
+\r
+\r
+/**\r
+ \brief LDRT Unprivileged (8 bit)\r
+ \details Executes a Unprivileged LDRT instruction for 8 bit value.\r
+ \param [in] ptr Pointer to data\r
+ \return value of type uint8_t at (*ptr)\r
+ */\r
+__STATIC_FORCEINLINE uint8_t __LDRBT(volatile uint8_t *ptr)\r
+{\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("ldrbt %0, %1" : "=r" (result) : "Q" (*ptr) );\r
+ return ((uint8_t) result); /* Add explicit type cast here */\r
+}\r
+\r
+\r
+/**\r
+ \brief LDRT Unprivileged (16 bit)\r
+ \details Executes a Unprivileged LDRT instruction for 16 bit values.\r
+ \param [in] ptr Pointer to data\r
+ \return value of type uint16_t at (*ptr)\r
+ */\r
+__STATIC_FORCEINLINE uint16_t __LDRHT(volatile uint16_t *ptr)\r
+{\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("ldrht %0, %1" : "=r" (result) : "Q" (*ptr) );\r
+ return ((uint16_t) result); /* Add explicit type cast here */\r
+}\r
+\r
+\r
+/**\r
+ \brief LDRT Unprivileged (32 bit)\r
+ \details Executes a Unprivileged LDRT instruction for 32 bit values.\r
+ \param [in] ptr Pointer to data\r
+ \return value of type uint32_t at (*ptr)\r
+ */\r
+__STATIC_FORCEINLINE uint32_t __LDRT(volatile uint32_t *ptr)\r
+{\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("ldrt %0, %1" : "=r" (result) : "Q" (*ptr) );\r
+ return(result);\r
+}\r
+\r
+\r
+/**\r
+ \brief STRT Unprivileged (8 bit)\r
+ \details Executes a Unprivileged STRT instruction for 8 bit values.\r
+ \param [in] value Value to store\r
+ \param [in] ptr Pointer to location\r
+ */\r
+__STATIC_FORCEINLINE void __STRBT(uint8_t value, volatile uint8_t *ptr)\r
+{\r
+ __ASM volatile ("strbt %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) );\r
+}\r
+\r
+\r
+/**\r
+ \brief STRT Unprivileged (16 bit)\r
+ \details Executes a Unprivileged STRT instruction for 16 bit values.\r
+ \param [in] value Value to store\r
+ \param [in] ptr Pointer to location\r
+ */\r
+__STATIC_FORCEINLINE void __STRHT(uint16_t value, volatile uint16_t *ptr)\r
+{\r
+ __ASM volatile ("strht %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) );\r
+}\r
+\r
+\r
+/**\r
+ \brief STRT Unprivileged (32 bit)\r
+ \details Executes a Unprivileged STRT instruction for 32 bit values.\r
+ \param [in] value Value to store\r
+ \param [in] ptr Pointer to location\r
+ */\r
+__STATIC_FORCEINLINE void __STRT(uint32_t value, volatile uint32_t *ptr)\r
+{\r
+ __ASM volatile ("strt %1, %0" : "=Q" (*ptr) : "r" (value) );\r
+}\r
+\r
+#else /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \\r
+ (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \\r
+ (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) */\r
+\r
+/**\r
+ \brief Signed Saturate\r
+ \details Saturates a signed value.\r
+ \param [in] value Value to be saturated\r
+ \param [in] sat Bit position to saturate to (1..32)\r
+ \return Saturated value\r
+ */\r
+__STATIC_FORCEINLINE int32_t __SSAT(int32_t val, uint32_t sat)\r
+{\r
+ if ((sat >= 1U) && (sat <= 32U))\r
+ {\r
+ const int32_t max = (int32_t)((1U << (sat - 1U)) - 1U);\r
+ const int32_t min = -1 - max ;\r
+ if (val > max)\r
+ {\r
+ return max;\r
+ }\r
+ else if (val < min)\r
+ {\r
+ return min;\r
+ }\r
+ }\r
+ return val;\r
+}\r
+\r
+/**\r
+ \brief Unsigned Saturate\r
+ \details Saturates an unsigned value.\r
+ \param [in] value Value to be saturated\r
+ \param [in] sat Bit position to saturate to (0..31)\r
+ \return Saturated value\r
+ */\r
+__STATIC_FORCEINLINE uint32_t __USAT(int32_t val, uint32_t sat)\r
+{\r
+ if (sat <= 31U)\r
+ {\r
+ const uint32_t max = ((1U << sat) - 1U);\r
+ if (val > (int32_t)max)\r
+ {\r
+ return max;\r
+ }\r
+ else if (val < 0)\r
+ {\r
+ return 0U;\r
+ }\r
+ }\r
+ return (uint32_t)val;\r
+}\r
+\r
+#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \\r
+ (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \\r
+ (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) */\r
+\r
+\r
+#if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \\r
+ (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) )\r
+/**\r
+ \brief Load-Acquire (8 bit)\r
+ \details Executes a LDAB instruction for 8 bit value.\r
+ \param [in] ptr Pointer to data\r
+ \return value of type uint8_t at (*ptr)\r
+ */\r
+__STATIC_FORCEINLINE uint8_t __LDAB(volatile uint8_t *ptr)\r
+{\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("ldab %0, %1" : "=r" (result) : "Q" (*ptr) );\r
+ return ((uint8_t) result);\r
+}\r
+\r
+\r
+/**\r
+ \brief Load-Acquire (16 bit)\r
+ \details Executes a LDAH instruction for 16 bit values.\r
+ \param [in] ptr Pointer to data\r
+ \return value of type uint16_t at (*ptr)\r
+ */\r
+__STATIC_FORCEINLINE uint16_t __LDAH(volatile uint16_t *ptr)\r
+{\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("ldah %0, %1" : "=r" (result) : "Q" (*ptr) );\r
+ return ((uint16_t) result);\r
+}\r
+\r
+\r
+/**\r
+ \brief Load-Acquire (32 bit)\r
+ \details Executes a LDA instruction for 32 bit values.\r
+ \param [in] ptr Pointer to data\r
+ \return value of type uint32_t at (*ptr)\r
+ */\r
+__STATIC_FORCEINLINE uint32_t __LDA(volatile uint32_t *ptr)\r
+{\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("lda %0, %1" : "=r" (result) : "Q" (*ptr) );\r
+ return(result);\r
+}\r
+\r
+\r
+/**\r
+ \brief Store-Release (8 bit)\r
+ \details Executes a STLB instruction for 8 bit values.\r
+ \param [in] value Value to store\r
+ \param [in] ptr Pointer to location\r
+ */\r
+__STATIC_FORCEINLINE void __STLB(uint8_t value, volatile uint8_t *ptr)\r
+{\r
+ __ASM volatile ("stlb %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) );\r
+}\r
+\r
+\r
+/**\r
+ \brief Store-Release (16 bit)\r
+ \details Executes a STLH instruction for 16 bit values.\r
+ \param [in] value Value to store\r
+ \param [in] ptr Pointer to location\r
+ */\r
+__STATIC_FORCEINLINE void __STLH(uint16_t value, volatile uint16_t *ptr)\r
+{\r
+ __ASM volatile ("stlh %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) );\r
+}\r
+\r
+\r
+/**\r
+ \brief Store-Release (32 bit)\r
+ \details Executes a STL instruction for 32 bit values.\r
+ \param [in] value Value to store\r
+ \param [in] ptr Pointer to location\r
+ */\r
+__STATIC_FORCEINLINE void __STL(uint32_t value, volatile uint32_t *ptr)\r
+{\r
+ __ASM volatile ("stl %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) );\r
+}\r
+\r
+\r
+/**\r
+ \brief Load-Acquire Exclusive (8 bit)\r
+ \details Executes a LDAB exclusive instruction for 8 bit value.\r
+ \param [in] ptr Pointer to data\r
+ \return value of type uint8_t at (*ptr)\r
+ */\r
+#define __LDAEXB (uint8_t)__builtin_arm_ldaex\r
+\r
+\r
+/**\r
+ \brief Load-Acquire Exclusive (16 bit)\r
+ \details Executes a LDAH exclusive instruction for 16 bit values.\r
+ \param [in] ptr Pointer to data\r
+ \return value of type uint16_t at (*ptr)\r
+ */\r
+#define __LDAEXH (uint16_t)__builtin_arm_ldaex\r
+\r
+\r
+/**\r
+ \brief Load-Acquire Exclusive (32 bit)\r
+ \details Executes a LDA exclusive instruction for 32 bit values.\r
+ \param [in] ptr Pointer to data\r
+ \return value of type uint32_t at (*ptr)\r
+ */\r
+#define __LDAEX (uint32_t)__builtin_arm_ldaex\r
+\r
+\r
+/**\r
+ \brief Store-Release Exclusive (8 bit)\r
+ \details Executes a STLB exclusive instruction for 8 bit values.\r
+ \param [in] value Value to store\r
+ \param [in] ptr Pointer to location\r
+ \return 0 Function succeeded\r
+ \return 1 Function failed\r
+ */\r
+#define __STLEXB (uint32_t)__builtin_arm_stlex\r
+\r
+\r
+/**\r
+ \brief Store-Release Exclusive (16 bit)\r
+ \details Executes a STLH exclusive instruction for 16 bit values.\r
+ \param [in] value Value to store\r
+ \param [in] ptr Pointer to location\r
+ \return 0 Function succeeded\r
+ \return 1 Function failed\r
+ */\r
+#define __STLEXH (uint32_t)__builtin_arm_stlex\r
+\r
+\r
+/**\r
+ \brief Store-Release Exclusive (32 bit)\r
+ \details Executes a STL exclusive instruction for 32 bit values.\r
+ \param [in] value Value to store\r
+ \param [in] ptr Pointer to location\r
+ \return 0 Function succeeded\r
+ \return 1 Function failed\r
+ */\r
+#define __STLEX (uint32_t)__builtin_arm_stlex\r
+\r
+#endif /* ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \\r
+ (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) */\r
+\r
+/*@}*/ /* end of group CMSIS_Core_InstructionInterface */\r
+\r
+\r
+/* ################### Compiler specific Intrinsics ########################### */\r
+/** \defgroup CMSIS_SIMD_intrinsics CMSIS SIMD Intrinsics\r
+ Access to dedicated SIMD instructions\r
+ @{\r
+*/\r
+\r
+#if (defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1))\r
+\r
+__STATIC_FORCEINLINE uint32_t __SADD8(uint32_t op1, uint32_t op2)\r
+{\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("sadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );\r
+ return(result);\r
+}\r
+\r
+__STATIC_FORCEINLINE uint32_t __QADD8(uint32_t op1, uint32_t op2)\r
+{\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("qadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );\r
+ return(result);\r
+}\r
+\r
+__STATIC_FORCEINLINE uint32_t __SHADD8(uint32_t op1, uint32_t op2)\r
+{\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("shadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );\r
+ return(result);\r
+}\r
+\r
+__STATIC_FORCEINLINE uint32_t __UADD8(uint32_t op1, uint32_t op2)\r
+{\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("uadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );\r
+ return(result);\r
+}\r
+\r
+__STATIC_FORCEINLINE uint32_t __UQADD8(uint32_t op1, uint32_t op2)\r
+{\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("uqadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );\r
+ return(result);\r
+}\r
+\r
+__STATIC_FORCEINLINE uint32_t __UHADD8(uint32_t op1, uint32_t op2)\r
+{\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("uhadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );\r
+ return(result);\r
+}\r
+\r
+\r
+__STATIC_FORCEINLINE uint32_t __SSUB8(uint32_t op1, uint32_t op2)\r
+{\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("ssub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );\r
+ return(result);\r
+}\r
+\r
+__STATIC_FORCEINLINE uint32_t __QSUB8(uint32_t op1, uint32_t op2)\r
+{\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("qsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );\r
+ return(result);\r
+}\r
+\r
+__STATIC_FORCEINLINE uint32_t __SHSUB8(uint32_t op1, uint32_t op2)\r
+{\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("shsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );\r
+ return(result);\r
+}\r
+\r
+__STATIC_FORCEINLINE uint32_t __USUB8(uint32_t op1, uint32_t op2)\r
+{\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("usub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );\r
+ return(result);\r
+}\r
+\r
+__STATIC_FORCEINLINE uint32_t __UQSUB8(uint32_t op1, uint32_t op2)\r
+{\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("uqsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );\r
+ return(result);\r
+}\r
+\r
+__STATIC_FORCEINLINE uint32_t __UHSUB8(uint32_t op1, uint32_t op2)\r
+{\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("uhsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );\r
+ return(result);\r
+}\r
+\r
+\r
+__STATIC_FORCEINLINE uint32_t __SADD16(uint32_t op1, uint32_t op2)\r
+{\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("sadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );\r
+ return(result);\r
+}\r
+\r
+__STATIC_FORCEINLINE uint32_t __QADD16(uint32_t op1, uint32_t op2)\r
+{\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("qadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );\r
+ return(result);\r
+}\r
+\r
+__STATIC_FORCEINLINE uint32_t __SHADD16(uint32_t op1, uint32_t op2)\r
+{\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("shadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );\r
+ return(result);\r
+}\r
+\r
+__STATIC_FORCEINLINE uint32_t __UADD16(uint32_t op1, uint32_t op2)\r
+{\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("uadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );\r
+ return(result);\r
+}\r
+\r
+__STATIC_FORCEINLINE uint32_t __UQADD16(uint32_t op1, uint32_t op2)\r
+{\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("uqadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );\r
+ return(result);\r
+}\r
+\r
+__STATIC_FORCEINLINE uint32_t __UHADD16(uint32_t op1, uint32_t op2)\r
+{\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("uhadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );\r
+ return(result);\r
+}\r
+\r
+__STATIC_FORCEINLINE uint32_t __SSUB16(uint32_t op1, uint32_t op2)\r
+{\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("ssub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );\r
+ return(result);\r
+}\r
+\r
+__STATIC_FORCEINLINE uint32_t __QSUB16(uint32_t op1, uint32_t op2)\r
+{\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("qsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );\r
+ return(result);\r
+}\r
+\r
+__STATIC_FORCEINLINE uint32_t __SHSUB16(uint32_t op1, uint32_t op2)\r
+{\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("shsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );\r
+ return(result);\r
+}\r
+\r
+__STATIC_FORCEINLINE uint32_t __USUB16(uint32_t op1, uint32_t op2)\r
+{\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("usub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );\r
+ return(result);\r
+}\r
+\r
+__STATIC_FORCEINLINE uint32_t __UQSUB16(uint32_t op1, uint32_t op2)\r
+{\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("uqsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );\r
+ return(result);\r
+}\r
+\r
+__STATIC_FORCEINLINE uint32_t __UHSUB16(uint32_t op1, uint32_t op2)\r
+{\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("uhsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );\r
+ return(result);\r
+}\r
+\r
+__STATIC_FORCEINLINE uint32_t __SASX(uint32_t op1, uint32_t op2)\r
+{\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("sasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );\r
+ return(result);\r
+}\r
+\r
+__STATIC_FORCEINLINE uint32_t __QASX(uint32_t op1, uint32_t op2)\r
+{\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("qasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );\r
+ return(result);\r
+}\r
+\r
+__STATIC_FORCEINLINE uint32_t __SHASX(uint32_t op1, uint32_t op2)\r
+{\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("shasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );\r
+ return(result);\r
+}\r
+\r
+__STATIC_FORCEINLINE uint32_t __UASX(uint32_t op1, uint32_t op2)\r
+{\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("uasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );\r
+ return(result);\r
+}\r
+\r
+__STATIC_FORCEINLINE uint32_t __UQASX(uint32_t op1, uint32_t op2)\r
+{\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("uqasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );\r
+ return(result);\r
+}\r
+\r
+__STATIC_FORCEINLINE uint32_t __UHASX(uint32_t op1, uint32_t op2)\r
+{\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("uhasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );\r
+ return(result);\r
+}\r
+\r
+__STATIC_FORCEINLINE uint32_t __SSAX(uint32_t op1, uint32_t op2)\r
+{\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("ssax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );\r
+ return(result);\r
+}\r
+\r
+__STATIC_FORCEINLINE uint32_t __QSAX(uint32_t op1, uint32_t op2)\r
+{\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("qsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );\r
+ return(result);\r
+}\r
+\r
+__STATIC_FORCEINLINE uint32_t __SHSAX(uint32_t op1, uint32_t op2)\r
+{\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("shsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );\r
+ return(result);\r
+}\r
+\r
+__STATIC_FORCEINLINE uint32_t __USAX(uint32_t op1, uint32_t op2)\r
+{\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("usax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );\r
+ return(result);\r
+}\r
+\r
+__STATIC_FORCEINLINE uint32_t __UQSAX(uint32_t op1, uint32_t op2)\r
+{\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("uqsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );\r
+ return(result);\r
+}\r
+\r
+__STATIC_FORCEINLINE uint32_t __UHSAX(uint32_t op1, uint32_t op2)\r
+{\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("uhsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );\r
+ return(result);\r
+}\r
+\r
+__STATIC_FORCEINLINE uint32_t __USAD8(uint32_t op1, uint32_t op2)\r
+{\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("usad8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );\r
+ return(result);\r
+}\r
+\r
+__STATIC_FORCEINLINE uint32_t __USADA8(uint32_t op1, uint32_t op2, uint32_t op3)\r
+{\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("usada8 %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );\r
+ return(result);\r
+}\r
+\r
+#define __SSAT16(ARG1,ARG2) \\r
+({ \\r
+ int32_t __RES, __ARG1 = (ARG1); \\r
+ __ASM ("ssat16 %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \\r
+ __RES; \\r
+ })\r
+\r
+#define __USAT16(ARG1,ARG2) \\r
+({ \\r
+ uint32_t __RES, __ARG1 = (ARG1); \\r
+ __ASM ("usat16 %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \\r
+ __RES; \\r
+ })\r
+\r
+__STATIC_FORCEINLINE uint32_t __UXTB16(uint32_t op1)\r
+{\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("uxtb16 %0, %1" : "=r" (result) : "r" (op1));\r
+ return(result);\r
+}\r
+\r
+__STATIC_FORCEINLINE uint32_t __UXTAB16(uint32_t op1, uint32_t op2)\r
+{\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("uxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );\r
+ return(result);\r
+}\r
+\r
+__STATIC_FORCEINLINE uint32_t __SXTB16(uint32_t op1)\r
+{\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("sxtb16 %0, %1" : "=r" (result) : "r" (op1));\r
+ return(result);\r
+}\r
+\r
+__STATIC_FORCEINLINE uint32_t __SXTAB16(uint32_t op1, uint32_t op2)\r
+{\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("sxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );\r
+ return(result);\r
+}\r
+\r
+__STATIC_FORCEINLINE uint32_t __SMUAD (uint32_t op1, uint32_t op2)\r
+{\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("smuad %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );\r
+ return(result);\r
+}\r
+\r
+__STATIC_FORCEINLINE uint32_t __SMUADX (uint32_t op1, uint32_t op2)\r
+{\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("smuadx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );\r
+ return(result);\r
+}\r
+\r
+__STATIC_FORCEINLINE uint32_t __SMLAD (uint32_t op1, uint32_t op2, uint32_t op3)\r
+{\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("smlad %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );\r
+ return(result);\r
+}\r
+\r
+__STATIC_FORCEINLINE uint32_t __SMLADX (uint32_t op1, uint32_t op2, uint32_t op3)\r
+{\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("smladx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );\r
+ return(result);\r
+}\r
+\r
+__STATIC_FORCEINLINE uint64_t __SMLALD (uint32_t op1, uint32_t op2, uint64_t acc)\r
+{\r
+ union llreg_u{\r
+ uint32_t w32[2];\r
+ uint64_t w64;\r
+ } llr;\r
+ llr.w64 = acc;\r
+\r
+#ifndef __ARMEB__ /* Little endian */\r
+ __ASM volatile ("smlald %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) );\r
+#else /* Big endian */\r
+ __ASM volatile ("smlald %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) );\r
+#endif\r
+\r
+ return(llr.w64);\r
+}\r
+\r
+__STATIC_FORCEINLINE uint64_t __SMLALDX (uint32_t op1, uint32_t op2, uint64_t acc)\r
+{\r
+ union llreg_u{\r
+ uint32_t w32[2];\r
+ uint64_t w64;\r
+ } llr;\r
+ llr.w64 = acc;\r
+\r
+#ifndef __ARMEB__ /* Little endian */\r
+ __ASM volatile ("smlaldx %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) );\r
+#else /* Big endian */\r
+ __ASM volatile ("smlaldx %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) );\r
+#endif\r
+\r
+ return(llr.w64);\r
+}\r
+\r
+__STATIC_FORCEINLINE uint32_t __SMUSD (uint32_t op1, uint32_t op2)\r
+{\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("smusd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );\r
+ return(result);\r
+}\r
+\r
+__STATIC_FORCEINLINE uint32_t __SMUSDX (uint32_t op1, uint32_t op2)\r
+{\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("smusdx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );\r
+ return(result);\r
+}\r
+\r
+__STATIC_FORCEINLINE uint32_t __SMLSD (uint32_t op1, uint32_t op2, uint32_t op3)\r
+{\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("smlsd %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );\r
+ return(result);\r
+}\r
+\r
+__STATIC_FORCEINLINE uint32_t __SMLSDX (uint32_t op1, uint32_t op2, uint32_t op3)\r
+{\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("smlsdx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );\r
+ return(result);\r
+}\r
+\r
+__STATIC_FORCEINLINE uint64_t __SMLSLD (uint32_t op1, uint32_t op2, uint64_t acc)\r
+{\r
+ union llreg_u{\r
+ uint32_t w32[2];\r
+ uint64_t w64;\r
+ } llr;\r
+ llr.w64 = acc;\r
+\r
+#ifndef __ARMEB__ /* Little endian */\r
+ __ASM volatile ("smlsld %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) );\r
+#else /* Big endian */\r
+ __ASM volatile ("smlsld %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) );\r
+#endif\r
+\r
+ return(llr.w64);\r
+}\r
+\r
+__STATIC_FORCEINLINE uint64_t __SMLSLDX (uint32_t op1, uint32_t op2, uint64_t acc)\r
+{\r
+ union llreg_u{\r
+ uint32_t w32[2];\r
+ uint64_t w64;\r
+ } llr;\r
+ llr.w64 = acc;\r
+\r
+#ifndef __ARMEB__ /* Little endian */\r
+ __ASM volatile ("smlsldx %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) );\r
+#else /* Big endian */\r
+ __ASM volatile ("smlsldx %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) );\r
+#endif\r
+\r
+ return(llr.w64);\r
+}\r
+\r
+__STATIC_FORCEINLINE uint32_t __SEL (uint32_t op1, uint32_t op2)\r
+{\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("sel %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );\r
+ return(result);\r
+}\r
+\r
+__STATIC_FORCEINLINE int32_t __QADD( int32_t op1, int32_t op2)\r
+{\r
+ int32_t result;\r
+\r
+ __ASM volatile ("qadd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );\r
+ return(result);\r
+}\r
+\r
+__STATIC_FORCEINLINE int32_t __QSUB( int32_t op1, int32_t op2)\r
+{\r
+ int32_t result;\r
+\r
+ __ASM volatile ("qsub %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );\r
+ return(result);\r
+}\r
+\r
+#if 0\r
+#define __PKHBT(ARG1,ARG2,ARG3) \\r
+({ \\r
+ uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \\r
+ __ASM ("pkhbt %0, %1, %2, lsl %3" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2), "I" (ARG3) ); \\r
+ __RES; \\r
+ })\r
+\r
+#define __PKHTB(ARG1,ARG2,ARG3) \\r
+({ \\r
+ uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \\r
+ if (ARG3 == 0) \\r
+ __ASM ("pkhtb %0, %1, %2" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2) ); \\r
+ else \\r
+ __ASM ("pkhtb %0, %1, %2, asr %3" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2), "I" (ARG3) ); \\r
+ __RES; \\r
+ })\r
+#endif\r
+\r
+#define __PKHBT(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0x0000FFFFUL) | \\r
+ ((((uint32_t)(ARG2)) << (ARG3)) & 0xFFFF0000UL) )\r
+\r
+#define __PKHTB(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0xFFFF0000UL) | \\r
+ ((((uint32_t)(ARG2)) >> (ARG3)) & 0x0000FFFFUL) )\r
+\r
+__STATIC_FORCEINLINE int32_t __SMMLA (int32_t op1, int32_t op2, int32_t op3)\r
+{\r
+ int32_t result;\r
+\r
+ __ASM volatile ("smmla %0, %1, %2, %3" : "=r" (result): "r" (op1), "r" (op2), "r" (op3) );\r
+ return(result);\r
+}\r
+\r
+#endif /* (__ARM_FEATURE_DSP == 1) */\r
+/*@} end of group CMSIS_SIMD_intrinsics */\r
+\r
+\r
+#endif /* __CMSIS_ARMCLANG_H */\r
--- /dev/null
+/**************************************************************************//**\r
+ * @file cmsis_compiler.h\r
+ * @brief CMSIS compiler generic header file\r
+ * @version V5.0.4\r
+ * @date 10. January 2018\r
+ ******************************************************************************/\r
+/*\r
+ * Copyright (c) 2009-2018 Arm Limited. All rights reserved.\r
+ *\r
+ * SPDX-License-Identifier: Apache-2.0\r
+ *\r
+ * Licensed under the Apache License, Version 2.0 (the License); you may\r
+ * not use this file except in compliance with the License.\r
+ * You may obtain a copy of the License at\r
+ *\r
+ * www.apache.org/licenses/LICENSE-2.0\r
+ *\r
+ * Unless required by applicable law or agreed to in writing, software\r
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT\r
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\r
+ * See the License for the specific language governing permissions and\r
+ * limitations under the License.\r
+ */\r
+\r
+#ifndef __CMSIS_COMPILER_H\r
+#define __CMSIS_COMPILER_H\r
+\r
+#include <stdint.h>\r
+\r
+/*\r
+ * Arm Compiler 4/5\r
+ */\r
+#if defined ( __CC_ARM )\r
+ #include "cmsis_armcc.h"\r
+\r
+\r
+/*\r
+ * Arm Compiler 6 (armclang)\r
+ */\r
+#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)\r
+ #include "cmsis_armclang.h"\r
+\r
+\r
+/*\r
+ * GNU Compiler\r
+ */\r
+#elif defined ( __GNUC__ )\r
+ #include "cmsis_gcc.h"\r
+\r
+\r
+/*\r
+ * IAR Compiler\r
+ */\r
+#elif defined ( __ICCARM__ )\r
+ #include <cmsis_iccarm.h>\r
+\r
+\r
+/*\r
+ * TI Arm Compiler\r
+ */\r
+#elif defined ( __TI_ARM__ )\r
+ #include <cmsis_ccs.h>\r
+\r
+ #ifndef __ASM\r
+ #define __ASM __asm\r
+ #endif\r
+ #ifndef __INLINE\r
+ #define __INLINE inline\r
+ #endif\r
+ #ifndef __STATIC_INLINE\r
+ #define __STATIC_INLINE static inline\r
+ #endif\r
+ #ifndef __STATIC_FORCEINLINE\r
+ #define __STATIC_FORCEINLINE __STATIC_INLINE\r
+ #endif\r
+ #ifndef __NO_RETURN\r
+ #define __NO_RETURN __attribute__((noreturn))\r
+ #endif\r
+ #ifndef __USED\r
+ #define __USED __attribute__((used))\r
+ #endif\r
+ #ifndef __WEAK\r
+ #define __WEAK __attribute__((weak))\r
+ #endif\r
+ #ifndef __PACKED\r
+ #define __PACKED __attribute__((packed))\r
+ #endif\r
+ #ifndef __PACKED_STRUCT\r
+ #define __PACKED_STRUCT struct __attribute__((packed))\r
+ #endif\r
+ #ifndef __PACKED_UNION\r
+ #define __PACKED_UNION union __attribute__((packed))\r
+ #endif\r
+ #ifndef __UNALIGNED_UINT32 /* deprecated */\r
+ struct __attribute__((packed)) T_UINT32 { uint32_t v; };\r
+ #define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v)\r
+ #endif\r
+ #ifndef __UNALIGNED_UINT16_WRITE\r
+ __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; };\r
+ #define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void*)(addr))->v) = (val))\r
+ #endif\r
+ #ifndef __UNALIGNED_UINT16_READ\r
+ __PACKED_STRUCT T_UINT16_READ { uint16_t v; };\r
+ #define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v)\r
+ #endif\r
+ #ifndef __UNALIGNED_UINT32_WRITE\r
+ __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; };\r
+ #define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val))\r
+ #endif\r
+ #ifndef __UNALIGNED_UINT32_READ\r
+ __PACKED_STRUCT T_UINT32_READ { uint32_t v; };\r
+ #define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v)\r
+ #endif\r
+ #ifndef __ALIGNED\r
+ #define __ALIGNED(x) __attribute__((aligned(x)))\r
+ #endif\r
+ #ifndef __RESTRICT\r
+ #warning No compiler specific solution for __RESTRICT. __RESTRICT is ignored.\r
+ #define __RESTRICT\r
+ #endif\r
+\r
+\r
+/*\r
+ * TASKING Compiler\r
+ */\r
+#elif defined ( __TASKING__ )\r
+ /*\r
+ * The CMSIS functions have been implemented as intrinsics in the compiler.\r
+ * Please use "carm -?i" to get an up to date list of all intrinsics,\r
+ * Including the CMSIS ones.\r
+ */\r
+\r
+ #ifndef __ASM\r
+ #define __ASM __asm\r
+ #endif\r
+ #ifndef __INLINE\r
+ #define __INLINE inline\r
+ #endif\r
+ #ifndef __STATIC_INLINE\r
+ #define __STATIC_INLINE static inline\r
+ #endif\r
+ #ifndef __STATIC_FORCEINLINE\r
+ #define __STATIC_FORCEINLINE __STATIC_INLINE\r
+ #endif\r
+ #ifndef __NO_RETURN\r
+ #define __NO_RETURN __attribute__((noreturn))\r
+ #endif\r
+ #ifndef __USED\r
+ #define __USED __attribute__((used))\r
+ #endif\r
+ #ifndef __WEAK\r
+ #define __WEAK __attribute__((weak))\r
+ #endif\r
+ #ifndef __PACKED\r
+ #define __PACKED __packed__\r
+ #endif\r
+ #ifndef __PACKED_STRUCT\r
+ #define __PACKED_STRUCT struct __packed__\r
+ #endif\r
+ #ifndef __PACKED_UNION\r
+ #define __PACKED_UNION union __packed__\r
+ #endif\r
+ #ifndef __UNALIGNED_UINT32 /* deprecated */\r
+ struct __packed__ T_UINT32 { uint32_t v; };\r
+ #define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v)\r
+ #endif\r
+ #ifndef __UNALIGNED_UINT16_WRITE\r
+ __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; };\r
+ #define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val))\r
+ #endif\r
+ #ifndef __UNALIGNED_UINT16_READ\r
+ __PACKED_STRUCT T_UINT16_READ { uint16_t v; };\r
+ #define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v)\r
+ #endif\r
+ #ifndef __UNALIGNED_UINT32_WRITE\r
+ __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; };\r
+ #define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val))\r
+ #endif\r
+ #ifndef __UNALIGNED_UINT32_READ\r
+ __PACKED_STRUCT T_UINT32_READ { uint32_t v; };\r
+ #define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v)\r
+ #endif\r
+ #ifndef __ALIGNED\r
+ #define __ALIGNED(x) __align(x)\r
+ #endif\r
+ #ifndef __RESTRICT\r
+ #warning No compiler specific solution for __RESTRICT. __RESTRICT is ignored.\r
+ #define __RESTRICT\r
+ #endif\r
+\r
+\r
+/*\r
+ * COSMIC Compiler\r
+ */\r
+#elif defined ( __CSMC__ )\r
+ #include <cmsis_csm.h>\r
+\r
+ #ifndef __ASM\r
+ #define __ASM _asm\r
+ #endif\r
+ #ifndef __INLINE\r
+ #define __INLINE inline\r
+ #endif\r
+ #ifndef __STATIC_INLINE\r
+ #define __STATIC_INLINE static inline\r
+ #endif\r
+ #ifndef __STATIC_FORCEINLINE\r
+ #define __STATIC_FORCEINLINE __STATIC_INLINE\r
+ #endif\r
+ #ifndef __NO_RETURN\r
+ // NO RETURN is automatically detected hence no warning here\r
+ #define __NO_RETURN\r
+ #endif\r
+ #ifndef __USED\r
+ #warning No compiler specific solution for __USED. __USED is ignored.\r
+ #define __USED\r
+ #endif\r
+ #ifndef __WEAK\r
+ #define __WEAK __weak\r
+ #endif\r
+ #ifndef __PACKED\r
+ #define __PACKED @packed\r
+ #endif\r
+ #ifndef __PACKED_STRUCT\r
+ #define __PACKED_STRUCT @packed struct\r
+ #endif\r
+ #ifndef __PACKED_UNION\r
+ #define __PACKED_UNION @packed union\r
+ #endif\r
+ #ifndef __UNALIGNED_UINT32 /* deprecated */\r
+ @packed struct T_UINT32 { uint32_t v; };\r
+ #define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v)\r
+ #endif\r
+ #ifndef __UNALIGNED_UINT16_WRITE\r
+ __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; };\r
+ #define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val))\r
+ #endif\r
+ #ifndef __UNALIGNED_UINT16_READ\r
+ __PACKED_STRUCT T_UINT16_READ { uint16_t v; };\r
+ #define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v)\r
+ #endif\r
+ #ifndef __UNALIGNED_UINT32_WRITE\r
+ __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; };\r
+ #define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val))\r
+ #endif\r
+ #ifndef __UNALIGNED_UINT32_READ\r
+ __PACKED_STRUCT T_UINT32_READ { uint32_t v; };\r
+ #define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v)\r
+ #endif\r
+ #ifndef __ALIGNED\r
+ #warning No compiler specific solution for __ALIGNED. __ALIGNED is ignored.\r
+ #define __ALIGNED(x)\r
+ #endif\r
+ #ifndef __RESTRICT\r
+ #warning No compiler specific solution for __RESTRICT. __RESTRICT is ignored.\r
+ #define __RESTRICT\r
+ #endif\r
+\r
+\r
+#else\r
+ #error Unknown compiler.\r
+#endif\r
+\r
+\r
+#endif /* __CMSIS_COMPILER_H */\r
+\r
--- /dev/null
+/**************************************************************************//**\r
+ * @file cmsis_gcc.h\r
+ * @brief CMSIS compiler GCC header file\r
+ * @version V5.0.4\r
+ * @date 09. April 2018\r
+ ******************************************************************************/\r
+/*\r
+ * Copyright (c) 2009-2018 Arm Limited. All rights reserved.\r
+ *\r
+ * SPDX-License-Identifier: Apache-2.0\r
+ *\r
+ * Licensed under the Apache License, Version 2.0 (the License); you may\r
+ * not use this file except in compliance with the License.\r
+ * You may obtain a copy of the License at\r
+ *\r
+ * www.apache.org/licenses/LICENSE-2.0\r
+ *\r
+ * Unless required by applicable law or agreed to in writing, software\r
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT\r
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\r
+ * See the License for the specific language governing permissions and\r
+ * limitations under the License.\r
+ */\r
+\r
+#ifndef __CMSIS_GCC_H\r
+#define __CMSIS_GCC_H\r
+\r
+/* ignore some GCC warnings */\r
+#pragma GCC diagnostic push\r
+#pragma GCC diagnostic ignored "-Wsign-conversion"\r
+#pragma GCC diagnostic ignored "-Wconversion"\r
+#pragma GCC diagnostic ignored "-Wunused-parameter"\r
+\r
+/* Fallback for __has_builtin */\r
+#ifndef __has_builtin\r
+ #define __has_builtin(x) (0)\r
+#endif\r
+\r
+/* CMSIS compiler specific defines */\r
+#ifndef __ASM\r
+ #define __ASM __asm\r
+#endif\r
+#ifndef __INLINE\r
+ #define __INLINE inline\r
+#endif\r
+#ifndef __STATIC_INLINE\r
+ #define __STATIC_INLINE static inline\r
+#endif\r
+#ifndef __STATIC_FORCEINLINE \r
+ #define __STATIC_FORCEINLINE __attribute__((always_inline)) static inline\r
+#endif \r
+#ifndef __NO_RETURN\r
+ #define __NO_RETURN __attribute__((__noreturn__))\r
+#endif\r
+#ifndef __USED\r
+ #define __USED __attribute__((used))\r
+#endif\r
+#ifndef __WEAK\r
+ #define __WEAK __attribute__((weak))\r
+#endif\r
+#ifndef __PACKED\r
+ #define __PACKED __attribute__((packed, aligned(1)))\r
+#endif\r
+#ifndef __PACKED_STRUCT\r
+ #define __PACKED_STRUCT struct __attribute__((packed, aligned(1)))\r
+#endif\r
+#ifndef __PACKED_UNION\r
+ #define __PACKED_UNION union __attribute__((packed, aligned(1)))\r
+#endif\r
+#ifndef __UNALIGNED_UINT32 /* deprecated */\r
+ #pragma GCC diagnostic push\r
+ #pragma GCC diagnostic ignored "-Wpacked"\r
+ #pragma GCC diagnostic ignored "-Wattributes"\r
+ struct __attribute__((packed)) T_UINT32 { uint32_t v; };\r
+ #pragma GCC diagnostic pop\r
+ #define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v)\r
+#endif\r
+#ifndef __UNALIGNED_UINT16_WRITE\r
+ #pragma GCC diagnostic push\r
+ #pragma GCC diagnostic ignored "-Wpacked"\r
+ #pragma GCC diagnostic ignored "-Wattributes"\r
+ __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; };\r
+ #pragma GCC diagnostic pop\r
+ #define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val))\r
+#endif\r
+#ifndef __UNALIGNED_UINT16_READ\r
+ #pragma GCC diagnostic push\r
+ #pragma GCC diagnostic ignored "-Wpacked"\r
+ #pragma GCC diagnostic ignored "-Wattributes"\r
+ __PACKED_STRUCT T_UINT16_READ { uint16_t v; };\r
+ #pragma GCC diagnostic pop\r
+ #define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v)\r
+#endif\r
+#ifndef __UNALIGNED_UINT32_WRITE\r
+ #pragma GCC diagnostic push\r
+ #pragma GCC diagnostic ignored "-Wpacked"\r
+ #pragma GCC diagnostic ignored "-Wattributes"\r
+ __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; };\r
+ #pragma GCC diagnostic pop\r
+ #define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val))\r
+#endif\r
+#ifndef __UNALIGNED_UINT32_READ\r
+ #pragma GCC diagnostic push\r
+ #pragma GCC diagnostic ignored "-Wpacked"\r
+ #pragma GCC diagnostic ignored "-Wattributes"\r
+ __PACKED_STRUCT T_UINT32_READ { uint32_t v; };\r
+ #pragma GCC diagnostic pop\r
+ #define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v)\r
+#endif\r
+#ifndef __ALIGNED\r
+ #define __ALIGNED(x) __attribute__((aligned(x)))\r
+#endif\r
+#ifndef __RESTRICT\r
+ #define __RESTRICT __restrict\r
+#endif\r
+\r
+\r
+/* ########################### Core Function Access ########################### */\r
+/** \ingroup CMSIS_Core_FunctionInterface\r
+ \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions\r
+ @{\r
+ */\r
+\r
+/**\r
+ \brief Enable IRQ Interrupts\r
+ \details Enables IRQ interrupts by clearing the I-bit in the CPSR.\r
+ Can only be executed in Privileged modes.\r
+ */\r
+__STATIC_FORCEINLINE void __enable_irq(void)\r
+{\r
+ __ASM volatile ("cpsie i" : : : "memory");\r
+}\r
+\r
+\r
+/**\r
+ \brief Disable IRQ Interrupts\r
+ \details Disables IRQ interrupts by setting the I-bit in the CPSR.\r
+ Can only be executed in Privileged modes.\r
+ */\r
+__STATIC_FORCEINLINE void __disable_irq(void)\r
+{\r
+ __ASM volatile ("cpsid i" : : : "memory");\r
+}\r
+\r
+\r
+/**\r
+ \brief Get Control Register\r
+ \details Returns the content of the Control Register.\r
+ \return Control Register value\r
+ */\r
+__STATIC_FORCEINLINE uint32_t __get_CONTROL(void)\r
+{\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("MRS %0, control" : "=r" (result) );\r
+ return(result);\r
+}\r
+\r
+\r
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))\r
+/**\r
+ \brief Get Control Register (non-secure)\r
+ \details Returns the content of the non-secure Control Register when in secure mode.\r
+ \return non-secure Control Register value\r
+ */\r
+__STATIC_FORCEINLINE uint32_t __TZ_get_CONTROL_NS(void)\r
+{\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("MRS %0, control_ns" : "=r" (result) );\r
+ return(result);\r
+}\r
+#endif\r
+\r
+\r
+/**\r
+ \brief Set Control Register\r
+ \details Writes the given value to the Control Register.\r
+ \param [in] control Control Register value to set\r
+ */\r
+__STATIC_FORCEINLINE void __set_CONTROL(uint32_t control)\r
+{\r
+ __ASM volatile ("MSR control, %0" : : "r" (control) : "memory");\r
+}\r
+\r
+\r
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))\r
+/**\r
+ \brief Set Control Register (non-secure)\r
+ \details Writes the given value to the non-secure Control Register when in secure state.\r
+ \param [in] control Control Register value to set\r
+ */\r
+__STATIC_FORCEINLINE void __TZ_set_CONTROL_NS(uint32_t control)\r
+{\r
+ __ASM volatile ("MSR control_ns, %0" : : "r" (control) : "memory");\r
+}\r
+#endif\r
+\r
+\r
+/**\r
+ \brief Get IPSR Register\r
+ \details Returns the content of the IPSR Register.\r
+ \return IPSR Register value\r
+ */\r
+__STATIC_FORCEINLINE uint32_t __get_IPSR(void)\r
+{\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("MRS %0, ipsr" : "=r" (result) );\r
+ return(result);\r
+}\r
+\r
+\r
+/**\r
+ \brief Get APSR Register\r
+ \details Returns the content of the APSR Register.\r
+ \return APSR Register value\r
+ */\r
+__STATIC_FORCEINLINE uint32_t __get_APSR(void)\r
+{\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("MRS %0, apsr" : "=r" (result) );\r
+ return(result);\r
+}\r
+\r
+\r
+/**\r
+ \brief Get xPSR Register\r
+ \details Returns the content of the xPSR Register.\r
+ \return xPSR Register value\r
+ */\r
+__STATIC_FORCEINLINE uint32_t __get_xPSR(void)\r
+{\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("MRS %0, xpsr" : "=r" (result) );\r
+ return(result);\r
+}\r
+\r
+\r
+/**\r
+ \brief Get Process Stack Pointer\r
+ \details Returns the current value of the Process Stack Pointer (PSP).\r
+ \return PSP Register value\r
+ */\r
+__STATIC_FORCEINLINE uint32_t __get_PSP(void)\r
+{\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("MRS %0, psp" : "=r" (result) );\r
+ return(result);\r
+}\r
+\r
+\r
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))\r
+/**\r
+ \brief Get Process Stack Pointer (non-secure)\r
+ \details Returns the current value of the non-secure Process Stack Pointer (PSP) when in secure state.\r
+ \return PSP Register value\r
+ */\r
+__STATIC_FORCEINLINE uint32_t __TZ_get_PSP_NS(void)\r
+{\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("MRS %0, psp_ns" : "=r" (result) );\r
+ return(result);\r
+}\r
+#endif\r
+\r
+\r
+/**\r
+ \brief Set Process Stack Pointer\r
+ \details Assigns the given value to the Process Stack Pointer (PSP).\r
+ \param [in] topOfProcStack Process Stack Pointer value to set\r
+ */\r
+__STATIC_FORCEINLINE void __set_PSP(uint32_t topOfProcStack)\r
+{\r
+ __ASM volatile ("MSR psp, %0" : : "r" (topOfProcStack) : );\r
+}\r
+\r
+\r
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))\r
+/**\r
+ \brief Set Process Stack Pointer (non-secure)\r
+ \details Assigns the given value to the non-secure Process Stack Pointer (PSP) when in secure state.\r
+ \param [in] topOfProcStack Process Stack Pointer value to set\r
+ */\r
+__STATIC_FORCEINLINE void __TZ_set_PSP_NS(uint32_t topOfProcStack)\r
+{\r
+ __ASM volatile ("MSR psp_ns, %0" : : "r" (topOfProcStack) : );\r
+}\r
+#endif\r
+\r
+\r
+/**\r
+ \brief Get Main Stack Pointer\r
+ \details Returns the current value of the Main Stack Pointer (MSP).\r
+ \return MSP Register value\r
+ */\r
+__STATIC_FORCEINLINE uint32_t __get_MSP(void)\r
+{\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("MRS %0, msp" : "=r" (result) );\r
+ return(result);\r
+}\r
+\r
+\r
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))\r
+/**\r
+ \brief Get Main Stack Pointer (non-secure)\r
+ \details Returns the current value of the non-secure Main Stack Pointer (MSP) when in secure state.\r
+ \return MSP Register value\r
+ */\r
+__STATIC_FORCEINLINE uint32_t __TZ_get_MSP_NS(void)\r
+{\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("MRS %0, msp_ns" : "=r" (result) );\r
+ return(result);\r
+}\r
+#endif\r
+\r
+\r
+/**\r
+ \brief Set Main Stack Pointer\r
+ \details Assigns the given value to the Main Stack Pointer (MSP).\r
+ \param [in] topOfMainStack Main Stack Pointer value to set\r
+ */\r
+__STATIC_FORCEINLINE void __set_MSP(uint32_t topOfMainStack)\r
+{\r
+ __ASM volatile ("MSR msp, %0" : : "r" (topOfMainStack) : );\r
+}\r
+\r
+\r
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))\r
+/**\r
+ \brief Set Main Stack Pointer (non-secure)\r
+ \details Assigns the given value to the non-secure Main Stack Pointer (MSP) when in secure state.\r
+ \param [in] topOfMainStack Main Stack Pointer value to set\r
+ */\r
+__STATIC_FORCEINLINE void __TZ_set_MSP_NS(uint32_t topOfMainStack)\r
+{\r
+ __ASM volatile ("MSR msp_ns, %0" : : "r" (topOfMainStack) : );\r
+}\r
+#endif\r
+\r
+\r
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))\r
+/**\r
+ \brief Get Stack Pointer (non-secure)\r
+ \details Returns the current value of the non-secure Stack Pointer (SP) when in secure state.\r
+ \return SP Register value\r
+ */\r
+__STATIC_FORCEINLINE uint32_t __TZ_get_SP_NS(void)\r
+{\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("MRS %0, sp_ns" : "=r" (result) );\r
+ return(result);\r
+}\r
+\r
+\r
+/**\r
+ \brief Set Stack Pointer (non-secure)\r
+ \details Assigns the given value to the non-secure Stack Pointer (SP) when in secure state.\r
+ \param [in] topOfStack Stack Pointer value to set\r
+ */\r
+__STATIC_FORCEINLINE void __TZ_set_SP_NS(uint32_t topOfStack)\r
+{\r
+ __ASM volatile ("MSR sp_ns, %0" : : "r" (topOfStack) : );\r
+}\r
+#endif\r
+\r
+\r
+/**\r
+ \brief Get Priority Mask\r
+ \details Returns the current state of the priority mask bit from the Priority Mask Register.\r
+ \return Priority Mask value\r
+ */\r
+__STATIC_FORCEINLINE uint32_t __get_PRIMASK(void)\r
+{\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("MRS %0, primask" : "=r" (result) :: "memory");\r
+ return(result);\r
+}\r
+\r
+\r
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))\r
+/**\r
+ \brief Get Priority Mask (non-secure)\r
+ \details Returns the current state of the non-secure priority mask bit from the Priority Mask Register when in secure state.\r
+ \return Priority Mask value\r
+ */\r
+__STATIC_FORCEINLINE uint32_t __TZ_get_PRIMASK_NS(void)\r
+{\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("MRS %0, primask_ns" : "=r" (result) :: "memory");\r
+ return(result);\r
+}\r
+#endif\r
+\r
+\r
+/**\r
+ \brief Set Priority Mask\r
+ \details Assigns the given value to the Priority Mask Register.\r
+ \param [in] priMask Priority Mask\r
+ */\r
+__STATIC_FORCEINLINE void __set_PRIMASK(uint32_t priMask)\r
+{\r
+ __ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory");\r
+}\r
+\r
+\r
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))\r
+/**\r
+ \brief Set Priority Mask (non-secure)\r
+ \details Assigns the given value to the non-secure Priority Mask Register when in secure state.\r
+ \param [in] priMask Priority Mask\r
+ */\r
+__STATIC_FORCEINLINE void __TZ_set_PRIMASK_NS(uint32_t priMask)\r
+{\r
+ __ASM volatile ("MSR primask_ns, %0" : : "r" (priMask) : "memory");\r
+}\r
+#endif\r
+\r
+\r
+#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \\r
+ (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \\r
+ (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) )\r
+/**\r
+ \brief Enable FIQ\r
+ \details Enables FIQ interrupts by clearing the F-bit in the CPSR.\r
+ Can only be executed in Privileged modes.\r
+ */\r
+__STATIC_FORCEINLINE void __enable_fault_irq(void)\r
+{\r
+ __ASM volatile ("cpsie f" : : : "memory");\r
+}\r
+\r
+\r
+/**\r
+ \brief Disable FIQ\r
+ \details Disables FIQ interrupts by setting the F-bit in the CPSR.\r
+ Can only be executed in Privileged modes.\r
+ */\r
+__STATIC_FORCEINLINE void __disable_fault_irq(void)\r
+{\r
+ __ASM volatile ("cpsid f" : : : "memory");\r
+}\r
+\r
+\r
+/**\r
+ \brief Get Base Priority\r
+ \details Returns the current value of the Base Priority register.\r
+ \return Base Priority register value\r
+ */\r
+__STATIC_FORCEINLINE uint32_t __get_BASEPRI(void)\r
+{\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("MRS %0, basepri" : "=r" (result) );\r
+ return(result);\r
+}\r
+\r
+\r
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))\r
+/**\r
+ \brief Get Base Priority (non-secure)\r
+ \details Returns the current value of the non-secure Base Priority register when in secure state.\r
+ \return Base Priority register value\r
+ */\r
+__STATIC_FORCEINLINE uint32_t __TZ_get_BASEPRI_NS(void)\r
+{\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("MRS %0, basepri_ns" : "=r" (result) );\r
+ return(result);\r
+}\r
+#endif\r
+\r
+\r
+/**\r
+ \brief Set Base Priority\r
+ \details Assigns the given value to the Base Priority register.\r
+ \param [in] basePri Base Priority value to set\r
+ */\r
+__STATIC_FORCEINLINE void __set_BASEPRI(uint32_t basePri)\r
+{\r
+ __ASM volatile ("MSR basepri, %0" : : "r" (basePri) : "memory");\r
+}\r
+\r
+\r
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))\r
+/**\r
+ \brief Set Base Priority (non-secure)\r
+ \details Assigns the given value to the non-secure Base Priority register when in secure state.\r
+ \param [in] basePri Base Priority value to set\r
+ */\r
+__STATIC_FORCEINLINE void __TZ_set_BASEPRI_NS(uint32_t basePri)\r
+{\r
+ __ASM volatile ("MSR basepri_ns, %0" : : "r" (basePri) : "memory");\r
+}\r
+#endif\r
+\r
+\r
+/**\r
+ \brief Set Base Priority with condition\r
+ \details Assigns the given value to the Base Priority register only if BASEPRI masking is disabled,\r
+ or the new value increases the BASEPRI priority level.\r
+ \param [in] basePri Base Priority value to set\r
+ */\r
+__STATIC_FORCEINLINE void __set_BASEPRI_MAX(uint32_t basePri)\r
+{\r
+ __ASM volatile ("MSR basepri_max, %0" : : "r" (basePri) : "memory");\r
+}\r
+\r
+\r
+/**\r
+ \brief Get Fault Mask\r
+ \details Returns the current value of the Fault Mask register.\r
+ \return Fault Mask register value\r
+ */\r
+__STATIC_FORCEINLINE uint32_t __get_FAULTMASK(void)\r
+{\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("MRS %0, faultmask" : "=r" (result) );\r
+ return(result);\r
+}\r
+\r
+\r
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))\r
+/**\r
+ \brief Get Fault Mask (non-secure)\r
+ \details Returns the current value of the non-secure Fault Mask register when in secure state.\r
+ \return Fault Mask register value\r
+ */\r
+__STATIC_FORCEINLINE uint32_t __TZ_get_FAULTMASK_NS(void)\r
+{\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("MRS %0, faultmask_ns" : "=r" (result) );\r
+ return(result);\r
+}\r
+#endif\r
+\r
+\r
+/**\r
+ \brief Set Fault Mask\r
+ \details Assigns the given value to the Fault Mask register.\r
+ \param [in] faultMask Fault Mask value to set\r
+ */\r
+__STATIC_FORCEINLINE void __set_FAULTMASK(uint32_t faultMask)\r
+{\r
+ __ASM volatile ("MSR faultmask, %0" : : "r" (faultMask) : "memory");\r
+}\r
+\r
+\r
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))\r
+/**\r
+ \brief Set Fault Mask (non-secure)\r
+ \details Assigns the given value to the non-secure Fault Mask register when in secure state.\r
+ \param [in] faultMask Fault Mask value to set\r
+ */\r
+__STATIC_FORCEINLINE void __TZ_set_FAULTMASK_NS(uint32_t faultMask)\r
+{\r
+ __ASM volatile ("MSR faultmask_ns, %0" : : "r" (faultMask) : "memory");\r
+}\r
+#endif\r
+\r
+#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \\r
+ (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \\r
+ (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) */\r
+\r
+\r
+#if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \\r
+ (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) )\r
+\r
+/**\r
+ \brief Get Process Stack Pointer Limit\r
+ Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure\r
+ Stack Pointer Limit register hence zero is returned always in non-secure\r
+ mode.\r
+ \r
+ \details Returns the current value of the Process Stack Pointer Limit (PSPLIM).\r
+ \return PSPLIM Register value\r
+ */\r
+__STATIC_FORCEINLINE uint32_t __get_PSPLIM(void)\r
+{\r
+#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \\r
+ (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))\r
+ // without main extensions, the non-secure PSPLIM is RAZ/WI\r
+ return 0U;\r
+#else\r
+ uint32_t result;\r
+ __ASM volatile ("MRS %0, psplim" : "=r" (result) );\r
+ return result;\r
+#endif\r
+}\r
+\r
+#if (defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3))\r
+/**\r
+ \brief Get Process Stack Pointer Limit (non-secure)\r
+ Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure\r
+ Stack Pointer Limit register hence zero is returned always.\r
+\r
+ \details Returns the current value of the non-secure Process Stack Pointer Limit (PSPLIM) when in secure state.\r
+ \return PSPLIM Register value\r
+ */\r
+__STATIC_FORCEINLINE uint32_t __TZ_get_PSPLIM_NS(void)\r
+{\r
+#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)))\r
+ // without main extensions, the non-secure PSPLIM is RAZ/WI\r
+ return 0U;\r
+#else\r
+ uint32_t result;\r
+ __ASM volatile ("MRS %0, psplim_ns" : "=r" (result) );\r
+ return result;\r
+#endif\r
+}\r
+#endif\r
+\r
+\r
+/**\r
+ \brief Set Process Stack Pointer Limit\r
+ Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure\r
+ Stack Pointer Limit register hence the write is silently ignored in non-secure\r
+ mode.\r
+ \r
+ \details Assigns the given value to the Process Stack Pointer Limit (PSPLIM).\r
+ \param [in] ProcStackPtrLimit Process Stack Pointer Limit value to set\r
+ */\r
+__STATIC_FORCEINLINE void __set_PSPLIM(uint32_t ProcStackPtrLimit)\r
+{\r
+#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \\r
+ (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))\r
+ // without main extensions, the non-secure PSPLIM is RAZ/WI\r
+ (void)ProcStackPtrLimit;\r
+#else\r
+ __ASM volatile ("MSR psplim, %0" : : "r" (ProcStackPtrLimit));\r
+#endif\r
+}\r
+\r
+\r
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))\r
+/**\r
+ \brief Set Process Stack Pointer (non-secure)\r
+ Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure\r
+ Stack Pointer Limit register hence the write is silently ignored.\r
+\r
+ \details Assigns the given value to the non-secure Process Stack Pointer Limit (PSPLIM) when in secure state.\r
+ \param [in] ProcStackPtrLimit Process Stack Pointer Limit value to set\r
+ */\r
+__STATIC_FORCEINLINE void __TZ_set_PSPLIM_NS(uint32_t ProcStackPtrLimit)\r
+{\r
+#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)))\r
+ // without main extensions, the non-secure PSPLIM is RAZ/WI\r
+ (void)ProcStackPtrLimit;\r
+#else\r
+ __ASM volatile ("MSR psplim_ns, %0\n" : : "r" (ProcStackPtrLimit));\r
+#endif\r
+}\r
+#endif\r
+\r
+\r
+/**\r
+ \brief Get Main Stack Pointer Limit\r
+ Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure\r
+ Stack Pointer Limit register hence zero is returned always in non-secure\r
+ mode.\r
+\r
+ \details Returns the current value of the Main Stack Pointer Limit (MSPLIM).\r
+ \return MSPLIM Register value\r
+ */\r
+__STATIC_FORCEINLINE uint32_t __get_MSPLIM(void)\r
+{\r
+#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \\r
+ (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))\r
+ // without main extensions, the non-secure MSPLIM is RAZ/WI\r
+ return 0U;\r
+#else\r
+ uint32_t result;\r
+ __ASM volatile ("MRS %0, msplim" : "=r" (result) );\r
+ return result;\r
+#endif\r
+}\r
+\r
+\r
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))\r
+/**\r
+ \brief Get Main Stack Pointer Limit (non-secure)\r
+ Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure\r
+ Stack Pointer Limit register hence zero is returned always.\r
+\r
+ \details Returns the current value of the non-secure Main Stack Pointer Limit(MSPLIM) when in secure state.\r
+ \return MSPLIM Register value\r
+ */\r
+__STATIC_FORCEINLINE uint32_t __TZ_get_MSPLIM_NS(void)\r
+{\r
+#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)))\r
+ // without main extensions, the non-secure MSPLIM is RAZ/WI\r
+ return 0U;\r
+#else\r
+ uint32_t result;\r
+ __ASM volatile ("MRS %0, msplim_ns" : "=r" (result) );\r
+ return result;\r
+#endif\r
+}\r
+#endif\r
+\r
+\r
+/**\r
+ \brief Set Main Stack Pointer Limit\r
+ Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure\r
+ Stack Pointer Limit register hence the write is silently ignored in non-secure\r
+ mode.\r
+\r
+ \details Assigns the given value to the Main Stack Pointer Limit (MSPLIM).\r
+ \param [in] MainStackPtrLimit Main Stack Pointer Limit value to set\r
+ */\r
+__STATIC_FORCEINLINE void __set_MSPLIM(uint32_t MainStackPtrLimit)\r
+{\r
+#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \\r
+ (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))\r
+ // without main extensions, the non-secure MSPLIM is RAZ/WI\r
+ (void)MainStackPtrLimit;\r
+#else\r
+ __ASM volatile ("MSR msplim, %0" : : "r" (MainStackPtrLimit));\r
+#endif\r
+}\r
+\r
+\r
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))\r
+/**\r
+ \brief Set Main Stack Pointer Limit (non-secure)\r
+ Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure\r
+ Stack Pointer Limit register hence the write is silently ignored.\r
+\r
+ \details Assigns the given value to the non-secure Main Stack Pointer Limit (MSPLIM) when in secure state.\r
+ \param [in] MainStackPtrLimit Main Stack Pointer value to set\r
+ */\r
+__STATIC_FORCEINLINE void __TZ_set_MSPLIM_NS(uint32_t MainStackPtrLimit)\r
+{\r
+#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)))\r
+ // without main extensions, the non-secure MSPLIM is RAZ/WI\r
+ (void)MainStackPtrLimit;\r
+#else\r
+ __ASM volatile ("MSR msplim_ns, %0" : : "r" (MainStackPtrLimit));\r
+#endif\r
+}\r
+#endif\r
+\r
+#endif /* ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \\r
+ (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) */\r
+\r
+\r
+/**\r
+ \brief Get FPSCR\r
+ \details Returns the current value of the Floating Point Status/Control register.\r
+ \return Floating Point Status/Control register value\r
+ */\r
+__STATIC_FORCEINLINE uint32_t __get_FPSCR(void)\r
+{\r
+#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \\r
+ (defined (__FPU_USED ) && (__FPU_USED == 1U)) )\r
+#if __has_builtin(__builtin_arm_get_fpscr) \r
+// Re-enable using built-in when GCC has been fixed\r
+// || (__GNUC__ > 7) || (__GNUC__ == 7 && __GNUC_MINOR__ >= 2)\r
+ /* see https://gcc.gnu.org/ml/gcc-patches/2017-04/msg00443.html */\r
+ return __builtin_arm_get_fpscr();\r
+#else\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("VMRS %0, fpscr" : "=r" (result) );\r
+ return(result);\r
+#endif\r
+#else\r
+ return(0U);\r
+#endif\r
+}\r
+\r
+\r
+/**\r
+ \brief Set FPSCR\r
+ \details Assigns the given value to the Floating Point Status/Control register.\r
+ \param [in] fpscr Floating Point Status/Control value to set\r
+ */\r
+__STATIC_FORCEINLINE void __set_FPSCR(uint32_t fpscr)\r
+{\r
+#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \\r
+ (defined (__FPU_USED ) && (__FPU_USED == 1U)) )\r
+#if __has_builtin(__builtin_arm_set_fpscr)\r
+// Re-enable using built-in when GCC has been fixed\r
+// || (__GNUC__ > 7) || (__GNUC__ == 7 && __GNUC_MINOR__ >= 2)\r
+ /* see https://gcc.gnu.org/ml/gcc-patches/2017-04/msg00443.html */\r
+ __builtin_arm_set_fpscr(fpscr);\r
+#else\r
+ __ASM volatile ("VMSR fpscr, %0" : : "r" (fpscr) : "vfpcc", "memory");\r
+#endif\r
+#else\r
+ (void)fpscr;\r
+#endif\r
+}\r
+\r
+\r
+/*@} end of CMSIS_Core_RegAccFunctions */\r
+\r
+\r
+/* ########################## Core Instruction Access ######################### */\r
+/** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface\r
+ Access to dedicated instructions\r
+ @{\r
+*/\r
+\r
+/* Define macros for porting to both thumb1 and thumb2.\r
+ * For thumb1, use low register (r0-r7), specified by constraint "l"\r
+ * Otherwise, use general registers, specified by constraint "r" */\r
+#if defined (__thumb__) && !defined (__thumb2__)\r
+#define __CMSIS_GCC_OUT_REG(r) "=l" (r)\r
+#define __CMSIS_GCC_RW_REG(r) "+l" (r)\r
+#define __CMSIS_GCC_USE_REG(r) "l" (r)\r
+#else\r
+#define __CMSIS_GCC_OUT_REG(r) "=r" (r)\r
+#define __CMSIS_GCC_RW_REG(r) "+r" (r)\r
+#define __CMSIS_GCC_USE_REG(r) "r" (r)\r
+#endif\r
+\r
+/**\r
+ \brief No Operation\r
+ \details No Operation does nothing. This instruction can be used for code alignment purposes.\r
+ */\r
+#define __NOP() __ASM volatile ("nop")\r
+\r
+/**\r
+ \brief Wait For Interrupt\r
+ \details Wait For Interrupt is a hint instruction that suspends execution until one of a number of events occurs.\r
+ */\r
+#define __WFI() __ASM volatile ("wfi")\r
+\r
+\r
+/**\r
+ \brief Wait For Event\r
+ \details Wait For Event is a hint instruction that permits the processor to enter\r
+ a low-power state until one of a number of events occurs.\r
+ */\r
+#define __WFE() __ASM volatile ("wfe")\r
+\r
+\r
+/**\r
+ \brief Send Event\r
+ \details Send Event is a hint instruction. It causes an event to be signaled to the CPU.\r
+ */\r
+#define __SEV() __ASM volatile ("sev")\r
+\r
+\r
+/**\r
+ \brief Instruction Synchronization Barrier\r
+ \details Instruction Synchronization Barrier flushes the pipeline in the processor,\r
+ so that all instructions following the ISB are fetched from cache or memory,\r
+ after the instruction has been completed.\r
+ */\r
+__STATIC_FORCEINLINE void __ISB(void)\r
+{\r
+ __ASM volatile ("isb 0xF":::"memory");\r
+}\r
+\r
+\r
+/**\r
+ \brief Data Synchronization Barrier\r
+ \details Acts as a special kind of Data Memory Barrier.\r
+ It completes when all explicit memory accesses before this instruction complete.\r
+ */\r
+__STATIC_FORCEINLINE void __DSB(void)\r
+{\r
+ __ASM volatile ("dsb 0xF":::"memory");\r
+}\r
+\r
+\r
+/**\r
+ \brief Data Memory Barrier\r
+ \details Ensures the apparent order of the explicit memory operations before\r
+ and after the instruction, without ensuring their completion.\r
+ */\r
+__STATIC_FORCEINLINE void __DMB(void)\r
+{\r
+ __ASM volatile ("dmb 0xF":::"memory");\r
+}\r
+\r
+\r
+/**\r
+ \brief Reverse byte order (32 bit)\r
+ \details Reverses the byte order in unsigned integer value. For example, 0x12345678 becomes 0x78563412.\r
+ \param [in] value Value to reverse\r
+ \return Reversed value\r
+ */\r
+__STATIC_FORCEINLINE uint32_t __REV(uint32_t value)\r
+{\r
+#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 5)\r
+ return __builtin_bswap32(value);\r
+#else\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("rev %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) );\r
+ return result;\r
+#endif\r
+}\r
+\r
+\r
+/**\r
+ \brief Reverse byte order (16 bit)\r
+ \details Reverses the byte order within each halfword of a word. For example, 0x12345678 becomes 0x34127856.\r
+ \param [in] value Value to reverse\r
+ \return Reversed value\r
+ */\r
+__STATIC_FORCEINLINE uint32_t __REV16(uint32_t value)\r
+{\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("rev16 %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) );\r
+ return result;\r
+}\r
+\r
+\r
+/**\r
+ \brief Reverse byte order (16 bit)\r
+ \details Reverses the byte order in a 16-bit value and returns the signed 16-bit result. For example, 0x0080 becomes 0x8000.\r
+ \param [in] value Value to reverse\r
+ \return Reversed value\r
+ */\r
+__STATIC_FORCEINLINE int16_t __REVSH(int16_t value)\r
+{\r
+#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8)\r
+ return (int16_t)__builtin_bswap16(value);\r
+#else\r
+ int16_t result;\r
+\r
+ __ASM volatile ("revsh %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) );\r
+ return result;\r
+#endif\r
+}\r
+\r
+\r
+/**\r
+ \brief Rotate Right in unsigned value (32 bit)\r
+ \details Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits.\r
+ \param [in] op1 Value to rotate\r
+ \param [in] op2 Number of Bits to rotate\r
+ \return Rotated value\r
+ */\r
+__STATIC_FORCEINLINE uint32_t __ROR(uint32_t op1, uint32_t op2)\r
+{\r
+ op2 %= 32U;\r
+ if (op2 == 0U)\r
+ {\r
+ return op1;\r
+ }\r
+ return (op1 >> op2) | (op1 << (32U - op2));\r
+}\r
+\r
+\r
+/**\r
+ \brief Breakpoint\r
+ \details Causes the processor to enter Debug state.\r
+ Debug tools can use this to investigate system state when the instruction at a particular address is reached.\r
+ \param [in] value is ignored by the processor.\r
+ If required, a debugger can use it to store additional information about the breakpoint.\r
+ */\r
+#define __BKPT(value) __ASM volatile ("bkpt "#value)\r
+\r
+\r
+/**\r
+ \brief Reverse bit order of value\r
+ \details Reverses the bit order of the given value.\r
+ \param [in] value Value to reverse\r
+ \return Reversed value\r
+ */\r
+__STATIC_FORCEINLINE uint32_t __RBIT(uint32_t value)\r
+{\r
+ uint32_t result;\r
+\r
+#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \\r
+ (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \\r
+ (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) )\r
+ __ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) );\r
+#else\r
+ uint32_t s = (4U /*sizeof(v)*/ * 8U) - 1U; /* extra shift needed at end */\r
+\r
+ result = value; /* r will be reversed bits of v; first get LSB of v */\r
+ for (value >>= 1U; value != 0U; value >>= 1U)\r
+ {\r
+ result <<= 1U;\r
+ result |= value & 1U;\r
+ s--;\r
+ }\r
+ result <<= s; /* shift when v's highest bits are zero */\r
+#endif\r
+ return result;\r
+}\r
+\r
+\r
+/**\r
+ \brief Count leading zeros\r
+ \details Counts the number of leading zeros of a data value.\r
+ \param [in] value Value to count the leading zeros\r
+ \return number of leading zeros in value\r
+ */\r
+#define __CLZ (uint8_t)__builtin_clz\r
+\r
+\r
+#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \\r
+ (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \\r
+ (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \\r
+ (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) )\r
+/**\r
+ \brief LDR Exclusive (8 bit)\r
+ \details Executes a exclusive LDR instruction for 8 bit value.\r
+ \param [in] ptr Pointer to data\r
+ \return value of type uint8_t at (*ptr)\r
+ */\r
+__STATIC_FORCEINLINE uint8_t __LDREXB(volatile uint8_t *addr)\r
+{\r
+ uint32_t result;\r
+\r
+#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8)\r
+ __ASM volatile ("ldrexb %0, %1" : "=r" (result) : "Q" (*addr) );\r
+#else\r
+ /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not\r
+ accepted by assembler. So has to use following less efficient pattern.\r
+ */\r
+ __ASM volatile ("ldrexb %0, [%1]" : "=r" (result) : "r" (addr) : "memory" );\r
+#endif\r
+ return ((uint8_t) result); /* Add explicit type cast here */\r
+}\r
+\r
+\r
+/**\r
+ \brief LDR Exclusive (16 bit)\r
+ \details Executes a exclusive LDR instruction for 16 bit values.\r
+ \param [in] ptr Pointer to data\r
+ \return value of type uint16_t at (*ptr)\r
+ */\r
+__STATIC_FORCEINLINE uint16_t __LDREXH(volatile uint16_t *addr)\r
+{\r
+ uint32_t result;\r
+\r
+#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8)\r
+ __ASM volatile ("ldrexh %0, %1" : "=r" (result) : "Q" (*addr) );\r
+#else\r
+ /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not\r
+ accepted by assembler. So has to use following less efficient pattern.\r
+ */\r
+ __ASM volatile ("ldrexh %0, [%1]" : "=r" (result) : "r" (addr) : "memory" );\r
+#endif\r
+ return ((uint16_t) result); /* Add explicit type cast here */\r
+}\r
+\r
+\r
+/**\r
+ \brief LDR Exclusive (32 bit)\r
+ \details Executes a exclusive LDR instruction for 32 bit values.\r
+ \param [in] ptr Pointer to data\r
+ \return value of type uint32_t at (*ptr)\r
+ */\r
+__STATIC_FORCEINLINE uint32_t __LDREXW(volatile uint32_t *addr)\r
+{\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) );\r
+ return(result);\r
+}\r
+\r
+\r
+/**\r
+ \brief STR Exclusive (8 bit)\r
+ \details Executes a exclusive STR instruction for 8 bit values.\r
+ \param [in] value Value to store\r
+ \param [in] ptr Pointer to location\r
+ \return 0 Function succeeded\r
+ \return 1 Function failed\r
+ */\r
+__STATIC_FORCEINLINE uint32_t __STREXB(uint8_t value, volatile uint8_t *addr)\r
+{\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("strexb %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" ((uint32_t)value) );\r
+ return(result);\r
+}\r
+\r
+\r
+/**\r
+ \brief STR Exclusive (16 bit)\r
+ \details Executes a exclusive STR instruction for 16 bit values.\r
+ \param [in] value Value to store\r
+ \param [in] ptr Pointer to location\r
+ \return 0 Function succeeded\r
+ \return 1 Function failed\r
+ */\r
+__STATIC_FORCEINLINE uint32_t __STREXH(uint16_t value, volatile uint16_t *addr)\r
+{\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("strexh %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" ((uint32_t)value) );\r
+ return(result);\r
+}\r
+\r
+\r
+/**\r
+ \brief STR Exclusive (32 bit)\r
+ \details Executes a exclusive STR instruction for 32 bit values.\r
+ \param [in] value Value to store\r
+ \param [in] ptr Pointer to location\r
+ \return 0 Function succeeded\r
+ \return 1 Function failed\r
+ */\r
+__STATIC_FORCEINLINE uint32_t __STREXW(uint32_t value, volatile uint32_t *addr)\r
+{\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );\r
+ return(result);\r
+}\r
+\r
+\r
+/**\r
+ \brief Remove the exclusive lock\r
+ \details Removes the exclusive lock which is created by LDREX.\r
+ */\r
+__STATIC_FORCEINLINE void __CLREX(void)\r
+{\r
+ __ASM volatile ("clrex" ::: "memory");\r
+}\r
+\r
+#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \\r
+ (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \\r
+ (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \\r
+ (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) */\r
+\r
+\r
+#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \\r
+ (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \\r
+ (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) )\r
+/**\r
+ \brief Signed Saturate\r
+ \details Saturates a signed value.\r
+ \param [in] ARG1 Value to be saturated\r
+ \param [in] ARG2 Bit position to saturate to (1..32)\r
+ \return Saturated value\r
+ */\r
+#define __SSAT(ARG1,ARG2) \\r
+__extension__ \\r
+({ \\r
+ int32_t __RES, __ARG1 = (ARG1); \\r
+ __ASM ("ssat %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \\r
+ __RES; \\r
+ })\r
+\r
+\r
+/**\r
+ \brief Unsigned Saturate\r
+ \details Saturates an unsigned value.\r
+ \param [in] ARG1 Value to be saturated\r
+ \param [in] ARG2 Bit position to saturate to (0..31)\r
+ \return Saturated value\r
+ */\r
+#define __USAT(ARG1,ARG2) \\r
+ __extension__ \\r
+({ \\r
+ uint32_t __RES, __ARG1 = (ARG1); \\r
+ __ASM ("usat %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \\r
+ __RES; \\r
+ })\r
+\r
+\r
+/**\r
+ \brief Rotate Right with Extend (32 bit)\r
+ \details Moves each bit of a bitstring right by one bit.\r
+ The carry input is shifted in at the left end of the bitstring.\r
+ \param [in] value Value to rotate\r
+ \return Rotated value\r
+ */\r
+__STATIC_FORCEINLINE uint32_t __RRX(uint32_t value)\r
+{\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("rrx %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) );\r
+ return(result);\r
+}\r
+\r
+\r
+/**\r
+ \brief LDRT Unprivileged (8 bit)\r
+ \details Executes a Unprivileged LDRT instruction for 8 bit value.\r
+ \param [in] ptr Pointer to data\r
+ \return value of type uint8_t at (*ptr)\r
+ */\r
+__STATIC_FORCEINLINE uint8_t __LDRBT(volatile uint8_t *ptr)\r
+{\r
+ uint32_t result;\r
+\r
+#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8)\r
+ __ASM volatile ("ldrbt %0, %1" : "=r" (result) : "Q" (*ptr) );\r
+#else\r
+ /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not\r
+ accepted by assembler. So has to use following less efficient pattern.\r
+ */\r
+ __ASM volatile ("ldrbt %0, [%1]" : "=r" (result) : "r" (ptr) : "memory" );\r
+#endif\r
+ return ((uint8_t) result); /* Add explicit type cast here */\r
+}\r
+\r
+\r
+/**\r
+ \brief LDRT Unprivileged (16 bit)\r
+ \details Executes a Unprivileged LDRT instruction for 16 bit values.\r
+ \param [in] ptr Pointer to data\r
+ \return value of type uint16_t at (*ptr)\r
+ */\r
+__STATIC_FORCEINLINE uint16_t __LDRHT(volatile uint16_t *ptr)\r
+{\r
+ uint32_t result;\r
+\r
+#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8)\r
+ __ASM volatile ("ldrht %0, %1" : "=r" (result) : "Q" (*ptr) );\r
+#else\r
+ /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not\r
+ accepted by assembler. So has to use following less efficient pattern.\r
+ */\r
+ __ASM volatile ("ldrht %0, [%1]" : "=r" (result) : "r" (ptr) : "memory" );\r
+#endif\r
+ return ((uint16_t) result); /* Add explicit type cast here */\r
+}\r
+\r
+\r
+/**\r
+ \brief LDRT Unprivileged (32 bit)\r
+ \details Executes a Unprivileged LDRT instruction for 32 bit values.\r
+ \param [in] ptr Pointer to data\r
+ \return value of type uint32_t at (*ptr)\r
+ */\r
+__STATIC_FORCEINLINE uint32_t __LDRT(volatile uint32_t *ptr)\r
+{\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("ldrt %0, %1" : "=r" (result) : "Q" (*ptr) );\r
+ return(result);\r
+}\r
+\r
+\r
+/**\r
+ \brief STRT Unprivileged (8 bit)\r
+ \details Executes a Unprivileged STRT instruction for 8 bit values.\r
+ \param [in] value Value to store\r
+ \param [in] ptr Pointer to location\r
+ */\r
+__STATIC_FORCEINLINE void __STRBT(uint8_t value, volatile uint8_t *ptr)\r
+{\r
+ __ASM volatile ("strbt %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) );\r
+}\r
+\r
+\r
+/**\r
+ \brief STRT Unprivileged (16 bit)\r
+ \details Executes a Unprivileged STRT instruction for 16 bit values.\r
+ \param [in] value Value to store\r
+ \param [in] ptr Pointer to location\r
+ */\r
+__STATIC_FORCEINLINE void __STRHT(uint16_t value, volatile uint16_t *ptr)\r
+{\r
+ __ASM volatile ("strht %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) );\r
+}\r
+\r
+\r
+/**\r
+ \brief STRT Unprivileged (32 bit)\r
+ \details Executes a Unprivileged STRT instruction for 32 bit values.\r
+ \param [in] value Value to store\r
+ \param [in] ptr Pointer to location\r
+ */\r
+__STATIC_FORCEINLINE void __STRT(uint32_t value, volatile uint32_t *ptr)\r
+{\r
+ __ASM volatile ("strt %1, %0" : "=Q" (*ptr) : "r" (value) );\r
+}\r
+\r
+#else /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \\r
+ (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \\r
+ (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) */\r
+\r
+/**\r
+ \brief Signed Saturate\r
+ \details Saturates a signed value.\r
+ \param [in] value Value to be saturated\r
+ \param [in] sat Bit position to saturate to (1..32)\r
+ \return Saturated value\r
+ */\r
+__STATIC_FORCEINLINE int32_t __SSAT(int32_t val, uint32_t sat)\r
+{\r
+ if ((sat >= 1U) && (sat <= 32U))\r
+ {\r
+ const int32_t max = (int32_t)((1U << (sat - 1U)) - 1U);\r
+ const int32_t min = -1 - max ;\r
+ if (val > max)\r
+ {\r
+ return max;\r
+ }\r
+ else if (val < min)\r
+ {\r
+ return min;\r
+ }\r
+ }\r
+ return val;\r
+}\r
+\r
+/**\r
+ \brief Unsigned Saturate\r
+ \details Saturates an unsigned value.\r
+ \param [in] value Value to be saturated\r
+ \param [in] sat Bit position to saturate to (0..31)\r
+ \return Saturated value\r
+ */\r
+__STATIC_FORCEINLINE uint32_t __USAT(int32_t val, uint32_t sat)\r
+{\r
+ if (sat <= 31U)\r
+ {\r
+ const uint32_t max = ((1U << sat) - 1U);\r
+ if (val > (int32_t)max)\r
+ {\r
+ return max;\r
+ }\r
+ else if (val < 0)\r
+ {\r
+ return 0U;\r
+ }\r
+ }\r
+ return (uint32_t)val;\r
+}\r
+\r
+#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \\r
+ (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \\r
+ (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) */\r
+\r
+\r
+#if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \\r
+ (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) )\r
+/**\r
+ \brief Load-Acquire (8 bit)\r
+ \details Executes a LDAB instruction for 8 bit value.\r
+ \param [in] ptr Pointer to data\r
+ \return value of type uint8_t at (*ptr)\r
+ */\r
+__STATIC_FORCEINLINE uint8_t __LDAB(volatile uint8_t *ptr)\r
+{\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("ldab %0, %1" : "=r" (result) : "Q" (*ptr) );\r
+ return ((uint8_t) result);\r
+}\r
+\r
+\r
+/**\r
+ \brief Load-Acquire (16 bit)\r
+ \details Executes a LDAH instruction for 16 bit values.\r
+ \param [in] ptr Pointer to data\r
+ \return value of type uint16_t at (*ptr)\r
+ */\r
+__STATIC_FORCEINLINE uint16_t __LDAH(volatile uint16_t *ptr)\r
+{\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("ldah %0, %1" : "=r" (result) : "Q" (*ptr) );\r
+ return ((uint16_t) result);\r
+}\r
+\r
+\r
+/**\r
+ \brief Load-Acquire (32 bit)\r
+ \details Executes a LDA instruction for 32 bit values.\r
+ \param [in] ptr Pointer to data\r
+ \return value of type uint32_t at (*ptr)\r
+ */\r
+__STATIC_FORCEINLINE uint32_t __LDA(volatile uint32_t *ptr)\r
+{\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("lda %0, %1" : "=r" (result) : "Q" (*ptr) );\r
+ return(result);\r
+}\r
+\r
+\r
+/**\r
+ \brief Store-Release (8 bit)\r
+ \details Executes a STLB instruction for 8 bit values.\r
+ \param [in] value Value to store\r
+ \param [in] ptr Pointer to location\r
+ */\r
+__STATIC_FORCEINLINE void __STLB(uint8_t value, volatile uint8_t *ptr)\r
+{\r
+ __ASM volatile ("stlb %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) );\r
+}\r
+\r
+\r
+/**\r
+ \brief Store-Release (16 bit)\r
+ \details Executes a STLH instruction for 16 bit values.\r
+ \param [in] value Value to store\r
+ \param [in] ptr Pointer to location\r
+ */\r
+__STATIC_FORCEINLINE void __STLH(uint16_t value, volatile uint16_t *ptr)\r
+{\r
+ __ASM volatile ("stlh %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) );\r
+}\r
+\r
+\r
+/**\r
+ \brief Store-Release (32 bit)\r
+ \details Executes a STL instruction for 32 bit values.\r
+ \param [in] value Value to store\r
+ \param [in] ptr Pointer to location\r
+ */\r
+__STATIC_FORCEINLINE void __STL(uint32_t value, volatile uint32_t *ptr)\r
+{\r
+ __ASM volatile ("stl %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) );\r
+}\r
+\r
+\r
+/**\r
+ \brief Load-Acquire Exclusive (8 bit)\r
+ \details Executes a LDAB exclusive instruction for 8 bit value.\r
+ \param [in] ptr Pointer to data\r
+ \return value of type uint8_t at (*ptr)\r
+ */\r
+__STATIC_FORCEINLINE uint8_t __LDAEXB(volatile uint8_t *ptr)\r
+{\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("ldaexb %0, %1" : "=r" (result) : "Q" (*ptr) );\r
+ return ((uint8_t) result);\r
+}\r
+\r
+\r
+/**\r
+ \brief Load-Acquire Exclusive (16 bit)\r
+ \details Executes a LDAH exclusive instruction for 16 bit values.\r
+ \param [in] ptr Pointer to data\r
+ \return value of type uint16_t at (*ptr)\r
+ */\r
+__STATIC_FORCEINLINE uint16_t __LDAEXH(volatile uint16_t *ptr)\r
+{\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("ldaexh %0, %1" : "=r" (result) : "Q" (*ptr) );\r
+ return ((uint16_t) result);\r
+}\r
+\r
+\r
+/**\r
+ \brief Load-Acquire Exclusive (32 bit)\r
+ \details Executes a LDA exclusive instruction for 32 bit values.\r
+ \param [in] ptr Pointer to data\r
+ \return value of type uint32_t at (*ptr)\r
+ */\r
+__STATIC_FORCEINLINE uint32_t __LDAEX(volatile uint32_t *ptr)\r
+{\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("ldaex %0, %1" : "=r" (result) : "Q" (*ptr) );\r
+ return(result);\r
+}\r
+\r
+\r
+/**\r
+ \brief Store-Release Exclusive (8 bit)\r
+ \details Executes a STLB exclusive instruction for 8 bit values.\r
+ \param [in] value Value to store\r
+ \param [in] ptr Pointer to location\r
+ \return 0 Function succeeded\r
+ \return 1 Function failed\r
+ */\r
+__STATIC_FORCEINLINE uint32_t __STLEXB(uint8_t value, volatile uint8_t *ptr)\r
+{\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("stlexb %0, %2, %1" : "=&r" (result), "=Q" (*ptr) : "r" ((uint32_t)value) );\r
+ return(result);\r
+}\r
+\r
+\r
+/**\r
+ \brief Store-Release Exclusive (16 bit)\r
+ \details Executes a STLH exclusive instruction for 16 bit values.\r
+ \param [in] value Value to store\r
+ \param [in] ptr Pointer to location\r
+ \return 0 Function succeeded\r
+ \return 1 Function failed\r
+ */\r
+__STATIC_FORCEINLINE uint32_t __STLEXH(uint16_t value, volatile uint16_t *ptr)\r
+{\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("stlexh %0, %2, %1" : "=&r" (result), "=Q" (*ptr) : "r" ((uint32_t)value) );\r
+ return(result);\r
+}\r
+\r
+\r
+/**\r
+ \brief Store-Release Exclusive (32 bit)\r
+ \details Executes a STL exclusive instruction for 32 bit values.\r
+ \param [in] value Value to store\r
+ \param [in] ptr Pointer to location\r
+ \return 0 Function succeeded\r
+ \return 1 Function failed\r
+ */\r
+__STATIC_FORCEINLINE uint32_t __STLEX(uint32_t value, volatile uint32_t *ptr)\r
+{\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("stlex %0, %2, %1" : "=&r" (result), "=Q" (*ptr) : "r" ((uint32_t)value) );\r
+ return(result);\r
+}\r
+\r
+#endif /* ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \\r
+ (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) */\r
+\r
+/*@}*/ /* end of group CMSIS_Core_InstructionInterface */\r
+\r
+\r
+/* ################### Compiler specific Intrinsics ########################### */\r
+/** \defgroup CMSIS_SIMD_intrinsics CMSIS SIMD Intrinsics\r
+ Access to dedicated SIMD instructions\r
+ @{\r
+*/\r
+\r
+#if (defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1))\r
+\r
+__STATIC_FORCEINLINE uint32_t __SADD8(uint32_t op1, uint32_t op2)\r
+{\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("sadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );\r
+ return(result);\r
+}\r
+\r
+__STATIC_FORCEINLINE uint32_t __QADD8(uint32_t op1, uint32_t op2)\r
+{\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("qadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );\r
+ return(result);\r
+}\r
+\r
+__STATIC_FORCEINLINE uint32_t __SHADD8(uint32_t op1, uint32_t op2)\r
+{\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("shadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );\r
+ return(result);\r
+}\r
+\r
+__STATIC_FORCEINLINE uint32_t __UADD8(uint32_t op1, uint32_t op2)\r
+{\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("uadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );\r
+ return(result);\r
+}\r
+\r
+__STATIC_FORCEINLINE uint32_t __UQADD8(uint32_t op1, uint32_t op2)\r
+{\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("uqadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );\r
+ return(result);\r
+}\r
+\r
+__STATIC_FORCEINLINE uint32_t __UHADD8(uint32_t op1, uint32_t op2)\r
+{\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("uhadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );\r
+ return(result);\r
+}\r
+\r
+\r
+__STATIC_FORCEINLINE uint32_t __SSUB8(uint32_t op1, uint32_t op2)\r
+{\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("ssub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );\r
+ return(result);\r
+}\r
+\r
+__STATIC_FORCEINLINE uint32_t __QSUB8(uint32_t op1, uint32_t op2)\r
+{\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("qsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );\r
+ return(result);\r
+}\r
+\r
+__STATIC_FORCEINLINE uint32_t __SHSUB8(uint32_t op1, uint32_t op2)\r
+{\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("shsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );\r
+ return(result);\r
+}\r
+\r
+__STATIC_FORCEINLINE uint32_t __USUB8(uint32_t op1, uint32_t op2)\r
+{\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("usub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );\r
+ return(result);\r
+}\r
+\r
+__STATIC_FORCEINLINE uint32_t __UQSUB8(uint32_t op1, uint32_t op2)\r
+{\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("uqsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );\r
+ return(result);\r
+}\r
+\r
+__STATIC_FORCEINLINE uint32_t __UHSUB8(uint32_t op1, uint32_t op2)\r
+{\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("uhsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );\r
+ return(result);\r
+}\r
+\r
+\r
+__STATIC_FORCEINLINE uint32_t __SADD16(uint32_t op1, uint32_t op2)\r
+{\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("sadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );\r
+ return(result);\r
+}\r
+\r
+__STATIC_FORCEINLINE uint32_t __QADD16(uint32_t op1, uint32_t op2)\r
+{\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("qadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );\r
+ return(result);\r
+}\r
+\r
+__STATIC_FORCEINLINE uint32_t __SHADD16(uint32_t op1, uint32_t op2)\r
+{\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("shadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );\r
+ return(result);\r
+}\r
+\r
+__STATIC_FORCEINLINE uint32_t __UADD16(uint32_t op1, uint32_t op2)\r
+{\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("uadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );\r
+ return(result);\r
+}\r
+\r
+__STATIC_FORCEINLINE uint32_t __UQADD16(uint32_t op1, uint32_t op2)\r
+{\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("uqadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );\r
+ return(result);\r
+}\r
+\r
+__STATIC_FORCEINLINE uint32_t __UHADD16(uint32_t op1, uint32_t op2)\r
+{\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("uhadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );\r
+ return(result);\r
+}\r
+\r
+__STATIC_FORCEINLINE uint32_t __SSUB16(uint32_t op1, uint32_t op2)\r
+{\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("ssub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );\r
+ return(result);\r
+}\r
+\r
+__STATIC_FORCEINLINE uint32_t __QSUB16(uint32_t op1, uint32_t op2)\r
+{\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("qsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );\r
+ return(result);\r
+}\r
+\r
+__STATIC_FORCEINLINE uint32_t __SHSUB16(uint32_t op1, uint32_t op2)\r
+{\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("shsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );\r
+ return(result);\r
+}\r
+\r
+__STATIC_FORCEINLINE uint32_t __USUB16(uint32_t op1, uint32_t op2)\r
+{\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("usub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );\r
+ return(result);\r
+}\r
+\r
+__STATIC_FORCEINLINE uint32_t __UQSUB16(uint32_t op1, uint32_t op2)\r
+{\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("uqsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );\r
+ return(result);\r
+}\r
+\r
+__STATIC_FORCEINLINE uint32_t __UHSUB16(uint32_t op1, uint32_t op2)\r
+{\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("uhsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );\r
+ return(result);\r
+}\r
+\r
+__STATIC_FORCEINLINE uint32_t __SASX(uint32_t op1, uint32_t op2)\r
+{\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("sasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );\r
+ return(result);\r
+}\r
+\r
+__STATIC_FORCEINLINE uint32_t __QASX(uint32_t op1, uint32_t op2)\r
+{\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("qasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );\r
+ return(result);\r
+}\r
+\r
+__STATIC_FORCEINLINE uint32_t __SHASX(uint32_t op1, uint32_t op2)\r
+{\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("shasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );\r
+ return(result);\r
+}\r
+\r
+__STATIC_FORCEINLINE uint32_t __UASX(uint32_t op1, uint32_t op2)\r
+{\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("uasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );\r
+ return(result);\r
+}\r
+\r
+__STATIC_FORCEINLINE uint32_t __UQASX(uint32_t op1, uint32_t op2)\r
+{\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("uqasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );\r
+ return(result);\r
+}\r
+\r
+__STATIC_FORCEINLINE uint32_t __UHASX(uint32_t op1, uint32_t op2)\r
+{\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("uhasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );\r
+ return(result);\r
+}\r
+\r
+__STATIC_FORCEINLINE uint32_t __SSAX(uint32_t op1, uint32_t op2)\r
+{\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("ssax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );\r
+ return(result);\r
+}\r
+\r
+__STATIC_FORCEINLINE uint32_t __QSAX(uint32_t op1, uint32_t op2)\r
+{\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("qsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );\r
+ return(result);\r
+}\r
+\r
+__STATIC_FORCEINLINE uint32_t __SHSAX(uint32_t op1, uint32_t op2)\r
+{\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("shsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );\r
+ return(result);\r
+}\r
+\r
+__STATIC_FORCEINLINE uint32_t __USAX(uint32_t op1, uint32_t op2)\r
+{\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("usax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );\r
+ return(result);\r
+}\r
+\r
+__STATIC_FORCEINLINE uint32_t __UQSAX(uint32_t op1, uint32_t op2)\r
+{\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("uqsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );\r
+ return(result);\r
+}\r
+\r
+__STATIC_FORCEINLINE uint32_t __UHSAX(uint32_t op1, uint32_t op2)\r
+{\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("uhsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );\r
+ return(result);\r
+}\r
+\r
+__STATIC_FORCEINLINE uint32_t __USAD8(uint32_t op1, uint32_t op2)\r
+{\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("usad8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );\r
+ return(result);\r
+}\r
+\r
+__STATIC_FORCEINLINE uint32_t __USADA8(uint32_t op1, uint32_t op2, uint32_t op3)\r
+{\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("usada8 %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );\r
+ return(result);\r
+}\r
+\r
+#define __SSAT16(ARG1,ARG2) \\r
+({ \\r
+ int32_t __RES, __ARG1 = (ARG1); \\r
+ __ASM ("ssat16 %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \\r
+ __RES; \\r
+ })\r
+\r
+#define __USAT16(ARG1,ARG2) \\r
+({ \\r
+ uint32_t __RES, __ARG1 = (ARG1); \\r
+ __ASM ("usat16 %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \\r
+ __RES; \\r
+ })\r
+\r
+__STATIC_FORCEINLINE uint32_t __UXTB16(uint32_t op1)\r
+{\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("uxtb16 %0, %1" : "=r" (result) : "r" (op1));\r
+ return(result);\r
+}\r
+\r
+__STATIC_FORCEINLINE uint32_t __UXTAB16(uint32_t op1, uint32_t op2)\r
+{\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("uxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );\r
+ return(result);\r
+}\r
+\r
+__STATIC_FORCEINLINE uint32_t __SXTB16(uint32_t op1)\r
+{\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("sxtb16 %0, %1" : "=r" (result) : "r" (op1));\r
+ return(result);\r
+}\r
+\r
+__STATIC_FORCEINLINE uint32_t __SXTAB16(uint32_t op1, uint32_t op2)\r
+{\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("sxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );\r
+ return(result);\r
+}\r
+\r
+__STATIC_FORCEINLINE uint32_t __SMUAD (uint32_t op1, uint32_t op2)\r
+{\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("smuad %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );\r
+ return(result);\r
+}\r
+\r
+__STATIC_FORCEINLINE uint32_t __SMUADX (uint32_t op1, uint32_t op2)\r
+{\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("smuadx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );\r
+ return(result);\r
+}\r
+\r
+__STATIC_FORCEINLINE uint32_t __SMLAD (uint32_t op1, uint32_t op2, uint32_t op3)\r
+{\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("smlad %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );\r
+ return(result);\r
+}\r
+\r
+__STATIC_FORCEINLINE uint32_t __SMLADX (uint32_t op1, uint32_t op2, uint32_t op3)\r
+{\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("smladx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );\r
+ return(result);\r
+}\r
+\r
+__STATIC_FORCEINLINE uint64_t __SMLALD (uint32_t op1, uint32_t op2, uint64_t acc)\r
+{\r
+ union llreg_u{\r
+ uint32_t w32[2];\r
+ uint64_t w64;\r
+ } llr;\r
+ llr.w64 = acc;\r
+\r
+#ifndef __ARMEB__ /* Little endian */\r
+ __ASM volatile ("smlald %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) );\r
+#else /* Big endian */\r
+ __ASM volatile ("smlald %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) );\r
+#endif\r
+\r
+ return(llr.w64);\r
+}\r
+\r
+__STATIC_FORCEINLINE uint64_t __SMLALDX (uint32_t op1, uint32_t op2, uint64_t acc)\r
+{\r
+ union llreg_u{\r
+ uint32_t w32[2];\r
+ uint64_t w64;\r
+ } llr;\r
+ llr.w64 = acc;\r
+\r
+#ifndef __ARMEB__ /* Little endian */\r
+ __ASM volatile ("smlaldx %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) );\r
+#else /* Big endian */\r
+ __ASM volatile ("smlaldx %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) );\r
+#endif\r
+\r
+ return(llr.w64);\r
+}\r
+\r
+__STATIC_FORCEINLINE uint32_t __SMUSD (uint32_t op1, uint32_t op2)\r
+{\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("smusd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );\r
+ return(result);\r
+}\r
+\r
+__STATIC_FORCEINLINE uint32_t __SMUSDX (uint32_t op1, uint32_t op2)\r
+{\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("smusdx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );\r
+ return(result);\r
+}\r
+\r
+__STATIC_FORCEINLINE uint32_t __SMLSD (uint32_t op1, uint32_t op2, uint32_t op3)\r
+{\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("smlsd %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );\r
+ return(result);\r
+}\r
+\r
+__STATIC_FORCEINLINE uint32_t __SMLSDX (uint32_t op1, uint32_t op2, uint32_t op3)\r
+{\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("smlsdx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );\r
+ return(result);\r
+}\r
+\r
+__STATIC_FORCEINLINE uint64_t __SMLSLD (uint32_t op1, uint32_t op2, uint64_t acc)\r
+{\r
+ union llreg_u{\r
+ uint32_t w32[2];\r
+ uint64_t w64;\r
+ } llr;\r
+ llr.w64 = acc;\r
+\r
+#ifndef __ARMEB__ /* Little endian */\r
+ __ASM volatile ("smlsld %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) );\r
+#else /* Big endian */\r
+ __ASM volatile ("smlsld %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) );\r
+#endif\r
+\r
+ return(llr.w64);\r
+}\r
+\r
+__STATIC_FORCEINLINE uint64_t __SMLSLDX (uint32_t op1, uint32_t op2, uint64_t acc)\r
+{\r
+ union llreg_u{\r
+ uint32_t w32[2];\r
+ uint64_t w64;\r
+ } llr;\r
+ llr.w64 = acc;\r
+\r
+#ifndef __ARMEB__ /* Little endian */\r
+ __ASM volatile ("smlsldx %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) );\r
+#else /* Big endian */\r
+ __ASM volatile ("smlsldx %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) );\r
+#endif\r
+\r
+ return(llr.w64);\r
+}\r
+\r
+__STATIC_FORCEINLINE uint32_t __SEL (uint32_t op1, uint32_t op2)\r
+{\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("sel %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );\r
+ return(result);\r
+}\r
+\r
+__STATIC_FORCEINLINE int32_t __QADD( int32_t op1, int32_t op2)\r
+{\r
+ int32_t result;\r
+\r
+ __ASM volatile ("qadd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );\r
+ return(result);\r
+}\r
+\r
+__STATIC_FORCEINLINE int32_t __QSUB( int32_t op1, int32_t op2)\r
+{\r
+ int32_t result;\r
+\r
+ __ASM volatile ("qsub %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );\r
+ return(result);\r
+}\r
+\r
+#if 0\r
+#define __PKHBT(ARG1,ARG2,ARG3) \\r
+({ \\r
+ uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \\r
+ __ASM ("pkhbt %0, %1, %2, lsl %3" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2), "I" (ARG3) ); \\r
+ __RES; \\r
+ })\r
+\r
+#define __PKHTB(ARG1,ARG2,ARG3) \\r
+({ \\r
+ uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \\r
+ if (ARG3 == 0) \\r
+ __ASM ("pkhtb %0, %1, %2" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2) ); \\r
+ else \\r
+ __ASM ("pkhtb %0, %1, %2, asr %3" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2), "I" (ARG3) ); \\r
+ __RES; \\r
+ })\r
+#endif\r
+\r
+#define __PKHBT(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0x0000FFFFUL) | \\r
+ ((((uint32_t)(ARG2)) << (ARG3)) & 0xFFFF0000UL) )\r
+\r
+#define __PKHTB(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0xFFFF0000UL) | \\r
+ ((((uint32_t)(ARG2)) >> (ARG3)) & 0x0000FFFFUL) )\r
+\r
+__STATIC_FORCEINLINE int32_t __SMMLA (int32_t op1, int32_t op2, int32_t op3)\r
+{\r
+ int32_t result;\r
+\r
+ __ASM volatile ("smmla %0, %1, %2, %3" : "=r" (result): "r" (op1), "r" (op2), "r" (op3) );\r
+ return(result);\r
+}\r
+\r
+#endif /* (__ARM_FEATURE_DSP == 1) */\r
+/*@} end of group CMSIS_SIMD_intrinsics */\r
+\r
+\r
+#pragma GCC diagnostic pop\r
+\r
+#endif /* __CMSIS_GCC_H */\r
--- /dev/null
+/**************************************************************************//**\r
+ * @file cmsis_iccarm.h\r
+ * @brief CMSIS compiler ICCARM (IAR Compiler for Arm) header file\r
+ * @version V5.0.7\r
+ * @date 19. June 2018\r
+ ******************************************************************************/\r
+\r
+//------------------------------------------------------------------------------\r
+//\r
+// Copyright (c) 2017-2018 IAR Systems\r
+//\r
+// Licensed under the Apache License, Version 2.0 (the "License")\r
+// you may not use this file except in compliance with the License.\r
+// You may obtain a copy of the License at\r
+// http://www.apache.org/licenses/LICENSE-2.0\r
+//\r
+// Unless required by applicable law or agreed to in writing, software\r
+// distributed under the License is distributed on an "AS IS" BASIS,\r
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\r
+// See the License for the specific language governing permissions and\r
+// limitations under the License.\r
+//\r
+//------------------------------------------------------------------------------\r
+\r
+\r
+#ifndef __CMSIS_ICCARM_H__\r
+#define __CMSIS_ICCARM_H__\r
+\r
+#ifndef __ICCARM__\r
+ #error This file should only be compiled by ICCARM\r
+#endif\r
+\r
+#pragma system_include\r
+\r
+#define __IAR_FT _Pragma("inline=forced") __intrinsic\r
+\r
+#if (__VER__ >= 8000000)\r
+ #define __ICCARM_V8 1\r
+#else\r
+ #define __ICCARM_V8 0\r
+#endif\r
+\r
+#ifndef __ALIGNED\r
+ #if __ICCARM_V8\r
+ #define __ALIGNED(x) __attribute__((aligned(x)))\r
+ #elif (__VER__ >= 7080000)\r
+ /* Needs IAR language extensions */\r
+ #define __ALIGNED(x) __attribute__((aligned(x)))\r
+ #else\r
+ #warning No compiler specific solution for __ALIGNED.__ALIGNED is ignored.\r
+ #define __ALIGNED(x)\r
+ #endif\r
+#endif\r
+\r
+\r
+/* Define compiler macros for CPU architecture, used in CMSIS 5.\r
+ */\r
+#if __ARM_ARCH_6M__ || __ARM_ARCH_7M__ || __ARM_ARCH_7EM__ || __ARM_ARCH_8M_BASE__ || __ARM_ARCH_8M_MAIN__\r
+/* Macros already defined */\r
+#else\r
+ #if defined(__ARM8M_MAINLINE__) || defined(__ARM8EM_MAINLINE__)\r
+ #define __ARM_ARCH_8M_MAIN__ 1\r
+ #elif defined(__ARM8M_BASELINE__)\r
+ #define __ARM_ARCH_8M_BASE__ 1\r
+ #elif defined(__ARM_ARCH_PROFILE) && __ARM_ARCH_PROFILE == 'M'\r
+ #if __ARM_ARCH == 6\r
+ #define __ARM_ARCH_6M__ 1\r
+ #elif __ARM_ARCH == 7\r
+ #if __ARM_FEATURE_DSP\r
+ #define __ARM_ARCH_7EM__ 1\r
+ #else\r
+ #define __ARM_ARCH_7M__ 1\r
+ #endif\r
+ #endif /* __ARM_ARCH */\r
+ #endif /* __ARM_ARCH_PROFILE == 'M' */\r
+#endif\r
+\r
+/* Alternativ core deduction for older ICCARM's */\r
+#if !defined(__ARM_ARCH_6M__) && !defined(__ARM_ARCH_7M__) && !defined(__ARM_ARCH_7EM__) && \\r
+ !defined(__ARM_ARCH_8M_BASE__) && !defined(__ARM_ARCH_8M_MAIN__)\r
+ #if defined(__ARM6M__) && (__CORE__ == __ARM6M__)\r
+ #define __ARM_ARCH_6M__ 1\r
+ #elif defined(__ARM7M__) && (__CORE__ == __ARM7M__)\r
+ #define __ARM_ARCH_7M__ 1\r
+ #elif defined(__ARM7EM__) && (__CORE__ == __ARM7EM__)\r
+ #define __ARM_ARCH_7EM__ 1\r
+ #elif defined(__ARM8M_BASELINE__) && (__CORE == __ARM8M_BASELINE__)\r
+ #define __ARM_ARCH_8M_BASE__ 1\r
+ #elif defined(__ARM8M_MAINLINE__) && (__CORE == __ARM8M_MAINLINE__)\r
+ #define __ARM_ARCH_8M_MAIN__ 1\r
+ #elif defined(__ARM8EM_MAINLINE__) && (__CORE == __ARM8EM_MAINLINE__)\r
+ #define __ARM_ARCH_8M_MAIN__ 1\r
+ #else\r
+ #error "Unknown target."\r
+ #endif\r
+#endif\r
+\r
+\r
+\r
+#if defined(__ARM_ARCH_6M__) && __ARM_ARCH_6M__==1\r
+ #define __IAR_M0_FAMILY 1\r
+#elif defined(__ARM_ARCH_8M_BASE__) && __ARM_ARCH_8M_BASE__==1\r
+ #define __IAR_M0_FAMILY 1\r
+#else\r
+ #define __IAR_M0_FAMILY 0\r
+#endif\r
+\r
+\r
+#ifndef __ASM\r
+ #define __ASM __asm\r
+#endif\r
+\r
+#ifndef __INLINE\r
+ #define __INLINE inline\r
+#endif\r
+\r
+#ifndef __NO_RETURN\r
+ #if __ICCARM_V8\r
+ #define __NO_RETURN __attribute__((__noreturn__))\r
+ #else\r
+ #define __NO_RETURN _Pragma("object_attribute=__noreturn")\r
+ #endif\r
+#endif\r
+\r
+#ifndef __PACKED\r
+ #if __ICCARM_V8\r
+ #define __PACKED __attribute__((packed, aligned(1)))\r
+ #else\r
+ /* Needs IAR language extensions */\r
+ #define __PACKED __packed\r
+ #endif\r
+#endif\r
+\r
+#ifndef __PACKED_STRUCT\r
+ #if __ICCARM_V8\r
+ #define __PACKED_STRUCT struct __attribute__((packed, aligned(1)))\r
+ #else\r
+ /* Needs IAR language extensions */\r
+ #define __PACKED_STRUCT __packed struct\r
+ #endif\r
+#endif\r
+\r
+#ifndef __PACKED_UNION\r
+ #if __ICCARM_V8\r
+ #define __PACKED_UNION union __attribute__((packed, aligned(1)))\r
+ #else\r
+ /* Needs IAR language extensions */\r
+ #define __PACKED_UNION __packed union\r
+ #endif\r
+#endif\r
+\r
+#ifndef __RESTRICT\r
+ #define __RESTRICT __restrict\r
+#endif\r
+\r
+#ifndef __STATIC_INLINE\r
+ #define __STATIC_INLINE static inline\r
+#endif\r
+\r
+#ifndef __FORCEINLINE\r
+ #define __FORCEINLINE _Pragma("inline=forced")\r
+#endif\r
+\r
+#ifndef __STATIC_FORCEINLINE\r
+ #define __STATIC_FORCEINLINE __FORCEINLINE __STATIC_INLINE\r
+#endif\r
+\r
+#ifndef __UNALIGNED_UINT16_READ\r
+#pragma language=save\r
+#pragma language=extended\r
+__IAR_FT uint16_t __iar_uint16_read(void const *ptr)\r
+{\r
+ return *(__packed uint16_t*)(ptr);\r
+}\r
+#pragma language=restore\r
+#define __UNALIGNED_UINT16_READ(PTR) __iar_uint16_read(PTR)\r
+#endif\r
+\r
+\r
+#ifndef __UNALIGNED_UINT16_WRITE\r
+#pragma language=save\r
+#pragma language=extended\r
+__IAR_FT void __iar_uint16_write(void const *ptr, uint16_t val)\r
+{\r
+ *(__packed uint16_t*)(ptr) = val;;\r
+}\r
+#pragma language=restore\r
+#define __UNALIGNED_UINT16_WRITE(PTR,VAL) __iar_uint16_write(PTR,VAL)\r
+#endif\r
+\r
+#ifndef __UNALIGNED_UINT32_READ\r
+#pragma language=save\r
+#pragma language=extended\r
+__IAR_FT uint32_t __iar_uint32_read(void const *ptr)\r
+{\r
+ return *(__packed uint32_t*)(ptr);\r
+}\r
+#pragma language=restore\r
+#define __UNALIGNED_UINT32_READ(PTR) __iar_uint32_read(PTR)\r
+#endif\r
+\r
+#ifndef __UNALIGNED_UINT32_WRITE\r
+#pragma language=save\r
+#pragma language=extended\r
+__IAR_FT void __iar_uint32_write(void const *ptr, uint32_t val)\r
+{\r
+ *(__packed uint32_t*)(ptr) = val;;\r
+}\r
+#pragma language=restore\r
+#define __UNALIGNED_UINT32_WRITE(PTR,VAL) __iar_uint32_write(PTR,VAL)\r
+#endif\r
+\r
+#ifndef __UNALIGNED_UINT32 /* deprecated */\r
+#pragma language=save\r
+#pragma language=extended\r
+__packed struct __iar_u32 { uint32_t v; };\r
+#pragma language=restore\r
+#define __UNALIGNED_UINT32(PTR) (((struct __iar_u32 *)(PTR))->v)\r
+#endif\r
+\r
+#ifndef __USED\r
+ #if __ICCARM_V8\r
+ #define __USED __attribute__((used))\r
+ #else\r
+ #define __USED _Pragma("__root")\r
+ #endif\r
+#endif\r
+\r
+#ifndef __WEAK\r
+ #if __ICCARM_V8\r
+ #define __WEAK __attribute__((weak))\r
+ #else\r
+ #define __WEAK _Pragma("__weak")\r
+ #endif\r
+#endif\r
+\r
+\r
+#ifndef __ICCARM_INTRINSICS_VERSION__\r
+ #define __ICCARM_INTRINSICS_VERSION__ 0\r
+#endif\r
+\r
+#if __ICCARM_INTRINSICS_VERSION__ == 2\r
+\r
+ #if defined(__CLZ)\r
+ #undef __CLZ\r
+ #endif\r
+ #if defined(__REVSH)\r
+ #undef __REVSH\r
+ #endif\r
+ #if defined(__RBIT)\r
+ #undef __RBIT\r
+ #endif\r
+ #if defined(__SSAT)\r
+ #undef __SSAT\r
+ #endif\r
+ #if defined(__USAT)\r
+ #undef __USAT\r
+ #endif\r
+\r
+ #include "iccarm_builtin.h"\r
+\r
+ #define __disable_fault_irq __iar_builtin_disable_fiq\r
+ #define __disable_irq __iar_builtin_disable_interrupt\r
+ #define __enable_fault_irq __iar_builtin_enable_fiq\r
+ #define __enable_irq __iar_builtin_enable_interrupt\r
+ #define __arm_rsr __iar_builtin_rsr\r
+ #define __arm_wsr __iar_builtin_wsr\r
+\r
+\r
+ #define __get_APSR() (__arm_rsr("APSR"))\r
+ #define __get_BASEPRI() (__arm_rsr("BASEPRI"))\r
+ #define __get_CONTROL() (__arm_rsr("CONTROL"))\r
+ #define __get_FAULTMASK() (__arm_rsr("FAULTMASK"))\r
+\r
+ #if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \\r
+ (defined (__FPU_USED ) && (__FPU_USED == 1U)) )\r
+ #define __get_FPSCR() (__arm_rsr("FPSCR"))\r
+ #define __set_FPSCR(VALUE) (__arm_wsr("FPSCR", (VALUE)))\r
+ #else\r
+ #define __get_FPSCR() ( 0 )\r
+ #define __set_FPSCR(VALUE) ((void)VALUE)\r
+ #endif\r
+\r
+ #define __get_IPSR() (__arm_rsr("IPSR"))\r
+ #define __get_MSP() (__arm_rsr("MSP"))\r
+ #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \\r
+ (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))\r
+ // without main extensions, the non-secure MSPLIM is RAZ/WI\r
+ #define __get_MSPLIM() (0U)\r
+ #else\r
+ #define __get_MSPLIM() (__arm_rsr("MSPLIM"))\r
+ #endif\r
+ #define __get_PRIMASK() (__arm_rsr("PRIMASK"))\r
+ #define __get_PSP() (__arm_rsr("PSP"))\r
+\r
+ #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \\r
+ (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))\r
+ // without main extensions, the non-secure PSPLIM is RAZ/WI\r
+ #define __get_PSPLIM() (0U)\r
+ #else\r
+ #define __get_PSPLIM() (__arm_rsr("PSPLIM"))\r
+ #endif\r
+\r
+ #define __get_xPSR() (__arm_rsr("xPSR"))\r
+\r
+ #define __set_BASEPRI(VALUE) (__arm_wsr("BASEPRI", (VALUE)))\r
+ #define __set_BASEPRI_MAX(VALUE) (__arm_wsr("BASEPRI_MAX", (VALUE)))\r
+ #define __set_CONTROL(VALUE) (__arm_wsr("CONTROL", (VALUE)))\r
+ #define __set_FAULTMASK(VALUE) (__arm_wsr("FAULTMASK", (VALUE)))\r
+ #define __set_MSP(VALUE) (__arm_wsr("MSP", (VALUE)))\r
+\r
+ #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \\r
+ (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))\r
+ // without main extensions, the non-secure MSPLIM is RAZ/WI\r
+ #define __set_MSPLIM(VALUE) ((void)(VALUE))\r
+ #else\r
+ #define __set_MSPLIM(VALUE) (__arm_wsr("MSPLIM", (VALUE)))\r
+ #endif\r
+ #define __set_PRIMASK(VALUE) (__arm_wsr("PRIMASK", (VALUE)))\r
+ #define __set_PSP(VALUE) (__arm_wsr("PSP", (VALUE)))\r
+ #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \\r
+ (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))\r
+ // without main extensions, the non-secure PSPLIM is RAZ/WI\r
+ #define __set_PSPLIM(VALUE) ((void)(VALUE))\r
+ #else\r
+ #define __set_PSPLIM(VALUE) (__arm_wsr("PSPLIM", (VALUE)))\r
+ #endif\r
+\r
+ #define __TZ_get_CONTROL_NS() (__arm_rsr("CONTROL_NS"))\r
+ #define __TZ_set_CONTROL_NS(VALUE) (__arm_wsr("CONTROL_NS", (VALUE)))\r
+ #define __TZ_get_PSP_NS() (__arm_rsr("PSP_NS"))\r
+ #define __TZ_set_PSP_NS(VALUE) (__arm_wsr("PSP_NS", (VALUE)))\r
+ #define __TZ_get_MSP_NS() (__arm_rsr("MSP_NS"))\r
+ #define __TZ_set_MSP_NS(VALUE) (__arm_wsr("MSP_NS", (VALUE)))\r
+ #define __TZ_get_SP_NS() (__arm_rsr("SP_NS"))\r
+ #define __TZ_set_SP_NS(VALUE) (__arm_wsr("SP_NS", (VALUE)))\r
+ #define __TZ_get_PRIMASK_NS() (__arm_rsr("PRIMASK_NS"))\r
+ #define __TZ_set_PRIMASK_NS(VALUE) (__arm_wsr("PRIMASK_NS", (VALUE)))\r
+ #define __TZ_get_BASEPRI_NS() (__arm_rsr("BASEPRI_NS"))\r
+ #define __TZ_set_BASEPRI_NS(VALUE) (__arm_wsr("BASEPRI_NS", (VALUE)))\r
+ #define __TZ_get_FAULTMASK_NS() (__arm_rsr("FAULTMASK_NS"))\r
+ #define __TZ_set_FAULTMASK_NS(VALUE)(__arm_wsr("FAULTMASK_NS", (VALUE)))\r
+\r
+ #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \\r
+ (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))\r
+ // without main extensions, the non-secure PSPLIM is RAZ/WI\r
+ #define __TZ_get_PSPLIM_NS() (0U)\r
+ #define __TZ_set_PSPLIM_NS(VALUE) ((void)(VALUE))\r
+ #else\r
+ #define __TZ_get_PSPLIM_NS() (__arm_rsr("PSPLIM_NS"))\r
+ #define __TZ_set_PSPLIM_NS(VALUE) (__arm_wsr("PSPLIM_NS", (VALUE)))\r
+ #endif\r
+\r
+ #define __TZ_get_MSPLIM_NS() (__arm_rsr("MSPLIM_NS"))\r
+ #define __TZ_set_MSPLIM_NS(VALUE) (__arm_wsr("MSPLIM_NS", (VALUE)))\r
+\r
+ #define __NOP __iar_builtin_no_operation\r
+\r
+ #define __CLZ __iar_builtin_CLZ\r
+ #define __CLREX __iar_builtin_CLREX\r
+\r
+ #define __DMB __iar_builtin_DMB\r
+ #define __DSB __iar_builtin_DSB\r
+ #define __ISB __iar_builtin_ISB\r
+\r
+ #define __LDREXB __iar_builtin_LDREXB\r
+ #define __LDREXH __iar_builtin_LDREXH\r
+ #define __LDREXW __iar_builtin_LDREX\r
+\r
+ #define __RBIT __iar_builtin_RBIT\r
+ #define __REV __iar_builtin_REV\r
+ #define __REV16 __iar_builtin_REV16\r
+\r
+ __IAR_FT int16_t __REVSH(int16_t val)\r
+ {\r
+ return (int16_t) __iar_builtin_REVSH(val);\r
+ }\r
+\r
+ #define __ROR __iar_builtin_ROR\r
+ #define __RRX __iar_builtin_RRX\r
+\r
+ #define __SEV __iar_builtin_SEV\r
+\r
+ #if !__IAR_M0_FAMILY\r
+ #define __SSAT __iar_builtin_SSAT\r
+ #endif\r
+\r
+ #define __STREXB __iar_builtin_STREXB\r
+ #define __STREXH __iar_builtin_STREXH\r
+ #define __STREXW __iar_builtin_STREX\r
+\r
+ #if !__IAR_M0_FAMILY\r
+ #define __USAT __iar_builtin_USAT\r
+ #endif\r
+\r
+ #define __WFE __iar_builtin_WFE\r
+ #define __WFI __iar_builtin_WFI\r
+\r
+ #if __ARM_MEDIA__\r
+ #define __SADD8 __iar_builtin_SADD8\r
+ #define __QADD8 __iar_builtin_QADD8\r
+ #define __SHADD8 __iar_builtin_SHADD8\r
+ #define __UADD8 __iar_builtin_UADD8\r
+ #define __UQADD8 __iar_builtin_UQADD8\r
+ #define __UHADD8 __iar_builtin_UHADD8\r
+ #define __SSUB8 __iar_builtin_SSUB8\r
+ #define __QSUB8 __iar_builtin_QSUB8\r
+ #define __SHSUB8 __iar_builtin_SHSUB8\r
+ #define __USUB8 __iar_builtin_USUB8\r
+ #define __UQSUB8 __iar_builtin_UQSUB8\r
+ #define __UHSUB8 __iar_builtin_UHSUB8\r
+ #define __SADD16 __iar_builtin_SADD16\r
+ #define __QADD16 __iar_builtin_QADD16\r
+ #define __SHADD16 __iar_builtin_SHADD16\r
+ #define __UADD16 __iar_builtin_UADD16\r
+ #define __UQADD16 __iar_builtin_UQADD16\r
+ #define __UHADD16 __iar_builtin_UHADD16\r
+ #define __SSUB16 __iar_builtin_SSUB16\r
+ #define __QSUB16 __iar_builtin_QSUB16\r
+ #define __SHSUB16 __iar_builtin_SHSUB16\r
+ #define __USUB16 __iar_builtin_USUB16\r
+ #define __UQSUB16 __iar_builtin_UQSUB16\r
+ #define __UHSUB16 __iar_builtin_UHSUB16\r
+ #define __SASX __iar_builtin_SASX\r
+ #define __QASX __iar_builtin_QASX\r
+ #define __SHASX __iar_builtin_SHASX\r
+ #define __UASX __iar_builtin_UASX\r
+ #define __UQASX __iar_builtin_UQASX\r
+ #define __UHASX __iar_builtin_UHASX\r
+ #define __SSAX __iar_builtin_SSAX\r
+ #define __QSAX __iar_builtin_QSAX\r
+ #define __SHSAX __iar_builtin_SHSAX\r
+ #define __USAX __iar_builtin_USAX\r
+ #define __UQSAX __iar_builtin_UQSAX\r
+ #define __UHSAX __iar_builtin_UHSAX\r
+ #define __USAD8 __iar_builtin_USAD8\r
+ #define __USADA8 __iar_builtin_USADA8\r
+ #define __SSAT16 __iar_builtin_SSAT16\r
+ #define __USAT16 __iar_builtin_USAT16\r
+ #define __UXTB16 __iar_builtin_UXTB16\r
+ #define __UXTAB16 __iar_builtin_UXTAB16\r
+ #define __SXTB16 __iar_builtin_SXTB16\r
+ #define __SXTAB16 __iar_builtin_SXTAB16\r
+ #define __SMUAD __iar_builtin_SMUAD\r
+ #define __SMUADX __iar_builtin_SMUADX\r
+ #define __SMMLA __iar_builtin_SMMLA\r
+ #define __SMLAD __iar_builtin_SMLAD\r
+ #define __SMLADX __iar_builtin_SMLADX\r
+ #define __SMLALD __iar_builtin_SMLALD\r
+ #define __SMLALDX __iar_builtin_SMLALDX\r
+ #define __SMUSD __iar_builtin_SMUSD\r
+ #define __SMUSDX __iar_builtin_SMUSDX\r
+ #define __SMLSD __iar_builtin_SMLSD\r
+ #define __SMLSDX __iar_builtin_SMLSDX\r
+ #define __SMLSLD __iar_builtin_SMLSLD\r
+ #define __SMLSLDX __iar_builtin_SMLSLDX\r
+ #define __SEL __iar_builtin_SEL\r
+ #define __QADD __iar_builtin_QADD\r
+ #define __QSUB __iar_builtin_QSUB\r
+ #define __PKHBT __iar_builtin_PKHBT\r
+ #define __PKHTB __iar_builtin_PKHTB\r
+ #endif\r
+\r
+#else /* __ICCARM_INTRINSICS_VERSION__ == 2 */\r
+\r
+ #if __IAR_M0_FAMILY\r
+ /* Avoid clash between intrinsics.h and arm_math.h when compiling for Cortex-M0. */\r
+ #define __CLZ __cmsis_iar_clz_not_active\r
+ #define __SSAT __cmsis_iar_ssat_not_active\r
+ #define __USAT __cmsis_iar_usat_not_active\r
+ #define __RBIT __cmsis_iar_rbit_not_active\r
+ #define __get_APSR __cmsis_iar_get_APSR_not_active\r
+ #endif\r
+\r
+\r
+ #if (!((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \\r
+ (defined (__FPU_USED ) && (__FPU_USED == 1U)) ))\r
+ #define __get_FPSCR __cmsis_iar_get_FPSR_not_active\r
+ #define __set_FPSCR __cmsis_iar_set_FPSR_not_active\r
+ #endif\r
+\r
+ #ifdef __INTRINSICS_INCLUDED\r
+ #error intrinsics.h is already included previously!\r
+ #endif\r
+\r
+ #include <intrinsics.h>\r
+\r
+ #if __IAR_M0_FAMILY\r
+ /* Avoid clash between intrinsics.h and arm_math.h when compiling for Cortex-M0. */\r
+ #undef __CLZ\r
+ #undef __SSAT\r
+ #undef __USAT\r
+ #undef __RBIT\r
+ #undef __get_APSR\r
+\r
+ __STATIC_INLINE uint8_t __CLZ(uint32_t data)\r
+ {\r
+ if (data == 0U) { return 32U; }\r
+\r
+ uint32_t count = 0U;\r
+ uint32_t mask = 0x80000000U;\r
+\r
+ while ((data & mask) == 0U)\r
+ {\r
+ count += 1U;\r
+ mask = mask >> 1U;\r
+ }\r
+ return count;\r
+ }\r
+\r
+ __STATIC_INLINE uint32_t __RBIT(uint32_t v)\r
+ {\r
+ uint8_t sc = 31U;\r
+ uint32_t r = v;\r
+ for (v >>= 1U; v; v >>= 1U)\r
+ {\r
+ r <<= 1U;\r
+ r |= v & 1U;\r
+ sc--;\r
+ }\r
+ return (r << sc);\r
+ }\r
+\r
+ __STATIC_INLINE uint32_t __get_APSR(void)\r
+ {\r
+ uint32_t res;\r
+ __asm("MRS %0,APSR" : "=r" (res));\r
+ return res;\r
+ }\r
+\r
+ #endif\r
+\r
+ #if (!((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \\r
+ (defined (__FPU_USED ) && (__FPU_USED == 1U)) ))\r
+ #undef __get_FPSCR\r
+ #undef __set_FPSCR\r
+ #define __get_FPSCR() (0)\r
+ #define __set_FPSCR(VALUE) ((void)VALUE)\r
+ #endif\r
+\r
+ #pragma diag_suppress=Pe940\r
+ #pragma diag_suppress=Pe177\r
+\r
+ #define __enable_irq __enable_interrupt\r
+ #define __disable_irq __disable_interrupt\r
+ #define __NOP __no_operation\r
+\r
+ #define __get_xPSR __get_PSR\r
+\r
+ #if (!defined(__ARM_ARCH_6M__) || __ARM_ARCH_6M__==0)\r
+\r
+ __IAR_FT uint32_t __LDREXW(uint32_t volatile *ptr)\r
+ {\r
+ return __LDREX((unsigned long *)ptr);\r
+ }\r
+\r
+ __IAR_FT uint32_t __STREXW(uint32_t value, uint32_t volatile *ptr)\r
+ {\r
+ return __STREX(value, (unsigned long *)ptr);\r
+ }\r
+ #endif\r
+\r
+\r
+ /* __CORTEX_M is defined in core_cm0.h, core_cm3.h and core_cm4.h. */\r
+ #if (__CORTEX_M >= 0x03)\r
+\r
+ __IAR_FT uint32_t __RRX(uint32_t value)\r
+ {\r
+ uint32_t result;\r
+ __ASM("RRX %0, %1" : "=r"(result) : "r" (value) : "cc");\r
+ return(result);\r
+ }\r
+\r
+ __IAR_FT void __set_BASEPRI_MAX(uint32_t value)\r
+ {\r
+ __asm volatile("MSR BASEPRI_MAX,%0"::"r" (value));\r
+ }\r
+\r
+\r
+ #define __enable_fault_irq __enable_fiq\r
+ #define __disable_fault_irq __disable_fiq\r
+\r
+\r
+ #endif /* (__CORTEX_M >= 0x03) */\r
+\r
+ __IAR_FT uint32_t __ROR(uint32_t op1, uint32_t op2)\r
+ {\r
+ return (op1 >> op2) | (op1 << ((sizeof(op1)*8)-op2));\r
+ }\r
+\r
+ #if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \\r
+ (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) )\r
+\r
+ __IAR_FT uint32_t __get_MSPLIM(void)\r
+ {\r
+ uint32_t res;\r
+ #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \\r
+ (!defined (__ARM_FEATURE_CMSE ) || (__ARM_FEATURE_CMSE < 3)))\r
+ // without main extensions, the non-secure MSPLIM is RAZ/WI\r
+ res = 0U;\r
+ #else\r
+ __asm volatile("MRS %0,MSPLIM" : "=r" (res));\r
+ #endif\r
+ return res;\r
+ }\r
+\r
+ __IAR_FT void __set_MSPLIM(uint32_t value)\r
+ {\r
+ #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \\r
+ (!defined (__ARM_FEATURE_CMSE ) || (__ARM_FEATURE_CMSE < 3)))\r
+ // without main extensions, the non-secure MSPLIM is RAZ/WI\r
+ (void)value;\r
+ #else\r
+ __asm volatile("MSR MSPLIM,%0" :: "r" (value));\r
+ #endif\r
+ }\r
+\r
+ __IAR_FT uint32_t __get_PSPLIM(void)\r
+ {\r
+ uint32_t res;\r
+ #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \\r
+ (!defined (__ARM_FEATURE_CMSE ) || (__ARM_FEATURE_CMSE < 3)))\r
+ // without main extensions, the non-secure PSPLIM is RAZ/WI\r
+ res = 0U;\r
+ #else\r
+ __asm volatile("MRS %0,PSPLIM" : "=r" (res));\r
+ #endif\r
+ return res;\r
+ }\r
+\r
+ __IAR_FT void __set_PSPLIM(uint32_t value)\r
+ {\r
+ #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \\r
+ (!defined (__ARM_FEATURE_CMSE ) || (__ARM_FEATURE_CMSE < 3)))\r
+ // without main extensions, the non-secure PSPLIM is RAZ/WI\r
+ (void)value;\r
+ #else\r
+ __asm volatile("MSR PSPLIM,%0" :: "r" (value));\r
+ #endif\r
+ }\r
+\r
+ __IAR_FT uint32_t __TZ_get_CONTROL_NS(void)\r
+ {\r
+ uint32_t res;\r
+ __asm volatile("MRS %0,CONTROL_NS" : "=r" (res));\r
+ return res;\r
+ }\r
+\r
+ __IAR_FT void __TZ_set_CONTROL_NS(uint32_t value)\r
+ {\r
+ __asm volatile("MSR CONTROL_NS,%0" :: "r" (value));\r
+ }\r
+\r
+ __IAR_FT uint32_t __TZ_get_PSP_NS(void)\r
+ {\r
+ uint32_t res;\r
+ __asm volatile("MRS %0,PSP_NS" : "=r" (res));\r
+ return res;\r
+ }\r
+\r
+ __IAR_FT void __TZ_set_PSP_NS(uint32_t value)\r
+ {\r
+ __asm volatile("MSR PSP_NS,%0" :: "r" (value));\r
+ }\r
+\r
+ __IAR_FT uint32_t __TZ_get_MSP_NS(void)\r
+ {\r
+ uint32_t res;\r
+ __asm volatile("MRS %0,MSP_NS" : "=r" (res));\r
+ return res;\r
+ }\r
+\r
+ __IAR_FT void __TZ_set_MSP_NS(uint32_t value)\r
+ {\r
+ __asm volatile("MSR MSP_NS,%0" :: "r" (value));\r
+ }\r
+\r
+ __IAR_FT uint32_t __TZ_get_SP_NS(void)\r
+ {\r
+ uint32_t res;\r
+ __asm volatile("MRS %0,SP_NS" : "=r" (res));\r
+ return res;\r
+ }\r
+ __IAR_FT void __TZ_set_SP_NS(uint32_t value)\r
+ {\r
+ __asm volatile("MSR SP_NS,%0" :: "r" (value));\r
+ }\r
+\r
+ __IAR_FT uint32_t __TZ_get_PRIMASK_NS(void)\r
+ {\r
+ uint32_t res;\r
+ __asm volatile("MRS %0,PRIMASK_NS" : "=r" (res));\r
+ return res;\r
+ }\r
+\r
+ __IAR_FT void __TZ_set_PRIMASK_NS(uint32_t value)\r
+ {\r
+ __asm volatile("MSR PRIMASK_NS,%0" :: "r" (value));\r
+ }\r
+\r
+ __IAR_FT uint32_t __TZ_get_BASEPRI_NS(void)\r
+ {\r
+ uint32_t res;\r
+ __asm volatile("MRS %0,BASEPRI_NS" : "=r" (res));\r
+ return res;\r
+ }\r
+\r
+ __IAR_FT void __TZ_set_BASEPRI_NS(uint32_t value)\r
+ {\r
+ __asm volatile("MSR BASEPRI_NS,%0" :: "r" (value));\r
+ }\r
+\r
+ __IAR_FT uint32_t __TZ_get_FAULTMASK_NS(void)\r
+ {\r
+ uint32_t res;\r
+ __asm volatile("MRS %0,FAULTMASK_NS" : "=r" (res));\r
+ return res;\r
+ }\r
+\r
+ __IAR_FT void __TZ_set_FAULTMASK_NS(uint32_t value)\r
+ {\r
+ __asm volatile("MSR FAULTMASK_NS,%0" :: "r" (value));\r
+ }\r
+\r
+ __IAR_FT uint32_t __TZ_get_PSPLIM_NS(void)\r
+ {\r
+ uint32_t res;\r
+ #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \\r
+ (!defined (__ARM_FEATURE_CMSE ) || (__ARM_FEATURE_CMSE < 3)))\r
+ // without main extensions, the non-secure PSPLIM is RAZ/WI\r
+ res = 0U;\r
+ #else\r
+ __asm volatile("MRS %0,PSPLIM_NS" : "=r" (res));\r
+ #endif\r
+ return res;\r
+ }\r
+\r
+ __IAR_FT void __TZ_set_PSPLIM_NS(uint32_t value)\r
+ {\r
+ #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \\r
+ (!defined (__ARM_FEATURE_CMSE ) || (__ARM_FEATURE_CMSE < 3)))\r
+ // without main extensions, the non-secure PSPLIM is RAZ/WI\r
+ (void)value;\r
+ #else\r
+ __asm volatile("MSR PSPLIM_NS,%0" :: "r" (value));\r
+ #endif\r
+ }\r
+\r
+ __IAR_FT uint32_t __TZ_get_MSPLIM_NS(void)\r
+ {\r
+ uint32_t res;\r
+ __asm volatile("MRS %0,MSPLIM_NS" : "=r" (res));\r
+ return res;\r
+ }\r
+\r
+ __IAR_FT void __TZ_set_MSPLIM_NS(uint32_t value)\r
+ {\r
+ __asm volatile("MSR MSPLIM_NS,%0" :: "r" (value));\r
+ }\r
+\r
+ #endif /* __ARM_ARCH_8M_MAIN__ or __ARM_ARCH_8M_BASE__ */\r
+\r
+#endif /* __ICCARM_INTRINSICS_VERSION__ == 2 */\r
+\r
+#define __BKPT(value) __asm volatile ("BKPT %0" : : "i"(value))\r
+\r
+#if __IAR_M0_FAMILY\r
+ __STATIC_INLINE int32_t __SSAT(int32_t val, uint32_t sat)\r
+ {\r
+ if ((sat >= 1U) && (sat <= 32U))\r
+ {\r
+ const int32_t max = (int32_t)((1U << (sat - 1U)) - 1U);\r
+ const int32_t min = -1 - max ;\r
+ if (val > max)\r
+ {\r
+ return max;\r
+ }\r
+ else if (val < min)\r
+ {\r
+ return min;\r
+ }\r
+ }\r
+ return val;\r
+ }\r
+\r
+ __STATIC_INLINE uint32_t __USAT(int32_t val, uint32_t sat)\r
+ {\r
+ if (sat <= 31U)\r
+ {\r
+ const uint32_t max = ((1U << sat) - 1U);\r
+ if (val > (int32_t)max)\r
+ {\r
+ return max;\r
+ }\r
+ else if (val < 0)\r
+ {\r
+ return 0U;\r
+ }\r
+ }\r
+ return (uint32_t)val;\r
+ }\r
+#endif\r
+\r
+#if (__CORTEX_M >= 0x03) /* __CORTEX_M is defined in core_cm0.h, core_cm3.h and core_cm4.h. */\r
+\r
+ __IAR_FT uint8_t __LDRBT(volatile uint8_t *addr)\r
+ {\r
+ uint32_t res;\r
+ __ASM("LDRBT %0, [%1]" : "=r" (res) : "r" (addr) : "memory");\r
+ return ((uint8_t)res);\r
+ }\r
+\r
+ __IAR_FT uint16_t __LDRHT(volatile uint16_t *addr)\r
+ {\r
+ uint32_t res;\r
+ __ASM("LDRHT %0, [%1]" : "=r" (res) : "r" (addr) : "memory");\r
+ return ((uint16_t)res);\r
+ }\r
+\r
+ __IAR_FT uint32_t __LDRT(volatile uint32_t *addr)\r
+ {\r
+ uint32_t res;\r
+ __ASM("LDRT %0, [%1]" : "=r" (res) : "r" (addr) : "memory");\r
+ return res;\r
+ }\r
+\r
+ __IAR_FT void __STRBT(uint8_t value, volatile uint8_t *addr)\r
+ {\r
+ __ASM("STRBT %1, [%0]" : : "r" (addr), "r" ((uint32_t)value) : "memory");\r
+ }\r
+\r
+ __IAR_FT void __STRHT(uint16_t value, volatile uint16_t *addr)\r
+ {\r
+ __ASM("STRHT %1, [%0]" : : "r" (addr), "r" ((uint32_t)value) : "memory");\r
+ }\r
+\r
+ __IAR_FT void __STRT(uint32_t value, volatile uint32_t *addr)\r
+ {\r
+ __ASM("STRT %1, [%0]" : : "r" (addr), "r" (value) : "memory");\r
+ }\r
+\r
+#endif /* (__CORTEX_M >= 0x03) */\r
+\r
+#if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \\r
+ (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) )\r
+\r
+\r
+ __IAR_FT uint8_t __LDAB(volatile uint8_t *ptr)\r
+ {\r
+ uint32_t res;\r
+ __ASM volatile ("LDAB %0, [%1]" : "=r" (res) : "r" (ptr) : "memory");\r
+ return ((uint8_t)res);\r
+ }\r
+\r
+ __IAR_FT uint16_t __LDAH(volatile uint16_t *ptr)\r
+ {\r
+ uint32_t res;\r
+ __ASM volatile ("LDAH %0, [%1]" : "=r" (res) : "r" (ptr) : "memory");\r
+ return ((uint16_t)res);\r
+ }\r
+\r
+ __IAR_FT uint32_t __LDA(volatile uint32_t *ptr)\r
+ {\r
+ uint32_t res;\r
+ __ASM volatile ("LDA %0, [%1]" : "=r" (res) : "r" (ptr) : "memory");\r
+ return res;\r
+ }\r
+\r
+ __IAR_FT void __STLB(uint8_t value, volatile uint8_t *ptr)\r
+ {\r
+ __ASM volatile ("STLB %1, [%0]" :: "r" (ptr), "r" (value) : "memory");\r
+ }\r
+\r
+ __IAR_FT void __STLH(uint16_t value, volatile uint16_t *ptr)\r
+ {\r
+ __ASM volatile ("STLH %1, [%0]" :: "r" (ptr), "r" (value) : "memory");\r
+ }\r
+\r
+ __IAR_FT void __STL(uint32_t value, volatile uint32_t *ptr)\r
+ {\r
+ __ASM volatile ("STL %1, [%0]" :: "r" (ptr), "r" (value) : "memory");\r
+ }\r
+\r
+ __IAR_FT uint8_t __LDAEXB(volatile uint8_t *ptr)\r
+ {\r
+ uint32_t res;\r
+ __ASM volatile ("LDAEXB %0, [%1]" : "=r" (res) : "r" (ptr) : "memory");\r
+ return ((uint8_t)res);\r
+ }\r
+\r
+ __IAR_FT uint16_t __LDAEXH(volatile uint16_t *ptr)\r
+ {\r
+ uint32_t res;\r
+ __ASM volatile ("LDAEXH %0, [%1]" : "=r" (res) : "r" (ptr) : "memory");\r
+ return ((uint16_t)res);\r
+ }\r
+\r
+ __IAR_FT uint32_t __LDAEX(volatile uint32_t *ptr)\r
+ {\r
+ uint32_t res;\r
+ __ASM volatile ("LDAEX %0, [%1]" : "=r" (res) : "r" (ptr) : "memory");\r
+ return res;\r
+ }\r
+\r
+ __IAR_FT uint32_t __STLEXB(uint8_t value, volatile uint8_t *ptr)\r
+ {\r
+ uint32_t res;\r
+ __ASM volatile ("STLEXB %0, %2, [%1]" : "=r" (res) : "r" (ptr), "r" (value) : "memory");\r
+ return res;\r
+ }\r
+\r
+ __IAR_FT uint32_t __STLEXH(uint16_t value, volatile uint16_t *ptr)\r
+ {\r
+ uint32_t res;\r
+ __ASM volatile ("STLEXH %0, %2, [%1]" : "=r" (res) : "r" (ptr), "r" (value) : "memory");\r
+ return res;\r
+ }\r
+\r
+ __IAR_FT uint32_t __STLEX(uint32_t value, volatile uint32_t *ptr)\r
+ {\r
+ uint32_t res;\r
+ __ASM volatile ("STLEX %0, %2, [%1]" : "=r" (res) : "r" (ptr), "r" (value) : "memory");\r
+ return res;\r
+ }\r
+\r
+#endif /* __ARM_ARCH_8M_MAIN__ or __ARM_ARCH_8M_BASE__ */\r
+\r
+#undef __IAR_FT\r
+#undef __IAR_M0_FAMILY\r
+#undef __ICCARM_V8\r
+\r
+#pragma diag_default=Pe940\r
+#pragma diag_default=Pe177\r
+\r
+#endif /* __CMSIS_ICCARM_H__ */\r
--- /dev/null
+/**************************************************************************//**\r
+ * @file cmsis_version.h\r
+ * @brief CMSIS Core(M) Version definitions\r
+ * @version V5.0.2\r
+ * @date 19. April 2017\r
+ ******************************************************************************/\r
+/*\r
+ * Copyright (c) 2009-2017 ARM Limited. All rights reserved.\r
+ *\r
+ * SPDX-License-Identifier: Apache-2.0\r
+ *\r
+ * Licensed under the Apache License, Version 2.0 (the License); you may\r
+ * not use this file except in compliance with the License.\r
+ * You may obtain a copy of the License at\r
+ *\r
+ * www.apache.org/licenses/LICENSE-2.0\r
+ *\r
+ * Unless required by applicable law or agreed to in writing, software\r
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT\r
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\r
+ * See the License for the specific language governing permissions and\r
+ * limitations under the License.\r
+ */\r
+\r
+#if defined ( __ICCARM__ )\r
+ #pragma system_include /* treat file as system include file for MISRA check */\r
+#elif defined (__clang__)\r
+ #pragma clang system_header /* treat file as system include file */\r
+#endif\r
+\r
+#ifndef __CMSIS_VERSION_H\r
+#define __CMSIS_VERSION_H\r
+\r
+/* CMSIS Version definitions */\r
+#define __CM_CMSIS_VERSION_MAIN ( 5U) /*!< [31:16] CMSIS Core(M) main version */\r
+#define __CM_CMSIS_VERSION_SUB ( 1U) /*!< [15:0] CMSIS Core(M) sub version */\r
+#define __CM_CMSIS_VERSION ((__CM_CMSIS_VERSION_MAIN << 16U) | \\r
+ __CM_CMSIS_VERSION_SUB ) /*!< CMSIS Core(M) version number */\r
+#endif\r
--- /dev/null
+/**************************************************************************//**\r
+ * @file core_armv8mbl.h\r
+ * @brief CMSIS Armv8-M Baseline Core Peripheral Access Layer Header File\r
+ * @version V5.0.7\r
+ * @date 22. June 2018\r
+ ******************************************************************************/\r
+/*\r
+ * Copyright (c) 2009-2018 Arm Limited. All rights reserved.\r
+ *\r
+ * SPDX-License-Identifier: Apache-2.0\r
+ *\r
+ * Licensed under the Apache License, Version 2.0 (the License); you may\r
+ * not use this file except in compliance with the License.\r
+ * You may obtain a copy of the License at\r
+ *\r
+ * www.apache.org/licenses/LICENSE-2.0\r
+ *\r
+ * Unless required by applicable law or agreed to in writing, software\r
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT\r
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\r
+ * See the License for the specific language governing permissions and\r
+ * limitations under the License.\r
+ */\r
+\r
+#if defined ( __ICCARM__ )\r
+ #pragma system_include /* treat file as system include file for MISRA check */\r
+#elif defined (__clang__)\r
+ #pragma clang system_header /* treat file as system include file */\r
+#endif\r
+\r
+#ifndef __CORE_ARMV8MBL_H_GENERIC\r
+#define __CORE_ARMV8MBL_H_GENERIC\r
+\r
+#include <stdint.h>\r
+\r
+#ifdef __cplusplus\r
+ extern "C" {\r
+#endif\r
+\r
+/**\r
+ \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions\r
+ CMSIS violates the following MISRA-C:2004 rules:\r
+\r
+ \li Required Rule 8.5, object/function definition in header file.<br>\r
+ Function definitions in header files are used to allow 'inlining'.\r
+\r
+ \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>\r
+ Unions are used for effective representation of core registers.\r
+\r
+ \li Advisory Rule 19.7, Function-like macro defined.<br>\r
+ Function-like macros are used to allow more efficient code.\r
+ */\r
+\r
+\r
+/*******************************************************************************\r
+ * CMSIS definitions\r
+ ******************************************************************************/\r
+/**\r
+ \ingroup Cortex_ARMv8MBL\r
+ @{\r
+ */\r
+\r
+#include "cmsis_version.h"\r
+\r
+/* CMSIS definitions */\r
+#define __ARMv8MBL_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */\r
+#define __ARMv8MBL_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */\r
+#define __ARMv8MBL_CMSIS_VERSION ((__ARMv8MBL_CMSIS_VERSION_MAIN << 16U) | \\r
+ __ARMv8MBL_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */\r
+\r
+#define __CORTEX_M ( 2U) /*!< Cortex-M Core */\r
+\r
+/** __FPU_USED indicates whether an FPU is used or not.\r
+ This core does not support an FPU at all\r
+*/\r
+#define __FPU_USED 0U\r
+\r
+#if defined ( __CC_ARM )\r
+ #if defined __TARGET_FPU_VFP\r
+ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"\r
+ #endif\r
+\r
+#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)\r
+ #if defined __ARM_PCS_VFP\r
+ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"\r
+ #endif\r
+\r
+#elif defined ( __GNUC__ )\r
+ #if defined (__VFP_FP__) && !defined(__SOFTFP__)\r
+ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"\r
+ #endif\r
+\r
+#elif defined ( __ICCARM__ )\r
+ #if defined __ARMVFP__\r
+ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"\r
+ #endif\r
+\r
+#elif defined ( __TI_ARM__ )\r
+ #if defined __TI_VFP_SUPPORT__\r
+ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"\r
+ #endif\r
+\r
+#elif defined ( __TASKING__ )\r
+ #if defined __FPU_VFP__\r
+ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"\r
+ #endif\r
+\r
+#elif defined ( __CSMC__ )\r
+ #if ( __CSMC__ & 0x400U)\r
+ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"\r
+ #endif\r
+\r
+#endif\r
+\r
+#include "cmsis_compiler.h" /* CMSIS compiler specific defines */\r
+\r
+\r
+#ifdef __cplusplus\r
+}\r
+#endif\r
+\r
+#endif /* __CORE_ARMV8MBL_H_GENERIC */\r
+\r
+#ifndef __CMSIS_GENERIC\r
+\r
+#ifndef __CORE_ARMV8MBL_H_DEPENDANT\r
+#define __CORE_ARMV8MBL_H_DEPENDANT\r
+\r
+#ifdef __cplusplus\r
+ extern "C" {\r
+#endif\r
+\r
+/* check device defines and use defaults */\r
+#if defined __CHECK_DEVICE_DEFINES\r
+ #ifndef __ARMv8MBL_REV\r
+ #define __ARMv8MBL_REV 0x0000U\r
+ #warning "__ARMv8MBL_REV not defined in device header file; using default!"\r
+ #endif\r
+\r
+ #ifndef __FPU_PRESENT\r
+ #define __FPU_PRESENT 0U\r
+ #warning "__FPU_PRESENT not defined in device header file; using default!"\r
+ #endif\r
+\r
+ #ifndef __MPU_PRESENT\r
+ #define __MPU_PRESENT 0U\r
+ #warning "__MPU_PRESENT not defined in device header file; using default!"\r
+ #endif\r
+\r
+ #ifndef __SAUREGION_PRESENT\r
+ #define __SAUREGION_PRESENT 0U\r
+ #warning "__SAUREGION_PRESENT not defined in device header file; using default!"\r
+ #endif\r
+\r
+ #ifndef __VTOR_PRESENT\r
+ #define __VTOR_PRESENT 0U\r
+ #warning "__VTOR_PRESENT not defined in device header file; using default!"\r
+ #endif\r
+\r
+ #ifndef __NVIC_PRIO_BITS\r
+ #define __NVIC_PRIO_BITS 2U\r
+ #warning "__NVIC_PRIO_BITS not defined in device header file; using default!"\r
+ #endif\r
+\r
+ #ifndef __Vendor_SysTickConfig\r
+ #define __Vendor_SysTickConfig 0U\r
+ #warning "__Vendor_SysTickConfig not defined in device header file; using default!"\r
+ #endif\r
+\r
+ #ifndef __ETM_PRESENT\r
+ #define __ETM_PRESENT 0U\r
+ #warning "__ETM_PRESENT not defined in device header file; using default!"\r
+ #endif\r
+\r
+ #ifndef __MTB_PRESENT\r
+ #define __MTB_PRESENT 0U\r
+ #warning "__MTB_PRESENT not defined in device header file; using default!"\r
+ #endif\r
+\r
+#endif\r
+\r
+/* IO definitions (access restrictions to peripheral registers) */\r
+/**\r
+ \defgroup CMSIS_glob_defs CMSIS Global Defines\r
+\r
+ <strong>IO Type Qualifiers</strong> are used\r
+ \li to specify the access to peripheral variables.\r
+ \li for automatic generation of peripheral register debug information.\r
+*/\r
+#ifdef __cplusplus\r
+ #define __I volatile /*!< Defines 'read only' permissions */\r
+#else\r
+ #define __I volatile const /*!< Defines 'read only' permissions */\r
+#endif\r
+#define __O volatile /*!< Defines 'write only' permissions */\r
+#define __IO volatile /*!< Defines 'read / write' permissions */\r
+\r
+/* following defines should be used for structure members */\r
+#define __IM volatile const /*! Defines 'read only' structure member permissions */\r
+#define __OM volatile /*! Defines 'write only' structure member permissions */\r
+#define __IOM volatile /*! Defines 'read / write' structure member permissions */\r
+\r
+/*@} end of group ARMv8MBL */\r
+\r
+\r
+\r
+/*******************************************************************************\r
+ * Register Abstraction\r
+ Core Register contain:\r
+ - Core Register\r
+ - Core NVIC Register\r
+ - Core SCB Register\r
+ - Core SysTick Register\r
+ - Core Debug Register\r
+ - Core MPU Register\r
+ - Core SAU Register\r
+ ******************************************************************************/\r
+/**\r
+ \defgroup CMSIS_core_register Defines and Type Definitions\r
+ \brief Type definitions and defines for Cortex-M processor based devices.\r
+*/\r
+\r
+/**\r
+ \ingroup CMSIS_core_register\r
+ \defgroup CMSIS_CORE Status and Control Registers\r
+ \brief Core Register type definitions.\r
+ @{\r
+ */\r
+\r
+/**\r
+ \brief Union type to access the Application Program Status Register (APSR).\r
+ */\r
+typedef union\r
+{\r
+ struct\r
+ {\r
+ uint32_t _reserved0:28; /*!< bit: 0..27 Reserved */\r
+ uint32_t V:1; /*!< bit: 28 Overflow condition code flag */\r
+ uint32_t C:1; /*!< bit: 29 Carry condition code flag */\r
+ uint32_t Z:1; /*!< bit: 30 Zero condition code flag */\r
+ uint32_t N:1; /*!< bit: 31 Negative condition code flag */\r
+ } b; /*!< Structure used for bit access */\r
+ uint32_t w; /*!< Type used for word access */\r
+} APSR_Type;\r
+\r
+/* APSR Register Definitions */\r
+#define APSR_N_Pos 31U /*!< APSR: N Position */\r
+#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */\r
+\r
+#define APSR_Z_Pos 30U /*!< APSR: Z Position */\r
+#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */\r
+\r
+#define APSR_C_Pos 29U /*!< APSR: C Position */\r
+#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */\r
+\r
+#define APSR_V_Pos 28U /*!< APSR: V Position */\r
+#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */\r
+\r
+\r
+/**\r
+ \brief Union type to access the Interrupt Program Status Register (IPSR).\r
+ */\r
+typedef union\r
+{\r
+ struct\r
+ {\r
+ uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */\r
+ uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */\r
+ } b; /*!< Structure used for bit access */\r
+ uint32_t w; /*!< Type used for word access */\r
+} IPSR_Type;\r
+\r
+/* IPSR Register Definitions */\r
+#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */\r
+#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */\r
+\r
+\r
+/**\r
+ \brief Union type to access the Special-Purpose Program Status Registers (xPSR).\r
+ */\r
+typedef union\r
+{\r
+ struct\r
+ {\r
+ uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */\r
+ uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */\r
+ uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */\r
+ uint32_t _reserved1:3; /*!< bit: 25..27 Reserved */\r
+ uint32_t V:1; /*!< bit: 28 Overflow condition code flag */\r
+ uint32_t C:1; /*!< bit: 29 Carry condition code flag */\r
+ uint32_t Z:1; /*!< bit: 30 Zero condition code flag */\r
+ uint32_t N:1; /*!< bit: 31 Negative condition code flag */\r
+ } b; /*!< Structure used for bit access */\r
+ uint32_t w; /*!< Type used for word access */\r
+} xPSR_Type;\r
+\r
+/* xPSR Register Definitions */\r
+#define xPSR_N_Pos 31U /*!< xPSR: N Position */\r
+#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */\r
+\r
+#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */\r
+#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */\r
+\r
+#define xPSR_C_Pos 29U /*!< xPSR: C Position */\r
+#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */\r
+\r
+#define xPSR_V_Pos 28U /*!< xPSR: V Position */\r
+#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */\r
+\r
+#define xPSR_T_Pos 24U /*!< xPSR: T Position */\r
+#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */\r
+\r
+#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */\r
+#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */\r
+\r
+\r
+/**\r
+ \brief Union type to access the Control Registers (CONTROL).\r
+ */\r
+typedef union\r
+{\r
+ struct\r
+ {\r
+ uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */\r
+ uint32_t SPSEL:1; /*!< bit: 1 Stack-pointer select */\r
+ uint32_t _reserved1:30; /*!< bit: 2..31 Reserved */\r
+ } b; /*!< Structure used for bit access */\r
+ uint32_t w; /*!< Type used for word access */\r
+} CONTROL_Type;\r
+\r
+/* CONTROL Register Definitions */\r
+#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */\r
+#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */\r
+\r
+#define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */\r
+#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */\r
+\r
+/*@} end of group CMSIS_CORE */\r
+\r
+\r
+/**\r
+ \ingroup CMSIS_core_register\r
+ \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC)\r
+ \brief Type definitions for the NVIC Registers\r
+ @{\r
+ */\r
+\r
+/**\r
+ \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC).\r
+ */\r
+typedef struct\r
+{\r
+ __IOM uint32_t ISER[16U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */\r
+ uint32_t RESERVED0[16U];\r
+ __IOM uint32_t ICER[16U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */\r
+ uint32_t RSERVED1[16U];\r
+ __IOM uint32_t ISPR[16U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */\r
+ uint32_t RESERVED2[16U];\r
+ __IOM uint32_t ICPR[16U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */\r
+ uint32_t RESERVED3[16U];\r
+ __IOM uint32_t IABR[16U]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */\r
+ uint32_t RESERVED4[16U];\r
+ __IOM uint32_t ITNS[16U]; /*!< Offset: 0x280 (R/W) Interrupt Non-Secure State Register */\r
+ uint32_t RESERVED5[16U];\r
+ __IOM uint32_t IPR[124U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register */\r
+} NVIC_Type;\r
+\r
+/*@} end of group CMSIS_NVIC */\r
+\r
+\r
+/**\r
+ \ingroup CMSIS_core_register\r
+ \defgroup CMSIS_SCB System Control Block (SCB)\r
+ \brief Type definitions for the System Control Block Registers\r
+ @{\r
+ */\r
+\r
+/**\r
+ \brief Structure type to access the System Control Block (SCB).\r
+ */\r
+typedef struct\r
+{\r
+ __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */\r
+ __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */\r
+#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U)\r
+ __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */\r
+#else\r
+ uint32_t RESERVED0;\r
+#endif\r
+ __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */\r
+ __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */\r
+ __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */\r
+ uint32_t RESERVED1;\r
+ __IOM uint32_t SHPR[2U]; /*!< Offset: 0x01C (R/W) System Handlers Priority Registers. [0] is RESERVED */\r
+ __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */\r
+} SCB_Type;\r
+\r
+/* SCB CPUID Register Definitions */\r
+#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */\r
+#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */\r
+\r
+#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */\r
+#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */\r
+\r
+#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */\r
+#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */\r
+\r
+#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */\r
+#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */\r
+\r
+#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */\r
+#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */\r
+\r
+/* SCB Interrupt Control State Register Definitions */\r
+#define SCB_ICSR_PENDNMISET_Pos 31U /*!< SCB ICSR: PENDNMISET Position */\r
+#define SCB_ICSR_PENDNMISET_Msk (1UL << SCB_ICSR_PENDNMISET_Pos) /*!< SCB ICSR: PENDNMISET Mask */\r
+\r
+#define SCB_ICSR_NMIPENDSET_Pos SCB_ICSR_PENDNMISET_Pos /*!< SCB ICSR: NMIPENDSET Position, backward compatibility */\r
+#define SCB_ICSR_NMIPENDSET_Msk SCB_ICSR_PENDNMISET_Msk /*!< SCB ICSR: NMIPENDSET Mask, backward compatibility */\r
+\r
+#define SCB_ICSR_PENDNMICLR_Pos 30U /*!< SCB ICSR: PENDNMICLR Position */\r
+#define SCB_ICSR_PENDNMICLR_Msk (1UL << SCB_ICSR_PENDNMICLR_Pos) /*!< SCB ICSR: PENDNMICLR Mask */\r
+\r
+#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */\r
+#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */\r
+\r
+#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */\r
+#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */\r
+\r
+#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */\r
+#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */\r
+\r
+#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */\r
+#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */\r
+\r
+#define SCB_ICSR_STTNS_Pos 24U /*!< SCB ICSR: STTNS Position (Security Extension) */\r
+#define SCB_ICSR_STTNS_Msk (1UL << SCB_ICSR_STTNS_Pos) /*!< SCB ICSR: STTNS Mask (Security Extension) */\r
+\r
+#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */\r
+#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */\r
+\r
+#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */\r
+#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */\r
+\r
+#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */\r
+#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */\r
+\r
+#define SCB_ICSR_RETTOBASE_Pos 11U /*!< SCB ICSR: RETTOBASE Position */\r
+#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */\r
+\r
+#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */\r
+#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */\r
+\r
+#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U)\r
+/* SCB Vector Table Offset Register Definitions */\r
+#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */\r
+#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */\r
+#endif\r
+\r
+/* SCB Application Interrupt and Reset Control Register Definitions */\r
+#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */\r
+#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */\r
+\r
+#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */\r
+#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */\r
+\r
+#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */\r
+#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */\r
+\r
+#define SCB_AIRCR_PRIS_Pos 14U /*!< SCB AIRCR: PRIS Position */\r
+#define SCB_AIRCR_PRIS_Msk (1UL << SCB_AIRCR_PRIS_Pos) /*!< SCB AIRCR: PRIS Mask */\r
+\r
+#define SCB_AIRCR_BFHFNMINS_Pos 13U /*!< SCB AIRCR: BFHFNMINS Position */\r
+#define SCB_AIRCR_BFHFNMINS_Msk (1UL << SCB_AIRCR_BFHFNMINS_Pos) /*!< SCB AIRCR: BFHFNMINS Mask */\r
+\r
+#define SCB_AIRCR_SYSRESETREQS_Pos 3U /*!< SCB AIRCR: SYSRESETREQS Position */\r
+#define SCB_AIRCR_SYSRESETREQS_Msk (1UL << SCB_AIRCR_SYSRESETREQS_Pos) /*!< SCB AIRCR: SYSRESETREQS Mask */\r
+\r
+#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */\r
+#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */\r
+\r
+#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */\r
+#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */\r
+\r
+/* SCB System Control Register Definitions */\r
+#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */\r
+#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */\r
+\r
+#define SCB_SCR_SLEEPDEEPS_Pos 3U /*!< SCB SCR: SLEEPDEEPS Position */\r
+#define SCB_SCR_SLEEPDEEPS_Msk (1UL << SCB_SCR_SLEEPDEEPS_Pos) /*!< SCB SCR: SLEEPDEEPS Mask */\r
+\r
+#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */\r
+#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */\r
+\r
+#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */\r
+#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */\r
+\r
+/* SCB Configuration Control Register Definitions */\r
+#define SCB_CCR_BP_Pos 18U /*!< SCB CCR: BP Position */\r
+#define SCB_CCR_BP_Msk (1UL << SCB_CCR_BP_Pos) /*!< SCB CCR: BP Mask */\r
+\r
+#define SCB_CCR_IC_Pos 17U /*!< SCB CCR: IC Position */\r
+#define SCB_CCR_IC_Msk (1UL << SCB_CCR_IC_Pos) /*!< SCB CCR: IC Mask */\r
+\r
+#define SCB_CCR_DC_Pos 16U /*!< SCB CCR: DC Position */\r
+#define SCB_CCR_DC_Msk (1UL << SCB_CCR_DC_Pos) /*!< SCB CCR: DC Mask */\r
+\r
+#define SCB_CCR_STKOFHFNMIGN_Pos 10U /*!< SCB CCR: STKOFHFNMIGN Position */\r
+#define SCB_CCR_STKOFHFNMIGN_Msk (1UL << SCB_CCR_STKOFHFNMIGN_Pos) /*!< SCB CCR: STKOFHFNMIGN Mask */\r
+\r
+#define SCB_CCR_BFHFNMIGN_Pos 8U /*!< SCB CCR: BFHFNMIGN Position */\r
+#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */\r
+\r
+#define SCB_CCR_DIV_0_TRP_Pos 4U /*!< SCB CCR: DIV_0_TRP Position */\r
+#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */\r
+\r
+#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */\r
+#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */\r
+\r
+#define SCB_CCR_USERSETMPEND_Pos 1U /*!< SCB CCR: USERSETMPEND Position */\r
+#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */\r
+\r
+/* SCB System Handler Control and State Register Definitions */\r
+#define SCB_SHCSR_HARDFAULTPENDED_Pos 21U /*!< SCB SHCSR: HARDFAULTPENDED Position */\r
+#define SCB_SHCSR_HARDFAULTPENDED_Msk (1UL << SCB_SHCSR_HARDFAULTPENDED_Pos) /*!< SCB SHCSR: HARDFAULTPENDED Mask */\r
+\r
+#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */\r
+#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */\r
+\r
+#define SCB_SHCSR_SYSTICKACT_Pos 11U /*!< SCB SHCSR: SYSTICKACT Position */\r
+#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */\r
+\r
+#define SCB_SHCSR_PENDSVACT_Pos 10U /*!< SCB SHCSR: PENDSVACT Position */\r
+#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */\r
+\r
+#define SCB_SHCSR_SVCALLACT_Pos 7U /*!< SCB SHCSR: SVCALLACT Position */\r
+#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */\r
+\r
+#define SCB_SHCSR_NMIACT_Pos 5U /*!< SCB SHCSR: NMIACT Position */\r
+#define SCB_SHCSR_NMIACT_Msk (1UL << SCB_SHCSR_NMIACT_Pos) /*!< SCB SHCSR: NMIACT Mask */\r
+\r
+#define SCB_SHCSR_HARDFAULTACT_Pos 2U /*!< SCB SHCSR: HARDFAULTACT Position */\r
+#define SCB_SHCSR_HARDFAULTACT_Msk (1UL << SCB_SHCSR_HARDFAULTACT_Pos) /*!< SCB SHCSR: HARDFAULTACT Mask */\r
+\r
+/*@} end of group CMSIS_SCB */\r
+\r
+\r
+/**\r
+ \ingroup CMSIS_core_register\r
+ \defgroup CMSIS_SysTick System Tick Timer (SysTick)\r
+ \brief Type definitions for the System Timer Registers.\r
+ @{\r
+ */\r
+\r
+/**\r
+ \brief Structure type to access the System Timer (SysTick).\r
+ */\r
+typedef struct\r
+{\r
+ __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */\r
+ __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */\r
+ __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */\r
+ __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */\r
+} SysTick_Type;\r
+\r
+/* SysTick Control / Status Register Definitions */\r
+#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */\r
+#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */\r
+\r
+#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */\r
+#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */\r
+\r
+#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */\r
+#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */\r
+\r
+#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */\r
+#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */\r
+\r
+/* SysTick Reload Register Definitions */\r
+#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */\r
+#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */\r
+\r
+/* SysTick Current Register Definitions */\r
+#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */\r
+#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */\r
+\r
+/* SysTick Calibration Register Definitions */\r
+#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */\r
+#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */\r
+\r
+#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */\r
+#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */\r
+\r
+#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */\r
+#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */\r
+\r
+/*@} end of group CMSIS_SysTick */\r
+\r
+\r
+/**\r
+ \ingroup CMSIS_core_register\r
+ \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT)\r
+ \brief Type definitions for the Data Watchpoint and Trace (DWT)\r
+ @{\r
+ */\r
+\r
+/**\r
+ \brief Structure type to access the Data Watchpoint and Trace Register (DWT).\r
+ */\r
+typedef struct\r
+{\r
+ __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */\r
+ uint32_t RESERVED0[6U];\r
+ __IM uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */\r
+ __IOM uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */\r
+ uint32_t RESERVED1[1U];\r
+ __IOM uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */\r
+ uint32_t RESERVED2[1U];\r
+ __IOM uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */\r
+ uint32_t RESERVED3[1U];\r
+ __IOM uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */\r
+ uint32_t RESERVED4[1U];\r
+ __IOM uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */\r
+ uint32_t RESERVED5[1U];\r
+ __IOM uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */\r
+ uint32_t RESERVED6[1U];\r
+ __IOM uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */\r
+ uint32_t RESERVED7[1U];\r
+ __IOM uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */\r
+ uint32_t RESERVED8[1U];\r
+ __IOM uint32_t COMP4; /*!< Offset: 0x060 (R/W) Comparator Register 4 */\r
+ uint32_t RESERVED9[1U];\r
+ __IOM uint32_t FUNCTION4; /*!< Offset: 0x068 (R/W) Function Register 4 */\r
+ uint32_t RESERVED10[1U];\r
+ __IOM uint32_t COMP5; /*!< Offset: 0x070 (R/W) Comparator Register 5 */\r
+ uint32_t RESERVED11[1U];\r
+ __IOM uint32_t FUNCTION5; /*!< Offset: 0x078 (R/W) Function Register 5 */\r
+ uint32_t RESERVED12[1U];\r
+ __IOM uint32_t COMP6; /*!< Offset: 0x080 (R/W) Comparator Register 6 */\r
+ uint32_t RESERVED13[1U];\r
+ __IOM uint32_t FUNCTION6; /*!< Offset: 0x088 (R/W) Function Register 6 */\r
+ uint32_t RESERVED14[1U];\r
+ __IOM uint32_t COMP7; /*!< Offset: 0x090 (R/W) Comparator Register 7 */\r
+ uint32_t RESERVED15[1U];\r
+ __IOM uint32_t FUNCTION7; /*!< Offset: 0x098 (R/W) Function Register 7 */\r
+ uint32_t RESERVED16[1U];\r
+ __IOM uint32_t COMP8; /*!< Offset: 0x0A0 (R/W) Comparator Register 8 */\r
+ uint32_t RESERVED17[1U];\r
+ __IOM uint32_t FUNCTION8; /*!< Offset: 0x0A8 (R/W) Function Register 8 */\r
+ uint32_t RESERVED18[1U];\r
+ __IOM uint32_t COMP9; /*!< Offset: 0x0B0 (R/W) Comparator Register 9 */\r
+ uint32_t RESERVED19[1U];\r
+ __IOM uint32_t FUNCTION9; /*!< Offset: 0x0B8 (R/W) Function Register 9 */\r
+ uint32_t RESERVED20[1U];\r
+ __IOM uint32_t COMP10; /*!< Offset: 0x0C0 (R/W) Comparator Register 10 */\r
+ uint32_t RESERVED21[1U];\r
+ __IOM uint32_t FUNCTION10; /*!< Offset: 0x0C8 (R/W) Function Register 10 */\r
+ uint32_t RESERVED22[1U];\r
+ __IOM uint32_t COMP11; /*!< Offset: 0x0D0 (R/W) Comparator Register 11 */\r
+ uint32_t RESERVED23[1U];\r
+ __IOM uint32_t FUNCTION11; /*!< Offset: 0x0D8 (R/W) Function Register 11 */\r
+ uint32_t RESERVED24[1U];\r
+ __IOM uint32_t COMP12; /*!< Offset: 0x0E0 (R/W) Comparator Register 12 */\r
+ uint32_t RESERVED25[1U];\r
+ __IOM uint32_t FUNCTION12; /*!< Offset: 0x0E8 (R/W) Function Register 12 */\r
+ uint32_t RESERVED26[1U];\r
+ __IOM uint32_t COMP13; /*!< Offset: 0x0F0 (R/W) Comparator Register 13 */\r
+ uint32_t RESERVED27[1U];\r
+ __IOM uint32_t FUNCTION13; /*!< Offset: 0x0F8 (R/W) Function Register 13 */\r
+ uint32_t RESERVED28[1U];\r
+ __IOM uint32_t COMP14; /*!< Offset: 0x100 (R/W) Comparator Register 14 */\r
+ uint32_t RESERVED29[1U];\r
+ __IOM uint32_t FUNCTION14; /*!< Offset: 0x108 (R/W) Function Register 14 */\r
+ uint32_t RESERVED30[1U];\r
+ __IOM uint32_t COMP15; /*!< Offset: 0x110 (R/W) Comparator Register 15 */\r
+ uint32_t RESERVED31[1U];\r
+ __IOM uint32_t FUNCTION15; /*!< Offset: 0x118 (R/W) Function Register 15 */\r
+} DWT_Type;\r
+\r
+/* DWT Control Register Definitions */\r
+#define DWT_CTRL_NUMCOMP_Pos 28U /*!< DWT CTRL: NUMCOMP Position */\r
+#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */\r
+\r
+#define DWT_CTRL_NOTRCPKT_Pos 27U /*!< DWT CTRL: NOTRCPKT Position */\r
+#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */\r
+\r
+#define DWT_CTRL_NOEXTTRIG_Pos 26U /*!< DWT CTRL: NOEXTTRIG Position */\r
+#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */\r
+\r
+#define DWT_CTRL_NOCYCCNT_Pos 25U /*!< DWT CTRL: NOCYCCNT Position */\r
+#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */\r
+\r
+#define DWT_CTRL_NOPRFCNT_Pos 24U /*!< DWT CTRL: NOPRFCNT Position */\r
+#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */\r
+\r
+/* DWT Comparator Function Register Definitions */\r
+#define DWT_FUNCTION_ID_Pos 27U /*!< DWT FUNCTION: ID Position */\r
+#define DWT_FUNCTION_ID_Msk (0x1FUL << DWT_FUNCTION_ID_Pos) /*!< DWT FUNCTION: ID Mask */\r
+\r
+#define DWT_FUNCTION_MATCHED_Pos 24U /*!< DWT FUNCTION: MATCHED Position */\r
+#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */\r
+\r
+#define DWT_FUNCTION_DATAVSIZE_Pos 10U /*!< DWT FUNCTION: DATAVSIZE Position */\r
+#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */\r
+\r
+#define DWT_FUNCTION_ACTION_Pos 4U /*!< DWT FUNCTION: ACTION Position */\r
+#define DWT_FUNCTION_ACTION_Msk (0x3UL << DWT_FUNCTION_ACTION_Pos) /*!< DWT FUNCTION: ACTION Mask */\r
+\r
+#define DWT_FUNCTION_MATCH_Pos 0U /*!< DWT FUNCTION: MATCH Position */\r
+#define DWT_FUNCTION_MATCH_Msk (0xFUL /*<< DWT_FUNCTION_MATCH_Pos*/) /*!< DWT FUNCTION: MATCH Mask */\r
+\r
+/*@}*/ /* end of group CMSIS_DWT */\r
+\r
+\r
+/**\r
+ \ingroup CMSIS_core_register\r
+ \defgroup CMSIS_TPI Trace Port Interface (TPI)\r
+ \brief Type definitions for the Trace Port Interface (TPI)\r
+ @{\r
+ */\r
+\r
+/**\r
+ \brief Structure type to access the Trace Port Interface Register (TPI).\r
+ */\r
+typedef struct\r
+{\r
+ __IM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Sizes Register */\r
+ __IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Sizes Register */\r
+ uint32_t RESERVED0[2U];\r
+ __IOM uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */\r
+ uint32_t RESERVED1[55U];\r
+ __IOM uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */\r
+ uint32_t RESERVED2[131U];\r
+ __IM uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */\r
+ __IOM uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */\r
+ __IOM uint32_t PSCR; /*!< Offset: 0x308 (R/W) Periodic Synchronization Control Register */\r
+ uint32_t RESERVED3[809U];\r
+ __OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) Software Lock Access Register */\r
+ __IM uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) Software Lock Status Register */\r
+ uint32_t RESERVED4[4U];\r
+ __IM uint32_t TYPE; /*!< Offset: 0xFC8 (R/ ) Device Identifier Register */\r
+ __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) Device Type Register */\r
+} TPI_Type;\r
+\r
+/* TPI Asynchronous Clock Prescaler Register Definitions */\r
+#define TPI_ACPR_SWOSCALER_Pos 0U /*!< TPI ACPR: SWOSCALER Position */\r
+#define TPI_ACPR_SWOSCALER_Msk (0xFFFFUL /*<< TPI_ACPR_SWOSCALER_Pos*/) /*!< TPI ACPR: SWOSCALER Mask */\r
+\r
+/* TPI Selected Pin Protocol Register Definitions */\r
+#define TPI_SPPR_TXMODE_Pos 0U /*!< TPI SPPR: TXMODE Position */\r
+#define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) /*!< TPI SPPR: TXMODE Mask */\r
+\r
+/* TPI Formatter and Flush Status Register Definitions */\r
+#define TPI_FFSR_FtNonStop_Pos 3U /*!< TPI FFSR: FtNonStop Position */\r
+#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */\r
+\r
+#define TPI_FFSR_TCPresent_Pos 2U /*!< TPI FFSR: TCPresent Position */\r
+#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */\r
+\r
+#define TPI_FFSR_FtStopped_Pos 1U /*!< TPI FFSR: FtStopped Position */\r
+#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */\r
+\r
+#define TPI_FFSR_FlInProg_Pos 0U /*!< TPI FFSR: FlInProg Position */\r
+#define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) /*!< TPI FFSR: FlInProg Mask */\r
+\r
+/* TPI Formatter and Flush Control Register Definitions */\r
+#define TPI_FFCR_TrigIn_Pos 8U /*!< TPI FFCR: TrigIn Position */\r
+#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */\r
+\r
+#define TPI_FFCR_FOnMan_Pos 6U /*!< TPI FFCR: FOnMan Position */\r
+#define TPI_FFCR_FOnMan_Msk (0x1UL << TPI_FFCR_FOnMan_Pos) /*!< TPI FFCR: FOnMan Mask */\r
+\r
+#define TPI_FFCR_EnFCont_Pos 1U /*!< TPI FFCR: EnFCont Position */\r
+#define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */\r
+\r
+/* TPI Periodic Synchronization Control Register Definitions */\r
+#define TPI_PSCR_PSCount_Pos 0U /*!< TPI PSCR: PSCount Position */\r
+#define TPI_PSCR_PSCount_Msk (0x1FUL /*<< TPI_PSCR_PSCount_Pos*/) /*!< TPI PSCR: TPSCount Mask */\r
+\r
+/* TPI Software Lock Status Register Definitions */\r
+#define TPI_LSR_nTT_Pos 1U /*!< TPI LSR: Not thirty-two bit. Position */\r
+#define TPI_LSR_nTT_Msk (0x1UL << TPI_LSR_nTT_Pos) /*!< TPI LSR: Not thirty-two bit. Mask */\r
+\r
+#define TPI_LSR_SLK_Pos 1U /*!< TPI LSR: Software Lock status Position */\r
+#define TPI_LSR_SLK_Msk (0x1UL << TPI_LSR_SLK_Pos) /*!< TPI LSR: Software Lock status Mask */\r
+\r
+#define TPI_LSR_SLI_Pos 0U /*!< TPI LSR: Software Lock implemented Position */\r
+#define TPI_LSR_SLI_Msk (0x1UL /*<< TPI_LSR_SLI_Pos*/) /*!< TPI LSR: Software Lock implemented Mask */\r
+\r
+/* TPI DEVID Register Definitions */\r
+#define TPI_DEVID_NRZVALID_Pos 11U /*!< TPI DEVID: NRZVALID Position */\r
+#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */\r
+\r
+#define TPI_DEVID_MANCVALID_Pos 10U /*!< TPI DEVID: MANCVALID Position */\r
+#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */\r
+\r
+#define TPI_DEVID_PTINVALID_Pos 9U /*!< TPI DEVID: PTINVALID Position */\r
+#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */\r
+\r
+#define TPI_DEVID_FIFOSZ_Pos 6U /*!< TPI DEVID: FIFO depth Position */\r
+#define TPI_DEVID_FIFOSZ_Msk (0x7UL << TPI_DEVID_FIFOSZ_Pos) /*!< TPI DEVID: FIFO depth Mask */\r
+\r
+/* TPI DEVTYPE Register Definitions */\r
+#define TPI_DEVTYPE_SubType_Pos 4U /*!< TPI DEVTYPE: SubType Position */\r
+#define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */\r
+\r
+#define TPI_DEVTYPE_MajorType_Pos 0U /*!< TPI DEVTYPE: MajorType Position */\r
+#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */\r
+\r
+/*@}*/ /* end of group CMSIS_TPI */\r
+\r
+\r
+#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)\r
+/**\r
+ \ingroup CMSIS_core_register\r
+ \defgroup CMSIS_MPU Memory Protection Unit (MPU)\r
+ \brief Type definitions for the Memory Protection Unit (MPU)\r
+ @{\r
+ */\r
+\r
+/**\r
+ \brief Structure type to access the Memory Protection Unit (MPU).\r
+ */\r
+typedef struct\r
+{\r
+ __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */\r
+ __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */\r
+ __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region Number Register */\r
+ __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */\r
+ __IOM uint32_t RLAR; /*!< Offset: 0x010 (R/W) MPU Region Limit Address Register */\r
+ uint32_t RESERVED0[7U];\r
+ union {\r
+ __IOM uint32_t MAIR[2];\r
+ struct {\r
+ __IOM uint32_t MAIR0; /*!< Offset: 0x030 (R/W) MPU Memory Attribute Indirection Register 0 */\r
+ __IOM uint32_t MAIR1; /*!< Offset: 0x034 (R/W) MPU Memory Attribute Indirection Register 1 */\r
+ };\r
+ };\r
+} MPU_Type;\r
+\r
+#define MPU_TYPE_RALIASES 1U\r
+\r
+/* MPU Type Register Definitions */\r
+#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */\r
+#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */\r
+\r
+#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */\r
+#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */\r
+\r
+#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */\r
+#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */\r
+\r
+/* MPU Control Register Definitions */\r
+#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */\r
+#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */\r
+\r
+#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */\r
+#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */\r
+\r
+#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */\r
+#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */\r
+\r
+/* MPU Region Number Register Definitions */\r
+#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */\r
+#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */\r
+\r
+/* MPU Region Base Address Register Definitions */\r
+#define MPU_RBAR_BASE_Pos 5U /*!< MPU RBAR: BASE Position */\r
+#define MPU_RBAR_BASE_Msk (0x7FFFFFFUL << MPU_RBAR_BASE_Pos) /*!< MPU RBAR: BASE Mask */\r
+\r
+#define MPU_RBAR_SH_Pos 3U /*!< MPU RBAR: SH Position */\r
+#define MPU_RBAR_SH_Msk (0x3UL << MPU_RBAR_SH_Pos) /*!< MPU RBAR: SH Mask */\r
+\r
+#define MPU_RBAR_AP_Pos 1U /*!< MPU RBAR: AP Position */\r
+#define MPU_RBAR_AP_Msk (0x3UL << MPU_RBAR_AP_Pos) /*!< MPU RBAR: AP Mask */\r
+\r
+#define MPU_RBAR_XN_Pos 0U /*!< MPU RBAR: XN Position */\r
+#define MPU_RBAR_XN_Msk (01UL /*<< MPU_RBAR_XN_Pos*/) /*!< MPU RBAR: XN Mask */\r
+\r
+/* MPU Region Limit Address Register Definitions */\r
+#define MPU_RLAR_LIMIT_Pos 5U /*!< MPU RLAR: LIMIT Position */\r
+#define MPU_RLAR_LIMIT_Msk (0x7FFFFFFUL << MPU_RLAR_LIMIT_Pos) /*!< MPU RLAR: LIMIT Mask */\r
+\r
+#define MPU_RLAR_AttrIndx_Pos 1U /*!< MPU RLAR: AttrIndx Position */\r
+#define MPU_RLAR_AttrIndx_Msk (0x7UL << MPU_RLAR_AttrIndx_Pos) /*!< MPU RLAR: AttrIndx Mask */\r
+\r
+#define MPU_RLAR_EN_Pos 0U /*!< MPU RLAR: EN Position */\r
+#define MPU_RLAR_EN_Msk (1UL /*<< MPU_RLAR_EN_Pos*/) /*!< MPU RLAR: EN Mask */\r
+\r
+/* MPU Memory Attribute Indirection Register 0 Definitions */\r
+#define MPU_MAIR0_Attr3_Pos 24U /*!< MPU MAIR0: Attr3 Position */\r
+#define MPU_MAIR0_Attr3_Msk (0xFFUL << MPU_MAIR0_Attr3_Pos) /*!< MPU MAIR0: Attr3 Mask */\r
+\r
+#define MPU_MAIR0_Attr2_Pos 16U /*!< MPU MAIR0: Attr2 Position */\r
+#define MPU_MAIR0_Attr2_Msk (0xFFUL << MPU_MAIR0_Attr2_Pos) /*!< MPU MAIR0: Attr2 Mask */\r
+\r
+#define MPU_MAIR0_Attr1_Pos 8U /*!< MPU MAIR0: Attr1 Position */\r
+#define MPU_MAIR0_Attr1_Msk (0xFFUL << MPU_MAIR0_Attr1_Pos) /*!< MPU MAIR0: Attr1 Mask */\r
+\r
+#define MPU_MAIR0_Attr0_Pos 0U /*!< MPU MAIR0: Attr0 Position */\r
+#define MPU_MAIR0_Attr0_Msk (0xFFUL /*<< MPU_MAIR0_Attr0_Pos*/) /*!< MPU MAIR0: Attr0 Mask */\r
+\r
+/* MPU Memory Attribute Indirection Register 1 Definitions */\r
+#define MPU_MAIR1_Attr7_Pos 24U /*!< MPU MAIR1: Attr7 Position */\r
+#define MPU_MAIR1_Attr7_Msk (0xFFUL << MPU_MAIR1_Attr7_Pos) /*!< MPU MAIR1: Attr7 Mask */\r
+\r
+#define MPU_MAIR1_Attr6_Pos 16U /*!< MPU MAIR1: Attr6 Position */\r
+#define MPU_MAIR1_Attr6_Msk (0xFFUL << MPU_MAIR1_Attr6_Pos) /*!< MPU MAIR1: Attr6 Mask */\r
+\r
+#define MPU_MAIR1_Attr5_Pos 8U /*!< MPU MAIR1: Attr5 Position */\r
+#define MPU_MAIR1_Attr5_Msk (0xFFUL << MPU_MAIR1_Attr5_Pos) /*!< MPU MAIR1: Attr5 Mask */\r
+\r
+#define MPU_MAIR1_Attr4_Pos 0U /*!< MPU MAIR1: Attr4 Position */\r
+#define MPU_MAIR1_Attr4_Msk (0xFFUL /*<< MPU_MAIR1_Attr4_Pos*/) /*!< MPU MAIR1: Attr4 Mask */\r
+\r
+/*@} end of group CMSIS_MPU */\r
+#endif\r
+\r
+\r
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)\r
+/**\r
+ \ingroup CMSIS_core_register\r
+ \defgroup CMSIS_SAU Security Attribution Unit (SAU)\r
+ \brief Type definitions for the Security Attribution Unit (SAU)\r
+ @{\r
+ */\r
+\r
+/**\r
+ \brief Structure type to access the Security Attribution Unit (SAU).\r
+ */\r
+typedef struct\r
+{\r
+ __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SAU Control Register */\r
+ __IM uint32_t TYPE; /*!< Offset: 0x004 (R/ ) SAU Type Register */\r
+#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U)\r
+ __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) SAU Region Number Register */\r
+ __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) SAU Region Base Address Register */\r
+ __IOM uint32_t RLAR; /*!< Offset: 0x010 (R/W) SAU Region Limit Address Register */\r
+#endif\r
+} SAU_Type;\r
+\r
+/* SAU Control Register Definitions */\r
+#define SAU_CTRL_ALLNS_Pos 1U /*!< SAU CTRL: ALLNS Position */\r
+#define SAU_CTRL_ALLNS_Msk (1UL << SAU_CTRL_ALLNS_Pos) /*!< SAU CTRL: ALLNS Mask */\r
+\r
+#define SAU_CTRL_ENABLE_Pos 0U /*!< SAU CTRL: ENABLE Position */\r
+#define SAU_CTRL_ENABLE_Msk (1UL /*<< SAU_CTRL_ENABLE_Pos*/) /*!< SAU CTRL: ENABLE Mask */\r
+\r
+/* SAU Type Register Definitions */\r
+#define SAU_TYPE_SREGION_Pos 0U /*!< SAU TYPE: SREGION Position */\r
+#define SAU_TYPE_SREGION_Msk (0xFFUL /*<< SAU_TYPE_SREGION_Pos*/) /*!< SAU TYPE: SREGION Mask */\r
+\r
+#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U)\r
+/* SAU Region Number Register Definitions */\r
+#define SAU_RNR_REGION_Pos 0U /*!< SAU RNR: REGION Position */\r
+#define SAU_RNR_REGION_Msk (0xFFUL /*<< SAU_RNR_REGION_Pos*/) /*!< SAU RNR: REGION Mask */\r
+\r
+/* SAU Region Base Address Register Definitions */\r
+#define SAU_RBAR_BADDR_Pos 5U /*!< SAU RBAR: BADDR Position */\r
+#define SAU_RBAR_BADDR_Msk (0x7FFFFFFUL << SAU_RBAR_BADDR_Pos) /*!< SAU RBAR: BADDR Mask */\r
+\r
+/* SAU Region Limit Address Register Definitions */\r
+#define SAU_RLAR_LADDR_Pos 5U /*!< SAU RLAR: LADDR Position */\r
+#define SAU_RLAR_LADDR_Msk (0x7FFFFFFUL << SAU_RLAR_LADDR_Pos) /*!< SAU RLAR: LADDR Mask */\r
+\r
+#define SAU_RLAR_NSC_Pos 1U /*!< SAU RLAR: NSC Position */\r
+#define SAU_RLAR_NSC_Msk (1UL << SAU_RLAR_NSC_Pos) /*!< SAU RLAR: NSC Mask */\r
+\r
+#define SAU_RLAR_ENABLE_Pos 0U /*!< SAU RLAR: ENABLE Position */\r
+#define SAU_RLAR_ENABLE_Msk (1UL /*<< SAU_RLAR_ENABLE_Pos*/) /*!< SAU RLAR: ENABLE Mask */\r
+\r
+#endif /* defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) */\r
+\r
+/*@} end of group CMSIS_SAU */\r
+#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */\r
+\r
+\r
+/**\r
+ \ingroup CMSIS_core_register\r
+ \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug)\r
+ \brief Type definitions for the Core Debug Registers\r
+ @{\r
+ */\r
+\r
+/**\r
+ \brief Structure type to access the Core Debug Register (CoreDebug).\r
+ */\r
+typedef struct\r
+{\r
+ __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */\r
+ __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */\r
+ __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */\r
+ __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */\r
+ uint32_t RESERVED4[1U];\r
+ __IOM uint32_t DAUTHCTRL; /*!< Offset: 0x014 (R/W) Debug Authentication Control Register */\r
+ __IOM uint32_t DSCSR; /*!< Offset: 0x018 (R/W) Debug Security Control and Status Register */\r
+} CoreDebug_Type;\r
+\r
+/* Debug Halting Control and Status Register Definitions */\r
+#define CoreDebug_DHCSR_DBGKEY_Pos 16U /*!< CoreDebug DHCSR: DBGKEY Position */\r
+#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */\r
+\r
+#define CoreDebug_DHCSR_S_RESTART_ST_Pos 26U /*!< CoreDebug DHCSR: S_RESTART_ST Position */\r
+#define CoreDebug_DHCSR_S_RESTART_ST_Msk (1UL << CoreDebug_DHCSR_S_RESTART_ST_Pos) /*!< CoreDebug DHCSR: S_RESTART_ST Mask */\r
+\r
+#define CoreDebug_DHCSR_S_RESET_ST_Pos 25U /*!< CoreDebug DHCSR: S_RESET_ST Position */\r
+#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */\r
+\r
+#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U /*!< CoreDebug DHCSR: S_RETIRE_ST Position */\r
+#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */\r
+\r
+#define CoreDebug_DHCSR_S_LOCKUP_Pos 19U /*!< CoreDebug DHCSR: S_LOCKUP Position */\r
+#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */\r
+\r
+#define CoreDebug_DHCSR_S_SLEEP_Pos 18U /*!< CoreDebug DHCSR: S_SLEEP Position */\r
+#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */\r
+\r
+#define CoreDebug_DHCSR_S_HALT_Pos 17U /*!< CoreDebug DHCSR: S_HALT Position */\r
+#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */\r
+\r
+#define CoreDebug_DHCSR_S_REGRDY_Pos 16U /*!< CoreDebug DHCSR: S_REGRDY Position */\r
+#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */\r
+\r
+#define CoreDebug_DHCSR_C_MASKINTS_Pos 3U /*!< CoreDebug DHCSR: C_MASKINTS Position */\r
+#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */\r
+\r
+#define CoreDebug_DHCSR_C_STEP_Pos 2U /*!< CoreDebug DHCSR: C_STEP Position */\r
+#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */\r
+\r
+#define CoreDebug_DHCSR_C_HALT_Pos 1U /*!< CoreDebug DHCSR: C_HALT Position */\r
+#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */\r
+\r
+#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U /*!< CoreDebug DHCSR: C_DEBUGEN Position */\r
+#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */\r
+\r
+/* Debug Core Register Selector Register Definitions */\r
+#define CoreDebug_DCRSR_REGWnR_Pos 16U /*!< CoreDebug DCRSR: REGWnR Position */\r
+#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */\r
+\r
+#define CoreDebug_DCRSR_REGSEL_Pos 0U /*!< CoreDebug DCRSR: REGSEL Position */\r
+#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/) /*!< CoreDebug DCRSR: REGSEL Mask */\r
+\r
+/* Debug Exception and Monitor Control Register */\r
+#define CoreDebug_DEMCR_DWTENA_Pos 24U /*!< CoreDebug DEMCR: DWTENA Position */\r
+#define CoreDebug_DEMCR_DWTENA_Msk (1UL << CoreDebug_DEMCR_DWTENA_Pos) /*!< CoreDebug DEMCR: DWTENA Mask */\r
+\r
+#define CoreDebug_DEMCR_VC_HARDERR_Pos 10U /*!< CoreDebug DEMCR: VC_HARDERR Position */\r
+#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */\r
+\r
+#define CoreDebug_DEMCR_VC_CORERESET_Pos 0U /*!< CoreDebug DEMCR: VC_CORERESET Position */\r
+#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/) /*!< CoreDebug DEMCR: VC_CORERESET Mask */\r
+\r
+/* Debug Authentication Control Register Definitions */\r
+#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos 3U /*!< CoreDebug DAUTHCTRL: INTSPNIDEN, Position */\r
+#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos) /*!< CoreDebug DAUTHCTRL: INTSPNIDEN, Mask */\r
+\r
+#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos 2U /*!< CoreDebug DAUTHCTRL: SPNIDENSEL Position */\r
+#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Msk (1UL << CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos) /*!< CoreDebug DAUTHCTRL: SPNIDENSEL Mask */\r
+\r
+#define CoreDebug_DAUTHCTRL_INTSPIDEN_Pos 1U /*!< CoreDebug DAUTHCTRL: INTSPIDEN Position */\r
+#define CoreDebug_DAUTHCTRL_INTSPIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPIDEN_Pos) /*!< CoreDebug DAUTHCTRL: INTSPIDEN Mask */\r
+\r
+#define CoreDebug_DAUTHCTRL_SPIDENSEL_Pos 0U /*!< CoreDebug DAUTHCTRL: SPIDENSEL Position */\r
+#define CoreDebug_DAUTHCTRL_SPIDENSEL_Msk (1UL /*<< CoreDebug_DAUTHCTRL_SPIDENSEL_Pos*/) /*!< CoreDebug DAUTHCTRL: SPIDENSEL Mask */\r
+\r
+/* Debug Security Control and Status Register Definitions */\r
+#define CoreDebug_DSCSR_CDS_Pos 16U /*!< CoreDebug DSCSR: CDS Position */\r
+#define CoreDebug_DSCSR_CDS_Msk (1UL << CoreDebug_DSCSR_CDS_Pos) /*!< CoreDebug DSCSR: CDS Mask */\r
+\r
+#define CoreDebug_DSCSR_SBRSEL_Pos 1U /*!< CoreDebug DSCSR: SBRSEL Position */\r
+#define CoreDebug_DSCSR_SBRSEL_Msk (1UL << CoreDebug_DSCSR_SBRSEL_Pos) /*!< CoreDebug DSCSR: SBRSEL Mask */\r
+\r
+#define CoreDebug_DSCSR_SBRSELEN_Pos 0U /*!< CoreDebug DSCSR: SBRSELEN Position */\r
+#define CoreDebug_DSCSR_SBRSELEN_Msk (1UL /*<< CoreDebug_DSCSR_SBRSELEN_Pos*/) /*!< CoreDebug DSCSR: SBRSELEN Mask */\r
+\r
+/*@} end of group CMSIS_CoreDebug */\r
+\r
+\r
+/**\r
+ \ingroup CMSIS_core_register\r
+ \defgroup CMSIS_core_bitfield Core register bit field macros\r
+ \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk).\r
+ @{\r
+ */\r
+\r
+/**\r
+ \brief Mask and shift a bit field value for use in a register bit range.\r
+ \param[in] field Name of the register bit field.\r
+ \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type.\r
+ \return Masked and shifted value.\r
+*/\r
+#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk)\r
+\r
+/**\r
+ \brief Mask and shift a register value to extract a bit filed value.\r
+ \param[in] field Name of the register bit field.\r
+ \param[in] value Value of register. This parameter is interpreted as an uint32_t type.\r
+ \return Masked and shifted bit field value.\r
+*/\r
+#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos)\r
+\r
+/*@} end of group CMSIS_core_bitfield */\r
+\r
+\r
+/**\r
+ \ingroup CMSIS_core_register\r
+ \defgroup CMSIS_core_base Core Definitions\r
+ \brief Definitions for base addresses, unions, and structures.\r
+ @{\r
+ */\r
+\r
+/* Memory mapping of Core Hardware */\r
+ #define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */\r
+ #define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */\r
+ #define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */\r
+ #define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */\r
+ #define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */\r
+ #define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */\r
+ #define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */\r
+\r
+\r
+ #define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */\r
+ #define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */\r
+ #define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */\r
+ #define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */\r
+ #define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */\r
+ #define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE ) /*!< Core Debug configuration struct */\r
+\r
+ #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)\r
+ #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */\r
+ #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */\r
+ #endif\r
+\r
+ #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)\r
+ #define SAU_BASE (SCS_BASE + 0x0DD0UL) /*!< Security Attribution Unit */\r
+ #define SAU ((SAU_Type *) SAU_BASE ) /*!< Security Attribution Unit */\r
+ #endif\r
+\r
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)\r
+ #define SCS_BASE_NS (0xE002E000UL) /*!< System Control Space Base Address (non-secure address space) */\r
+ #define CoreDebug_BASE_NS (0xE002EDF0UL) /*!< Core Debug Base Address (non-secure address space) */\r
+ #define SysTick_BASE_NS (SCS_BASE_NS + 0x0010UL) /*!< SysTick Base Address (non-secure address space) */\r
+ #define NVIC_BASE_NS (SCS_BASE_NS + 0x0100UL) /*!< NVIC Base Address (non-secure address space) */\r
+ #define SCB_BASE_NS (SCS_BASE_NS + 0x0D00UL) /*!< System Control Block Base Address (non-secure address space) */\r
+\r
+ #define SCB_NS ((SCB_Type *) SCB_BASE_NS ) /*!< SCB configuration struct (non-secure address space) */\r
+ #define SysTick_NS ((SysTick_Type *) SysTick_BASE_NS ) /*!< SysTick configuration struct (non-secure address space) */\r
+ #define NVIC_NS ((NVIC_Type *) NVIC_BASE_NS ) /*!< NVIC configuration struct (non-secure address space) */\r
+ #define CoreDebug_NS ((CoreDebug_Type *) CoreDebug_BASE_NS) /*!< Core Debug configuration struct (non-secure address space) */\r
+\r
+ #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)\r
+ #define MPU_BASE_NS (SCS_BASE_NS + 0x0D90UL) /*!< Memory Protection Unit (non-secure address space) */\r
+ #define MPU_NS ((MPU_Type *) MPU_BASE_NS ) /*!< Memory Protection Unit (non-secure address space) */\r
+ #endif\r
+\r
+#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */\r
+/*@} */\r
+\r
+\r
+\r
+/*******************************************************************************\r
+ * Hardware Abstraction Layer\r
+ Core Function Interface contains:\r
+ - Core NVIC Functions\r
+ - Core SysTick Functions\r
+ - Core Register Access Functions\r
+ ******************************************************************************/\r
+/**\r
+ \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference\r
+*/\r
+\r
+\r
+\r
+/* ########################## NVIC functions #################################### */\r
+/**\r
+ \ingroup CMSIS_Core_FunctionInterface\r
+ \defgroup CMSIS_Core_NVICFunctions NVIC Functions\r
+ \brief Functions that manage interrupts and exceptions via the NVIC.\r
+ @{\r
+ */\r
+\r
+#ifdef CMSIS_NVIC_VIRTUAL\r
+ #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE\r
+ #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h"\r
+ #endif\r
+ #include CMSIS_NVIC_VIRTUAL_HEADER_FILE\r
+#else\r
+ #define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping\r
+ #define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping\r
+ #define NVIC_EnableIRQ __NVIC_EnableIRQ\r
+ #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ\r
+ #define NVIC_DisableIRQ __NVIC_DisableIRQ\r
+ #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ\r
+ #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ\r
+ #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ\r
+ #define NVIC_GetActive __NVIC_GetActive\r
+ #define NVIC_SetPriority __NVIC_SetPriority\r
+ #define NVIC_GetPriority __NVIC_GetPriority\r
+ #define NVIC_SystemReset __NVIC_SystemReset\r
+#endif /* CMSIS_NVIC_VIRTUAL */\r
+\r
+#ifdef CMSIS_VECTAB_VIRTUAL\r
+ #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE\r
+ #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h"\r
+ #endif\r
+ #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE\r
+#else\r
+ #define NVIC_SetVector __NVIC_SetVector\r
+ #define NVIC_GetVector __NVIC_GetVector\r
+#endif /* (CMSIS_VECTAB_VIRTUAL) */\r
+\r
+#define NVIC_USER_IRQ_OFFSET 16\r
+\r
+\r
+/* Special LR values for Secure/Non-Secure call handling and exception handling */\r
+\r
+/* Function Return Payload (from ARMv8-M Architecture Reference Manual) LR value on entry from Secure BLXNS */\r
+#define FNC_RETURN (0xFEFFFFFFUL) /* bit [0] ignored when processing a branch */\r
+\r
+/* The following EXC_RETURN mask values are used to evaluate the LR on exception entry */\r
+#define EXC_RETURN_PREFIX (0xFF000000UL) /* bits [31:24] set to indicate an EXC_RETURN value */\r
+#define EXC_RETURN_S (0x00000040UL) /* bit [6] stack used to push registers: 0=Non-secure 1=Secure */\r
+#define EXC_RETURN_DCRS (0x00000020UL) /* bit [5] stacking rules for called registers: 0=skipped 1=saved */\r
+#define EXC_RETURN_FTYPE (0x00000010UL) /* bit [4] allocate stack for floating-point context: 0=done 1=skipped */\r
+#define EXC_RETURN_MODE (0x00000008UL) /* bit [3] processor mode for return: 0=Handler mode 1=Thread mode */\r
+#define EXC_RETURN_SPSEL (0x00000002UL) /* bit [1] stack pointer used to restore context: 0=MSP 1=PSP */\r
+#define EXC_RETURN_ES (0x00000001UL) /* bit [0] security state exception was taken to: 0=Non-secure 1=Secure */\r
+\r
+/* Integrity Signature (from ARMv8-M Architecture Reference Manual) for exception context stacking */\r
+#if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) /* Value for processors with floating-point extension: */\r
+#define EXC_INTEGRITY_SIGNATURE (0xFEFA125AUL) /* bit [0] SFTC must match LR bit[4] EXC_RETURN_FTYPE */\r
+#else\r
+#define EXC_INTEGRITY_SIGNATURE (0xFEFA125BUL) /* Value for processors without floating-point extension */\r
+#endif\r
+\r
+\r
+/* Interrupt Priorities are WORD accessible only under Armv6-M */\r
+/* The following MACROS handle generation of the register offset and byte masks */\r
+#define _BIT_SHIFT(IRQn) ( ((((uint32_t)(int32_t)(IRQn)) ) & 0x03UL) * 8UL)\r
+#define _SHP_IDX(IRQn) ( (((((uint32_t)(int32_t)(IRQn)) & 0x0FUL)-8UL) >> 2UL) )\r
+#define _IP_IDX(IRQn) ( (((uint32_t)(int32_t)(IRQn)) >> 2UL) )\r
+\r
+#define __NVIC_SetPriorityGrouping(X) (void)(X)\r
+#define __NVIC_GetPriorityGrouping() (0U)\r
+\r
+/**\r
+ \brief Enable Interrupt\r
+ \details Enables a device specific interrupt in the NVIC interrupt controller.\r
+ \param [in] IRQn Device specific interrupt number.\r
+ \note IRQn must not be negative.\r
+ */\r
+__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn)\r
+{\r
+ if ((int32_t)(IRQn) >= 0)\r
+ {\r
+ NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));\r
+ }\r
+}\r
+\r
+\r
+/**\r
+ \brief Get Interrupt Enable status\r
+ \details Returns a device specific interrupt enable status from the NVIC interrupt controller.\r
+ \param [in] IRQn Device specific interrupt number.\r
+ \return 0 Interrupt is not enabled.\r
+ \return 1 Interrupt is enabled.\r
+ \note IRQn must not be negative.\r
+ */\r
+__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn)\r
+{\r
+ if ((int32_t)(IRQn) >= 0)\r
+ {\r
+ return((uint32_t)(((NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));\r
+ }\r
+ else\r
+ {\r
+ return(0U);\r
+ }\r
+}\r
+\r
+\r
+/**\r
+ \brief Disable Interrupt\r
+ \details Disables a device specific interrupt in the NVIC interrupt controller.\r
+ \param [in] IRQn Device specific interrupt number.\r
+ \note IRQn must not be negative.\r
+ */\r
+__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn)\r
+{\r
+ if ((int32_t)(IRQn) >= 0)\r
+ {\r
+ NVIC->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));\r
+ __DSB();\r
+ __ISB();\r
+ }\r
+}\r
+\r
+\r
+/**\r
+ \brief Get Pending Interrupt\r
+ \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt.\r
+ \param [in] IRQn Device specific interrupt number.\r
+ \return 0 Interrupt status is not pending.\r
+ \return 1 Interrupt status is pending.\r
+ \note IRQn must not be negative.\r
+ */\r
+__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn)\r
+{\r
+ if ((int32_t)(IRQn) >= 0)\r
+ {\r
+ return((uint32_t)(((NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));\r
+ }\r
+ else\r
+ {\r
+ return(0U);\r
+ }\r
+}\r
+\r
+\r
+/**\r
+ \brief Set Pending Interrupt\r
+ \details Sets the pending bit of a device specific interrupt in the NVIC pending register.\r
+ \param [in] IRQn Device specific interrupt number.\r
+ \note IRQn must not be negative.\r
+ */\r
+__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn)\r
+{\r
+ if ((int32_t)(IRQn) >= 0)\r
+ {\r
+ NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));\r
+ }\r
+}\r
+\r
+\r
+/**\r
+ \brief Clear Pending Interrupt\r
+ \details Clears the pending bit of a device specific interrupt in the NVIC pending register.\r
+ \param [in] IRQn Device specific interrupt number.\r
+ \note IRQn must not be negative.\r
+ */\r
+__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn)\r
+{\r
+ if ((int32_t)(IRQn) >= 0)\r
+ {\r
+ NVIC->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));\r
+ }\r
+}\r
+\r
+\r
+/**\r
+ \brief Get Active Interrupt\r
+ \details Reads the active register in the NVIC and returns the active bit for the device specific interrupt.\r
+ \param [in] IRQn Device specific interrupt number.\r
+ \return 0 Interrupt status is not active.\r
+ \return 1 Interrupt status is active.\r
+ \note IRQn must not be negative.\r
+ */\r
+__STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn)\r
+{\r
+ if ((int32_t)(IRQn) >= 0)\r
+ {\r
+ return((uint32_t)(((NVIC->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));\r
+ }\r
+ else\r
+ {\r
+ return(0U);\r
+ }\r
+}\r
+\r
+\r
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)\r
+/**\r
+ \brief Get Interrupt Target State\r
+ \details Reads the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt.\r
+ \param [in] IRQn Device specific interrupt number.\r
+ \return 0 if interrupt is assigned to Secure\r
+ \return 1 if interrupt is assigned to Non Secure\r
+ \note IRQn must not be negative.\r
+ */\r
+__STATIC_INLINE uint32_t NVIC_GetTargetState(IRQn_Type IRQn)\r
+{\r
+ if ((int32_t)(IRQn) >= 0)\r
+ {\r
+ return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));\r
+ }\r
+ else\r
+ {\r
+ return(0U);\r
+ }\r
+}\r
+\r
+\r
+/**\r
+ \brief Set Interrupt Target State\r
+ \details Sets the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt.\r
+ \param [in] IRQn Device specific interrupt number.\r
+ \return 0 if interrupt is assigned to Secure\r
+ 1 if interrupt is assigned to Non Secure\r
+ \note IRQn must not be negative.\r
+ */\r
+__STATIC_INLINE uint32_t NVIC_SetTargetState(IRQn_Type IRQn)\r
+{\r
+ if ((int32_t)(IRQn) >= 0)\r
+ {\r
+ NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] |= ((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)));\r
+ return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));\r
+ }\r
+ else\r
+ {\r
+ return(0U);\r
+ }\r
+}\r
+\r
+\r
+/**\r
+ \brief Clear Interrupt Target State\r
+ \details Clears the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt.\r
+ \param [in] IRQn Device specific interrupt number.\r
+ \return 0 if interrupt is assigned to Secure\r
+ 1 if interrupt is assigned to Non Secure\r
+ \note IRQn must not be negative.\r
+ */\r
+__STATIC_INLINE uint32_t NVIC_ClearTargetState(IRQn_Type IRQn)\r
+{\r
+ if ((int32_t)(IRQn) >= 0)\r
+ {\r
+ NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] &= ~((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)));\r
+ return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));\r
+ }\r
+ else\r
+ {\r
+ return(0U);\r
+ }\r
+}\r
+#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */\r
+\r
+\r
+/**\r
+ \brief Set Interrupt Priority\r
+ \details Sets the priority of a device specific interrupt or a processor exception.\r
+ The interrupt number can be positive to specify a device specific interrupt,\r
+ or negative to specify a processor exception.\r
+ \param [in] IRQn Interrupt number.\r
+ \param [in] priority Priority to set.\r
+ \note The priority cannot be set for every processor exception.\r
+ */\r
+__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)\r
+{\r
+ if ((int32_t)(IRQn) >= 0)\r
+ {\r
+ NVIC->IPR[_IP_IDX(IRQn)] = ((uint32_t)(NVIC->IPR[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |\r
+ (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));\r
+ }\r
+ else\r
+ {\r
+ SCB->SHPR[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHPR[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |\r
+ (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));\r
+ }\r
+}\r
+\r
+\r
+/**\r
+ \brief Get Interrupt Priority\r
+ \details Reads the priority of a device specific interrupt or a processor exception.\r
+ The interrupt number can be positive to specify a device specific interrupt,\r
+ or negative to specify a processor exception.\r
+ \param [in] IRQn Interrupt number.\r
+ \return Interrupt Priority.\r
+ Value is aligned automatically to the implemented priority bits of the microcontroller.\r
+ */\r
+__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn)\r
+{\r
+\r
+ if ((int32_t)(IRQn) >= 0)\r
+ {\r
+ return((uint32_t)(((NVIC->IPR[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));\r
+ }\r
+ else\r
+ {\r
+ return((uint32_t)(((SCB->SHPR[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));\r
+ }\r
+}\r
+\r
+\r
+/**\r
+ \brief Encode Priority\r
+ \details Encodes the priority for an interrupt with the given priority group,\r
+ preemptive priority value, and subpriority value.\r
+ In case of a conflict between priority grouping and available\r
+ priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.\r
+ \param [in] PriorityGroup Used priority group.\r
+ \param [in] PreemptPriority Preemptive priority value (starting from 0).\r
+ \param [in] SubPriority Subpriority value (starting from 0).\r
+ \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority().\r
+ */\r
+__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)\r
+{\r
+ uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */\r
+ uint32_t PreemptPriorityBits;\r
+ uint32_t SubPriorityBits;\r
+\r
+ PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);\r
+ SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));\r
+\r
+ return (\r
+ ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) |\r
+ ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL)))\r
+ );\r
+}\r
+\r
+\r
+/**\r
+ \brief Decode Priority\r
+ \details Decodes an interrupt priority value with a given priority group to\r
+ preemptive priority value and subpriority value.\r
+ In case of a conflict between priority grouping and available\r
+ priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set.\r
+ \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority().\r
+ \param [in] PriorityGroup Used priority group.\r
+ \param [out] pPreemptPriority Preemptive priority value (starting from 0).\r
+ \param [out] pSubPriority Subpriority value (starting from 0).\r
+ */\r
+__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority)\r
+{\r
+ uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */\r
+ uint32_t PreemptPriorityBits;\r
+ uint32_t SubPriorityBits;\r
+\r
+ PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);\r
+ SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));\r
+\r
+ *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL);\r
+ *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL);\r
+}\r
+\r
+\r
+/**\r
+ \brief Set Interrupt Vector\r
+ \details Sets an interrupt vector in SRAM based interrupt vector table.\r
+ The interrupt number can be positive to specify a device specific interrupt,\r
+ or negative to specify a processor exception.\r
+ VTOR must been relocated to SRAM before.\r
+ If VTOR is not present address 0 must be mapped to SRAM.\r
+ \param [in] IRQn Interrupt number\r
+ \param [in] vector Address of interrupt handler function\r
+ */\r
+__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector)\r
+{\r
+#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U)\r
+ uint32_t *vectors = (uint32_t *)SCB->VTOR;\r
+#else\r
+ uint32_t *vectors = (uint32_t *)0x0U;\r
+#endif\r
+ vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector;\r
+}\r
+\r
+\r
+/**\r
+ \brief Get Interrupt Vector\r
+ \details Reads an interrupt vector from interrupt vector table.\r
+ The interrupt number can be positive to specify a device specific interrupt,\r
+ or negative to specify a processor exception.\r
+ \param [in] IRQn Interrupt number.\r
+ \return Address of interrupt handler function\r
+ */\r
+__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn)\r
+{\r
+#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U)\r
+ uint32_t *vectors = (uint32_t *)SCB->VTOR;\r
+#else\r
+ uint32_t *vectors = (uint32_t *)0x0U;\r
+#endif\r
+ return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET];\r
+}\r
+\r
+\r
+/**\r
+ \brief System Reset\r
+ \details Initiates a system reset request to reset the MCU.\r
+ */\r
+__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void)\r
+{\r
+ __DSB(); /* Ensure all outstanding memory accesses included\r
+ buffered write are completed before reset */\r
+ SCB->AIRCR = ((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |\r
+ SCB_AIRCR_SYSRESETREQ_Msk);\r
+ __DSB(); /* Ensure completion of memory access */\r
+\r
+ for(;;) /* wait until reset */\r
+ {\r
+ __NOP();\r
+ }\r
+}\r
+\r
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)\r
+/**\r
+ \brief Enable Interrupt (non-secure)\r
+ \details Enables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state.\r
+ \param [in] IRQn Device specific interrupt number.\r
+ \note IRQn must not be negative.\r
+ */\r
+__STATIC_INLINE void TZ_NVIC_EnableIRQ_NS(IRQn_Type IRQn)\r
+{\r
+ if ((int32_t)(IRQn) >= 0)\r
+ {\r
+ NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));\r
+ }\r
+}\r
+\r
+\r
+/**\r
+ \brief Get Interrupt Enable status (non-secure)\r
+ \details Returns a device specific interrupt enable status from the non-secure NVIC interrupt controller when in secure state.\r
+ \param [in] IRQn Device specific interrupt number.\r
+ \return 0 Interrupt is not enabled.\r
+ \return 1 Interrupt is enabled.\r
+ \note IRQn must not be negative.\r
+ */\r
+__STATIC_INLINE uint32_t TZ_NVIC_GetEnableIRQ_NS(IRQn_Type IRQn)\r
+{\r
+ if ((int32_t)(IRQn) >= 0)\r
+ {\r
+ return((uint32_t)(((NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));\r
+ }\r
+ else\r
+ {\r
+ return(0U);\r
+ }\r
+}\r
+\r
+\r
+/**\r
+ \brief Disable Interrupt (non-secure)\r
+ \details Disables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state.\r
+ \param [in] IRQn Device specific interrupt number.\r
+ \note IRQn must not be negative.\r
+ */\r
+__STATIC_INLINE void TZ_NVIC_DisableIRQ_NS(IRQn_Type IRQn)\r
+{\r
+ if ((int32_t)(IRQn) >= 0)\r
+ {\r
+ NVIC_NS->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));\r
+ }\r
+}\r
+\r
+\r
+/**\r
+ \brief Get Pending Interrupt (non-secure)\r
+ \details Reads the NVIC pending register in the non-secure NVIC when in secure state and returns the pending bit for the specified device specific interrupt.\r
+ \param [in] IRQn Device specific interrupt number.\r
+ \return 0 Interrupt status is not pending.\r
+ \return 1 Interrupt status is pending.\r
+ \note IRQn must not be negative.\r
+ */\r
+__STATIC_INLINE uint32_t TZ_NVIC_GetPendingIRQ_NS(IRQn_Type IRQn)\r
+{\r
+ if ((int32_t)(IRQn) >= 0)\r
+ {\r
+ return((uint32_t)(((NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));\r
+ }\r
+ else\r
+ {\r
+ return(0U);\r
+ }\r
+}\r
+\r
+\r
+/**\r
+ \brief Set Pending Interrupt (non-secure)\r
+ \details Sets the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state.\r
+ \param [in] IRQn Device specific interrupt number.\r
+ \note IRQn must not be negative.\r
+ */\r
+__STATIC_INLINE void TZ_NVIC_SetPendingIRQ_NS(IRQn_Type IRQn)\r
+{\r
+ if ((int32_t)(IRQn) >= 0)\r
+ {\r
+ NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));\r
+ }\r
+}\r
+\r
+\r
+/**\r
+ \brief Clear Pending Interrupt (non-secure)\r
+ \details Clears the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state.\r
+ \param [in] IRQn Device specific interrupt number.\r
+ \note IRQn must not be negative.\r
+ */\r
+__STATIC_INLINE void TZ_NVIC_ClearPendingIRQ_NS(IRQn_Type IRQn)\r
+{\r
+ if ((int32_t)(IRQn) >= 0)\r
+ {\r
+ NVIC_NS->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));\r
+ }\r
+}\r
+\r
+\r
+/**\r
+ \brief Get Active Interrupt (non-secure)\r
+ \details Reads the active register in non-secure NVIC when in secure state and returns the active bit for the device specific interrupt.\r
+ \param [in] IRQn Device specific interrupt number.\r
+ \return 0 Interrupt status is not active.\r
+ \return 1 Interrupt status is active.\r
+ \note IRQn must not be negative.\r
+ */\r
+__STATIC_INLINE uint32_t TZ_NVIC_GetActive_NS(IRQn_Type IRQn)\r
+{\r
+ if ((int32_t)(IRQn) >= 0)\r
+ {\r
+ return((uint32_t)(((NVIC_NS->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));\r
+ }\r
+ else\r
+ {\r
+ return(0U);\r
+ }\r
+}\r
+\r
+\r
+/**\r
+ \brief Set Interrupt Priority (non-secure)\r
+ \details Sets the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state.\r
+ The interrupt number can be positive to specify a device specific interrupt,\r
+ or negative to specify a processor exception.\r
+ \param [in] IRQn Interrupt number.\r
+ \param [in] priority Priority to set.\r
+ \note The priority cannot be set for every non-secure processor exception.\r
+ */\r
+__STATIC_INLINE void TZ_NVIC_SetPriority_NS(IRQn_Type IRQn, uint32_t priority)\r
+{\r
+ if ((int32_t)(IRQn) >= 0)\r
+ {\r
+ NVIC_NS->IPR[_IP_IDX(IRQn)] = ((uint32_t)(NVIC_NS->IPR[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |\r
+ (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));\r
+ }\r
+ else\r
+ {\r
+ SCB_NS->SHPR[_SHP_IDX(IRQn)] = ((uint32_t)(SCB_NS->SHPR[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |\r
+ (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));\r
+ }\r
+}\r
+\r
+\r
+/**\r
+ \brief Get Interrupt Priority (non-secure)\r
+ \details Reads the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state.\r
+ The interrupt number can be positive to specify a device specific interrupt,\r
+ or negative to specify a processor exception.\r
+ \param [in] IRQn Interrupt number.\r
+ \return Interrupt Priority. Value is aligned automatically to the implemented priority bits of the microcontroller.\r
+ */\r
+__STATIC_INLINE uint32_t TZ_NVIC_GetPriority_NS(IRQn_Type IRQn)\r
+{\r
+\r
+ if ((int32_t)(IRQn) >= 0)\r
+ {\r
+ return((uint32_t)(((NVIC_NS->IPR[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));\r
+ }\r
+ else\r
+ {\r
+ return((uint32_t)(((SCB_NS->SHPR[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));\r
+ }\r
+}\r
+#endif /* defined (__ARM_FEATURE_CMSE) &&(__ARM_FEATURE_CMSE == 3U) */\r
+\r
+/*@} end of CMSIS_Core_NVICFunctions */\r
+\r
+/* ########################## MPU functions #################################### */\r
+\r
+#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)\r
+\r
+#include "mpu_armv8.h"\r
+\r
+#endif\r
+\r
+/* ########################## FPU functions #################################### */\r
+/**\r
+ \ingroup CMSIS_Core_FunctionInterface\r
+ \defgroup CMSIS_Core_FpuFunctions FPU Functions\r
+ \brief Function that provides FPU type.\r
+ @{\r
+ */\r
+\r
+/**\r
+ \brief get FPU type\r
+ \details returns the FPU type\r
+ \returns\r
+ - \b 0: No FPU\r
+ - \b 1: Single precision FPU\r
+ - \b 2: Double + Single precision FPU\r
+ */\r
+__STATIC_INLINE uint32_t SCB_GetFPUType(void)\r
+{\r
+ return 0U; /* No FPU */\r
+}\r
+\r
+\r
+/*@} end of CMSIS_Core_FpuFunctions */\r
+\r
+\r
+\r
+/* ########################## SAU functions #################################### */\r
+/**\r
+ \ingroup CMSIS_Core_FunctionInterface\r
+ \defgroup CMSIS_Core_SAUFunctions SAU Functions\r
+ \brief Functions that configure the SAU.\r
+ @{\r
+ */\r
+\r
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)\r
+\r
+/**\r
+ \brief Enable SAU\r
+ \details Enables the Security Attribution Unit (SAU).\r
+ */\r
+__STATIC_INLINE void TZ_SAU_Enable(void)\r
+{\r
+ SAU->CTRL |= (SAU_CTRL_ENABLE_Msk);\r
+}\r
+\r
+\r
+\r
+/**\r
+ \brief Disable SAU\r
+ \details Disables the Security Attribution Unit (SAU).\r
+ */\r
+__STATIC_INLINE void TZ_SAU_Disable(void)\r
+{\r
+ SAU->CTRL &= ~(SAU_CTRL_ENABLE_Msk);\r
+}\r
+\r
+#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */\r
+\r
+/*@} end of CMSIS_Core_SAUFunctions */\r
+\r
+\r
+\r
+\r
+/* ################################## SysTick function ############################################ */\r
+/**\r
+ \ingroup CMSIS_Core_FunctionInterface\r
+ \defgroup CMSIS_Core_SysTickFunctions SysTick Functions\r
+ \brief Functions that configure the System.\r
+ @{\r
+ */\r
+\r
+#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U)\r
+\r
+/**\r
+ \brief System Tick Configuration\r
+ \details Initializes the System Timer and its interrupt, and starts the System Tick Timer.\r
+ Counter is in free running mode to generate periodic interrupts.\r
+ \param [in] ticks Number of ticks between two interrupts.\r
+ \return 0 Function succeeded.\r
+ \return 1 Function failed.\r
+ \note When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the\r
+ function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>\r
+ must contain a vendor-specific implementation of this function.\r
+ */\r
+__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)\r
+{\r
+ if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk)\r
+ {\r
+ return (1UL); /* Reload value impossible */\r
+ }\r
+\r
+ SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */\r
+ NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */\r
+ SysTick->VAL = 0UL; /* Load the SysTick Counter Value */\r
+ SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk |\r
+ SysTick_CTRL_TICKINT_Msk |\r
+ SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */\r
+ return (0UL); /* Function successful */\r
+}\r
+\r
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)\r
+/**\r
+ \brief System Tick Configuration (non-secure)\r
+ \details Initializes the non-secure System Timer and its interrupt when in secure state, and starts the System Tick Timer.\r
+ Counter is in free running mode to generate periodic interrupts.\r
+ \param [in] ticks Number of ticks between two interrupts.\r
+ \return 0 Function succeeded.\r
+ \return 1 Function failed.\r
+ \note When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the\r
+ function <b>TZ_SysTick_Config_NS</b> is not included. In this case, the file <b><i>device</i>.h</b>\r
+ must contain a vendor-specific implementation of this function.\r
+\r
+ */\r
+__STATIC_INLINE uint32_t TZ_SysTick_Config_NS(uint32_t ticks)\r
+{\r
+ if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk)\r
+ {\r
+ return (1UL); /* Reload value impossible */\r
+ }\r
+\r
+ SysTick_NS->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */\r
+ TZ_NVIC_SetPriority_NS (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */\r
+ SysTick_NS->VAL = 0UL; /* Load the SysTick Counter Value */\r
+ SysTick_NS->CTRL = SysTick_CTRL_CLKSOURCE_Msk |\r
+ SysTick_CTRL_TICKINT_Msk |\r
+ SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */\r
+ return (0UL); /* Function successful */\r
+}\r
+#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */\r
+\r
+#endif\r
+\r
+/*@} end of CMSIS_Core_SysTickFunctions */\r
+\r
+\r
+\r
+\r
+#ifdef __cplusplus\r
+}\r
+#endif\r
+\r
+#endif /* __CORE_ARMV8MBL_H_DEPENDANT */\r
+\r
+#endif /* __CMSIS_GENERIC */\r
--- /dev/null
+/**************************************************************************//**\r
+ * @file core_armv8mml.h\r
+ * @brief CMSIS Armv8-M Mainline Core Peripheral Access Layer Header File\r
+ * @version V5.0.7\r
+ * @date 06. July 2018\r
+ ******************************************************************************/\r
+/*\r
+ * Copyright (c) 2009-2018 Arm Limited. All rights reserved.\r
+ *\r
+ * SPDX-License-Identifier: Apache-2.0\r
+ *\r
+ * Licensed under the Apache License, Version 2.0 (the License); you may\r
+ * not use this file except in compliance with the License.\r
+ * You may obtain a copy of the License at\r
+ *\r
+ * www.apache.org/licenses/LICENSE-2.0\r
+ *\r
+ * Unless required by applicable law or agreed to in writing, software\r
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT\r
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\r
+ * See the License for the specific language governing permissions and\r
+ * limitations under the License.\r
+ */\r
+\r
+#if defined ( __ICCARM__ )\r
+ #pragma system_include /* treat file as system include file for MISRA check */\r
+#elif defined (__clang__)\r
+ #pragma clang system_header /* treat file as system include file */\r
+#endif\r
+\r
+#ifndef __CORE_ARMV8MML_H_GENERIC\r
+#define __CORE_ARMV8MML_H_GENERIC\r
+\r
+#include <stdint.h>\r
+\r
+#ifdef __cplusplus\r
+ extern "C" {\r
+#endif\r
+\r
+/**\r
+ \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions\r
+ CMSIS violates the following MISRA-C:2004 rules:\r
+\r
+ \li Required Rule 8.5, object/function definition in header file.<br>\r
+ Function definitions in header files are used to allow 'inlining'.\r
+\r
+ \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>\r
+ Unions are used for effective representation of core registers.\r
+\r
+ \li Advisory Rule 19.7, Function-like macro defined.<br>\r
+ Function-like macros are used to allow more efficient code.\r
+ */\r
+\r
+\r
+/*******************************************************************************\r
+ * CMSIS definitions\r
+ ******************************************************************************/\r
+/**\r
+ \ingroup Cortex_ARMv8MML\r
+ @{\r
+ */\r
+\r
+#include "cmsis_version.h"\r
+\r
+/* CMSIS Armv8MML definitions */\r
+#define __ARMv8MML_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */\r
+#define __ARMv8MML_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */\r
+#define __ARMv8MML_CMSIS_VERSION ((__ARMv8MML_CMSIS_VERSION_MAIN << 16U) | \\r
+ __ARMv8MML_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */\r
+\r
+#define __CORTEX_M (81U) /*!< Cortex-M Core */\r
+\r
+/** __FPU_USED indicates whether an FPU is used or not.\r
+ For this, __FPU_PRESENT has to be checked prior to making use of FPU specific registers and functions.\r
+*/\r
+#if defined ( __CC_ARM )\r
+ #if defined __TARGET_FPU_VFP\r
+ #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)\r
+ #define __FPU_USED 1U\r
+ #else\r
+ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"\r
+ #define __FPU_USED 0U\r
+ #endif\r
+ #else\r
+ #define __FPU_USED 0U\r
+ #endif\r
+\r
+ #if defined(__ARM_FEATURE_DSP)\r
+ #if defined(__DSP_PRESENT) && (__DSP_PRESENT == 1U)\r
+ #define __DSP_USED 1U\r
+ #else\r
+ #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)"\r
+ #define __DSP_USED 0U\r
+ #endif\r
+ #else\r
+ #define __DSP_USED 0U\r
+ #endif\r
+\r
+#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)\r
+ #if defined __ARM_PCS_VFP\r
+ #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)\r
+ #define __FPU_USED 1U\r
+ #else\r
+ #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"\r
+ #define __FPU_USED 0U\r
+ #endif\r
+ #else\r
+ #define __FPU_USED 0U\r
+ #endif\r
+\r
+ #if defined(__ARM_FEATURE_DSP)\r
+ #if defined(__DSP_PRESENT) && (__DSP_PRESENT == 1U)\r
+ #define __DSP_USED 1U\r
+ #else\r
+ #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)"\r
+ #define __DSP_USED 0U\r
+ #endif\r
+ #else\r
+ #define __DSP_USED 0U\r
+ #endif\r
+\r
+#elif defined ( __GNUC__ )\r
+ #if defined (__VFP_FP__) && !defined(__SOFTFP__)\r
+ #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)\r
+ #define __FPU_USED 1U\r
+ #else\r
+ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"\r
+ #define __FPU_USED 0U\r
+ #endif\r
+ #else\r
+ #define __FPU_USED 0U\r
+ #endif\r
+\r
+ #if defined(__ARM_FEATURE_DSP)\r
+ #if defined(__DSP_PRESENT) && (__DSP_PRESENT == 1U)\r
+ #define __DSP_USED 1U\r
+ #else\r
+ #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)"\r
+ #define __DSP_USED 0U\r
+ #endif\r
+ #else\r
+ #define __DSP_USED 0U\r
+ #endif\r
+\r
+#elif defined ( __ICCARM__ )\r
+ #if defined __ARMVFP__\r
+ #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)\r
+ #define __FPU_USED 1U\r
+ #else\r
+ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"\r
+ #define __FPU_USED 0U\r
+ #endif\r
+ #else\r
+ #define __FPU_USED 0U\r
+ #endif\r
+\r
+ #if defined(__ARM_FEATURE_DSP)\r
+ #if defined(__DSP_PRESENT) && (__DSP_PRESENT == 1U)\r
+ #define __DSP_USED 1U\r
+ #else\r
+ #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)"\r
+ #define __DSP_USED 0U\r
+ #endif\r
+ #else\r
+ #define __DSP_USED 0U\r
+ #endif\r
+\r
+#elif defined ( __TI_ARM__ )\r
+ #if defined __TI_VFP_SUPPORT__\r
+ #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)\r
+ #define __FPU_USED 1U\r
+ #else\r
+ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"\r
+ #define __FPU_USED 0U\r
+ #endif\r
+ #else\r
+ #define __FPU_USED 0U\r
+ #endif\r
+\r
+#elif defined ( __TASKING__ )\r
+ #if defined __FPU_VFP__\r
+ #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)\r
+ #define __FPU_USED 1U\r
+ #else\r
+ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"\r
+ #define __FPU_USED 0U\r
+ #endif\r
+ #else\r
+ #define __FPU_USED 0U\r
+ #endif\r
+\r
+#elif defined ( __CSMC__ )\r
+ #if ( __CSMC__ & 0x400U)\r
+ #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)\r
+ #define __FPU_USED 1U\r
+ #else\r
+ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"\r
+ #define __FPU_USED 0U\r
+ #endif\r
+ #else\r
+ #define __FPU_USED 0U\r
+ #endif\r
+\r
+#endif\r
+\r
+#include "cmsis_compiler.h" /* CMSIS compiler specific defines */\r
+\r
+\r
+#ifdef __cplusplus\r
+}\r
+#endif\r
+\r
+#endif /* __CORE_ARMV8MML_H_GENERIC */\r
+\r
+#ifndef __CMSIS_GENERIC\r
+\r
+#ifndef __CORE_ARMV8MML_H_DEPENDANT\r
+#define __CORE_ARMV8MML_H_DEPENDANT\r
+\r
+#ifdef __cplusplus\r
+ extern "C" {\r
+#endif\r
+\r
+/* check device defines and use defaults */\r
+#if defined __CHECK_DEVICE_DEFINES\r
+ #ifndef __ARMv8MML_REV\r
+ #define __ARMv8MML_REV 0x0000U\r
+ #warning "__ARMv8MML_REV not defined in device header file; using default!"\r
+ #endif\r
+\r
+ #ifndef __FPU_PRESENT\r
+ #define __FPU_PRESENT 0U\r
+ #warning "__FPU_PRESENT not defined in device header file; using default!"\r
+ #endif\r
+\r
+ #ifndef __MPU_PRESENT\r
+ #define __MPU_PRESENT 0U\r
+ #warning "__MPU_PRESENT not defined in device header file; using default!"\r
+ #endif\r
+\r
+ #ifndef __SAUREGION_PRESENT\r
+ #define __SAUREGION_PRESENT 0U\r
+ #warning "__SAUREGION_PRESENT not defined in device header file; using default!"\r
+ #endif\r
+\r
+ #ifndef __DSP_PRESENT\r
+ #define __DSP_PRESENT 0U\r
+ #warning "__DSP_PRESENT not defined in device header file; using default!"\r
+ #endif\r
+\r
+ #ifndef __NVIC_PRIO_BITS\r
+ #define __NVIC_PRIO_BITS 3U\r
+ #warning "__NVIC_PRIO_BITS not defined in device header file; using default!"\r
+ #endif\r
+\r
+ #ifndef __Vendor_SysTickConfig\r
+ #define __Vendor_SysTickConfig 0U\r
+ #warning "__Vendor_SysTickConfig not defined in device header file; using default!"\r
+ #endif\r
+#endif\r
+\r
+/* IO definitions (access restrictions to peripheral registers) */\r
+/**\r
+ \defgroup CMSIS_glob_defs CMSIS Global Defines\r
+\r
+ <strong>IO Type Qualifiers</strong> are used\r
+ \li to specify the access to peripheral variables.\r
+ \li for automatic generation of peripheral register debug information.\r
+*/\r
+#ifdef __cplusplus\r
+ #define __I volatile /*!< Defines 'read only' permissions */\r
+#else\r
+ #define __I volatile const /*!< Defines 'read only' permissions */\r
+#endif\r
+#define __O volatile /*!< Defines 'write only' permissions */\r
+#define __IO volatile /*!< Defines 'read / write' permissions */\r
+\r
+/* following defines should be used for structure members */\r
+#define __IM volatile const /*! Defines 'read only' structure member permissions */\r
+#define __OM volatile /*! Defines 'write only' structure member permissions */\r
+#define __IOM volatile /*! Defines 'read / write' structure member permissions */\r
+\r
+/*@} end of group ARMv8MML */\r
+\r
+\r
+\r
+/*******************************************************************************\r
+ * Register Abstraction\r
+ Core Register contain:\r
+ - Core Register\r
+ - Core NVIC Register\r
+ - Core SCB Register\r
+ - Core SysTick Register\r
+ - Core Debug Register\r
+ - Core MPU Register\r
+ - Core SAU Register\r
+ - Core FPU Register\r
+ ******************************************************************************/\r
+/**\r
+ \defgroup CMSIS_core_register Defines and Type Definitions\r
+ \brief Type definitions and defines for Cortex-M processor based devices.\r
+*/\r
+\r
+/**\r
+ \ingroup CMSIS_core_register\r
+ \defgroup CMSIS_CORE Status and Control Registers\r
+ \brief Core Register type definitions.\r
+ @{\r
+ */\r
+\r
+/**\r
+ \brief Union type to access the Application Program Status Register (APSR).\r
+ */\r
+typedef union\r
+{\r
+ struct\r
+ {\r
+ uint32_t _reserved0:16; /*!< bit: 0..15 Reserved */\r
+ uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */\r
+ uint32_t _reserved1:7; /*!< bit: 20..26 Reserved */\r
+ uint32_t Q:1; /*!< bit: 27 Saturation condition flag */\r
+ uint32_t V:1; /*!< bit: 28 Overflow condition code flag */\r
+ uint32_t C:1; /*!< bit: 29 Carry condition code flag */\r
+ uint32_t Z:1; /*!< bit: 30 Zero condition code flag */\r
+ uint32_t N:1; /*!< bit: 31 Negative condition code flag */\r
+ } b; /*!< Structure used for bit access */\r
+ uint32_t w; /*!< Type used for word access */\r
+} APSR_Type;\r
+\r
+/* APSR Register Definitions */\r
+#define APSR_N_Pos 31U /*!< APSR: N Position */\r
+#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */\r
+\r
+#define APSR_Z_Pos 30U /*!< APSR: Z Position */\r
+#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */\r
+\r
+#define APSR_C_Pos 29U /*!< APSR: C Position */\r
+#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */\r
+\r
+#define APSR_V_Pos 28U /*!< APSR: V Position */\r
+#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */\r
+\r
+#define APSR_Q_Pos 27U /*!< APSR: Q Position */\r
+#define APSR_Q_Msk (1UL << APSR_Q_Pos) /*!< APSR: Q Mask */\r
+\r
+#define APSR_GE_Pos 16U /*!< APSR: GE Position */\r
+#define APSR_GE_Msk (0xFUL << APSR_GE_Pos) /*!< APSR: GE Mask */\r
+\r
+\r
+/**\r
+ \brief Union type to access the Interrupt Program Status Register (IPSR).\r
+ */\r
+typedef union\r
+{\r
+ struct\r
+ {\r
+ uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */\r
+ uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */\r
+ } b; /*!< Structure used for bit access */\r
+ uint32_t w; /*!< Type used for word access */\r
+} IPSR_Type;\r
+\r
+/* IPSR Register Definitions */\r
+#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */\r
+#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */\r
+\r
+\r
+/**\r
+ \brief Union type to access the Special-Purpose Program Status Registers (xPSR).\r
+ */\r
+typedef union\r
+{\r
+ struct\r
+ {\r
+ uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */\r
+ uint32_t _reserved0:7; /*!< bit: 9..15 Reserved */\r
+ uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */\r
+ uint32_t _reserved1:4; /*!< bit: 20..23 Reserved */\r
+ uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */\r
+ uint32_t IT:2; /*!< bit: 25..26 saved IT state (read 0) */\r
+ uint32_t Q:1; /*!< bit: 27 Saturation condition flag */\r
+ uint32_t V:1; /*!< bit: 28 Overflow condition code flag */\r
+ uint32_t C:1; /*!< bit: 29 Carry condition code flag */\r
+ uint32_t Z:1; /*!< bit: 30 Zero condition code flag */\r
+ uint32_t N:1; /*!< bit: 31 Negative condition code flag */\r
+ } b; /*!< Structure used for bit access */\r
+ uint32_t w; /*!< Type used for word access */\r
+} xPSR_Type;\r
+\r
+/* xPSR Register Definitions */\r
+#define xPSR_N_Pos 31U /*!< xPSR: N Position */\r
+#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */\r
+\r
+#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */\r
+#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */\r
+\r
+#define xPSR_C_Pos 29U /*!< xPSR: C Position */\r
+#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */\r
+\r
+#define xPSR_V_Pos 28U /*!< xPSR: V Position */\r
+#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */\r
+\r
+#define xPSR_Q_Pos 27U /*!< xPSR: Q Position */\r
+#define xPSR_Q_Msk (1UL << xPSR_Q_Pos) /*!< xPSR: Q Mask */\r
+\r
+#define xPSR_IT_Pos 25U /*!< xPSR: IT Position */\r
+#define xPSR_IT_Msk (3UL << xPSR_IT_Pos) /*!< xPSR: IT Mask */\r
+\r
+#define xPSR_T_Pos 24U /*!< xPSR: T Position */\r
+#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */\r
+\r
+#define xPSR_GE_Pos 16U /*!< xPSR: GE Position */\r
+#define xPSR_GE_Msk (0xFUL << xPSR_GE_Pos) /*!< xPSR: GE Mask */\r
+\r
+#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */\r
+#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */\r
+\r
+\r
+/**\r
+ \brief Union type to access the Control Registers (CONTROL).\r
+ */\r
+typedef union\r
+{\r
+ struct\r
+ {\r
+ uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */\r
+ uint32_t SPSEL:1; /*!< bit: 1 Stack-pointer select */\r
+ uint32_t FPCA:1; /*!< bit: 2 Floating-point context active */\r
+ uint32_t SFPA:1; /*!< bit: 3 Secure floating-point active */\r
+ uint32_t _reserved1:28; /*!< bit: 4..31 Reserved */\r
+ } b; /*!< Structure used for bit access */\r
+ uint32_t w; /*!< Type used for word access */\r
+} CONTROL_Type;\r
+\r
+/* CONTROL Register Definitions */\r
+#define CONTROL_SFPA_Pos 3U /*!< CONTROL: SFPA Position */\r
+#define CONTROL_SFPA_Msk (1UL << CONTROL_SFPA_Pos) /*!< CONTROL: SFPA Mask */\r
+\r
+#define CONTROL_FPCA_Pos 2U /*!< CONTROL: FPCA Position */\r
+#define CONTROL_FPCA_Msk (1UL << CONTROL_FPCA_Pos) /*!< CONTROL: FPCA Mask */\r
+\r
+#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */\r
+#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */\r
+\r
+#define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */\r
+#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */\r
+\r
+/*@} end of group CMSIS_CORE */\r
+\r
+\r
+/**\r
+ \ingroup CMSIS_core_register\r
+ \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC)\r
+ \brief Type definitions for the NVIC Registers\r
+ @{\r
+ */\r
+\r
+/**\r
+ \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC).\r
+ */\r
+typedef struct\r
+{\r
+ __IOM uint32_t ISER[16U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */\r
+ uint32_t RESERVED0[16U];\r
+ __IOM uint32_t ICER[16U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */\r
+ uint32_t RSERVED1[16U];\r
+ __IOM uint32_t ISPR[16U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */\r
+ uint32_t RESERVED2[16U];\r
+ __IOM uint32_t ICPR[16U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */\r
+ uint32_t RESERVED3[16U];\r
+ __IOM uint32_t IABR[16U]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */\r
+ uint32_t RESERVED4[16U];\r
+ __IOM uint32_t ITNS[16U]; /*!< Offset: 0x280 (R/W) Interrupt Non-Secure State Register */\r
+ uint32_t RESERVED5[16U];\r
+ __IOM uint8_t IPR[496U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */\r
+ uint32_t RESERVED6[580U];\r
+ __OM uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */\r
+} NVIC_Type;\r
+\r
+/* Software Triggered Interrupt Register Definitions */\r
+#define NVIC_STIR_INTID_Pos 0U /*!< STIR: INTLINESNUM Position */\r
+#define NVIC_STIR_INTID_Msk (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/) /*!< STIR: INTLINESNUM Mask */\r
+\r
+/*@} end of group CMSIS_NVIC */\r
+\r
+\r
+/**\r
+ \ingroup CMSIS_core_register\r
+ \defgroup CMSIS_SCB System Control Block (SCB)\r
+ \brief Type definitions for the System Control Block Registers\r
+ @{\r
+ */\r
+\r
+/**\r
+ \brief Structure type to access the System Control Block (SCB).\r
+ */\r
+typedef struct\r
+{\r
+ __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */\r
+ __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */\r
+ __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */\r
+ __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */\r
+ __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */\r
+ __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */\r
+ __IOM uint8_t SHPR[12U]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */\r
+ __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */\r
+ __IOM uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */\r
+ __IOM uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */\r
+ __IOM uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */\r
+ __IOM uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */\r
+ __IOM uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */\r
+ __IOM uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */\r
+ __IM uint32_t ID_PFR[2U]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */\r
+ __IM uint32_t ID_DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */\r
+ __IM uint32_t ID_ADR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */\r
+ __IM uint32_t ID_MMFR[4U]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */\r
+ __IM uint32_t ID_ISAR[6U]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */\r
+ __IM uint32_t CLIDR; /*!< Offset: 0x078 (R/ ) Cache Level ID register */\r
+ __IM uint32_t CTR; /*!< Offset: 0x07C (R/ ) Cache Type register */\r
+ __IM uint32_t CCSIDR; /*!< Offset: 0x080 (R/ ) Cache Size ID Register */\r
+ __IOM uint32_t CSSELR; /*!< Offset: 0x084 (R/W) Cache Size Selection Register */\r
+ __IOM uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */\r
+ __IOM uint32_t NSACR; /*!< Offset: 0x08C (R/W) Non-Secure Access Control Register */\r
+ uint32_t RESERVED3[92U];\r
+ __OM uint32_t STIR; /*!< Offset: 0x200 ( /W) Software Triggered Interrupt Register */\r
+ uint32_t RESERVED4[15U];\r
+ __IM uint32_t MVFR0; /*!< Offset: 0x240 (R/ ) Media and VFP Feature Register 0 */\r
+ __IM uint32_t MVFR1; /*!< Offset: 0x244 (R/ ) Media and VFP Feature Register 1 */\r
+ __IM uint32_t MVFR2; /*!< Offset: 0x248 (R/ ) Media and VFP Feature Register 2 */\r
+ uint32_t RESERVED5[1U];\r
+ __OM uint32_t ICIALLU; /*!< Offset: 0x250 ( /W) I-Cache Invalidate All to PoU */\r
+ uint32_t RESERVED6[1U];\r
+ __OM uint32_t ICIMVAU; /*!< Offset: 0x258 ( /W) I-Cache Invalidate by MVA to PoU */\r
+ __OM uint32_t DCIMVAC; /*!< Offset: 0x25C ( /W) D-Cache Invalidate by MVA to PoC */\r
+ __OM uint32_t DCISW; /*!< Offset: 0x260 ( /W) D-Cache Invalidate by Set-way */\r
+ __OM uint32_t DCCMVAU; /*!< Offset: 0x264 ( /W) D-Cache Clean by MVA to PoU */\r
+ __OM uint32_t DCCMVAC; /*!< Offset: 0x268 ( /W) D-Cache Clean by MVA to PoC */\r
+ __OM uint32_t DCCSW; /*!< Offset: 0x26C ( /W) D-Cache Clean by Set-way */\r
+ __OM uint32_t DCCIMVAC; /*!< Offset: 0x270 ( /W) D-Cache Clean and Invalidate by MVA to PoC */\r
+ __OM uint32_t DCCISW; /*!< Offset: 0x274 ( /W) D-Cache Clean and Invalidate by Set-way */\r
+ uint32_t RESERVED7[6U];\r
+ __IOM uint32_t ITCMCR; /*!< Offset: 0x290 (R/W) Instruction Tightly-Coupled Memory Control Register */\r
+ __IOM uint32_t DTCMCR; /*!< Offset: 0x294 (R/W) Data Tightly-Coupled Memory Control Registers */\r
+ __IOM uint32_t AHBPCR; /*!< Offset: 0x298 (R/W) AHBP Control Register */\r
+ __IOM uint32_t CACR; /*!< Offset: 0x29C (R/W) L1 Cache Control Register */\r
+ __IOM uint32_t AHBSCR; /*!< Offset: 0x2A0 (R/W) AHB Slave Control Register */\r
+ uint32_t RESERVED8[1U];\r
+ __IOM uint32_t ABFSR; /*!< Offset: 0x2A8 (R/W) Auxiliary Bus Fault Status Register */\r
+} SCB_Type;\r
+\r
+/* SCB CPUID Register Definitions */\r
+#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */\r
+#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */\r
+\r
+#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */\r
+#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */\r
+\r
+#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */\r
+#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */\r
+\r
+#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */\r
+#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */\r
+\r
+#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */\r
+#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */\r
+\r
+/* SCB Interrupt Control State Register Definitions */\r
+#define SCB_ICSR_PENDNMISET_Pos 31U /*!< SCB ICSR: PENDNMISET Position */\r
+#define SCB_ICSR_PENDNMISET_Msk (1UL << SCB_ICSR_PENDNMISET_Pos) /*!< SCB ICSR: PENDNMISET Mask */\r
+\r
+#define SCB_ICSR_NMIPENDSET_Pos SCB_ICSR_PENDNMISET_Pos /*!< SCB ICSR: NMIPENDSET Position, backward compatibility */\r
+#define SCB_ICSR_NMIPENDSET_Msk SCB_ICSR_PENDNMISET_Msk /*!< SCB ICSR: NMIPENDSET Mask, backward compatibility */\r
+\r
+#define SCB_ICSR_PENDNMICLR_Pos 30U /*!< SCB ICSR: PENDNMICLR Position */\r
+#define SCB_ICSR_PENDNMICLR_Msk (1UL << SCB_ICSR_PENDNMICLR_Pos) /*!< SCB ICSR: PENDNMICLR Mask */\r
+\r
+#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */\r
+#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */\r
+\r
+#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */\r
+#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */\r
+\r
+#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */\r
+#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */\r
+\r
+#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */\r
+#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */\r
+\r
+#define SCB_ICSR_STTNS_Pos 24U /*!< SCB ICSR: STTNS Position (Security Extension) */\r
+#define SCB_ICSR_STTNS_Msk (1UL << SCB_ICSR_STTNS_Pos) /*!< SCB ICSR: STTNS Mask (Security Extension) */\r
+\r
+#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */\r
+#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */\r
+\r
+#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */\r
+#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */\r
+\r
+#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */\r
+#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */\r
+\r
+#define SCB_ICSR_RETTOBASE_Pos 11U /*!< SCB ICSR: RETTOBASE Position */\r
+#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */\r
+\r
+#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */\r
+#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */\r
+\r
+/* SCB Vector Table Offset Register Definitions */\r
+#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */\r
+#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */\r
+\r
+/* SCB Application Interrupt and Reset Control Register Definitions */\r
+#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */\r
+#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */\r
+\r
+#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */\r
+#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */\r
+\r
+#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */\r
+#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */\r
+\r
+#define SCB_AIRCR_PRIS_Pos 14U /*!< SCB AIRCR: PRIS Position */\r
+#define SCB_AIRCR_PRIS_Msk (1UL << SCB_AIRCR_PRIS_Pos) /*!< SCB AIRCR: PRIS Mask */\r
+\r
+#define SCB_AIRCR_BFHFNMINS_Pos 13U /*!< SCB AIRCR: BFHFNMINS Position */\r
+#define SCB_AIRCR_BFHFNMINS_Msk (1UL << SCB_AIRCR_BFHFNMINS_Pos) /*!< SCB AIRCR: BFHFNMINS Mask */\r
+\r
+#define SCB_AIRCR_PRIGROUP_Pos 8U /*!< SCB AIRCR: PRIGROUP Position */\r
+#define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */\r
+\r
+#define SCB_AIRCR_SYSRESETREQS_Pos 3U /*!< SCB AIRCR: SYSRESETREQS Position */\r
+#define SCB_AIRCR_SYSRESETREQS_Msk (1UL << SCB_AIRCR_SYSRESETREQS_Pos) /*!< SCB AIRCR: SYSRESETREQS Mask */\r
+\r
+#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */\r
+#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */\r
+\r
+#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */\r
+#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */\r
+\r
+/* SCB System Control Register Definitions */\r
+#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */\r
+#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */\r
+\r
+#define SCB_SCR_SLEEPDEEPS_Pos 3U /*!< SCB SCR: SLEEPDEEPS Position */\r
+#define SCB_SCR_SLEEPDEEPS_Msk (1UL << SCB_SCR_SLEEPDEEPS_Pos) /*!< SCB SCR: SLEEPDEEPS Mask */\r
+\r
+#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */\r
+#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */\r
+\r
+#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */\r
+#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */\r
+\r
+/* SCB Configuration Control Register Definitions */\r
+#define SCB_CCR_BP_Pos 18U /*!< SCB CCR: BP Position */\r
+#define SCB_CCR_BP_Msk (1UL << SCB_CCR_BP_Pos) /*!< SCB CCR: BP Mask */\r
+\r
+#define SCB_CCR_IC_Pos 17U /*!< SCB CCR: IC Position */\r
+#define SCB_CCR_IC_Msk (1UL << SCB_CCR_IC_Pos) /*!< SCB CCR: IC Mask */\r
+\r
+#define SCB_CCR_DC_Pos 16U /*!< SCB CCR: DC Position */\r
+#define SCB_CCR_DC_Msk (1UL << SCB_CCR_DC_Pos) /*!< SCB CCR: DC Mask */\r
+\r
+#define SCB_CCR_STKOFHFNMIGN_Pos 10U /*!< SCB CCR: STKOFHFNMIGN Position */\r
+#define SCB_CCR_STKOFHFNMIGN_Msk (1UL << SCB_CCR_STKOFHFNMIGN_Pos) /*!< SCB CCR: STKOFHFNMIGN Mask */\r
+\r
+#define SCB_CCR_BFHFNMIGN_Pos 8U /*!< SCB CCR: BFHFNMIGN Position */\r
+#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */\r
+\r
+#define SCB_CCR_DIV_0_TRP_Pos 4U /*!< SCB CCR: DIV_0_TRP Position */\r
+#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */\r
+\r
+#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */\r
+#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */\r
+\r
+#define SCB_CCR_USERSETMPEND_Pos 1U /*!< SCB CCR: USERSETMPEND Position */\r
+#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */\r
+\r
+/* SCB System Handler Control and State Register Definitions */\r
+#define SCB_SHCSR_HARDFAULTPENDED_Pos 21U /*!< SCB SHCSR: HARDFAULTPENDED Position */\r
+#define SCB_SHCSR_HARDFAULTPENDED_Msk (1UL << SCB_SHCSR_HARDFAULTPENDED_Pos) /*!< SCB SHCSR: HARDFAULTPENDED Mask */\r
+\r
+#define SCB_SHCSR_SECUREFAULTPENDED_Pos 20U /*!< SCB SHCSR: SECUREFAULTPENDED Position */\r
+#define SCB_SHCSR_SECUREFAULTPENDED_Msk (1UL << SCB_SHCSR_SECUREFAULTPENDED_Pos) /*!< SCB SHCSR: SECUREFAULTPENDED Mask */\r
+\r
+#define SCB_SHCSR_SECUREFAULTENA_Pos 19U /*!< SCB SHCSR: SECUREFAULTENA Position */\r
+#define SCB_SHCSR_SECUREFAULTENA_Msk (1UL << SCB_SHCSR_SECUREFAULTENA_Pos) /*!< SCB SHCSR: SECUREFAULTENA Mask */\r
+\r
+#define SCB_SHCSR_USGFAULTENA_Pos 18U /*!< SCB SHCSR: USGFAULTENA Position */\r
+#define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */\r
+\r
+#define SCB_SHCSR_BUSFAULTENA_Pos 17U /*!< SCB SHCSR: BUSFAULTENA Position */\r
+#define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */\r
+\r
+#define SCB_SHCSR_MEMFAULTENA_Pos 16U /*!< SCB SHCSR: MEMFAULTENA Position */\r
+#define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */\r
+\r
+#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */\r
+#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */\r
+\r
+#define SCB_SHCSR_BUSFAULTPENDED_Pos 14U /*!< SCB SHCSR: BUSFAULTPENDED Position */\r
+#define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */\r
+\r
+#define SCB_SHCSR_MEMFAULTPENDED_Pos 13U /*!< SCB SHCSR: MEMFAULTPENDED Position */\r
+#define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */\r
+\r
+#define SCB_SHCSR_USGFAULTPENDED_Pos 12U /*!< SCB SHCSR: USGFAULTPENDED Position */\r
+#define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */\r
+\r
+#define SCB_SHCSR_SYSTICKACT_Pos 11U /*!< SCB SHCSR: SYSTICKACT Position */\r
+#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */\r
+\r
+#define SCB_SHCSR_PENDSVACT_Pos 10U /*!< SCB SHCSR: PENDSVACT Position */\r
+#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */\r
+\r
+#define SCB_SHCSR_MONITORACT_Pos 8U /*!< SCB SHCSR: MONITORACT Position */\r
+#define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */\r
+\r
+#define SCB_SHCSR_SVCALLACT_Pos 7U /*!< SCB SHCSR: SVCALLACT Position */\r
+#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */\r
+\r
+#define SCB_SHCSR_NMIACT_Pos 5U /*!< SCB SHCSR: NMIACT Position */\r
+#define SCB_SHCSR_NMIACT_Msk (1UL << SCB_SHCSR_NMIACT_Pos) /*!< SCB SHCSR: NMIACT Mask */\r
+\r
+#define SCB_SHCSR_SECUREFAULTACT_Pos 4U /*!< SCB SHCSR: SECUREFAULTACT Position */\r
+#define SCB_SHCSR_SECUREFAULTACT_Msk (1UL << SCB_SHCSR_SECUREFAULTACT_Pos) /*!< SCB SHCSR: SECUREFAULTACT Mask */\r
+\r
+#define SCB_SHCSR_USGFAULTACT_Pos 3U /*!< SCB SHCSR: USGFAULTACT Position */\r
+#define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */\r
+\r
+#define SCB_SHCSR_HARDFAULTACT_Pos 2U /*!< SCB SHCSR: HARDFAULTACT Position */\r
+#define SCB_SHCSR_HARDFAULTACT_Msk (1UL << SCB_SHCSR_HARDFAULTACT_Pos) /*!< SCB SHCSR: HARDFAULTACT Mask */\r
+\r
+#define SCB_SHCSR_BUSFAULTACT_Pos 1U /*!< SCB SHCSR: BUSFAULTACT Position */\r
+#define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */\r
+\r
+#define SCB_SHCSR_MEMFAULTACT_Pos 0U /*!< SCB SHCSR: MEMFAULTACT Position */\r
+#define SCB_SHCSR_MEMFAULTACT_Msk (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/) /*!< SCB SHCSR: MEMFAULTACT Mask */\r
+\r
+/* SCB Configurable Fault Status Register Definitions */\r
+#define SCB_CFSR_USGFAULTSR_Pos 16U /*!< SCB CFSR: Usage Fault Status Register Position */\r
+#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */\r
+\r
+#define SCB_CFSR_BUSFAULTSR_Pos 8U /*!< SCB CFSR: Bus Fault Status Register Position */\r
+#define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */\r
+\r
+#define SCB_CFSR_MEMFAULTSR_Pos 0U /*!< SCB CFSR: Memory Manage Fault Status Register Position */\r
+#define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */\r
+\r
+/* MemManage Fault Status Register (part of SCB Configurable Fault Status Register) */\r
+#define SCB_CFSR_MMARVALID_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 7U) /*!< SCB CFSR (MMFSR): MMARVALID Position */\r
+#define SCB_CFSR_MMARVALID_Msk (1UL << SCB_CFSR_MMARVALID_Pos) /*!< SCB CFSR (MMFSR): MMARVALID Mask */\r
+\r
+#define SCB_CFSR_MLSPERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 5U) /*!< SCB CFSR (MMFSR): MLSPERR Position */\r
+#define SCB_CFSR_MLSPERR_Msk (1UL << SCB_CFSR_MLSPERR_Pos) /*!< SCB CFSR (MMFSR): MLSPERR Mask */\r
+\r
+#define SCB_CFSR_MSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 4U) /*!< SCB CFSR (MMFSR): MSTKERR Position */\r
+#define SCB_CFSR_MSTKERR_Msk (1UL << SCB_CFSR_MSTKERR_Pos) /*!< SCB CFSR (MMFSR): MSTKERR Mask */\r
+\r
+#define SCB_CFSR_MUNSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 3U) /*!< SCB CFSR (MMFSR): MUNSTKERR Position */\r
+#define SCB_CFSR_MUNSTKERR_Msk (1UL << SCB_CFSR_MUNSTKERR_Pos) /*!< SCB CFSR (MMFSR): MUNSTKERR Mask */\r
+\r
+#define SCB_CFSR_DACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 1U) /*!< SCB CFSR (MMFSR): DACCVIOL Position */\r
+#define SCB_CFSR_DACCVIOL_Msk (1UL << SCB_CFSR_DACCVIOL_Pos) /*!< SCB CFSR (MMFSR): DACCVIOL Mask */\r
+\r
+#define SCB_CFSR_IACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 0U) /*!< SCB CFSR (MMFSR): IACCVIOL Position */\r
+#define SCB_CFSR_IACCVIOL_Msk (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/) /*!< SCB CFSR (MMFSR): IACCVIOL Mask */\r
+\r
+/* BusFault Status Register (part of SCB Configurable Fault Status Register) */\r
+#define SCB_CFSR_BFARVALID_Pos (SCB_CFSR_BUSFAULTSR_Pos + 7U) /*!< SCB CFSR (BFSR): BFARVALID Position */\r
+#define SCB_CFSR_BFARVALID_Msk (1UL << SCB_CFSR_BFARVALID_Pos) /*!< SCB CFSR (BFSR): BFARVALID Mask */\r
+\r
+#define SCB_CFSR_LSPERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 5U) /*!< SCB CFSR (BFSR): LSPERR Position */\r
+#define SCB_CFSR_LSPERR_Msk (1UL << SCB_CFSR_LSPERR_Pos) /*!< SCB CFSR (BFSR): LSPERR Mask */\r
+\r
+#define SCB_CFSR_STKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 4U) /*!< SCB CFSR (BFSR): STKERR Position */\r
+#define SCB_CFSR_STKERR_Msk (1UL << SCB_CFSR_STKERR_Pos) /*!< SCB CFSR (BFSR): STKERR Mask */\r
+\r
+#define SCB_CFSR_UNSTKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 3U) /*!< SCB CFSR (BFSR): UNSTKERR Position */\r
+#define SCB_CFSR_UNSTKERR_Msk (1UL << SCB_CFSR_UNSTKERR_Pos) /*!< SCB CFSR (BFSR): UNSTKERR Mask */\r
+\r
+#define SCB_CFSR_IMPRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 2U) /*!< SCB CFSR (BFSR): IMPRECISERR Position */\r
+#define SCB_CFSR_IMPRECISERR_Msk (1UL << SCB_CFSR_IMPRECISERR_Pos) /*!< SCB CFSR (BFSR): IMPRECISERR Mask */\r
+\r
+#define SCB_CFSR_PRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 1U) /*!< SCB CFSR (BFSR): PRECISERR Position */\r
+#define SCB_CFSR_PRECISERR_Msk (1UL << SCB_CFSR_PRECISERR_Pos) /*!< SCB CFSR (BFSR): PRECISERR Mask */\r
+\r
+#define SCB_CFSR_IBUSERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 0U) /*!< SCB CFSR (BFSR): IBUSERR Position */\r
+#define SCB_CFSR_IBUSERR_Msk (1UL << SCB_CFSR_IBUSERR_Pos) /*!< SCB CFSR (BFSR): IBUSERR Mask */\r
+\r
+/* UsageFault Status Register (part of SCB Configurable Fault Status Register) */\r
+#define SCB_CFSR_DIVBYZERO_Pos (SCB_CFSR_USGFAULTSR_Pos + 9U) /*!< SCB CFSR (UFSR): DIVBYZERO Position */\r
+#define SCB_CFSR_DIVBYZERO_Msk (1UL << SCB_CFSR_DIVBYZERO_Pos) /*!< SCB CFSR (UFSR): DIVBYZERO Mask */\r
+\r
+#define SCB_CFSR_UNALIGNED_Pos (SCB_CFSR_USGFAULTSR_Pos + 8U) /*!< SCB CFSR (UFSR): UNALIGNED Position */\r
+#define SCB_CFSR_UNALIGNED_Msk (1UL << SCB_CFSR_UNALIGNED_Pos) /*!< SCB CFSR (UFSR): UNALIGNED Mask */\r
+\r
+#define SCB_CFSR_STKOF_Pos (SCB_CFSR_USGFAULTSR_Pos + 4U) /*!< SCB CFSR (UFSR): STKOF Position */\r
+#define SCB_CFSR_STKOF_Msk (1UL << SCB_CFSR_STKOF_Pos) /*!< SCB CFSR (UFSR): STKOF Mask */\r
+\r
+#define SCB_CFSR_NOCP_Pos (SCB_CFSR_USGFAULTSR_Pos + 3U) /*!< SCB CFSR (UFSR): NOCP Position */\r
+#define SCB_CFSR_NOCP_Msk (1UL << SCB_CFSR_NOCP_Pos) /*!< SCB CFSR (UFSR): NOCP Mask */\r
+\r
+#define SCB_CFSR_INVPC_Pos (SCB_CFSR_USGFAULTSR_Pos + 2U) /*!< SCB CFSR (UFSR): INVPC Position */\r
+#define SCB_CFSR_INVPC_Msk (1UL << SCB_CFSR_INVPC_Pos) /*!< SCB CFSR (UFSR): INVPC Mask */\r
+\r
+#define SCB_CFSR_INVSTATE_Pos (SCB_CFSR_USGFAULTSR_Pos + 1U) /*!< SCB CFSR (UFSR): INVSTATE Position */\r
+#define SCB_CFSR_INVSTATE_Msk (1UL << SCB_CFSR_INVSTATE_Pos) /*!< SCB CFSR (UFSR): INVSTATE Mask */\r
+\r
+#define SCB_CFSR_UNDEFINSTR_Pos (SCB_CFSR_USGFAULTSR_Pos + 0U) /*!< SCB CFSR (UFSR): UNDEFINSTR Position */\r
+#define SCB_CFSR_UNDEFINSTR_Msk (1UL << SCB_CFSR_UNDEFINSTR_Pos) /*!< SCB CFSR (UFSR): UNDEFINSTR Mask */\r
+\r
+/* SCB Hard Fault Status Register Definitions */\r
+#define SCB_HFSR_DEBUGEVT_Pos 31U /*!< SCB HFSR: DEBUGEVT Position */\r
+#define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */\r
+\r
+#define SCB_HFSR_FORCED_Pos 30U /*!< SCB HFSR: FORCED Position */\r
+#define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */\r
+\r
+#define SCB_HFSR_VECTTBL_Pos 1U /*!< SCB HFSR: VECTTBL Position */\r
+#define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */\r
+\r
+/* SCB Debug Fault Status Register Definitions */\r
+#define SCB_DFSR_EXTERNAL_Pos 4U /*!< SCB DFSR: EXTERNAL Position */\r
+#define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */\r
+\r
+#define SCB_DFSR_VCATCH_Pos 3U /*!< SCB DFSR: VCATCH Position */\r
+#define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */\r
+\r
+#define SCB_DFSR_DWTTRAP_Pos 2U /*!< SCB DFSR: DWTTRAP Position */\r
+#define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */\r
+\r
+#define SCB_DFSR_BKPT_Pos 1U /*!< SCB DFSR: BKPT Position */\r
+#define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */\r
+\r
+#define SCB_DFSR_HALTED_Pos 0U /*!< SCB DFSR: HALTED Position */\r
+#define SCB_DFSR_HALTED_Msk (1UL /*<< SCB_DFSR_HALTED_Pos*/) /*!< SCB DFSR: HALTED Mask */\r
+\r
+/* SCB Non-Secure Access Control Register Definitions */\r
+#define SCB_NSACR_CP11_Pos 11U /*!< SCB NSACR: CP11 Position */\r
+#define SCB_NSACR_CP11_Msk (1UL << SCB_NSACR_CP11_Pos) /*!< SCB NSACR: CP11 Mask */\r
+\r
+#define SCB_NSACR_CP10_Pos 10U /*!< SCB NSACR: CP10 Position */\r
+#define SCB_NSACR_CP10_Msk (1UL << SCB_NSACR_CP10_Pos) /*!< SCB NSACR: CP10 Mask */\r
+\r
+#define SCB_NSACR_CPn_Pos 0U /*!< SCB NSACR: CPn Position */\r
+#define SCB_NSACR_CPn_Msk (1UL /*<< SCB_NSACR_CPn_Pos*/) /*!< SCB NSACR: CPn Mask */\r
+\r
+/* SCB Cache Level ID Register Definitions */\r
+#define SCB_CLIDR_LOUU_Pos 27U /*!< SCB CLIDR: LoUU Position */\r
+#define SCB_CLIDR_LOUU_Msk (7UL << SCB_CLIDR_LOUU_Pos) /*!< SCB CLIDR: LoUU Mask */\r
+\r
+#define SCB_CLIDR_LOC_Pos 24U /*!< SCB CLIDR: LoC Position */\r
+#define SCB_CLIDR_LOC_Msk (7UL << SCB_CLIDR_LOC_Pos) /*!< SCB CLIDR: LoC Mask */\r
+\r
+/* SCB Cache Type Register Definitions */\r
+#define SCB_CTR_FORMAT_Pos 29U /*!< SCB CTR: Format Position */\r
+#define SCB_CTR_FORMAT_Msk (7UL << SCB_CTR_FORMAT_Pos) /*!< SCB CTR: Format Mask */\r
+\r
+#define SCB_CTR_CWG_Pos 24U /*!< SCB CTR: CWG Position */\r
+#define SCB_CTR_CWG_Msk (0xFUL << SCB_CTR_CWG_Pos) /*!< SCB CTR: CWG Mask */\r
+\r
+#define SCB_CTR_ERG_Pos 20U /*!< SCB CTR: ERG Position */\r
+#define SCB_CTR_ERG_Msk (0xFUL << SCB_CTR_ERG_Pos) /*!< SCB CTR: ERG Mask */\r
+\r
+#define SCB_CTR_DMINLINE_Pos 16U /*!< SCB CTR: DminLine Position */\r
+#define SCB_CTR_DMINLINE_Msk (0xFUL << SCB_CTR_DMINLINE_Pos) /*!< SCB CTR: DminLine Mask */\r
+\r
+#define SCB_CTR_IMINLINE_Pos 0U /*!< SCB CTR: ImInLine Position */\r
+#define SCB_CTR_IMINLINE_Msk (0xFUL /*<< SCB_CTR_IMINLINE_Pos*/) /*!< SCB CTR: ImInLine Mask */\r
+\r
+/* SCB Cache Size ID Register Definitions */\r
+#define SCB_CCSIDR_WT_Pos 31U /*!< SCB CCSIDR: WT Position */\r
+#define SCB_CCSIDR_WT_Msk (1UL << SCB_CCSIDR_WT_Pos) /*!< SCB CCSIDR: WT Mask */\r
+\r
+#define SCB_CCSIDR_WB_Pos 30U /*!< SCB CCSIDR: WB Position */\r
+#define SCB_CCSIDR_WB_Msk (1UL << SCB_CCSIDR_WB_Pos) /*!< SCB CCSIDR: WB Mask */\r
+\r
+#define SCB_CCSIDR_RA_Pos 29U /*!< SCB CCSIDR: RA Position */\r
+#define SCB_CCSIDR_RA_Msk (1UL << SCB_CCSIDR_RA_Pos) /*!< SCB CCSIDR: RA Mask */\r
+\r
+#define SCB_CCSIDR_WA_Pos 28U /*!< SCB CCSIDR: WA Position */\r
+#define SCB_CCSIDR_WA_Msk (1UL << SCB_CCSIDR_WA_Pos) /*!< SCB CCSIDR: WA Mask */\r
+\r
+#define SCB_CCSIDR_NUMSETS_Pos 13U /*!< SCB CCSIDR: NumSets Position */\r
+#define SCB_CCSIDR_NUMSETS_Msk (0x7FFFUL << SCB_CCSIDR_NUMSETS_Pos) /*!< SCB CCSIDR: NumSets Mask */\r
+\r
+#define SCB_CCSIDR_ASSOCIATIVITY_Pos 3U /*!< SCB CCSIDR: Associativity Position */\r
+#define SCB_CCSIDR_ASSOCIATIVITY_Msk (0x3FFUL << SCB_CCSIDR_ASSOCIATIVITY_Pos) /*!< SCB CCSIDR: Associativity Mask */\r
+\r
+#define SCB_CCSIDR_LINESIZE_Pos 0U /*!< SCB CCSIDR: LineSize Position */\r
+#define SCB_CCSIDR_LINESIZE_Msk (7UL /*<< SCB_CCSIDR_LINESIZE_Pos*/) /*!< SCB CCSIDR: LineSize Mask */\r
+\r
+/* SCB Cache Size Selection Register Definitions */\r
+#define SCB_CSSELR_LEVEL_Pos 1U /*!< SCB CSSELR: Level Position */\r
+#define SCB_CSSELR_LEVEL_Msk (7UL << SCB_CSSELR_LEVEL_Pos) /*!< SCB CSSELR: Level Mask */\r
+\r
+#define SCB_CSSELR_IND_Pos 0U /*!< SCB CSSELR: InD Position */\r
+#define SCB_CSSELR_IND_Msk (1UL /*<< SCB_CSSELR_IND_Pos*/) /*!< SCB CSSELR: InD Mask */\r
+\r
+/* SCB Software Triggered Interrupt Register Definitions */\r
+#define SCB_STIR_INTID_Pos 0U /*!< SCB STIR: INTID Position */\r
+#define SCB_STIR_INTID_Msk (0x1FFUL /*<< SCB_STIR_INTID_Pos*/) /*!< SCB STIR: INTID Mask */\r
+\r
+/* SCB D-Cache Invalidate by Set-way Register Definitions */\r
+#define SCB_DCISW_WAY_Pos 30U /*!< SCB DCISW: Way Position */\r
+#define SCB_DCISW_WAY_Msk (3UL << SCB_DCISW_WAY_Pos) /*!< SCB DCISW: Way Mask */\r
+\r
+#define SCB_DCISW_SET_Pos 5U /*!< SCB DCISW: Set Position */\r
+#define SCB_DCISW_SET_Msk (0x1FFUL << SCB_DCISW_SET_Pos) /*!< SCB DCISW: Set Mask */\r
+\r
+/* SCB D-Cache Clean by Set-way Register Definitions */\r
+#define SCB_DCCSW_WAY_Pos 30U /*!< SCB DCCSW: Way Position */\r
+#define SCB_DCCSW_WAY_Msk (3UL << SCB_DCCSW_WAY_Pos) /*!< SCB DCCSW: Way Mask */\r
+\r
+#define SCB_DCCSW_SET_Pos 5U /*!< SCB DCCSW: Set Position */\r
+#define SCB_DCCSW_SET_Msk (0x1FFUL << SCB_DCCSW_SET_Pos) /*!< SCB DCCSW: Set Mask */\r
+\r
+/* SCB D-Cache Clean and Invalidate by Set-way Register Definitions */\r
+#define SCB_DCCISW_WAY_Pos 30U /*!< SCB DCCISW: Way Position */\r
+#define SCB_DCCISW_WAY_Msk (3UL << SCB_DCCISW_WAY_Pos) /*!< SCB DCCISW: Way Mask */\r
+\r
+#define SCB_DCCISW_SET_Pos 5U /*!< SCB DCCISW: Set Position */\r
+#define SCB_DCCISW_SET_Msk (0x1FFUL << SCB_DCCISW_SET_Pos) /*!< SCB DCCISW: Set Mask */\r
+\r
+/* Instruction Tightly-Coupled Memory Control Register Definitions */\r
+#define SCB_ITCMCR_SZ_Pos 3U /*!< SCB ITCMCR: SZ Position */\r
+#define SCB_ITCMCR_SZ_Msk (0xFUL << SCB_ITCMCR_SZ_Pos) /*!< SCB ITCMCR: SZ Mask */\r
+\r
+#define SCB_ITCMCR_RETEN_Pos 2U /*!< SCB ITCMCR: RETEN Position */\r
+#define SCB_ITCMCR_RETEN_Msk (1UL << SCB_ITCMCR_RETEN_Pos) /*!< SCB ITCMCR: RETEN Mask */\r
+\r
+#define SCB_ITCMCR_RMW_Pos 1U /*!< SCB ITCMCR: RMW Position */\r
+#define SCB_ITCMCR_RMW_Msk (1UL << SCB_ITCMCR_RMW_Pos) /*!< SCB ITCMCR: RMW Mask */\r
+\r
+#define SCB_ITCMCR_EN_Pos 0U /*!< SCB ITCMCR: EN Position */\r
+#define SCB_ITCMCR_EN_Msk (1UL /*<< SCB_ITCMCR_EN_Pos*/) /*!< SCB ITCMCR: EN Mask */\r
+\r
+/* Data Tightly-Coupled Memory Control Register Definitions */\r
+#define SCB_DTCMCR_SZ_Pos 3U /*!< SCB DTCMCR: SZ Position */\r
+#define SCB_DTCMCR_SZ_Msk (0xFUL << SCB_DTCMCR_SZ_Pos) /*!< SCB DTCMCR: SZ Mask */\r
+\r
+#define SCB_DTCMCR_RETEN_Pos 2U /*!< SCB DTCMCR: RETEN Position */\r
+#define SCB_DTCMCR_RETEN_Msk (1UL << SCB_DTCMCR_RETEN_Pos) /*!< SCB DTCMCR: RETEN Mask */\r
+\r
+#define SCB_DTCMCR_RMW_Pos 1U /*!< SCB DTCMCR: RMW Position */\r
+#define SCB_DTCMCR_RMW_Msk (1UL << SCB_DTCMCR_RMW_Pos) /*!< SCB DTCMCR: RMW Mask */\r
+\r
+#define SCB_DTCMCR_EN_Pos 0U /*!< SCB DTCMCR: EN Position */\r
+#define SCB_DTCMCR_EN_Msk (1UL /*<< SCB_DTCMCR_EN_Pos*/) /*!< SCB DTCMCR: EN Mask */\r
+\r
+/* AHBP Control Register Definitions */\r
+#define SCB_AHBPCR_SZ_Pos 1U /*!< SCB AHBPCR: SZ Position */\r
+#define SCB_AHBPCR_SZ_Msk (7UL << SCB_AHBPCR_SZ_Pos) /*!< SCB AHBPCR: SZ Mask */\r
+\r
+#define SCB_AHBPCR_EN_Pos 0U /*!< SCB AHBPCR: EN Position */\r
+#define SCB_AHBPCR_EN_Msk (1UL /*<< SCB_AHBPCR_EN_Pos*/) /*!< SCB AHBPCR: EN Mask */\r
+\r
+/* L1 Cache Control Register Definitions */\r
+#define SCB_CACR_FORCEWT_Pos 2U /*!< SCB CACR: FORCEWT Position */\r
+#define SCB_CACR_FORCEWT_Msk (1UL << SCB_CACR_FORCEWT_Pos) /*!< SCB CACR: FORCEWT Mask */\r
+\r
+#define SCB_CACR_ECCEN_Pos 1U /*!< SCB CACR: ECCEN Position */\r
+#define SCB_CACR_ECCEN_Msk (1UL << SCB_CACR_ECCEN_Pos) /*!< SCB CACR: ECCEN Mask */\r
+\r
+#define SCB_CACR_SIWT_Pos 0U /*!< SCB CACR: SIWT Position */\r
+#define SCB_CACR_SIWT_Msk (1UL /*<< SCB_CACR_SIWT_Pos*/) /*!< SCB CACR: SIWT Mask */\r
+\r
+/* AHBS Control Register Definitions */\r
+#define SCB_AHBSCR_INITCOUNT_Pos 11U /*!< SCB AHBSCR: INITCOUNT Position */\r
+#define SCB_AHBSCR_INITCOUNT_Msk (0x1FUL << SCB_AHBPCR_INITCOUNT_Pos) /*!< SCB AHBSCR: INITCOUNT Mask */\r
+\r
+#define SCB_AHBSCR_TPRI_Pos 2U /*!< SCB AHBSCR: TPRI Position */\r
+#define SCB_AHBSCR_TPRI_Msk (0x1FFUL << SCB_AHBPCR_TPRI_Pos) /*!< SCB AHBSCR: TPRI Mask */\r
+\r
+#define SCB_AHBSCR_CTL_Pos 0U /*!< SCB AHBSCR: CTL Position*/\r
+#define SCB_AHBSCR_CTL_Msk (3UL /*<< SCB_AHBPCR_CTL_Pos*/) /*!< SCB AHBSCR: CTL Mask */\r
+\r
+/* Auxiliary Bus Fault Status Register Definitions */\r
+#define SCB_ABFSR_AXIMTYPE_Pos 8U /*!< SCB ABFSR: AXIMTYPE Position*/\r
+#define SCB_ABFSR_AXIMTYPE_Msk (3UL << SCB_ABFSR_AXIMTYPE_Pos) /*!< SCB ABFSR: AXIMTYPE Mask */\r
+\r
+#define SCB_ABFSR_EPPB_Pos 4U /*!< SCB ABFSR: EPPB Position*/\r
+#define SCB_ABFSR_EPPB_Msk (1UL << SCB_ABFSR_EPPB_Pos) /*!< SCB ABFSR: EPPB Mask */\r
+\r
+#define SCB_ABFSR_AXIM_Pos 3U /*!< SCB ABFSR: AXIM Position*/\r
+#define SCB_ABFSR_AXIM_Msk (1UL << SCB_ABFSR_AXIM_Pos) /*!< SCB ABFSR: AXIM Mask */\r
+\r
+#define SCB_ABFSR_AHBP_Pos 2U /*!< SCB ABFSR: AHBP Position*/\r
+#define SCB_ABFSR_AHBP_Msk (1UL << SCB_ABFSR_AHBP_Pos) /*!< SCB ABFSR: AHBP Mask */\r
+\r
+#define SCB_ABFSR_DTCM_Pos 1U /*!< SCB ABFSR: DTCM Position*/\r
+#define SCB_ABFSR_DTCM_Msk (1UL << SCB_ABFSR_DTCM_Pos) /*!< SCB ABFSR: DTCM Mask */\r
+\r
+#define SCB_ABFSR_ITCM_Pos 0U /*!< SCB ABFSR: ITCM Position*/\r
+#define SCB_ABFSR_ITCM_Msk (1UL /*<< SCB_ABFSR_ITCM_Pos*/) /*!< SCB ABFSR: ITCM Mask */\r
+\r
+/*@} end of group CMSIS_SCB */\r
+\r
+\r
+/**\r
+ \ingroup CMSIS_core_register\r
+ \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB)\r
+ \brief Type definitions for the System Control and ID Register not in the SCB\r
+ @{\r
+ */\r
+\r
+/**\r
+ \brief Structure type to access the System Control and ID Register not in the SCB.\r
+ */\r
+typedef struct\r
+{\r
+ uint32_t RESERVED0[1U];\r
+ __IM uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */\r
+ __IOM uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */\r
+ __IOM uint32_t CPPWR; /*!< Offset: 0x00C (R/W) Coprocessor Power Control Register */\r
+} SCnSCB_Type;\r
+\r
+/* Interrupt Controller Type Register Definitions */\r
+#define SCnSCB_ICTR_INTLINESNUM_Pos 0U /*!< ICTR: INTLINESNUM Position */\r
+#define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/) /*!< ICTR: INTLINESNUM Mask */\r
+\r
+/*@} end of group CMSIS_SCnotSCB */\r
+\r
+\r
+/**\r
+ \ingroup CMSIS_core_register\r
+ \defgroup CMSIS_SysTick System Tick Timer (SysTick)\r
+ \brief Type definitions for the System Timer Registers.\r
+ @{\r
+ */\r
+\r
+/**\r
+ \brief Structure type to access the System Timer (SysTick).\r
+ */\r
+typedef struct\r
+{\r
+ __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */\r
+ __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */\r
+ __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */\r
+ __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */\r
+} SysTick_Type;\r
+\r
+/* SysTick Control / Status Register Definitions */\r
+#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */\r
+#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */\r
+\r
+#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */\r
+#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */\r
+\r
+#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */\r
+#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */\r
+\r
+#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */\r
+#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */\r
+\r
+/* SysTick Reload Register Definitions */\r
+#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */\r
+#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */\r
+\r
+/* SysTick Current Register Definitions */\r
+#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */\r
+#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */\r
+\r
+/* SysTick Calibration Register Definitions */\r
+#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */\r
+#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */\r
+\r
+#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */\r
+#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */\r
+\r
+#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */\r
+#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */\r
+\r
+/*@} end of group CMSIS_SysTick */\r
+\r
+\r
+/**\r
+ \ingroup CMSIS_core_register\r
+ \defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM)\r
+ \brief Type definitions for the Instrumentation Trace Macrocell (ITM)\r
+ @{\r
+ */\r
+\r
+/**\r
+ \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM).\r
+ */\r
+typedef struct\r
+{\r
+ __OM union\r
+ {\r
+ __OM uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */\r
+ __OM uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */\r
+ __OM uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */\r
+ } PORT [32U]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */\r
+ uint32_t RESERVED0[864U];\r
+ __IOM uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */\r
+ uint32_t RESERVED1[15U];\r
+ __IOM uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */\r
+ uint32_t RESERVED2[15U];\r
+ __IOM uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */\r
+ uint32_t RESERVED3[29U];\r
+ __OM uint32_t IWR; /*!< Offset: 0xEF8 ( /W) ITM Integration Write Register */\r
+ __IM uint32_t IRR; /*!< Offset: 0xEFC (R/ ) ITM Integration Read Register */\r
+ __IOM uint32_t IMCR; /*!< Offset: 0xF00 (R/W) ITM Integration Mode Control Register */\r
+ uint32_t RESERVED4[43U];\r
+ __OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */\r
+ __IM uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */\r
+ uint32_t RESERVED5[1U];\r
+ __IM uint32_t DEVARCH; /*!< Offset: 0xFBC (R/ ) ITM Device Architecture Register */\r
+ uint32_t RESERVED6[4U];\r
+ __IM uint32_t PID4; /*!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 */\r
+ __IM uint32_t PID5; /*!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 */\r
+ __IM uint32_t PID6; /*!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 */\r
+ __IM uint32_t PID7; /*!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 */\r
+ __IM uint32_t PID0; /*!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 */\r
+ __IM uint32_t PID1; /*!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 */\r
+ __IM uint32_t PID2; /*!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 */\r
+ __IM uint32_t PID3; /*!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 */\r
+ __IM uint32_t CID0; /*!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 */\r
+ __IM uint32_t CID1; /*!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 */\r
+ __IM uint32_t CID2; /*!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 */\r
+ __IM uint32_t CID3; /*!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 */\r
+} ITM_Type;\r
+\r
+/* ITM Stimulus Port Register Definitions */\r
+#define ITM_STIM_DISABLED_Pos 1U /*!< ITM STIM: DISABLED Position */\r
+#define ITM_STIM_DISABLED_Msk (0x1UL << ITM_STIM_DISABLED_Pos) /*!< ITM STIM: DISABLED Mask */\r
+\r
+#define ITM_STIM_FIFOREADY_Pos 0U /*!< ITM STIM: FIFOREADY Position */\r
+#define ITM_STIM_FIFOREADY_Msk (0x1UL /*<< ITM_STIM_FIFOREADY_Pos*/) /*!< ITM STIM: FIFOREADY Mask */\r
+\r
+/* ITM Trace Privilege Register Definitions */\r
+#define ITM_TPR_PRIVMASK_Pos 0U /*!< ITM TPR: PRIVMASK Position */\r
+#define ITM_TPR_PRIVMASK_Msk (0xFUL /*<< ITM_TPR_PRIVMASK_Pos*/) /*!< ITM TPR: PRIVMASK Mask */\r
+\r
+/* ITM Trace Control Register Definitions */\r
+#define ITM_TCR_BUSY_Pos 23U /*!< ITM TCR: BUSY Position */\r
+#define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */\r
+\r
+#define ITM_TCR_TRACEBUSID_Pos 16U /*!< ITM TCR: ATBID Position */\r
+#define ITM_TCR_TRACEBUSID_Msk (0x7FUL << ITM_TCR_TRACEBUSID_Pos) /*!< ITM TCR: ATBID Mask */\r
+\r
+#define ITM_TCR_GTSFREQ_Pos 10U /*!< ITM TCR: Global timestamp frequency Position */\r
+#define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */\r
+\r
+#define ITM_TCR_TSPRESCALE_Pos 8U /*!< ITM TCR: TSPRESCALE Position */\r
+#define ITM_TCR_TSPRESCALE_Msk (3UL << ITM_TCR_TSPRESCALE_Pos) /*!< ITM TCR: TSPRESCALE Mask */\r
+\r
+#define ITM_TCR_STALLENA_Pos 5U /*!< ITM TCR: STALLENA Position */\r
+#define ITM_TCR_STALLENA_Msk (1UL << ITM_TCR_STALLENA_Pos) /*!< ITM TCR: STALLENA Mask */\r
+\r
+#define ITM_TCR_SWOENA_Pos 4U /*!< ITM TCR: SWOENA Position */\r
+#define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */\r
+\r
+#define ITM_TCR_DWTENA_Pos 3U /*!< ITM TCR: DWTENA Position */\r
+#define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */\r
+\r
+#define ITM_TCR_SYNCENA_Pos 2U /*!< ITM TCR: SYNCENA Position */\r
+#define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */\r
+\r
+#define ITM_TCR_TSENA_Pos 1U /*!< ITM TCR: TSENA Position */\r
+#define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */\r
+\r
+#define ITM_TCR_ITMENA_Pos 0U /*!< ITM TCR: ITM Enable bit Position */\r
+#define ITM_TCR_ITMENA_Msk (1UL /*<< ITM_TCR_ITMENA_Pos*/) /*!< ITM TCR: ITM Enable bit Mask */\r
+\r
+/* ITM Integration Write Register Definitions */\r
+#define ITM_IWR_ATVALIDM_Pos 0U /*!< ITM IWR: ATVALIDM Position */\r
+#define ITM_IWR_ATVALIDM_Msk (1UL /*<< ITM_IWR_ATVALIDM_Pos*/) /*!< ITM IWR: ATVALIDM Mask */\r
+\r
+/* ITM Integration Read Register Definitions */\r
+#define ITM_IRR_ATREADYM_Pos 0U /*!< ITM IRR: ATREADYM Position */\r
+#define ITM_IRR_ATREADYM_Msk (1UL /*<< ITM_IRR_ATREADYM_Pos*/) /*!< ITM IRR: ATREADYM Mask */\r
+\r
+/* ITM Integration Mode Control Register Definitions */\r
+#define ITM_IMCR_INTEGRATION_Pos 0U /*!< ITM IMCR: INTEGRATION Position */\r
+#define ITM_IMCR_INTEGRATION_Msk (1UL /*<< ITM_IMCR_INTEGRATION_Pos*/) /*!< ITM IMCR: INTEGRATION Mask */\r
+\r
+/* ITM Lock Status Register Definitions */\r
+#define ITM_LSR_ByteAcc_Pos 2U /*!< ITM LSR: ByteAcc Position */\r
+#define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */\r
+\r
+#define ITM_LSR_Access_Pos 1U /*!< ITM LSR: Access Position */\r
+#define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */\r
+\r
+#define ITM_LSR_Present_Pos 0U /*!< ITM LSR: Present Position */\r
+#define ITM_LSR_Present_Msk (1UL /*<< ITM_LSR_Present_Pos*/) /*!< ITM LSR: Present Mask */\r
+\r
+/*@}*/ /* end of group CMSIS_ITM */\r
+\r
+\r
+/**\r
+ \ingroup CMSIS_core_register\r
+ \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT)\r
+ \brief Type definitions for the Data Watchpoint and Trace (DWT)\r
+ @{\r
+ */\r
+\r
+/**\r
+ \brief Structure type to access the Data Watchpoint and Trace Register (DWT).\r
+ */\r
+typedef struct\r
+{\r
+ __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */\r
+ __IOM uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */\r
+ __IOM uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */\r
+ __IOM uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */\r
+ __IOM uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */\r
+ __IOM uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */\r
+ __IOM uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */\r
+ __IM uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */\r
+ __IOM uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */\r
+ uint32_t RESERVED1[1U];\r
+ __IOM uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */\r
+ uint32_t RESERVED2[1U];\r
+ __IOM uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */\r
+ uint32_t RESERVED3[1U];\r
+ __IOM uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */\r
+ uint32_t RESERVED4[1U];\r
+ __IOM uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */\r
+ uint32_t RESERVED5[1U];\r
+ __IOM uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */\r
+ uint32_t RESERVED6[1U];\r
+ __IOM uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */\r
+ uint32_t RESERVED7[1U];\r
+ __IOM uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */\r
+ uint32_t RESERVED8[1U];\r
+ __IOM uint32_t COMP4; /*!< Offset: 0x060 (R/W) Comparator Register 4 */\r
+ uint32_t RESERVED9[1U];\r
+ __IOM uint32_t FUNCTION4; /*!< Offset: 0x068 (R/W) Function Register 4 */\r
+ uint32_t RESERVED10[1U];\r
+ __IOM uint32_t COMP5; /*!< Offset: 0x070 (R/W) Comparator Register 5 */\r
+ uint32_t RESERVED11[1U];\r
+ __IOM uint32_t FUNCTION5; /*!< Offset: 0x078 (R/W) Function Register 5 */\r
+ uint32_t RESERVED12[1U];\r
+ __IOM uint32_t COMP6; /*!< Offset: 0x080 (R/W) Comparator Register 6 */\r
+ uint32_t RESERVED13[1U];\r
+ __IOM uint32_t FUNCTION6; /*!< Offset: 0x088 (R/W) Function Register 6 */\r
+ uint32_t RESERVED14[1U];\r
+ __IOM uint32_t COMP7; /*!< Offset: 0x090 (R/W) Comparator Register 7 */\r
+ uint32_t RESERVED15[1U];\r
+ __IOM uint32_t FUNCTION7; /*!< Offset: 0x098 (R/W) Function Register 7 */\r
+ uint32_t RESERVED16[1U];\r
+ __IOM uint32_t COMP8; /*!< Offset: 0x0A0 (R/W) Comparator Register 8 */\r
+ uint32_t RESERVED17[1U];\r
+ __IOM uint32_t FUNCTION8; /*!< Offset: 0x0A8 (R/W) Function Register 8 */\r
+ uint32_t RESERVED18[1U];\r
+ __IOM uint32_t COMP9; /*!< Offset: 0x0B0 (R/W) Comparator Register 9 */\r
+ uint32_t RESERVED19[1U];\r
+ __IOM uint32_t FUNCTION9; /*!< Offset: 0x0B8 (R/W) Function Register 9 */\r
+ uint32_t RESERVED20[1U];\r
+ __IOM uint32_t COMP10; /*!< Offset: 0x0C0 (R/W) Comparator Register 10 */\r
+ uint32_t RESERVED21[1U];\r
+ __IOM uint32_t FUNCTION10; /*!< Offset: 0x0C8 (R/W) Function Register 10 */\r
+ uint32_t RESERVED22[1U];\r
+ __IOM uint32_t COMP11; /*!< Offset: 0x0D0 (R/W) Comparator Register 11 */\r
+ uint32_t RESERVED23[1U];\r
+ __IOM uint32_t FUNCTION11; /*!< Offset: 0x0D8 (R/W) Function Register 11 */\r
+ uint32_t RESERVED24[1U];\r
+ __IOM uint32_t COMP12; /*!< Offset: 0x0E0 (R/W) Comparator Register 12 */\r
+ uint32_t RESERVED25[1U];\r
+ __IOM uint32_t FUNCTION12; /*!< Offset: 0x0E8 (R/W) Function Register 12 */\r
+ uint32_t RESERVED26[1U];\r
+ __IOM uint32_t COMP13; /*!< Offset: 0x0F0 (R/W) Comparator Register 13 */\r
+ uint32_t RESERVED27[1U];\r
+ __IOM uint32_t FUNCTION13; /*!< Offset: 0x0F8 (R/W) Function Register 13 */\r
+ uint32_t RESERVED28[1U];\r
+ __IOM uint32_t COMP14; /*!< Offset: 0x100 (R/W) Comparator Register 14 */\r
+ uint32_t RESERVED29[1U];\r
+ __IOM uint32_t FUNCTION14; /*!< Offset: 0x108 (R/W) Function Register 14 */\r
+ uint32_t RESERVED30[1U];\r
+ __IOM uint32_t COMP15; /*!< Offset: 0x110 (R/W) Comparator Register 15 */\r
+ uint32_t RESERVED31[1U];\r
+ __IOM uint32_t FUNCTION15; /*!< Offset: 0x118 (R/W) Function Register 15 */\r
+ uint32_t RESERVED32[934U];\r
+ __IM uint32_t LSR; /*!< Offset: 0xFB4 (R ) Lock Status Register */\r
+ uint32_t RESERVED33[1U];\r
+ __IM uint32_t DEVARCH; /*!< Offset: 0xFBC (R/ ) Device Architecture Register */\r
+} DWT_Type;\r
+\r
+/* DWT Control Register Definitions */\r
+#define DWT_CTRL_NUMCOMP_Pos 28U /*!< DWT CTRL: NUMCOMP Position */\r
+#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */\r
+\r
+#define DWT_CTRL_NOTRCPKT_Pos 27U /*!< DWT CTRL: NOTRCPKT Position */\r
+#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */\r
+\r
+#define DWT_CTRL_NOEXTTRIG_Pos 26U /*!< DWT CTRL: NOEXTTRIG Position */\r
+#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */\r
+\r
+#define DWT_CTRL_NOCYCCNT_Pos 25U /*!< DWT CTRL: NOCYCCNT Position */\r
+#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */\r
+\r
+#define DWT_CTRL_NOPRFCNT_Pos 24U /*!< DWT CTRL: NOPRFCNT Position */\r
+#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */\r
+\r
+#define DWT_CTRL_CYCDISS_Pos 23U /*!< DWT CTRL: CYCDISS Position */\r
+#define DWT_CTRL_CYCDISS_Msk (0x1UL << DWT_CTRL_CYCDISS_Pos) /*!< DWT CTRL: CYCDISS Mask */\r
+\r
+#define DWT_CTRL_CYCEVTENA_Pos 22U /*!< DWT CTRL: CYCEVTENA Position */\r
+#define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */\r
+\r
+#define DWT_CTRL_FOLDEVTENA_Pos 21U /*!< DWT CTRL: FOLDEVTENA Position */\r
+#define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */\r
+\r
+#define DWT_CTRL_LSUEVTENA_Pos 20U /*!< DWT CTRL: LSUEVTENA Position */\r
+#define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */\r
+\r
+#define DWT_CTRL_SLEEPEVTENA_Pos 19U /*!< DWT CTRL: SLEEPEVTENA Position */\r
+#define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */\r
+\r
+#define DWT_CTRL_EXCEVTENA_Pos 18U /*!< DWT CTRL: EXCEVTENA Position */\r
+#define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */\r
+\r
+#define DWT_CTRL_CPIEVTENA_Pos 17U /*!< DWT CTRL: CPIEVTENA Position */\r
+#define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */\r
+\r
+#define DWT_CTRL_EXCTRCENA_Pos 16U /*!< DWT CTRL: EXCTRCENA Position */\r
+#define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */\r
+\r
+#define DWT_CTRL_PCSAMPLENA_Pos 12U /*!< DWT CTRL: PCSAMPLENA Position */\r
+#define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */\r
+\r
+#define DWT_CTRL_SYNCTAP_Pos 10U /*!< DWT CTRL: SYNCTAP Position */\r
+#define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */\r
+\r
+#define DWT_CTRL_CYCTAP_Pos 9U /*!< DWT CTRL: CYCTAP Position */\r
+#define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */\r
+\r
+#define DWT_CTRL_POSTINIT_Pos 5U /*!< DWT CTRL: POSTINIT Position */\r
+#define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */\r
+\r
+#define DWT_CTRL_POSTPRESET_Pos 1U /*!< DWT CTRL: POSTPRESET Position */\r
+#define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */\r
+\r
+#define DWT_CTRL_CYCCNTENA_Pos 0U /*!< DWT CTRL: CYCCNTENA Position */\r
+#define DWT_CTRL_CYCCNTENA_Msk (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/) /*!< DWT CTRL: CYCCNTENA Mask */\r
+\r
+/* DWT CPI Count Register Definitions */\r
+#define DWT_CPICNT_CPICNT_Pos 0U /*!< DWT CPICNT: CPICNT Position */\r
+#define DWT_CPICNT_CPICNT_Msk (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/) /*!< DWT CPICNT: CPICNT Mask */\r
+\r
+/* DWT Exception Overhead Count Register Definitions */\r
+#define DWT_EXCCNT_EXCCNT_Pos 0U /*!< DWT EXCCNT: EXCCNT Position */\r
+#define DWT_EXCCNT_EXCCNT_Msk (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/) /*!< DWT EXCCNT: EXCCNT Mask */\r
+\r
+/* DWT Sleep Count Register Definitions */\r
+#define DWT_SLEEPCNT_SLEEPCNT_Pos 0U /*!< DWT SLEEPCNT: SLEEPCNT Position */\r
+#define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/) /*!< DWT SLEEPCNT: SLEEPCNT Mask */\r
+\r
+/* DWT LSU Count Register Definitions */\r
+#define DWT_LSUCNT_LSUCNT_Pos 0U /*!< DWT LSUCNT: LSUCNT Position */\r
+#define DWT_LSUCNT_LSUCNT_Msk (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/) /*!< DWT LSUCNT: LSUCNT Mask */\r
+\r
+/* DWT Folded-instruction Count Register Definitions */\r
+#define DWT_FOLDCNT_FOLDCNT_Pos 0U /*!< DWT FOLDCNT: FOLDCNT Position */\r
+#define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/) /*!< DWT FOLDCNT: FOLDCNT Mask */\r
+\r
+/* DWT Comparator Function Register Definitions */\r
+#define DWT_FUNCTION_ID_Pos 27U /*!< DWT FUNCTION: ID Position */\r
+#define DWT_FUNCTION_ID_Msk (0x1FUL << DWT_FUNCTION_ID_Pos) /*!< DWT FUNCTION: ID Mask */\r
+\r
+#define DWT_FUNCTION_MATCHED_Pos 24U /*!< DWT FUNCTION: MATCHED Position */\r
+#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */\r
+\r
+#define DWT_FUNCTION_DATAVSIZE_Pos 10U /*!< DWT FUNCTION: DATAVSIZE Position */\r
+#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */\r
+\r
+#define DWT_FUNCTION_ACTION_Pos 4U /*!< DWT FUNCTION: ACTION Position */\r
+#define DWT_FUNCTION_ACTION_Msk (0x1UL << DWT_FUNCTION_ACTION_Pos) /*!< DWT FUNCTION: ACTION Mask */\r
+\r
+#define DWT_FUNCTION_MATCH_Pos 0U /*!< DWT FUNCTION: MATCH Position */\r
+#define DWT_FUNCTION_MATCH_Msk (0xFUL /*<< DWT_FUNCTION_MATCH_Pos*/) /*!< DWT FUNCTION: MATCH Mask */\r
+\r
+/*@}*/ /* end of group CMSIS_DWT */\r
+\r
+\r
+/**\r
+ \ingroup CMSIS_core_register\r
+ \defgroup CMSIS_TPI Trace Port Interface (TPI)\r
+ \brief Type definitions for the Trace Port Interface (TPI)\r
+ @{\r
+ */\r
+\r
+/**\r
+ \brief Structure type to access the Trace Port Interface Register (TPI).\r
+ */\r
+typedef struct\r
+{\r
+ __IM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Sizes Register */\r
+ __IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Sizes Register */\r
+ uint32_t RESERVED0[2U];\r
+ __IOM uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */\r
+ uint32_t RESERVED1[55U];\r
+ __IOM uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */\r
+ uint32_t RESERVED2[131U];\r
+ __IM uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */\r
+ __IOM uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */\r
+ __IOM uint32_t PSCR; /*!< Offset: 0x308 (R/W) Periodic Synchronization Control Register */\r
+ uint32_t RESERVED3[809U];\r
+ __OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) Software Lock Access Register */\r
+ __IM uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) Software Lock Status Register */\r
+ uint32_t RESERVED4[4U];\r
+ __IM uint32_t TYPE; /*!< Offset: 0xFC8 (R/ ) Device Identifier Register */\r
+ __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) Device Type Register */\r
+} TPI_Type;\r
+\r
+/* TPI Asynchronous Clock Prescaler Register Definitions */\r
+#define TPI_ACPR_SWOSCALER_Pos 0U /*!< TPI ACPR: SWOSCALER Position */\r
+#define TPI_ACPR_SWOSCALER_Msk (0xFFFFUL /*<< TPI_ACPR_SWOSCALER_Pos*/) /*!< TPI ACPR: SWOSCALER Mask */\r
+\r
+/* TPI Selected Pin Protocol Register Definitions */\r
+#define TPI_SPPR_TXMODE_Pos 0U /*!< TPI SPPR: TXMODE Position */\r
+#define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) /*!< TPI SPPR: TXMODE Mask */\r
+\r
+/* TPI Formatter and Flush Status Register Definitions */\r
+#define TPI_FFSR_FtNonStop_Pos 3U /*!< TPI FFSR: FtNonStop Position */\r
+#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */\r
+\r
+#define TPI_FFSR_TCPresent_Pos 2U /*!< TPI FFSR: TCPresent Position */\r
+#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */\r
+\r
+#define TPI_FFSR_FtStopped_Pos 1U /*!< TPI FFSR: FtStopped Position */\r
+#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */\r
+\r
+#define TPI_FFSR_FlInProg_Pos 0U /*!< TPI FFSR: FlInProg Position */\r
+#define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) /*!< TPI FFSR: FlInProg Mask */\r
+\r
+/* TPI Formatter and Flush Control Register Definitions */\r
+#define TPI_FFCR_TrigIn_Pos 8U /*!< TPI FFCR: TrigIn Position */\r
+#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */\r
+\r
+#define TPI_FFCR_FOnMan_Pos 6U /*!< TPI FFCR: FOnMan Position */\r
+#define TPI_FFCR_FOnMan_Msk (0x1UL << TPI_FFCR_FOnMan_Pos) /*!< TPI FFCR: FOnMan Mask */\r
+\r
+#define TPI_FFCR_EnFCont_Pos 1U /*!< TPI FFCR: EnFCont Position */\r
+#define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */\r
+\r
+/* TPI Periodic Synchronization Control Register Definitions */\r
+#define TPI_PSCR_PSCount_Pos 0U /*!< TPI PSCR: PSCount Position */\r
+#define TPI_PSCR_PSCount_Msk (0x1FUL /*<< TPI_PSCR_PSCount_Pos*/) /*!< TPI PSCR: TPSCount Mask */\r
+\r
+/* TPI Software Lock Status Register Definitions */\r
+#define TPI_LSR_nTT_Pos 1U /*!< TPI LSR: Not thirty-two bit. Position */\r
+#define TPI_LSR_nTT_Msk (0x1UL << TPI_LSR_nTT_Pos) /*!< TPI LSR: Not thirty-two bit. Mask */\r
+\r
+#define TPI_LSR_SLK_Pos 1U /*!< TPI LSR: Software Lock status Position */\r
+#define TPI_LSR_SLK_Msk (0x1UL << TPI_LSR_SLK_Pos) /*!< TPI LSR: Software Lock status Mask */\r
+\r
+#define TPI_LSR_SLI_Pos 0U /*!< TPI LSR: Software Lock implemented Position */\r
+#define TPI_LSR_SLI_Msk (0x1UL /*<< TPI_LSR_SLI_Pos*/) /*!< TPI LSR: Software Lock implemented Mask */\r
+\r
+/* TPI DEVID Register Definitions */\r
+#define TPI_DEVID_NRZVALID_Pos 11U /*!< TPI DEVID: NRZVALID Position */\r
+#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */\r
+\r
+#define TPI_DEVID_MANCVALID_Pos 10U /*!< TPI DEVID: MANCVALID Position */\r
+#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */\r
+\r
+#define TPI_DEVID_PTINVALID_Pos 9U /*!< TPI DEVID: PTINVALID Position */\r
+#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */\r
+\r
+#define TPI_DEVID_FIFOSZ_Pos 6U /*!< TPI DEVID: FIFO depth Position */\r
+#define TPI_DEVID_FIFOSZ_Msk (0x7UL << TPI_DEVID_FIFOSZ_Pos) /*!< TPI DEVID: FIFO depth Mask */\r
+\r
+/* TPI DEVTYPE Register Definitions */\r
+#define TPI_DEVTYPE_SubType_Pos 4U /*!< TPI DEVTYPE: SubType Position */\r
+#define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */\r
+\r
+#define TPI_DEVTYPE_MajorType_Pos 0U /*!< TPI DEVTYPE: MajorType Position */\r
+#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */\r
+\r
+/*@}*/ /* end of group CMSIS_TPI */\r
+\r
+\r
+#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)\r
+/**\r
+ \ingroup CMSIS_core_register\r
+ \defgroup CMSIS_MPU Memory Protection Unit (MPU)\r
+ \brief Type definitions for the Memory Protection Unit (MPU)\r
+ @{\r
+ */\r
+\r
+/**\r
+ \brief Structure type to access the Memory Protection Unit (MPU).\r
+ */\r
+typedef struct\r
+{\r
+ __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */\r
+ __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */\r
+ __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region Number Register */\r
+ __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */\r
+ __IOM uint32_t RLAR; /*!< Offset: 0x010 (R/W) MPU Region Limit Address Register */\r
+ __IOM uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Region Base Address Register Alias 1 */\r
+ __IOM uint32_t RLAR_A1; /*!< Offset: 0x018 (R/W) MPU Region Limit Address Register Alias 1 */\r
+ __IOM uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Region Base Address Register Alias 2 */\r
+ __IOM uint32_t RLAR_A2; /*!< Offset: 0x020 (R/W) MPU Region Limit Address Register Alias 2 */\r
+ __IOM uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Region Base Address Register Alias 3 */\r
+ __IOM uint32_t RLAR_A3; /*!< Offset: 0x028 (R/W) MPU Region Limit Address Register Alias 3 */\r
+ uint32_t RESERVED0[1];\r
+ union {\r
+ __IOM uint32_t MAIR[2];\r
+ struct {\r
+ __IOM uint32_t MAIR0; /*!< Offset: 0x030 (R/W) MPU Memory Attribute Indirection Register 0 */\r
+ __IOM uint32_t MAIR1; /*!< Offset: 0x034 (R/W) MPU Memory Attribute Indirection Register 1 */\r
+ };\r
+ };\r
+} MPU_Type;\r
+\r
+#define MPU_TYPE_RALIASES 4U\r
+\r
+/* MPU Type Register Definitions */\r
+#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */\r
+#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */\r
+\r
+#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */\r
+#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */\r
+\r
+#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */\r
+#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */\r
+\r
+/* MPU Control Register Definitions */\r
+#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */\r
+#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */\r
+\r
+#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */\r
+#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */\r
+\r
+#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */\r
+#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */\r
+\r
+/* MPU Region Number Register Definitions */\r
+#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */\r
+#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */\r
+\r
+/* MPU Region Base Address Register Definitions */\r
+#define MPU_RBAR_BASE_Pos 5U /*!< MPU RBAR: BASE Position */\r
+#define MPU_RBAR_BASE_Msk (0x7FFFFFFUL << MPU_RBAR_BASE_Pos) /*!< MPU RBAR: BASE Mask */\r
+\r
+#define MPU_RBAR_SH_Pos 3U /*!< MPU RBAR: SH Position */\r
+#define MPU_RBAR_SH_Msk (0x3UL << MPU_RBAR_SH_Pos) /*!< MPU RBAR: SH Mask */\r
+\r
+#define MPU_RBAR_AP_Pos 1U /*!< MPU RBAR: AP Position */\r
+#define MPU_RBAR_AP_Msk (0x3UL << MPU_RBAR_AP_Pos) /*!< MPU RBAR: AP Mask */\r
+\r
+#define MPU_RBAR_XN_Pos 0U /*!< MPU RBAR: XN Position */\r
+#define MPU_RBAR_XN_Msk (01UL /*<< MPU_RBAR_XN_Pos*/) /*!< MPU RBAR: XN Mask */\r
+\r
+/* MPU Region Limit Address Register Definitions */\r
+#define MPU_RLAR_LIMIT_Pos 5U /*!< MPU RLAR: LIMIT Position */\r
+#define MPU_RLAR_LIMIT_Msk (0x7FFFFFFUL << MPU_RLAR_LIMIT_Pos) /*!< MPU RLAR: LIMIT Mask */\r
+\r
+#define MPU_RLAR_AttrIndx_Pos 1U /*!< MPU RLAR: AttrIndx Position */\r
+#define MPU_RLAR_AttrIndx_Msk (0x7UL << MPU_RLAR_AttrIndx_Pos) /*!< MPU RLAR: AttrIndx Mask */\r
+\r
+#define MPU_RLAR_EN_Pos 0U /*!< MPU RLAR: Region enable bit Position */\r
+#define MPU_RLAR_EN_Msk (1UL /*<< MPU_RLAR_EN_Pos*/) /*!< MPU RLAR: Region enable bit Disable Mask */\r
+\r
+/* MPU Memory Attribute Indirection Register 0 Definitions */\r
+#define MPU_MAIR0_Attr3_Pos 24U /*!< MPU MAIR0: Attr3 Position */\r
+#define MPU_MAIR0_Attr3_Msk (0xFFUL << MPU_MAIR0_Attr3_Pos) /*!< MPU MAIR0: Attr3 Mask */\r
+\r
+#define MPU_MAIR0_Attr2_Pos 16U /*!< MPU MAIR0: Attr2 Position */\r
+#define MPU_MAIR0_Attr2_Msk (0xFFUL << MPU_MAIR0_Attr2_Pos) /*!< MPU MAIR0: Attr2 Mask */\r
+\r
+#define MPU_MAIR0_Attr1_Pos 8U /*!< MPU MAIR0: Attr1 Position */\r
+#define MPU_MAIR0_Attr1_Msk (0xFFUL << MPU_MAIR0_Attr1_Pos) /*!< MPU MAIR0: Attr1 Mask */\r
+\r
+#define MPU_MAIR0_Attr0_Pos 0U /*!< MPU MAIR0: Attr0 Position */\r
+#define MPU_MAIR0_Attr0_Msk (0xFFUL /*<< MPU_MAIR0_Attr0_Pos*/) /*!< MPU MAIR0: Attr0 Mask */\r
+\r
+/* MPU Memory Attribute Indirection Register 1 Definitions */\r
+#define MPU_MAIR1_Attr7_Pos 24U /*!< MPU MAIR1: Attr7 Position */\r
+#define MPU_MAIR1_Attr7_Msk (0xFFUL << MPU_MAIR1_Attr7_Pos) /*!< MPU MAIR1: Attr7 Mask */\r
+\r
+#define MPU_MAIR1_Attr6_Pos 16U /*!< MPU MAIR1: Attr6 Position */\r
+#define MPU_MAIR1_Attr6_Msk (0xFFUL << MPU_MAIR1_Attr6_Pos) /*!< MPU MAIR1: Attr6 Mask */\r
+\r
+#define MPU_MAIR1_Attr5_Pos 8U /*!< MPU MAIR1: Attr5 Position */\r
+#define MPU_MAIR1_Attr5_Msk (0xFFUL << MPU_MAIR1_Attr5_Pos) /*!< MPU MAIR1: Attr5 Mask */\r
+\r
+#define MPU_MAIR1_Attr4_Pos 0U /*!< MPU MAIR1: Attr4 Position */\r
+#define MPU_MAIR1_Attr4_Msk (0xFFUL /*<< MPU_MAIR1_Attr4_Pos*/) /*!< MPU MAIR1: Attr4 Mask */\r
+\r
+/*@} end of group CMSIS_MPU */\r
+#endif\r
+\r
+\r
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)\r
+/**\r
+ \ingroup CMSIS_core_register\r
+ \defgroup CMSIS_SAU Security Attribution Unit (SAU)\r
+ \brief Type definitions for the Security Attribution Unit (SAU)\r
+ @{\r
+ */\r
+\r
+/**\r
+ \brief Structure type to access the Security Attribution Unit (SAU).\r
+ */\r
+typedef struct\r
+{\r
+ __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SAU Control Register */\r
+ __IM uint32_t TYPE; /*!< Offset: 0x004 (R/ ) SAU Type Register */\r
+#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U)\r
+ __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) SAU Region Number Register */\r
+ __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) SAU Region Base Address Register */\r
+ __IOM uint32_t RLAR; /*!< Offset: 0x010 (R/W) SAU Region Limit Address Register */\r
+#else\r
+ uint32_t RESERVED0[3];\r
+#endif\r
+ __IOM uint32_t SFSR; /*!< Offset: 0x014 (R/W) Secure Fault Status Register */\r
+ __IOM uint32_t SFAR; /*!< Offset: 0x018 (R/W) Secure Fault Address Register */\r
+} SAU_Type;\r
+\r
+/* SAU Control Register Definitions */\r
+#define SAU_CTRL_ALLNS_Pos 1U /*!< SAU CTRL: ALLNS Position */\r
+#define SAU_CTRL_ALLNS_Msk (1UL << SAU_CTRL_ALLNS_Pos) /*!< SAU CTRL: ALLNS Mask */\r
+\r
+#define SAU_CTRL_ENABLE_Pos 0U /*!< SAU CTRL: ENABLE Position */\r
+#define SAU_CTRL_ENABLE_Msk (1UL /*<< SAU_CTRL_ENABLE_Pos*/) /*!< SAU CTRL: ENABLE Mask */\r
+\r
+/* SAU Type Register Definitions */\r
+#define SAU_TYPE_SREGION_Pos 0U /*!< SAU TYPE: SREGION Position */\r
+#define SAU_TYPE_SREGION_Msk (0xFFUL /*<< SAU_TYPE_SREGION_Pos*/) /*!< SAU TYPE: SREGION Mask */\r
+\r
+#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U)\r
+/* SAU Region Number Register Definitions */\r
+#define SAU_RNR_REGION_Pos 0U /*!< SAU RNR: REGION Position */\r
+#define SAU_RNR_REGION_Msk (0xFFUL /*<< SAU_RNR_REGION_Pos*/) /*!< SAU RNR: REGION Mask */\r
+\r
+/* SAU Region Base Address Register Definitions */\r
+#define SAU_RBAR_BADDR_Pos 5U /*!< SAU RBAR: BADDR Position */\r
+#define SAU_RBAR_BADDR_Msk (0x7FFFFFFUL << SAU_RBAR_BADDR_Pos) /*!< SAU RBAR: BADDR Mask */\r
+\r
+/* SAU Region Limit Address Register Definitions */\r
+#define SAU_RLAR_LADDR_Pos 5U /*!< SAU RLAR: LADDR Position */\r
+#define SAU_RLAR_LADDR_Msk (0x7FFFFFFUL << SAU_RLAR_LADDR_Pos) /*!< SAU RLAR: LADDR Mask */\r
+\r
+#define SAU_RLAR_NSC_Pos 1U /*!< SAU RLAR: NSC Position */\r
+#define SAU_RLAR_NSC_Msk (1UL << SAU_RLAR_NSC_Pos) /*!< SAU RLAR: NSC Mask */\r
+\r
+#define SAU_RLAR_ENABLE_Pos 0U /*!< SAU RLAR: ENABLE Position */\r
+#define SAU_RLAR_ENABLE_Msk (1UL /*<< SAU_RLAR_ENABLE_Pos*/) /*!< SAU RLAR: ENABLE Mask */\r
+\r
+#endif /* defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) */\r
+\r
+/* Secure Fault Status Register Definitions */\r
+#define SAU_SFSR_LSERR_Pos 7U /*!< SAU SFSR: LSERR Position */\r
+#define SAU_SFSR_LSERR_Msk (1UL << SAU_SFSR_LSERR_Pos) /*!< SAU SFSR: LSERR Mask */\r
+\r
+#define SAU_SFSR_SFARVALID_Pos 6U /*!< SAU SFSR: SFARVALID Position */\r
+#define SAU_SFSR_SFARVALID_Msk (1UL << SAU_SFSR_SFARVALID_Pos) /*!< SAU SFSR: SFARVALID Mask */\r
+\r
+#define SAU_SFSR_LSPERR_Pos 5U /*!< SAU SFSR: LSPERR Position */\r
+#define SAU_SFSR_LSPERR_Msk (1UL << SAU_SFSR_LSPERR_Pos) /*!< SAU SFSR: LSPERR Mask */\r
+\r
+#define SAU_SFSR_INVTRAN_Pos 4U /*!< SAU SFSR: INVTRAN Position */\r
+#define SAU_SFSR_INVTRAN_Msk (1UL << SAU_SFSR_INVTRAN_Pos) /*!< SAU SFSR: INVTRAN Mask */\r
+\r
+#define SAU_SFSR_AUVIOL_Pos 3U /*!< SAU SFSR: AUVIOL Position */\r
+#define SAU_SFSR_AUVIOL_Msk (1UL << SAU_SFSR_AUVIOL_Pos) /*!< SAU SFSR: AUVIOL Mask */\r
+\r
+#define SAU_SFSR_INVER_Pos 2U /*!< SAU SFSR: INVER Position */\r
+#define SAU_SFSR_INVER_Msk (1UL << SAU_SFSR_INVER_Pos) /*!< SAU SFSR: INVER Mask */\r
+\r
+#define SAU_SFSR_INVIS_Pos 1U /*!< SAU SFSR: INVIS Position */\r
+#define SAU_SFSR_INVIS_Msk (1UL << SAU_SFSR_INVIS_Pos) /*!< SAU SFSR: INVIS Mask */\r
+\r
+#define SAU_SFSR_INVEP_Pos 0U /*!< SAU SFSR: INVEP Position */\r
+#define SAU_SFSR_INVEP_Msk (1UL /*<< SAU_SFSR_INVEP_Pos*/) /*!< SAU SFSR: INVEP Mask */\r
+\r
+/*@} end of group CMSIS_SAU */\r
+#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */\r
+\r
+\r
+/**\r
+ \ingroup CMSIS_core_register\r
+ \defgroup CMSIS_FPU Floating Point Unit (FPU)\r
+ \brief Type definitions for the Floating Point Unit (FPU)\r
+ @{\r
+ */\r
+\r
+/**\r
+ \brief Structure type to access the Floating Point Unit (FPU).\r
+ */\r
+typedef struct\r
+{\r
+ uint32_t RESERVED0[1U];\r
+ __IOM uint32_t FPCCR; /*!< Offset: 0x004 (R/W) Floating-Point Context Control Register */\r
+ __IOM uint32_t FPCAR; /*!< Offset: 0x008 (R/W) Floating-Point Context Address Register */\r
+ __IOM uint32_t FPDSCR; /*!< Offset: 0x00C (R/W) Floating-Point Default Status Control Register */\r
+ __IM uint32_t MVFR0; /*!< Offset: 0x010 (R/ ) Media and FP Feature Register 0 */\r
+ __IM uint32_t MVFR1; /*!< Offset: 0x014 (R/ ) Media and FP Feature Register 1 */\r
+} FPU_Type;\r
+\r
+/* Floating-Point Context Control Register Definitions */\r
+#define FPU_FPCCR_ASPEN_Pos 31U /*!< FPCCR: ASPEN bit Position */\r
+#define FPU_FPCCR_ASPEN_Msk (1UL << FPU_FPCCR_ASPEN_Pos) /*!< FPCCR: ASPEN bit Mask */\r
+\r
+#define FPU_FPCCR_LSPEN_Pos 30U /*!< FPCCR: LSPEN Position */\r
+#define FPU_FPCCR_LSPEN_Msk (1UL << FPU_FPCCR_LSPEN_Pos) /*!< FPCCR: LSPEN bit Mask */\r
+\r
+#define FPU_FPCCR_LSPENS_Pos 29U /*!< FPCCR: LSPENS Position */\r
+#define FPU_FPCCR_LSPENS_Msk (1UL << FPU_FPCCR_LSPENS_Pos) /*!< FPCCR: LSPENS bit Mask */\r
+\r
+#define FPU_FPCCR_CLRONRET_Pos 28U /*!< FPCCR: CLRONRET Position */\r
+#define FPU_FPCCR_CLRONRET_Msk (1UL << FPU_FPCCR_CLRONRET_Pos) /*!< FPCCR: CLRONRET bit Mask */\r
+\r
+#define FPU_FPCCR_CLRONRETS_Pos 27U /*!< FPCCR: CLRONRETS Position */\r
+#define FPU_FPCCR_CLRONRETS_Msk (1UL << FPU_FPCCR_CLRONRETS_Pos) /*!< FPCCR: CLRONRETS bit Mask */\r
+\r
+#define FPU_FPCCR_TS_Pos 26U /*!< FPCCR: TS Position */\r
+#define FPU_FPCCR_TS_Msk (1UL << FPU_FPCCR_TS_Pos) /*!< FPCCR: TS bit Mask */\r
+\r
+#define FPU_FPCCR_UFRDY_Pos 10U /*!< FPCCR: UFRDY Position */\r
+#define FPU_FPCCR_UFRDY_Msk (1UL << FPU_FPCCR_UFRDY_Pos) /*!< FPCCR: UFRDY bit Mask */\r
+\r
+#define FPU_FPCCR_SPLIMVIOL_Pos 9U /*!< FPCCR: SPLIMVIOL Position */\r
+#define FPU_FPCCR_SPLIMVIOL_Msk (1UL << FPU_FPCCR_SPLIMVIOL_Pos) /*!< FPCCR: SPLIMVIOL bit Mask */\r
+\r
+#define FPU_FPCCR_MONRDY_Pos 8U /*!< FPCCR: MONRDY Position */\r
+#define FPU_FPCCR_MONRDY_Msk (1UL << FPU_FPCCR_MONRDY_Pos) /*!< FPCCR: MONRDY bit Mask */\r
+\r
+#define FPU_FPCCR_SFRDY_Pos 7U /*!< FPCCR: SFRDY Position */\r
+#define FPU_FPCCR_SFRDY_Msk (1UL << FPU_FPCCR_SFRDY_Pos) /*!< FPCCR: SFRDY bit Mask */\r
+\r
+#define FPU_FPCCR_BFRDY_Pos 6U /*!< FPCCR: BFRDY Position */\r
+#define FPU_FPCCR_BFRDY_Msk (1UL << FPU_FPCCR_BFRDY_Pos) /*!< FPCCR: BFRDY bit Mask */\r
+\r
+#define FPU_FPCCR_MMRDY_Pos 5U /*!< FPCCR: MMRDY Position */\r
+#define FPU_FPCCR_MMRDY_Msk (1UL << FPU_FPCCR_MMRDY_Pos) /*!< FPCCR: MMRDY bit Mask */\r
+\r
+#define FPU_FPCCR_HFRDY_Pos 4U /*!< FPCCR: HFRDY Position */\r
+#define FPU_FPCCR_HFRDY_Msk (1UL << FPU_FPCCR_HFRDY_Pos) /*!< FPCCR: HFRDY bit Mask */\r
+\r
+#define FPU_FPCCR_THREAD_Pos 3U /*!< FPCCR: processor mode bit Position */\r
+#define FPU_FPCCR_THREAD_Msk (1UL << FPU_FPCCR_THREAD_Pos) /*!< FPCCR: processor mode active bit Mask */\r
+\r
+#define FPU_FPCCR_S_Pos 2U /*!< FPCCR: Security status of the FP context bit Position */\r
+#define FPU_FPCCR_S_Msk (1UL << FPU_FPCCR_S_Pos) /*!< FPCCR: Security status of the FP context bit Mask */\r
+\r
+#define FPU_FPCCR_USER_Pos 1U /*!< FPCCR: privilege level bit Position */\r
+#define FPU_FPCCR_USER_Msk (1UL << FPU_FPCCR_USER_Pos) /*!< FPCCR: privilege level bit Mask */\r
+\r
+#define FPU_FPCCR_LSPACT_Pos 0U /*!< FPCCR: Lazy state preservation active bit Position */\r
+#define FPU_FPCCR_LSPACT_Msk (1UL /*<< FPU_FPCCR_LSPACT_Pos*/) /*!< FPCCR: Lazy state preservation active bit Mask */\r
+\r
+/* Floating-Point Context Address Register Definitions */\r
+#define FPU_FPCAR_ADDRESS_Pos 3U /*!< FPCAR: ADDRESS bit Position */\r
+#define FPU_FPCAR_ADDRESS_Msk (0x1FFFFFFFUL << FPU_FPCAR_ADDRESS_Pos) /*!< FPCAR: ADDRESS bit Mask */\r
+\r
+/* Floating-Point Default Status Control Register Definitions */\r
+#define FPU_FPDSCR_AHP_Pos 26U /*!< FPDSCR: AHP bit Position */\r
+#define FPU_FPDSCR_AHP_Msk (1UL << FPU_FPDSCR_AHP_Pos) /*!< FPDSCR: AHP bit Mask */\r
+\r
+#define FPU_FPDSCR_DN_Pos 25U /*!< FPDSCR: DN bit Position */\r
+#define FPU_FPDSCR_DN_Msk (1UL << FPU_FPDSCR_DN_Pos) /*!< FPDSCR: DN bit Mask */\r
+\r
+#define FPU_FPDSCR_FZ_Pos 24U /*!< FPDSCR: FZ bit Position */\r
+#define FPU_FPDSCR_FZ_Msk (1UL << FPU_FPDSCR_FZ_Pos) /*!< FPDSCR: FZ bit Mask */\r
+\r
+#define FPU_FPDSCR_RMode_Pos 22U /*!< FPDSCR: RMode bit Position */\r
+#define FPU_FPDSCR_RMode_Msk (3UL << FPU_FPDSCR_RMode_Pos) /*!< FPDSCR: RMode bit Mask */\r
+\r
+/* Media and FP Feature Register 0 Definitions */\r
+#define FPU_MVFR0_FP_rounding_modes_Pos 28U /*!< MVFR0: FP rounding modes bits Position */\r
+#define FPU_MVFR0_FP_rounding_modes_Msk (0xFUL << FPU_MVFR0_FP_rounding_modes_Pos) /*!< MVFR0: FP rounding modes bits Mask */\r
+\r
+#define FPU_MVFR0_Short_vectors_Pos 24U /*!< MVFR0: Short vectors bits Position */\r
+#define FPU_MVFR0_Short_vectors_Msk (0xFUL << FPU_MVFR0_Short_vectors_Pos) /*!< MVFR0: Short vectors bits Mask */\r
+\r
+#define FPU_MVFR0_Square_root_Pos 20U /*!< MVFR0: Square root bits Position */\r
+#define FPU_MVFR0_Square_root_Msk (0xFUL << FPU_MVFR0_Square_root_Pos) /*!< MVFR0: Square root bits Mask */\r
+\r
+#define FPU_MVFR0_Divide_Pos 16U /*!< MVFR0: Divide bits Position */\r
+#define FPU_MVFR0_Divide_Msk (0xFUL << FPU_MVFR0_Divide_Pos) /*!< MVFR0: Divide bits Mask */\r
+\r
+#define FPU_MVFR0_FP_excep_trapping_Pos 12U /*!< MVFR0: FP exception trapping bits Position */\r
+#define FPU_MVFR0_FP_excep_trapping_Msk (0xFUL << FPU_MVFR0_FP_excep_trapping_Pos) /*!< MVFR0: FP exception trapping bits Mask */\r
+\r
+#define FPU_MVFR0_Double_precision_Pos 8U /*!< MVFR0: Double-precision bits Position */\r
+#define FPU_MVFR0_Double_precision_Msk (0xFUL << FPU_MVFR0_Double_precision_Pos) /*!< MVFR0: Double-precision bits Mask */\r
+\r
+#define FPU_MVFR0_Single_precision_Pos 4U /*!< MVFR0: Single-precision bits Position */\r
+#define FPU_MVFR0_Single_precision_Msk (0xFUL << FPU_MVFR0_Single_precision_Pos) /*!< MVFR0: Single-precision bits Mask */\r
+\r
+#define FPU_MVFR0_A_SIMD_registers_Pos 0U /*!< MVFR0: A_SIMD registers bits Position */\r
+#define FPU_MVFR0_A_SIMD_registers_Msk (0xFUL /*<< FPU_MVFR0_A_SIMD_registers_Pos*/) /*!< MVFR0: A_SIMD registers bits Mask */\r
+\r
+/* Media and FP Feature Register 1 Definitions */\r
+#define FPU_MVFR1_FP_fused_MAC_Pos 28U /*!< MVFR1: FP fused MAC bits Position */\r
+#define FPU_MVFR1_FP_fused_MAC_Msk (0xFUL << FPU_MVFR1_FP_fused_MAC_Pos) /*!< MVFR1: FP fused MAC bits Mask */\r
+\r
+#define FPU_MVFR1_FP_HPFP_Pos 24U /*!< MVFR1: FP HPFP bits Position */\r
+#define FPU_MVFR1_FP_HPFP_Msk (0xFUL << FPU_MVFR1_FP_HPFP_Pos) /*!< MVFR1: FP HPFP bits Mask */\r
+\r
+#define FPU_MVFR1_D_NaN_mode_Pos 4U /*!< MVFR1: D_NaN mode bits Position */\r
+#define FPU_MVFR1_D_NaN_mode_Msk (0xFUL << FPU_MVFR1_D_NaN_mode_Pos) /*!< MVFR1: D_NaN mode bits Mask */\r
+\r
+#define FPU_MVFR1_FtZ_mode_Pos 0U /*!< MVFR1: FtZ mode bits Position */\r
+#define FPU_MVFR1_FtZ_mode_Msk (0xFUL /*<< FPU_MVFR1_FtZ_mode_Pos*/) /*!< MVFR1: FtZ mode bits Mask */\r
+\r
+/*@} end of group CMSIS_FPU */\r
+\r
+\r
+/**\r
+ \ingroup CMSIS_core_register\r
+ \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug)\r
+ \brief Type definitions for the Core Debug Registers\r
+ @{\r
+ */\r
+\r
+/**\r
+ \brief Structure type to access the Core Debug Register (CoreDebug).\r
+ */\r
+typedef struct\r
+{\r
+ __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */\r
+ __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */\r
+ __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */\r
+ __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */\r
+ uint32_t RESERVED4[1U];\r
+ __IOM uint32_t DAUTHCTRL; /*!< Offset: 0x014 (R/W) Debug Authentication Control Register */\r
+ __IOM uint32_t DSCSR; /*!< Offset: 0x018 (R/W) Debug Security Control and Status Register */\r
+} CoreDebug_Type;\r
+\r
+/* Debug Halting Control and Status Register Definitions */\r
+#define CoreDebug_DHCSR_DBGKEY_Pos 16U /*!< CoreDebug DHCSR: DBGKEY Position */\r
+#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */\r
+\r
+#define CoreDebug_DHCSR_S_RESTART_ST_Pos 26U /*!< CoreDebug DHCSR: S_RESTART_ST Position */\r
+#define CoreDebug_DHCSR_S_RESTART_ST_Msk (1UL << CoreDebug_DHCSR_S_RESTART_ST_Pos) /*!< CoreDebug DHCSR: S_RESTART_ST Mask */\r
+\r
+#define CoreDebug_DHCSR_S_RESET_ST_Pos 25U /*!< CoreDebug DHCSR: S_RESET_ST Position */\r
+#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */\r
+\r
+#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U /*!< CoreDebug DHCSR: S_RETIRE_ST Position */\r
+#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */\r
+\r
+#define CoreDebug_DHCSR_S_LOCKUP_Pos 19U /*!< CoreDebug DHCSR: S_LOCKUP Position */\r
+#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */\r
+\r
+#define CoreDebug_DHCSR_S_SLEEP_Pos 18U /*!< CoreDebug DHCSR: S_SLEEP Position */\r
+#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */\r
+\r
+#define CoreDebug_DHCSR_S_HALT_Pos 17U /*!< CoreDebug DHCSR: S_HALT Position */\r
+#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */\r
+\r
+#define CoreDebug_DHCSR_S_REGRDY_Pos 16U /*!< CoreDebug DHCSR: S_REGRDY Position */\r
+#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */\r
+\r
+#define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5U /*!< CoreDebug DHCSR: C_SNAPSTALL Position */\r
+#define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */\r
+\r
+#define CoreDebug_DHCSR_C_MASKINTS_Pos 3U /*!< CoreDebug DHCSR: C_MASKINTS Position */\r
+#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */\r
+\r
+#define CoreDebug_DHCSR_C_STEP_Pos 2U /*!< CoreDebug DHCSR: C_STEP Position */\r
+#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */\r
+\r
+#define CoreDebug_DHCSR_C_HALT_Pos 1U /*!< CoreDebug DHCSR: C_HALT Position */\r
+#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */\r
+\r
+#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U /*!< CoreDebug DHCSR: C_DEBUGEN Position */\r
+#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */\r
+\r
+/* Debug Core Register Selector Register Definitions */\r
+#define CoreDebug_DCRSR_REGWnR_Pos 16U /*!< CoreDebug DCRSR: REGWnR Position */\r
+#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */\r
+\r
+#define CoreDebug_DCRSR_REGSEL_Pos 0U /*!< CoreDebug DCRSR: REGSEL Position */\r
+#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/) /*!< CoreDebug DCRSR: REGSEL Mask */\r
+\r
+/* Debug Exception and Monitor Control Register Definitions */\r
+#define CoreDebug_DEMCR_TRCENA_Pos 24U /*!< CoreDebug DEMCR: TRCENA Position */\r
+#define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< CoreDebug DEMCR: TRCENA Mask */\r
+\r
+#define CoreDebug_DEMCR_MON_REQ_Pos 19U /*!< CoreDebug DEMCR: MON_REQ Position */\r
+#define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< CoreDebug DEMCR: MON_REQ Mask */\r
+\r
+#define CoreDebug_DEMCR_MON_STEP_Pos 18U /*!< CoreDebug DEMCR: MON_STEP Position */\r
+#define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< CoreDebug DEMCR: MON_STEP Mask */\r
+\r
+#define CoreDebug_DEMCR_MON_PEND_Pos 17U /*!< CoreDebug DEMCR: MON_PEND Position */\r
+#define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< CoreDebug DEMCR: MON_PEND Mask */\r
+\r
+#define CoreDebug_DEMCR_MON_EN_Pos 16U /*!< CoreDebug DEMCR: MON_EN Position */\r
+#define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< CoreDebug DEMCR: MON_EN Mask */\r
+\r
+#define CoreDebug_DEMCR_VC_HARDERR_Pos 10U /*!< CoreDebug DEMCR: VC_HARDERR Position */\r
+#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */\r
+\r
+#define CoreDebug_DEMCR_VC_INTERR_Pos 9U /*!< CoreDebug DEMCR: VC_INTERR Position */\r
+#define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< CoreDebug DEMCR: VC_INTERR Mask */\r
+\r
+#define CoreDebug_DEMCR_VC_BUSERR_Pos 8U /*!< CoreDebug DEMCR: VC_BUSERR Position */\r
+#define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< CoreDebug DEMCR: VC_BUSERR Mask */\r
+\r
+#define CoreDebug_DEMCR_VC_STATERR_Pos 7U /*!< CoreDebug DEMCR: VC_STATERR Position */\r
+#define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< CoreDebug DEMCR: VC_STATERR Mask */\r
+\r
+#define CoreDebug_DEMCR_VC_CHKERR_Pos 6U /*!< CoreDebug DEMCR: VC_CHKERR Position */\r
+#define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< CoreDebug DEMCR: VC_CHKERR Mask */\r
+\r
+#define CoreDebug_DEMCR_VC_NOCPERR_Pos 5U /*!< CoreDebug DEMCR: VC_NOCPERR Position */\r
+#define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< CoreDebug DEMCR: VC_NOCPERR Mask */\r
+\r
+#define CoreDebug_DEMCR_VC_MMERR_Pos 4U /*!< CoreDebug DEMCR: VC_MMERR Position */\r
+#define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< CoreDebug DEMCR: VC_MMERR Mask */\r
+\r
+#define CoreDebug_DEMCR_VC_CORERESET_Pos 0U /*!< CoreDebug DEMCR: VC_CORERESET Position */\r
+#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/) /*!< CoreDebug DEMCR: VC_CORERESET Mask */\r
+\r
+/* Debug Authentication Control Register Definitions */\r
+#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos 3U /*!< CoreDebug DAUTHCTRL: INTSPNIDEN, Position */\r
+#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos) /*!< CoreDebug DAUTHCTRL: INTSPNIDEN, Mask */\r
+\r
+#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos 2U /*!< CoreDebug DAUTHCTRL: SPNIDENSEL Position */\r
+#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Msk (1UL << CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos) /*!< CoreDebug DAUTHCTRL: SPNIDENSEL Mask */\r
+\r
+#define CoreDebug_DAUTHCTRL_INTSPIDEN_Pos 1U /*!< CoreDebug DAUTHCTRL: INTSPIDEN Position */\r
+#define CoreDebug_DAUTHCTRL_INTSPIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPIDEN_Pos) /*!< CoreDebug DAUTHCTRL: INTSPIDEN Mask */\r
+\r
+#define CoreDebug_DAUTHCTRL_SPIDENSEL_Pos 0U /*!< CoreDebug DAUTHCTRL: SPIDENSEL Position */\r
+#define CoreDebug_DAUTHCTRL_SPIDENSEL_Msk (1UL /*<< CoreDebug_DAUTHCTRL_SPIDENSEL_Pos*/) /*!< CoreDebug DAUTHCTRL: SPIDENSEL Mask */\r
+\r
+/* Debug Security Control and Status Register Definitions */\r
+#define CoreDebug_DSCSR_CDS_Pos 16U /*!< CoreDebug DSCSR: CDS Position */\r
+#define CoreDebug_DSCSR_CDS_Msk (1UL << CoreDebug_DSCSR_CDS_Pos) /*!< CoreDebug DSCSR: CDS Mask */\r
+\r
+#define CoreDebug_DSCSR_SBRSEL_Pos 1U /*!< CoreDebug DSCSR: SBRSEL Position */\r
+#define CoreDebug_DSCSR_SBRSEL_Msk (1UL << CoreDebug_DSCSR_SBRSEL_Pos) /*!< CoreDebug DSCSR: SBRSEL Mask */\r
+\r
+#define CoreDebug_DSCSR_SBRSELEN_Pos 0U /*!< CoreDebug DSCSR: SBRSELEN Position */\r
+#define CoreDebug_DSCSR_SBRSELEN_Msk (1UL /*<< CoreDebug_DSCSR_SBRSELEN_Pos*/) /*!< CoreDebug DSCSR: SBRSELEN Mask */\r
+\r
+/*@} end of group CMSIS_CoreDebug */\r
+\r
+\r
+/**\r
+ \ingroup CMSIS_core_register\r
+ \defgroup CMSIS_core_bitfield Core register bit field macros\r
+ \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk).\r
+ @{\r
+ */\r
+\r
+/**\r
+ \brief Mask and shift a bit field value for use in a register bit range.\r
+ \param[in] field Name of the register bit field.\r
+ \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type.\r
+ \return Masked and shifted value.\r
+*/\r
+#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk)\r
+\r
+/**\r
+ \brief Mask and shift a register value to extract a bit filed value.\r
+ \param[in] field Name of the register bit field.\r
+ \param[in] value Value of register. This parameter is interpreted as an uint32_t type.\r
+ \return Masked and shifted bit field value.\r
+*/\r
+#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos)\r
+\r
+/*@} end of group CMSIS_core_bitfield */\r
+\r
+\r
+/**\r
+ \ingroup CMSIS_core_register\r
+ \defgroup CMSIS_core_base Core Definitions\r
+ \brief Definitions for base addresses, unions, and structures.\r
+ @{\r
+ */\r
+\r
+/* Memory mapping of Core Hardware */\r
+ #define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */\r
+ #define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */\r
+ #define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */\r
+ #define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */\r
+ #define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */\r
+ #define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */\r
+ #define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */\r
+ #define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */\r
+\r
+ #define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */\r
+ #define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */\r
+ #define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */\r
+ #define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */\r
+ #define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */\r
+ #define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */\r
+ #define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */\r
+ #define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE ) /*!< Core Debug configuration struct */\r
+\r
+ #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)\r
+ #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */\r
+ #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */\r
+ #endif\r
+\r
+ #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)\r
+ #define SAU_BASE (SCS_BASE + 0x0DD0UL) /*!< Security Attribution Unit */\r
+ #define SAU ((SAU_Type *) SAU_BASE ) /*!< Security Attribution Unit */\r
+ #endif\r
+\r
+ #define FPU_BASE (SCS_BASE + 0x0F30UL) /*!< Floating Point Unit */\r
+ #define FPU ((FPU_Type *) FPU_BASE ) /*!< Floating Point Unit */\r
+\r
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)\r
+ #define SCS_BASE_NS (0xE002E000UL) /*!< System Control Space Base Address (non-secure address space) */\r
+ #define CoreDebug_BASE_NS (0xE002EDF0UL) /*!< Core Debug Base Address (non-secure address space) */\r
+ #define SysTick_BASE_NS (SCS_BASE_NS + 0x0010UL) /*!< SysTick Base Address (non-secure address space) */\r
+ #define NVIC_BASE_NS (SCS_BASE_NS + 0x0100UL) /*!< NVIC Base Address (non-secure address space) */\r
+ #define SCB_BASE_NS (SCS_BASE_NS + 0x0D00UL) /*!< System Control Block Base Address (non-secure address space) */\r
+\r
+ #define SCnSCB_NS ((SCnSCB_Type *) SCS_BASE_NS ) /*!< System control Register not in SCB(non-secure address space) */\r
+ #define SCB_NS ((SCB_Type *) SCB_BASE_NS ) /*!< SCB configuration struct (non-secure address space) */\r
+ #define SysTick_NS ((SysTick_Type *) SysTick_BASE_NS ) /*!< SysTick configuration struct (non-secure address space) */\r
+ #define NVIC_NS ((NVIC_Type *) NVIC_BASE_NS ) /*!< NVIC configuration struct (non-secure address space) */\r
+ #define CoreDebug_NS ((CoreDebug_Type *) CoreDebug_BASE_NS) /*!< Core Debug configuration struct (non-secure address space) */\r
+\r
+ #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)\r
+ #define MPU_BASE_NS (SCS_BASE_NS + 0x0D90UL) /*!< Memory Protection Unit (non-secure address space) */\r
+ #define MPU_NS ((MPU_Type *) MPU_BASE_NS ) /*!< Memory Protection Unit (non-secure address space) */\r
+ #endif\r
+\r
+ #define FPU_BASE_NS (SCS_BASE_NS + 0x0F30UL) /*!< Floating Point Unit (non-secure address space) */\r
+ #define FPU_NS ((FPU_Type *) FPU_BASE_NS ) /*!< Floating Point Unit (non-secure address space) */\r
+\r
+#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */\r
+/*@} */\r
+\r
+\r
+\r
+/*******************************************************************************\r
+ * Hardware Abstraction Layer\r
+ Core Function Interface contains:\r
+ - Core NVIC Functions\r
+ - Core SysTick Functions\r
+ - Core Debug Functions\r
+ - Core Register Access Functions\r
+ ******************************************************************************/\r
+/**\r
+ \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference\r
+*/\r
+\r
+\r
+\r
+/* ########################## NVIC functions #################################### */\r
+/**\r
+ \ingroup CMSIS_Core_FunctionInterface\r
+ \defgroup CMSIS_Core_NVICFunctions NVIC Functions\r
+ \brief Functions that manage interrupts and exceptions via the NVIC.\r
+ @{\r
+ */\r
+\r
+#ifdef CMSIS_NVIC_VIRTUAL\r
+ #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE\r
+ #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h"\r
+ #endif\r
+ #include CMSIS_NVIC_VIRTUAL_HEADER_FILE\r
+#else\r
+ #define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping\r
+ #define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping\r
+ #define NVIC_EnableIRQ __NVIC_EnableIRQ\r
+ #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ\r
+ #define NVIC_DisableIRQ __NVIC_DisableIRQ\r
+ #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ\r
+ #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ\r
+ #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ\r
+ #define NVIC_GetActive __NVIC_GetActive\r
+ #define NVIC_SetPriority __NVIC_SetPriority\r
+ #define NVIC_GetPriority __NVIC_GetPriority\r
+ #define NVIC_SystemReset __NVIC_SystemReset\r
+#endif /* CMSIS_NVIC_VIRTUAL */\r
+\r
+#ifdef CMSIS_VECTAB_VIRTUAL\r
+ #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE\r
+ #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h"\r
+ #endif\r
+ #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE\r
+#else\r
+ #define NVIC_SetVector __NVIC_SetVector\r
+ #define NVIC_GetVector __NVIC_GetVector\r
+#endif /* (CMSIS_VECTAB_VIRTUAL) */\r
+\r
+#define NVIC_USER_IRQ_OFFSET 16\r
+\r
+\r
+/* Special LR values for Secure/Non-Secure call handling and exception handling */\r
+\r
+/* Function Return Payload (from ARMv8-M Architecture Reference Manual) LR value on entry from Secure BLXNS */\r
+#define FNC_RETURN (0xFEFFFFFFUL) /* bit [0] ignored when processing a branch */\r
+\r
+/* The following EXC_RETURN mask values are used to evaluate the LR on exception entry */\r
+#define EXC_RETURN_PREFIX (0xFF000000UL) /* bits [31:24] set to indicate an EXC_RETURN value */\r
+#define EXC_RETURN_S (0x00000040UL) /* bit [6] stack used to push registers: 0=Non-secure 1=Secure */\r
+#define EXC_RETURN_DCRS (0x00000020UL) /* bit [5] stacking rules for called registers: 0=skipped 1=saved */\r
+#define EXC_RETURN_FTYPE (0x00000010UL) /* bit [4] allocate stack for floating-point context: 0=done 1=skipped */\r
+#define EXC_RETURN_MODE (0x00000008UL) /* bit [3] processor mode for return: 0=Handler mode 1=Thread mode */\r
+#define EXC_RETURN_SPSEL (0x00000002UL) /* bit [1] stack pointer used to restore context: 0=MSP 1=PSP */\r
+#define EXC_RETURN_ES (0x00000001UL) /* bit [0] security state exception was taken to: 0=Non-secure 1=Secure */\r
+\r
+/* Integrity Signature (from ARMv8-M Architecture Reference Manual) for exception context stacking */\r
+#if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) /* Value for processors with floating-point extension: */\r
+#define EXC_INTEGRITY_SIGNATURE (0xFEFA125AUL) /* bit [0] SFTC must match LR bit[4] EXC_RETURN_FTYPE */\r
+#else\r
+#define EXC_INTEGRITY_SIGNATURE (0xFEFA125BUL) /* Value for processors without floating-point extension */\r
+#endif\r
+\r
+\r
+/**\r
+ \brief Set Priority Grouping\r
+ \details Sets the priority grouping field using the required unlock sequence.\r
+ The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field.\r
+ Only values from 0..7 are used.\r
+ In case of a conflict between priority grouping and available\r
+ priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.\r
+ \param [in] PriorityGroup Priority grouping field.\r
+ */\r
+__STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup)\r
+{\r
+ uint32_t reg_value;\r
+ uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */\r
+\r
+ reg_value = SCB->AIRCR; /* read old register configuration */\r
+ reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */\r
+ reg_value = (reg_value |\r
+ ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |\r
+ (PriorityGroupTmp << 8U) ); /* Insert write key and priorty group */\r
+ SCB->AIRCR = reg_value;\r
+}\r
+\r
+\r
+/**\r
+ \brief Get Priority Grouping\r
+ \details Reads the priority grouping field from the NVIC Interrupt Controller.\r
+ \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field).\r
+ */\r
+__STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void)\r
+{\r
+ return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos));\r
+}\r
+\r
+\r
+/**\r
+ \brief Enable Interrupt\r
+ \details Enables a device specific interrupt in the NVIC interrupt controller.\r
+ \param [in] IRQn Device specific interrupt number.\r
+ \note IRQn must not be negative.\r
+ */\r
+__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn)\r
+{\r
+ if ((int32_t)(IRQn) >= 0)\r
+ {\r
+ NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));\r
+ }\r
+}\r
+\r
+\r
+/**\r
+ \brief Get Interrupt Enable status\r
+ \details Returns a device specific interrupt enable status from the NVIC interrupt controller.\r
+ \param [in] IRQn Device specific interrupt number.\r
+ \return 0 Interrupt is not enabled.\r
+ \return 1 Interrupt is enabled.\r
+ \note IRQn must not be negative.\r
+ */\r
+__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn)\r
+{\r
+ if ((int32_t)(IRQn) >= 0)\r
+ {\r
+ return((uint32_t)(((NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));\r
+ }\r
+ else\r
+ {\r
+ return(0U);\r
+ }\r
+}\r
+\r
+\r
+/**\r
+ \brief Disable Interrupt\r
+ \details Disables a device specific interrupt in the NVIC interrupt controller.\r
+ \param [in] IRQn Device specific interrupt number.\r
+ \note IRQn must not be negative.\r
+ */\r
+__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn)\r
+{\r
+ if ((int32_t)(IRQn) >= 0)\r
+ {\r
+ NVIC->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));\r
+ __DSB();\r
+ __ISB();\r
+ }\r
+}\r
+\r
+\r
+/**\r
+ \brief Get Pending Interrupt\r
+ \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt.\r
+ \param [in] IRQn Device specific interrupt number.\r
+ \return 0 Interrupt status is not pending.\r
+ \return 1 Interrupt status is pending.\r
+ \note IRQn must not be negative.\r
+ */\r
+__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn)\r
+{\r
+ if ((int32_t)(IRQn) >= 0)\r
+ {\r
+ return((uint32_t)(((NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));\r
+ }\r
+ else\r
+ {\r
+ return(0U);\r
+ }\r
+}\r
+\r
+\r
+/**\r
+ \brief Set Pending Interrupt\r
+ \details Sets the pending bit of a device specific interrupt in the NVIC pending register.\r
+ \param [in] IRQn Device specific interrupt number.\r
+ \note IRQn must not be negative.\r
+ */\r
+__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn)\r
+{\r
+ if ((int32_t)(IRQn) >= 0)\r
+ {\r
+ NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));\r
+ }\r
+}\r
+\r
+\r
+/**\r
+ \brief Clear Pending Interrupt\r
+ \details Clears the pending bit of a device specific interrupt in the NVIC pending register.\r
+ \param [in] IRQn Device specific interrupt number.\r
+ \note IRQn must not be negative.\r
+ */\r
+__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn)\r
+{\r
+ if ((int32_t)(IRQn) >= 0)\r
+ {\r
+ NVIC->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));\r
+ }\r
+}\r
+\r
+\r
+/**\r
+ \brief Get Active Interrupt\r
+ \details Reads the active register in the NVIC and returns the active bit for the device specific interrupt.\r
+ \param [in] IRQn Device specific interrupt number.\r
+ \return 0 Interrupt status is not active.\r
+ \return 1 Interrupt status is active.\r
+ \note IRQn must not be negative.\r
+ */\r
+__STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn)\r
+{\r
+ if ((int32_t)(IRQn) >= 0)\r
+ {\r
+ return((uint32_t)(((NVIC->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));\r
+ }\r
+ else\r
+ {\r
+ return(0U);\r
+ }\r
+}\r
+\r
+\r
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)\r
+/**\r
+ \brief Get Interrupt Target State\r
+ \details Reads the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt.\r
+ \param [in] IRQn Device specific interrupt number.\r
+ \return 0 if interrupt is assigned to Secure\r
+ \return 1 if interrupt is assigned to Non Secure\r
+ \note IRQn must not be negative.\r
+ */\r
+__STATIC_INLINE uint32_t NVIC_GetTargetState(IRQn_Type IRQn)\r
+{\r
+ if ((int32_t)(IRQn) >= 0)\r
+ {\r
+ return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));\r
+ }\r
+ else\r
+ {\r
+ return(0U);\r
+ }\r
+}\r
+\r
+\r
+/**\r
+ \brief Set Interrupt Target State\r
+ \details Sets the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt.\r
+ \param [in] IRQn Device specific interrupt number.\r
+ \return 0 if interrupt is assigned to Secure\r
+ 1 if interrupt is assigned to Non Secure\r
+ \note IRQn must not be negative.\r
+ */\r
+__STATIC_INLINE uint32_t NVIC_SetTargetState(IRQn_Type IRQn)\r
+{\r
+ if ((int32_t)(IRQn) >= 0)\r
+ {\r
+ NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] |= ((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)));\r
+ return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));\r
+ }\r
+ else\r
+ {\r
+ return(0U);\r
+ }\r
+}\r
+\r
+\r
+/**\r
+ \brief Clear Interrupt Target State\r
+ \details Clears the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt.\r
+ \param [in] IRQn Device specific interrupt number.\r
+ \return 0 if interrupt is assigned to Secure\r
+ 1 if interrupt is assigned to Non Secure\r
+ \note IRQn must not be negative.\r
+ */\r
+__STATIC_INLINE uint32_t NVIC_ClearTargetState(IRQn_Type IRQn)\r
+{\r
+ if ((int32_t)(IRQn) >= 0)\r
+ {\r
+ NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] &= ~((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)));\r
+ return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));\r
+ }\r
+ else\r
+ {\r
+ return(0U);\r
+ }\r
+}\r
+#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */\r
+\r
+\r
+/**\r
+ \brief Set Interrupt Priority\r
+ \details Sets the priority of a device specific interrupt or a processor exception.\r
+ The interrupt number can be positive to specify a device specific interrupt,\r
+ or negative to specify a processor exception.\r
+ \param [in] IRQn Interrupt number.\r
+ \param [in] priority Priority to set.\r
+ \note The priority cannot be set for every processor exception.\r
+ */\r
+__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)\r
+{\r
+ if ((int32_t)(IRQn) >= 0)\r
+ {\r
+ NVIC->IPR[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);\r
+ }\r
+ else\r
+ {\r
+ SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);\r
+ }\r
+}\r
+\r
+\r
+/**\r
+ \brief Get Interrupt Priority\r
+ \details Reads the priority of a device specific interrupt or a processor exception.\r
+ The interrupt number can be positive to specify a device specific interrupt,\r
+ or negative to specify a processor exception.\r
+ \param [in] IRQn Interrupt number.\r
+ \return Interrupt Priority.\r
+ Value is aligned automatically to the implemented priority bits of the microcontroller.\r
+ */\r
+__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn)\r
+{\r
+\r
+ if ((int32_t)(IRQn) >= 0)\r
+ {\r
+ return(((uint32_t)NVIC->IPR[((uint32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS)));\r
+ }\r
+ else\r
+ {\r
+ return(((uint32_t)SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS)));\r
+ }\r
+}\r
+\r
+\r
+/**\r
+ \brief Encode Priority\r
+ \details Encodes the priority for an interrupt with the given priority group,\r
+ preemptive priority value, and subpriority value.\r
+ In case of a conflict between priority grouping and available\r
+ priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.\r
+ \param [in] PriorityGroup Used priority group.\r
+ \param [in] PreemptPriority Preemptive priority value (starting from 0).\r
+ \param [in] SubPriority Subpriority value (starting from 0).\r
+ \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority().\r
+ */\r
+__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)\r
+{\r
+ uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */\r
+ uint32_t PreemptPriorityBits;\r
+ uint32_t SubPriorityBits;\r
+\r
+ PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);\r
+ SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));\r
+\r
+ return (\r
+ ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) |\r
+ ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL)))\r
+ );\r
+}\r
+\r
+\r
+/**\r
+ \brief Decode Priority\r
+ \details Decodes an interrupt priority value with a given priority group to\r
+ preemptive priority value and subpriority value.\r
+ In case of a conflict between priority grouping and available\r
+ priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set.\r
+ \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority().\r
+ \param [in] PriorityGroup Used priority group.\r
+ \param [out] pPreemptPriority Preemptive priority value (starting from 0).\r
+ \param [out] pSubPriority Subpriority value (starting from 0).\r
+ */\r
+__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority)\r
+{\r
+ uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */\r
+ uint32_t PreemptPriorityBits;\r
+ uint32_t SubPriorityBits;\r
+\r
+ PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);\r
+ SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));\r
+\r
+ *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL);\r
+ *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL);\r
+}\r
+\r
+\r
+/**\r
+ \brief Set Interrupt Vector\r
+ \details Sets an interrupt vector in SRAM based interrupt vector table.\r
+ The interrupt number can be positive to specify a device specific interrupt,\r
+ or negative to specify a processor exception.\r
+ VTOR must been relocated to SRAM before.\r
+ \param [in] IRQn Interrupt number\r
+ \param [in] vector Address of interrupt handler function\r
+ */\r
+__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector)\r
+{\r
+ uint32_t *vectors = (uint32_t *)SCB->VTOR;\r
+ vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector;\r
+}\r
+\r
+\r
+/**\r
+ \brief Get Interrupt Vector\r
+ \details Reads an interrupt vector from interrupt vector table.\r
+ The interrupt number can be positive to specify a device specific interrupt,\r
+ or negative to specify a processor exception.\r
+ \param [in] IRQn Interrupt number.\r
+ \return Address of interrupt handler function\r
+ */\r
+__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn)\r
+{\r
+ uint32_t *vectors = (uint32_t *)SCB->VTOR;\r
+ return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET];\r
+}\r
+\r
+\r
+/**\r
+ \brief System Reset\r
+ \details Initiates a system reset request to reset the MCU.\r
+ */\r
+__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void)\r
+{\r
+ __DSB(); /* Ensure all outstanding memory accesses included\r
+ buffered write are completed before reset */\r
+ SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |\r
+ (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) |\r
+ SCB_AIRCR_SYSRESETREQ_Msk ); /* Keep priority group unchanged */\r
+ __DSB(); /* Ensure completion of memory access */\r
+\r
+ for(;;) /* wait until reset */\r
+ {\r
+ __NOP();\r
+ }\r
+}\r
+\r
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)\r
+/**\r
+ \brief Set Priority Grouping (non-secure)\r
+ \details Sets the non-secure priority grouping field when in secure state using the required unlock sequence.\r
+ The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field.\r
+ Only values from 0..7 are used.\r
+ In case of a conflict between priority grouping and available\r
+ priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.\r
+ \param [in] PriorityGroup Priority grouping field.\r
+ */\r
+__STATIC_INLINE void TZ_NVIC_SetPriorityGrouping_NS(uint32_t PriorityGroup)\r
+{\r
+ uint32_t reg_value;\r
+ uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */\r
+\r
+ reg_value = SCB_NS->AIRCR; /* read old register configuration */\r
+ reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */\r
+ reg_value = (reg_value |\r
+ ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |\r
+ (PriorityGroupTmp << 8U) ); /* Insert write key and priorty group */\r
+ SCB_NS->AIRCR = reg_value;\r
+}\r
+\r
+\r
+/**\r
+ \brief Get Priority Grouping (non-secure)\r
+ \details Reads the priority grouping field from the non-secure NVIC when in secure state.\r
+ \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field).\r
+ */\r
+__STATIC_INLINE uint32_t TZ_NVIC_GetPriorityGrouping_NS(void)\r
+{\r
+ return ((uint32_t)((SCB_NS->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos));\r
+}\r
+\r
+\r
+/**\r
+ \brief Enable Interrupt (non-secure)\r
+ \details Enables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state.\r
+ \param [in] IRQn Device specific interrupt number.\r
+ \note IRQn must not be negative.\r
+ */\r
+__STATIC_INLINE void TZ_NVIC_EnableIRQ_NS(IRQn_Type IRQn)\r
+{\r
+ if ((int32_t)(IRQn) >= 0)\r
+ {\r
+ NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));\r
+ }\r
+}\r
+\r
+\r
+/**\r
+ \brief Get Interrupt Enable status (non-secure)\r
+ \details Returns a device specific interrupt enable status from the non-secure NVIC interrupt controller when in secure state.\r
+ \param [in] IRQn Device specific interrupt number.\r
+ \return 0 Interrupt is not enabled.\r
+ \return 1 Interrupt is enabled.\r
+ \note IRQn must not be negative.\r
+ */\r
+__STATIC_INLINE uint32_t TZ_NVIC_GetEnableIRQ_NS(IRQn_Type IRQn)\r
+{\r
+ if ((int32_t)(IRQn) >= 0)\r
+ {\r
+ return((uint32_t)(((NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));\r
+ }\r
+ else\r
+ {\r
+ return(0U);\r
+ }\r
+}\r
+\r
+\r
+/**\r
+ \brief Disable Interrupt (non-secure)\r
+ \details Disables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state.\r
+ \param [in] IRQn Device specific interrupt number.\r
+ \note IRQn must not be negative.\r
+ */\r
+__STATIC_INLINE void TZ_NVIC_DisableIRQ_NS(IRQn_Type IRQn)\r
+{\r
+ if ((int32_t)(IRQn) >= 0)\r
+ {\r
+ NVIC_NS->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));\r
+ }\r
+}\r
+\r
+\r
+/**\r
+ \brief Get Pending Interrupt (non-secure)\r
+ \details Reads the NVIC pending register in the non-secure NVIC when in secure state and returns the pending bit for the specified device specific interrupt.\r
+ \param [in] IRQn Device specific interrupt number.\r
+ \return 0 Interrupt status is not pending.\r
+ \return 1 Interrupt status is pending.\r
+ \note IRQn must not be negative.\r
+ */\r
+__STATIC_INLINE uint32_t TZ_NVIC_GetPendingIRQ_NS(IRQn_Type IRQn)\r
+{\r
+ if ((int32_t)(IRQn) >= 0)\r
+ {\r
+ return((uint32_t)(((NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));\r
+ }\r
+ else\r
+ {\r
+ return(0U);\r
+ }\r
+}\r
+\r
+\r
+/**\r
+ \brief Set Pending Interrupt (non-secure)\r
+ \details Sets the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state.\r
+ \param [in] IRQn Device specific interrupt number.\r
+ \note IRQn must not be negative.\r
+ */\r
+__STATIC_INLINE void TZ_NVIC_SetPendingIRQ_NS(IRQn_Type IRQn)\r
+{\r
+ if ((int32_t)(IRQn) >= 0)\r
+ {\r
+ NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));\r
+ }\r
+}\r
+\r
+\r
+/**\r
+ \brief Clear Pending Interrupt (non-secure)\r
+ \details Clears the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state.\r
+ \param [in] IRQn Device specific interrupt number.\r
+ \note IRQn must not be negative.\r
+ */\r
+__STATIC_INLINE void TZ_NVIC_ClearPendingIRQ_NS(IRQn_Type IRQn)\r
+{\r
+ if ((int32_t)(IRQn) >= 0)\r
+ {\r
+ NVIC_NS->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));\r
+ }\r
+}\r
+\r
+\r
+/**\r
+ \brief Get Active Interrupt (non-secure)\r
+ \details Reads the active register in non-secure NVIC when in secure state and returns the active bit for the device specific interrupt.\r
+ \param [in] IRQn Device specific interrupt number.\r
+ \return 0 Interrupt status is not active.\r
+ \return 1 Interrupt status is active.\r
+ \note IRQn must not be negative.\r
+ */\r
+__STATIC_INLINE uint32_t TZ_NVIC_GetActive_NS(IRQn_Type IRQn)\r
+{\r
+ if ((int32_t)(IRQn) >= 0)\r
+ {\r
+ return((uint32_t)(((NVIC_NS->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));\r
+ }\r
+ else\r
+ {\r
+ return(0U);\r
+ }\r
+}\r
+\r
+\r
+/**\r
+ \brief Set Interrupt Priority (non-secure)\r
+ \details Sets the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state.\r
+ The interrupt number can be positive to specify a device specific interrupt,\r
+ or negative to specify a processor exception.\r
+ \param [in] IRQn Interrupt number.\r
+ \param [in] priority Priority to set.\r
+ \note The priority cannot be set for every non-secure processor exception.\r
+ */\r
+__STATIC_INLINE void TZ_NVIC_SetPriority_NS(IRQn_Type IRQn, uint32_t priority)\r
+{\r
+ if ((int32_t)(IRQn) >= 0)\r
+ {\r
+ NVIC_NS->IPR[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);\r
+ }\r
+ else\r
+ {\r
+ SCB_NS->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);\r
+ }\r
+}\r
+\r
+\r
+/**\r
+ \brief Get Interrupt Priority (non-secure)\r
+ \details Reads the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state.\r
+ The interrupt number can be positive to specify a device specific interrupt,\r
+ or negative to specify a processor exception.\r
+ \param [in] IRQn Interrupt number.\r
+ \return Interrupt Priority. Value is aligned automatically to the implemented priority bits of the microcontroller.\r
+ */\r
+__STATIC_INLINE uint32_t TZ_NVIC_GetPriority_NS(IRQn_Type IRQn)\r
+{\r
+\r
+ if ((int32_t)(IRQn) >= 0)\r
+ {\r
+ return(((uint32_t)NVIC_NS->IPR[((uint32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS)));\r
+ }\r
+ else\r
+ {\r
+ return(((uint32_t)SCB_NS->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS)));\r
+ }\r
+}\r
+#endif /* defined (__ARM_FEATURE_CMSE) &&(__ARM_FEATURE_CMSE == 3U) */\r
+\r
+/*@} end of CMSIS_Core_NVICFunctions */\r
+\r
+/* ########################## MPU functions #################################### */\r
+\r
+#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)\r
+\r
+#include "mpu_armv8.h"\r
+\r
+#endif\r
+\r
+/* ########################## FPU functions #################################### */\r
+/**\r
+ \ingroup CMSIS_Core_FunctionInterface\r
+ \defgroup CMSIS_Core_FpuFunctions FPU Functions\r
+ \brief Function that provides FPU type.\r
+ @{\r
+ */\r
+\r
+/**\r
+ \brief get FPU type\r
+ \details returns the FPU type\r
+ \returns\r
+ - \b 0: No FPU\r
+ - \b 1: Single precision FPU\r
+ - \b 2: Double + Single precision FPU\r
+ */\r
+__STATIC_INLINE uint32_t SCB_GetFPUType(void)\r
+{\r
+ uint32_t mvfr0;\r
+\r
+ mvfr0 = FPU->MVFR0;\r
+ if ((mvfr0 & (FPU_MVFR0_Single_precision_Msk | FPU_MVFR0_Double_precision_Msk)) == 0x220U)\r
+ {\r
+ return 2U; /* Double + Single precision FPU */\r
+ }\r
+ else if ((mvfr0 & (FPU_MVFR0_Single_precision_Msk | FPU_MVFR0_Double_precision_Msk)) == 0x020U)\r
+ {\r
+ return 1U; /* Single precision FPU */\r
+ }\r
+ else\r
+ {\r
+ return 0U; /* No FPU */\r
+ }\r
+}\r
+\r
+\r
+/*@} end of CMSIS_Core_FpuFunctions */\r
+\r
+\r
+\r
+/* ########################## SAU functions #################################### */\r
+/**\r
+ \ingroup CMSIS_Core_FunctionInterface\r
+ \defgroup CMSIS_Core_SAUFunctions SAU Functions\r
+ \brief Functions that configure the SAU.\r
+ @{\r
+ */\r
+\r
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)\r
+\r
+/**\r
+ \brief Enable SAU\r
+ \details Enables the Security Attribution Unit (SAU).\r
+ */\r
+__STATIC_INLINE void TZ_SAU_Enable(void)\r
+{\r
+ SAU->CTRL |= (SAU_CTRL_ENABLE_Msk);\r
+}\r
+\r
+\r
+\r
+/**\r
+ \brief Disable SAU\r
+ \details Disables the Security Attribution Unit (SAU).\r
+ */\r
+__STATIC_INLINE void TZ_SAU_Disable(void)\r
+{\r
+ SAU->CTRL &= ~(SAU_CTRL_ENABLE_Msk);\r
+}\r
+\r
+#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */\r
+\r
+/*@} end of CMSIS_Core_SAUFunctions */\r
+\r
+\r
+\r
+\r
+/* ################################## SysTick function ############################################ */\r
+/**\r
+ \ingroup CMSIS_Core_FunctionInterface\r
+ \defgroup CMSIS_Core_SysTickFunctions SysTick Functions\r
+ \brief Functions that configure the System.\r
+ @{\r
+ */\r
+\r
+#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U)\r
+\r
+/**\r
+ \brief System Tick Configuration\r
+ \details Initializes the System Timer and its interrupt, and starts the System Tick Timer.\r
+ Counter is in free running mode to generate periodic interrupts.\r
+ \param [in] ticks Number of ticks between two interrupts.\r
+ \return 0 Function succeeded.\r
+ \return 1 Function failed.\r
+ \note When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the\r
+ function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>\r
+ must contain a vendor-specific implementation of this function.\r
+ */\r
+__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)\r
+{\r
+ if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk)\r
+ {\r
+ return (1UL); /* Reload value impossible */\r
+ }\r
+\r
+ SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */\r
+ NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */\r
+ SysTick->VAL = 0UL; /* Load the SysTick Counter Value */\r
+ SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk |\r
+ SysTick_CTRL_TICKINT_Msk |\r
+ SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */\r
+ return (0UL); /* Function successful */\r
+}\r
+\r
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)\r
+/**\r
+ \brief System Tick Configuration (non-secure)\r
+ \details Initializes the non-secure System Timer and its interrupt when in secure state, and starts the System Tick Timer.\r
+ Counter is in free running mode to generate periodic interrupts.\r
+ \param [in] ticks Number of ticks between two interrupts.\r
+ \return 0 Function succeeded.\r
+ \return 1 Function failed.\r
+ \note When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the\r
+ function <b>TZ_SysTick_Config_NS</b> is not included. In this case, the file <b><i>device</i>.h</b>\r
+ must contain a vendor-specific implementation of this function.\r
+\r
+ */\r
+__STATIC_INLINE uint32_t TZ_SysTick_Config_NS(uint32_t ticks)\r
+{\r
+ if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk)\r
+ {\r
+ return (1UL); /* Reload value impossible */\r
+ }\r
+\r
+ SysTick_NS->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */\r
+ TZ_NVIC_SetPriority_NS (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */\r
+ SysTick_NS->VAL = 0UL; /* Load the SysTick Counter Value */\r
+ SysTick_NS->CTRL = SysTick_CTRL_CLKSOURCE_Msk |\r
+ SysTick_CTRL_TICKINT_Msk |\r
+ SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */\r
+ return (0UL); /* Function successful */\r
+}\r
+#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */\r
+\r
+#endif\r
+\r
+/*@} end of CMSIS_Core_SysTickFunctions */\r
+\r
+\r
+\r
+/* ##################################### Debug In/Output function ########################################### */\r
+/**\r
+ \ingroup CMSIS_Core_FunctionInterface\r
+ \defgroup CMSIS_core_DebugFunctions ITM Functions\r
+ \brief Functions that access the ITM debug interface.\r
+ @{\r
+ */\r
+\r
+extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters. */\r
+#define ITM_RXBUFFER_EMPTY ((int32_t)0x5AA55AA5U) /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */\r
+\r
+\r
+/**\r
+ \brief ITM Send Character\r
+ \details Transmits a character via the ITM channel 0, and\r
+ \li Just returns when no debugger is connected that has booked the output.\r
+ \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted.\r
+ \param [in] ch Character to transmit.\r
+ \returns Character to transmit.\r
+ */\r
+__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch)\r
+{\r
+ if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) && /* ITM enabled */\r
+ ((ITM->TER & 1UL ) != 0UL) ) /* ITM Port #0 enabled */\r
+ {\r
+ while (ITM->PORT[0U].u32 == 0UL)\r
+ {\r
+ __NOP();\r
+ }\r
+ ITM->PORT[0U].u8 = (uint8_t)ch;\r
+ }\r
+ return (ch);\r
+}\r
+\r
+\r
+/**\r
+ \brief ITM Receive Character\r
+ \details Inputs a character via the external variable \ref ITM_RxBuffer.\r
+ \return Received character.\r
+ \return -1 No character pending.\r
+ */\r
+__STATIC_INLINE int32_t ITM_ReceiveChar (void)\r
+{\r
+ int32_t ch = -1; /* no character available */\r
+\r
+ if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY)\r
+ {\r
+ ch = ITM_RxBuffer;\r
+ ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */\r
+ }\r
+\r
+ return (ch);\r
+}\r
+\r
+\r
+/**\r
+ \brief ITM Check Character\r
+ \details Checks whether a character is pending for reading in the variable \ref ITM_RxBuffer.\r
+ \return 0 No character available.\r
+ \return 1 Character available.\r
+ */\r
+__STATIC_INLINE int32_t ITM_CheckChar (void)\r
+{\r
+\r
+ if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY)\r
+ {\r
+ return (0); /* no character available */\r
+ }\r
+ else\r
+ {\r
+ return (1); /* character available */\r
+ }\r
+}\r
+\r
+/*@} end of CMSIS_core_DebugFunctions */\r
+\r
+\r
+\r
+\r
+#ifdef __cplusplus\r
+}\r
+#endif\r
+\r
+#endif /* __CORE_ARMV8MML_H_DEPENDANT */\r
+\r
+#endif /* __CMSIS_GENERIC */\r
--- /dev/null
+/**************************************************************************//**\r
+ * @file core_cm0.h\r
+ * @brief CMSIS Cortex-M0 Core Peripheral Access Layer Header File\r
+ * @version V5.0.5\r
+ * @date 28. May 2018\r
+ ******************************************************************************/\r
+/*\r
+ * Copyright (c) 2009-2018 Arm Limited. All rights reserved.\r
+ *\r
+ * SPDX-License-Identifier: Apache-2.0\r
+ *\r
+ * Licensed under the Apache License, Version 2.0 (the License); you may\r
+ * not use this file except in compliance with the License.\r
+ * You may obtain a copy of the License at\r
+ *\r
+ * www.apache.org/licenses/LICENSE-2.0\r
+ *\r
+ * Unless required by applicable law or agreed to in writing, software\r
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT\r
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\r
+ * See the License for the specific language governing permissions and\r
+ * limitations under the License.\r
+ */\r
+\r
+#if defined ( __ICCARM__ )\r
+ #pragma system_include /* treat file as system include file for MISRA check */\r
+#elif defined (__clang__)\r
+ #pragma clang system_header /* treat file as system include file */\r
+#endif\r
+\r
+#ifndef __CORE_CM0_H_GENERIC\r
+#define __CORE_CM0_H_GENERIC\r
+\r
+#include <stdint.h>\r
+\r
+#ifdef __cplusplus\r
+ extern "C" {\r
+#endif\r
+\r
+/**\r
+ \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions\r
+ CMSIS violates the following MISRA-C:2004 rules:\r
+\r
+ \li Required Rule 8.5, object/function definition in header file.<br>\r
+ Function definitions in header files are used to allow 'inlining'.\r
+\r
+ \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>\r
+ Unions are used for effective representation of core registers.\r
+\r
+ \li Advisory Rule 19.7, Function-like macro defined.<br>\r
+ Function-like macros are used to allow more efficient code.\r
+ */\r
+\r
+\r
+/*******************************************************************************\r
+ * CMSIS definitions\r
+ ******************************************************************************/\r
+/**\r
+ \ingroup Cortex_M0\r
+ @{\r
+ */\r
+\r
+#include "cmsis_version.h"\r
+ \r
+/* CMSIS CM0 definitions */\r
+#define __CM0_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */\r
+#define __CM0_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */\r
+#define __CM0_CMSIS_VERSION ((__CM0_CMSIS_VERSION_MAIN << 16U) | \\r
+ __CM0_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */\r
+\r
+#define __CORTEX_M (0U) /*!< Cortex-M Core */\r
+\r
+/** __FPU_USED indicates whether an FPU is used or not.\r
+ This core does not support an FPU at all\r
+*/\r
+#define __FPU_USED 0U\r
+\r
+#if defined ( __CC_ARM )\r
+ #if defined __TARGET_FPU_VFP\r
+ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"\r
+ #endif\r
+\r
+#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)\r
+ #if defined __ARM_PCS_VFP\r
+ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"\r
+ #endif\r
+\r
+#elif defined ( __GNUC__ )\r
+ #if defined (__VFP_FP__) && !defined(__SOFTFP__)\r
+ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"\r
+ #endif\r
+\r
+#elif defined ( __ICCARM__ )\r
+ #if defined __ARMVFP__\r
+ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"\r
+ #endif\r
+\r
+#elif defined ( __TI_ARM__ )\r
+ #if defined __TI_VFP_SUPPORT__\r
+ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"\r
+ #endif\r
+\r
+#elif defined ( __TASKING__ )\r
+ #if defined __FPU_VFP__\r
+ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"\r
+ #endif\r
+\r
+#elif defined ( __CSMC__ )\r
+ #if ( __CSMC__ & 0x400U)\r
+ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"\r
+ #endif\r
+\r
+#endif\r
+\r
+#include "cmsis_compiler.h" /* CMSIS compiler specific defines */\r
+\r
+\r
+#ifdef __cplusplus\r
+}\r
+#endif\r
+\r
+#endif /* __CORE_CM0_H_GENERIC */\r
+\r
+#ifndef __CMSIS_GENERIC\r
+\r
+#ifndef __CORE_CM0_H_DEPENDANT\r
+#define __CORE_CM0_H_DEPENDANT\r
+\r
+#ifdef __cplusplus\r
+ extern "C" {\r
+#endif\r
+\r
+/* check device defines and use defaults */\r
+#if defined __CHECK_DEVICE_DEFINES\r
+ #ifndef __CM0_REV\r
+ #define __CM0_REV 0x0000U\r
+ #warning "__CM0_REV not defined in device header file; using default!"\r
+ #endif\r
+\r
+ #ifndef __NVIC_PRIO_BITS\r
+ #define __NVIC_PRIO_BITS 2U\r
+ #warning "__NVIC_PRIO_BITS not defined in device header file; using default!"\r
+ #endif\r
+\r
+ #ifndef __Vendor_SysTickConfig\r
+ #define __Vendor_SysTickConfig 0U\r
+ #warning "__Vendor_SysTickConfig not defined in device header file; using default!"\r
+ #endif\r
+#endif\r
+\r
+/* IO definitions (access restrictions to peripheral registers) */\r
+/**\r
+ \defgroup CMSIS_glob_defs CMSIS Global Defines\r
+\r
+ <strong>IO Type Qualifiers</strong> are used\r
+ \li to specify the access to peripheral variables.\r
+ \li for automatic generation of peripheral register debug information.\r
+*/\r
+#ifdef __cplusplus\r
+ #define __I volatile /*!< Defines 'read only' permissions */\r
+#else\r
+ #define __I volatile const /*!< Defines 'read only' permissions */\r
+#endif\r
+#define __O volatile /*!< Defines 'write only' permissions */\r
+#define __IO volatile /*!< Defines 'read / write' permissions */\r
+\r
+/* following defines should be used for structure members */\r
+#define __IM volatile const /*! Defines 'read only' structure member permissions */\r
+#define __OM volatile /*! Defines 'write only' structure member permissions */\r
+#define __IOM volatile /*! Defines 'read / write' structure member permissions */\r
+\r
+/*@} end of group Cortex_M0 */\r
+\r
+\r
+\r
+/*******************************************************************************\r
+ * Register Abstraction\r
+ Core Register contain:\r
+ - Core Register\r
+ - Core NVIC Register\r
+ - Core SCB Register\r
+ - Core SysTick Register\r
+ ******************************************************************************/\r
+/**\r
+ \defgroup CMSIS_core_register Defines and Type Definitions\r
+ \brief Type definitions and defines for Cortex-M processor based devices.\r
+*/\r
+\r
+/**\r
+ \ingroup CMSIS_core_register\r
+ \defgroup CMSIS_CORE Status and Control Registers\r
+ \brief Core Register type definitions.\r
+ @{\r
+ */\r
+\r
+/**\r
+ \brief Union type to access the Application Program Status Register (APSR).\r
+ */\r
+typedef union\r
+{\r
+ struct\r
+ {\r
+ uint32_t _reserved0:28; /*!< bit: 0..27 Reserved */\r
+ uint32_t V:1; /*!< bit: 28 Overflow condition code flag */\r
+ uint32_t C:1; /*!< bit: 29 Carry condition code flag */\r
+ uint32_t Z:1; /*!< bit: 30 Zero condition code flag */\r
+ uint32_t N:1; /*!< bit: 31 Negative condition code flag */\r
+ } b; /*!< Structure used for bit access */\r
+ uint32_t w; /*!< Type used for word access */\r
+} APSR_Type;\r
+\r
+/* APSR Register Definitions */\r
+#define APSR_N_Pos 31U /*!< APSR: N Position */\r
+#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */\r
+\r
+#define APSR_Z_Pos 30U /*!< APSR: Z Position */\r
+#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */\r
+\r
+#define APSR_C_Pos 29U /*!< APSR: C Position */\r
+#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */\r
+\r
+#define APSR_V_Pos 28U /*!< APSR: V Position */\r
+#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */\r
+\r
+\r
+/**\r
+ \brief Union type to access the Interrupt Program Status Register (IPSR).\r
+ */\r
+typedef union\r
+{\r
+ struct\r
+ {\r
+ uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */\r
+ uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */\r
+ } b; /*!< Structure used for bit access */\r
+ uint32_t w; /*!< Type used for word access */\r
+} IPSR_Type;\r
+\r
+/* IPSR Register Definitions */\r
+#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */\r
+#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */\r
+\r
+\r
+/**\r
+ \brief Union type to access the Special-Purpose Program Status Registers (xPSR).\r
+ */\r
+typedef union\r
+{\r
+ struct\r
+ {\r
+ uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */\r
+ uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */\r
+ uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */\r
+ uint32_t _reserved1:3; /*!< bit: 25..27 Reserved */\r
+ uint32_t V:1; /*!< bit: 28 Overflow condition code flag */\r
+ uint32_t C:1; /*!< bit: 29 Carry condition code flag */\r
+ uint32_t Z:1; /*!< bit: 30 Zero condition code flag */\r
+ uint32_t N:1; /*!< bit: 31 Negative condition code flag */\r
+ } b; /*!< Structure used for bit access */\r
+ uint32_t w; /*!< Type used for word access */\r
+} xPSR_Type;\r
+\r
+/* xPSR Register Definitions */\r
+#define xPSR_N_Pos 31U /*!< xPSR: N Position */\r
+#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */\r
+\r
+#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */\r
+#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */\r
+\r
+#define xPSR_C_Pos 29U /*!< xPSR: C Position */\r
+#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */\r
+\r
+#define xPSR_V_Pos 28U /*!< xPSR: V Position */\r
+#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */\r
+\r
+#define xPSR_T_Pos 24U /*!< xPSR: T Position */\r
+#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */\r
+\r
+#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */\r
+#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */\r
+\r
+\r
+/**\r
+ \brief Union type to access the Control Registers (CONTROL).\r
+ */\r
+typedef union\r
+{\r
+ struct\r
+ {\r
+ uint32_t _reserved0:1; /*!< bit: 0 Reserved */\r
+ uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */\r
+ uint32_t _reserved1:30; /*!< bit: 2..31 Reserved */\r
+ } b; /*!< Structure used for bit access */\r
+ uint32_t w; /*!< Type used for word access */\r
+} CONTROL_Type;\r
+\r
+/* CONTROL Register Definitions */\r
+#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */\r
+#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */\r
+\r
+/*@} end of group CMSIS_CORE */\r
+\r
+\r
+/**\r
+ \ingroup CMSIS_core_register\r
+ \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC)\r
+ \brief Type definitions for the NVIC Registers\r
+ @{\r
+ */\r
+\r
+/**\r
+ \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC).\r
+ */\r
+typedef struct\r
+{\r
+ __IOM uint32_t ISER[1U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */\r
+ uint32_t RESERVED0[31U];\r
+ __IOM uint32_t ICER[1U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */\r
+ uint32_t RSERVED1[31U];\r
+ __IOM uint32_t ISPR[1U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */\r
+ uint32_t RESERVED2[31U];\r
+ __IOM uint32_t ICPR[1U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */\r
+ uint32_t RESERVED3[31U];\r
+ uint32_t RESERVED4[64U];\r
+ __IOM uint32_t IP[8U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register */\r
+} NVIC_Type;\r
+\r
+/*@} end of group CMSIS_NVIC */\r
+\r
+\r
+/**\r
+ \ingroup CMSIS_core_register\r
+ \defgroup CMSIS_SCB System Control Block (SCB)\r
+ \brief Type definitions for the System Control Block Registers\r
+ @{\r
+ */\r
+\r
+/**\r
+ \brief Structure type to access the System Control Block (SCB).\r
+ */\r
+typedef struct\r
+{\r
+ __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */\r
+ __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */\r
+ uint32_t RESERVED0;\r
+ __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */\r
+ __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */\r
+ __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */\r
+ uint32_t RESERVED1;\r
+ __IOM uint32_t SHP[2U]; /*!< Offset: 0x01C (R/W) System Handlers Priority Registers. [0] is RESERVED */\r
+ __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */\r
+} SCB_Type;\r
+\r
+/* SCB CPUID Register Definitions */\r
+#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */\r
+#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */\r
+\r
+#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */\r
+#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */\r
+\r
+#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */\r
+#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */\r
+\r
+#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */\r
+#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */\r
+\r
+#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */\r
+#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */\r
+\r
+/* SCB Interrupt Control State Register Definitions */\r
+#define SCB_ICSR_NMIPENDSET_Pos 31U /*!< SCB ICSR: NMIPENDSET Position */\r
+#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */\r
+\r
+#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */\r
+#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */\r
+\r
+#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */\r
+#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */\r
+\r
+#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */\r
+#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */\r
+\r
+#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */\r
+#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */\r
+\r
+#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */\r
+#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */\r
+\r
+#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */\r
+#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */\r
+\r
+#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */\r
+#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */\r
+\r
+#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */\r
+#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */\r
+\r
+/* SCB Application Interrupt and Reset Control Register Definitions */\r
+#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */\r
+#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */\r
+\r
+#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */\r
+#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */\r
+\r
+#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */\r
+#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */\r
+\r
+#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */\r
+#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */\r
+\r
+#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */\r
+#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */\r
+\r
+/* SCB System Control Register Definitions */\r
+#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */\r
+#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */\r
+\r
+#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */\r
+#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */\r
+\r
+#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */\r
+#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */\r
+\r
+/* SCB Configuration Control Register Definitions */\r
+#define SCB_CCR_STKALIGN_Pos 9U /*!< SCB CCR: STKALIGN Position */\r
+#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */\r
+\r
+#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */\r
+#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */\r
+\r
+/* SCB System Handler Control and State Register Definitions */\r
+#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */\r
+#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */\r
+\r
+/*@} end of group CMSIS_SCB */\r
+\r
+\r
+/**\r
+ \ingroup CMSIS_core_register\r
+ \defgroup CMSIS_SysTick System Tick Timer (SysTick)\r
+ \brief Type definitions for the System Timer Registers.\r
+ @{\r
+ */\r
+\r
+/**\r
+ \brief Structure type to access the System Timer (SysTick).\r
+ */\r
+typedef struct\r
+{\r
+ __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */\r
+ __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */\r
+ __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */\r
+ __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */\r
+} SysTick_Type;\r
+\r
+/* SysTick Control / Status Register Definitions */\r
+#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */\r
+#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */\r
+\r
+#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */\r
+#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */\r
+\r
+#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */\r
+#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */\r
+\r
+#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */\r
+#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */\r
+\r
+/* SysTick Reload Register Definitions */\r
+#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */\r
+#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */\r
+\r
+/* SysTick Current Register Definitions */\r
+#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */\r
+#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */\r
+\r
+/* SysTick Calibration Register Definitions */\r
+#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */\r
+#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */\r
+\r
+#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */\r
+#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */\r
+\r
+#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */\r
+#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */\r
+\r
+/*@} end of group CMSIS_SysTick */\r
+\r
+\r
+/**\r
+ \ingroup CMSIS_core_register\r
+ \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug)\r
+ \brief Cortex-M0 Core Debug Registers (DCB registers, SHCSR, and DFSR) are only accessible over DAP and not via processor.\r
+ Therefore they are not covered by the Cortex-M0 header file.\r
+ @{\r
+ */\r
+/*@} end of group CMSIS_CoreDebug */\r
+\r
+\r
+/**\r
+ \ingroup CMSIS_core_register\r
+ \defgroup CMSIS_core_bitfield Core register bit field macros\r
+ \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk).\r
+ @{\r
+ */\r
+\r
+/**\r
+ \brief Mask and shift a bit field value for use in a register bit range.\r
+ \param[in] field Name of the register bit field.\r
+ \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type.\r
+ \return Masked and shifted value.\r
+*/\r
+#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk)\r
+\r
+/**\r
+ \brief Mask and shift a register value to extract a bit filed value.\r
+ \param[in] field Name of the register bit field.\r
+ \param[in] value Value of register. This parameter is interpreted as an uint32_t type.\r
+ \return Masked and shifted bit field value.\r
+*/\r
+#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos)\r
+\r
+/*@} end of group CMSIS_core_bitfield */\r
+\r
+\r
+/**\r
+ \ingroup CMSIS_core_register\r
+ \defgroup CMSIS_core_base Core Definitions\r
+ \brief Definitions for base addresses, unions, and structures.\r
+ @{\r
+ */\r
+\r
+/* Memory mapping of Core Hardware */\r
+#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */\r
+#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */\r
+#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */\r
+#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */\r
+\r
+#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */\r
+#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */\r
+#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */\r
+\r
+\r
+/*@} */\r
+\r
+\r
+\r
+/*******************************************************************************\r
+ * Hardware Abstraction Layer\r
+ Core Function Interface contains:\r
+ - Core NVIC Functions\r
+ - Core SysTick Functions\r
+ - Core Register Access Functions\r
+ ******************************************************************************/\r
+/**\r
+ \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference\r
+*/\r
+\r
+\r
+\r
+/* ########################## NVIC functions #################################### */\r
+/**\r
+ \ingroup CMSIS_Core_FunctionInterface\r
+ \defgroup CMSIS_Core_NVICFunctions NVIC Functions\r
+ \brief Functions that manage interrupts and exceptions via the NVIC.\r
+ @{\r
+ */\r
+\r
+#ifdef CMSIS_NVIC_VIRTUAL\r
+ #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE\r
+ #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h"\r
+ #endif\r
+ #include CMSIS_NVIC_VIRTUAL_HEADER_FILE\r
+#else\r
+ #define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping\r
+ #define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping\r
+ #define NVIC_EnableIRQ __NVIC_EnableIRQ\r
+ #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ\r
+ #define NVIC_DisableIRQ __NVIC_DisableIRQ\r
+ #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ\r
+ #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ\r
+ #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ\r
+/*#define NVIC_GetActive __NVIC_GetActive not available for Cortex-M0 */\r
+ #define NVIC_SetPriority __NVIC_SetPriority\r
+ #define NVIC_GetPriority __NVIC_GetPriority\r
+ #define NVIC_SystemReset __NVIC_SystemReset\r
+#endif /* CMSIS_NVIC_VIRTUAL */\r
+\r
+#ifdef CMSIS_VECTAB_VIRTUAL\r
+ #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE\r
+ #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h"\r
+ #endif\r
+ #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE\r
+#else\r
+ #define NVIC_SetVector __NVIC_SetVector\r
+ #define NVIC_GetVector __NVIC_GetVector\r
+#endif /* (CMSIS_VECTAB_VIRTUAL) */\r
+\r
+#define NVIC_USER_IRQ_OFFSET 16\r
+\r
+\r
+/* The following EXC_RETURN values are saved the LR on exception entry */\r
+#define EXC_RETURN_HANDLER (0xFFFFFFF1UL) /* return to Handler mode, uses MSP after return */\r
+#define EXC_RETURN_THREAD_MSP (0xFFFFFFF9UL) /* return to Thread mode, uses MSP after return */\r
+#define EXC_RETURN_THREAD_PSP (0xFFFFFFFDUL) /* return to Thread mode, uses PSP after return */\r
+\r
+\r
+/* Interrupt Priorities are WORD accessible only under Armv6-M */\r
+/* The following MACROS handle generation of the register offset and byte masks */\r
+#define _BIT_SHIFT(IRQn) ( ((((uint32_t)(int32_t)(IRQn)) ) & 0x03UL) * 8UL)\r
+#define _SHP_IDX(IRQn) ( (((((uint32_t)(int32_t)(IRQn)) & 0x0FUL)-8UL) >> 2UL) )\r
+#define _IP_IDX(IRQn) ( (((uint32_t)(int32_t)(IRQn)) >> 2UL) )\r
+\r
+#define __NVIC_SetPriorityGrouping(X) (void)(X)\r
+#define __NVIC_GetPriorityGrouping() (0U)\r
+\r
+/**\r
+ \brief Enable Interrupt\r
+ \details Enables a device specific interrupt in the NVIC interrupt controller.\r
+ \param [in] IRQn Device specific interrupt number.\r
+ \note IRQn must not be negative.\r
+ */\r
+__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn)\r
+{\r
+ if ((int32_t)(IRQn) >= 0)\r
+ {\r
+ NVIC->ISER[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));\r
+ }\r
+}\r
+\r
+\r
+/**\r
+ \brief Get Interrupt Enable status\r
+ \details Returns a device specific interrupt enable status from the NVIC interrupt controller.\r
+ \param [in] IRQn Device specific interrupt number.\r
+ \return 0 Interrupt is not enabled.\r
+ \return 1 Interrupt is enabled.\r
+ \note IRQn must not be negative.\r
+ */\r
+__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn)\r
+{\r
+ if ((int32_t)(IRQn) >= 0)\r
+ {\r
+ return((uint32_t)(((NVIC->ISER[0U] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));\r
+ }\r
+ else\r
+ {\r
+ return(0U);\r
+ }\r
+}\r
+\r
+\r
+/**\r
+ \brief Disable Interrupt\r
+ \details Disables a device specific interrupt in the NVIC interrupt controller.\r
+ \param [in] IRQn Device specific interrupt number.\r
+ \note IRQn must not be negative.\r
+ */\r
+__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn)\r
+{\r
+ if ((int32_t)(IRQn) >= 0)\r
+ {\r
+ NVIC->ICER[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));\r
+ __DSB();\r
+ __ISB();\r
+ }\r
+}\r
+\r
+\r
+/**\r
+ \brief Get Pending Interrupt\r
+ \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt.\r
+ \param [in] IRQn Device specific interrupt number.\r
+ \return 0 Interrupt status is not pending.\r
+ \return 1 Interrupt status is pending.\r
+ \note IRQn must not be negative.\r
+ */\r
+__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn)\r
+{\r
+ if ((int32_t)(IRQn) >= 0)\r
+ {\r
+ return((uint32_t)(((NVIC->ISPR[0U] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));\r
+ }\r
+ else\r
+ {\r
+ return(0U);\r
+ }\r
+}\r
+\r
+\r
+/**\r
+ \brief Set Pending Interrupt\r
+ \details Sets the pending bit of a device specific interrupt in the NVIC pending register.\r
+ \param [in] IRQn Device specific interrupt number.\r
+ \note IRQn must not be negative.\r
+ */\r
+__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn)\r
+{\r
+ if ((int32_t)(IRQn) >= 0)\r
+ {\r
+ NVIC->ISPR[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));\r
+ }\r
+}\r
+\r
+\r
+/**\r
+ \brief Clear Pending Interrupt\r
+ \details Clears the pending bit of a device specific interrupt in the NVIC pending register.\r
+ \param [in] IRQn Device specific interrupt number.\r
+ \note IRQn must not be negative.\r
+ */\r
+__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn)\r
+{\r
+ if ((int32_t)(IRQn) >= 0)\r
+ {\r
+ NVIC->ICPR[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));\r
+ }\r
+}\r
+\r
+\r
+/**\r
+ \brief Set Interrupt Priority\r
+ \details Sets the priority of a device specific interrupt or a processor exception.\r
+ The interrupt number can be positive to specify a device specific interrupt,\r
+ or negative to specify a processor exception.\r
+ \param [in] IRQn Interrupt number.\r
+ \param [in] priority Priority to set.\r
+ \note The priority cannot be set for every processor exception.\r
+ */\r
+__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)\r
+{\r
+ if ((int32_t)(IRQn) >= 0)\r
+ {\r
+ NVIC->IP[_IP_IDX(IRQn)] = ((uint32_t)(NVIC->IP[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |\r
+ (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));\r
+ }\r
+ else\r
+ {\r
+ SCB->SHP[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |\r
+ (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));\r
+ }\r
+}\r
+\r
+\r
+/**\r
+ \brief Get Interrupt Priority\r
+ \details Reads the priority of a device specific interrupt or a processor exception.\r
+ The interrupt number can be positive to specify a device specific interrupt,\r
+ or negative to specify a processor exception.\r
+ \param [in] IRQn Interrupt number.\r
+ \return Interrupt Priority.\r
+ Value is aligned automatically to the implemented priority bits of the microcontroller.\r
+ */\r
+__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn)\r
+{\r
+\r
+ if ((int32_t)(IRQn) >= 0)\r
+ {\r
+ return((uint32_t)(((NVIC->IP[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));\r
+ }\r
+ else\r
+ {\r
+ return((uint32_t)(((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));\r
+ }\r
+}\r
+\r
+\r
+/**\r
+ \brief Encode Priority\r
+ \details Encodes the priority for an interrupt with the given priority group,\r
+ preemptive priority value, and subpriority value.\r
+ In case of a conflict between priority grouping and available\r
+ priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.\r
+ \param [in] PriorityGroup Used priority group.\r
+ \param [in] PreemptPriority Preemptive priority value (starting from 0).\r
+ \param [in] SubPriority Subpriority value (starting from 0).\r
+ \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority().\r
+ */\r
+__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)\r
+{\r
+ uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */\r
+ uint32_t PreemptPriorityBits;\r
+ uint32_t SubPriorityBits;\r
+\r
+ PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);\r
+ SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));\r
+\r
+ return (\r
+ ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) |\r
+ ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL)))\r
+ );\r
+}\r
+\r
+\r
+/**\r
+ \brief Decode Priority\r
+ \details Decodes an interrupt priority value with a given priority group to\r
+ preemptive priority value and subpriority value.\r
+ In case of a conflict between priority grouping and available\r
+ priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set.\r
+ \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority().\r
+ \param [in] PriorityGroup Used priority group.\r
+ \param [out] pPreemptPriority Preemptive priority value (starting from 0).\r
+ \param [out] pSubPriority Subpriority value (starting from 0).\r
+ */\r
+__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority)\r
+{\r
+ uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */\r
+ uint32_t PreemptPriorityBits;\r
+ uint32_t SubPriorityBits;\r
+\r
+ PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);\r
+ SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));\r
+\r
+ *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL);\r
+ *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL);\r
+}\r
+\r
+\r
+\r
+/**\r
+ \brief Set Interrupt Vector\r
+ \details Sets an interrupt vector in SRAM based interrupt vector table.\r
+ The interrupt number can be positive to specify a device specific interrupt,\r
+ or negative to specify a processor exception.\r
+ Address 0 must be mapped to SRAM.\r
+ \param [in] IRQn Interrupt number\r
+ \param [in] vector Address of interrupt handler function\r
+ */\r
+__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector)\r
+{\r
+ uint32_t *vectors = (uint32_t *)0x0U;\r
+ vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector;\r
+}\r
+\r
+\r
+/**\r
+ \brief Get Interrupt Vector\r
+ \details Reads an interrupt vector from interrupt vector table.\r
+ The interrupt number can be positive to specify a device specific interrupt,\r
+ or negative to specify a processor exception.\r
+ \param [in] IRQn Interrupt number.\r
+ \return Address of interrupt handler function\r
+ */\r
+__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn)\r
+{\r
+ uint32_t *vectors = (uint32_t *)0x0U;\r
+ return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET];\r
+}\r
+\r
+\r
+/**\r
+ \brief System Reset\r
+ \details Initiates a system reset request to reset the MCU.\r
+ */\r
+__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void)\r
+{\r
+ __DSB(); /* Ensure all outstanding memory accesses included\r
+ buffered write are completed before reset */\r
+ SCB->AIRCR = ((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |\r
+ SCB_AIRCR_SYSRESETREQ_Msk);\r
+ __DSB(); /* Ensure completion of memory access */\r
+\r
+ for(;;) /* wait until reset */\r
+ {\r
+ __NOP();\r
+ }\r
+}\r
+\r
+/*@} end of CMSIS_Core_NVICFunctions */\r
+\r
+\r
+/* ########################## FPU functions #################################### */\r
+/**\r
+ \ingroup CMSIS_Core_FunctionInterface\r
+ \defgroup CMSIS_Core_FpuFunctions FPU Functions\r
+ \brief Function that provides FPU type.\r
+ @{\r
+ */\r
+\r
+/**\r
+ \brief get FPU type\r
+ \details returns the FPU type\r
+ \returns\r
+ - \b 0: No FPU\r
+ - \b 1: Single precision FPU\r
+ - \b 2: Double + Single precision FPU\r
+ */\r
+__STATIC_INLINE uint32_t SCB_GetFPUType(void)\r
+{\r
+ return 0U; /* No FPU */\r
+}\r
+\r
+\r
+/*@} end of CMSIS_Core_FpuFunctions */\r
+\r
+\r
+\r
+/* ################################## SysTick function ############################################ */\r
+/**\r
+ \ingroup CMSIS_Core_FunctionInterface\r
+ \defgroup CMSIS_Core_SysTickFunctions SysTick Functions\r
+ \brief Functions that configure the System.\r
+ @{\r
+ */\r
+\r
+#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U)\r
+\r
+/**\r
+ \brief System Tick Configuration\r
+ \details Initializes the System Timer and its interrupt, and starts the System Tick Timer.\r
+ Counter is in free running mode to generate periodic interrupts.\r
+ \param [in] ticks Number of ticks between two interrupts.\r
+ \return 0 Function succeeded.\r
+ \return 1 Function failed.\r
+ \note When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the\r
+ function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>\r
+ must contain a vendor-specific implementation of this function.\r
+ */\r
+__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)\r
+{\r
+ if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk)\r
+ {\r
+ return (1UL); /* Reload value impossible */\r
+ }\r
+\r
+ SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */\r
+ NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */\r
+ SysTick->VAL = 0UL; /* Load the SysTick Counter Value */\r
+ SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk |\r
+ SysTick_CTRL_TICKINT_Msk |\r
+ SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */\r
+ return (0UL); /* Function successful */\r
+}\r
+\r
+#endif\r
+\r
+/*@} end of CMSIS_Core_SysTickFunctions */\r
+\r
+\r
+\r
+\r
+#ifdef __cplusplus\r
+}\r
+#endif\r
+\r
+#endif /* __CORE_CM0_H_DEPENDANT */\r
+\r
+#endif /* __CMSIS_GENERIC */\r
--- /dev/null
+/**************************************************************************//**\r
+ * @file core_cm0plus.h\r
+ * @brief CMSIS Cortex-M0+ Core Peripheral Access Layer Header File\r
+ * @version V5.0.6\r
+ * @date 28. May 2018\r
+ ******************************************************************************/\r
+/*\r
+ * Copyright (c) 2009-2018 Arm Limited. All rights reserved.\r
+ *\r
+ * SPDX-License-Identifier: Apache-2.0\r
+ *\r
+ * Licensed under the Apache License, Version 2.0 (the License); you may\r
+ * not use this file except in compliance with the License.\r
+ * You may obtain a copy of the License at\r
+ *\r
+ * www.apache.org/licenses/LICENSE-2.0\r
+ *\r
+ * Unless required by applicable law or agreed to in writing, software\r
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT\r
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\r
+ * See the License for the specific language governing permissions and\r
+ * limitations under the License.\r
+ */\r
+\r
+#if defined ( __ICCARM__ )\r
+ #pragma system_include /* treat file as system include file for MISRA check */\r
+#elif defined (__clang__)\r
+ #pragma clang system_header /* treat file as system include file */\r
+#endif\r
+\r
+#ifndef __CORE_CM0PLUS_H_GENERIC\r
+#define __CORE_CM0PLUS_H_GENERIC\r
+\r
+#include <stdint.h>\r
+\r
+#ifdef __cplusplus\r
+ extern "C" {\r
+#endif\r
+\r
+/**\r
+ \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions\r
+ CMSIS violates the following MISRA-C:2004 rules:\r
+\r
+ \li Required Rule 8.5, object/function definition in header file.<br>\r
+ Function definitions in header files are used to allow 'inlining'.\r
+\r
+ \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>\r
+ Unions are used for effective representation of core registers.\r
+\r
+ \li Advisory Rule 19.7, Function-like macro defined.<br>\r
+ Function-like macros are used to allow more efficient code.\r
+ */\r
+\r
+\r
+/*******************************************************************************\r
+ * CMSIS definitions\r
+ ******************************************************************************/\r
+/**\r
+ \ingroup Cortex-M0+\r
+ @{\r
+ */\r
+\r
+#include "cmsis_version.h"\r
+ \r
+/* CMSIS CM0+ definitions */\r
+#define __CM0PLUS_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */\r
+#define __CM0PLUS_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */\r
+#define __CM0PLUS_CMSIS_VERSION ((__CM0PLUS_CMSIS_VERSION_MAIN << 16U) | \\r
+ __CM0PLUS_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */\r
+\r
+#define __CORTEX_M (0U) /*!< Cortex-M Core */\r
+\r
+/** __FPU_USED indicates whether an FPU is used or not.\r
+ This core does not support an FPU at all\r
+*/\r
+#define __FPU_USED 0U\r
+\r
+#if defined ( __CC_ARM )\r
+ #if defined __TARGET_FPU_VFP\r
+ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"\r
+ #endif\r
+\r
+#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)\r
+ #if defined __ARM_PCS_VFP\r
+ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"\r
+ #endif\r
+\r
+#elif defined ( __GNUC__ )\r
+ #if defined (__VFP_FP__) && !defined(__SOFTFP__)\r
+ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"\r
+ #endif\r
+\r
+#elif defined ( __ICCARM__ )\r
+ #if defined __ARMVFP__\r
+ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"\r
+ #endif\r
+\r
+#elif defined ( __TI_ARM__ )\r
+ #if defined __TI_VFP_SUPPORT__\r
+ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"\r
+ #endif\r
+\r
+#elif defined ( __TASKING__ )\r
+ #if defined __FPU_VFP__\r
+ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"\r
+ #endif\r
+\r
+#elif defined ( __CSMC__ )\r
+ #if ( __CSMC__ & 0x400U)\r
+ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"\r
+ #endif\r
+\r
+#endif\r
+\r
+#include "cmsis_compiler.h" /* CMSIS compiler specific defines */\r
+\r
+\r
+#ifdef __cplusplus\r
+}\r
+#endif\r
+\r
+#endif /* __CORE_CM0PLUS_H_GENERIC */\r
+\r
+#ifndef __CMSIS_GENERIC\r
+\r
+#ifndef __CORE_CM0PLUS_H_DEPENDANT\r
+#define __CORE_CM0PLUS_H_DEPENDANT\r
+\r
+#ifdef __cplusplus\r
+ extern "C" {\r
+#endif\r
+\r
+/* check device defines and use defaults */\r
+#if defined __CHECK_DEVICE_DEFINES\r
+ #ifndef __CM0PLUS_REV\r
+ #define __CM0PLUS_REV 0x0000U\r
+ #warning "__CM0PLUS_REV not defined in device header file; using default!"\r
+ #endif\r
+\r
+ #ifndef __MPU_PRESENT\r
+ #define __MPU_PRESENT 0U\r
+ #warning "__MPU_PRESENT not defined in device header file; using default!"\r
+ #endif\r
+\r
+ #ifndef __VTOR_PRESENT\r
+ #define __VTOR_PRESENT 0U\r
+ #warning "__VTOR_PRESENT not defined in device header file; using default!"\r
+ #endif\r
+\r
+ #ifndef __NVIC_PRIO_BITS\r
+ #define __NVIC_PRIO_BITS 2U\r
+ #warning "__NVIC_PRIO_BITS not defined in device header file; using default!"\r
+ #endif\r
+\r
+ #ifndef __Vendor_SysTickConfig\r
+ #define __Vendor_SysTickConfig 0U\r
+ #warning "__Vendor_SysTickConfig not defined in device header file; using default!"\r
+ #endif\r
+#endif\r
+\r
+/* IO definitions (access restrictions to peripheral registers) */\r
+/**\r
+ \defgroup CMSIS_glob_defs CMSIS Global Defines\r
+\r
+ <strong>IO Type Qualifiers</strong> are used\r
+ \li to specify the access to peripheral variables.\r
+ \li for automatic generation of peripheral register debug information.\r
+*/\r
+#ifdef __cplusplus\r
+ #define __I volatile /*!< Defines 'read only' permissions */\r
+#else\r
+ #define __I volatile const /*!< Defines 'read only' permissions */\r
+#endif\r
+#define __O volatile /*!< Defines 'write only' permissions */\r
+#define __IO volatile /*!< Defines 'read / write' permissions */\r
+\r
+/* following defines should be used for structure members */\r
+#define __IM volatile const /*! Defines 'read only' structure member permissions */\r
+#define __OM volatile /*! Defines 'write only' structure member permissions */\r
+#define __IOM volatile /*! Defines 'read / write' structure member permissions */\r
+\r
+/*@} end of group Cortex-M0+ */\r
+\r
+\r
+\r
+/*******************************************************************************\r
+ * Register Abstraction\r
+ Core Register contain:\r
+ - Core Register\r
+ - Core NVIC Register\r
+ - Core SCB Register\r
+ - Core SysTick Register\r
+ - Core MPU Register\r
+ ******************************************************************************/\r
+/**\r
+ \defgroup CMSIS_core_register Defines and Type Definitions\r
+ \brief Type definitions and defines for Cortex-M processor based devices.\r
+*/\r
+\r
+/**\r
+ \ingroup CMSIS_core_register\r
+ \defgroup CMSIS_CORE Status and Control Registers\r
+ \brief Core Register type definitions.\r
+ @{\r
+ */\r
+\r
+/**\r
+ \brief Union type to access the Application Program Status Register (APSR).\r
+ */\r
+typedef union\r
+{\r
+ struct\r
+ {\r
+ uint32_t _reserved0:28; /*!< bit: 0..27 Reserved */\r
+ uint32_t V:1; /*!< bit: 28 Overflow condition code flag */\r
+ uint32_t C:1; /*!< bit: 29 Carry condition code flag */\r
+ uint32_t Z:1; /*!< bit: 30 Zero condition code flag */\r
+ uint32_t N:1; /*!< bit: 31 Negative condition code flag */\r
+ } b; /*!< Structure used for bit access */\r
+ uint32_t w; /*!< Type used for word access */\r
+} APSR_Type;\r
+\r
+/* APSR Register Definitions */\r
+#define APSR_N_Pos 31U /*!< APSR: N Position */\r
+#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */\r
+\r
+#define APSR_Z_Pos 30U /*!< APSR: Z Position */\r
+#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */\r
+\r
+#define APSR_C_Pos 29U /*!< APSR: C Position */\r
+#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */\r
+\r
+#define APSR_V_Pos 28U /*!< APSR: V Position */\r
+#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */\r
+\r
+\r
+/**\r
+ \brief Union type to access the Interrupt Program Status Register (IPSR).\r
+ */\r
+typedef union\r
+{\r
+ struct\r
+ {\r
+ uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */\r
+ uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */\r
+ } b; /*!< Structure used for bit access */\r
+ uint32_t w; /*!< Type used for word access */\r
+} IPSR_Type;\r
+\r
+/* IPSR Register Definitions */\r
+#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */\r
+#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */\r
+\r
+\r
+/**\r
+ \brief Union type to access the Special-Purpose Program Status Registers (xPSR).\r
+ */\r
+typedef union\r
+{\r
+ struct\r
+ {\r
+ uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */\r
+ uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */\r
+ uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */\r
+ uint32_t _reserved1:3; /*!< bit: 25..27 Reserved */\r
+ uint32_t V:1; /*!< bit: 28 Overflow condition code flag */\r
+ uint32_t C:1; /*!< bit: 29 Carry condition code flag */\r
+ uint32_t Z:1; /*!< bit: 30 Zero condition code flag */\r
+ uint32_t N:1; /*!< bit: 31 Negative condition code flag */\r
+ } b; /*!< Structure used for bit access */\r
+ uint32_t w; /*!< Type used for word access */\r
+} xPSR_Type;\r
+\r
+/* xPSR Register Definitions */\r
+#define xPSR_N_Pos 31U /*!< xPSR: N Position */\r
+#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */\r
+\r
+#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */\r
+#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */\r
+\r
+#define xPSR_C_Pos 29U /*!< xPSR: C Position */\r
+#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */\r
+\r
+#define xPSR_V_Pos 28U /*!< xPSR: V Position */\r
+#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */\r
+\r
+#define xPSR_T_Pos 24U /*!< xPSR: T Position */\r
+#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */\r
+\r
+#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */\r
+#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */\r
+\r
+\r
+/**\r
+ \brief Union type to access the Control Registers (CONTROL).\r
+ */\r
+typedef union\r
+{\r
+ struct\r
+ {\r
+ uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */\r
+ uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */\r
+ uint32_t _reserved1:30; /*!< bit: 2..31 Reserved */\r
+ } b; /*!< Structure used for bit access */\r
+ uint32_t w; /*!< Type used for word access */\r
+} CONTROL_Type;\r
+\r
+/* CONTROL Register Definitions */\r
+#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */\r
+#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */\r
+\r
+#define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */\r
+#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */\r
+\r
+/*@} end of group CMSIS_CORE */\r
+\r
+\r
+/**\r
+ \ingroup CMSIS_core_register\r
+ \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC)\r
+ \brief Type definitions for the NVIC Registers\r
+ @{\r
+ */\r
+\r
+/**\r
+ \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC).\r
+ */\r
+typedef struct\r
+{\r
+ __IOM uint32_t ISER[1U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */\r
+ uint32_t RESERVED0[31U];\r
+ __IOM uint32_t ICER[1U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */\r
+ uint32_t RSERVED1[31U];\r
+ __IOM uint32_t ISPR[1U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */\r
+ uint32_t RESERVED2[31U];\r
+ __IOM uint32_t ICPR[1U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */\r
+ uint32_t RESERVED3[31U];\r
+ uint32_t RESERVED4[64U];\r
+ __IOM uint32_t IP[8U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register */\r
+} NVIC_Type;\r
+\r
+/*@} end of group CMSIS_NVIC */\r
+\r
+\r
+/**\r
+ \ingroup CMSIS_core_register\r
+ \defgroup CMSIS_SCB System Control Block (SCB)\r
+ \brief Type definitions for the System Control Block Registers\r
+ @{\r
+ */\r
+\r
+/**\r
+ \brief Structure type to access the System Control Block (SCB).\r
+ */\r
+typedef struct\r
+{\r
+ __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */\r
+ __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */\r
+#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U)\r
+ __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */\r
+#else\r
+ uint32_t RESERVED0;\r
+#endif\r
+ __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */\r
+ __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */\r
+ __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */\r
+ uint32_t RESERVED1;\r
+ __IOM uint32_t SHP[2U]; /*!< Offset: 0x01C (R/W) System Handlers Priority Registers. [0] is RESERVED */\r
+ __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */\r
+} SCB_Type;\r
+\r
+/* SCB CPUID Register Definitions */\r
+#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */\r
+#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */\r
+\r
+#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */\r
+#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */\r
+\r
+#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */\r
+#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */\r
+\r
+#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */\r
+#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */\r
+\r
+#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */\r
+#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */\r
+\r
+/* SCB Interrupt Control State Register Definitions */\r
+#define SCB_ICSR_NMIPENDSET_Pos 31U /*!< SCB ICSR: NMIPENDSET Position */\r
+#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */\r
+\r
+#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */\r
+#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */\r
+\r
+#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */\r
+#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */\r
+\r
+#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */\r
+#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */\r
+\r
+#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */\r
+#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */\r
+\r
+#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */\r
+#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */\r
+\r
+#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */\r
+#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */\r
+\r
+#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */\r
+#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */\r
+\r
+#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */\r
+#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */\r
+\r
+#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U)\r
+/* SCB Interrupt Control State Register Definitions */\r
+#define SCB_VTOR_TBLOFF_Pos 8U /*!< SCB VTOR: TBLOFF Position */\r
+#define SCB_VTOR_TBLOFF_Msk (0xFFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */\r
+#endif\r
+\r
+/* SCB Application Interrupt and Reset Control Register Definitions */\r
+#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */\r
+#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */\r
+\r
+#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */\r
+#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */\r
+\r
+#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */\r
+#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */\r
+\r
+#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */\r
+#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */\r
+\r
+#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */\r
+#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */\r
+\r
+/* SCB System Control Register Definitions */\r
+#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */\r
+#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */\r
+\r
+#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */\r
+#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */\r
+\r
+#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */\r
+#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */\r
+\r
+/* SCB Configuration Control Register Definitions */\r
+#define SCB_CCR_STKALIGN_Pos 9U /*!< SCB CCR: STKALIGN Position */\r
+#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */\r
+\r
+#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */\r
+#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */\r
+\r
+/* SCB System Handler Control and State Register Definitions */\r
+#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */\r
+#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */\r
+\r
+/*@} end of group CMSIS_SCB */\r
+\r
+\r
+/**\r
+ \ingroup CMSIS_core_register\r
+ \defgroup CMSIS_SysTick System Tick Timer (SysTick)\r
+ \brief Type definitions for the System Timer Registers.\r
+ @{\r
+ */\r
+\r
+/**\r
+ \brief Structure type to access the System Timer (SysTick).\r
+ */\r
+typedef struct\r
+{\r
+ __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */\r
+ __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */\r
+ __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */\r
+ __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */\r
+} SysTick_Type;\r
+\r
+/* SysTick Control / Status Register Definitions */\r
+#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */\r
+#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */\r
+\r
+#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */\r
+#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */\r
+\r
+#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */\r
+#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */\r
+\r
+#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */\r
+#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */\r
+\r
+/* SysTick Reload Register Definitions */\r
+#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */\r
+#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */\r
+\r
+/* SysTick Current Register Definitions */\r
+#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */\r
+#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */\r
+\r
+/* SysTick Calibration Register Definitions */\r
+#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */\r
+#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */\r
+\r
+#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */\r
+#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */\r
+\r
+#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */\r
+#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */\r
+\r
+/*@} end of group CMSIS_SysTick */\r
+\r
+#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)\r
+/**\r
+ \ingroup CMSIS_core_register\r
+ \defgroup CMSIS_MPU Memory Protection Unit (MPU)\r
+ \brief Type definitions for the Memory Protection Unit (MPU)\r
+ @{\r
+ */\r
+\r
+/**\r
+ \brief Structure type to access the Memory Protection Unit (MPU).\r
+ */\r
+typedef struct\r
+{\r
+ __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */\r
+ __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */\r
+ __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */\r
+ __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */\r
+ __IOM uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */\r
+} MPU_Type;\r
+\r
+#define MPU_TYPE_RALIASES 1U\r
+\r
+/* MPU Type Register Definitions */\r
+#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */\r
+#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */\r
+\r
+#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */\r
+#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */\r
+\r
+#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */\r
+#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */\r
+\r
+/* MPU Control Register Definitions */\r
+#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */\r
+#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */\r
+\r
+#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */\r
+#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */\r
+\r
+#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */\r
+#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */\r
+\r
+/* MPU Region Number Register Definitions */\r
+#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */\r
+#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */\r
+\r
+/* MPU Region Base Address Register Definitions */\r
+#define MPU_RBAR_ADDR_Pos 8U /*!< MPU RBAR: ADDR Position */\r
+#define MPU_RBAR_ADDR_Msk (0xFFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */\r
+\r
+#define MPU_RBAR_VALID_Pos 4U /*!< MPU RBAR: VALID Position */\r
+#define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */\r
+\r
+#define MPU_RBAR_REGION_Pos 0U /*!< MPU RBAR: REGION Position */\r
+#define MPU_RBAR_REGION_Msk (0xFUL /*<< MPU_RBAR_REGION_Pos*/) /*!< MPU RBAR: REGION Mask */\r
+\r
+/* MPU Region Attribute and Size Register Definitions */\r
+#define MPU_RASR_ATTRS_Pos 16U /*!< MPU RASR: MPU Region Attribute field Position */\r
+#define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */\r
+\r
+#define MPU_RASR_XN_Pos 28U /*!< MPU RASR: ATTRS.XN Position */\r
+#define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */\r
+\r
+#define MPU_RASR_AP_Pos 24U /*!< MPU RASR: ATTRS.AP Position */\r
+#define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */\r
+\r
+#define MPU_RASR_TEX_Pos 19U /*!< MPU RASR: ATTRS.TEX Position */\r
+#define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */\r
+\r
+#define MPU_RASR_S_Pos 18U /*!< MPU RASR: ATTRS.S Position */\r
+#define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */\r
+\r
+#define MPU_RASR_C_Pos 17U /*!< MPU RASR: ATTRS.C Position */\r
+#define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */\r
+\r
+#define MPU_RASR_B_Pos 16U /*!< MPU RASR: ATTRS.B Position */\r
+#define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */\r
+\r
+#define MPU_RASR_SRD_Pos 8U /*!< MPU RASR: Sub-Region Disable Position */\r
+#define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */\r
+\r
+#define MPU_RASR_SIZE_Pos 1U /*!< MPU RASR: Region Size Field Position */\r
+#define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */\r
+\r
+#define MPU_RASR_ENABLE_Pos 0U /*!< MPU RASR: Region enable bit Position */\r
+#define MPU_RASR_ENABLE_Msk (1UL /*<< MPU_RASR_ENABLE_Pos*/) /*!< MPU RASR: Region enable bit Disable Mask */\r
+\r
+/*@} end of group CMSIS_MPU */\r
+#endif\r
+\r
+\r
+/**\r
+ \ingroup CMSIS_core_register\r
+ \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug)\r
+ \brief Cortex-M0+ Core Debug Registers (DCB registers, SHCSR, and DFSR) are only accessible over DAP and not via processor.\r
+ Therefore they are not covered by the Cortex-M0+ header file.\r
+ @{\r
+ */\r
+/*@} end of group CMSIS_CoreDebug */\r
+\r
+\r
+/**\r
+ \ingroup CMSIS_core_register\r
+ \defgroup CMSIS_core_bitfield Core register bit field macros\r
+ \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk).\r
+ @{\r
+ */\r
+\r
+/**\r
+ \brief Mask and shift a bit field value for use in a register bit range.\r
+ \param[in] field Name of the register bit field.\r
+ \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type.\r
+ \return Masked and shifted value.\r
+*/\r
+#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk)\r
+\r
+/**\r
+ \brief Mask and shift a register value to extract a bit filed value.\r
+ \param[in] field Name of the register bit field.\r
+ \param[in] value Value of register. This parameter is interpreted as an uint32_t type.\r
+ \return Masked and shifted bit field value.\r
+*/\r
+#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos)\r
+\r
+/*@} end of group CMSIS_core_bitfield */\r
+\r
+\r
+/**\r
+ \ingroup CMSIS_core_register\r
+ \defgroup CMSIS_core_base Core Definitions\r
+ \brief Definitions for base addresses, unions, and structures.\r
+ @{\r
+ */\r
+\r
+/* Memory mapping of Core Hardware */\r
+#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */\r
+#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */\r
+#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */\r
+#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */\r
+\r
+#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */\r
+#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */\r
+#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */\r
+\r
+#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)\r
+ #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */\r
+ #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */\r
+#endif\r
+\r
+/*@} */\r
+\r
+\r
+\r
+/*******************************************************************************\r
+ * Hardware Abstraction Layer\r
+ Core Function Interface contains:\r
+ - Core NVIC Functions\r
+ - Core SysTick Functions\r
+ - Core Register Access Functions\r
+ ******************************************************************************/\r
+/**\r
+ \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference\r
+*/\r
+\r
+\r
+\r
+/* ########################## NVIC functions #################################### */\r
+/**\r
+ \ingroup CMSIS_Core_FunctionInterface\r
+ \defgroup CMSIS_Core_NVICFunctions NVIC Functions\r
+ \brief Functions that manage interrupts and exceptions via the NVIC.\r
+ @{\r
+ */\r
+\r
+#ifdef CMSIS_NVIC_VIRTUAL\r
+ #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE\r
+ #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h"\r
+ #endif\r
+ #include CMSIS_NVIC_VIRTUAL_HEADER_FILE\r
+#else\r
+ #define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping\r
+ #define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping\r
+ #define NVIC_EnableIRQ __NVIC_EnableIRQ\r
+ #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ\r
+ #define NVIC_DisableIRQ __NVIC_DisableIRQ\r
+ #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ\r
+ #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ\r
+ #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ\r
+/*#define NVIC_GetActive __NVIC_GetActive not available for Cortex-M0+ */\r
+ #define NVIC_SetPriority __NVIC_SetPriority\r
+ #define NVIC_GetPriority __NVIC_GetPriority\r
+ #define NVIC_SystemReset __NVIC_SystemReset\r
+#endif /* CMSIS_NVIC_VIRTUAL */\r
+\r
+#ifdef CMSIS_VECTAB_VIRTUAL\r
+ #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE\r
+ #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h"\r
+ #endif\r
+ #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE\r
+#else\r
+ #define NVIC_SetVector __NVIC_SetVector\r
+ #define NVIC_GetVector __NVIC_GetVector\r
+#endif /* (CMSIS_VECTAB_VIRTUAL) */\r
+\r
+#define NVIC_USER_IRQ_OFFSET 16\r
+\r
+\r
+/* The following EXC_RETURN values are saved the LR on exception entry */\r
+#define EXC_RETURN_HANDLER (0xFFFFFFF1UL) /* return to Handler mode, uses MSP after return */\r
+#define EXC_RETURN_THREAD_MSP (0xFFFFFFF9UL) /* return to Thread mode, uses MSP after return */\r
+#define EXC_RETURN_THREAD_PSP (0xFFFFFFFDUL) /* return to Thread mode, uses PSP after return */\r
+\r
+\r
+/* Interrupt Priorities are WORD accessible only under Armv6-M */\r
+/* The following MACROS handle generation of the register offset and byte masks */\r
+#define _BIT_SHIFT(IRQn) ( ((((uint32_t)(int32_t)(IRQn)) ) & 0x03UL) * 8UL)\r
+#define _SHP_IDX(IRQn) ( (((((uint32_t)(int32_t)(IRQn)) & 0x0FUL)-8UL) >> 2UL) )\r
+#define _IP_IDX(IRQn) ( (((uint32_t)(int32_t)(IRQn)) >> 2UL) )\r
+\r
+#define __NVIC_SetPriorityGrouping(X) (void)(X)\r
+#define __NVIC_GetPriorityGrouping() (0U)\r
+\r
+/**\r
+ \brief Enable Interrupt\r
+ \details Enables a device specific interrupt in the NVIC interrupt controller.\r
+ \param [in] IRQn Device specific interrupt number.\r
+ \note IRQn must not be negative.\r
+ */\r
+__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn)\r
+{\r
+ if ((int32_t)(IRQn) >= 0)\r
+ {\r
+ NVIC->ISER[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));\r
+ }\r
+}\r
+\r
+\r
+/**\r
+ \brief Get Interrupt Enable status\r
+ \details Returns a device specific interrupt enable status from the NVIC interrupt controller.\r
+ \param [in] IRQn Device specific interrupt number.\r
+ \return 0 Interrupt is not enabled.\r
+ \return 1 Interrupt is enabled.\r
+ \note IRQn must not be negative.\r
+ */\r
+__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn)\r
+{\r
+ if ((int32_t)(IRQn) >= 0)\r
+ {\r
+ return((uint32_t)(((NVIC->ISER[0U] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));\r
+ }\r
+ else\r
+ {\r
+ return(0U);\r
+ }\r
+}\r
+\r
+\r
+/**\r
+ \brief Disable Interrupt\r
+ \details Disables a device specific interrupt in the NVIC interrupt controller.\r
+ \param [in] IRQn Device specific interrupt number.\r
+ \note IRQn must not be negative.\r
+ */\r
+__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn)\r
+{\r
+ if ((int32_t)(IRQn) >= 0)\r
+ {\r
+ NVIC->ICER[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));\r
+ __DSB();\r
+ __ISB();\r
+ }\r
+}\r
+\r
+\r
+/**\r
+ \brief Get Pending Interrupt\r
+ \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt.\r
+ \param [in] IRQn Device specific interrupt number.\r
+ \return 0 Interrupt status is not pending.\r
+ \return 1 Interrupt status is pending.\r
+ \note IRQn must not be negative.\r
+ */\r
+__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn)\r
+{\r
+ if ((int32_t)(IRQn) >= 0)\r
+ {\r
+ return((uint32_t)(((NVIC->ISPR[0U] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));\r
+ }\r
+ else\r
+ {\r
+ return(0U);\r
+ }\r
+}\r
+\r
+\r
+/**\r
+ \brief Set Pending Interrupt\r
+ \details Sets the pending bit of a device specific interrupt in the NVIC pending register.\r
+ \param [in] IRQn Device specific interrupt number.\r
+ \note IRQn must not be negative.\r
+ */\r
+__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn)\r
+{\r
+ if ((int32_t)(IRQn) >= 0)\r
+ {\r
+ NVIC->ISPR[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));\r
+ }\r
+}\r
+\r
+\r
+/**\r
+ \brief Clear Pending Interrupt\r
+ \details Clears the pending bit of a device specific interrupt in the NVIC pending register.\r
+ \param [in] IRQn Device specific interrupt number.\r
+ \note IRQn must not be negative.\r
+ */\r
+__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn)\r
+{\r
+ if ((int32_t)(IRQn) >= 0)\r
+ {\r
+ NVIC->ICPR[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));\r
+ }\r
+}\r
+\r
+\r
+/**\r
+ \brief Set Interrupt Priority\r
+ \details Sets the priority of a device specific interrupt or a processor exception.\r
+ The interrupt number can be positive to specify a device specific interrupt,\r
+ or negative to specify a processor exception.\r
+ \param [in] IRQn Interrupt number.\r
+ \param [in] priority Priority to set.\r
+ \note The priority cannot be set for every processor exception.\r
+ */\r
+__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)\r
+{\r
+ if ((int32_t)(IRQn) >= 0)\r
+ {\r
+ NVIC->IP[_IP_IDX(IRQn)] = ((uint32_t)(NVIC->IP[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |\r
+ (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));\r
+ }\r
+ else\r
+ {\r
+ SCB->SHP[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |\r
+ (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));\r
+ }\r
+}\r
+\r
+\r
+/**\r
+ \brief Get Interrupt Priority\r
+ \details Reads the priority of a device specific interrupt or a processor exception.\r
+ The interrupt number can be positive to specify a device specific interrupt,\r
+ or negative to specify a processor exception.\r
+ \param [in] IRQn Interrupt number.\r
+ \return Interrupt Priority.\r
+ Value is aligned automatically to the implemented priority bits of the microcontroller.\r
+ */\r
+__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn)\r
+{\r
+\r
+ if ((int32_t)(IRQn) >= 0)\r
+ {\r
+ return((uint32_t)(((NVIC->IP[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));\r
+ }\r
+ else\r
+ {\r
+ return((uint32_t)(((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));\r
+ }\r
+}\r
+\r
+\r
+/**\r
+ \brief Encode Priority\r
+ \details Encodes the priority for an interrupt with the given priority group,\r
+ preemptive priority value, and subpriority value.\r
+ In case of a conflict between priority grouping and available\r
+ priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.\r
+ \param [in] PriorityGroup Used priority group.\r
+ \param [in] PreemptPriority Preemptive priority value (starting from 0).\r
+ \param [in] SubPriority Subpriority value (starting from 0).\r
+ \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority().\r
+ */\r
+__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)\r
+{\r
+ uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */\r
+ uint32_t PreemptPriorityBits;\r
+ uint32_t SubPriorityBits;\r
+\r
+ PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);\r
+ SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));\r
+\r
+ return (\r
+ ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) |\r
+ ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL)))\r
+ );\r
+}\r
+\r
+\r
+/**\r
+ \brief Decode Priority\r
+ \details Decodes an interrupt priority value with a given priority group to\r
+ preemptive priority value and subpriority value.\r
+ In case of a conflict between priority grouping and available\r
+ priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set.\r
+ \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority().\r
+ \param [in] PriorityGroup Used priority group.\r
+ \param [out] pPreemptPriority Preemptive priority value (starting from 0).\r
+ \param [out] pSubPriority Subpriority value (starting from 0).\r
+ */\r
+__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority)\r
+{\r
+ uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */\r
+ uint32_t PreemptPriorityBits;\r
+ uint32_t SubPriorityBits;\r
+\r
+ PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);\r
+ SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));\r
+\r
+ *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL);\r
+ *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL);\r
+}\r
+\r
+\r
+/**\r
+ \brief Set Interrupt Vector\r
+ \details Sets an interrupt vector in SRAM based interrupt vector table.\r
+ The interrupt number can be positive to specify a device specific interrupt,\r
+ or negative to specify a processor exception.\r
+ VTOR must been relocated to SRAM before.\r
+ If VTOR is not present address 0 must be mapped to SRAM.\r
+ \param [in] IRQn Interrupt number\r
+ \param [in] vector Address of interrupt handler function\r
+ */\r
+__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector)\r
+{\r
+#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U)\r
+ uint32_t *vectors = (uint32_t *)SCB->VTOR;\r
+#else\r
+ uint32_t *vectors = (uint32_t *)0x0U;\r
+#endif\r
+ vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector;\r
+}\r
+\r
+\r
+/**\r
+ \brief Get Interrupt Vector\r
+ \details Reads an interrupt vector from interrupt vector table.\r
+ The interrupt number can be positive to specify a device specific interrupt,\r
+ or negative to specify a processor exception.\r
+ \param [in] IRQn Interrupt number.\r
+ \return Address of interrupt handler function\r
+ */\r
+__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn)\r
+{\r
+#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U)\r
+ uint32_t *vectors = (uint32_t *)SCB->VTOR;\r
+#else\r
+ uint32_t *vectors = (uint32_t *)0x0U;\r
+#endif\r
+ return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET];\r
+\r
+}\r
+\r
+\r
+/**\r
+ \brief System Reset\r
+ \details Initiates a system reset request to reset the MCU.\r
+ */\r
+__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void)\r
+{\r
+ __DSB(); /* Ensure all outstanding memory accesses included\r
+ buffered write are completed before reset */\r
+ SCB->AIRCR = ((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |\r
+ SCB_AIRCR_SYSRESETREQ_Msk);\r
+ __DSB(); /* Ensure completion of memory access */\r
+\r
+ for(;;) /* wait until reset */\r
+ {\r
+ __NOP();\r
+ }\r
+}\r
+\r
+/*@} end of CMSIS_Core_NVICFunctions */\r
+\r
+/* ########################## MPU functions #################################### */\r
+\r
+#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)\r
+\r
+#include "mpu_armv7.h"\r
+\r
+#endif\r
+\r
+/* ########################## FPU functions #################################### */\r
+/**\r
+ \ingroup CMSIS_Core_FunctionInterface\r
+ \defgroup CMSIS_Core_FpuFunctions FPU Functions\r
+ \brief Function that provides FPU type.\r
+ @{\r
+ */\r
+\r
+/**\r
+ \brief get FPU type\r
+ \details returns the FPU type\r
+ \returns\r
+ - \b 0: No FPU\r
+ - \b 1: Single precision FPU\r
+ - \b 2: Double + Single precision FPU\r
+ */\r
+__STATIC_INLINE uint32_t SCB_GetFPUType(void)\r
+{\r
+ return 0U; /* No FPU */\r
+}\r
+\r
+\r
+/*@} end of CMSIS_Core_FpuFunctions */\r
+\r
+\r
+\r
+/* ################################## SysTick function ############################################ */\r
+/**\r
+ \ingroup CMSIS_Core_FunctionInterface\r
+ \defgroup CMSIS_Core_SysTickFunctions SysTick Functions\r
+ \brief Functions that configure the System.\r
+ @{\r
+ */\r
+\r
+#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U)\r
+\r
+/**\r
+ \brief System Tick Configuration\r
+ \details Initializes the System Timer and its interrupt, and starts the System Tick Timer.\r
+ Counter is in free running mode to generate periodic interrupts.\r
+ \param [in] ticks Number of ticks between two interrupts.\r
+ \return 0 Function succeeded.\r
+ \return 1 Function failed.\r
+ \note When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the\r
+ function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>\r
+ must contain a vendor-specific implementation of this function.\r
+ */\r
+__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)\r
+{\r
+ if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk)\r
+ {\r
+ return (1UL); /* Reload value impossible */\r
+ }\r
+\r
+ SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */\r
+ NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */\r
+ SysTick->VAL = 0UL; /* Load the SysTick Counter Value */\r
+ SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk |\r
+ SysTick_CTRL_TICKINT_Msk |\r
+ SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */\r
+ return (0UL); /* Function successful */\r
+}\r
+\r
+#endif\r
+\r
+/*@} end of CMSIS_Core_SysTickFunctions */\r
+\r
+\r
+\r
+\r
+#ifdef __cplusplus\r
+}\r
+#endif\r
+\r
+#endif /* __CORE_CM0PLUS_H_DEPENDANT */\r
+\r
+#endif /* __CMSIS_GENERIC */\r
--- /dev/null
+/**************************************************************************//**\r
+ * @file core_cm1.h\r
+ * @brief CMSIS Cortex-M1 Core Peripheral Access Layer Header File\r
+ * @version V1.0.0\r
+ * @date 23. July 2018\r
+ ******************************************************************************/\r
+/*\r
+ * Copyright (c) 2009-2018 Arm Limited. All rights reserved.\r
+ *\r
+ * SPDX-License-Identifier: Apache-2.0\r
+ *\r
+ * Licensed under the Apache License, Version 2.0 (the License); you may\r
+ * not use this file except in compliance with the License.\r
+ * You may obtain a copy of the License at\r
+ *\r
+ * www.apache.org/licenses/LICENSE-2.0\r
+ *\r
+ * Unless required by applicable law or agreed to in writing, software\r
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT\r
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\r
+ * See the License for the specific language governing permissions and\r
+ * limitations under the License.\r
+ */\r
+\r
+#if defined ( __ICCARM__ )\r
+ #pragma system_include /* treat file as system include file for MISRA check */\r
+#elif defined (__clang__)\r
+ #pragma clang system_header /* treat file as system include file */\r
+#endif\r
+\r
+#ifndef __CORE_CM1_H_GENERIC\r
+#define __CORE_CM1_H_GENERIC\r
+\r
+#include <stdint.h>\r
+\r
+#ifdef __cplusplus\r
+ extern "C" {\r
+#endif\r
+\r
+/**\r
+ \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions\r
+ CMSIS violates the following MISRA-C:2004 rules:\r
+\r
+ \li Required Rule 8.5, object/function definition in header file.<br>\r
+ Function definitions in header files are used to allow 'inlining'.\r
+\r
+ \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>\r
+ Unions are used for effective representation of core registers.\r
+\r
+ \li Advisory Rule 19.7, Function-like macro defined.<br>\r
+ Function-like macros are used to allow more efficient code.\r
+ */\r
+\r
+\r
+/*******************************************************************************\r
+ * CMSIS definitions\r
+ ******************************************************************************/\r
+/**\r
+ \ingroup Cortex_M1\r
+ @{\r
+ */\r
+\r
+#include "cmsis_version.h"\r
+ \r
+/* CMSIS CM1 definitions */\r
+#define __CM1_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */\r
+#define __CM1_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */\r
+#define __CM1_CMSIS_VERSION ((__CM1_CMSIS_VERSION_MAIN << 16U) | \\r
+ __CM1_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */\r
+\r
+#define __CORTEX_M (1U) /*!< Cortex-M Core */\r
+\r
+/** __FPU_USED indicates whether an FPU is used or not.\r
+ This core does not support an FPU at all\r
+*/\r
+#define __FPU_USED 0U\r
+\r
+#if defined ( __CC_ARM )\r
+ #if defined __TARGET_FPU_VFP\r
+ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"\r
+ #endif\r
+\r
+#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)\r
+ #if defined __ARM_PCS_VFP\r
+ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"\r
+ #endif\r
+\r
+#elif defined ( __GNUC__ )\r
+ #if defined (__VFP_FP__) && !defined(__SOFTFP__)\r
+ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"\r
+ #endif\r
+\r
+#elif defined ( __ICCARM__ )\r
+ #if defined __ARMVFP__\r
+ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"\r
+ #endif\r
+\r
+#elif defined ( __TI_ARM__ )\r
+ #if defined __TI_VFP_SUPPORT__\r
+ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"\r
+ #endif\r
+\r
+#elif defined ( __TASKING__ )\r
+ #if defined __FPU_VFP__\r
+ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"\r
+ #endif\r
+\r
+#elif defined ( __CSMC__ )\r
+ #if ( __CSMC__ & 0x400U)\r
+ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"\r
+ #endif\r
+\r
+#endif\r
+\r
+#include "cmsis_compiler.h" /* CMSIS compiler specific defines */\r
+\r
+\r
+#ifdef __cplusplus\r
+}\r
+#endif\r
+\r
+#endif /* __CORE_CM1_H_GENERIC */\r
+\r
+#ifndef __CMSIS_GENERIC\r
+\r
+#ifndef __CORE_CM1_H_DEPENDANT\r
+#define __CORE_CM1_H_DEPENDANT\r
+\r
+#ifdef __cplusplus\r
+ extern "C" {\r
+#endif\r
+\r
+/* check device defines and use defaults */\r
+#if defined __CHECK_DEVICE_DEFINES\r
+ #ifndef __CM1_REV\r
+ #define __CM1_REV 0x0100U\r
+ #warning "__CM1_REV not defined in device header file; using default!"\r
+ #endif\r
+\r
+ #ifndef __NVIC_PRIO_BITS\r
+ #define __NVIC_PRIO_BITS 2U\r
+ #warning "__NVIC_PRIO_BITS not defined in device header file; using default!"\r
+ #endif\r
+\r
+ #ifndef __Vendor_SysTickConfig\r
+ #define __Vendor_SysTickConfig 0U\r
+ #warning "__Vendor_SysTickConfig not defined in device header file; using default!"\r
+ #endif\r
+#endif\r
+\r
+/* IO definitions (access restrictions to peripheral registers) */\r
+/**\r
+ \defgroup CMSIS_glob_defs CMSIS Global Defines\r
+\r
+ <strong>IO Type Qualifiers</strong> are used\r
+ \li to specify the access to peripheral variables.\r
+ \li for automatic generation of peripheral register debug information.\r
+*/\r
+#ifdef __cplusplus\r
+ #define __I volatile /*!< Defines 'read only' permissions */\r
+#else\r
+ #define __I volatile const /*!< Defines 'read only' permissions */\r
+#endif\r
+#define __O volatile /*!< Defines 'write only' permissions */\r
+#define __IO volatile /*!< Defines 'read / write' permissions */\r
+\r
+/* following defines should be used for structure members */\r
+#define __IM volatile const /*! Defines 'read only' structure member permissions */\r
+#define __OM volatile /*! Defines 'write only' structure member permissions */\r
+#define __IOM volatile /*! Defines 'read / write' structure member permissions */\r
+\r
+/*@} end of group Cortex_M1 */\r
+\r
+\r
+\r
+/*******************************************************************************\r
+ * Register Abstraction\r
+ Core Register contain:\r
+ - Core Register\r
+ - Core NVIC Register\r
+ - Core SCB Register\r
+ - Core SysTick Register\r
+ ******************************************************************************/\r
+/**\r
+ \defgroup CMSIS_core_register Defines and Type Definitions\r
+ \brief Type definitions and defines for Cortex-M processor based devices.\r
+*/\r
+\r
+/**\r
+ \ingroup CMSIS_core_register\r
+ \defgroup CMSIS_CORE Status and Control Registers\r
+ \brief Core Register type definitions.\r
+ @{\r
+ */\r
+\r
+/**\r
+ \brief Union type to access the Application Program Status Register (APSR).\r
+ */\r
+typedef union\r
+{\r
+ struct\r
+ {\r
+ uint32_t _reserved0:28; /*!< bit: 0..27 Reserved */\r
+ uint32_t V:1; /*!< bit: 28 Overflow condition code flag */\r
+ uint32_t C:1; /*!< bit: 29 Carry condition code flag */\r
+ uint32_t Z:1; /*!< bit: 30 Zero condition code flag */\r
+ uint32_t N:1; /*!< bit: 31 Negative condition code flag */\r
+ } b; /*!< Structure used for bit access */\r
+ uint32_t w; /*!< Type used for word access */\r
+} APSR_Type;\r
+\r
+/* APSR Register Definitions */\r
+#define APSR_N_Pos 31U /*!< APSR: N Position */\r
+#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */\r
+\r
+#define APSR_Z_Pos 30U /*!< APSR: Z Position */\r
+#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */\r
+\r
+#define APSR_C_Pos 29U /*!< APSR: C Position */\r
+#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */\r
+\r
+#define APSR_V_Pos 28U /*!< APSR: V Position */\r
+#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */\r
+\r
+\r
+/**\r
+ \brief Union type to access the Interrupt Program Status Register (IPSR).\r
+ */\r
+typedef union\r
+{\r
+ struct\r
+ {\r
+ uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */\r
+ uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */\r
+ } b; /*!< Structure used for bit access */\r
+ uint32_t w; /*!< Type used for word access */\r
+} IPSR_Type;\r
+\r
+/* IPSR Register Definitions */\r
+#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */\r
+#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */\r
+\r
+\r
+/**\r
+ \brief Union type to access the Special-Purpose Program Status Registers (xPSR).\r
+ */\r
+typedef union\r
+{\r
+ struct\r
+ {\r
+ uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */\r
+ uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */\r
+ uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */\r
+ uint32_t _reserved1:3; /*!< bit: 25..27 Reserved */\r
+ uint32_t V:1; /*!< bit: 28 Overflow condition code flag */\r
+ uint32_t C:1; /*!< bit: 29 Carry condition code flag */\r
+ uint32_t Z:1; /*!< bit: 30 Zero condition code flag */\r
+ uint32_t N:1; /*!< bit: 31 Negative condition code flag */\r
+ } b; /*!< Structure used for bit access */\r
+ uint32_t w; /*!< Type used for word access */\r
+} xPSR_Type;\r
+\r
+/* xPSR Register Definitions */\r
+#define xPSR_N_Pos 31U /*!< xPSR: N Position */\r
+#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */\r
+\r
+#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */\r
+#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */\r
+\r
+#define xPSR_C_Pos 29U /*!< xPSR: C Position */\r
+#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */\r
+\r
+#define xPSR_V_Pos 28U /*!< xPSR: V Position */\r
+#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */\r
+\r
+#define xPSR_T_Pos 24U /*!< xPSR: T Position */\r
+#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */\r
+\r
+#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */\r
+#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */\r
+\r
+\r
+/**\r
+ \brief Union type to access the Control Registers (CONTROL).\r
+ */\r
+typedef union\r
+{\r
+ struct\r
+ {\r
+ uint32_t _reserved0:1; /*!< bit: 0 Reserved */\r
+ uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */\r
+ uint32_t _reserved1:30; /*!< bit: 2..31 Reserved */\r
+ } b; /*!< Structure used for bit access */\r
+ uint32_t w; /*!< Type used for word access */\r
+} CONTROL_Type;\r
+\r
+/* CONTROL Register Definitions */\r
+#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */\r
+#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */\r
+\r
+/*@} end of group CMSIS_CORE */\r
+\r
+\r
+/**\r
+ \ingroup CMSIS_core_register\r
+ \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC)\r
+ \brief Type definitions for the NVIC Registers\r
+ @{\r
+ */\r
+\r
+/**\r
+ \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC).\r
+ */\r
+typedef struct\r
+{\r
+ __IOM uint32_t ISER[1U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */\r
+ uint32_t RESERVED0[31U];\r
+ __IOM uint32_t ICER[1U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */\r
+ uint32_t RSERVED1[31U];\r
+ __IOM uint32_t ISPR[1U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */\r
+ uint32_t RESERVED2[31U];\r
+ __IOM uint32_t ICPR[1U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */\r
+ uint32_t RESERVED3[31U];\r
+ uint32_t RESERVED4[64U];\r
+ __IOM uint32_t IP[8U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register */\r
+} NVIC_Type;\r
+\r
+/*@} end of group CMSIS_NVIC */\r
+\r
+\r
+/**\r
+ \ingroup CMSIS_core_register\r
+ \defgroup CMSIS_SCB System Control Block (SCB)\r
+ \brief Type definitions for the System Control Block Registers\r
+ @{\r
+ */\r
+\r
+/**\r
+ \brief Structure type to access the System Control Block (SCB).\r
+ */\r
+typedef struct\r
+{\r
+ __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */\r
+ __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */\r
+ uint32_t RESERVED0;\r
+ __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */\r
+ __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */\r
+ __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */\r
+ uint32_t RESERVED1;\r
+ __IOM uint32_t SHP[2U]; /*!< Offset: 0x01C (R/W) System Handlers Priority Registers. [0] is RESERVED */\r
+ __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */\r
+} SCB_Type;\r
+\r
+/* SCB CPUID Register Definitions */\r
+#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */\r
+#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */\r
+\r
+#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */\r
+#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */\r
+\r
+#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */\r
+#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */\r
+\r
+#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */\r
+#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */\r
+\r
+#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */\r
+#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */\r
+\r
+/* SCB Interrupt Control State Register Definitions */\r
+#define SCB_ICSR_NMIPENDSET_Pos 31U /*!< SCB ICSR: NMIPENDSET Position */\r
+#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */\r
+\r
+#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */\r
+#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */\r
+\r
+#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */\r
+#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */\r
+\r
+#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */\r
+#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */\r
+\r
+#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */\r
+#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */\r
+\r
+#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */\r
+#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */\r
+\r
+#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */\r
+#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */\r
+\r
+#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */\r
+#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */\r
+\r
+#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */\r
+#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */\r
+\r
+/* SCB Application Interrupt and Reset Control Register Definitions */\r
+#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */\r
+#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */\r
+\r
+#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */\r
+#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */\r
+\r
+#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */\r
+#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */\r
+\r
+#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */\r
+#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */\r
+\r
+#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */\r
+#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */\r
+\r
+/* SCB System Control Register Definitions */\r
+#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */\r
+#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */\r
+\r
+#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */\r
+#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */\r
+\r
+#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */\r
+#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */\r
+\r
+/* SCB Configuration Control Register Definitions */\r
+#define SCB_CCR_STKALIGN_Pos 9U /*!< SCB CCR: STKALIGN Position */\r
+#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */\r
+\r
+#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */\r
+#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */\r
+\r
+/* SCB System Handler Control and State Register Definitions */\r
+#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */\r
+#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */\r
+\r
+/*@} end of group CMSIS_SCB */\r
+\r
+\r
+/**\r
+ \ingroup CMSIS_core_register\r
+ \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB)\r
+ \brief Type definitions for the System Control and ID Register not in the SCB\r
+ @{\r
+ */\r
+\r
+/**\r
+ \brief Structure type to access the System Control and ID Register not in the SCB.\r
+ */\r
+typedef struct\r
+{\r
+ uint32_t RESERVED0[2U];\r
+ __IOM uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */\r
+} SCnSCB_Type;\r
+\r
+/* Auxiliary Control Register Definitions */\r
+#define SCnSCB_ACTLR_ITCMUAEN_Pos 4U /*!< ACTLR: Instruction TCM Upper Alias Enable Position */\r
+#define SCnSCB_ACTLR_ITCMUAEN_Msk (1UL << SCnSCB_ACTLR_ITCMUAEN_Pos) /*!< ACTLR: Instruction TCM Upper Alias Enable Mask */\r
+\r
+#define SCnSCB_ACTLR_ITCMLAEN_Pos 3U /*!< ACTLR: Instruction TCM Lower Alias Enable Position */\r
+#define SCnSCB_ACTLR_ITCMLAEN_Msk (1UL << SCnSCB_ACTLR_ITCMLAEN_Pos) /*!< ACTLR: Instruction TCM Lower Alias Enable Mask */\r
+\r
+/*@} end of group CMSIS_SCnotSCB */\r
+\r
+\r
+/**\r
+ \ingroup CMSIS_core_register\r
+ \defgroup CMSIS_SysTick System Tick Timer (SysTick)\r
+ \brief Type definitions for the System Timer Registers.\r
+ @{\r
+ */\r
+\r
+/**\r
+ \brief Structure type to access the System Timer (SysTick).\r
+ */\r
+typedef struct\r
+{\r
+ __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */\r
+ __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */\r
+ __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */\r
+ __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */\r
+} SysTick_Type;\r
+\r
+/* SysTick Control / Status Register Definitions */\r
+#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */\r
+#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */\r
+\r
+#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */\r
+#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */\r
+\r
+#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */\r
+#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */\r
+\r
+#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */\r
+#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */\r
+\r
+/* SysTick Reload Register Definitions */\r
+#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */\r
+#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */\r
+\r
+/* SysTick Current Register Definitions */\r
+#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */\r
+#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */\r
+\r
+/* SysTick Calibration Register Definitions */\r
+#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */\r
+#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */\r
+\r
+#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */\r
+#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */\r
+\r
+#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */\r
+#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */\r
+\r
+/*@} end of group CMSIS_SysTick */\r
+\r
+\r
+/**\r
+ \ingroup CMSIS_core_register\r
+ \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug)\r
+ \brief Cortex-M1 Core Debug Registers (DCB registers, SHCSR, and DFSR) are only accessible over DAP and not via processor.\r
+ Therefore they are not covered by the Cortex-M1 header file.\r
+ @{\r
+ */\r
+/*@} end of group CMSIS_CoreDebug */\r
+\r
+\r
+/**\r
+ \ingroup CMSIS_core_register\r
+ \defgroup CMSIS_core_bitfield Core register bit field macros\r
+ \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk).\r
+ @{\r
+ */\r
+\r
+/**\r
+ \brief Mask and shift a bit field value for use in a register bit range.\r
+ \param[in] field Name of the register bit field.\r
+ \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type.\r
+ \return Masked and shifted value.\r
+*/\r
+#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk)\r
+\r
+/**\r
+ \brief Mask and shift a register value to extract a bit filed value.\r
+ \param[in] field Name of the register bit field.\r
+ \param[in] value Value of register. This parameter is interpreted as an uint32_t type.\r
+ \return Masked and shifted bit field value.\r
+*/\r
+#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos)\r
+\r
+/*@} end of group CMSIS_core_bitfield */\r
+\r
+\r
+/**\r
+ \ingroup CMSIS_core_register\r
+ \defgroup CMSIS_core_base Core Definitions\r
+ \brief Definitions for base addresses, unions, and structures.\r
+ @{\r
+ */\r
+\r
+/* Memory mapping of Core Hardware */\r
+#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */\r
+#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */\r
+#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */\r
+#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */\r
+\r
+#define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */\r
+#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */\r
+#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */\r
+#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */\r
+\r
+\r
+/*@} */\r
+\r
+\r
+\r
+/*******************************************************************************\r
+ * Hardware Abstraction Layer\r
+ Core Function Interface contains:\r
+ - Core NVIC Functions\r
+ - Core SysTick Functions\r
+ - Core Register Access Functions\r
+ ******************************************************************************/\r
+/**\r
+ \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference\r
+*/\r
+\r
+\r
+\r
+/* ########################## NVIC functions #################################### */\r
+/**\r
+ \ingroup CMSIS_Core_FunctionInterface\r
+ \defgroup CMSIS_Core_NVICFunctions NVIC Functions\r
+ \brief Functions that manage interrupts and exceptions via the NVIC.\r
+ @{\r
+ */\r
+\r
+#ifdef CMSIS_NVIC_VIRTUAL\r
+ #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE\r
+ #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h"\r
+ #endif\r
+ #include CMSIS_NVIC_VIRTUAL_HEADER_FILE\r
+#else\r
+ #define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping\r
+ #define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping\r
+ #define NVIC_EnableIRQ __NVIC_EnableIRQ\r
+ #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ\r
+ #define NVIC_DisableIRQ __NVIC_DisableIRQ\r
+ #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ\r
+ #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ\r
+ #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ\r
+/*#define NVIC_GetActive __NVIC_GetActive not available for Cortex-M1 */\r
+ #define NVIC_SetPriority __NVIC_SetPriority\r
+ #define NVIC_GetPriority __NVIC_GetPriority\r
+ #define NVIC_SystemReset __NVIC_SystemReset\r
+#endif /* CMSIS_NVIC_VIRTUAL */\r
+\r
+#ifdef CMSIS_VECTAB_VIRTUAL\r
+ #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE\r
+ #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h"\r
+ #endif\r
+ #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE\r
+#else\r
+ #define NVIC_SetVector __NVIC_SetVector\r
+ #define NVIC_GetVector __NVIC_GetVector\r
+#endif /* (CMSIS_VECTAB_VIRTUAL) */\r
+\r
+#define NVIC_USER_IRQ_OFFSET 16\r
+\r
+\r
+/* The following EXC_RETURN values are saved the LR on exception entry */\r
+#define EXC_RETURN_HANDLER (0xFFFFFFF1UL) /* return to Handler mode, uses MSP after return */\r
+#define EXC_RETURN_THREAD_MSP (0xFFFFFFF9UL) /* return to Thread mode, uses MSP after return */\r
+#define EXC_RETURN_THREAD_PSP (0xFFFFFFFDUL) /* return to Thread mode, uses PSP after return */\r
+\r
+\r
+/* Interrupt Priorities are WORD accessible only under Armv6-M */\r
+/* The following MACROS handle generation of the register offset and byte masks */\r
+#define _BIT_SHIFT(IRQn) ( ((((uint32_t)(int32_t)(IRQn)) ) & 0x03UL) * 8UL)\r
+#define _SHP_IDX(IRQn) ( (((((uint32_t)(int32_t)(IRQn)) & 0x0FUL)-8UL) >> 2UL) )\r
+#define _IP_IDX(IRQn) ( (((uint32_t)(int32_t)(IRQn)) >> 2UL) )\r
+\r
+#define __NVIC_SetPriorityGrouping(X) (void)(X)\r
+#define __NVIC_GetPriorityGrouping() (0U)\r
+\r
+/**\r
+ \brief Enable Interrupt\r
+ \details Enables a device specific interrupt in the NVIC interrupt controller.\r
+ \param [in] IRQn Device specific interrupt number.\r
+ \note IRQn must not be negative.\r
+ */\r
+__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn)\r
+{\r
+ if ((int32_t)(IRQn) >= 0)\r
+ {\r
+ NVIC->ISER[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));\r
+ }\r
+}\r
+\r
+\r
+/**\r
+ \brief Get Interrupt Enable status\r
+ \details Returns a device specific interrupt enable status from the NVIC interrupt controller.\r
+ \param [in] IRQn Device specific interrupt number.\r
+ \return 0 Interrupt is not enabled.\r
+ \return 1 Interrupt is enabled.\r
+ \note IRQn must not be negative.\r
+ */\r
+__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn)\r
+{\r
+ if ((int32_t)(IRQn) >= 0)\r
+ {\r
+ return((uint32_t)(((NVIC->ISER[0U] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));\r
+ }\r
+ else\r
+ {\r
+ return(0U);\r
+ }\r
+}\r
+\r
+\r
+/**\r
+ \brief Disable Interrupt\r
+ \details Disables a device specific interrupt in the NVIC interrupt controller.\r
+ \param [in] IRQn Device specific interrupt number.\r
+ \note IRQn must not be negative.\r
+ */\r
+__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn)\r
+{\r
+ if ((int32_t)(IRQn) >= 0)\r
+ {\r
+ NVIC->ICER[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));\r
+ __DSB();\r
+ __ISB();\r
+ }\r
+}\r
+\r
+\r
+/**\r
+ \brief Get Pending Interrupt\r
+ \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt.\r
+ \param [in] IRQn Device specific interrupt number.\r
+ \return 0 Interrupt status is not pending.\r
+ \return 1 Interrupt status is pending.\r
+ \note IRQn must not be negative.\r
+ */\r
+__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn)\r
+{\r
+ if ((int32_t)(IRQn) >= 0)\r
+ {\r
+ return((uint32_t)(((NVIC->ISPR[0U] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));\r
+ }\r
+ else\r
+ {\r
+ return(0U);\r
+ }\r
+}\r
+\r
+\r
+/**\r
+ \brief Set Pending Interrupt\r
+ \details Sets the pending bit of a device specific interrupt in the NVIC pending register.\r
+ \param [in] IRQn Device specific interrupt number.\r
+ \note IRQn must not be negative.\r
+ */\r
+__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn)\r
+{\r
+ if ((int32_t)(IRQn) >= 0)\r
+ {\r
+ NVIC->ISPR[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));\r
+ }\r
+}\r
+\r
+\r
+/**\r
+ \brief Clear Pending Interrupt\r
+ \details Clears the pending bit of a device specific interrupt in the NVIC pending register.\r
+ \param [in] IRQn Device specific interrupt number.\r
+ \note IRQn must not be negative.\r
+ */\r
+__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn)\r
+{\r
+ if ((int32_t)(IRQn) >= 0)\r
+ {\r
+ NVIC->ICPR[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));\r
+ }\r
+}\r
+\r
+\r
+/**\r
+ \brief Set Interrupt Priority\r
+ \details Sets the priority of a device specific interrupt or a processor exception.\r
+ The interrupt number can be positive to specify a device specific interrupt,\r
+ or negative to specify a processor exception.\r
+ \param [in] IRQn Interrupt number.\r
+ \param [in] priority Priority to set.\r
+ \note The priority cannot be set for every processor exception.\r
+ */\r
+__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)\r
+{\r
+ if ((int32_t)(IRQn) >= 0)\r
+ {\r
+ NVIC->IP[_IP_IDX(IRQn)] = ((uint32_t)(NVIC->IP[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |\r
+ (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));\r
+ }\r
+ else\r
+ {\r
+ SCB->SHP[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |\r
+ (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));\r
+ }\r
+}\r
+\r
+\r
+/**\r
+ \brief Get Interrupt Priority\r
+ \details Reads the priority of a device specific interrupt or a processor exception.\r
+ The interrupt number can be positive to specify a device specific interrupt,\r
+ or negative to specify a processor exception.\r
+ \param [in] IRQn Interrupt number.\r
+ \return Interrupt Priority.\r
+ Value is aligned automatically to the implemented priority bits of the microcontroller.\r
+ */\r
+__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn)\r
+{\r
+\r
+ if ((int32_t)(IRQn) >= 0)\r
+ {\r
+ return((uint32_t)(((NVIC->IP[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));\r
+ }\r
+ else\r
+ {\r
+ return((uint32_t)(((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));\r
+ }\r
+}\r
+\r
+\r
+/**\r
+ \brief Encode Priority\r
+ \details Encodes the priority for an interrupt with the given priority group,\r
+ preemptive priority value, and subpriority value.\r
+ In case of a conflict between priority grouping and available\r
+ priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.\r
+ \param [in] PriorityGroup Used priority group.\r
+ \param [in] PreemptPriority Preemptive priority value (starting from 0).\r
+ \param [in] SubPriority Subpriority value (starting from 0).\r
+ \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority().\r
+ */\r
+__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)\r
+{\r
+ uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */\r
+ uint32_t PreemptPriorityBits;\r
+ uint32_t SubPriorityBits;\r
+\r
+ PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);\r
+ SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));\r
+\r
+ return (\r
+ ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) |\r
+ ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL)))\r
+ );\r
+}\r
+\r
+\r
+/**\r
+ \brief Decode Priority\r
+ \details Decodes an interrupt priority value with a given priority group to\r
+ preemptive priority value and subpriority value.\r
+ In case of a conflict between priority grouping and available\r
+ priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set.\r
+ \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority().\r
+ \param [in] PriorityGroup Used priority group.\r
+ \param [out] pPreemptPriority Preemptive priority value (starting from 0).\r
+ \param [out] pSubPriority Subpriority value (starting from 0).\r
+ */\r
+__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority)\r
+{\r
+ uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */\r
+ uint32_t PreemptPriorityBits;\r
+ uint32_t SubPriorityBits;\r
+\r
+ PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);\r
+ SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));\r
+\r
+ *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL);\r
+ *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL);\r
+}\r
+\r
+\r
+\r
+/**\r
+ \brief Set Interrupt Vector\r
+ \details Sets an interrupt vector in SRAM based interrupt vector table.\r
+ The interrupt number can be positive to specify a device specific interrupt,\r
+ or negative to specify a processor exception.\r
+ Address 0 must be mapped to SRAM.\r
+ \param [in] IRQn Interrupt number\r
+ \param [in] vector Address of interrupt handler function\r
+ */\r
+__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector)\r
+{\r
+ uint32_t *vectors = (uint32_t *)0x0U;\r
+ vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector;\r
+}\r
+\r
+\r
+/**\r
+ \brief Get Interrupt Vector\r
+ \details Reads an interrupt vector from interrupt vector table.\r
+ The interrupt number can be positive to specify a device specific interrupt,\r
+ or negative to specify a processor exception.\r
+ \param [in] IRQn Interrupt number.\r
+ \return Address of interrupt handler function\r
+ */\r
+__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn)\r
+{\r
+ uint32_t *vectors = (uint32_t *)0x0U;\r
+ return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET];\r
+}\r
+\r
+\r
+/**\r
+ \brief System Reset\r
+ \details Initiates a system reset request to reset the MCU.\r
+ */\r
+__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void)\r
+{\r
+ __DSB(); /* Ensure all outstanding memory accesses included\r
+ buffered write are completed before reset */\r
+ SCB->AIRCR = ((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |\r
+ SCB_AIRCR_SYSRESETREQ_Msk);\r
+ __DSB(); /* Ensure completion of memory access */\r
+\r
+ for(;;) /* wait until reset */\r
+ {\r
+ __NOP();\r
+ }\r
+}\r
+\r
+/*@} end of CMSIS_Core_NVICFunctions */\r
+\r
+\r
+/* ########################## FPU functions #################################### */\r
+/**\r
+ \ingroup CMSIS_Core_FunctionInterface\r
+ \defgroup CMSIS_Core_FpuFunctions FPU Functions\r
+ \brief Function that provides FPU type.\r
+ @{\r
+ */\r
+\r
+/**\r
+ \brief get FPU type\r
+ \details returns the FPU type\r
+ \returns\r
+ - \b 0: No FPU\r
+ - \b 1: Single precision FPU\r
+ - \b 2: Double + Single precision FPU\r
+ */\r
+__STATIC_INLINE uint32_t SCB_GetFPUType(void)\r
+{\r
+ return 0U; /* No FPU */\r
+}\r
+\r
+\r
+/*@} end of CMSIS_Core_FpuFunctions */\r
+\r
+\r
+\r
+/* ################################## SysTick function ############################################ */\r
+/**\r
+ \ingroup CMSIS_Core_FunctionInterface\r
+ \defgroup CMSIS_Core_SysTickFunctions SysTick Functions\r
+ \brief Functions that configure the System.\r
+ @{\r
+ */\r
+\r
+#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U)\r
+\r
+/**\r
+ \brief System Tick Configuration\r
+ \details Initializes the System Timer and its interrupt, and starts the System Tick Timer.\r
+ Counter is in free running mode to generate periodic interrupts.\r
+ \param [in] ticks Number of ticks between two interrupts.\r
+ \return 0 Function succeeded.\r
+ \return 1 Function failed.\r
+ \note When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the\r
+ function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>\r
+ must contain a vendor-specific implementation of this function.\r
+ */\r
+__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)\r
+{\r
+ if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk)\r
+ {\r
+ return (1UL); /* Reload value impossible */\r
+ }\r
+\r
+ SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */\r
+ NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */\r
+ SysTick->VAL = 0UL; /* Load the SysTick Counter Value */\r
+ SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk |\r
+ SysTick_CTRL_TICKINT_Msk |\r
+ SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */\r
+ return (0UL); /* Function successful */\r
+}\r
+\r
+#endif\r
+\r
+/*@} end of CMSIS_Core_SysTickFunctions */\r
+\r
+\r
+\r
+\r
+#ifdef __cplusplus\r
+}\r
+#endif\r
+\r
+#endif /* __CORE_CM1_H_DEPENDANT */\r
+\r
+#endif /* __CMSIS_GENERIC */\r
--- /dev/null
+/**************************************************************************//**\r
+ * @file core_cm23.h\r
+ * @brief CMSIS Cortex-M23 Core Peripheral Access Layer Header File\r
+ * @version V5.0.7\r
+ * @date 22. June 2018\r
+ ******************************************************************************/\r
+/*\r
+ * Copyright (c) 2009-2018 Arm Limited. All rights reserved.\r
+ *\r
+ * SPDX-License-Identifier: Apache-2.0\r
+ *\r
+ * Licensed under the Apache License, Version 2.0 (the License); you may\r
+ * not use this file except in compliance with the License.\r
+ * You may obtain a copy of the License at\r
+ *\r
+ * www.apache.org/licenses/LICENSE-2.0\r
+ *\r
+ * Unless required by applicable law or agreed to in writing, software\r
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT\r
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\r
+ * See the License for the specific language governing permissions and\r
+ * limitations under the License.\r
+ */\r
+\r
+#if defined ( __ICCARM__ )\r
+ #pragma system_include /* treat file as system include file for MISRA check */\r
+#elif defined (__clang__)\r
+ #pragma clang system_header /* treat file as system include file */\r
+#endif\r
+\r
+#ifndef __CORE_CM23_H_GENERIC\r
+#define __CORE_CM23_H_GENERIC\r
+\r
+#include <stdint.h>\r
+\r
+#ifdef __cplusplus\r
+ extern "C" {\r
+#endif\r
+\r
+/**\r
+ \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions\r
+ CMSIS violates the following MISRA-C:2004 rules:\r
+\r
+ \li Required Rule 8.5, object/function definition in header file.<br>\r
+ Function definitions in header files are used to allow 'inlining'.\r
+\r
+ \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>\r
+ Unions are used for effective representation of core registers.\r
+\r
+ \li Advisory Rule 19.7, Function-like macro defined.<br>\r
+ Function-like macros are used to allow more efficient code.\r
+ */\r
+\r
+\r
+/*******************************************************************************\r
+ * CMSIS definitions\r
+ ******************************************************************************/\r
+/**\r
+ \ingroup Cortex_M23\r
+ @{\r
+ */\r
+\r
+#include "cmsis_version.h"\r
+\r
+/* CMSIS definitions */\r
+#define __CM23_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */\r
+#define __CM23_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */\r
+#define __CM23_CMSIS_VERSION ((__CM23_CMSIS_VERSION_MAIN << 16U) | \\r
+ __CM23_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */\r
+\r
+#define __CORTEX_M (23U) /*!< Cortex-M Core */\r
+\r
+/** __FPU_USED indicates whether an FPU is used or not.\r
+ This core does not support an FPU at all\r
+*/\r
+#define __FPU_USED 0U\r
+\r
+#if defined ( __CC_ARM )\r
+ #if defined __TARGET_FPU_VFP\r
+ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"\r
+ #endif\r
+\r
+#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)\r
+ #if defined __ARM_PCS_VFP\r
+ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"\r
+ #endif\r
+\r
+#elif defined ( __GNUC__ )\r
+ #if defined (__VFP_FP__) && !defined(__SOFTFP__)\r
+ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"\r
+ #endif\r
+\r
+#elif defined ( __ICCARM__ )\r
+ #if defined __ARMVFP__\r
+ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"\r
+ #endif\r
+\r
+#elif defined ( __TI_ARM__ )\r
+ #if defined __TI_VFP_SUPPORT__\r
+ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"\r
+ #endif\r
+\r
+#elif defined ( __TASKING__ )\r
+ #if defined __FPU_VFP__\r
+ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"\r
+ #endif\r
+\r
+#elif defined ( __CSMC__ )\r
+ #if ( __CSMC__ & 0x400U)\r
+ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"\r
+ #endif\r
+\r
+#endif\r
+\r
+#include "cmsis_compiler.h" /* CMSIS compiler specific defines */\r
+\r
+\r
+#ifdef __cplusplus\r
+}\r
+#endif\r
+\r
+#endif /* __CORE_CM23_H_GENERIC */\r
+\r
+#ifndef __CMSIS_GENERIC\r
+\r
+#ifndef __CORE_CM23_H_DEPENDANT\r
+#define __CORE_CM23_H_DEPENDANT\r
+\r
+#ifdef __cplusplus\r
+ extern "C" {\r
+#endif\r
+\r
+/* check device defines and use defaults */\r
+#if defined __CHECK_DEVICE_DEFINES\r
+ #ifndef __CM23_REV\r
+ #define __CM23_REV 0x0000U\r
+ #warning "__CM23_REV not defined in device header file; using default!"\r
+ #endif\r
+\r
+ #ifndef __FPU_PRESENT\r
+ #define __FPU_PRESENT 0U\r
+ #warning "__FPU_PRESENT not defined in device header file; using default!"\r
+ #endif\r
+\r
+ #ifndef __MPU_PRESENT\r
+ #define __MPU_PRESENT 0U\r
+ #warning "__MPU_PRESENT not defined in device header file; using default!"\r
+ #endif\r
+\r
+ #ifndef __SAUREGION_PRESENT\r
+ #define __SAUREGION_PRESENT 0U\r
+ #warning "__SAUREGION_PRESENT not defined in device header file; using default!"\r
+ #endif\r
+\r
+ #ifndef __VTOR_PRESENT\r
+ #define __VTOR_PRESENT 0U\r
+ #warning "__VTOR_PRESENT not defined in device header file; using default!"\r
+ #endif\r
+\r
+ #ifndef __NVIC_PRIO_BITS\r
+ #define __NVIC_PRIO_BITS 2U\r
+ #warning "__NVIC_PRIO_BITS not defined in device header file; using default!"\r
+ #endif\r
+\r
+ #ifndef __Vendor_SysTickConfig\r
+ #define __Vendor_SysTickConfig 0U\r
+ #warning "__Vendor_SysTickConfig not defined in device header file; using default!"\r
+ #endif\r
+\r
+ #ifndef __ETM_PRESENT\r
+ #define __ETM_PRESENT 0U\r
+ #warning "__ETM_PRESENT not defined in device header file; using default!"\r
+ #endif\r
+\r
+ #ifndef __MTB_PRESENT\r
+ #define __MTB_PRESENT 0U\r
+ #warning "__MTB_PRESENT not defined in device header file; using default!"\r
+ #endif\r
+\r
+#endif\r
+\r
+/* IO definitions (access restrictions to peripheral registers) */\r
+/**\r
+ \defgroup CMSIS_glob_defs CMSIS Global Defines\r
+\r
+ <strong>IO Type Qualifiers</strong> are used\r
+ \li to specify the access to peripheral variables.\r
+ \li for automatic generation of peripheral register debug information.\r
+*/\r
+#ifdef __cplusplus\r
+ #define __I volatile /*!< Defines 'read only' permissions */\r
+#else\r
+ #define __I volatile const /*!< Defines 'read only' permissions */\r
+#endif\r
+#define __O volatile /*!< Defines 'write only' permissions */\r
+#define __IO volatile /*!< Defines 'read / write' permissions */\r
+\r
+/* following defines should be used for structure members */\r
+#define __IM volatile const /*! Defines 'read only' structure member permissions */\r
+#define __OM volatile /*! Defines 'write only' structure member permissions */\r
+#define __IOM volatile /*! Defines 'read / write' structure member permissions */\r
+\r
+/*@} end of group Cortex_M23 */\r
+\r
+\r
+\r
+/*******************************************************************************\r
+ * Register Abstraction\r
+ Core Register contain:\r
+ - Core Register\r
+ - Core NVIC Register\r
+ - Core SCB Register\r
+ - Core SysTick Register\r
+ - Core Debug Register\r
+ - Core MPU Register\r
+ - Core SAU Register\r
+ ******************************************************************************/\r
+/**\r
+ \defgroup CMSIS_core_register Defines and Type Definitions\r
+ \brief Type definitions and defines for Cortex-M processor based devices.\r
+*/\r
+\r
+/**\r
+ \ingroup CMSIS_core_register\r
+ \defgroup CMSIS_CORE Status and Control Registers\r
+ \brief Core Register type definitions.\r
+ @{\r
+ */\r
+\r
+/**\r
+ \brief Union type to access the Application Program Status Register (APSR).\r
+ */\r
+typedef union\r
+{\r
+ struct\r
+ {\r
+ uint32_t _reserved0:28; /*!< bit: 0..27 Reserved */\r
+ uint32_t V:1; /*!< bit: 28 Overflow condition code flag */\r
+ uint32_t C:1; /*!< bit: 29 Carry condition code flag */\r
+ uint32_t Z:1; /*!< bit: 30 Zero condition code flag */\r
+ uint32_t N:1; /*!< bit: 31 Negative condition code flag */\r
+ } b; /*!< Structure used for bit access */\r
+ uint32_t w; /*!< Type used for word access */\r
+} APSR_Type;\r
+\r
+/* APSR Register Definitions */\r
+#define APSR_N_Pos 31U /*!< APSR: N Position */\r
+#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */\r
+\r
+#define APSR_Z_Pos 30U /*!< APSR: Z Position */\r
+#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */\r
+\r
+#define APSR_C_Pos 29U /*!< APSR: C Position */\r
+#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */\r
+\r
+#define APSR_V_Pos 28U /*!< APSR: V Position */\r
+#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */\r
+\r
+\r
+/**\r
+ \brief Union type to access the Interrupt Program Status Register (IPSR).\r
+ */\r
+typedef union\r
+{\r
+ struct\r
+ {\r
+ uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */\r
+ uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */\r
+ } b; /*!< Structure used for bit access */\r
+ uint32_t w; /*!< Type used for word access */\r
+} IPSR_Type;\r
+\r
+/* IPSR Register Definitions */\r
+#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */\r
+#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */\r
+\r
+\r
+/**\r
+ \brief Union type to access the Special-Purpose Program Status Registers (xPSR).\r
+ */\r
+typedef union\r
+{\r
+ struct\r
+ {\r
+ uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */\r
+ uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */\r
+ uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */\r
+ uint32_t _reserved1:3; /*!< bit: 25..27 Reserved */\r
+ uint32_t V:1; /*!< bit: 28 Overflow condition code flag */\r
+ uint32_t C:1; /*!< bit: 29 Carry condition code flag */\r
+ uint32_t Z:1; /*!< bit: 30 Zero condition code flag */\r
+ uint32_t N:1; /*!< bit: 31 Negative condition code flag */\r
+ } b; /*!< Structure used for bit access */\r
+ uint32_t w; /*!< Type used for word access */\r
+} xPSR_Type;\r
+\r
+/* xPSR Register Definitions */\r
+#define xPSR_N_Pos 31U /*!< xPSR: N Position */\r
+#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */\r
+\r
+#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */\r
+#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */\r
+\r
+#define xPSR_C_Pos 29U /*!< xPSR: C Position */\r
+#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */\r
+\r
+#define xPSR_V_Pos 28U /*!< xPSR: V Position */\r
+#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */\r
+\r
+#define xPSR_T_Pos 24U /*!< xPSR: T Position */\r
+#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */\r
+\r
+#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */\r
+#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */\r
+\r
+\r
+/**\r
+ \brief Union type to access the Control Registers (CONTROL).\r
+ */\r
+typedef union\r
+{\r
+ struct\r
+ {\r
+ uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */\r
+ uint32_t SPSEL:1; /*!< bit: 1 Stack-pointer select */\r
+ uint32_t _reserved1:30; /*!< bit: 2..31 Reserved */\r
+ } b; /*!< Structure used for bit access */\r
+ uint32_t w; /*!< Type used for word access */\r
+} CONTROL_Type;\r
+\r
+/* CONTROL Register Definitions */\r
+#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */\r
+#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */\r
+\r
+#define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */\r
+#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */\r
+\r
+/*@} end of group CMSIS_CORE */\r
+\r
+\r
+/**\r
+ \ingroup CMSIS_core_register\r
+ \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC)\r
+ \brief Type definitions for the NVIC Registers\r
+ @{\r
+ */\r
+\r
+/**\r
+ \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC).\r
+ */\r
+typedef struct\r
+{\r
+ __IOM uint32_t ISER[16U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */\r
+ uint32_t RESERVED0[16U];\r
+ __IOM uint32_t ICER[16U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */\r
+ uint32_t RSERVED1[16U];\r
+ __IOM uint32_t ISPR[16U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */\r
+ uint32_t RESERVED2[16U];\r
+ __IOM uint32_t ICPR[16U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */\r
+ uint32_t RESERVED3[16U];\r
+ __IOM uint32_t IABR[16U]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */\r
+ uint32_t RESERVED4[16U];\r
+ __IOM uint32_t ITNS[16U]; /*!< Offset: 0x280 (R/W) Interrupt Non-Secure State Register */\r
+ uint32_t RESERVED5[16U];\r
+ __IOM uint32_t IPR[124U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register */\r
+} NVIC_Type;\r
+\r
+/*@} end of group CMSIS_NVIC */\r
+\r
+\r
+/**\r
+ \ingroup CMSIS_core_register\r
+ \defgroup CMSIS_SCB System Control Block (SCB)\r
+ \brief Type definitions for the System Control Block Registers\r
+ @{\r
+ */\r
+\r
+/**\r
+ \brief Structure type to access the System Control Block (SCB).\r
+ */\r
+typedef struct\r
+{\r
+ __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */\r
+ __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */\r
+#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U)\r
+ __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */\r
+#else\r
+ uint32_t RESERVED0;\r
+#endif\r
+ __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */\r
+ __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */\r
+ __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */\r
+ uint32_t RESERVED1;\r
+ __IOM uint32_t SHPR[2U]; /*!< Offset: 0x01C (R/W) System Handlers Priority Registers. [0] is RESERVED */\r
+ __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */\r
+} SCB_Type;\r
+\r
+/* SCB CPUID Register Definitions */\r
+#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */\r
+#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */\r
+\r
+#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */\r
+#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */\r
+\r
+#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */\r
+#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */\r
+\r
+#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */\r
+#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */\r
+\r
+#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */\r
+#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */\r
+\r
+/* SCB Interrupt Control State Register Definitions */\r
+#define SCB_ICSR_PENDNMISET_Pos 31U /*!< SCB ICSR: PENDNMISET Position */\r
+#define SCB_ICSR_PENDNMISET_Msk (1UL << SCB_ICSR_PENDNMISET_Pos) /*!< SCB ICSR: PENDNMISET Mask */\r
+\r
+#define SCB_ICSR_NMIPENDSET_Pos SCB_ICSR_PENDNMISET_Pos /*!< SCB ICSR: NMIPENDSET Position, backward compatibility */\r
+#define SCB_ICSR_NMIPENDSET_Msk SCB_ICSR_PENDNMISET_Msk /*!< SCB ICSR: NMIPENDSET Mask, backward compatibility */\r
+\r
+#define SCB_ICSR_PENDNMICLR_Pos 30U /*!< SCB ICSR: PENDNMICLR Position */\r
+#define SCB_ICSR_PENDNMICLR_Msk (1UL << SCB_ICSR_PENDNMICLR_Pos) /*!< SCB ICSR: PENDNMICLR Mask */\r
+\r
+#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */\r
+#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */\r
+\r
+#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */\r
+#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */\r
+\r
+#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */\r
+#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */\r
+\r
+#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */\r
+#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */\r
+\r
+#define SCB_ICSR_STTNS_Pos 24U /*!< SCB ICSR: STTNS Position (Security Extension) */\r
+#define SCB_ICSR_STTNS_Msk (1UL << SCB_ICSR_STTNS_Pos) /*!< SCB ICSR: STTNS Mask (Security Extension) */\r
+\r
+#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */\r
+#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */\r
+\r
+#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */\r
+#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */\r
+\r
+#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */\r
+#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */\r
+\r
+#define SCB_ICSR_RETTOBASE_Pos 11U /*!< SCB ICSR: RETTOBASE Position */\r
+#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */\r
+\r
+#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */\r
+#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */\r
+\r
+#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U)\r
+/* SCB Vector Table Offset Register Definitions */\r
+#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */\r
+#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */\r
+#endif\r
+\r
+/* SCB Application Interrupt and Reset Control Register Definitions */\r
+#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */\r
+#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */\r
+\r
+#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */\r
+#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */\r
+\r
+#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */\r
+#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */\r
+\r
+#define SCB_AIRCR_PRIS_Pos 14U /*!< SCB AIRCR: PRIS Position */\r
+#define SCB_AIRCR_PRIS_Msk (1UL << SCB_AIRCR_PRIS_Pos) /*!< SCB AIRCR: PRIS Mask */\r
+\r
+#define SCB_AIRCR_BFHFNMINS_Pos 13U /*!< SCB AIRCR: BFHFNMINS Position */\r
+#define SCB_AIRCR_BFHFNMINS_Msk (1UL << SCB_AIRCR_BFHFNMINS_Pos) /*!< SCB AIRCR: BFHFNMINS Mask */\r
+\r
+#define SCB_AIRCR_SYSRESETREQS_Pos 3U /*!< SCB AIRCR: SYSRESETREQS Position */\r
+#define SCB_AIRCR_SYSRESETREQS_Msk (1UL << SCB_AIRCR_SYSRESETREQS_Pos) /*!< SCB AIRCR: SYSRESETREQS Mask */\r
+\r
+#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */\r
+#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */\r
+\r
+#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */\r
+#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */\r
+\r
+/* SCB System Control Register Definitions */\r
+#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */\r
+#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */\r
+\r
+#define SCB_SCR_SLEEPDEEPS_Pos 3U /*!< SCB SCR: SLEEPDEEPS Position */\r
+#define SCB_SCR_SLEEPDEEPS_Msk (1UL << SCB_SCR_SLEEPDEEPS_Pos) /*!< SCB SCR: SLEEPDEEPS Mask */\r
+\r
+#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */\r
+#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */\r
+\r
+#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */\r
+#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */\r
+\r
+/* SCB Configuration Control Register Definitions */\r
+#define SCB_CCR_BP_Pos 18U /*!< SCB CCR: BP Position */\r
+#define SCB_CCR_BP_Msk (1UL << SCB_CCR_BP_Pos) /*!< SCB CCR: BP Mask */\r
+\r
+#define SCB_CCR_IC_Pos 17U /*!< SCB CCR: IC Position */\r
+#define SCB_CCR_IC_Msk (1UL << SCB_CCR_IC_Pos) /*!< SCB CCR: IC Mask */\r
+\r
+#define SCB_CCR_DC_Pos 16U /*!< SCB CCR: DC Position */\r
+#define SCB_CCR_DC_Msk (1UL << SCB_CCR_DC_Pos) /*!< SCB CCR: DC Mask */\r
+\r
+#define SCB_CCR_STKOFHFNMIGN_Pos 10U /*!< SCB CCR: STKOFHFNMIGN Position */\r
+#define SCB_CCR_STKOFHFNMIGN_Msk (1UL << SCB_CCR_STKOFHFNMIGN_Pos) /*!< SCB CCR: STKOFHFNMIGN Mask */\r
+\r
+#define SCB_CCR_BFHFNMIGN_Pos 8U /*!< SCB CCR: BFHFNMIGN Position */\r
+#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */\r
+\r
+#define SCB_CCR_DIV_0_TRP_Pos 4U /*!< SCB CCR: DIV_0_TRP Position */\r
+#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */\r
+\r
+#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */\r
+#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */\r
+\r
+#define SCB_CCR_USERSETMPEND_Pos 1U /*!< SCB CCR: USERSETMPEND Position */\r
+#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */\r
+\r
+/* SCB System Handler Control and State Register Definitions */\r
+#define SCB_SHCSR_HARDFAULTPENDED_Pos 21U /*!< SCB SHCSR: HARDFAULTPENDED Position */\r
+#define SCB_SHCSR_HARDFAULTPENDED_Msk (1UL << SCB_SHCSR_HARDFAULTPENDED_Pos) /*!< SCB SHCSR: HARDFAULTPENDED Mask */\r
+\r
+#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */\r
+#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */\r
+\r
+#define SCB_SHCSR_SYSTICKACT_Pos 11U /*!< SCB SHCSR: SYSTICKACT Position */\r
+#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */\r
+\r
+#define SCB_SHCSR_PENDSVACT_Pos 10U /*!< SCB SHCSR: PENDSVACT Position */\r
+#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */\r
+\r
+#define SCB_SHCSR_SVCALLACT_Pos 7U /*!< SCB SHCSR: SVCALLACT Position */\r
+#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */\r
+\r
+#define SCB_SHCSR_NMIACT_Pos 5U /*!< SCB SHCSR: NMIACT Position */\r
+#define SCB_SHCSR_NMIACT_Msk (1UL << SCB_SHCSR_NMIACT_Pos) /*!< SCB SHCSR: NMIACT Mask */\r
+\r
+#define SCB_SHCSR_HARDFAULTACT_Pos 2U /*!< SCB SHCSR: HARDFAULTACT Position */\r
+#define SCB_SHCSR_HARDFAULTACT_Msk (1UL << SCB_SHCSR_HARDFAULTACT_Pos) /*!< SCB SHCSR: HARDFAULTACT Mask */\r
+\r
+/*@} end of group CMSIS_SCB */\r
+\r
+\r
+/**\r
+ \ingroup CMSIS_core_register\r
+ \defgroup CMSIS_SysTick System Tick Timer (SysTick)\r
+ \brief Type definitions for the System Timer Registers.\r
+ @{\r
+ */\r
+\r
+/**\r
+ \brief Structure type to access the System Timer (SysTick).\r
+ */\r
+typedef struct\r
+{\r
+ __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */\r
+ __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */\r
+ __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */\r
+ __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */\r
+} SysTick_Type;\r
+\r
+/* SysTick Control / Status Register Definitions */\r
+#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */\r
+#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */\r
+\r
+#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */\r
+#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */\r
+\r
+#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */\r
+#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */\r
+\r
+#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */\r
+#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */\r
+\r
+/* SysTick Reload Register Definitions */\r
+#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */\r
+#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */\r
+\r
+/* SysTick Current Register Definitions */\r
+#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */\r
+#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */\r
+\r
+/* SysTick Calibration Register Definitions */\r
+#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */\r
+#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */\r
+\r
+#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */\r
+#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */\r
+\r
+#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */\r
+#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */\r
+\r
+/*@} end of group CMSIS_SysTick */\r
+\r
+\r
+/**\r
+ \ingroup CMSIS_core_register\r
+ \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT)\r
+ \brief Type definitions for the Data Watchpoint and Trace (DWT)\r
+ @{\r
+ */\r
+\r
+/**\r
+ \brief Structure type to access the Data Watchpoint and Trace Register (DWT).\r
+ */\r
+typedef struct\r
+{\r
+ __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */\r
+ uint32_t RESERVED0[6U];\r
+ __IM uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */\r
+ __IOM uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */\r
+ uint32_t RESERVED1[1U];\r
+ __IOM uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */\r
+ uint32_t RESERVED2[1U];\r
+ __IOM uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */\r
+ uint32_t RESERVED3[1U];\r
+ __IOM uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */\r
+ uint32_t RESERVED4[1U];\r
+ __IOM uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */\r
+ uint32_t RESERVED5[1U];\r
+ __IOM uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */\r
+ uint32_t RESERVED6[1U];\r
+ __IOM uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */\r
+ uint32_t RESERVED7[1U];\r
+ __IOM uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */\r
+ uint32_t RESERVED8[1U];\r
+ __IOM uint32_t COMP4; /*!< Offset: 0x060 (R/W) Comparator Register 4 */\r
+ uint32_t RESERVED9[1U];\r
+ __IOM uint32_t FUNCTION4; /*!< Offset: 0x068 (R/W) Function Register 4 */\r
+ uint32_t RESERVED10[1U];\r
+ __IOM uint32_t COMP5; /*!< Offset: 0x070 (R/W) Comparator Register 5 */\r
+ uint32_t RESERVED11[1U];\r
+ __IOM uint32_t FUNCTION5; /*!< Offset: 0x078 (R/W) Function Register 5 */\r
+ uint32_t RESERVED12[1U];\r
+ __IOM uint32_t COMP6; /*!< Offset: 0x080 (R/W) Comparator Register 6 */\r
+ uint32_t RESERVED13[1U];\r
+ __IOM uint32_t FUNCTION6; /*!< Offset: 0x088 (R/W) Function Register 6 */\r
+ uint32_t RESERVED14[1U];\r
+ __IOM uint32_t COMP7; /*!< Offset: 0x090 (R/W) Comparator Register 7 */\r
+ uint32_t RESERVED15[1U];\r
+ __IOM uint32_t FUNCTION7; /*!< Offset: 0x098 (R/W) Function Register 7 */\r
+ uint32_t RESERVED16[1U];\r
+ __IOM uint32_t COMP8; /*!< Offset: 0x0A0 (R/W) Comparator Register 8 */\r
+ uint32_t RESERVED17[1U];\r
+ __IOM uint32_t FUNCTION8; /*!< Offset: 0x0A8 (R/W) Function Register 8 */\r
+ uint32_t RESERVED18[1U];\r
+ __IOM uint32_t COMP9; /*!< Offset: 0x0B0 (R/W) Comparator Register 9 */\r
+ uint32_t RESERVED19[1U];\r
+ __IOM uint32_t FUNCTION9; /*!< Offset: 0x0B8 (R/W) Function Register 9 */\r
+ uint32_t RESERVED20[1U];\r
+ __IOM uint32_t COMP10; /*!< Offset: 0x0C0 (R/W) Comparator Register 10 */\r
+ uint32_t RESERVED21[1U];\r
+ __IOM uint32_t FUNCTION10; /*!< Offset: 0x0C8 (R/W) Function Register 10 */\r
+ uint32_t RESERVED22[1U];\r
+ __IOM uint32_t COMP11; /*!< Offset: 0x0D0 (R/W) Comparator Register 11 */\r
+ uint32_t RESERVED23[1U];\r
+ __IOM uint32_t FUNCTION11; /*!< Offset: 0x0D8 (R/W) Function Register 11 */\r
+ uint32_t RESERVED24[1U];\r
+ __IOM uint32_t COMP12; /*!< Offset: 0x0E0 (R/W) Comparator Register 12 */\r
+ uint32_t RESERVED25[1U];\r
+ __IOM uint32_t FUNCTION12; /*!< Offset: 0x0E8 (R/W) Function Register 12 */\r
+ uint32_t RESERVED26[1U];\r
+ __IOM uint32_t COMP13; /*!< Offset: 0x0F0 (R/W) Comparator Register 13 */\r
+ uint32_t RESERVED27[1U];\r
+ __IOM uint32_t FUNCTION13; /*!< Offset: 0x0F8 (R/W) Function Register 13 */\r
+ uint32_t RESERVED28[1U];\r
+ __IOM uint32_t COMP14; /*!< Offset: 0x100 (R/W) Comparator Register 14 */\r
+ uint32_t RESERVED29[1U];\r
+ __IOM uint32_t FUNCTION14; /*!< Offset: 0x108 (R/W) Function Register 14 */\r
+ uint32_t RESERVED30[1U];\r
+ __IOM uint32_t COMP15; /*!< Offset: 0x110 (R/W) Comparator Register 15 */\r
+ uint32_t RESERVED31[1U];\r
+ __IOM uint32_t FUNCTION15; /*!< Offset: 0x118 (R/W) Function Register 15 */\r
+} DWT_Type;\r
+\r
+/* DWT Control Register Definitions */\r
+#define DWT_CTRL_NUMCOMP_Pos 28U /*!< DWT CTRL: NUMCOMP Position */\r
+#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */\r
+\r
+#define DWT_CTRL_NOTRCPKT_Pos 27U /*!< DWT CTRL: NOTRCPKT Position */\r
+#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */\r
+\r
+#define DWT_CTRL_NOEXTTRIG_Pos 26U /*!< DWT CTRL: NOEXTTRIG Position */\r
+#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */\r
+\r
+#define DWT_CTRL_NOCYCCNT_Pos 25U /*!< DWT CTRL: NOCYCCNT Position */\r
+#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */\r
+\r
+#define DWT_CTRL_NOPRFCNT_Pos 24U /*!< DWT CTRL: NOPRFCNT Position */\r
+#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */\r
+\r
+/* DWT Comparator Function Register Definitions */\r
+#define DWT_FUNCTION_ID_Pos 27U /*!< DWT FUNCTION: ID Position */\r
+#define DWT_FUNCTION_ID_Msk (0x1FUL << DWT_FUNCTION_ID_Pos) /*!< DWT FUNCTION: ID Mask */\r
+\r
+#define DWT_FUNCTION_MATCHED_Pos 24U /*!< DWT FUNCTION: MATCHED Position */\r
+#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */\r
+\r
+#define DWT_FUNCTION_DATAVSIZE_Pos 10U /*!< DWT FUNCTION: DATAVSIZE Position */\r
+#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */\r
+\r
+#define DWT_FUNCTION_ACTION_Pos 4U /*!< DWT FUNCTION: ACTION Position */\r
+#define DWT_FUNCTION_ACTION_Msk (0x3UL << DWT_FUNCTION_ACTION_Pos) /*!< DWT FUNCTION: ACTION Mask */\r
+\r
+#define DWT_FUNCTION_MATCH_Pos 0U /*!< DWT FUNCTION: MATCH Position */\r
+#define DWT_FUNCTION_MATCH_Msk (0xFUL /*<< DWT_FUNCTION_MATCH_Pos*/) /*!< DWT FUNCTION: MATCH Mask */\r
+\r
+/*@}*/ /* end of group CMSIS_DWT */\r
+\r
+\r
+/**\r
+ \ingroup CMSIS_core_register\r
+ \defgroup CMSIS_TPI Trace Port Interface (TPI)\r
+ \brief Type definitions for the Trace Port Interface (TPI)\r
+ @{\r
+ */\r
+\r
+/**\r
+ \brief Structure type to access the Trace Port Interface Register (TPI).\r
+ */\r
+typedef struct\r
+{\r
+ __IM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */\r
+ __IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */\r
+ uint32_t RESERVED0[2U];\r
+ __IOM uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */\r
+ uint32_t RESERVED1[55U];\r
+ __IOM uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */\r
+ uint32_t RESERVED2[131U];\r
+ __IM uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */\r
+ __IOM uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */\r
+ __IOM uint32_t PSCR; /*!< Offset: 0x308 (R/W) Periodic Synchronization Control Register */\r
+ uint32_t RESERVED3[759U];\r
+ __IM uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER Register */\r
+ __IM uint32_t ITFTTD0; /*!< Offset: 0xEEC (R/ ) Integration Test FIFO Test Data 0 Register */\r
+ __IOM uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/W) Integration Test ATB Control Register 2 */\r
+ uint32_t RESERVED4[1U];\r
+ __IM uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) Integration Test ATB Control Register 0 */\r
+ __IM uint32_t ITFTTD1; /*!< Offset: 0xEFC (R/ ) Integration Test FIFO Test Data 1 Register */\r
+ __IOM uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */\r
+ uint32_t RESERVED5[39U];\r
+ __IOM uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */\r
+ __IOM uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */\r
+ uint32_t RESERVED7[8U];\r
+ __IM uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) Device Configuration Register */\r
+ __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) Device Type Identifier Register */\r
+} TPI_Type;\r
+\r
+/* TPI Asynchronous Clock Prescaler Register Definitions */\r
+#define TPI_ACPR_PRESCALER_Pos 0U /*!< TPI ACPR: PRESCALER Position */\r
+#define TPI_ACPR_PRESCALER_Msk (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/) /*!< TPI ACPR: PRESCALER Mask */\r
+\r
+/* TPI Selected Pin Protocol Register Definitions */\r
+#define TPI_SPPR_TXMODE_Pos 0U /*!< TPI SPPR: TXMODE Position */\r
+#define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) /*!< TPI SPPR: TXMODE Mask */\r
+\r
+/* TPI Formatter and Flush Status Register Definitions */\r
+#define TPI_FFSR_FtNonStop_Pos 3U /*!< TPI FFSR: FtNonStop Position */\r
+#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */\r
+\r
+#define TPI_FFSR_TCPresent_Pos 2U /*!< TPI FFSR: TCPresent Position */\r
+#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */\r
+\r
+#define TPI_FFSR_FtStopped_Pos 1U /*!< TPI FFSR: FtStopped Position */\r
+#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */\r
+\r
+#define TPI_FFSR_FlInProg_Pos 0U /*!< TPI FFSR: FlInProg Position */\r
+#define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) /*!< TPI FFSR: FlInProg Mask */\r
+\r
+/* TPI Formatter and Flush Control Register Definitions */\r
+#define TPI_FFCR_TrigIn_Pos 8U /*!< TPI FFCR: TrigIn Position */\r
+#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */\r
+\r
+#define TPI_FFCR_FOnMan_Pos 6U /*!< TPI FFCR: FOnMan Position */\r
+#define TPI_FFCR_FOnMan_Msk (0x1UL << TPI_FFCR_FOnMan_Pos) /*!< TPI FFCR: FOnMan Mask */\r
+\r
+#define TPI_FFCR_EnFCont_Pos 1U /*!< TPI FFCR: EnFCont Position */\r
+#define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */\r
+\r
+/* TPI TRIGGER Register Definitions */\r
+#define TPI_TRIGGER_TRIGGER_Pos 0U /*!< TPI TRIGGER: TRIGGER Position */\r
+#define TPI_TRIGGER_TRIGGER_Msk (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/) /*!< TPI TRIGGER: TRIGGER Mask */\r
+\r
+/* TPI Integration Test FIFO Test Data 0 Register Definitions */\r
+#define TPI_ITFTTD0_ATB_IF2_ATVALID_Pos 29U /*!< TPI ITFTTD0: ATB Interface 2 ATVALIDPosition */\r
+#define TPI_ITFTTD0_ATB_IF2_ATVALID_Msk (0x3UL << TPI_ITFTTD0_ATB_IF2_ATVALID_Pos) /*!< TPI ITFTTD0: ATB Interface 2 ATVALID Mask */\r
+\r
+#define TPI_ITFTTD0_ATB_IF2_bytecount_Pos 27U /*!< TPI ITFTTD0: ATB Interface 2 byte count Position */\r
+#define TPI_ITFTTD0_ATB_IF2_bytecount_Msk (0x3UL << TPI_ITFTTD0_ATB_IF2_bytecount_Pos) /*!< TPI ITFTTD0: ATB Interface 2 byte count Mask */\r
+\r
+#define TPI_ITFTTD0_ATB_IF1_ATVALID_Pos 26U /*!< TPI ITFTTD0: ATB Interface 1 ATVALID Position */\r
+#define TPI_ITFTTD0_ATB_IF1_ATVALID_Msk (0x3UL << TPI_ITFTTD0_ATB_IF1_ATVALID_Pos) /*!< TPI ITFTTD0: ATB Interface 1 ATVALID Mask */\r
+\r
+#define TPI_ITFTTD0_ATB_IF1_bytecount_Pos 24U /*!< TPI ITFTTD0: ATB Interface 1 byte count Position */\r
+#define TPI_ITFTTD0_ATB_IF1_bytecount_Msk (0x3UL << TPI_ITFTTD0_ATB_IF1_bytecount_Pos) /*!< TPI ITFTTD0: ATB Interface 1 byte countt Mask */\r
+\r
+#define TPI_ITFTTD0_ATB_IF1_data2_Pos 16U /*!< TPI ITFTTD0: ATB Interface 1 data2 Position */\r
+#define TPI_ITFTTD0_ATB_IF1_data2_Msk (0xFFUL << TPI_ITFTTD0_ATB_IF1_data1_Pos) /*!< TPI ITFTTD0: ATB Interface 1 data2 Mask */\r
+\r
+#define TPI_ITFTTD0_ATB_IF1_data1_Pos 8U /*!< TPI ITFTTD0: ATB Interface 1 data1 Position */\r
+#define TPI_ITFTTD0_ATB_IF1_data1_Msk (0xFFUL << TPI_ITFTTD0_ATB_IF1_data1_Pos) /*!< TPI ITFTTD0: ATB Interface 1 data1 Mask */\r
+\r
+#define TPI_ITFTTD0_ATB_IF1_data0_Pos 0U /*!< TPI ITFTTD0: ATB Interface 1 data0 Position */\r
+#define TPI_ITFTTD0_ATB_IF1_data0_Msk (0xFFUL /*<< TPI_ITFTTD0_ATB_IF1_data0_Pos*/) /*!< TPI ITFTTD0: ATB Interface 1 data0 Mask */\r
+\r
+/* TPI Integration Test ATB Control Register 2 Register Definitions */\r
+#define TPI_ITATBCTR2_AFVALID2S_Pos 1U /*!< TPI ITATBCTR2: AFVALID2S Position */\r
+#define TPI_ITATBCTR2_AFVALID2S_Msk (0x1UL << TPI_ITATBCTR2_AFVALID2S_Pos) /*!< TPI ITATBCTR2: AFVALID2SS Mask */\r
+\r
+#define TPI_ITATBCTR2_AFVALID1S_Pos 1U /*!< TPI ITATBCTR2: AFVALID1S Position */\r
+#define TPI_ITATBCTR2_AFVALID1S_Msk (0x1UL << TPI_ITATBCTR2_AFVALID1S_Pos) /*!< TPI ITATBCTR2: AFVALID1SS Mask */\r
+\r
+#define TPI_ITATBCTR2_ATREADY2S_Pos 0U /*!< TPI ITATBCTR2: ATREADY2S Position */\r
+#define TPI_ITATBCTR2_ATREADY2S_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY2S_Pos*/) /*!< TPI ITATBCTR2: ATREADY2S Mask */\r
+\r
+#define TPI_ITATBCTR2_ATREADY1S_Pos 0U /*!< TPI ITATBCTR2: ATREADY1S Position */\r
+#define TPI_ITATBCTR2_ATREADY1S_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY1S_Pos*/) /*!< TPI ITATBCTR2: ATREADY1S Mask */\r
+\r
+/* TPI Integration Test FIFO Test Data 1 Register Definitions */\r
+#define TPI_ITFTTD1_ATB_IF2_ATVALID_Pos 29U /*!< TPI ITFTTD1: ATB Interface 2 ATVALID Position */\r
+#define TPI_ITFTTD1_ATB_IF2_ATVALID_Msk (0x3UL << TPI_ITFTTD1_ATB_IF2_ATVALID_Pos) /*!< TPI ITFTTD1: ATB Interface 2 ATVALID Mask */\r
+\r
+#define TPI_ITFTTD1_ATB_IF2_bytecount_Pos 27U /*!< TPI ITFTTD1: ATB Interface 2 byte count Position */\r
+#define TPI_ITFTTD1_ATB_IF2_bytecount_Msk (0x3UL << TPI_ITFTTD1_ATB_IF2_bytecount_Pos) /*!< TPI ITFTTD1: ATB Interface 2 byte count Mask */\r
+\r
+#define TPI_ITFTTD1_ATB_IF1_ATVALID_Pos 26U /*!< TPI ITFTTD1: ATB Interface 1 ATVALID Position */\r
+#define TPI_ITFTTD1_ATB_IF1_ATVALID_Msk (0x3UL << TPI_ITFTTD1_ATB_IF1_ATVALID_Pos) /*!< TPI ITFTTD1: ATB Interface 1 ATVALID Mask */\r
+\r
+#define TPI_ITFTTD1_ATB_IF1_bytecount_Pos 24U /*!< TPI ITFTTD1: ATB Interface 1 byte count Position */\r
+#define TPI_ITFTTD1_ATB_IF1_bytecount_Msk (0x3UL << TPI_ITFTTD1_ATB_IF1_bytecount_Pos) /*!< TPI ITFTTD1: ATB Interface 1 byte countt Mask */\r
+\r
+#define TPI_ITFTTD1_ATB_IF2_data2_Pos 16U /*!< TPI ITFTTD1: ATB Interface 2 data2 Position */\r
+#define TPI_ITFTTD1_ATB_IF2_data2_Msk (0xFFUL << TPI_ITFTTD1_ATB_IF2_data1_Pos) /*!< TPI ITFTTD1: ATB Interface 2 data2 Mask */\r
+\r
+#define TPI_ITFTTD1_ATB_IF2_data1_Pos 8U /*!< TPI ITFTTD1: ATB Interface 2 data1 Position */\r
+#define TPI_ITFTTD1_ATB_IF2_data1_Msk (0xFFUL << TPI_ITFTTD1_ATB_IF2_data1_Pos) /*!< TPI ITFTTD1: ATB Interface 2 data1 Mask */\r
+\r
+#define TPI_ITFTTD1_ATB_IF2_data0_Pos 0U /*!< TPI ITFTTD1: ATB Interface 2 data0 Position */\r
+#define TPI_ITFTTD1_ATB_IF2_data0_Msk (0xFFUL /*<< TPI_ITFTTD1_ATB_IF2_data0_Pos*/) /*!< TPI ITFTTD1: ATB Interface 2 data0 Mask */\r
+\r
+/* TPI Integration Test ATB Control Register 0 Definitions */\r
+#define TPI_ITATBCTR0_AFVALID2S_Pos 1U /*!< TPI ITATBCTR0: AFVALID2S Position */\r
+#define TPI_ITATBCTR0_AFVALID2S_Msk (0x1UL << TPI_ITATBCTR0_AFVALID2S_Pos) /*!< TPI ITATBCTR0: AFVALID2SS Mask */\r
+\r
+#define TPI_ITATBCTR0_AFVALID1S_Pos 1U /*!< TPI ITATBCTR0: AFVALID1S Position */\r
+#define TPI_ITATBCTR0_AFVALID1S_Msk (0x1UL << TPI_ITATBCTR0_AFVALID1S_Pos) /*!< TPI ITATBCTR0: AFVALID1SS Mask */\r
+\r
+#define TPI_ITATBCTR0_ATREADY2S_Pos 0U /*!< TPI ITATBCTR0: ATREADY2S Position */\r
+#define TPI_ITATBCTR0_ATREADY2S_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY2S_Pos*/) /*!< TPI ITATBCTR0: ATREADY2S Mask */\r
+\r
+#define TPI_ITATBCTR0_ATREADY1S_Pos 0U /*!< TPI ITATBCTR0: ATREADY1S Position */\r
+#define TPI_ITATBCTR0_ATREADY1S_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY1S_Pos*/) /*!< TPI ITATBCTR0: ATREADY1S Mask */\r
+\r
+/* TPI Integration Mode Control Register Definitions */\r
+#define TPI_ITCTRL_Mode_Pos 0U /*!< TPI ITCTRL: Mode Position */\r
+#define TPI_ITCTRL_Mode_Msk (0x3UL /*<< TPI_ITCTRL_Mode_Pos*/) /*!< TPI ITCTRL: Mode Mask */\r
+\r
+/* TPI DEVID Register Definitions */\r
+#define TPI_DEVID_NRZVALID_Pos 11U /*!< TPI DEVID: NRZVALID Position */\r
+#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */\r
+\r
+#define TPI_DEVID_MANCVALID_Pos 10U /*!< TPI DEVID: MANCVALID Position */\r
+#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */\r
+\r
+#define TPI_DEVID_PTINVALID_Pos 9U /*!< TPI DEVID: PTINVALID Position */\r
+#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */\r
+\r
+#define TPI_DEVID_FIFOSZ_Pos 6U /*!< TPI DEVID: FIFOSZ Position */\r
+#define TPI_DEVID_FIFOSZ_Msk (0x7UL << TPI_DEVID_FIFOSZ_Pos) /*!< TPI DEVID: FIFOSZ Mask */\r
+\r
+#define TPI_DEVID_NrTraceInput_Pos 0U /*!< TPI DEVID: NrTraceInput Position */\r
+#define TPI_DEVID_NrTraceInput_Msk (0x3FUL /*<< TPI_DEVID_NrTraceInput_Pos*/) /*!< TPI DEVID: NrTraceInput Mask */\r
+\r
+/* TPI DEVTYPE Register Definitions */\r
+#define TPI_DEVTYPE_SubType_Pos 4U /*!< TPI DEVTYPE: SubType Position */\r
+#define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */\r
+\r
+#define TPI_DEVTYPE_MajorType_Pos 0U /*!< TPI DEVTYPE: MajorType Position */\r
+#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */\r
+\r
+/*@}*/ /* end of group CMSIS_TPI */\r
+\r
+\r
+#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)\r
+/**\r
+ \ingroup CMSIS_core_register\r
+ \defgroup CMSIS_MPU Memory Protection Unit (MPU)\r
+ \brief Type definitions for the Memory Protection Unit (MPU)\r
+ @{\r
+ */\r
+\r
+/**\r
+ \brief Structure type to access the Memory Protection Unit (MPU).\r
+ */\r
+typedef struct\r
+{\r
+ __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */\r
+ __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */\r
+ __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region Number Register */\r
+ __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */\r
+ __IOM uint32_t RLAR; /*!< Offset: 0x010 (R/W) MPU Region Limit Address Register */\r
+ uint32_t RESERVED0[7U];\r
+ union {\r
+ __IOM uint32_t MAIR[2];\r
+ struct {\r
+ __IOM uint32_t MAIR0; /*!< Offset: 0x030 (R/W) MPU Memory Attribute Indirection Register 0 */\r
+ __IOM uint32_t MAIR1; /*!< Offset: 0x034 (R/W) MPU Memory Attribute Indirection Register 1 */\r
+ };\r
+ };\r
+} MPU_Type;\r
+\r
+#define MPU_TYPE_RALIASES 1U\r
+\r
+/* MPU Type Register Definitions */\r
+#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */\r
+#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */\r
+\r
+#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */\r
+#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */\r
+\r
+#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */\r
+#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */\r
+\r
+/* MPU Control Register Definitions */\r
+#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */\r
+#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */\r
+\r
+#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */\r
+#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */\r
+\r
+#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */\r
+#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */\r
+\r
+/* MPU Region Number Register Definitions */\r
+#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */\r
+#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */\r
+\r
+/* MPU Region Base Address Register Definitions */\r
+#define MPU_RBAR_BASE_Pos 5U /*!< MPU RBAR: BASE Position */\r
+#define MPU_RBAR_BASE_Msk (0x7FFFFFFUL << MPU_RBAR_BASE_Pos) /*!< MPU RBAR: BASE Mask */\r
+\r
+#define MPU_RBAR_SH_Pos 3U /*!< MPU RBAR: SH Position */\r
+#define MPU_RBAR_SH_Msk (0x3UL << MPU_RBAR_SH_Pos) /*!< MPU RBAR: SH Mask */\r
+\r
+#define MPU_RBAR_AP_Pos 1U /*!< MPU RBAR: AP Position */\r
+#define MPU_RBAR_AP_Msk (0x3UL << MPU_RBAR_AP_Pos) /*!< MPU RBAR: AP Mask */\r
+\r
+#define MPU_RBAR_XN_Pos 0U /*!< MPU RBAR: XN Position */\r
+#define MPU_RBAR_XN_Msk (01UL /*<< MPU_RBAR_XN_Pos*/) /*!< MPU RBAR: XN Mask */\r
+\r
+/* MPU Region Limit Address Register Definitions */\r
+#define MPU_RLAR_LIMIT_Pos 5U /*!< MPU RLAR: LIMIT Position */\r
+#define MPU_RLAR_LIMIT_Msk (0x7FFFFFFUL << MPU_RLAR_LIMIT_Pos) /*!< MPU RLAR: LIMIT Mask */\r
+\r
+#define MPU_RLAR_AttrIndx_Pos 1U /*!< MPU RLAR: AttrIndx Position */\r
+#define MPU_RLAR_AttrIndx_Msk (0x7UL << MPU_RLAR_AttrIndx_Pos) /*!< MPU RLAR: AttrIndx Mask */\r
+\r
+#define MPU_RLAR_EN_Pos 0U /*!< MPU RLAR: EN Position */\r
+#define MPU_RLAR_EN_Msk (1UL /*<< MPU_RLAR_EN_Pos*/) /*!< MPU RLAR: EN Mask */\r
+\r
+/* MPU Memory Attribute Indirection Register 0 Definitions */\r
+#define MPU_MAIR0_Attr3_Pos 24U /*!< MPU MAIR0: Attr3 Position */\r
+#define MPU_MAIR0_Attr3_Msk (0xFFUL << MPU_MAIR0_Attr3_Pos) /*!< MPU MAIR0: Attr3 Mask */\r
+\r
+#define MPU_MAIR0_Attr2_Pos 16U /*!< MPU MAIR0: Attr2 Position */\r
+#define MPU_MAIR0_Attr2_Msk (0xFFUL << MPU_MAIR0_Attr2_Pos) /*!< MPU MAIR0: Attr2 Mask */\r
+\r
+#define MPU_MAIR0_Attr1_Pos 8U /*!< MPU MAIR0: Attr1 Position */\r
+#define MPU_MAIR0_Attr1_Msk (0xFFUL << MPU_MAIR0_Attr1_Pos) /*!< MPU MAIR0: Attr1 Mask */\r
+\r
+#define MPU_MAIR0_Attr0_Pos 0U /*!< MPU MAIR0: Attr0 Position */\r
+#define MPU_MAIR0_Attr0_Msk (0xFFUL /*<< MPU_MAIR0_Attr0_Pos*/) /*!< MPU MAIR0: Attr0 Mask */\r
+\r
+/* MPU Memory Attribute Indirection Register 1 Definitions */\r
+#define MPU_MAIR1_Attr7_Pos 24U /*!< MPU MAIR1: Attr7 Position */\r
+#define MPU_MAIR1_Attr7_Msk (0xFFUL << MPU_MAIR1_Attr7_Pos) /*!< MPU MAIR1: Attr7 Mask */\r
+\r
+#define MPU_MAIR1_Attr6_Pos 16U /*!< MPU MAIR1: Attr6 Position */\r
+#define MPU_MAIR1_Attr6_Msk (0xFFUL << MPU_MAIR1_Attr6_Pos) /*!< MPU MAIR1: Attr6 Mask */\r
+\r
+#define MPU_MAIR1_Attr5_Pos 8U /*!< MPU MAIR1: Attr5 Position */\r
+#define MPU_MAIR1_Attr5_Msk (0xFFUL << MPU_MAIR1_Attr5_Pos) /*!< MPU MAIR1: Attr5 Mask */\r
+\r
+#define MPU_MAIR1_Attr4_Pos 0U /*!< MPU MAIR1: Attr4 Position */\r
+#define MPU_MAIR1_Attr4_Msk (0xFFUL /*<< MPU_MAIR1_Attr4_Pos*/) /*!< MPU MAIR1: Attr4 Mask */\r
+\r
+/*@} end of group CMSIS_MPU */\r
+#endif\r
+\r
+\r
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)\r
+/**\r
+ \ingroup CMSIS_core_register\r
+ \defgroup CMSIS_SAU Security Attribution Unit (SAU)\r
+ \brief Type definitions for the Security Attribution Unit (SAU)\r
+ @{\r
+ */\r
+\r
+/**\r
+ \brief Structure type to access the Security Attribution Unit (SAU).\r
+ */\r
+typedef struct\r
+{\r
+ __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SAU Control Register */\r
+ __IM uint32_t TYPE; /*!< Offset: 0x004 (R/ ) SAU Type Register */\r
+#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U)\r
+ __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) SAU Region Number Register */\r
+ __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) SAU Region Base Address Register */\r
+ __IOM uint32_t RLAR; /*!< Offset: 0x010 (R/W) SAU Region Limit Address Register */\r
+#endif\r
+} SAU_Type;\r
+\r
+/* SAU Control Register Definitions */\r
+#define SAU_CTRL_ALLNS_Pos 1U /*!< SAU CTRL: ALLNS Position */\r
+#define SAU_CTRL_ALLNS_Msk (1UL << SAU_CTRL_ALLNS_Pos) /*!< SAU CTRL: ALLNS Mask */\r
+\r
+#define SAU_CTRL_ENABLE_Pos 0U /*!< SAU CTRL: ENABLE Position */\r
+#define SAU_CTRL_ENABLE_Msk (1UL /*<< SAU_CTRL_ENABLE_Pos*/) /*!< SAU CTRL: ENABLE Mask */\r
+\r
+/* SAU Type Register Definitions */\r
+#define SAU_TYPE_SREGION_Pos 0U /*!< SAU TYPE: SREGION Position */\r
+#define SAU_TYPE_SREGION_Msk (0xFFUL /*<< SAU_TYPE_SREGION_Pos*/) /*!< SAU TYPE: SREGION Mask */\r
+\r
+#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U)\r
+/* SAU Region Number Register Definitions */\r
+#define SAU_RNR_REGION_Pos 0U /*!< SAU RNR: REGION Position */\r
+#define SAU_RNR_REGION_Msk (0xFFUL /*<< SAU_RNR_REGION_Pos*/) /*!< SAU RNR: REGION Mask */\r
+\r
+/* SAU Region Base Address Register Definitions */\r
+#define SAU_RBAR_BADDR_Pos 5U /*!< SAU RBAR: BADDR Position */\r
+#define SAU_RBAR_BADDR_Msk (0x7FFFFFFUL << SAU_RBAR_BADDR_Pos) /*!< SAU RBAR: BADDR Mask */\r
+\r
+/* SAU Region Limit Address Register Definitions */\r
+#define SAU_RLAR_LADDR_Pos 5U /*!< SAU RLAR: LADDR Position */\r
+#define SAU_RLAR_LADDR_Msk (0x7FFFFFFUL << SAU_RLAR_LADDR_Pos) /*!< SAU RLAR: LADDR Mask */\r
+\r
+#define SAU_RLAR_NSC_Pos 1U /*!< SAU RLAR: NSC Position */\r
+#define SAU_RLAR_NSC_Msk (1UL << SAU_RLAR_NSC_Pos) /*!< SAU RLAR: NSC Mask */\r
+\r
+#define SAU_RLAR_ENABLE_Pos 0U /*!< SAU RLAR: ENABLE Position */\r
+#define SAU_RLAR_ENABLE_Msk (1UL /*<< SAU_RLAR_ENABLE_Pos*/) /*!< SAU RLAR: ENABLE Mask */\r
+\r
+#endif /* defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) */\r
+\r
+/*@} end of group CMSIS_SAU */\r
+#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */\r
+\r
+\r
+/**\r
+ \ingroup CMSIS_core_register\r
+ \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug)\r
+ \brief Type definitions for the Core Debug Registers\r
+ @{\r
+ */\r
+\r
+/**\r
+ \brief Structure type to access the Core Debug Register (CoreDebug).\r
+ */\r
+typedef struct\r
+{\r
+ __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */\r
+ __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */\r
+ __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */\r
+ __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */\r
+ uint32_t RESERVED4[1U];\r
+ __IOM uint32_t DAUTHCTRL; /*!< Offset: 0x014 (R/W) Debug Authentication Control Register */\r
+ __IOM uint32_t DSCSR; /*!< Offset: 0x018 (R/W) Debug Security Control and Status Register */\r
+} CoreDebug_Type;\r
+\r
+/* Debug Halting Control and Status Register Definitions */\r
+#define CoreDebug_DHCSR_DBGKEY_Pos 16U /*!< CoreDebug DHCSR: DBGKEY Position */\r
+#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */\r
+\r
+#define CoreDebug_DHCSR_S_RESTART_ST_Pos 26U /*!< CoreDebug DHCSR: S_RESTART_ST Position */\r
+#define CoreDebug_DHCSR_S_RESTART_ST_Msk (1UL << CoreDebug_DHCSR_S_RESTART_ST_Pos) /*!< CoreDebug DHCSR: S_RESTART_ST Mask */\r
+\r
+#define CoreDebug_DHCSR_S_RESET_ST_Pos 25U /*!< CoreDebug DHCSR: S_RESET_ST Position */\r
+#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */\r
+\r
+#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U /*!< CoreDebug DHCSR: S_RETIRE_ST Position */\r
+#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */\r
+\r
+#define CoreDebug_DHCSR_S_LOCKUP_Pos 19U /*!< CoreDebug DHCSR: S_LOCKUP Position */\r
+#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */\r
+\r
+#define CoreDebug_DHCSR_S_SLEEP_Pos 18U /*!< CoreDebug DHCSR: S_SLEEP Position */\r
+#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */\r
+\r
+#define CoreDebug_DHCSR_S_HALT_Pos 17U /*!< CoreDebug DHCSR: S_HALT Position */\r
+#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */\r
+\r
+#define CoreDebug_DHCSR_S_REGRDY_Pos 16U /*!< CoreDebug DHCSR: S_REGRDY Position */\r
+#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */\r
+\r
+#define CoreDebug_DHCSR_C_MASKINTS_Pos 3U /*!< CoreDebug DHCSR: C_MASKINTS Position */\r
+#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */\r
+\r
+#define CoreDebug_DHCSR_C_STEP_Pos 2U /*!< CoreDebug DHCSR: C_STEP Position */\r
+#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */\r
+\r
+#define CoreDebug_DHCSR_C_HALT_Pos 1U /*!< CoreDebug DHCSR: C_HALT Position */\r
+#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */\r
+\r
+#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U /*!< CoreDebug DHCSR: C_DEBUGEN Position */\r
+#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */\r
+\r
+/* Debug Core Register Selector Register Definitions */\r
+#define CoreDebug_DCRSR_REGWnR_Pos 16U /*!< CoreDebug DCRSR: REGWnR Position */\r
+#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */\r
+\r
+#define CoreDebug_DCRSR_REGSEL_Pos 0U /*!< CoreDebug DCRSR: REGSEL Position */\r
+#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/) /*!< CoreDebug DCRSR: REGSEL Mask */\r
+\r
+/* Debug Exception and Monitor Control Register */\r
+#define CoreDebug_DEMCR_DWTENA_Pos 24U /*!< CoreDebug DEMCR: DWTENA Position */\r
+#define CoreDebug_DEMCR_DWTENA_Msk (1UL << CoreDebug_DEMCR_DWTENA_Pos) /*!< CoreDebug DEMCR: DWTENA Mask */\r
+\r
+#define CoreDebug_DEMCR_VC_HARDERR_Pos 10U /*!< CoreDebug DEMCR: VC_HARDERR Position */\r
+#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */\r
+\r
+#define CoreDebug_DEMCR_VC_CORERESET_Pos 0U /*!< CoreDebug DEMCR: VC_CORERESET Position */\r
+#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/) /*!< CoreDebug DEMCR: VC_CORERESET Mask */\r
+\r
+/* Debug Authentication Control Register Definitions */\r
+#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos 3U /*!< CoreDebug DAUTHCTRL: INTSPNIDEN, Position */\r
+#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos) /*!< CoreDebug DAUTHCTRL: INTSPNIDEN, Mask */\r
+\r
+#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos 2U /*!< CoreDebug DAUTHCTRL: SPNIDENSEL Position */\r
+#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Msk (1UL << CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos) /*!< CoreDebug DAUTHCTRL: SPNIDENSEL Mask */\r
+\r
+#define CoreDebug_DAUTHCTRL_INTSPIDEN_Pos 1U /*!< CoreDebug DAUTHCTRL: INTSPIDEN Position */\r
+#define CoreDebug_DAUTHCTRL_INTSPIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPIDEN_Pos) /*!< CoreDebug DAUTHCTRL: INTSPIDEN Mask */\r
+\r
+#define CoreDebug_DAUTHCTRL_SPIDENSEL_Pos 0U /*!< CoreDebug DAUTHCTRL: SPIDENSEL Position */\r
+#define CoreDebug_DAUTHCTRL_SPIDENSEL_Msk (1UL /*<< CoreDebug_DAUTHCTRL_SPIDENSEL_Pos*/) /*!< CoreDebug DAUTHCTRL: SPIDENSEL Mask */\r
+\r
+/* Debug Security Control and Status Register Definitions */\r
+#define CoreDebug_DSCSR_CDS_Pos 16U /*!< CoreDebug DSCSR: CDS Position */\r
+#define CoreDebug_DSCSR_CDS_Msk (1UL << CoreDebug_DSCSR_CDS_Pos) /*!< CoreDebug DSCSR: CDS Mask */\r
+\r
+#define CoreDebug_DSCSR_SBRSEL_Pos 1U /*!< CoreDebug DSCSR: SBRSEL Position */\r
+#define CoreDebug_DSCSR_SBRSEL_Msk (1UL << CoreDebug_DSCSR_SBRSEL_Pos) /*!< CoreDebug DSCSR: SBRSEL Mask */\r
+\r
+#define CoreDebug_DSCSR_SBRSELEN_Pos 0U /*!< CoreDebug DSCSR: SBRSELEN Position */\r
+#define CoreDebug_DSCSR_SBRSELEN_Msk (1UL /*<< CoreDebug_DSCSR_SBRSELEN_Pos*/) /*!< CoreDebug DSCSR: SBRSELEN Mask */\r
+\r
+/*@} end of group CMSIS_CoreDebug */\r
+\r
+\r
+/**\r
+ \ingroup CMSIS_core_register\r
+ \defgroup CMSIS_core_bitfield Core register bit field macros\r
+ \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk).\r
+ @{\r
+ */\r
+\r
+/**\r
+ \brief Mask and shift a bit field value for use in a register bit range.\r
+ \param[in] field Name of the register bit field.\r
+ \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type.\r
+ \return Masked and shifted value.\r
+*/\r
+#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk)\r
+\r
+/**\r
+ \brief Mask and shift a register value to extract a bit filed value.\r
+ \param[in] field Name of the register bit field.\r
+ \param[in] value Value of register. This parameter is interpreted as an uint32_t type.\r
+ \return Masked and shifted bit field value.\r
+*/\r
+#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos)\r
+\r
+/*@} end of group CMSIS_core_bitfield */\r
+\r
+\r
+/**\r
+ \ingroup CMSIS_core_register\r
+ \defgroup CMSIS_core_base Core Definitions\r
+ \brief Definitions for base addresses, unions, and structures.\r
+ @{\r
+ */\r
+\r
+/* Memory mapping of Core Hardware */\r
+ #define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */\r
+ #define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */\r
+ #define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */\r
+ #define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */\r
+ #define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */\r
+ #define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */\r
+ #define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */\r
+\r
+\r
+ #define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */\r
+ #define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */\r
+ #define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */\r
+ #define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */\r
+ #define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */\r
+ #define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE ) /*!< Core Debug configuration struct */\r
+\r
+ #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)\r
+ #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */\r
+ #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */\r
+ #endif\r
+\r
+ #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)\r
+ #define SAU_BASE (SCS_BASE + 0x0DD0UL) /*!< Security Attribution Unit */\r
+ #define SAU ((SAU_Type *) SAU_BASE ) /*!< Security Attribution Unit */\r
+ #endif\r
+\r
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)\r
+ #define SCS_BASE_NS (0xE002E000UL) /*!< System Control Space Base Address (non-secure address space) */\r
+ #define CoreDebug_BASE_NS (0xE002EDF0UL) /*!< Core Debug Base Address (non-secure address space) */\r
+ #define SysTick_BASE_NS (SCS_BASE_NS + 0x0010UL) /*!< SysTick Base Address (non-secure address space) */\r
+ #define NVIC_BASE_NS (SCS_BASE_NS + 0x0100UL) /*!< NVIC Base Address (non-secure address space) */\r
+ #define SCB_BASE_NS (SCS_BASE_NS + 0x0D00UL) /*!< System Control Block Base Address (non-secure address space) */\r
+\r
+ #define SCB_NS ((SCB_Type *) SCB_BASE_NS ) /*!< SCB configuration struct (non-secure address space) */\r
+ #define SysTick_NS ((SysTick_Type *) SysTick_BASE_NS ) /*!< SysTick configuration struct (non-secure address space) */\r
+ #define NVIC_NS ((NVIC_Type *) NVIC_BASE_NS ) /*!< NVIC configuration struct (non-secure address space) */\r
+ #define CoreDebug_NS ((CoreDebug_Type *) CoreDebug_BASE_NS) /*!< Core Debug configuration struct (non-secure address space) */\r
+\r
+ #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)\r
+ #define MPU_BASE_NS (SCS_BASE_NS + 0x0D90UL) /*!< Memory Protection Unit (non-secure address space) */\r
+ #define MPU_NS ((MPU_Type *) MPU_BASE_NS ) /*!< Memory Protection Unit (non-secure address space) */\r
+ #endif\r
+\r
+#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */\r
+/*@} */\r
+\r
+\r
+\r
+/*******************************************************************************\r
+ * Hardware Abstraction Layer\r
+ Core Function Interface contains:\r
+ - Core NVIC Functions\r
+ - Core SysTick Functions\r
+ - Core Register Access Functions\r
+ ******************************************************************************/\r
+/**\r
+ \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference\r
+*/\r
+\r
+\r
+\r
+/* ########################## NVIC functions #################################### */\r
+/**\r
+ \ingroup CMSIS_Core_FunctionInterface\r
+ \defgroup CMSIS_Core_NVICFunctions NVIC Functions\r
+ \brief Functions that manage interrupts and exceptions via the NVIC.\r
+ @{\r
+ */\r
+\r
+#ifdef CMSIS_NVIC_VIRTUAL\r
+ #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE\r
+ #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h"\r
+ #endif\r
+ #include CMSIS_NVIC_VIRTUAL_HEADER_FILE\r
+#else\r
+/*#define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping not available for Cortex-M23 */\r
+/*#define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping not available for Cortex-M23 */\r
+ #define NVIC_EnableIRQ __NVIC_EnableIRQ\r
+ #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ\r
+ #define NVIC_DisableIRQ __NVIC_DisableIRQ\r
+ #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ\r
+ #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ\r
+ #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ\r
+ #define NVIC_GetActive __NVIC_GetActive\r
+ #define NVIC_SetPriority __NVIC_SetPriority\r
+ #define NVIC_GetPriority __NVIC_GetPriority\r
+ #define NVIC_SystemReset __NVIC_SystemReset\r
+#endif /* CMSIS_NVIC_VIRTUAL */\r
+\r
+#ifdef CMSIS_VECTAB_VIRTUAL\r
+ #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE\r
+ #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h"\r
+ #endif\r
+ #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE\r
+#else\r
+ #define NVIC_SetVector __NVIC_SetVector\r
+ #define NVIC_GetVector __NVIC_GetVector\r
+#endif /* (CMSIS_VECTAB_VIRTUAL) */\r
+\r
+#define NVIC_USER_IRQ_OFFSET 16\r
+\r
+\r
+/* Special LR values for Secure/Non-Secure call handling and exception handling */\r
+\r
+/* Function Return Payload (from ARMv8-M Architecture Reference Manual) LR value on entry from Secure BLXNS */ \r
+#define FNC_RETURN (0xFEFFFFFFUL) /* bit [0] ignored when processing a branch */\r
+\r
+/* The following EXC_RETURN mask values are used to evaluate the LR on exception entry */\r
+#define EXC_RETURN_PREFIX (0xFF000000UL) /* bits [31:24] set to indicate an EXC_RETURN value */\r
+#define EXC_RETURN_S (0x00000040UL) /* bit [6] stack used to push registers: 0=Non-secure 1=Secure */\r
+#define EXC_RETURN_DCRS (0x00000020UL) /* bit [5] stacking rules for called registers: 0=skipped 1=saved */\r
+#define EXC_RETURN_FTYPE (0x00000010UL) /* bit [4] allocate stack for floating-point context: 0=done 1=skipped */\r
+#define EXC_RETURN_MODE (0x00000008UL) /* bit [3] processor mode for return: 0=Handler mode 1=Thread mode */\r
+#define EXC_RETURN_SPSEL (0x00000002UL) /* bit [1] stack pointer used to restore context: 0=MSP 1=PSP */\r
+#define EXC_RETURN_ES (0x00000001UL) /* bit [0] security state exception was taken to: 0=Non-secure 1=Secure */\r
+\r
+/* Integrity Signature (from ARMv8-M Architecture Reference Manual) for exception context stacking */\r
+#if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) /* Value for processors with floating-point extension: */\r
+#define EXC_INTEGRITY_SIGNATURE (0xFEFA125AUL) /* bit [0] SFTC must match LR bit[4] EXC_RETURN_FTYPE */\r
+#else \r
+#define EXC_INTEGRITY_SIGNATURE (0xFEFA125BUL) /* Value for processors without floating-point extension */\r
+#endif\r
+\r
+ \r
+/* Interrupt Priorities are WORD accessible only under Armv6-M */\r
+/* The following MACROS handle generation of the register offset and byte masks */\r
+#define _BIT_SHIFT(IRQn) ( ((((uint32_t)(int32_t)(IRQn)) ) & 0x03UL) * 8UL)\r
+#define _SHP_IDX(IRQn) ( (((((uint32_t)(int32_t)(IRQn)) & 0x0FUL)-8UL) >> 2UL) )\r
+#define _IP_IDX(IRQn) ( (((uint32_t)(int32_t)(IRQn)) >> 2UL) )\r
+\r
+#define __NVIC_SetPriorityGrouping(X) (void)(X)\r
+#define __NVIC_GetPriorityGrouping() (0U)\r
+\r
+/**\r
+ \brief Enable Interrupt\r
+ \details Enables a device specific interrupt in the NVIC interrupt controller.\r
+ \param [in] IRQn Device specific interrupt number.\r
+ \note IRQn must not be negative.\r
+ */\r
+__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn)\r
+{\r
+ if ((int32_t)(IRQn) >= 0)\r
+ {\r
+ NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));\r
+ }\r
+}\r
+\r
+\r
+/**\r
+ \brief Get Interrupt Enable status\r
+ \details Returns a device specific interrupt enable status from the NVIC interrupt controller.\r
+ \param [in] IRQn Device specific interrupt number.\r
+ \return 0 Interrupt is not enabled.\r
+ \return 1 Interrupt is enabled.\r
+ \note IRQn must not be negative.\r
+ */\r
+__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn)\r
+{\r
+ if ((int32_t)(IRQn) >= 0)\r
+ {\r
+ return((uint32_t)(((NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));\r
+ }\r
+ else\r
+ {\r
+ return(0U);\r
+ }\r
+}\r
+\r
+\r
+/**\r
+ \brief Disable Interrupt\r
+ \details Disables a device specific interrupt in the NVIC interrupt controller.\r
+ \param [in] IRQn Device specific interrupt number.\r
+ \note IRQn must not be negative.\r
+ */\r
+__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn)\r
+{\r
+ if ((int32_t)(IRQn) >= 0)\r
+ {\r
+ NVIC->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));\r
+ __DSB();\r
+ __ISB();\r
+ }\r
+}\r
+\r
+\r
+/**\r
+ \brief Get Pending Interrupt\r
+ \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt.\r
+ \param [in] IRQn Device specific interrupt number.\r
+ \return 0 Interrupt status is not pending.\r
+ \return 1 Interrupt status is pending.\r
+ \note IRQn must not be negative.\r
+ */\r
+__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn)\r
+{\r
+ if ((int32_t)(IRQn) >= 0)\r
+ {\r
+ return((uint32_t)(((NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));\r
+ }\r
+ else\r
+ {\r
+ return(0U);\r
+ }\r
+}\r
+\r
+\r
+/**\r
+ \brief Set Pending Interrupt\r
+ \details Sets the pending bit of a device specific interrupt in the NVIC pending register.\r
+ \param [in] IRQn Device specific interrupt number.\r
+ \note IRQn must not be negative.\r
+ */\r
+__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn)\r
+{\r
+ if ((int32_t)(IRQn) >= 0)\r
+ {\r
+ NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));\r
+ }\r
+}\r
+\r
+\r
+/**\r
+ \brief Clear Pending Interrupt\r
+ \details Clears the pending bit of a device specific interrupt in the NVIC pending register.\r
+ \param [in] IRQn Device specific interrupt number.\r
+ \note IRQn must not be negative.\r
+ */\r
+__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn)\r
+{\r
+ if ((int32_t)(IRQn) >= 0)\r
+ {\r
+ NVIC->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));\r
+ }\r
+}\r
+\r
+\r
+/**\r
+ \brief Get Active Interrupt\r
+ \details Reads the active register in the NVIC and returns the active bit for the device specific interrupt.\r
+ \param [in] IRQn Device specific interrupt number.\r
+ \return 0 Interrupt status is not active.\r
+ \return 1 Interrupt status is active.\r
+ \note IRQn must not be negative.\r
+ */\r
+__STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn)\r
+{\r
+ if ((int32_t)(IRQn) >= 0)\r
+ {\r
+ return((uint32_t)(((NVIC->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));\r
+ }\r
+ else\r
+ {\r
+ return(0U);\r
+ }\r
+}\r
+\r
+\r
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)\r
+/**\r
+ \brief Get Interrupt Target State\r
+ \details Reads the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt.\r
+ \param [in] IRQn Device specific interrupt number.\r
+ \return 0 if interrupt is assigned to Secure\r
+ \return 1 if interrupt is assigned to Non Secure\r
+ \note IRQn must not be negative.\r
+ */\r
+__STATIC_INLINE uint32_t NVIC_GetTargetState(IRQn_Type IRQn)\r
+{\r
+ if ((int32_t)(IRQn) >= 0)\r
+ {\r
+ return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));\r
+ }\r
+ else\r
+ {\r
+ return(0U);\r
+ }\r
+}\r
+\r
+\r
+/**\r
+ \brief Set Interrupt Target State\r
+ \details Sets the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt.\r
+ \param [in] IRQn Device specific interrupt number.\r
+ \return 0 if interrupt is assigned to Secure\r
+ 1 if interrupt is assigned to Non Secure\r
+ \note IRQn must not be negative.\r
+ */\r
+__STATIC_INLINE uint32_t NVIC_SetTargetState(IRQn_Type IRQn)\r
+{\r
+ if ((int32_t)(IRQn) >= 0)\r
+ {\r
+ NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] |= ((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)));\r
+ return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));\r
+ }\r
+ else\r
+ {\r
+ return(0U);\r
+ }\r
+}\r
+\r
+\r
+/**\r
+ \brief Clear Interrupt Target State\r
+ \details Clears the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt.\r
+ \param [in] IRQn Device specific interrupt number.\r
+ \return 0 if interrupt is assigned to Secure\r
+ 1 if interrupt is assigned to Non Secure\r
+ \note IRQn must not be negative.\r
+ */\r
+__STATIC_INLINE uint32_t NVIC_ClearTargetState(IRQn_Type IRQn)\r
+{\r
+ if ((int32_t)(IRQn) >= 0)\r
+ {\r
+ NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] &= ~((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)));\r
+ return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));\r
+ }\r
+ else\r
+ {\r
+ return(0U);\r
+ }\r
+}\r
+#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */\r
+\r
+\r
+/**\r
+ \brief Set Interrupt Priority\r
+ \details Sets the priority of a device specific interrupt or a processor exception.\r
+ The interrupt number can be positive to specify a device specific interrupt,\r
+ or negative to specify a processor exception.\r
+ \param [in] IRQn Interrupt number.\r
+ \param [in] priority Priority to set.\r
+ \note The priority cannot be set for every processor exception.\r
+ */\r
+__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)\r
+{\r
+ if ((int32_t)(IRQn) >= 0)\r
+ {\r
+ NVIC->IPR[_IP_IDX(IRQn)] = ((uint32_t)(NVIC->IPR[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |\r
+ (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));\r
+ }\r
+ else\r
+ {\r
+ SCB->SHPR[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHPR[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |\r
+ (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));\r
+ }\r
+}\r
+\r
+\r
+/**\r
+ \brief Get Interrupt Priority\r
+ \details Reads the priority of a device specific interrupt or a processor exception.\r
+ The interrupt number can be positive to specify a device specific interrupt,\r
+ or negative to specify a processor exception.\r
+ \param [in] IRQn Interrupt number.\r
+ \return Interrupt Priority.\r
+ Value is aligned automatically to the implemented priority bits of the microcontroller.\r
+ */\r
+__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn)\r
+{\r
+\r
+ if ((int32_t)(IRQn) >= 0)\r
+ {\r
+ return((uint32_t)(((NVIC->IPR[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));\r
+ }\r
+ else\r
+ {\r
+ return((uint32_t)(((SCB->SHPR[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));\r
+ }\r
+}\r
+\r
+\r
+/**\r
+ \brief Encode Priority\r
+ \details Encodes the priority for an interrupt with the given priority group,\r
+ preemptive priority value, and subpriority value.\r
+ In case of a conflict between priority grouping and available\r
+ priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.\r
+ \param [in] PriorityGroup Used priority group.\r
+ \param [in] PreemptPriority Preemptive priority value (starting from 0).\r
+ \param [in] SubPriority Subpriority value (starting from 0).\r
+ \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority().\r
+ */\r
+__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)\r
+{\r
+ uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */\r
+ uint32_t PreemptPriorityBits;\r
+ uint32_t SubPriorityBits;\r
+\r
+ PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);\r
+ SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));\r
+\r
+ return (\r
+ ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) |\r
+ ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL)))\r
+ );\r
+}\r
+\r
+\r
+/**\r
+ \brief Decode Priority\r
+ \details Decodes an interrupt priority value with a given priority group to\r
+ preemptive priority value and subpriority value.\r
+ In case of a conflict between priority grouping and available\r
+ priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set.\r
+ \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority().\r
+ \param [in] PriorityGroup Used priority group.\r
+ \param [out] pPreemptPriority Preemptive priority value (starting from 0).\r
+ \param [out] pSubPriority Subpriority value (starting from 0).\r
+ */\r
+__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority)\r
+{\r
+ uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */\r
+ uint32_t PreemptPriorityBits;\r
+ uint32_t SubPriorityBits;\r
+\r
+ PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);\r
+ SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));\r
+\r
+ *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL);\r
+ *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL);\r
+}\r
+\r
+\r
+/**\r
+ \brief Set Interrupt Vector\r
+ \details Sets an interrupt vector in SRAM based interrupt vector table.\r
+ The interrupt number can be positive to specify a device specific interrupt,\r
+ or negative to specify a processor exception.\r
+ VTOR must been relocated to SRAM before.\r
+ If VTOR is not present address 0 must be mapped to SRAM.\r
+ \param [in] IRQn Interrupt number\r
+ \param [in] vector Address of interrupt handler function\r
+ */\r
+__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector)\r
+{\r
+#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U)\r
+ uint32_t *vectors = (uint32_t *)SCB->VTOR;\r
+#else\r
+ uint32_t *vectors = (uint32_t *)0x0U;\r
+#endif\r
+ vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector;\r
+}\r
+\r
+\r
+/**\r
+ \brief Get Interrupt Vector\r
+ \details Reads an interrupt vector from interrupt vector table.\r
+ The interrupt number can be positive to specify a device specific interrupt,\r
+ or negative to specify a processor exception.\r
+ \param [in] IRQn Interrupt number.\r
+ \return Address of interrupt handler function\r
+ */\r
+__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn)\r
+{\r
+#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U)\r
+ uint32_t *vectors = (uint32_t *)SCB->VTOR;\r
+#else\r
+ uint32_t *vectors = (uint32_t *)0x0U;\r
+#endif\r
+ return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET];\r
+}\r
+\r
+\r
+/**\r
+ \brief System Reset\r
+ \details Initiates a system reset request to reset the MCU.\r
+ */\r
+__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void)\r
+{\r
+ __DSB(); /* Ensure all outstanding memory accesses included\r
+ buffered write are completed before reset */\r
+ SCB->AIRCR = ((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |\r
+ SCB_AIRCR_SYSRESETREQ_Msk);\r
+ __DSB(); /* Ensure completion of memory access */\r
+\r
+ for(;;) /* wait until reset */\r
+ {\r
+ __NOP();\r
+ }\r
+}\r
+\r
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)\r
+/**\r
+ \brief Enable Interrupt (non-secure)\r
+ \details Enables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state.\r
+ \param [in] IRQn Device specific interrupt number.\r
+ \note IRQn must not be negative.\r
+ */\r
+__STATIC_INLINE void TZ_NVIC_EnableIRQ_NS(IRQn_Type IRQn)\r
+{\r
+ if ((int32_t)(IRQn) >= 0)\r
+ {\r
+ NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));\r
+ }\r
+}\r
+\r
+\r
+/**\r
+ \brief Get Interrupt Enable status (non-secure)\r
+ \details Returns a device specific interrupt enable status from the non-secure NVIC interrupt controller when in secure state.\r
+ \param [in] IRQn Device specific interrupt number.\r
+ \return 0 Interrupt is not enabled.\r
+ \return 1 Interrupt is enabled.\r
+ \note IRQn must not be negative.\r
+ */\r
+__STATIC_INLINE uint32_t TZ_NVIC_GetEnableIRQ_NS(IRQn_Type IRQn)\r
+{\r
+ if ((int32_t)(IRQn) >= 0)\r
+ {\r
+ return((uint32_t)(((NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));\r
+ }\r
+ else\r
+ {\r
+ return(0U);\r
+ }\r
+}\r
+\r
+\r
+/**\r
+ \brief Disable Interrupt (non-secure)\r
+ \details Disables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state.\r
+ \param [in] IRQn Device specific interrupt number.\r
+ \note IRQn must not be negative.\r
+ */\r
+__STATIC_INLINE void TZ_NVIC_DisableIRQ_NS(IRQn_Type IRQn)\r
+{\r
+ if ((int32_t)(IRQn) >= 0)\r
+ {\r
+ NVIC_NS->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));\r
+ }\r
+}\r
+\r
+\r
+/**\r
+ \brief Get Pending Interrupt (non-secure)\r
+ \details Reads the NVIC pending register in the non-secure NVIC when in secure state and returns the pending bit for the specified device specific interrupt.\r
+ \param [in] IRQn Device specific interrupt number.\r
+ \return 0 Interrupt status is not pending.\r
+ \return 1 Interrupt status is pending.\r
+ \note IRQn must not be negative.\r
+ */\r
+__STATIC_INLINE uint32_t TZ_NVIC_GetPendingIRQ_NS(IRQn_Type IRQn)\r
+{\r
+ if ((int32_t)(IRQn) >= 0)\r
+ {\r
+ return((uint32_t)(((NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));\r
+ }\r
+ else\r
+ {\r
+ return(0U);\r
+ }\r
+}\r
+\r
+\r
+/**\r
+ \brief Set Pending Interrupt (non-secure)\r
+ \details Sets the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state.\r
+ \param [in] IRQn Device specific interrupt number.\r
+ \note IRQn must not be negative.\r
+ */\r
+__STATIC_INLINE void TZ_NVIC_SetPendingIRQ_NS(IRQn_Type IRQn)\r
+{\r
+ if ((int32_t)(IRQn) >= 0)\r
+ {\r
+ NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));\r
+ }\r
+}\r
+\r
+\r
+/**\r
+ \brief Clear Pending Interrupt (non-secure)\r
+ \details Clears the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state.\r
+ \param [in] IRQn Device specific interrupt number.\r
+ \note IRQn must not be negative.\r
+ */\r
+__STATIC_INLINE void TZ_NVIC_ClearPendingIRQ_NS(IRQn_Type IRQn)\r
+{\r
+ if ((int32_t)(IRQn) >= 0)\r
+ {\r
+ NVIC_NS->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));\r
+ }\r
+}\r
+\r
+\r
+/**\r
+ \brief Get Active Interrupt (non-secure)\r
+ \details Reads the active register in non-secure NVIC when in secure state and returns the active bit for the device specific interrupt.\r
+ \param [in] IRQn Device specific interrupt number.\r
+ \return 0 Interrupt status is not active.\r
+ \return 1 Interrupt status is active.\r
+ \note IRQn must not be negative.\r
+ */\r
+__STATIC_INLINE uint32_t TZ_NVIC_GetActive_NS(IRQn_Type IRQn)\r
+{\r
+ if ((int32_t)(IRQn) >= 0)\r
+ {\r
+ return((uint32_t)(((NVIC_NS->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));\r
+ }\r
+ else\r
+ {\r
+ return(0U);\r
+ }\r
+}\r
+\r
+\r
+/**\r
+ \brief Set Interrupt Priority (non-secure)\r
+ \details Sets the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state.\r
+ The interrupt number can be positive to specify a device specific interrupt,\r
+ or negative to specify a processor exception.\r
+ \param [in] IRQn Interrupt number.\r
+ \param [in] priority Priority to set.\r
+ \note The priority cannot be set for every non-secure processor exception.\r
+ */\r
+__STATIC_INLINE void TZ_NVIC_SetPriority_NS(IRQn_Type IRQn, uint32_t priority)\r
+{\r
+ if ((int32_t)(IRQn) >= 0)\r
+ {\r
+ NVIC_NS->IPR[_IP_IDX(IRQn)] = ((uint32_t)(NVIC_NS->IPR[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |\r
+ (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));\r
+ }\r
+ else\r
+ {\r
+ SCB_NS->SHPR[_SHP_IDX(IRQn)] = ((uint32_t)(SCB_NS->SHPR[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |\r
+ (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));\r
+ }\r
+}\r
+\r
+\r
+/**\r
+ \brief Get Interrupt Priority (non-secure)\r
+ \details Reads the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state.\r
+ The interrupt number can be positive to specify a device specific interrupt,\r
+ or negative to specify a processor exception.\r
+ \param [in] IRQn Interrupt number.\r
+ \return Interrupt Priority. Value is aligned automatically to the implemented priority bits of the microcontroller.\r
+ */\r
+__STATIC_INLINE uint32_t TZ_NVIC_GetPriority_NS(IRQn_Type IRQn)\r
+{\r
+\r
+ if ((int32_t)(IRQn) >= 0)\r
+ {\r
+ return((uint32_t)(((NVIC_NS->IPR[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));\r
+ }\r
+ else\r
+ {\r
+ return((uint32_t)(((SCB_NS->SHPR[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));\r
+ }\r
+}\r
+#endif /* defined (__ARM_FEATURE_CMSE) &&(__ARM_FEATURE_CMSE == 3U) */\r
+\r
+/*@} end of CMSIS_Core_NVICFunctions */\r
+\r
+/* ########################## MPU functions #################################### */\r
+\r
+#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)\r
+\r
+#include "mpu_armv8.h"\r
+\r
+#endif\r
+\r
+/* ########################## FPU functions #################################### */\r
+/**\r
+ \ingroup CMSIS_Core_FunctionInterface\r
+ \defgroup CMSIS_Core_FpuFunctions FPU Functions\r
+ \brief Function that provides FPU type.\r
+ @{\r
+ */\r
+\r
+/**\r
+ \brief get FPU type\r
+ \details returns the FPU type\r
+ \returns\r
+ - \b 0: No FPU\r
+ - \b 1: Single precision FPU\r
+ - \b 2: Double + Single precision FPU\r
+ */\r
+__STATIC_INLINE uint32_t SCB_GetFPUType(void)\r
+{\r
+ return 0U; /* No FPU */\r
+}\r
+\r
+\r
+/*@} end of CMSIS_Core_FpuFunctions */\r
+\r
+\r
+\r
+/* ########################## SAU functions #################################### */\r
+/**\r
+ \ingroup CMSIS_Core_FunctionInterface\r
+ \defgroup CMSIS_Core_SAUFunctions SAU Functions\r
+ \brief Functions that configure the SAU.\r
+ @{\r
+ */\r
+\r
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)\r
+\r
+/**\r
+ \brief Enable SAU\r
+ \details Enables the Security Attribution Unit (SAU).\r
+ */\r
+__STATIC_INLINE void TZ_SAU_Enable(void)\r
+{\r
+ SAU->CTRL |= (SAU_CTRL_ENABLE_Msk);\r
+}\r
+\r
+\r
+\r
+/**\r
+ \brief Disable SAU\r
+ \details Disables the Security Attribution Unit (SAU).\r
+ */\r
+__STATIC_INLINE void TZ_SAU_Disable(void)\r
+{\r
+ SAU->CTRL &= ~(SAU_CTRL_ENABLE_Msk);\r
+}\r
+\r
+#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */\r
+\r
+/*@} end of CMSIS_Core_SAUFunctions */\r
+\r
+\r
+\r
+\r
+/* ################################## SysTick function ############################################ */\r
+/**\r
+ \ingroup CMSIS_Core_FunctionInterface\r
+ \defgroup CMSIS_Core_SysTickFunctions SysTick Functions\r
+ \brief Functions that configure the System.\r
+ @{\r
+ */\r
+\r
+#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U)\r
+\r
+/**\r
+ \brief System Tick Configuration\r
+ \details Initializes the System Timer and its interrupt, and starts the System Tick Timer.\r
+ Counter is in free running mode to generate periodic interrupts.\r
+ \param [in] ticks Number of ticks between two interrupts.\r
+ \return 0 Function succeeded.\r
+ \return 1 Function failed.\r
+ \note When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the\r
+ function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>\r
+ must contain a vendor-specific implementation of this function.\r
+ */\r
+__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)\r
+{\r
+ if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk)\r
+ {\r
+ return (1UL); /* Reload value impossible */\r
+ }\r
+\r
+ SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */\r
+ NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */\r
+ SysTick->VAL = 0UL; /* Load the SysTick Counter Value */\r
+ SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk |\r
+ SysTick_CTRL_TICKINT_Msk |\r
+ SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */\r
+ return (0UL); /* Function successful */\r
+}\r
+\r
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)\r
+/**\r
+ \brief System Tick Configuration (non-secure)\r
+ \details Initializes the non-secure System Timer and its interrupt when in secure state, and starts the System Tick Timer.\r
+ Counter is in free running mode to generate periodic interrupts.\r
+ \param [in] ticks Number of ticks between two interrupts.\r
+ \return 0 Function succeeded.\r
+ \return 1 Function failed.\r
+ \note When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the\r
+ function <b>TZ_SysTick_Config_NS</b> is not included. In this case, the file <b><i>device</i>.h</b>\r
+ must contain a vendor-specific implementation of this function.\r
+\r
+ */\r
+__STATIC_INLINE uint32_t TZ_SysTick_Config_NS(uint32_t ticks)\r
+{\r
+ if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk)\r
+ {\r
+ return (1UL); /* Reload value impossible */\r
+ }\r
+\r
+ SysTick_NS->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */\r
+ TZ_NVIC_SetPriority_NS (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */\r
+ SysTick_NS->VAL = 0UL; /* Load the SysTick Counter Value */\r
+ SysTick_NS->CTRL = SysTick_CTRL_CLKSOURCE_Msk |\r
+ SysTick_CTRL_TICKINT_Msk |\r
+ SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */\r
+ return (0UL); /* Function successful */\r
+}\r
+#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */\r
+\r
+#endif\r
+\r
+/*@} end of CMSIS_Core_SysTickFunctions */\r
+\r
+\r
+\r
+\r
+#ifdef __cplusplus\r
+}\r
+#endif\r
+\r
+#endif /* __CORE_CM23_H_DEPENDANT */\r
+\r
+#endif /* __CMSIS_GENERIC */\r
--- /dev/null
+/**************************************************************************//**\r
+ * @file core_cm3.h\r
+ * @brief CMSIS Cortex-M3 Core Peripheral Access Layer Header File\r
+ * @version V5.0.8\r
+ * @date 04. June 2018\r
+ ******************************************************************************/\r
+/*\r
+ * Copyright (c) 2009-2018 Arm Limited. All rights reserved.\r
+ *\r
+ * SPDX-License-Identifier: Apache-2.0\r
+ *\r
+ * Licensed under the Apache License, Version 2.0 (the License); you may\r
+ * not use this file except in compliance with the License.\r
+ * You may obtain a copy of the License at\r
+ *\r
+ * www.apache.org/licenses/LICENSE-2.0\r
+ *\r
+ * Unless required by applicable law or agreed to in writing, software\r
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT\r
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\r
+ * See the License for the specific language governing permissions and\r
+ * limitations under the License.\r
+ */\r
+\r
+#if defined ( __ICCARM__ )\r
+ #pragma system_include /* treat file as system include file for MISRA check */\r
+#elif defined (__clang__)\r
+ #pragma clang system_header /* treat file as system include file */\r
+#endif\r
+\r
+#ifndef __CORE_CM3_H_GENERIC\r
+#define __CORE_CM3_H_GENERIC\r
+\r
+#include <stdint.h>\r
+\r
+#ifdef __cplusplus\r
+ extern "C" {\r
+#endif\r
+\r
+/**\r
+ \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions\r
+ CMSIS violates the following MISRA-C:2004 rules:\r
+\r
+ \li Required Rule 8.5, object/function definition in header file.<br>\r
+ Function definitions in header files are used to allow 'inlining'.\r
+\r
+ \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>\r
+ Unions are used for effective representation of core registers.\r
+\r
+ \li Advisory Rule 19.7, Function-like macro defined.<br>\r
+ Function-like macros are used to allow more efficient code.\r
+ */\r
+\r
+\r
+/*******************************************************************************\r
+ * CMSIS definitions\r
+ ******************************************************************************/\r
+/**\r
+ \ingroup Cortex_M3\r
+ @{\r
+ */\r
+\r
+#include "cmsis_version.h"\r
+\r
+/* CMSIS CM3 definitions */\r
+#define __CM3_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */\r
+#define __CM3_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */\r
+#define __CM3_CMSIS_VERSION ((__CM3_CMSIS_VERSION_MAIN << 16U) | \\r
+ __CM3_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */\r
+\r
+#define __CORTEX_M (3U) /*!< Cortex-M Core */\r
+\r
+/** __FPU_USED indicates whether an FPU is used or not.\r
+ This core does not support an FPU at all\r
+*/\r
+#define __FPU_USED 0U\r
+\r
+#if defined ( __CC_ARM )\r
+ #if defined __TARGET_FPU_VFP\r
+ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"\r
+ #endif\r
+\r
+#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)\r
+ #if defined __ARM_PCS_VFP\r
+ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"\r
+ #endif\r
+\r
+#elif defined ( __GNUC__ )\r
+ #if defined (__VFP_FP__) && !defined(__SOFTFP__)\r
+ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"\r
+ #endif\r
+\r
+#elif defined ( __ICCARM__ )\r
+ #if defined __ARMVFP__\r
+ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"\r
+ #endif\r
+\r
+#elif defined ( __TI_ARM__ )\r
+ #if defined __TI_VFP_SUPPORT__\r
+ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"\r
+ #endif\r
+\r
+#elif defined ( __TASKING__ )\r
+ #if defined __FPU_VFP__\r
+ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"\r
+ #endif\r
+\r
+#elif defined ( __CSMC__ )\r
+ #if ( __CSMC__ & 0x400U)\r
+ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"\r
+ #endif\r
+\r
+#endif\r
+\r
+#include "cmsis_compiler.h" /* CMSIS compiler specific defines */\r
+\r
+\r
+#ifdef __cplusplus\r
+}\r
+#endif\r
+\r
+#endif /* __CORE_CM3_H_GENERIC */\r
+\r
+#ifndef __CMSIS_GENERIC\r
+\r
+#ifndef __CORE_CM3_H_DEPENDANT\r
+#define __CORE_CM3_H_DEPENDANT\r
+\r
+#ifdef __cplusplus\r
+ extern "C" {\r
+#endif\r
+\r
+/* check device defines and use defaults */\r
+#if defined __CHECK_DEVICE_DEFINES\r
+ #ifndef __CM3_REV\r
+ #define __CM3_REV 0x0200U\r
+ #warning "__CM3_REV not defined in device header file; using default!"\r
+ #endif\r
+\r
+ #ifndef __MPU_PRESENT\r
+ #define __MPU_PRESENT 0U\r
+ #warning "__MPU_PRESENT not defined in device header file; using default!"\r
+ #endif\r
+\r
+ #ifndef __NVIC_PRIO_BITS\r
+ #define __NVIC_PRIO_BITS 3U\r
+ #warning "__NVIC_PRIO_BITS not defined in device header file; using default!"\r
+ #endif\r
+\r
+ #ifndef __Vendor_SysTickConfig\r
+ #define __Vendor_SysTickConfig 0U\r
+ #warning "__Vendor_SysTickConfig not defined in device header file; using default!"\r
+ #endif\r
+#endif\r
+\r
+/* IO definitions (access restrictions to peripheral registers) */\r
+/**\r
+ \defgroup CMSIS_glob_defs CMSIS Global Defines\r
+\r
+ <strong>IO Type Qualifiers</strong> are used\r
+ \li to specify the access to peripheral variables.\r
+ \li for automatic generation of peripheral register debug information.\r
+*/\r
+#ifdef __cplusplus\r
+ #define __I volatile /*!< Defines 'read only' permissions */\r
+#else\r
+ #define __I volatile const /*!< Defines 'read only' permissions */\r
+#endif\r
+#define __O volatile /*!< Defines 'write only' permissions */\r
+#define __IO volatile /*!< Defines 'read / write' permissions */\r
+\r
+/* following defines should be used for structure members */\r
+#define __IM volatile const /*! Defines 'read only' structure member permissions */\r
+#define __OM volatile /*! Defines 'write only' structure member permissions */\r
+#define __IOM volatile /*! Defines 'read / write' structure member permissions */\r
+\r
+/*@} end of group Cortex_M3 */\r
+\r
+\r
+\r
+/*******************************************************************************\r
+ * Register Abstraction\r
+ Core Register contain:\r
+ - Core Register\r
+ - Core NVIC Register\r
+ - Core SCB Register\r
+ - Core SysTick Register\r
+ - Core Debug Register\r
+ - Core MPU Register\r
+ ******************************************************************************/\r
+/**\r
+ \defgroup CMSIS_core_register Defines and Type Definitions\r
+ \brief Type definitions and defines for Cortex-M processor based devices.\r
+*/\r
+\r
+/**\r
+ \ingroup CMSIS_core_register\r
+ \defgroup CMSIS_CORE Status and Control Registers\r
+ \brief Core Register type definitions.\r
+ @{\r
+ */\r
+\r
+/**\r
+ \brief Union type to access the Application Program Status Register (APSR).\r
+ */\r
+typedef union\r
+{\r
+ struct\r
+ {\r
+ uint32_t _reserved0:27; /*!< bit: 0..26 Reserved */\r
+ uint32_t Q:1; /*!< bit: 27 Saturation condition flag */\r
+ uint32_t V:1; /*!< bit: 28 Overflow condition code flag */\r
+ uint32_t C:1; /*!< bit: 29 Carry condition code flag */\r
+ uint32_t Z:1; /*!< bit: 30 Zero condition code flag */\r
+ uint32_t N:1; /*!< bit: 31 Negative condition code flag */\r
+ } b; /*!< Structure used for bit access */\r
+ uint32_t w; /*!< Type used for word access */\r
+} APSR_Type;\r
+\r
+/* APSR Register Definitions */\r
+#define APSR_N_Pos 31U /*!< APSR: N Position */\r
+#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */\r
+\r
+#define APSR_Z_Pos 30U /*!< APSR: Z Position */\r
+#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */\r
+\r
+#define APSR_C_Pos 29U /*!< APSR: C Position */\r
+#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */\r
+\r
+#define APSR_V_Pos 28U /*!< APSR: V Position */\r
+#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */\r
+\r
+#define APSR_Q_Pos 27U /*!< APSR: Q Position */\r
+#define APSR_Q_Msk (1UL << APSR_Q_Pos) /*!< APSR: Q Mask */\r
+\r
+\r
+/**\r
+ \brief Union type to access the Interrupt Program Status Register (IPSR).\r
+ */\r
+typedef union\r
+{\r
+ struct\r
+ {\r
+ uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */\r
+ uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */\r
+ } b; /*!< Structure used for bit access */\r
+ uint32_t w; /*!< Type used for word access */\r
+} IPSR_Type;\r
+\r
+/* IPSR Register Definitions */\r
+#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */\r
+#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */\r
+\r
+\r
+/**\r
+ \brief Union type to access the Special-Purpose Program Status Registers (xPSR).\r
+ */\r
+typedef union\r
+{\r
+ struct\r
+ {\r
+ uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */\r
+ uint32_t _reserved0:1; /*!< bit: 9 Reserved */\r
+ uint32_t ICI_IT_1:6; /*!< bit: 10..15 ICI/IT part 1 */\r
+ uint32_t _reserved1:8; /*!< bit: 16..23 Reserved */\r
+ uint32_t T:1; /*!< bit: 24 Thumb bit */\r
+ uint32_t ICI_IT_2:2; /*!< bit: 25..26 ICI/IT part 2 */\r
+ uint32_t Q:1; /*!< bit: 27 Saturation condition flag */\r
+ uint32_t V:1; /*!< bit: 28 Overflow condition code flag */\r
+ uint32_t C:1; /*!< bit: 29 Carry condition code flag */\r
+ uint32_t Z:1; /*!< bit: 30 Zero condition code flag */\r
+ uint32_t N:1; /*!< bit: 31 Negative condition code flag */\r
+ } b; /*!< Structure used for bit access */\r
+ uint32_t w; /*!< Type used for word access */\r
+} xPSR_Type;\r
+\r
+/* xPSR Register Definitions */\r
+#define xPSR_N_Pos 31U /*!< xPSR: N Position */\r
+#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */\r
+\r
+#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */\r
+#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */\r
+\r
+#define xPSR_C_Pos 29U /*!< xPSR: C Position */\r
+#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */\r
+\r
+#define xPSR_V_Pos 28U /*!< xPSR: V Position */\r
+#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */\r
+\r
+#define xPSR_Q_Pos 27U /*!< xPSR: Q Position */\r
+#define xPSR_Q_Msk (1UL << xPSR_Q_Pos) /*!< xPSR: Q Mask */\r
+\r
+#define xPSR_ICI_IT_2_Pos 25U /*!< xPSR: ICI/IT part 2 Position */\r
+#define xPSR_ICI_IT_2_Msk (3UL << xPSR_ICI_IT_2_Pos) /*!< xPSR: ICI/IT part 2 Mask */\r
+\r
+#define xPSR_T_Pos 24U /*!< xPSR: T Position */\r
+#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */\r
+\r
+#define xPSR_ICI_IT_1_Pos 10U /*!< xPSR: ICI/IT part 1 Position */\r
+#define xPSR_ICI_IT_1_Msk (0x3FUL << xPSR_ICI_IT_1_Pos) /*!< xPSR: ICI/IT part 1 Mask */\r
+\r
+#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */\r
+#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */\r
+\r
+\r
+/**\r
+ \brief Union type to access the Control Registers (CONTROL).\r
+ */\r
+typedef union\r
+{\r
+ struct\r
+ {\r
+ uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */\r
+ uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */\r
+ uint32_t _reserved1:30; /*!< bit: 2..31 Reserved */\r
+ } b; /*!< Structure used for bit access */\r
+ uint32_t w; /*!< Type used for word access */\r
+} CONTROL_Type;\r
+\r
+/* CONTROL Register Definitions */\r
+#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */\r
+#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */\r
+\r
+#define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */\r
+#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */\r
+\r
+/*@} end of group CMSIS_CORE */\r
+\r
+\r
+/**\r
+ \ingroup CMSIS_core_register\r
+ \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC)\r
+ \brief Type definitions for the NVIC Registers\r
+ @{\r
+ */\r
+\r
+/**\r
+ \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC).\r
+ */\r
+typedef struct\r
+{\r
+ __IOM uint32_t ISER[8U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */\r
+ uint32_t RESERVED0[24U];\r
+ __IOM uint32_t ICER[8U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */\r
+ uint32_t RSERVED1[24U];\r
+ __IOM uint32_t ISPR[8U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */\r
+ uint32_t RESERVED2[24U];\r
+ __IOM uint32_t ICPR[8U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */\r
+ uint32_t RESERVED3[24U];\r
+ __IOM uint32_t IABR[8U]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */\r
+ uint32_t RESERVED4[56U];\r
+ __IOM uint8_t IP[240U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */\r
+ uint32_t RESERVED5[644U];\r
+ __OM uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */\r
+} NVIC_Type;\r
+\r
+/* Software Triggered Interrupt Register Definitions */\r
+#define NVIC_STIR_INTID_Pos 0U /*!< STIR: INTLINESNUM Position */\r
+#define NVIC_STIR_INTID_Msk (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/) /*!< STIR: INTLINESNUM Mask */\r
+\r
+/*@} end of group CMSIS_NVIC */\r
+\r
+\r
+/**\r
+ \ingroup CMSIS_core_register\r
+ \defgroup CMSIS_SCB System Control Block (SCB)\r
+ \brief Type definitions for the System Control Block Registers\r
+ @{\r
+ */\r
+\r
+/**\r
+ \brief Structure type to access the System Control Block (SCB).\r
+ */\r
+typedef struct\r
+{\r
+ __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */\r
+ __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */\r
+ __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */\r
+ __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */\r
+ __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */\r
+ __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */\r
+ __IOM uint8_t SHP[12U]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */\r
+ __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */\r
+ __IOM uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */\r
+ __IOM uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */\r
+ __IOM uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */\r
+ __IOM uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */\r
+ __IOM uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */\r
+ __IOM uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */\r
+ __IM uint32_t PFR[2U]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */\r
+ __IM uint32_t DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */\r
+ __IM uint32_t ADR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */\r
+ __IM uint32_t MMFR[4U]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */\r
+ __IM uint32_t ISAR[5U]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */\r
+ uint32_t RESERVED0[5U];\r
+ __IOM uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */\r
+} SCB_Type;\r
+\r
+/* SCB CPUID Register Definitions */\r
+#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */\r
+#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */\r
+\r
+#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */\r
+#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */\r
+\r
+#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */\r
+#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */\r
+\r
+#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */\r
+#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */\r
+\r
+#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */\r
+#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */\r
+\r
+/* SCB Interrupt Control State Register Definitions */\r
+#define SCB_ICSR_NMIPENDSET_Pos 31U /*!< SCB ICSR: NMIPENDSET Position */\r
+#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */\r
+\r
+#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */\r
+#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */\r
+\r
+#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */\r
+#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */\r
+\r
+#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */\r
+#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */\r
+\r
+#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */\r
+#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */\r
+\r
+#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */\r
+#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */\r
+\r
+#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */\r
+#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */\r
+\r
+#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */\r
+#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */\r
+\r
+#define SCB_ICSR_RETTOBASE_Pos 11U /*!< SCB ICSR: RETTOBASE Position */\r
+#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */\r
+\r
+#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */\r
+#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */\r
+\r
+/* SCB Vector Table Offset Register Definitions */\r
+#if defined (__CM3_REV) && (__CM3_REV < 0x0201U) /* core r2p1 */\r
+#define SCB_VTOR_TBLBASE_Pos 29U /*!< SCB VTOR: TBLBASE Position */\r
+#define SCB_VTOR_TBLBASE_Msk (1UL << SCB_VTOR_TBLBASE_Pos) /*!< SCB VTOR: TBLBASE Mask */\r
+\r
+#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */\r
+#define SCB_VTOR_TBLOFF_Msk (0x3FFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */\r
+#else\r
+#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */\r
+#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */\r
+#endif\r
+\r
+/* SCB Application Interrupt and Reset Control Register Definitions */\r
+#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */\r
+#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */\r
+\r
+#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */\r
+#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */\r
+\r
+#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */\r
+#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */\r
+\r
+#define SCB_AIRCR_PRIGROUP_Pos 8U /*!< SCB AIRCR: PRIGROUP Position */\r
+#define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */\r
+\r
+#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */\r
+#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */\r
+\r
+#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */\r
+#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */\r
+\r
+#define SCB_AIRCR_VECTRESET_Pos 0U /*!< SCB AIRCR: VECTRESET Position */\r
+#define SCB_AIRCR_VECTRESET_Msk (1UL /*<< SCB_AIRCR_VECTRESET_Pos*/) /*!< SCB AIRCR: VECTRESET Mask */\r
+\r
+/* SCB System Control Register Definitions */\r
+#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */\r
+#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */\r
+\r
+#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */\r
+#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */\r
+\r
+#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */\r
+#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */\r
+\r
+/* SCB Configuration Control Register Definitions */\r
+#define SCB_CCR_STKALIGN_Pos 9U /*!< SCB CCR: STKALIGN Position */\r
+#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */\r
+\r
+#define SCB_CCR_BFHFNMIGN_Pos 8U /*!< SCB CCR: BFHFNMIGN Position */\r
+#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */\r
+\r
+#define SCB_CCR_DIV_0_TRP_Pos 4U /*!< SCB CCR: DIV_0_TRP Position */\r
+#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */\r
+\r
+#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */\r
+#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */\r
+\r
+#define SCB_CCR_USERSETMPEND_Pos 1U /*!< SCB CCR: USERSETMPEND Position */\r
+#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */\r
+\r
+#define SCB_CCR_NONBASETHRDENA_Pos 0U /*!< SCB CCR: NONBASETHRDENA Position */\r
+#define SCB_CCR_NONBASETHRDENA_Msk (1UL /*<< SCB_CCR_NONBASETHRDENA_Pos*/) /*!< SCB CCR: NONBASETHRDENA Mask */\r
+\r
+/* SCB System Handler Control and State Register Definitions */\r
+#define SCB_SHCSR_USGFAULTENA_Pos 18U /*!< SCB SHCSR: USGFAULTENA Position */\r
+#define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */\r
+\r
+#define SCB_SHCSR_BUSFAULTENA_Pos 17U /*!< SCB SHCSR: BUSFAULTENA Position */\r
+#define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */\r
+\r
+#define SCB_SHCSR_MEMFAULTENA_Pos 16U /*!< SCB SHCSR: MEMFAULTENA Position */\r
+#define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */\r
+\r
+#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */\r
+#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */\r
+\r
+#define SCB_SHCSR_BUSFAULTPENDED_Pos 14U /*!< SCB SHCSR: BUSFAULTPENDED Position */\r
+#define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */\r
+\r
+#define SCB_SHCSR_MEMFAULTPENDED_Pos 13U /*!< SCB SHCSR: MEMFAULTPENDED Position */\r
+#define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */\r
+\r
+#define SCB_SHCSR_USGFAULTPENDED_Pos 12U /*!< SCB SHCSR: USGFAULTPENDED Position */\r
+#define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */\r
+\r
+#define SCB_SHCSR_SYSTICKACT_Pos 11U /*!< SCB SHCSR: SYSTICKACT Position */\r
+#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */\r
+\r
+#define SCB_SHCSR_PENDSVACT_Pos 10U /*!< SCB SHCSR: PENDSVACT Position */\r
+#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */\r
+\r
+#define SCB_SHCSR_MONITORACT_Pos 8U /*!< SCB SHCSR: MONITORACT Position */\r
+#define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */\r
+\r
+#define SCB_SHCSR_SVCALLACT_Pos 7U /*!< SCB SHCSR: SVCALLACT Position */\r
+#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */\r
+\r
+#define SCB_SHCSR_USGFAULTACT_Pos 3U /*!< SCB SHCSR: USGFAULTACT Position */\r
+#define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */\r
+\r
+#define SCB_SHCSR_BUSFAULTACT_Pos 1U /*!< SCB SHCSR: BUSFAULTACT Position */\r
+#define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */\r
+\r
+#define SCB_SHCSR_MEMFAULTACT_Pos 0U /*!< SCB SHCSR: MEMFAULTACT Position */\r
+#define SCB_SHCSR_MEMFAULTACT_Msk (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/) /*!< SCB SHCSR: MEMFAULTACT Mask */\r
+\r
+/* SCB Configurable Fault Status Register Definitions */\r
+#define SCB_CFSR_USGFAULTSR_Pos 16U /*!< SCB CFSR: Usage Fault Status Register Position */\r
+#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */\r
+\r
+#define SCB_CFSR_BUSFAULTSR_Pos 8U /*!< SCB CFSR: Bus Fault Status Register Position */\r
+#define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */\r
+\r
+#define SCB_CFSR_MEMFAULTSR_Pos 0U /*!< SCB CFSR: Memory Manage Fault Status Register Position */\r
+#define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */\r
+\r
+/* MemManage Fault Status Register (part of SCB Configurable Fault Status Register) */\r
+#define SCB_CFSR_MMARVALID_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 7U) /*!< SCB CFSR (MMFSR): MMARVALID Position */\r
+#define SCB_CFSR_MMARVALID_Msk (1UL << SCB_CFSR_MMARVALID_Pos) /*!< SCB CFSR (MMFSR): MMARVALID Mask */\r
+\r
+#define SCB_CFSR_MSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 4U) /*!< SCB CFSR (MMFSR): MSTKERR Position */\r
+#define SCB_CFSR_MSTKERR_Msk (1UL << SCB_CFSR_MSTKERR_Pos) /*!< SCB CFSR (MMFSR): MSTKERR Mask */\r
+\r
+#define SCB_CFSR_MUNSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 3U) /*!< SCB CFSR (MMFSR): MUNSTKERR Position */\r
+#define SCB_CFSR_MUNSTKERR_Msk (1UL << SCB_CFSR_MUNSTKERR_Pos) /*!< SCB CFSR (MMFSR): MUNSTKERR Mask */\r
+\r
+#define SCB_CFSR_DACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 1U) /*!< SCB CFSR (MMFSR): DACCVIOL Position */\r
+#define SCB_CFSR_DACCVIOL_Msk (1UL << SCB_CFSR_DACCVIOL_Pos) /*!< SCB CFSR (MMFSR): DACCVIOL Mask */\r
+\r
+#define SCB_CFSR_IACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 0U) /*!< SCB CFSR (MMFSR): IACCVIOL Position */\r
+#define SCB_CFSR_IACCVIOL_Msk (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/) /*!< SCB CFSR (MMFSR): IACCVIOL Mask */\r
+\r
+/* BusFault Status Register (part of SCB Configurable Fault Status Register) */\r
+#define SCB_CFSR_BFARVALID_Pos (SCB_CFSR_BUSFAULTSR_Pos + 7U) /*!< SCB CFSR (BFSR): BFARVALID Position */\r
+#define SCB_CFSR_BFARVALID_Msk (1UL << SCB_CFSR_BFARVALID_Pos) /*!< SCB CFSR (BFSR): BFARVALID Mask */\r
+\r
+#define SCB_CFSR_STKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 4U) /*!< SCB CFSR (BFSR): STKERR Position */\r
+#define SCB_CFSR_STKERR_Msk (1UL << SCB_CFSR_STKERR_Pos) /*!< SCB CFSR (BFSR): STKERR Mask */\r
+\r
+#define SCB_CFSR_UNSTKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 3U) /*!< SCB CFSR (BFSR): UNSTKERR Position */\r
+#define SCB_CFSR_UNSTKERR_Msk (1UL << SCB_CFSR_UNSTKERR_Pos) /*!< SCB CFSR (BFSR): UNSTKERR Mask */\r
+\r
+#define SCB_CFSR_IMPRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 2U) /*!< SCB CFSR (BFSR): IMPRECISERR Position */\r
+#define SCB_CFSR_IMPRECISERR_Msk (1UL << SCB_CFSR_IMPRECISERR_Pos) /*!< SCB CFSR (BFSR): IMPRECISERR Mask */\r
+\r
+#define SCB_CFSR_PRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 1U) /*!< SCB CFSR (BFSR): PRECISERR Position */\r
+#define SCB_CFSR_PRECISERR_Msk (1UL << SCB_CFSR_PRECISERR_Pos) /*!< SCB CFSR (BFSR): PRECISERR Mask */\r
+\r
+#define SCB_CFSR_IBUSERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 0U) /*!< SCB CFSR (BFSR): IBUSERR Position */\r
+#define SCB_CFSR_IBUSERR_Msk (1UL << SCB_CFSR_IBUSERR_Pos) /*!< SCB CFSR (BFSR): IBUSERR Mask */\r
+\r
+/* UsageFault Status Register (part of SCB Configurable Fault Status Register) */\r
+#define SCB_CFSR_DIVBYZERO_Pos (SCB_CFSR_USGFAULTSR_Pos + 9U) /*!< SCB CFSR (UFSR): DIVBYZERO Position */\r
+#define SCB_CFSR_DIVBYZERO_Msk (1UL << SCB_CFSR_DIVBYZERO_Pos) /*!< SCB CFSR (UFSR): DIVBYZERO Mask */\r
+\r
+#define SCB_CFSR_UNALIGNED_Pos (SCB_CFSR_USGFAULTSR_Pos + 8U) /*!< SCB CFSR (UFSR): UNALIGNED Position */\r
+#define SCB_CFSR_UNALIGNED_Msk (1UL << SCB_CFSR_UNALIGNED_Pos) /*!< SCB CFSR (UFSR): UNALIGNED Mask */\r
+\r
+#define SCB_CFSR_NOCP_Pos (SCB_CFSR_USGFAULTSR_Pos + 3U) /*!< SCB CFSR (UFSR): NOCP Position */\r
+#define SCB_CFSR_NOCP_Msk (1UL << SCB_CFSR_NOCP_Pos) /*!< SCB CFSR (UFSR): NOCP Mask */\r
+\r
+#define SCB_CFSR_INVPC_Pos (SCB_CFSR_USGFAULTSR_Pos + 2U) /*!< SCB CFSR (UFSR): INVPC Position */\r
+#define SCB_CFSR_INVPC_Msk (1UL << SCB_CFSR_INVPC_Pos) /*!< SCB CFSR (UFSR): INVPC Mask */\r
+\r
+#define SCB_CFSR_INVSTATE_Pos (SCB_CFSR_USGFAULTSR_Pos + 1U) /*!< SCB CFSR (UFSR): INVSTATE Position */\r
+#define SCB_CFSR_INVSTATE_Msk (1UL << SCB_CFSR_INVSTATE_Pos) /*!< SCB CFSR (UFSR): INVSTATE Mask */\r
+\r
+#define SCB_CFSR_UNDEFINSTR_Pos (SCB_CFSR_USGFAULTSR_Pos + 0U) /*!< SCB CFSR (UFSR): UNDEFINSTR Position */\r
+#define SCB_CFSR_UNDEFINSTR_Msk (1UL << SCB_CFSR_UNDEFINSTR_Pos) /*!< SCB CFSR (UFSR): UNDEFINSTR Mask */\r
+\r
+/* SCB Hard Fault Status Register Definitions */\r
+#define SCB_HFSR_DEBUGEVT_Pos 31U /*!< SCB HFSR: DEBUGEVT Position */\r
+#define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */\r
+\r
+#define SCB_HFSR_FORCED_Pos 30U /*!< SCB HFSR: FORCED Position */\r
+#define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */\r
+\r
+#define SCB_HFSR_VECTTBL_Pos 1U /*!< SCB HFSR: VECTTBL Position */\r
+#define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */\r
+\r
+/* SCB Debug Fault Status Register Definitions */\r
+#define SCB_DFSR_EXTERNAL_Pos 4U /*!< SCB DFSR: EXTERNAL Position */\r
+#define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */\r
+\r
+#define SCB_DFSR_VCATCH_Pos 3U /*!< SCB DFSR: VCATCH Position */\r
+#define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */\r
+\r
+#define SCB_DFSR_DWTTRAP_Pos 2U /*!< SCB DFSR: DWTTRAP Position */\r
+#define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */\r
+\r
+#define SCB_DFSR_BKPT_Pos 1U /*!< SCB DFSR: BKPT Position */\r
+#define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */\r
+\r
+#define SCB_DFSR_HALTED_Pos 0U /*!< SCB DFSR: HALTED Position */\r
+#define SCB_DFSR_HALTED_Msk (1UL /*<< SCB_DFSR_HALTED_Pos*/) /*!< SCB DFSR: HALTED Mask */\r
+\r
+/*@} end of group CMSIS_SCB */\r
+\r
+\r
+/**\r
+ \ingroup CMSIS_core_register\r
+ \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB)\r
+ \brief Type definitions for the System Control and ID Register not in the SCB\r
+ @{\r
+ */\r
+\r
+/**\r
+ \brief Structure type to access the System Control and ID Register not in the SCB.\r
+ */\r
+typedef struct\r
+{\r
+ uint32_t RESERVED0[1U];\r
+ __IM uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */\r
+#if defined (__CM3_REV) && (__CM3_REV >= 0x200U)\r
+ __IOM uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */\r
+#else\r
+ uint32_t RESERVED1[1U];\r
+#endif\r
+} SCnSCB_Type;\r
+\r
+/* Interrupt Controller Type Register Definitions */\r
+#define SCnSCB_ICTR_INTLINESNUM_Pos 0U /*!< ICTR: INTLINESNUM Position */\r
+#define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/) /*!< ICTR: INTLINESNUM Mask */\r
+\r
+/* Auxiliary Control Register Definitions */\r
+\r
+#define SCnSCB_ACTLR_DISFOLD_Pos 2U /*!< ACTLR: DISFOLD Position */\r
+#define SCnSCB_ACTLR_DISFOLD_Msk (1UL << SCnSCB_ACTLR_DISFOLD_Pos) /*!< ACTLR: DISFOLD Mask */\r
+\r
+#define SCnSCB_ACTLR_DISDEFWBUF_Pos 1U /*!< ACTLR: DISDEFWBUF Position */\r
+#define SCnSCB_ACTLR_DISDEFWBUF_Msk (1UL << SCnSCB_ACTLR_DISDEFWBUF_Pos) /*!< ACTLR: DISDEFWBUF Mask */\r
+\r
+#define SCnSCB_ACTLR_DISMCYCINT_Pos 0U /*!< ACTLR: DISMCYCINT Position */\r
+#define SCnSCB_ACTLR_DISMCYCINT_Msk (1UL /*<< SCnSCB_ACTLR_DISMCYCINT_Pos*/) /*!< ACTLR: DISMCYCINT Mask */\r
+\r
+/*@} end of group CMSIS_SCnotSCB */\r
+\r
+\r
+/**\r
+ \ingroup CMSIS_core_register\r
+ \defgroup CMSIS_SysTick System Tick Timer (SysTick)\r
+ \brief Type definitions for the System Timer Registers.\r
+ @{\r
+ */\r
+\r
+/**\r
+ \brief Structure type to access the System Timer (SysTick).\r
+ */\r
+typedef struct\r
+{\r
+ __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */\r
+ __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */\r
+ __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */\r
+ __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */\r
+} SysTick_Type;\r
+\r
+/* SysTick Control / Status Register Definitions */\r
+#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */\r
+#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */\r
+\r
+#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */\r
+#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */\r
+\r
+#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */\r
+#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */\r
+\r
+#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */\r
+#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */\r
+\r
+/* SysTick Reload Register Definitions */\r
+#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */\r
+#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */\r
+\r
+/* SysTick Current Register Definitions */\r
+#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */\r
+#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */\r
+\r
+/* SysTick Calibration Register Definitions */\r
+#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */\r
+#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */\r
+\r
+#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */\r
+#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */\r
+\r
+#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */\r
+#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */\r
+\r
+/*@} end of group CMSIS_SysTick */\r
+\r
+\r
+/**\r
+ \ingroup CMSIS_core_register\r
+ \defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM)\r
+ \brief Type definitions for the Instrumentation Trace Macrocell (ITM)\r
+ @{\r
+ */\r
+\r
+/**\r
+ \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM).\r
+ */\r
+typedef struct\r
+{\r
+ __OM union\r
+ {\r
+ __OM uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */\r
+ __OM uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */\r
+ __OM uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */\r
+ } PORT [32U]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */\r
+ uint32_t RESERVED0[864U];\r
+ __IOM uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */\r
+ uint32_t RESERVED1[15U];\r
+ __IOM uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */\r
+ uint32_t RESERVED2[15U];\r
+ __IOM uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */\r
+ uint32_t RESERVED3[29U];\r
+ __OM uint32_t IWR; /*!< Offset: 0xEF8 ( /W) ITM Integration Write Register */\r
+ __IM uint32_t IRR; /*!< Offset: 0xEFC (R/ ) ITM Integration Read Register */\r
+ __IOM uint32_t IMCR; /*!< Offset: 0xF00 (R/W) ITM Integration Mode Control Register */\r
+ uint32_t RESERVED4[43U];\r
+ __OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */\r
+ __IM uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */\r
+ uint32_t RESERVED5[6U];\r
+ __IM uint32_t PID4; /*!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 */\r
+ __IM uint32_t PID5; /*!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 */\r
+ __IM uint32_t PID6; /*!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 */\r
+ __IM uint32_t PID7; /*!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 */\r
+ __IM uint32_t PID0; /*!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 */\r
+ __IM uint32_t PID1; /*!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 */\r
+ __IM uint32_t PID2; /*!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 */\r
+ __IM uint32_t PID3; /*!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 */\r
+ __IM uint32_t CID0; /*!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 */\r
+ __IM uint32_t CID1; /*!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 */\r
+ __IM uint32_t CID2; /*!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 */\r
+ __IM uint32_t CID3; /*!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 */\r
+} ITM_Type;\r
+\r
+/* ITM Trace Privilege Register Definitions */\r
+#define ITM_TPR_PRIVMASK_Pos 0U /*!< ITM TPR: PRIVMASK Position */\r
+#define ITM_TPR_PRIVMASK_Msk (0xFFFFFFFFUL /*<< ITM_TPR_PRIVMASK_Pos*/) /*!< ITM TPR: PRIVMASK Mask */\r
+\r
+/* ITM Trace Control Register Definitions */\r
+#define ITM_TCR_BUSY_Pos 23U /*!< ITM TCR: BUSY Position */\r
+#define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */\r
+\r
+#define ITM_TCR_TraceBusID_Pos 16U /*!< ITM TCR: ATBID Position */\r
+#define ITM_TCR_TraceBusID_Msk (0x7FUL << ITM_TCR_TraceBusID_Pos) /*!< ITM TCR: ATBID Mask */\r
+\r
+#define ITM_TCR_GTSFREQ_Pos 10U /*!< ITM TCR: Global timestamp frequency Position */\r
+#define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */\r
+\r
+#define ITM_TCR_TSPrescale_Pos 8U /*!< ITM TCR: TSPrescale Position */\r
+#define ITM_TCR_TSPrescale_Msk (3UL << ITM_TCR_TSPrescale_Pos) /*!< ITM TCR: TSPrescale Mask */\r
+\r
+#define ITM_TCR_SWOENA_Pos 4U /*!< ITM TCR: SWOENA Position */\r
+#define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */\r
+\r
+#define ITM_TCR_DWTENA_Pos 3U /*!< ITM TCR: DWTENA Position */\r
+#define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */\r
+\r
+#define ITM_TCR_SYNCENA_Pos 2U /*!< ITM TCR: SYNCENA Position */\r
+#define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */\r
+\r
+#define ITM_TCR_TSENA_Pos 1U /*!< ITM TCR: TSENA Position */\r
+#define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */\r
+\r
+#define ITM_TCR_ITMENA_Pos 0U /*!< ITM TCR: ITM Enable bit Position */\r
+#define ITM_TCR_ITMENA_Msk (1UL /*<< ITM_TCR_ITMENA_Pos*/) /*!< ITM TCR: ITM Enable bit Mask */\r
+\r
+/* ITM Integration Write Register Definitions */\r
+#define ITM_IWR_ATVALIDM_Pos 0U /*!< ITM IWR: ATVALIDM Position */\r
+#define ITM_IWR_ATVALIDM_Msk (1UL /*<< ITM_IWR_ATVALIDM_Pos*/) /*!< ITM IWR: ATVALIDM Mask */\r
+\r
+/* ITM Integration Read Register Definitions */\r
+#define ITM_IRR_ATREADYM_Pos 0U /*!< ITM IRR: ATREADYM Position */\r
+#define ITM_IRR_ATREADYM_Msk (1UL /*<< ITM_IRR_ATREADYM_Pos*/) /*!< ITM IRR: ATREADYM Mask */\r
+\r
+/* ITM Integration Mode Control Register Definitions */\r
+#define ITM_IMCR_INTEGRATION_Pos 0U /*!< ITM IMCR: INTEGRATION Position */\r
+#define ITM_IMCR_INTEGRATION_Msk (1UL /*<< ITM_IMCR_INTEGRATION_Pos*/) /*!< ITM IMCR: INTEGRATION Mask */\r
+\r
+/* ITM Lock Status Register Definitions */\r
+#define ITM_LSR_ByteAcc_Pos 2U /*!< ITM LSR: ByteAcc Position */\r
+#define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */\r
+\r
+#define ITM_LSR_Access_Pos 1U /*!< ITM LSR: Access Position */\r
+#define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */\r
+\r
+#define ITM_LSR_Present_Pos 0U /*!< ITM LSR: Present Position */\r
+#define ITM_LSR_Present_Msk (1UL /*<< ITM_LSR_Present_Pos*/) /*!< ITM LSR: Present Mask */\r
+\r
+/*@}*/ /* end of group CMSIS_ITM */\r
+\r
+\r
+/**\r
+ \ingroup CMSIS_core_register\r
+ \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT)\r
+ \brief Type definitions for the Data Watchpoint and Trace (DWT)\r
+ @{\r
+ */\r
+\r
+/**\r
+ \brief Structure type to access the Data Watchpoint and Trace Register (DWT).\r
+ */\r
+typedef struct\r
+{\r
+ __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */\r
+ __IOM uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */\r
+ __IOM uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */\r
+ __IOM uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */\r
+ __IOM uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */\r
+ __IOM uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */\r
+ __IOM uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */\r
+ __IM uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */\r
+ __IOM uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */\r
+ __IOM uint32_t MASK0; /*!< Offset: 0x024 (R/W) Mask Register 0 */\r
+ __IOM uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */\r
+ uint32_t RESERVED0[1U];\r
+ __IOM uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */\r
+ __IOM uint32_t MASK1; /*!< Offset: 0x034 (R/W) Mask Register 1 */\r
+ __IOM uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */\r
+ uint32_t RESERVED1[1U];\r
+ __IOM uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */\r
+ __IOM uint32_t MASK2; /*!< Offset: 0x044 (R/W) Mask Register 2 */\r
+ __IOM uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */\r
+ uint32_t RESERVED2[1U];\r
+ __IOM uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */\r
+ __IOM uint32_t MASK3; /*!< Offset: 0x054 (R/W) Mask Register 3 */\r
+ __IOM uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */\r
+} DWT_Type;\r
+\r
+/* DWT Control Register Definitions */\r
+#define DWT_CTRL_NUMCOMP_Pos 28U /*!< DWT CTRL: NUMCOMP Position */\r
+#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */\r
+\r
+#define DWT_CTRL_NOTRCPKT_Pos 27U /*!< DWT CTRL: NOTRCPKT Position */\r
+#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */\r
+\r
+#define DWT_CTRL_NOEXTTRIG_Pos 26U /*!< DWT CTRL: NOEXTTRIG Position */\r
+#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */\r
+\r
+#define DWT_CTRL_NOCYCCNT_Pos 25U /*!< DWT CTRL: NOCYCCNT Position */\r
+#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */\r
+\r
+#define DWT_CTRL_NOPRFCNT_Pos 24U /*!< DWT CTRL: NOPRFCNT Position */\r
+#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */\r
+\r
+#define DWT_CTRL_CYCEVTENA_Pos 22U /*!< DWT CTRL: CYCEVTENA Position */\r
+#define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */\r
+\r
+#define DWT_CTRL_FOLDEVTENA_Pos 21U /*!< DWT CTRL: FOLDEVTENA Position */\r
+#define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */\r
+\r
+#define DWT_CTRL_LSUEVTENA_Pos 20U /*!< DWT CTRL: LSUEVTENA Position */\r
+#define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */\r
+\r
+#define DWT_CTRL_SLEEPEVTENA_Pos 19U /*!< DWT CTRL: SLEEPEVTENA Position */\r
+#define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */\r
+\r
+#define DWT_CTRL_EXCEVTENA_Pos 18U /*!< DWT CTRL: EXCEVTENA Position */\r
+#define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */\r
+\r
+#define DWT_CTRL_CPIEVTENA_Pos 17U /*!< DWT CTRL: CPIEVTENA Position */\r
+#define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */\r
+\r
+#define DWT_CTRL_EXCTRCENA_Pos 16U /*!< DWT CTRL: EXCTRCENA Position */\r
+#define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */\r
+\r
+#define DWT_CTRL_PCSAMPLENA_Pos 12U /*!< DWT CTRL: PCSAMPLENA Position */\r
+#define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */\r
+\r
+#define DWT_CTRL_SYNCTAP_Pos 10U /*!< DWT CTRL: SYNCTAP Position */\r
+#define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */\r
+\r
+#define DWT_CTRL_CYCTAP_Pos 9U /*!< DWT CTRL: CYCTAP Position */\r
+#define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */\r
+\r
+#define DWT_CTRL_POSTINIT_Pos 5U /*!< DWT CTRL: POSTINIT Position */\r
+#define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */\r
+\r
+#define DWT_CTRL_POSTPRESET_Pos 1U /*!< DWT CTRL: POSTPRESET Position */\r
+#define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */\r
+\r
+#define DWT_CTRL_CYCCNTENA_Pos 0U /*!< DWT CTRL: CYCCNTENA Position */\r
+#define DWT_CTRL_CYCCNTENA_Msk (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/) /*!< DWT CTRL: CYCCNTENA Mask */\r
+\r
+/* DWT CPI Count Register Definitions */\r
+#define DWT_CPICNT_CPICNT_Pos 0U /*!< DWT CPICNT: CPICNT Position */\r
+#define DWT_CPICNT_CPICNT_Msk (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/) /*!< DWT CPICNT: CPICNT Mask */\r
+\r
+/* DWT Exception Overhead Count Register Definitions */\r
+#define DWT_EXCCNT_EXCCNT_Pos 0U /*!< DWT EXCCNT: EXCCNT Position */\r
+#define DWT_EXCCNT_EXCCNT_Msk (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/) /*!< DWT EXCCNT: EXCCNT Mask */\r
+\r
+/* DWT Sleep Count Register Definitions */\r
+#define DWT_SLEEPCNT_SLEEPCNT_Pos 0U /*!< DWT SLEEPCNT: SLEEPCNT Position */\r
+#define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/) /*!< DWT SLEEPCNT: SLEEPCNT Mask */\r
+\r
+/* DWT LSU Count Register Definitions */\r
+#define DWT_LSUCNT_LSUCNT_Pos 0U /*!< DWT LSUCNT: LSUCNT Position */\r
+#define DWT_LSUCNT_LSUCNT_Msk (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/) /*!< DWT LSUCNT: LSUCNT Mask */\r
+\r
+/* DWT Folded-instruction Count Register Definitions */\r
+#define DWT_FOLDCNT_FOLDCNT_Pos 0U /*!< DWT FOLDCNT: FOLDCNT Position */\r
+#define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/) /*!< DWT FOLDCNT: FOLDCNT Mask */\r
+\r
+/* DWT Comparator Mask Register Definitions */\r
+#define DWT_MASK_MASK_Pos 0U /*!< DWT MASK: MASK Position */\r
+#define DWT_MASK_MASK_Msk (0x1FUL /*<< DWT_MASK_MASK_Pos*/) /*!< DWT MASK: MASK Mask */\r
+\r
+/* DWT Comparator Function Register Definitions */\r
+#define DWT_FUNCTION_MATCHED_Pos 24U /*!< DWT FUNCTION: MATCHED Position */\r
+#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */\r
+\r
+#define DWT_FUNCTION_DATAVADDR1_Pos 16U /*!< DWT FUNCTION: DATAVADDR1 Position */\r
+#define DWT_FUNCTION_DATAVADDR1_Msk (0xFUL << DWT_FUNCTION_DATAVADDR1_Pos) /*!< DWT FUNCTION: DATAVADDR1 Mask */\r
+\r
+#define DWT_FUNCTION_DATAVADDR0_Pos 12U /*!< DWT FUNCTION: DATAVADDR0 Position */\r
+#define DWT_FUNCTION_DATAVADDR0_Msk (0xFUL << DWT_FUNCTION_DATAVADDR0_Pos) /*!< DWT FUNCTION: DATAVADDR0 Mask */\r
+\r
+#define DWT_FUNCTION_DATAVSIZE_Pos 10U /*!< DWT FUNCTION: DATAVSIZE Position */\r
+#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */\r
+\r
+#define DWT_FUNCTION_LNK1ENA_Pos 9U /*!< DWT FUNCTION: LNK1ENA Position */\r
+#define DWT_FUNCTION_LNK1ENA_Msk (0x1UL << DWT_FUNCTION_LNK1ENA_Pos) /*!< DWT FUNCTION: LNK1ENA Mask */\r
+\r
+#define DWT_FUNCTION_DATAVMATCH_Pos 8U /*!< DWT FUNCTION: DATAVMATCH Position */\r
+#define DWT_FUNCTION_DATAVMATCH_Msk (0x1UL << DWT_FUNCTION_DATAVMATCH_Pos) /*!< DWT FUNCTION: DATAVMATCH Mask */\r
+\r
+#define DWT_FUNCTION_CYCMATCH_Pos 7U /*!< DWT FUNCTION: CYCMATCH Position */\r
+#define DWT_FUNCTION_CYCMATCH_Msk (0x1UL << DWT_FUNCTION_CYCMATCH_Pos) /*!< DWT FUNCTION: CYCMATCH Mask */\r
+\r
+#define DWT_FUNCTION_EMITRANGE_Pos 5U /*!< DWT FUNCTION: EMITRANGE Position */\r
+#define DWT_FUNCTION_EMITRANGE_Msk (0x1UL << DWT_FUNCTION_EMITRANGE_Pos) /*!< DWT FUNCTION: EMITRANGE Mask */\r
+\r
+#define DWT_FUNCTION_FUNCTION_Pos 0U /*!< DWT FUNCTION: FUNCTION Position */\r
+#define DWT_FUNCTION_FUNCTION_Msk (0xFUL /*<< DWT_FUNCTION_FUNCTION_Pos*/) /*!< DWT FUNCTION: FUNCTION Mask */\r
+\r
+/*@}*/ /* end of group CMSIS_DWT */\r
+\r
+\r
+/**\r
+ \ingroup CMSIS_core_register\r
+ \defgroup CMSIS_TPI Trace Port Interface (TPI)\r
+ \brief Type definitions for the Trace Port Interface (TPI)\r
+ @{\r
+ */\r
+\r
+/**\r
+ \brief Structure type to access the Trace Port Interface Register (TPI).\r
+ */\r
+typedef struct\r
+{\r
+ __IM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */\r
+ __IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */\r
+ uint32_t RESERVED0[2U];\r
+ __IOM uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */\r
+ uint32_t RESERVED1[55U];\r
+ __IOM uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */\r
+ uint32_t RESERVED2[131U];\r
+ __IM uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */\r
+ __IOM uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */\r
+ __IM uint32_t FSCR; /*!< Offset: 0x308 (R/ ) Formatter Synchronization Counter Register */\r
+ uint32_t RESERVED3[759U];\r
+ __IM uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER Register */\r
+ __IM uint32_t FIFO0; /*!< Offset: 0xEEC (R/ ) Integration ETM Data */\r
+ __IM uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/ ) ITATBCTR2 */\r
+ uint32_t RESERVED4[1U];\r
+ __IM uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) ITATBCTR0 */\r
+ __IM uint32_t FIFO1; /*!< Offset: 0xEFC (R/ ) Integration ITM Data */\r
+ __IOM uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */\r
+ uint32_t RESERVED5[39U];\r
+ __IOM uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */\r
+ __IOM uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */\r
+ uint32_t RESERVED7[8U];\r
+ __IM uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) TPIU_DEVID */\r
+ __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) TPIU_DEVTYPE */\r
+} TPI_Type;\r
+\r
+/* TPI Asynchronous Clock Prescaler Register Definitions */\r
+#define TPI_ACPR_PRESCALER_Pos 0U /*!< TPI ACPR: PRESCALER Position */\r
+#define TPI_ACPR_PRESCALER_Msk (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/) /*!< TPI ACPR: PRESCALER Mask */\r
+\r
+/* TPI Selected Pin Protocol Register Definitions */\r
+#define TPI_SPPR_TXMODE_Pos 0U /*!< TPI SPPR: TXMODE Position */\r
+#define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) /*!< TPI SPPR: TXMODE Mask */\r
+\r
+/* TPI Formatter and Flush Status Register Definitions */\r
+#define TPI_FFSR_FtNonStop_Pos 3U /*!< TPI FFSR: FtNonStop Position */\r
+#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */\r
+\r
+#define TPI_FFSR_TCPresent_Pos 2U /*!< TPI FFSR: TCPresent Position */\r
+#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */\r
+\r
+#define TPI_FFSR_FtStopped_Pos 1U /*!< TPI FFSR: FtStopped Position */\r
+#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */\r
+\r
+#define TPI_FFSR_FlInProg_Pos 0U /*!< TPI FFSR: FlInProg Position */\r
+#define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) /*!< TPI FFSR: FlInProg Mask */\r
+\r
+/* TPI Formatter and Flush Control Register Definitions */\r
+#define TPI_FFCR_TrigIn_Pos 8U /*!< TPI FFCR: TrigIn Position */\r
+#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */\r
+\r
+#define TPI_FFCR_EnFCont_Pos 1U /*!< TPI FFCR: EnFCont Position */\r
+#define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */\r
+\r
+/* TPI TRIGGER Register Definitions */\r
+#define TPI_TRIGGER_TRIGGER_Pos 0U /*!< TPI TRIGGER: TRIGGER Position */\r
+#define TPI_TRIGGER_TRIGGER_Msk (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/) /*!< TPI TRIGGER: TRIGGER Mask */\r
+\r
+/* TPI Integration ETM Data Register Definitions (FIFO0) */\r
+#define TPI_FIFO0_ITM_ATVALID_Pos 29U /*!< TPI FIFO0: ITM_ATVALID Position */\r
+#define TPI_FIFO0_ITM_ATVALID_Msk (0x3UL << TPI_FIFO0_ITM_ATVALID_Pos) /*!< TPI FIFO0: ITM_ATVALID Mask */\r
+\r
+#define TPI_FIFO0_ITM_bytecount_Pos 27U /*!< TPI FIFO0: ITM_bytecount Position */\r
+#define TPI_FIFO0_ITM_bytecount_Msk (0x3UL << TPI_FIFO0_ITM_bytecount_Pos) /*!< TPI FIFO0: ITM_bytecount Mask */\r
+\r
+#define TPI_FIFO0_ETM_ATVALID_Pos 26U /*!< TPI FIFO0: ETM_ATVALID Position */\r
+#define TPI_FIFO0_ETM_ATVALID_Msk (0x3UL << TPI_FIFO0_ETM_ATVALID_Pos) /*!< TPI FIFO0: ETM_ATVALID Mask */\r
+\r
+#define TPI_FIFO0_ETM_bytecount_Pos 24U /*!< TPI FIFO0: ETM_bytecount Position */\r
+#define TPI_FIFO0_ETM_bytecount_Msk (0x3UL << TPI_FIFO0_ETM_bytecount_Pos) /*!< TPI FIFO0: ETM_bytecount Mask */\r
+\r
+#define TPI_FIFO0_ETM2_Pos 16U /*!< TPI FIFO0: ETM2 Position */\r
+#define TPI_FIFO0_ETM2_Msk (0xFFUL << TPI_FIFO0_ETM2_Pos) /*!< TPI FIFO0: ETM2 Mask */\r
+\r
+#define TPI_FIFO0_ETM1_Pos 8U /*!< TPI FIFO0: ETM1 Position */\r
+#define TPI_FIFO0_ETM1_Msk (0xFFUL << TPI_FIFO0_ETM1_Pos) /*!< TPI FIFO0: ETM1 Mask */\r
+\r
+#define TPI_FIFO0_ETM0_Pos 0U /*!< TPI FIFO0: ETM0 Position */\r
+#define TPI_FIFO0_ETM0_Msk (0xFFUL /*<< TPI_FIFO0_ETM0_Pos*/) /*!< TPI FIFO0: ETM0 Mask */\r
+\r
+/* TPI ITATBCTR2 Register Definitions */\r
+#define TPI_ITATBCTR2_ATREADY2_Pos 0U /*!< TPI ITATBCTR2: ATREADY2 Position */\r
+#define TPI_ITATBCTR2_ATREADY2_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY2_Pos*/) /*!< TPI ITATBCTR2: ATREADY2 Mask */\r
+\r
+#define TPI_ITATBCTR2_ATREADY1_Pos 0U /*!< TPI ITATBCTR2: ATREADY1 Position */\r
+#define TPI_ITATBCTR2_ATREADY1_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY1_Pos*/) /*!< TPI ITATBCTR2: ATREADY1 Mask */\r
+\r
+/* TPI Integration ITM Data Register Definitions (FIFO1) */\r
+#define TPI_FIFO1_ITM_ATVALID_Pos 29U /*!< TPI FIFO1: ITM_ATVALID Position */\r
+#define TPI_FIFO1_ITM_ATVALID_Msk (0x3UL << TPI_FIFO1_ITM_ATVALID_Pos) /*!< TPI FIFO1: ITM_ATVALID Mask */\r
+\r
+#define TPI_FIFO1_ITM_bytecount_Pos 27U /*!< TPI FIFO1: ITM_bytecount Position */\r
+#define TPI_FIFO1_ITM_bytecount_Msk (0x3UL << TPI_FIFO1_ITM_bytecount_Pos) /*!< TPI FIFO1: ITM_bytecount Mask */\r
+\r
+#define TPI_FIFO1_ETM_ATVALID_Pos 26U /*!< TPI FIFO1: ETM_ATVALID Position */\r
+#define TPI_FIFO1_ETM_ATVALID_Msk (0x3UL << TPI_FIFO1_ETM_ATVALID_Pos) /*!< TPI FIFO1: ETM_ATVALID Mask */\r
+\r
+#define TPI_FIFO1_ETM_bytecount_Pos 24U /*!< TPI FIFO1: ETM_bytecount Position */\r
+#define TPI_FIFO1_ETM_bytecount_Msk (0x3UL << TPI_FIFO1_ETM_bytecount_Pos) /*!< TPI FIFO1: ETM_bytecount Mask */\r
+\r
+#define TPI_FIFO1_ITM2_Pos 16U /*!< TPI FIFO1: ITM2 Position */\r
+#define TPI_FIFO1_ITM2_Msk (0xFFUL << TPI_FIFO1_ITM2_Pos) /*!< TPI FIFO1: ITM2 Mask */\r
+\r
+#define TPI_FIFO1_ITM1_Pos 8U /*!< TPI FIFO1: ITM1 Position */\r
+#define TPI_FIFO1_ITM1_Msk (0xFFUL << TPI_FIFO1_ITM1_Pos) /*!< TPI FIFO1: ITM1 Mask */\r
+\r
+#define TPI_FIFO1_ITM0_Pos 0U /*!< TPI FIFO1: ITM0 Position */\r
+#define TPI_FIFO1_ITM0_Msk (0xFFUL /*<< TPI_FIFO1_ITM0_Pos*/) /*!< TPI FIFO1: ITM0 Mask */\r
+\r
+/* TPI ITATBCTR0 Register Definitions */\r
+#define TPI_ITATBCTR0_ATREADY2_Pos 0U /*!< TPI ITATBCTR0: ATREADY2 Position */\r
+#define TPI_ITATBCTR0_ATREADY2_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY2_Pos*/) /*!< TPI ITATBCTR0: ATREADY2 Mask */\r
+\r
+#define TPI_ITATBCTR0_ATREADY1_Pos 0U /*!< TPI ITATBCTR0: ATREADY1 Position */\r
+#define TPI_ITATBCTR0_ATREADY1_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY1_Pos*/) /*!< TPI ITATBCTR0: ATREADY1 Mask */\r
+\r
+/* TPI Integration Mode Control Register Definitions */\r
+#define TPI_ITCTRL_Mode_Pos 0U /*!< TPI ITCTRL: Mode Position */\r
+#define TPI_ITCTRL_Mode_Msk (0x3UL /*<< TPI_ITCTRL_Mode_Pos*/) /*!< TPI ITCTRL: Mode Mask */\r
+\r
+/* TPI DEVID Register Definitions */\r
+#define TPI_DEVID_NRZVALID_Pos 11U /*!< TPI DEVID: NRZVALID Position */\r
+#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */\r
+\r
+#define TPI_DEVID_MANCVALID_Pos 10U /*!< TPI DEVID: MANCVALID Position */\r
+#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */\r
+\r
+#define TPI_DEVID_PTINVALID_Pos 9U /*!< TPI DEVID: PTINVALID Position */\r
+#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */\r
+\r
+#define TPI_DEVID_MinBufSz_Pos 6U /*!< TPI DEVID: MinBufSz Position */\r
+#define TPI_DEVID_MinBufSz_Msk (0x7UL << TPI_DEVID_MinBufSz_Pos) /*!< TPI DEVID: MinBufSz Mask */\r
+\r
+#define TPI_DEVID_AsynClkIn_Pos 5U /*!< TPI DEVID: AsynClkIn Position */\r
+#define TPI_DEVID_AsynClkIn_Msk (0x1UL << TPI_DEVID_AsynClkIn_Pos) /*!< TPI DEVID: AsynClkIn Mask */\r
+\r
+#define TPI_DEVID_NrTraceInput_Pos 0U /*!< TPI DEVID: NrTraceInput Position */\r
+#define TPI_DEVID_NrTraceInput_Msk (0x1FUL /*<< TPI_DEVID_NrTraceInput_Pos*/) /*!< TPI DEVID: NrTraceInput Mask */\r
+\r
+/* TPI DEVTYPE Register Definitions */\r
+#define TPI_DEVTYPE_SubType_Pos 4U /*!< TPI DEVTYPE: SubType Position */\r
+#define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */\r
+\r
+#define TPI_DEVTYPE_MajorType_Pos 0U /*!< TPI DEVTYPE: MajorType Position */\r
+#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */\r
+\r
+/*@}*/ /* end of group CMSIS_TPI */\r
+\r
+\r
+#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)\r
+/**\r
+ \ingroup CMSIS_core_register\r
+ \defgroup CMSIS_MPU Memory Protection Unit (MPU)\r
+ \brief Type definitions for the Memory Protection Unit (MPU)\r
+ @{\r
+ */\r
+\r
+/**\r
+ \brief Structure type to access the Memory Protection Unit (MPU).\r
+ */\r
+typedef struct\r
+{\r
+ __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */\r
+ __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */\r
+ __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */\r
+ __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */\r
+ __IOM uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */\r
+ __IOM uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Alias 1 Region Base Address Register */\r
+ __IOM uint32_t RASR_A1; /*!< Offset: 0x018 (R/W) MPU Alias 1 Region Attribute and Size Register */\r
+ __IOM uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Alias 2 Region Base Address Register */\r
+ __IOM uint32_t RASR_A2; /*!< Offset: 0x020 (R/W) MPU Alias 2 Region Attribute and Size Register */\r
+ __IOM uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Alias 3 Region Base Address Register */\r
+ __IOM uint32_t RASR_A3; /*!< Offset: 0x028 (R/W) MPU Alias 3 Region Attribute and Size Register */\r
+} MPU_Type;\r
+\r
+#define MPU_TYPE_RALIASES 4U\r
+\r
+/* MPU Type Register Definitions */\r
+#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */\r
+#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */\r
+\r
+#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */\r
+#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */\r
+\r
+#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */\r
+#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */\r
+\r
+/* MPU Control Register Definitions */\r
+#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */\r
+#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */\r
+\r
+#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */\r
+#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */\r
+\r
+#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */\r
+#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */\r
+\r
+/* MPU Region Number Register Definitions */\r
+#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */\r
+#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */\r
+\r
+/* MPU Region Base Address Register Definitions */\r
+#define MPU_RBAR_ADDR_Pos 5U /*!< MPU RBAR: ADDR Position */\r
+#define MPU_RBAR_ADDR_Msk (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */\r
+\r
+#define MPU_RBAR_VALID_Pos 4U /*!< MPU RBAR: VALID Position */\r
+#define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */\r
+\r
+#define MPU_RBAR_REGION_Pos 0U /*!< MPU RBAR: REGION Position */\r
+#define MPU_RBAR_REGION_Msk (0xFUL /*<< MPU_RBAR_REGION_Pos*/) /*!< MPU RBAR: REGION Mask */\r
+\r
+/* MPU Region Attribute and Size Register Definitions */\r
+#define MPU_RASR_ATTRS_Pos 16U /*!< MPU RASR: MPU Region Attribute field Position */\r
+#define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */\r
+\r
+#define MPU_RASR_XN_Pos 28U /*!< MPU RASR: ATTRS.XN Position */\r
+#define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */\r
+\r
+#define MPU_RASR_AP_Pos 24U /*!< MPU RASR: ATTRS.AP Position */\r
+#define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */\r
+\r
+#define MPU_RASR_TEX_Pos 19U /*!< MPU RASR: ATTRS.TEX Position */\r
+#define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */\r
+\r
+#define MPU_RASR_S_Pos 18U /*!< MPU RASR: ATTRS.S Position */\r
+#define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */\r
+\r
+#define MPU_RASR_C_Pos 17U /*!< MPU RASR: ATTRS.C Position */\r
+#define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */\r
+\r
+#define MPU_RASR_B_Pos 16U /*!< MPU RASR: ATTRS.B Position */\r
+#define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */\r
+\r
+#define MPU_RASR_SRD_Pos 8U /*!< MPU RASR: Sub-Region Disable Position */\r
+#define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */\r
+\r
+#define MPU_RASR_SIZE_Pos 1U /*!< MPU RASR: Region Size Field Position */\r
+#define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */\r
+\r
+#define MPU_RASR_ENABLE_Pos 0U /*!< MPU RASR: Region enable bit Position */\r
+#define MPU_RASR_ENABLE_Msk (1UL /*<< MPU_RASR_ENABLE_Pos*/) /*!< MPU RASR: Region enable bit Disable Mask */\r
+\r
+/*@} end of group CMSIS_MPU */\r
+#endif\r
+\r
+\r
+/**\r
+ \ingroup CMSIS_core_register\r
+ \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug)\r
+ \brief Type definitions for the Core Debug Registers\r
+ @{\r
+ */\r
+\r
+/**\r
+ \brief Structure type to access the Core Debug Register (CoreDebug).\r
+ */\r
+typedef struct\r
+{\r
+ __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */\r
+ __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */\r
+ __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */\r
+ __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */\r
+} CoreDebug_Type;\r
+\r
+/* Debug Halting Control and Status Register Definitions */\r
+#define CoreDebug_DHCSR_DBGKEY_Pos 16U /*!< CoreDebug DHCSR: DBGKEY Position */\r
+#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */\r
+\r
+#define CoreDebug_DHCSR_S_RESET_ST_Pos 25U /*!< CoreDebug DHCSR: S_RESET_ST Position */\r
+#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */\r
+\r
+#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U /*!< CoreDebug DHCSR: S_RETIRE_ST Position */\r
+#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */\r
+\r
+#define CoreDebug_DHCSR_S_LOCKUP_Pos 19U /*!< CoreDebug DHCSR: S_LOCKUP Position */\r
+#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */\r
+\r
+#define CoreDebug_DHCSR_S_SLEEP_Pos 18U /*!< CoreDebug DHCSR: S_SLEEP Position */\r
+#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */\r
+\r
+#define CoreDebug_DHCSR_S_HALT_Pos 17U /*!< CoreDebug DHCSR: S_HALT Position */\r
+#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */\r
+\r
+#define CoreDebug_DHCSR_S_REGRDY_Pos 16U /*!< CoreDebug DHCSR: S_REGRDY Position */\r
+#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */\r
+\r
+#define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5U /*!< CoreDebug DHCSR: C_SNAPSTALL Position */\r
+#define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */\r
+\r
+#define CoreDebug_DHCSR_C_MASKINTS_Pos 3U /*!< CoreDebug DHCSR: C_MASKINTS Position */\r
+#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */\r
+\r
+#define CoreDebug_DHCSR_C_STEP_Pos 2U /*!< CoreDebug DHCSR: C_STEP Position */\r
+#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */\r
+\r
+#define CoreDebug_DHCSR_C_HALT_Pos 1U /*!< CoreDebug DHCSR: C_HALT Position */\r
+#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */\r
+\r
+#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U /*!< CoreDebug DHCSR: C_DEBUGEN Position */\r
+#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */\r
+\r
+/* Debug Core Register Selector Register Definitions */\r
+#define CoreDebug_DCRSR_REGWnR_Pos 16U /*!< CoreDebug DCRSR: REGWnR Position */\r
+#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */\r
+\r
+#define CoreDebug_DCRSR_REGSEL_Pos 0U /*!< CoreDebug DCRSR: REGSEL Position */\r
+#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/) /*!< CoreDebug DCRSR: REGSEL Mask */\r
+\r
+/* Debug Exception and Monitor Control Register Definitions */\r
+#define CoreDebug_DEMCR_TRCENA_Pos 24U /*!< CoreDebug DEMCR: TRCENA Position */\r
+#define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< CoreDebug DEMCR: TRCENA Mask */\r
+\r
+#define CoreDebug_DEMCR_MON_REQ_Pos 19U /*!< CoreDebug DEMCR: MON_REQ Position */\r
+#define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< CoreDebug DEMCR: MON_REQ Mask */\r
+\r
+#define CoreDebug_DEMCR_MON_STEP_Pos 18U /*!< CoreDebug DEMCR: MON_STEP Position */\r
+#define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< CoreDebug DEMCR: MON_STEP Mask */\r
+\r
+#define CoreDebug_DEMCR_MON_PEND_Pos 17U /*!< CoreDebug DEMCR: MON_PEND Position */\r
+#define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< CoreDebug DEMCR: MON_PEND Mask */\r
+\r
+#define CoreDebug_DEMCR_MON_EN_Pos 16U /*!< CoreDebug DEMCR: MON_EN Position */\r
+#define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< CoreDebug DEMCR: MON_EN Mask */\r
+\r
+#define CoreDebug_DEMCR_VC_HARDERR_Pos 10U /*!< CoreDebug DEMCR: VC_HARDERR Position */\r
+#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */\r
+\r
+#define CoreDebug_DEMCR_VC_INTERR_Pos 9U /*!< CoreDebug DEMCR: VC_INTERR Position */\r
+#define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< CoreDebug DEMCR: VC_INTERR Mask */\r
+\r
+#define CoreDebug_DEMCR_VC_BUSERR_Pos 8U /*!< CoreDebug DEMCR: VC_BUSERR Position */\r
+#define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< CoreDebug DEMCR: VC_BUSERR Mask */\r
+\r
+#define CoreDebug_DEMCR_VC_STATERR_Pos 7U /*!< CoreDebug DEMCR: VC_STATERR Position */\r
+#define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< CoreDebug DEMCR: VC_STATERR Mask */\r
+\r
+#define CoreDebug_DEMCR_VC_CHKERR_Pos 6U /*!< CoreDebug DEMCR: VC_CHKERR Position */\r
+#define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< CoreDebug DEMCR: VC_CHKERR Mask */\r
+\r
+#define CoreDebug_DEMCR_VC_NOCPERR_Pos 5U /*!< CoreDebug DEMCR: VC_NOCPERR Position */\r
+#define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< CoreDebug DEMCR: VC_NOCPERR Mask */\r
+\r
+#define CoreDebug_DEMCR_VC_MMERR_Pos 4U /*!< CoreDebug DEMCR: VC_MMERR Position */\r
+#define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< CoreDebug DEMCR: VC_MMERR Mask */\r
+\r
+#define CoreDebug_DEMCR_VC_CORERESET_Pos 0U /*!< CoreDebug DEMCR: VC_CORERESET Position */\r
+#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/) /*!< CoreDebug DEMCR: VC_CORERESET Mask */\r
+\r
+/*@} end of group CMSIS_CoreDebug */\r
+\r
+\r
+/**\r
+ \ingroup CMSIS_core_register\r
+ \defgroup CMSIS_core_bitfield Core register bit field macros\r
+ \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk).\r
+ @{\r
+ */\r
+\r
+/**\r
+ \brief Mask and shift a bit field value for use in a register bit range.\r
+ \param[in] field Name of the register bit field.\r
+ \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type.\r
+ \return Masked and shifted value.\r
+*/\r
+#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk)\r
+\r
+/**\r
+ \brief Mask and shift a register value to extract a bit filed value.\r
+ \param[in] field Name of the register bit field.\r
+ \param[in] value Value of register. This parameter is interpreted as an uint32_t type.\r
+ \return Masked and shifted bit field value.\r
+*/\r
+#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos)\r
+\r
+/*@} end of group CMSIS_core_bitfield */\r
+\r
+\r
+/**\r
+ \ingroup CMSIS_core_register\r
+ \defgroup CMSIS_core_base Core Definitions\r
+ \brief Definitions for base addresses, unions, and structures.\r
+ @{\r
+ */\r
+\r
+/* Memory mapping of Core Hardware */\r
+#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */\r
+#define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */\r
+#define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */\r
+#define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */\r
+#define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */\r
+#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */\r
+#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */\r
+#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */\r
+\r
+#define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */\r
+#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */\r
+#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */\r
+#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */\r
+#define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */\r
+#define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */\r
+#define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */\r
+#define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE) /*!< Core Debug configuration struct */\r
+\r
+#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)\r
+ #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */\r
+ #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */\r
+#endif\r
+\r
+/*@} */\r
+\r
+\r
+\r
+/*******************************************************************************\r
+ * Hardware Abstraction Layer\r
+ Core Function Interface contains:\r
+ - Core NVIC Functions\r
+ - Core SysTick Functions\r
+ - Core Debug Functions\r
+ - Core Register Access Functions\r
+ ******************************************************************************/\r
+/**\r
+ \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference\r
+*/\r
+\r
+\r
+\r
+/* ########################## NVIC functions #################################### */\r
+/**\r
+ \ingroup CMSIS_Core_FunctionInterface\r
+ \defgroup CMSIS_Core_NVICFunctions NVIC Functions\r
+ \brief Functions that manage interrupts and exceptions via the NVIC.\r
+ @{\r
+ */\r
+\r
+#ifdef CMSIS_NVIC_VIRTUAL\r
+ #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE\r
+ #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h"\r
+ #endif\r
+ #include CMSIS_NVIC_VIRTUAL_HEADER_FILE\r
+#else\r
+ #define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping\r
+ #define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping\r
+ #define NVIC_EnableIRQ __NVIC_EnableIRQ\r
+ #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ\r
+ #define NVIC_DisableIRQ __NVIC_DisableIRQ\r
+ #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ\r
+ #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ\r
+ #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ\r
+ #define NVIC_GetActive __NVIC_GetActive\r
+ #define NVIC_SetPriority __NVIC_SetPriority\r
+ #define NVIC_GetPriority __NVIC_GetPriority\r
+ #define NVIC_SystemReset __NVIC_SystemReset\r
+#endif /* CMSIS_NVIC_VIRTUAL */\r
+\r
+#ifdef CMSIS_VECTAB_VIRTUAL\r
+ #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE\r
+ #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h"\r
+ #endif\r
+ #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE\r
+#else\r
+ #define NVIC_SetVector __NVIC_SetVector\r
+ #define NVIC_GetVector __NVIC_GetVector\r
+#endif /* (CMSIS_VECTAB_VIRTUAL) */\r
+\r
+#define NVIC_USER_IRQ_OFFSET 16\r
+\r
+\r
+/* The following EXC_RETURN values are saved the LR on exception entry */\r
+#define EXC_RETURN_HANDLER (0xFFFFFFF1UL) /* return to Handler mode, uses MSP after return */\r
+#define EXC_RETURN_THREAD_MSP (0xFFFFFFF9UL) /* return to Thread mode, uses MSP after return */\r
+#define EXC_RETURN_THREAD_PSP (0xFFFFFFFDUL) /* return to Thread mode, uses PSP after return */\r
+\r
+\r
+/**\r
+ \brief Set Priority Grouping\r
+ \details Sets the priority grouping field using the required unlock sequence.\r
+ The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field.\r
+ Only values from 0..7 are used.\r
+ In case of a conflict between priority grouping and available\r
+ priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.\r
+ \param [in] PriorityGroup Priority grouping field.\r
+ */\r
+__STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup)\r
+{\r
+ uint32_t reg_value;\r
+ uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */\r
+\r
+ reg_value = SCB->AIRCR; /* read old register configuration */\r
+ reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */\r
+ reg_value = (reg_value |\r
+ ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |\r
+ (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key and priority group */\r
+ SCB->AIRCR = reg_value;\r
+}\r
+\r
+\r
+/**\r
+ \brief Get Priority Grouping\r
+ \details Reads the priority grouping field from the NVIC Interrupt Controller.\r
+ \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field).\r
+ */\r
+__STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void)\r
+{\r
+ return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos));\r
+}\r
+\r
+\r
+/**\r
+ \brief Enable Interrupt\r
+ \details Enables a device specific interrupt in the NVIC interrupt controller.\r
+ \param [in] IRQn Device specific interrupt number.\r
+ \note IRQn must not be negative.\r
+ */\r
+__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn)\r
+{\r
+ if ((int32_t)(IRQn) >= 0)\r
+ {\r
+ NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));\r
+ }\r
+}\r
+\r
+\r
+/**\r
+ \brief Get Interrupt Enable status\r
+ \details Returns a device specific interrupt enable status from the NVIC interrupt controller.\r
+ \param [in] IRQn Device specific interrupt number.\r
+ \return 0 Interrupt is not enabled.\r
+ \return 1 Interrupt is enabled.\r
+ \note IRQn must not be negative.\r
+ */\r
+__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn)\r
+{\r
+ if ((int32_t)(IRQn) >= 0)\r
+ {\r
+ return((uint32_t)(((NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));\r
+ }\r
+ else\r
+ {\r
+ return(0U);\r
+ }\r
+}\r
+\r
+\r
+/**\r
+ \brief Disable Interrupt\r
+ \details Disables a device specific interrupt in the NVIC interrupt controller.\r
+ \param [in] IRQn Device specific interrupt number.\r
+ \note IRQn must not be negative.\r
+ */\r
+__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn)\r
+{\r
+ if ((int32_t)(IRQn) >= 0)\r
+ {\r
+ NVIC->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));\r
+ __DSB();\r
+ __ISB();\r
+ }\r
+}\r
+\r
+\r
+/**\r
+ \brief Get Pending Interrupt\r
+ \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt.\r
+ \param [in] IRQn Device specific interrupt number.\r
+ \return 0 Interrupt status is not pending.\r
+ \return 1 Interrupt status is pending.\r
+ \note IRQn must not be negative.\r
+ */\r
+__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn)\r
+{\r
+ if ((int32_t)(IRQn) >= 0)\r
+ {\r
+ return((uint32_t)(((NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));\r
+ }\r
+ else\r
+ {\r
+ return(0U);\r
+ }\r
+}\r
+\r
+\r
+/**\r
+ \brief Set Pending Interrupt\r
+ \details Sets the pending bit of a device specific interrupt in the NVIC pending register.\r
+ \param [in] IRQn Device specific interrupt number.\r
+ \note IRQn must not be negative.\r
+ */\r
+__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn)\r
+{\r
+ if ((int32_t)(IRQn) >= 0)\r
+ {\r
+ NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));\r
+ }\r
+}\r
+\r
+\r
+/**\r
+ \brief Clear Pending Interrupt\r
+ \details Clears the pending bit of a device specific interrupt in the NVIC pending register.\r
+ \param [in] IRQn Device specific interrupt number.\r
+ \note IRQn must not be negative.\r
+ */\r
+__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn)\r
+{\r
+ if ((int32_t)(IRQn) >= 0)\r
+ {\r
+ NVIC->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));\r
+ }\r
+}\r
+\r
+\r
+/**\r
+ \brief Get Active Interrupt\r
+ \details Reads the active register in the NVIC and returns the active bit for the device specific interrupt.\r
+ \param [in] IRQn Device specific interrupt number.\r
+ \return 0 Interrupt status is not active.\r
+ \return 1 Interrupt status is active.\r
+ \note IRQn must not be negative.\r
+ */\r
+__STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn)\r
+{\r
+ if ((int32_t)(IRQn) >= 0)\r
+ {\r
+ return((uint32_t)(((NVIC->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));\r
+ }\r
+ else\r
+ {\r
+ return(0U);\r
+ }\r
+}\r
+\r
+\r
+/**\r
+ \brief Set Interrupt Priority\r
+ \details Sets the priority of a device specific interrupt or a processor exception.\r
+ The interrupt number can be positive to specify a device specific interrupt,\r
+ or negative to specify a processor exception.\r
+ \param [in] IRQn Interrupt number.\r
+ \param [in] priority Priority to set.\r
+ \note The priority cannot be set for every processor exception.\r
+ */\r
+__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)\r
+{\r
+ if ((int32_t)(IRQn) >= 0)\r
+ {\r
+ NVIC->IP[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);\r
+ }\r
+ else\r
+ {\r
+ SCB->SHP[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);\r
+ }\r
+}\r
+\r
+\r
+/**\r
+ \brief Get Interrupt Priority\r
+ \details Reads the priority of a device specific interrupt or a processor exception.\r
+ The interrupt number can be positive to specify a device specific interrupt,\r
+ or negative to specify a processor exception.\r
+ \param [in] IRQn Interrupt number.\r
+ \return Interrupt Priority.\r
+ Value is aligned automatically to the implemented priority bits of the microcontroller.\r
+ */\r
+__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn)\r
+{\r
+\r
+ if ((int32_t)(IRQn) >= 0)\r
+ {\r
+ return(((uint32_t)NVIC->IP[((uint32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS)));\r
+ }\r
+ else\r
+ {\r
+ return(((uint32_t)SCB->SHP[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS)));\r
+ }\r
+}\r
+\r
+\r
+/**\r
+ \brief Encode Priority\r
+ \details Encodes the priority for an interrupt with the given priority group,\r
+ preemptive priority value, and subpriority value.\r
+ In case of a conflict between priority grouping and available\r
+ priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.\r
+ \param [in] PriorityGroup Used priority group.\r
+ \param [in] PreemptPriority Preemptive priority value (starting from 0).\r
+ \param [in] SubPriority Subpriority value (starting from 0).\r
+ \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority().\r
+ */\r
+__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)\r
+{\r
+ uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */\r
+ uint32_t PreemptPriorityBits;\r
+ uint32_t SubPriorityBits;\r
+\r
+ PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);\r
+ SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));\r
+\r
+ return (\r
+ ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) |\r
+ ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL)))\r
+ );\r
+}\r
+\r
+\r
+/**\r
+ \brief Decode Priority\r
+ \details Decodes an interrupt priority value with a given priority group to\r
+ preemptive priority value and subpriority value.\r
+ In case of a conflict between priority grouping and available\r
+ priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set.\r
+ \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority().\r
+ \param [in] PriorityGroup Used priority group.\r
+ \param [out] pPreemptPriority Preemptive priority value (starting from 0).\r
+ \param [out] pSubPriority Subpriority value (starting from 0).\r
+ */\r
+__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority)\r
+{\r
+ uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */\r
+ uint32_t PreemptPriorityBits;\r
+ uint32_t SubPriorityBits;\r
+\r
+ PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);\r
+ SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));\r
+\r
+ *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL);\r
+ *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL);\r
+}\r
+\r
+\r
+/**\r
+ \brief Set Interrupt Vector\r
+ \details Sets an interrupt vector in SRAM based interrupt vector table.\r
+ The interrupt number can be positive to specify a device specific interrupt,\r
+ or negative to specify a processor exception.\r
+ VTOR must been relocated to SRAM before.\r
+ \param [in] IRQn Interrupt number\r
+ \param [in] vector Address of interrupt handler function\r
+ */\r
+__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector)\r
+{\r
+ uint32_t *vectors = (uint32_t *)SCB->VTOR;\r
+ vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector;\r
+}\r
+\r
+\r
+/**\r
+ \brief Get Interrupt Vector\r
+ \details Reads an interrupt vector from interrupt vector table.\r
+ The interrupt number can be positive to specify a device specific interrupt,\r
+ or negative to specify a processor exception.\r
+ \param [in] IRQn Interrupt number.\r
+ \return Address of interrupt handler function\r
+ */\r
+__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn)\r
+{\r
+ uint32_t *vectors = (uint32_t *)SCB->VTOR;\r
+ return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET];\r
+}\r
+\r
+\r
+/**\r
+ \brief System Reset\r
+ \details Initiates a system reset request to reset the MCU.\r
+ */\r
+__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void)\r
+{\r
+ __DSB(); /* Ensure all outstanding memory accesses included\r
+ buffered write are completed before reset */\r
+ SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |\r
+ (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) |\r
+ SCB_AIRCR_SYSRESETREQ_Msk ); /* Keep priority group unchanged */\r
+ __DSB(); /* Ensure completion of memory access */\r
+\r
+ for(;;) /* wait until reset */\r
+ {\r
+ __NOP();\r
+ }\r
+}\r
+\r
+/*@} end of CMSIS_Core_NVICFunctions */\r
+\r
+/* ########################## MPU functions #################################### */\r
+\r
+#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)\r
+\r
+#include "mpu_armv7.h"\r
+\r
+#endif\r
+\r
+/* ########################## FPU functions #################################### */\r
+/**\r
+ \ingroup CMSIS_Core_FunctionInterface\r
+ \defgroup CMSIS_Core_FpuFunctions FPU Functions\r
+ \brief Function that provides FPU type.\r
+ @{\r
+ */\r
+\r
+/**\r
+ \brief get FPU type\r
+ \details returns the FPU type\r
+ \returns\r
+ - \b 0: No FPU\r
+ - \b 1: Single precision FPU\r
+ - \b 2: Double + Single precision FPU\r
+ */\r
+__STATIC_INLINE uint32_t SCB_GetFPUType(void)\r
+{\r
+ return 0U; /* No FPU */\r
+}\r
+\r
+\r
+/*@} end of CMSIS_Core_FpuFunctions */\r
+\r
+\r
+\r
+/* ################################## SysTick function ############################################ */\r
+/**\r
+ \ingroup CMSIS_Core_FunctionInterface\r
+ \defgroup CMSIS_Core_SysTickFunctions SysTick Functions\r
+ \brief Functions that configure the System.\r
+ @{\r
+ */\r
+\r
+#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U)\r
+\r
+/**\r
+ \brief System Tick Configuration\r
+ \details Initializes the System Timer and its interrupt, and starts the System Tick Timer.\r
+ Counter is in free running mode to generate periodic interrupts.\r
+ \param [in] ticks Number of ticks between two interrupts.\r
+ \return 0 Function succeeded.\r
+ \return 1 Function failed.\r
+ \note When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the\r
+ function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>\r
+ must contain a vendor-specific implementation of this function.\r
+ */\r
+__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)\r
+{\r
+ if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk)\r
+ {\r
+ return (1UL); /* Reload value impossible */\r
+ }\r
+\r
+ SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */\r
+ NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */\r
+ SysTick->VAL = 0UL; /* Load the SysTick Counter Value */\r
+ SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk |\r
+ SysTick_CTRL_TICKINT_Msk |\r
+ SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */\r
+ return (0UL); /* Function successful */\r
+}\r
+\r
+#endif\r
+\r
+/*@} end of CMSIS_Core_SysTickFunctions */\r
+\r
+\r
+\r
+/* ##################################### Debug In/Output function ########################################### */\r
+/**\r
+ \ingroup CMSIS_Core_FunctionInterface\r
+ \defgroup CMSIS_core_DebugFunctions ITM Functions\r
+ \brief Functions that access the ITM debug interface.\r
+ @{\r
+ */\r
+\r
+extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters. */\r
+#define ITM_RXBUFFER_EMPTY ((int32_t)0x5AA55AA5U) /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */\r
+\r
+\r
+/**\r
+ \brief ITM Send Character\r
+ \details Transmits a character via the ITM channel 0, and\r
+ \li Just returns when no debugger is connected that has booked the output.\r
+ \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted.\r
+ \param [in] ch Character to transmit.\r
+ \returns Character to transmit.\r
+ */\r
+__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch)\r
+{\r
+ if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) && /* ITM enabled */\r
+ ((ITM->TER & 1UL ) != 0UL) ) /* ITM Port #0 enabled */\r
+ {\r
+ while (ITM->PORT[0U].u32 == 0UL)\r
+ {\r
+ __NOP();\r
+ }\r
+ ITM->PORT[0U].u8 = (uint8_t)ch;\r
+ }\r
+ return (ch);\r
+}\r
+\r
+\r
+/**\r
+ \brief ITM Receive Character\r
+ \details Inputs a character via the external variable \ref ITM_RxBuffer.\r
+ \return Received character.\r
+ \return -1 No character pending.\r
+ */\r
+__STATIC_INLINE int32_t ITM_ReceiveChar (void)\r
+{\r
+ int32_t ch = -1; /* no character available */\r
+\r
+ if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY)\r
+ {\r
+ ch = ITM_RxBuffer;\r
+ ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */\r
+ }\r
+\r
+ return (ch);\r
+}\r
+\r
+\r
+/**\r
+ \brief ITM Check Character\r
+ \details Checks whether a character is pending for reading in the variable \ref ITM_RxBuffer.\r
+ \return 0 No character available.\r
+ \return 1 Character available.\r
+ */\r
+__STATIC_INLINE int32_t ITM_CheckChar (void)\r
+{\r
+\r
+ if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY)\r
+ {\r
+ return (0); /* no character available */\r
+ }\r
+ else\r
+ {\r
+ return (1); /* character available */\r
+ }\r
+}\r
+\r
+/*@} end of CMSIS_core_DebugFunctions */\r
+\r
+\r
+\r
+\r
+#ifdef __cplusplus\r
+}\r
+#endif\r
+\r
+#endif /* __CORE_CM3_H_DEPENDANT */\r
+\r
+#endif /* __CMSIS_GENERIC */\r
--- /dev/null
+/**************************************************************************//**\r
+ * @file core_cm33.h\r
+ * @brief CMSIS Cortex-M33 Core Peripheral Access Layer Header File\r
+ * @version V5.0.9\r
+ * @date 06. July 2018\r
+ ******************************************************************************/\r
+/*\r
+ * Copyright (c) 2009-2018 Arm Limited. All rights reserved.\r
+ *\r
+ * SPDX-License-Identifier: Apache-2.0\r
+ *\r
+ * Licensed under the Apache License, Version 2.0 (the License); you may\r
+ * not use this file except in compliance with the License.\r
+ * You may obtain a copy of the License at\r
+ *\r
+ * www.apache.org/licenses/LICENSE-2.0\r
+ *\r
+ * Unless required by applicable law or agreed to in writing, software\r
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT\r
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\r
+ * See the License for the specific language governing permissions and\r
+ * limitations under the License.\r
+ */\r
+\r
+#if defined ( __ICCARM__ )\r
+ #pragma system_include /* treat file as system include file for MISRA check */\r
+#elif defined (__clang__)\r
+ #pragma clang system_header /* treat file as system include file */\r
+#endif\r
+\r
+#ifndef __CORE_CM33_H_GENERIC\r
+#define __CORE_CM33_H_GENERIC\r
+\r
+#include <stdint.h>\r
+\r
+#ifdef __cplusplus\r
+ extern "C" {\r
+#endif\r
+\r
+/**\r
+ \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions\r
+ CMSIS violates the following MISRA-C:2004 rules:\r
+\r
+ \li Required Rule 8.5, object/function definition in header file.<br>\r
+ Function definitions in header files are used to allow 'inlining'.\r
+\r
+ \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>\r
+ Unions are used for effective representation of core registers.\r
+\r
+ \li Advisory Rule 19.7, Function-like macro defined.<br>\r
+ Function-like macros are used to allow more efficient code.\r
+ */\r
+\r
+\r
+/*******************************************************************************\r
+ * CMSIS definitions\r
+ ******************************************************************************/\r
+/**\r
+ \ingroup Cortex_M33\r
+ @{\r
+ */\r
+\r
+#include "cmsis_version.h"\r
+\r
+/* CMSIS CM33 definitions */\r
+#define __CM33_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */\r
+#define __CM33_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */\r
+#define __CM33_CMSIS_VERSION ((__CM33_CMSIS_VERSION_MAIN << 16U) | \\r
+ __CM33_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */\r
+\r
+#define __CORTEX_M (33U) /*!< Cortex-M Core */\r
+\r
+/** __FPU_USED indicates whether an FPU is used or not.\r
+ For this, __FPU_PRESENT has to be checked prior to making use of FPU specific registers and functions.\r
+*/\r
+#if defined ( __CC_ARM )\r
+ #if defined (__TARGET_FPU_VFP)\r
+ #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)\r
+ #define __FPU_USED 1U\r
+ #else\r
+ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"\r
+ #define __FPU_USED 0U\r
+ #endif\r
+ #else\r
+ #define __FPU_USED 0U\r
+ #endif\r
+\r
+ #if defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1U)\r
+ #if defined (__DSP_PRESENT) && (__DSP_PRESENT == 1U)\r
+ #define __DSP_USED 1U\r
+ #else\r
+ #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)"\r
+ #define __DSP_USED 0U\r
+ #endif\r
+ #else\r
+ #define __DSP_USED 0U\r
+ #endif\r
+\r
+#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)\r
+ #if defined (__ARM_PCS_VFP)\r
+ #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)\r
+ #define __FPU_USED 1U\r
+ #else\r
+ #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"\r
+ #define __FPU_USED 0U\r
+ #endif\r
+ #else\r
+ #define __FPU_USED 0U\r
+ #endif\r
+\r
+ #if defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1U)\r
+ #if defined (__DSP_PRESENT) && (__DSP_PRESENT == 1U)\r
+ #define __DSP_USED 1U\r
+ #else\r
+ #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)"\r
+ #define __DSP_USED 0U\r
+ #endif\r
+ #else\r
+ #define __DSP_USED 0U\r
+ #endif\r
+\r
+#elif defined ( __GNUC__ )\r
+ #if defined (__VFP_FP__) && !defined(__SOFTFP__)\r
+ #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)\r
+ #define __FPU_USED 1U\r
+ #else\r
+ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"\r
+ #define __FPU_USED 0U\r
+ #endif\r
+ #else\r
+ #define __FPU_USED 0U\r
+ #endif\r
+\r
+ #if defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1U)\r
+ #if defined (__DSP_PRESENT) && (__DSP_PRESENT == 1U)\r
+ #define __DSP_USED 1U\r
+ #else\r
+ #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)"\r
+ #define __DSP_USED 0U\r
+ #endif\r
+ #else\r
+ #define __DSP_USED 0U\r
+ #endif\r
+\r
+#elif defined ( __ICCARM__ )\r
+ #if defined (__ARMVFP__)\r
+ #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)\r
+ #define __FPU_USED 1U\r
+ #else\r
+ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"\r
+ #define __FPU_USED 0U\r
+ #endif\r
+ #else\r
+ #define __FPU_USED 0U\r
+ #endif\r
+\r
+ #if defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1U)\r
+ #if defined (__DSP_PRESENT) && (__DSP_PRESENT == 1U)\r
+ #define __DSP_USED 1U\r
+ #else\r
+ #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)"\r
+ #define __DSP_USED 0U\r
+ #endif\r
+ #else\r
+ #define __DSP_USED 0U\r
+ #endif\r
+\r
+#elif defined ( __TI_ARM__ )\r
+ #if defined (__TI_VFP_SUPPORT__)\r
+ #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)\r
+ #define __FPU_USED 1U\r
+ #else\r
+ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"\r
+ #define __FPU_USED 0U\r
+ #endif\r
+ #else\r
+ #define __FPU_USED 0U\r
+ #endif\r
+\r
+#elif defined ( __TASKING__ )\r
+ #if defined (__FPU_VFP__)\r
+ #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)\r
+ #define __FPU_USED 1U\r
+ #else\r
+ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"\r
+ #define __FPU_USED 0U\r
+ #endif\r
+ #else\r
+ #define __FPU_USED 0U\r
+ #endif\r
+\r
+#elif defined ( __CSMC__ )\r
+ #if ( __CSMC__ & 0x400U)\r
+ #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)\r
+ #define __FPU_USED 1U\r
+ #else\r
+ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"\r
+ #define __FPU_USED 0U\r
+ #endif\r
+ #else\r
+ #define __FPU_USED 0U\r
+ #endif\r
+\r
+#endif\r
+\r
+#include "cmsis_compiler.h" /* CMSIS compiler specific defines */\r
+\r
+\r
+#ifdef __cplusplus\r
+}\r
+#endif\r
+\r
+#endif /* __CORE_CM33_H_GENERIC */\r
+\r
+#ifndef __CMSIS_GENERIC\r
+\r
+#ifndef __CORE_CM33_H_DEPENDANT\r
+#define __CORE_CM33_H_DEPENDANT\r
+\r
+#ifdef __cplusplus\r
+ extern "C" {\r
+#endif\r
+\r
+/* check device defines and use defaults */\r
+#if defined __CHECK_DEVICE_DEFINES\r
+ #ifndef __CM33_REV\r
+ #define __CM33_REV 0x0000U\r
+ #warning "__CM33_REV not defined in device header file; using default!"\r
+ #endif\r
+\r
+ #ifndef __FPU_PRESENT\r
+ #define __FPU_PRESENT 0U\r
+ #warning "__FPU_PRESENT not defined in device header file; using default!"\r
+ #endif\r
+\r
+ #ifndef __MPU_PRESENT\r
+ #define __MPU_PRESENT 0U\r
+ #warning "__MPU_PRESENT not defined in device header file; using default!"\r
+ #endif\r
+\r
+ #ifndef __SAUREGION_PRESENT\r
+ #define __SAUREGION_PRESENT 0U\r
+ #warning "__SAUREGION_PRESENT not defined in device header file; using default!"\r
+ #endif\r
+\r
+ #ifndef __DSP_PRESENT\r
+ #define __DSP_PRESENT 0U\r
+ #warning "__DSP_PRESENT not defined in device header file; using default!"\r
+ #endif\r
+\r
+ #ifndef __NVIC_PRIO_BITS\r
+ #define __NVIC_PRIO_BITS 3U\r
+ #warning "__NVIC_PRIO_BITS not defined in device header file; using default!"\r
+ #endif\r
+\r
+ #ifndef __Vendor_SysTickConfig\r
+ #define __Vendor_SysTickConfig 0U\r
+ #warning "__Vendor_SysTickConfig not defined in device header file; using default!"\r
+ #endif\r
+#endif\r
+\r
+/* IO definitions (access restrictions to peripheral registers) */\r
+/**\r
+ \defgroup CMSIS_glob_defs CMSIS Global Defines\r
+\r
+ <strong>IO Type Qualifiers</strong> are used\r
+ \li to specify the access to peripheral variables.\r
+ \li for automatic generation of peripheral register debug information.\r
+*/\r
+#ifdef __cplusplus\r
+ #define __I volatile /*!< Defines 'read only' permissions */\r
+#else\r
+ #define __I volatile const /*!< Defines 'read only' permissions */\r
+#endif\r
+#define __O volatile /*!< Defines 'write only' permissions */\r
+#define __IO volatile /*!< Defines 'read / write' permissions */\r
+\r
+/* following defines should be used for structure members */\r
+#define __IM volatile const /*! Defines 'read only' structure member permissions */\r
+#define __OM volatile /*! Defines 'write only' structure member permissions */\r
+#define __IOM volatile /*! Defines 'read / write' structure member permissions */\r
+\r
+/*@} end of group Cortex_M33 */\r
+\r
+\r
+\r
+/*******************************************************************************\r
+ * Register Abstraction\r
+ Core Register contain:\r
+ - Core Register\r
+ - Core NVIC Register\r
+ - Core SCB Register\r
+ - Core SysTick Register\r
+ - Core Debug Register\r
+ - Core MPU Register\r
+ - Core SAU Register\r
+ - Core FPU Register\r
+ ******************************************************************************/\r
+/**\r
+ \defgroup CMSIS_core_register Defines and Type Definitions\r
+ \brief Type definitions and defines for Cortex-M processor based devices.\r
+*/\r
+\r
+/**\r
+ \ingroup CMSIS_core_register\r
+ \defgroup CMSIS_CORE Status and Control Registers\r
+ \brief Core Register type definitions.\r
+ @{\r
+ */\r
+\r
+/**\r
+ \brief Union type to access the Application Program Status Register (APSR).\r
+ */\r
+typedef union\r
+{\r
+ struct\r
+ {\r
+ uint32_t _reserved0:16; /*!< bit: 0..15 Reserved */\r
+ uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */\r
+ uint32_t _reserved1:7; /*!< bit: 20..26 Reserved */\r
+ uint32_t Q:1; /*!< bit: 27 Saturation condition flag */\r
+ uint32_t V:1; /*!< bit: 28 Overflow condition code flag */\r
+ uint32_t C:1; /*!< bit: 29 Carry condition code flag */\r
+ uint32_t Z:1; /*!< bit: 30 Zero condition code flag */\r
+ uint32_t N:1; /*!< bit: 31 Negative condition code flag */\r
+ } b; /*!< Structure used for bit access */\r
+ uint32_t w; /*!< Type used for word access */\r
+} APSR_Type;\r
+\r
+/* APSR Register Definitions */\r
+#define APSR_N_Pos 31U /*!< APSR: N Position */\r
+#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */\r
+\r
+#define APSR_Z_Pos 30U /*!< APSR: Z Position */\r
+#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */\r
+\r
+#define APSR_C_Pos 29U /*!< APSR: C Position */\r
+#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */\r
+\r
+#define APSR_V_Pos 28U /*!< APSR: V Position */\r
+#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */\r
+\r
+#define APSR_Q_Pos 27U /*!< APSR: Q Position */\r
+#define APSR_Q_Msk (1UL << APSR_Q_Pos) /*!< APSR: Q Mask */\r
+\r
+#define APSR_GE_Pos 16U /*!< APSR: GE Position */\r
+#define APSR_GE_Msk (0xFUL << APSR_GE_Pos) /*!< APSR: GE Mask */\r
+\r
+\r
+/**\r
+ \brief Union type to access the Interrupt Program Status Register (IPSR).\r
+ */\r
+typedef union\r
+{\r
+ struct\r
+ {\r
+ uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */\r
+ uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */\r
+ } b; /*!< Structure used for bit access */\r
+ uint32_t w; /*!< Type used for word access */\r
+} IPSR_Type;\r
+\r
+/* IPSR Register Definitions */\r
+#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */\r
+#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */\r
+\r
+\r
+/**\r
+ \brief Union type to access the Special-Purpose Program Status Registers (xPSR).\r
+ */\r
+typedef union\r
+{\r
+ struct\r
+ {\r
+ uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */\r
+ uint32_t _reserved0:7; /*!< bit: 9..15 Reserved */\r
+ uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */\r
+ uint32_t _reserved1:4; /*!< bit: 20..23 Reserved */\r
+ uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */\r
+ uint32_t IT:2; /*!< bit: 25..26 saved IT state (read 0) */\r
+ uint32_t Q:1; /*!< bit: 27 Saturation condition flag */\r
+ uint32_t V:1; /*!< bit: 28 Overflow condition code flag */\r
+ uint32_t C:1; /*!< bit: 29 Carry condition code flag */\r
+ uint32_t Z:1; /*!< bit: 30 Zero condition code flag */\r
+ uint32_t N:1; /*!< bit: 31 Negative condition code flag */\r
+ } b; /*!< Structure used for bit access */\r
+ uint32_t w; /*!< Type used for word access */\r
+} xPSR_Type;\r
+\r
+/* xPSR Register Definitions */\r
+#define xPSR_N_Pos 31U /*!< xPSR: N Position */\r
+#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */\r
+\r
+#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */\r
+#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */\r
+\r
+#define xPSR_C_Pos 29U /*!< xPSR: C Position */\r
+#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */\r
+\r
+#define xPSR_V_Pos 28U /*!< xPSR: V Position */\r
+#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */\r
+\r
+#define xPSR_Q_Pos 27U /*!< xPSR: Q Position */\r
+#define xPSR_Q_Msk (1UL << xPSR_Q_Pos) /*!< xPSR: Q Mask */\r
+\r
+#define xPSR_IT_Pos 25U /*!< xPSR: IT Position */\r
+#define xPSR_IT_Msk (3UL << xPSR_IT_Pos) /*!< xPSR: IT Mask */\r
+\r
+#define xPSR_T_Pos 24U /*!< xPSR: T Position */\r
+#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */\r
+\r
+#define xPSR_GE_Pos 16U /*!< xPSR: GE Position */\r
+#define xPSR_GE_Msk (0xFUL << xPSR_GE_Pos) /*!< xPSR: GE Mask */\r
+\r
+#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */\r
+#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */\r
+\r
+\r
+/**\r
+ \brief Union type to access the Control Registers (CONTROL).\r
+ */\r
+typedef union\r
+{\r
+ struct\r
+ {\r
+ uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */\r
+ uint32_t SPSEL:1; /*!< bit: 1 Stack-pointer select */\r
+ uint32_t FPCA:1; /*!< bit: 2 Floating-point context active */\r
+ uint32_t SFPA:1; /*!< bit: 3 Secure floating-point active */\r
+ uint32_t _reserved1:28; /*!< bit: 4..31 Reserved */\r
+ } b; /*!< Structure used for bit access */\r
+ uint32_t w; /*!< Type used for word access */\r
+} CONTROL_Type;\r
+\r
+/* CONTROL Register Definitions */\r
+#define CONTROL_SFPA_Pos 3U /*!< CONTROL: SFPA Position */\r
+#define CONTROL_SFPA_Msk (1UL << CONTROL_SFPA_Pos) /*!< CONTROL: SFPA Mask */\r
+\r
+#define CONTROL_FPCA_Pos 2U /*!< CONTROL: FPCA Position */\r
+#define CONTROL_FPCA_Msk (1UL << CONTROL_FPCA_Pos) /*!< CONTROL: FPCA Mask */\r
+\r
+#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */\r
+#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */\r
+\r
+#define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */\r
+#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */\r
+\r
+/*@} end of group CMSIS_CORE */\r
+\r
+\r
+/**\r
+ \ingroup CMSIS_core_register\r
+ \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC)\r
+ \brief Type definitions for the NVIC Registers\r
+ @{\r
+ */\r
+\r
+/**\r
+ \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC).\r
+ */\r
+typedef struct\r
+{\r
+ __IOM uint32_t ISER[16U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */\r
+ uint32_t RESERVED0[16U];\r
+ __IOM uint32_t ICER[16U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */\r
+ uint32_t RSERVED1[16U];\r
+ __IOM uint32_t ISPR[16U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */\r
+ uint32_t RESERVED2[16U];\r
+ __IOM uint32_t ICPR[16U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */\r
+ uint32_t RESERVED3[16U];\r
+ __IOM uint32_t IABR[16U]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */\r
+ uint32_t RESERVED4[16U];\r
+ __IOM uint32_t ITNS[16U]; /*!< Offset: 0x280 (R/W) Interrupt Non-Secure State Register */\r
+ uint32_t RESERVED5[16U];\r
+ __IOM uint8_t IPR[496U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */\r
+ uint32_t RESERVED6[580U];\r
+ __OM uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */\r
+} NVIC_Type;\r
+\r
+/* Software Triggered Interrupt Register Definitions */\r
+#define NVIC_STIR_INTID_Pos 0U /*!< STIR: INTLINESNUM Position */\r
+#define NVIC_STIR_INTID_Msk (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/) /*!< STIR: INTLINESNUM Mask */\r
+\r
+/*@} end of group CMSIS_NVIC */\r
+\r
+\r
+/**\r
+ \ingroup CMSIS_core_register\r
+ \defgroup CMSIS_SCB System Control Block (SCB)\r
+ \brief Type definitions for the System Control Block Registers\r
+ @{\r
+ */\r
+\r
+/**\r
+ \brief Structure type to access the System Control Block (SCB).\r
+ */\r
+typedef struct\r
+{\r
+ __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */\r
+ __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */\r
+ __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */\r
+ __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */\r
+ __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */\r
+ __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */\r
+ __IOM uint8_t SHPR[12U]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */\r
+ __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */\r
+ __IOM uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */\r
+ __IOM uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */\r
+ __IOM uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */\r
+ __IOM uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */\r
+ __IOM uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */\r
+ __IOM uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */\r
+ __IM uint32_t ID_PFR[2U]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */\r
+ __IM uint32_t ID_DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */\r
+ __IM uint32_t ID_ADR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */\r
+ __IM uint32_t ID_MMFR[4U]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */\r
+ __IM uint32_t ID_ISAR[6U]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */\r
+ __IM uint32_t CLIDR; /*!< Offset: 0x078 (R/ ) Cache Level ID register */\r
+ __IM uint32_t CTR; /*!< Offset: 0x07C (R/ ) Cache Type register */\r
+ __IM uint32_t CCSIDR; /*!< Offset: 0x080 (R/ ) Cache Size ID Register */\r
+ __IOM uint32_t CSSELR; /*!< Offset: 0x084 (R/W) Cache Size Selection Register */\r
+ __IOM uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */\r
+ __IOM uint32_t NSACR; /*!< Offset: 0x08C (R/W) Non-Secure Access Control Register */\r
+ uint32_t RESERVED3[92U];\r
+ __OM uint32_t STIR; /*!< Offset: 0x200 ( /W) Software Triggered Interrupt Register */\r
+ uint32_t RESERVED4[15U];\r
+ __IM uint32_t MVFR0; /*!< Offset: 0x240 (R/ ) Media and VFP Feature Register 0 */\r
+ __IM uint32_t MVFR1; /*!< Offset: 0x244 (R/ ) Media and VFP Feature Register 1 */\r
+ __IM uint32_t MVFR2; /*!< Offset: 0x248 (R/ ) Media and VFP Feature Register 2 */\r
+ uint32_t RESERVED5[1U];\r
+ __OM uint32_t ICIALLU; /*!< Offset: 0x250 ( /W) I-Cache Invalidate All to PoU */\r
+ uint32_t RESERVED6[1U];\r
+ __OM uint32_t ICIMVAU; /*!< Offset: 0x258 ( /W) I-Cache Invalidate by MVA to PoU */\r
+ __OM uint32_t DCIMVAC; /*!< Offset: 0x25C ( /W) D-Cache Invalidate by MVA to PoC */\r
+ __OM uint32_t DCISW; /*!< Offset: 0x260 ( /W) D-Cache Invalidate by Set-way */\r
+ __OM uint32_t DCCMVAU; /*!< Offset: 0x264 ( /W) D-Cache Clean by MVA to PoU */\r
+ __OM uint32_t DCCMVAC; /*!< Offset: 0x268 ( /W) D-Cache Clean by MVA to PoC */\r
+ __OM uint32_t DCCSW; /*!< Offset: 0x26C ( /W) D-Cache Clean by Set-way */\r
+ __OM uint32_t DCCIMVAC; /*!< Offset: 0x270 ( /W) D-Cache Clean and Invalidate by MVA to PoC */\r
+ __OM uint32_t DCCISW; /*!< Offset: 0x274 ( /W) D-Cache Clean and Invalidate by Set-way */\r
+ uint32_t RESERVED7[6U];\r
+ __IOM uint32_t ITCMCR; /*!< Offset: 0x290 (R/W) Instruction Tightly-Coupled Memory Control Register */\r
+ __IOM uint32_t DTCMCR; /*!< Offset: 0x294 (R/W) Data Tightly-Coupled Memory Control Registers */\r
+ __IOM uint32_t AHBPCR; /*!< Offset: 0x298 (R/W) AHBP Control Register */\r
+ __IOM uint32_t CACR; /*!< Offset: 0x29C (R/W) L1 Cache Control Register */\r
+ __IOM uint32_t AHBSCR; /*!< Offset: 0x2A0 (R/W) AHB Slave Control Register */\r
+ uint32_t RESERVED8[1U];\r
+ __IOM uint32_t ABFSR; /*!< Offset: 0x2A8 (R/W) Auxiliary Bus Fault Status Register */\r
+} SCB_Type;\r
+\r
+/* SCB CPUID Register Definitions */\r
+#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */\r
+#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */\r
+\r
+#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */\r
+#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */\r
+\r
+#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */\r
+#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */\r
+\r
+#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */\r
+#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */\r
+\r
+#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */\r
+#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */\r
+\r
+/* SCB Interrupt Control State Register Definitions */\r
+#define SCB_ICSR_PENDNMISET_Pos 31U /*!< SCB ICSR: PENDNMISET Position */\r
+#define SCB_ICSR_PENDNMISET_Msk (1UL << SCB_ICSR_PENDNMISET_Pos) /*!< SCB ICSR: PENDNMISET Mask */\r
+\r
+#define SCB_ICSR_NMIPENDSET_Pos SCB_ICSR_PENDNMISET_Pos /*!< SCB ICSR: NMIPENDSET Position, backward compatibility */\r
+#define SCB_ICSR_NMIPENDSET_Msk SCB_ICSR_PENDNMISET_Msk /*!< SCB ICSR: NMIPENDSET Mask, backward compatibility */\r
+\r
+#define SCB_ICSR_PENDNMICLR_Pos 30U /*!< SCB ICSR: PENDNMICLR Position */\r
+#define SCB_ICSR_PENDNMICLR_Msk (1UL << SCB_ICSR_PENDNMICLR_Pos) /*!< SCB ICSR: PENDNMICLR Mask */\r
+\r
+#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */\r
+#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */\r
+\r
+#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */\r
+#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */\r
+\r
+#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */\r
+#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */\r
+\r
+#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */\r
+#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */\r
+\r
+#define SCB_ICSR_STTNS_Pos 24U /*!< SCB ICSR: STTNS Position (Security Extension) */\r
+#define SCB_ICSR_STTNS_Msk (1UL << SCB_ICSR_STTNS_Pos) /*!< SCB ICSR: STTNS Mask (Security Extension) */\r
+\r
+#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */\r
+#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */\r
+\r
+#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */\r
+#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */\r
+\r
+#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */\r
+#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */\r
+\r
+#define SCB_ICSR_RETTOBASE_Pos 11U /*!< SCB ICSR: RETTOBASE Position */\r
+#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */\r
+\r
+#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */\r
+#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */\r
+\r
+/* SCB Vector Table Offset Register Definitions */\r
+#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */\r
+#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */\r
+\r
+/* SCB Application Interrupt and Reset Control Register Definitions */\r
+#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */\r
+#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */\r
+\r
+#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */\r
+#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */\r
+\r
+#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */\r
+#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */\r
+\r
+#define SCB_AIRCR_PRIS_Pos 14U /*!< SCB AIRCR: PRIS Position */\r
+#define SCB_AIRCR_PRIS_Msk (1UL << SCB_AIRCR_PRIS_Pos) /*!< SCB AIRCR: PRIS Mask */\r
+\r
+#define SCB_AIRCR_BFHFNMINS_Pos 13U /*!< SCB AIRCR: BFHFNMINS Position */\r
+#define SCB_AIRCR_BFHFNMINS_Msk (1UL << SCB_AIRCR_BFHFNMINS_Pos) /*!< SCB AIRCR: BFHFNMINS Mask */\r
+\r
+#define SCB_AIRCR_PRIGROUP_Pos 8U /*!< SCB AIRCR: PRIGROUP Position */\r
+#define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */\r
+\r
+#define SCB_AIRCR_SYSRESETREQS_Pos 3U /*!< SCB AIRCR: SYSRESETREQS Position */\r
+#define SCB_AIRCR_SYSRESETREQS_Msk (1UL << SCB_AIRCR_SYSRESETREQS_Pos) /*!< SCB AIRCR: SYSRESETREQS Mask */\r
+\r
+#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */\r
+#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */\r
+\r
+#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */\r
+#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */\r
+\r
+/* SCB System Control Register Definitions */\r
+#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */\r
+#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */\r
+\r
+#define SCB_SCR_SLEEPDEEPS_Pos 3U /*!< SCB SCR: SLEEPDEEPS Position */\r
+#define SCB_SCR_SLEEPDEEPS_Msk (1UL << SCB_SCR_SLEEPDEEPS_Pos) /*!< SCB SCR: SLEEPDEEPS Mask */\r
+\r
+#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */\r
+#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */\r
+\r
+#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */\r
+#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */\r
+\r
+/* SCB Configuration Control Register Definitions */\r
+#define SCB_CCR_BP_Pos 18U /*!< SCB CCR: BP Position */\r
+#define SCB_CCR_BP_Msk (1UL << SCB_CCR_BP_Pos) /*!< SCB CCR: BP Mask */\r
+\r
+#define SCB_CCR_IC_Pos 17U /*!< SCB CCR: IC Position */\r
+#define SCB_CCR_IC_Msk (1UL << SCB_CCR_IC_Pos) /*!< SCB CCR: IC Mask */\r
+\r
+#define SCB_CCR_DC_Pos 16U /*!< SCB CCR: DC Position */\r
+#define SCB_CCR_DC_Msk (1UL << SCB_CCR_DC_Pos) /*!< SCB CCR: DC Mask */\r
+\r
+#define SCB_CCR_STKOFHFNMIGN_Pos 10U /*!< SCB CCR: STKOFHFNMIGN Position */\r
+#define SCB_CCR_STKOFHFNMIGN_Msk (1UL << SCB_CCR_STKOFHFNMIGN_Pos) /*!< SCB CCR: STKOFHFNMIGN Mask */\r
+\r
+#define SCB_CCR_BFHFNMIGN_Pos 8U /*!< SCB CCR: BFHFNMIGN Position */\r
+#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */\r
+\r
+#define SCB_CCR_DIV_0_TRP_Pos 4U /*!< SCB CCR: DIV_0_TRP Position */\r
+#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */\r
+\r
+#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */\r
+#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */\r
+\r
+#define SCB_CCR_USERSETMPEND_Pos 1U /*!< SCB CCR: USERSETMPEND Position */\r
+#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */\r
+\r
+/* SCB System Handler Control and State Register Definitions */\r
+#define SCB_SHCSR_HARDFAULTPENDED_Pos 21U /*!< SCB SHCSR: HARDFAULTPENDED Position */\r
+#define SCB_SHCSR_HARDFAULTPENDED_Msk (1UL << SCB_SHCSR_HARDFAULTPENDED_Pos) /*!< SCB SHCSR: HARDFAULTPENDED Mask */\r
+\r
+#define SCB_SHCSR_SECUREFAULTPENDED_Pos 20U /*!< SCB SHCSR: SECUREFAULTPENDED Position */\r
+#define SCB_SHCSR_SECUREFAULTPENDED_Msk (1UL << SCB_SHCSR_SECUREFAULTPENDED_Pos) /*!< SCB SHCSR: SECUREFAULTPENDED Mask */\r
+\r
+#define SCB_SHCSR_SECUREFAULTENA_Pos 19U /*!< SCB SHCSR: SECUREFAULTENA Position */\r
+#define SCB_SHCSR_SECUREFAULTENA_Msk (1UL << SCB_SHCSR_SECUREFAULTENA_Pos) /*!< SCB SHCSR: SECUREFAULTENA Mask */\r
+\r
+#define SCB_SHCSR_USGFAULTENA_Pos 18U /*!< SCB SHCSR: USGFAULTENA Position */\r
+#define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */\r
+\r
+#define SCB_SHCSR_BUSFAULTENA_Pos 17U /*!< SCB SHCSR: BUSFAULTENA Position */\r
+#define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */\r
+\r
+#define SCB_SHCSR_MEMFAULTENA_Pos 16U /*!< SCB SHCSR: MEMFAULTENA Position */\r
+#define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */\r
+\r
+#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */\r
+#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */\r
+\r
+#define SCB_SHCSR_BUSFAULTPENDED_Pos 14U /*!< SCB SHCSR: BUSFAULTPENDED Position */\r
+#define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */\r
+\r
+#define SCB_SHCSR_MEMFAULTPENDED_Pos 13U /*!< SCB SHCSR: MEMFAULTPENDED Position */\r
+#define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */\r
+\r
+#define SCB_SHCSR_USGFAULTPENDED_Pos 12U /*!< SCB SHCSR: USGFAULTPENDED Position */\r
+#define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */\r
+\r
+#define SCB_SHCSR_SYSTICKACT_Pos 11U /*!< SCB SHCSR: SYSTICKACT Position */\r
+#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */\r
+\r
+#define SCB_SHCSR_PENDSVACT_Pos 10U /*!< SCB SHCSR: PENDSVACT Position */\r
+#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */\r
+\r
+#define SCB_SHCSR_MONITORACT_Pos 8U /*!< SCB SHCSR: MONITORACT Position */\r
+#define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */\r
+\r
+#define SCB_SHCSR_SVCALLACT_Pos 7U /*!< SCB SHCSR: SVCALLACT Position */\r
+#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */\r
+\r
+#define SCB_SHCSR_NMIACT_Pos 5U /*!< SCB SHCSR: NMIACT Position */\r
+#define SCB_SHCSR_NMIACT_Msk (1UL << SCB_SHCSR_NMIACT_Pos) /*!< SCB SHCSR: NMIACT Mask */\r
+\r
+#define SCB_SHCSR_SECUREFAULTACT_Pos 4U /*!< SCB SHCSR: SECUREFAULTACT Position */\r
+#define SCB_SHCSR_SECUREFAULTACT_Msk (1UL << SCB_SHCSR_SECUREFAULTACT_Pos) /*!< SCB SHCSR: SECUREFAULTACT Mask */\r
+\r
+#define SCB_SHCSR_USGFAULTACT_Pos 3U /*!< SCB SHCSR: USGFAULTACT Position */\r
+#define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */\r
+\r
+#define SCB_SHCSR_HARDFAULTACT_Pos 2U /*!< SCB SHCSR: HARDFAULTACT Position */\r
+#define SCB_SHCSR_HARDFAULTACT_Msk (1UL << SCB_SHCSR_HARDFAULTACT_Pos) /*!< SCB SHCSR: HARDFAULTACT Mask */\r
+\r
+#define SCB_SHCSR_BUSFAULTACT_Pos 1U /*!< SCB SHCSR: BUSFAULTACT Position */\r
+#define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */\r
+\r
+#define SCB_SHCSR_MEMFAULTACT_Pos 0U /*!< SCB SHCSR: MEMFAULTACT Position */\r
+#define SCB_SHCSR_MEMFAULTACT_Msk (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/) /*!< SCB SHCSR: MEMFAULTACT Mask */\r
+\r
+/* SCB Configurable Fault Status Register Definitions */\r
+#define SCB_CFSR_USGFAULTSR_Pos 16U /*!< SCB CFSR: Usage Fault Status Register Position */\r
+#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */\r
+\r
+#define SCB_CFSR_BUSFAULTSR_Pos 8U /*!< SCB CFSR: Bus Fault Status Register Position */\r
+#define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */\r
+\r
+#define SCB_CFSR_MEMFAULTSR_Pos 0U /*!< SCB CFSR: Memory Manage Fault Status Register Position */\r
+#define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */\r
+\r
+/* MemManage Fault Status Register (part of SCB Configurable Fault Status Register) */\r
+#define SCB_CFSR_MMARVALID_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 7U) /*!< SCB CFSR (MMFSR): MMARVALID Position */\r
+#define SCB_CFSR_MMARVALID_Msk (1UL << SCB_CFSR_MMARVALID_Pos) /*!< SCB CFSR (MMFSR): MMARVALID Mask */\r
+\r
+#define SCB_CFSR_MLSPERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 5U) /*!< SCB CFSR (MMFSR): MLSPERR Position */\r
+#define SCB_CFSR_MLSPERR_Msk (1UL << SCB_CFSR_MLSPERR_Pos) /*!< SCB CFSR (MMFSR): MLSPERR Mask */\r
+\r
+#define SCB_CFSR_MSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 4U) /*!< SCB CFSR (MMFSR): MSTKERR Position */\r
+#define SCB_CFSR_MSTKERR_Msk (1UL << SCB_CFSR_MSTKERR_Pos) /*!< SCB CFSR (MMFSR): MSTKERR Mask */\r
+\r
+#define SCB_CFSR_MUNSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 3U) /*!< SCB CFSR (MMFSR): MUNSTKERR Position */\r
+#define SCB_CFSR_MUNSTKERR_Msk (1UL << SCB_CFSR_MUNSTKERR_Pos) /*!< SCB CFSR (MMFSR): MUNSTKERR Mask */\r
+\r
+#define SCB_CFSR_DACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 1U) /*!< SCB CFSR (MMFSR): DACCVIOL Position */\r
+#define SCB_CFSR_DACCVIOL_Msk (1UL << SCB_CFSR_DACCVIOL_Pos) /*!< SCB CFSR (MMFSR): DACCVIOL Mask */\r
+\r
+#define SCB_CFSR_IACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 0U) /*!< SCB CFSR (MMFSR): IACCVIOL Position */\r
+#define SCB_CFSR_IACCVIOL_Msk (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/) /*!< SCB CFSR (MMFSR): IACCVIOL Mask */\r
+\r
+/* BusFault Status Register (part of SCB Configurable Fault Status Register) */\r
+#define SCB_CFSR_BFARVALID_Pos (SCB_CFSR_BUSFAULTSR_Pos + 7U) /*!< SCB CFSR (BFSR): BFARVALID Position */\r
+#define SCB_CFSR_BFARVALID_Msk (1UL << SCB_CFSR_BFARVALID_Pos) /*!< SCB CFSR (BFSR): BFARVALID Mask */\r
+\r
+#define SCB_CFSR_LSPERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 5U) /*!< SCB CFSR (BFSR): LSPERR Position */\r
+#define SCB_CFSR_LSPERR_Msk (1UL << SCB_CFSR_LSPERR_Pos) /*!< SCB CFSR (BFSR): LSPERR Mask */\r
+\r
+#define SCB_CFSR_STKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 4U) /*!< SCB CFSR (BFSR): STKERR Position */\r
+#define SCB_CFSR_STKERR_Msk (1UL << SCB_CFSR_STKERR_Pos) /*!< SCB CFSR (BFSR): STKERR Mask */\r
+\r
+#define SCB_CFSR_UNSTKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 3U) /*!< SCB CFSR (BFSR): UNSTKERR Position */\r
+#define SCB_CFSR_UNSTKERR_Msk (1UL << SCB_CFSR_UNSTKERR_Pos) /*!< SCB CFSR (BFSR): UNSTKERR Mask */\r
+\r
+#define SCB_CFSR_IMPRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 2U) /*!< SCB CFSR (BFSR): IMPRECISERR Position */\r
+#define SCB_CFSR_IMPRECISERR_Msk (1UL << SCB_CFSR_IMPRECISERR_Pos) /*!< SCB CFSR (BFSR): IMPRECISERR Mask */\r
+\r
+#define SCB_CFSR_PRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 1U) /*!< SCB CFSR (BFSR): PRECISERR Position */\r
+#define SCB_CFSR_PRECISERR_Msk (1UL << SCB_CFSR_PRECISERR_Pos) /*!< SCB CFSR (BFSR): PRECISERR Mask */\r
+\r
+#define SCB_CFSR_IBUSERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 0U) /*!< SCB CFSR (BFSR): IBUSERR Position */\r
+#define SCB_CFSR_IBUSERR_Msk (1UL << SCB_CFSR_IBUSERR_Pos) /*!< SCB CFSR (BFSR): IBUSERR Mask */\r
+\r
+/* UsageFault Status Register (part of SCB Configurable Fault Status Register) */\r
+#define SCB_CFSR_DIVBYZERO_Pos (SCB_CFSR_USGFAULTSR_Pos + 9U) /*!< SCB CFSR (UFSR): DIVBYZERO Position */\r
+#define SCB_CFSR_DIVBYZERO_Msk (1UL << SCB_CFSR_DIVBYZERO_Pos) /*!< SCB CFSR (UFSR): DIVBYZERO Mask */\r
+\r
+#define SCB_CFSR_UNALIGNED_Pos (SCB_CFSR_USGFAULTSR_Pos + 8U) /*!< SCB CFSR (UFSR): UNALIGNED Position */\r
+#define SCB_CFSR_UNALIGNED_Msk (1UL << SCB_CFSR_UNALIGNED_Pos) /*!< SCB CFSR (UFSR): UNALIGNED Mask */\r
+\r
+#define SCB_CFSR_STKOF_Pos (SCB_CFSR_USGFAULTSR_Pos + 4U) /*!< SCB CFSR (UFSR): STKOF Position */\r
+#define SCB_CFSR_STKOF_Msk (1UL << SCB_CFSR_STKOF_Pos) /*!< SCB CFSR (UFSR): STKOF Mask */\r
+\r
+#define SCB_CFSR_NOCP_Pos (SCB_CFSR_USGFAULTSR_Pos + 3U) /*!< SCB CFSR (UFSR): NOCP Position */\r
+#define SCB_CFSR_NOCP_Msk (1UL << SCB_CFSR_NOCP_Pos) /*!< SCB CFSR (UFSR): NOCP Mask */\r
+\r
+#define SCB_CFSR_INVPC_Pos (SCB_CFSR_USGFAULTSR_Pos + 2U) /*!< SCB CFSR (UFSR): INVPC Position */\r
+#define SCB_CFSR_INVPC_Msk (1UL << SCB_CFSR_INVPC_Pos) /*!< SCB CFSR (UFSR): INVPC Mask */\r
+\r
+#define SCB_CFSR_INVSTATE_Pos (SCB_CFSR_USGFAULTSR_Pos + 1U) /*!< SCB CFSR (UFSR): INVSTATE Position */\r
+#define SCB_CFSR_INVSTATE_Msk (1UL << SCB_CFSR_INVSTATE_Pos) /*!< SCB CFSR (UFSR): INVSTATE Mask */\r
+\r
+#define SCB_CFSR_UNDEFINSTR_Pos (SCB_CFSR_USGFAULTSR_Pos + 0U) /*!< SCB CFSR (UFSR): UNDEFINSTR Position */\r
+#define SCB_CFSR_UNDEFINSTR_Msk (1UL << SCB_CFSR_UNDEFINSTR_Pos) /*!< SCB CFSR (UFSR): UNDEFINSTR Mask */\r
+\r
+/* SCB Hard Fault Status Register Definitions */\r
+#define SCB_HFSR_DEBUGEVT_Pos 31U /*!< SCB HFSR: DEBUGEVT Position */\r
+#define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */\r
+\r
+#define SCB_HFSR_FORCED_Pos 30U /*!< SCB HFSR: FORCED Position */\r
+#define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */\r
+\r
+#define SCB_HFSR_VECTTBL_Pos 1U /*!< SCB HFSR: VECTTBL Position */\r
+#define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */\r
+\r
+/* SCB Debug Fault Status Register Definitions */\r
+#define SCB_DFSR_EXTERNAL_Pos 4U /*!< SCB DFSR: EXTERNAL Position */\r
+#define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */\r
+\r
+#define SCB_DFSR_VCATCH_Pos 3U /*!< SCB DFSR: VCATCH Position */\r
+#define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */\r
+\r
+#define SCB_DFSR_DWTTRAP_Pos 2U /*!< SCB DFSR: DWTTRAP Position */\r
+#define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */\r
+\r
+#define SCB_DFSR_BKPT_Pos 1U /*!< SCB DFSR: BKPT Position */\r
+#define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */\r
+\r
+#define SCB_DFSR_HALTED_Pos 0U /*!< SCB DFSR: HALTED Position */\r
+#define SCB_DFSR_HALTED_Msk (1UL /*<< SCB_DFSR_HALTED_Pos*/) /*!< SCB DFSR: HALTED Mask */\r
+\r
+/* SCB Non-Secure Access Control Register Definitions */\r
+#define SCB_NSACR_CP11_Pos 11U /*!< SCB NSACR: CP11 Position */\r
+#define SCB_NSACR_CP11_Msk (1UL << SCB_NSACR_CP11_Pos) /*!< SCB NSACR: CP11 Mask */\r
+\r
+#define SCB_NSACR_CP10_Pos 10U /*!< SCB NSACR: CP10 Position */\r
+#define SCB_NSACR_CP10_Msk (1UL << SCB_NSACR_CP10_Pos) /*!< SCB NSACR: CP10 Mask */\r
+\r
+#define SCB_NSACR_CPn_Pos 0U /*!< SCB NSACR: CPn Position */\r
+#define SCB_NSACR_CPn_Msk (1UL /*<< SCB_NSACR_CPn_Pos*/) /*!< SCB NSACR: CPn Mask */\r
+\r
+/* SCB Cache Level ID Register Definitions */\r
+#define SCB_CLIDR_LOUU_Pos 27U /*!< SCB CLIDR: LoUU Position */\r
+#define SCB_CLIDR_LOUU_Msk (7UL << SCB_CLIDR_LOUU_Pos) /*!< SCB CLIDR: LoUU Mask */\r
+\r
+#define SCB_CLIDR_LOC_Pos 24U /*!< SCB CLIDR: LoC Position */\r
+#define SCB_CLIDR_LOC_Msk (7UL << SCB_CLIDR_LOC_Pos) /*!< SCB CLIDR: LoC Mask */\r
+\r
+/* SCB Cache Type Register Definitions */\r
+#define SCB_CTR_FORMAT_Pos 29U /*!< SCB CTR: Format Position */\r
+#define SCB_CTR_FORMAT_Msk (7UL << SCB_CTR_FORMAT_Pos) /*!< SCB CTR: Format Mask */\r
+\r
+#define SCB_CTR_CWG_Pos 24U /*!< SCB CTR: CWG Position */\r
+#define SCB_CTR_CWG_Msk (0xFUL << SCB_CTR_CWG_Pos) /*!< SCB CTR: CWG Mask */\r
+\r
+#define SCB_CTR_ERG_Pos 20U /*!< SCB CTR: ERG Position */\r
+#define SCB_CTR_ERG_Msk (0xFUL << SCB_CTR_ERG_Pos) /*!< SCB CTR: ERG Mask */\r
+\r
+#define SCB_CTR_DMINLINE_Pos 16U /*!< SCB CTR: DminLine Position */\r
+#define SCB_CTR_DMINLINE_Msk (0xFUL << SCB_CTR_DMINLINE_Pos) /*!< SCB CTR: DminLine Mask */\r
+\r
+#define SCB_CTR_IMINLINE_Pos 0U /*!< SCB CTR: ImInLine Position */\r
+#define SCB_CTR_IMINLINE_Msk (0xFUL /*<< SCB_CTR_IMINLINE_Pos*/) /*!< SCB CTR: ImInLine Mask */\r
+\r
+/* SCB Cache Size ID Register Definitions */\r
+#define SCB_CCSIDR_WT_Pos 31U /*!< SCB CCSIDR: WT Position */\r
+#define SCB_CCSIDR_WT_Msk (1UL << SCB_CCSIDR_WT_Pos) /*!< SCB CCSIDR: WT Mask */\r
+\r
+#define SCB_CCSIDR_WB_Pos 30U /*!< SCB CCSIDR: WB Position */\r
+#define SCB_CCSIDR_WB_Msk (1UL << SCB_CCSIDR_WB_Pos) /*!< SCB CCSIDR: WB Mask */\r
+\r
+#define SCB_CCSIDR_RA_Pos 29U /*!< SCB CCSIDR: RA Position */\r
+#define SCB_CCSIDR_RA_Msk (1UL << SCB_CCSIDR_RA_Pos) /*!< SCB CCSIDR: RA Mask */\r
+\r
+#define SCB_CCSIDR_WA_Pos 28U /*!< SCB CCSIDR: WA Position */\r
+#define SCB_CCSIDR_WA_Msk (1UL << SCB_CCSIDR_WA_Pos) /*!< SCB CCSIDR: WA Mask */\r
+\r
+#define SCB_CCSIDR_NUMSETS_Pos 13U /*!< SCB CCSIDR: NumSets Position */\r
+#define SCB_CCSIDR_NUMSETS_Msk (0x7FFFUL << SCB_CCSIDR_NUMSETS_Pos) /*!< SCB CCSIDR: NumSets Mask */\r
+\r
+#define SCB_CCSIDR_ASSOCIATIVITY_Pos 3U /*!< SCB CCSIDR: Associativity Position */\r
+#define SCB_CCSIDR_ASSOCIATIVITY_Msk (0x3FFUL << SCB_CCSIDR_ASSOCIATIVITY_Pos) /*!< SCB CCSIDR: Associativity Mask */\r
+\r
+#define SCB_CCSIDR_LINESIZE_Pos 0U /*!< SCB CCSIDR: LineSize Position */\r
+#define SCB_CCSIDR_LINESIZE_Msk (7UL /*<< SCB_CCSIDR_LINESIZE_Pos*/) /*!< SCB CCSIDR: LineSize Mask */\r
+\r
+/* SCB Cache Size Selection Register Definitions */\r
+#define SCB_CSSELR_LEVEL_Pos 1U /*!< SCB CSSELR: Level Position */\r
+#define SCB_CSSELR_LEVEL_Msk (7UL << SCB_CSSELR_LEVEL_Pos) /*!< SCB CSSELR: Level Mask */\r
+\r
+#define SCB_CSSELR_IND_Pos 0U /*!< SCB CSSELR: InD Position */\r
+#define SCB_CSSELR_IND_Msk (1UL /*<< SCB_CSSELR_IND_Pos*/) /*!< SCB CSSELR: InD Mask */\r
+\r
+/* SCB Software Triggered Interrupt Register Definitions */\r
+#define SCB_STIR_INTID_Pos 0U /*!< SCB STIR: INTID Position */\r
+#define SCB_STIR_INTID_Msk (0x1FFUL /*<< SCB_STIR_INTID_Pos*/) /*!< SCB STIR: INTID Mask */\r
+\r
+/* SCB D-Cache Invalidate by Set-way Register Definitions */\r
+#define SCB_DCISW_WAY_Pos 30U /*!< SCB DCISW: Way Position */\r
+#define SCB_DCISW_WAY_Msk (3UL << SCB_DCISW_WAY_Pos) /*!< SCB DCISW: Way Mask */\r
+\r
+#define SCB_DCISW_SET_Pos 5U /*!< SCB DCISW: Set Position */\r
+#define SCB_DCISW_SET_Msk (0x1FFUL << SCB_DCISW_SET_Pos) /*!< SCB DCISW: Set Mask */\r
+\r
+/* SCB D-Cache Clean by Set-way Register Definitions */\r
+#define SCB_DCCSW_WAY_Pos 30U /*!< SCB DCCSW: Way Position */\r
+#define SCB_DCCSW_WAY_Msk (3UL << SCB_DCCSW_WAY_Pos) /*!< SCB DCCSW: Way Mask */\r
+\r
+#define SCB_DCCSW_SET_Pos 5U /*!< SCB DCCSW: Set Position */\r
+#define SCB_DCCSW_SET_Msk (0x1FFUL << SCB_DCCSW_SET_Pos) /*!< SCB DCCSW: Set Mask */\r
+\r
+/* SCB D-Cache Clean and Invalidate by Set-way Register Definitions */\r
+#define SCB_DCCISW_WAY_Pos 30U /*!< SCB DCCISW: Way Position */\r
+#define SCB_DCCISW_WAY_Msk (3UL << SCB_DCCISW_WAY_Pos) /*!< SCB DCCISW: Way Mask */\r
+\r
+#define SCB_DCCISW_SET_Pos 5U /*!< SCB DCCISW: Set Position */\r
+#define SCB_DCCISW_SET_Msk (0x1FFUL << SCB_DCCISW_SET_Pos) /*!< SCB DCCISW: Set Mask */\r
+\r
+/* Instruction Tightly-Coupled Memory Control Register Definitions */\r
+#define SCB_ITCMCR_SZ_Pos 3U /*!< SCB ITCMCR: SZ Position */\r
+#define SCB_ITCMCR_SZ_Msk (0xFUL << SCB_ITCMCR_SZ_Pos) /*!< SCB ITCMCR: SZ Mask */\r
+\r
+#define SCB_ITCMCR_RETEN_Pos 2U /*!< SCB ITCMCR: RETEN Position */\r
+#define SCB_ITCMCR_RETEN_Msk (1UL << SCB_ITCMCR_RETEN_Pos) /*!< SCB ITCMCR: RETEN Mask */\r
+\r
+#define SCB_ITCMCR_RMW_Pos 1U /*!< SCB ITCMCR: RMW Position */\r
+#define SCB_ITCMCR_RMW_Msk (1UL << SCB_ITCMCR_RMW_Pos) /*!< SCB ITCMCR: RMW Mask */\r
+\r
+#define SCB_ITCMCR_EN_Pos 0U /*!< SCB ITCMCR: EN Position */\r
+#define SCB_ITCMCR_EN_Msk (1UL /*<< SCB_ITCMCR_EN_Pos*/) /*!< SCB ITCMCR: EN Mask */\r
+\r
+/* Data Tightly-Coupled Memory Control Register Definitions */\r
+#define SCB_DTCMCR_SZ_Pos 3U /*!< SCB DTCMCR: SZ Position */\r
+#define SCB_DTCMCR_SZ_Msk (0xFUL << SCB_DTCMCR_SZ_Pos) /*!< SCB DTCMCR: SZ Mask */\r
+\r
+#define SCB_DTCMCR_RETEN_Pos 2U /*!< SCB DTCMCR: RETEN Position */\r
+#define SCB_DTCMCR_RETEN_Msk (1UL << SCB_DTCMCR_RETEN_Pos) /*!< SCB DTCMCR: RETEN Mask */\r
+\r
+#define SCB_DTCMCR_RMW_Pos 1U /*!< SCB DTCMCR: RMW Position */\r
+#define SCB_DTCMCR_RMW_Msk (1UL << SCB_DTCMCR_RMW_Pos) /*!< SCB DTCMCR: RMW Mask */\r
+\r
+#define SCB_DTCMCR_EN_Pos 0U /*!< SCB DTCMCR: EN Position */\r
+#define SCB_DTCMCR_EN_Msk (1UL /*<< SCB_DTCMCR_EN_Pos*/) /*!< SCB DTCMCR: EN Mask */\r
+\r
+/* AHBP Control Register Definitions */\r
+#define SCB_AHBPCR_SZ_Pos 1U /*!< SCB AHBPCR: SZ Position */\r
+#define SCB_AHBPCR_SZ_Msk (7UL << SCB_AHBPCR_SZ_Pos) /*!< SCB AHBPCR: SZ Mask */\r
+\r
+#define SCB_AHBPCR_EN_Pos 0U /*!< SCB AHBPCR: EN Position */\r
+#define SCB_AHBPCR_EN_Msk (1UL /*<< SCB_AHBPCR_EN_Pos*/) /*!< SCB AHBPCR: EN Mask */\r
+\r
+/* L1 Cache Control Register Definitions */\r
+#define SCB_CACR_FORCEWT_Pos 2U /*!< SCB CACR: FORCEWT Position */\r
+#define SCB_CACR_FORCEWT_Msk (1UL << SCB_CACR_FORCEWT_Pos) /*!< SCB CACR: FORCEWT Mask */\r
+\r
+#define SCB_CACR_ECCEN_Pos 1U /*!< SCB CACR: ECCEN Position */\r
+#define SCB_CACR_ECCEN_Msk (1UL << SCB_CACR_ECCEN_Pos) /*!< SCB CACR: ECCEN Mask */\r
+\r
+#define SCB_CACR_SIWT_Pos 0U /*!< SCB CACR: SIWT Position */\r
+#define SCB_CACR_SIWT_Msk (1UL /*<< SCB_CACR_SIWT_Pos*/) /*!< SCB CACR: SIWT Mask */\r
+\r
+/* AHBS Control Register Definitions */\r
+#define SCB_AHBSCR_INITCOUNT_Pos 11U /*!< SCB AHBSCR: INITCOUNT Position */\r
+#define SCB_AHBSCR_INITCOUNT_Msk (0x1FUL << SCB_AHBPCR_INITCOUNT_Pos) /*!< SCB AHBSCR: INITCOUNT Mask */\r
+\r
+#define SCB_AHBSCR_TPRI_Pos 2U /*!< SCB AHBSCR: TPRI Position */\r
+#define SCB_AHBSCR_TPRI_Msk (0x1FFUL << SCB_AHBPCR_TPRI_Pos) /*!< SCB AHBSCR: TPRI Mask */\r
+\r
+#define SCB_AHBSCR_CTL_Pos 0U /*!< SCB AHBSCR: CTL Position*/\r
+#define SCB_AHBSCR_CTL_Msk (3UL /*<< SCB_AHBPCR_CTL_Pos*/) /*!< SCB AHBSCR: CTL Mask */\r
+\r
+/* Auxiliary Bus Fault Status Register Definitions */\r
+#define SCB_ABFSR_AXIMTYPE_Pos 8U /*!< SCB ABFSR: AXIMTYPE Position*/\r
+#define SCB_ABFSR_AXIMTYPE_Msk (3UL << SCB_ABFSR_AXIMTYPE_Pos) /*!< SCB ABFSR: AXIMTYPE Mask */\r
+\r
+#define SCB_ABFSR_EPPB_Pos 4U /*!< SCB ABFSR: EPPB Position*/\r
+#define SCB_ABFSR_EPPB_Msk (1UL << SCB_ABFSR_EPPB_Pos) /*!< SCB ABFSR: EPPB Mask */\r
+\r
+#define SCB_ABFSR_AXIM_Pos 3U /*!< SCB ABFSR: AXIM Position*/\r
+#define SCB_ABFSR_AXIM_Msk (1UL << SCB_ABFSR_AXIM_Pos) /*!< SCB ABFSR: AXIM Mask */\r
+\r
+#define SCB_ABFSR_AHBP_Pos 2U /*!< SCB ABFSR: AHBP Position*/\r
+#define SCB_ABFSR_AHBP_Msk (1UL << SCB_ABFSR_AHBP_Pos) /*!< SCB ABFSR: AHBP Mask */\r
+\r
+#define SCB_ABFSR_DTCM_Pos 1U /*!< SCB ABFSR: DTCM Position*/\r
+#define SCB_ABFSR_DTCM_Msk (1UL << SCB_ABFSR_DTCM_Pos) /*!< SCB ABFSR: DTCM Mask */\r
+\r
+#define SCB_ABFSR_ITCM_Pos 0U /*!< SCB ABFSR: ITCM Position*/\r
+#define SCB_ABFSR_ITCM_Msk (1UL /*<< SCB_ABFSR_ITCM_Pos*/) /*!< SCB ABFSR: ITCM Mask */\r
+\r
+/*@} end of group CMSIS_SCB */\r
+\r
+\r
+/**\r
+ \ingroup CMSIS_core_register\r
+ \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB)\r
+ \brief Type definitions for the System Control and ID Register not in the SCB\r
+ @{\r
+ */\r
+\r
+/**\r
+ \brief Structure type to access the System Control and ID Register not in the SCB.\r
+ */\r
+typedef struct\r
+{\r
+ uint32_t RESERVED0[1U];\r
+ __IM uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */\r
+ __IOM uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */\r
+ __IOM uint32_t CPPWR; /*!< Offset: 0x00C (R/W) Coprocessor Power Control Register */\r
+} SCnSCB_Type;\r
+\r
+/* Interrupt Controller Type Register Definitions */\r
+#define SCnSCB_ICTR_INTLINESNUM_Pos 0U /*!< ICTR: INTLINESNUM Position */\r
+#define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/) /*!< ICTR: INTLINESNUM Mask */\r
+\r
+/*@} end of group CMSIS_SCnotSCB */\r
+\r
+\r
+/**\r
+ \ingroup CMSIS_core_register\r
+ \defgroup CMSIS_SysTick System Tick Timer (SysTick)\r
+ \brief Type definitions for the System Timer Registers.\r
+ @{\r
+ */\r
+\r
+/**\r
+ \brief Structure type to access the System Timer (SysTick).\r
+ */\r
+typedef struct\r
+{\r
+ __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */\r
+ __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */\r
+ __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */\r
+ __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */\r
+} SysTick_Type;\r
+\r
+/* SysTick Control / Status Register Definitions */\r
+#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */\r
+#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */\r
+\r
+#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */\r
+#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */\r
+\r
+#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */\r
+#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */\r
+\r
+#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */\r
+#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */\r
+\r
+/* SysTick Reload Register Definitions */\r
+#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */\r
+#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */\r
+\r
+/* SysTick Current Register Definitions */\r
+#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */\r
+#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */\r
+\r
+/* SysTick Calibration Register Definitions */\r
+#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */\r
+#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */\r
+\r
+#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */\r
+#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */\r
+\r
+#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */\r
+#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */\r
+\r
+/*@} end of group CMSIS_SysTick */\r
+\r
+\r
+/**\r
+ \ingroup CMSIS_core_register\r
+ \defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM)\r
+ \brief Type definitions for the Instrumentation Trace Macrocell (ITM)\r
+ @{\r
+ */\r
+\r
+/**\r
+ \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM).\r
+ */\r
+typedef struct\r
+{\r
+ __OM union\r
+ {\r
+ __OM uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */\r
+ __OM uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */\r
+ __OM uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */\r
+ } PORT [32U]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */\r
+ uint32_t RESERVED0[864U];\r
+ __IOM uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */\r
+ uint32_t RESERVED1[15U];\r
+ __IOM uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */\r
+ uint32_t RESERVED2[15U];\r
+ __IOM uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */\r
+ uint32_t RESERVED3[29U];\r
+ __OM uint32_t IWR; /*!< Offset: 0xEF8 ( /W) ITM Integration Write Register */\r
+ __IM uint32_t IRR; /*!< Offset: 0xEFC (R/ ) ITM Integration Read Register */\r
+ __IOM uint32_t IMCR; /*!< Offset: 0xF00 (R/W) ITM Integration Mode Control Register */\r
+ uint32_t RESERVED4[43U];\r
+ __OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */\r
+ __IM uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */\r
+ uint32_t RESERVED5[1U];\r
+ __IM uint32_t DEVARCH; /*!< Offset: 0xFBC (R/ ) ITM Device Architecture Register */\r
+ uint32_t RESERVED6[4U];\r
+ __IM uint32_t PID4; /*!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 */\r
+ __IM uint32_t PID5; /*!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 */\r
+ __IM uint32_t PID6; /*!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 */\r
+ __IM uint32_t PID7; /*!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 */\r
+ __IM uint32_t PID0; /*!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 */\r
+ __IM uint32_t PID1; /*!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 */\r
+ __IM uint32_t PID2; /*!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 */\r
+ __IM uint32_t PID3; /*!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 */\r
+ __IM uint32_t CID0; /*!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 */\r
+ __IM uint32_t CID1; /*!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 */\r
+ __IM uint32_t CID2; /*!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 */\r
+ __IM uint32_t CID3; /*!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 */\r
+} ITM_Type;\r
+\r
+/* ITM Stimulus Port Register Definitions */\r
+#define ITM_STIM_DISABLED_Pos 1U /*!< ITM STIM: DISABLED Position */\r
+#define ITM_STIM_DISABLED_Msk (0x1UL << ITM_STIM_DISABLED_Pos) /*!< ITM STIM: DISABLED Mask */\r
+\r
+#define ITM_STIM_FIFOREADY_Pos 0U /*!< ITM STIM: FIFOREADY Position */\r
+#define ITM_STIM_FIFOREADY_Msk (0x1UL /*<< ITM_STIM_FIFOREADY_Pos*/) /*!< ITM STIM: FIFOREADY Mask */\r
+\r
+/* ITM Trace Privilege Register Definitions */\r
+#define ITM_TPR_PRIVMASK_Pos 0U /*!< ITM TPR: PRIVMASK Position */\r
+#define ITM_TPR_PRIVMASK_Msk (0xFFFFFFFFUL /*<< ITM_TPR_PRIVMASK_Pos*/) /*!< ITM TPR: PRIVMASK Mask */\r
+\r
+/* ITM Trace Control Register Definitions */\r
+#define ITM_TCR_BUSY_Pos 23U /*!< ITM TCR: BUSY Position */\r
+#define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */\r
+\r
+#define ITM_TCR_TRACEBUSID_Pos 16U /*!< ITM TCR: ATBID Position */\r
+#define ITM_TCR_TRACEBUSID_Msk (0x7FUL << ITM_TCR_TRACEBUSID_Pos) /*!< ITM TCR: ATBID Mask */\r
+\r
+#define ITM_TCR_GTSFREQ_Pos 10U /*!< ITM TCR: Global timestamp frequency Position */\r
+#define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */\r
+\r
+#define ITM_TCR_TSPRESCALE_Pos 8U /*!< ITM TCR: TSPRESCALE Position */\r
+#define ITM_TCR_TSPRESCALE_Msk (3UL << ITM_TCR_TSPRESCALE_Pos) /*!< ITM TCR: TSPRESCALE Mask */\r
+\r
+#define ITM_TCR_STALLENA_Pos 5U /*!< ITM TCR: STALLENA Position */\r
+#define ITM_TCR_STALLENA_Msk (1UL << ITM_TCR_STALLENA_Pos) /*!< ITM TCR: STALLENA Mask */\r
+\r
+#define ITM_TCR_SWOENA_Pos 4U /*!< ITM TCR: SWOENA Position */\r
+#define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */\r
+\r
+#define ITM_TCR_DWTENA_Pos 3U /*!< ITM TCR: DWTENA Position */\r
+#define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */\r
+\r
+#define ITM_TCR_SYNCENA_Pos 2U /*!< ITM TCR: SYNCENA Position */\r
+#define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */\r
+\r
+#define ITM_TCR_TSENA_Pos 1U /*!< ITM TCR: TSENA Position */\r
+#define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */\r
+\r
+#define ITM_TCR_ITMENA_Pos 0U /*!< ITM TCR: ITM Enable bit Position */\r
+#define ITM_TCR_ITMENA_Msk (1UL /*<< ITM_TCR_ITMENA_Pos*/) /*!< ITM TCR: ITM Enable bit Mask */\r
+\r
+/* ITM Integration Write Register Definitions */\r
+#define ITM_IWR_ATVALIDM_Pos 0U /*!< ITM IWR: ATVALIDM Position */\r
+#define ITM_IWR_ATVALIDM_Msk (1UL /*<< ITM_IWR_ATVALIDM_Pos*/) /*!< ITM IWR: ATVALIDM Mask */\r
+\r
+/* ITM Integration Read Register Definitions */\r
+#define ITM_IRR_ATREADYM_Pos 0U /*!< ITM IRR: ATREADYM Position */\r
+#define ITM_IRR_ATREADYM_Msk (1UL /*<< ITM_IRR_ATREADYM_Pos*/) /*!< ITM IRR: ATREADYM Mask */\r
+\r
+/* ITM Integration Mode Control Register Definitions */\r
+#define ITM_IMCR_INTEGRATION_Pos 0U /*!< ITM IMCR: INTEGRATION Position */\r
+#define ITM_IMCR_INTEGRATION_Msk (1UL /*<< ITM_IMCR_INTEGRATION_Pos*/) /*!< ITM IMCR: INTEGRATION Mask */\r
+\r
+/* ITM Lock Status Register Definitions */\r
+#define ITM_LSR_ByteAcc_Pos 2U /*!< ITM LSR: ByteAcc Position */\r
+#define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */\r
+\r
+#define ITM_LSR_Access_Pos 1U /*!< ITM LSR: Access Position */\r
+#define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */\r
+\r
+#define ITM_LSR_Present_Pos 0U /*!< ITM LSR: Present Position */\r
+#define ITM_LSR_Present_Msk (1UL /*<< ITM_LSR_Present_Pos*/) /*!< ITM LSR: Present Mask */\r
+\r
+/*@}*/ /* end of group CMSIS_ITM */\r
+\r
+\r
+/**\r
+ \ingroup CMSIS_core_register\r
+ \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT)\r
+ \brief Type definitions for the Data Watchpoint and Trace (DWT)\r
+ @{\r
+ */\r
+\r
+/**\r
+ \brief Structure type to access the Data Watchpoint and Trace Register (DWT).\r
+ */\r
+typedef struct\r
+{\r
+ __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */\r
+ __IOM uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */\r
+ __IOM uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */\r
+ __IOM uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */\r
+ __IOM uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */\r
+ __IOM uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */\r
+ __IOM uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */\r
+ __IM uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */\r
+ __IOM uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */\r
+ uint32_t RESERVED1[1U];\r
+ __IOM uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */\r
+ uint32_t RESERVED2[1U];\r
+ __IOM uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */\r
+ uint32_t RESERVED3[1U];\r
+ __IOM uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */\r
+ uint32_t RESERVED4[1U];\r
+ __IOM uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */\r
+ uint32_t RESERVED5[1U];\r
+ __IOM uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */\r
+ uint32_t RESERVED6[1U];\r
+ __IOM uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */\r
+ uint32_t RESERVED7[1U];\r
+ __IOM uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */\r
+ uint32_t RESERVED8[1U];\r
+ __IOM uint32_t COMP4; /*!< Offset: 0x060 (R/W) Comparator Register 4 */\r
+ uint32_t RESERVED9[1U];\r
+ __IOM uint32_t FUNCTION4; /*!< Offset: 0x068 (R/W) Function Register 4 */\r
+ uint32_t RESERVED10[1U];\r
+ __IOM uint32_t COMP5; /*!< Offset: 0x070 (R/W) Comparator Register 5 */\r
+ uint32_t RESERVED11[1U];\r
+ __IOM uint32_t FUNCTION5; /*!< Offset: 0x078 (R/W) Function Register 5 */\r
+ uint32_t RESERVED12[1U];\r
+ __IOM uint32_t COMP6; /*!< Offset: 0x080 (R/W) Comparator Register 6 */\r
+ uint32_t RESERVED13[1U];\r
+ __IOM uint32_t FUNCTION6; /*!< Offset: 0x088 (R/W) Function Register 6 */\r
+ uint32_t RESERVED14[1U];\r
+ __IOM uint32_t COMP7; /*!< Offset: 0x090 (R/W) Comparator Register 7 */\r
+ uint32_t RESERVED15[1U];\r
+ __IOM uint32_t FUNCTION7; /*!< Offset: 0x098 (R/W) Function Register 7 */\r
+ uint32_t RESERVED16[1U];\r
+ __IOM uint32_t COMP8; /*!< Offset: 0x0A0 (R/W) Comparator Register 8 */\r
+ uint32_t RESERVED17[1U];\r
+ __IOM uint32_t FUNCTION8; /*!< Offset: 0x0A8 (R/W) Function Register 8 */\r
+ uint32_t RESERVED18[1U];\r
+ __IOM uint32_t COMP9; /*!< Offset: 0x0B0 (R/W) Comparator Register 9 */\r
+ uint32_t RESERVED19[1U];\r
+ __IOM uint32_t FUNCTION9; /*!< Offset: 0x0B8 (R/W) Function Register 9 */\r
+ uint32_t RESERVED20[1U];\r
+ __IOM uint32_t COMP10; /*!< Offset: 0x0C0 (R/W) Comparator Register 10 */\r
+ uint32_t RESERVED21[1U];\r
+ __IOM uint32_t FUNCTION10; /*!< Offset: 0x0C8 (R/W) Function Register 10 */\r
+ uint32_t RESERVED22[1U];\r
+ __IOM uint32_t COMP11; /*!< Offset: 0x0D0 (R/W) Comparator Register 11 */\r
+ uint32_t RESERVED23[1U];\r
+ __IOM uint32_t FUNCTION11; /*!< Offset: 0x0D8 (R/W) Function Register 11 */\r
+ uint32_t RESERVED24[1U];\r
+ __IOM uint32_t COMP12; /*!< Offset: 0x0E0 (R/W) Comparator Register 12 */\r
+ uint32_t RESERVED25[1U];\r
+ __IOM uint32_t FUNCTION12; /*!< Offset: 0x0E8 (R/W) Function Register 12 */\r
+ uint32_t RESERVED26[1U];\r
+ __IOM uint32_t COMP13; /*!< Offset: 0x0F0 (R/W) Comparator Register 13 */\r
+ uint32_t RESERVED27[1U];\r
+ __IOM uint32_t FUNCTION13; /*!< Offset: 0x0F8 (R/W) Function Register 13 */\r
+ uint32_t RESERVED28[1U];\r
+ __IOM uint32_t COMP14; /*!< Offset: 0x100 (R/W) Comparator Register 14 */\r
+ uint32_t RESERVED29[1U];\r
+ __IOM uint32_t FUNCTION14; /*!< Offset: 0x108 (R/W) Function Register 14 */\r
+ uint32_t RESERVED30[1U];\r
+ __IOM uint32_t COMP15; /*!< Offset: 0x110 (R/W) Comparator Register 15 */\r
+ uint32_t RESERVED31[1U];\r
+ __IOM uint32_t FUNCTION15; /*!< Offset: 0x118 (R/W) Function Register 15 */\r
+ uint32_t RESERVED32[934U];\r
+ __IM uint32_t LSR; /*!< Offset: 0xFB4 (R ) Lock Status Register */\r
+ uint32_t RESERVED33[1U];\r
+ __IM uint32_t DEVARCH; /*!< Offset: 0xFBC (R/ ) Device Architecture Register */\r
+} DWT_Type;\r
+\r
+/* DWT Control Register Definitions */\r
+#define DWT_CTRL_NUMCOMP_Pos 28U /*!< DWT CTRL: NUMCOMP Position */\r
+#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */\r
+\r
+#define DWT_CTRL_NOTRCPKT_Pos 27U /*!< DWT CTRL: NOTRCPKT Position */\r
+#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */\r
+\r
+#define DWT_CTRL_NOEXTTRIG_Pos 26U /*!< DWT CTRL: NOEXTTRIG Position */\r
+#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */\r
+\r
+#define DWT_CTRL_NOCYCCNT_Pos 25U /*!< DWT CTRL: NOCYCCNT Position */\r
+#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */\r
+\r
+#define DWT_CTRL_NOPRFCNT_Pos 24U /*!< DWT CTRL: NOPRFCNT Position */\r
+#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */\r
+\r
+#define DWT_CTRL_CYCDISS_Pos 23U /*!< DWT CTRL: CYCDISS Position */\r
+#define DWT_CTRL_CYCDISS_Msk (0x1UL << DWT_CTRL_CYCDISS_Pos) /*!< DWT CTRL: CYCDISS Mask */\r
+\r
+#define DWT_CTRL_CYCEVTENA_Pos 22U /*!< DWT CTRL: CYCEVTENA Position */\r
+#define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */\r
+\r
+#define DWT_CTRL_FOLDEVTENA_Pos 21U /*!< DWT CTRL: FOLDEVTENA Position */\r
+#define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */\r
+\r
+#define DWT_CTRL_LSUEVTENA_Pos 20U /*!< DWT CTRL: LSUEVTENA Position */\r
+#define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */\r
+\r
+#define DWT_CTRL_SLEEPEVTENA_Pos 19U /*!< DWT CTRL: SLEEPEVTENA Position */\r
+#define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */\r
+\r
+#define DWT_CTRL_EXCEVTENA_Pos 18U /*!< DWT CTRL: EXCEVTENA Position */\r
+#define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */\r
+\r
+#define DWT_CTRL_CPIEVTENA_Pos 17U /*!< DWT CTRL: CPIEVTENA Position */\r
+#define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */\r
+\r
+#define DWT_CTRL_EXCTRCENA_Pos 16U /*!< DWT CTRL: EXCTRCENA Position */\r
+#define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */\r
+\r
+#define DWT_CTRL_PCSAMPLENA_Pos 12U /*!< DWT CTRL: PCSAMPLENA Position */\r
+#define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */\r
+\r
+#define DWT_CTRL_SYNCTAP_Pos 10U /*!< DWT CTRL: SYNCTAP Position */\r
+#define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */\r
+\r
+#define DWT_CTRL_CYCTAP_Pos 9U /*!< DWT CTRL: CYCTAP Position */\r
+#define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */\r
+\r
+#define DWT_CTRL_POSTINIT_Pos 5U /*!< DWT CTRL: POSTINIT Position */\r
+#define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */\r
+\r
+#define DWT_CTRL_POSTPRESET_Pos 1U /*!< DWT CTRL: POSTPRESET Position */\r
+#define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */\r
+\r
+#define DWT_CTRL_CYCCNTENA_Pos 0U /*!< DWT CTRL: CYCCNTENA Position */\r
+#define DWT_CTRL_CYCCNTENA_Msk (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/) /*!< DWT CTRL: CYCCNTENA Mask */\r
+\r
+/* DWT CPI Count Register Definitions */\r
+#define DWT_CPICNT_CPICNT_Pos 0U /*!< DWT CPICNT: CPICNT Position */\r
+#define DWT_CPICNT_CPICNT_Msk (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/) /*!< DWT CPICNT: CPICNT Mask */\r
+\r
+/* DWT Exception Overhead Count Register Definitions */\r
+#define DWT_EXCCNT_EXCCNT_Pos 0U /*!< DWT EXCCNT: EXCCNT Position */\r
+#define DWT_EXCCNT_EXCCNT_Msk (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/) /*!< DWT EXCCNT: EXCCNT Mask */\r
+\r
+/* DWT Sleep Count Register Definitions */\r
+#define DWT_SLEEPCNT_SLEEPCNT_Pos 0U /*!< DWT SLEEPCNT: SLEEPCNT Position */\r
+#define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/) /*!< DWT SLEEPCNT: SLEEPCNT Mask */\r
+\r
+/* DWT LSU Count Register Definitions */\r
+#define DWT_LSUCNT_LSUCNT_Pos 0U /*!< DWT LSUCNT: LSUCNT Position */\r
+#define DWT_LSUCNT_LSUCNT_Msk (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/) /*!< DWT LSUCNT: LSUCNT Mask */\r
+\r
+/* DWT Folded-instruction Count Register Definitions */\r
+#define DWT_FOLDCNT_FOLDCNT_Pos 0U /*!< DWT FOLDCNT: FOLDCNT Position */\r
+#define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/) /*!< DWT FOLDCNT: FOLDCNT Mask */\r
+\r
+/* DWT Comparator Function Register Definitions */\r
+#define DWT_FUNCTION_ID_Pos 27U /*!< DWT FUNCTION: ID Position */\r
+#define DWT_FUNCTION_ID_Msk (0x1FUL << DWT_FUNCTION_ID_Pos) /*!< DWT FUNCTION: ID Mask */\r
+\r
+#define DWT_FUNCTION_MATCHED_Pos 24U /*!< DWT FUNCTION: MATCHED Position */\r
+#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */\r
+\r
+#define DWT_FUNCTION_DATAVSIZE_Pos 10U /*!< DWT FUNCTION: DATAVSIZE Position */\r
+#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */\r
+\r
+#define DWT_FUNCTION_ACTION_Pos 4U /*!< DWT FUNCTION: ACTION Position */\r
+#define DWT_FUNCTION_ACTION_Msk (0x1UL << DWT_FUNCTION_ACTION_Pos) /*!< DWT FUNCTION: ACTION Mask */\r
+\r
+#define DWT_FUNCTION_MATCH_Pos 0U /*!< DWT FUNCTION: MATCH Position */\r
+#define DWT_FUNCTION_MATCH_Msk (0xFUL /*<< DWT_FUNCTION_MATCH_Pos*/) /*!< DWT FUNCTION: MATCH Mask */\r
+\r
+/*@}*/ /* end of group CMSIS_DWT */\r
+\r
+\r
+/**\r
+ \ingroup CMSIS_core_register\r
+ \defgroup CMSIS_TPI Trace Port Interface (TPI)\r
+ \brief Type definitions for the Trace Port Interface (TPI)\r
+ @{\r
+ */\r
+\r
+/**\r
+ \brief Structure type to access the Trace Port Interface Register (TPI).\r
+ */\r
+typedef struct\r
+{\r
+ __IM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */\r
+ __IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */\r
+ uint32_t RESERVED0[2U];\r
+ __IOM uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */\r
+ uint32_t RESERVED1[55U];\r
+ __IOM uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */\r
+ uint32_t RESERVED2[131U];\r
+ __IM uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */\r
+ __IOM uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */\r
+ __IOM uint32_t PSCR; /*!< Offset: 0x308 (R/W) Periodic Synchronization Control Register */\r
+ uint32_t RESERVED3[759U];\r
+ __IM uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER Register */\r
+ __IM uint32_t ITFTTD0; /*!< Offset: 0xEEC (R/ ) Integration Test FIFO Test Data 0 Register */\r
+ __IOM uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/W) Integration Test ATB Control Register 2 */\r
+ uint32_t RESERVED4[1U];\r
+ __IM uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) Integration Test ATB Control Register 0 */\r
+ __IM uint32_t ITFTTD1; /*!< Offset: 0xEFC (R/ ) Integration Test FIFO Test Data 1 Register */\r
+ __IOM uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */\r
+ uint32_t RESERVED5[39U];\r
+ __IOM uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */\r
+ __IOM uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */\r
+ uint32_t RESERVED7[8U];\r
+ __IM uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) Device Configuration Register */\r
+ __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) Device Type Identifier Register */\r
+} TPI_Type;\r
+\r
+/* TPI Asynchronous Clock Prescaler Register Definitions */\r
+#define TPI_ACPR_PRESCALER_Pos 0U /*!< TPI ACPR: PRESCALER Position */\r
+#define TPI_ACPR_PRESCALER_Msk (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/) /*!< TPI ACPR: PRESCALER Mask */\r
+\r
+/* TPI Selected Pin Protocol Register Definitions */\r
+#define TPI_SPPR_TXMODE_Pos 0U /*!< TPI SPPR: TXMODE Position */\r
+#define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) /*!< TPI SPPR: TXMODE Mask */\r
+\r
+/* TPI Formatter and Flush Status Register Definitions */\r
+#define TPI_FFSR_FtNonStop_Pos 3U /*!< TPI FFSR: FtNonStop Position */\r
+#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */\r
+\r
+#define TPI_FFSR_TCPresent_Pos 2U /*!< TPI FFSR: TCPresent Position */\r
+#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */\r
+\r
+#define TPI_FFSR_FtStopped_Pos 1U /*!< TPI FFSR: FtStopped Position */\r
+#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */\r
+\r
+#define TPI_FFSR_FlInProg_Pos 0U /*!< TPI FFSR: FlInProg Position */\r
+#define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) /*!< TPI FFSR: FlInProg Mask */\r
+\r
+/* TPI Formatter and Flush Control Register Definitions */\r
+#define TPI_FFCR_TrigIn_Pos 8U /*!< TPI FFCR: TrigIn Position */\r
+#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */\r
+\r
+#define TPI_FFCR_FOnMan_Pos 6U /*!< TPI FFCR: FOnMan Position */\r
+#define TPI_FFCR_FOnMan_Msk (0x1UL << TPI_FFCR_FOnMan_Pos) /*!< TPI FFCR: FOnMan Mask */\r
+\r
+#define TPI_FFCR_EnFCont_Pos 1U /*!< TPI FFCR: EnFCont Position */\r
+#define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */\r
+\r
+/* TPI TRIGGER Register Definitions */\r
+#define TPI_TRIGGER_TRIGGER_Pos 0U /*!< TPI TRIGGER: TRIGGER Position */\r
+#define TPI_TRIGGER_TRIGGER_Msk (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/) /*!< TPI TRIGGER: TRIGGER Mask */\r
+\r
+/* TPI Integration Test FIFO Test Data 0 Register Definitions */\r
+#define TPI_ITFTTD0_ATB_IF2_ATVALID_Pos 29U /*!< TPI ITFTTD0: ATB Interface 2 ATVALIDPosition */\r
+#define TPI_ITFTTD0_ATB_IF2_ATVALID_Msk (0x3UL << TPI_ITFTTD0_ATB_IF2_ATVALID_Pos) /*!< TPI ITFTTD0: ATB Interface 2 ATVALID Mask */\r
+\r
+#define TPI_ITFTTD0_ATB_IF2_bytecount_Pos 27U /*!< TPI ITFTTD0: ATB Interface 2 byte count Position */\r
+#define TPI_ITFTTD0_ATB_IF2_bytecount_Msk (0x3UL << TPI_ITFTTD0_ATB_IF2_bytecount_Pos) /*!< TPI ITFTTD0: ATB Interface 2 byte count Mask */\r
+\r
+#define TPI_ITFTTD0_ATB_IF1_ATVALID_Pos 26U /*!< TPI ITFTTD0: ATB Interface 1 ATVALID Position */\r
+#define TPI_ITFTTD0_ATB_IF1_ATVALID_Msk (0x3UL << TPI_ITFTTD0_ATB_IF1_ATVALID_Pos) /*!< TPI ITFTTD0: ATB Interface 1 ATVALID Mask */\r
+\r
+#define TPI_ITFTTD0_ATB_IF1_bytecount_Pos 24U /*!< TPI ITFTTD0: ATB Interface 1 byte count Position */\r
+#define TPI_ITFTTD0_ATB_IF1_bytecount_Msk (0x3UL << TPI_ITFTTD0_ATB_IF1_bytecount_Pos) /*!< TPI ITFTTD0: ATB Interface 1 byte countt Mask */\r
+\r
+#define TPI_ITFTTD0_ATB_IF1_data2_Pos 16U /*!< TPI ITFTTD0: ATB Interface 1 data2 Position */\r
+#define TPI_ITFTTD0_ATB_IF1_data2_Msk (0xFFUL << TPI_ITFTTD0_ATB_IF1_data1_Pos) /*!< TPI ITFTTD0: ATB Interface 1 data2 Mask */\r
+\r
+#define TPI_ITFTTD0_ATB_IF1_data1_Pos 8U /*!< TPI ITFTTD0: ATB Interface 1 data1 Position */\r
+#define TPI_ITFTTD0_ATB_IF1_data1_Msk (0xFFUL << TPI_ITFTTD0_ATB_IF1_data1_Pos) /*!< TPI ITFTTD0: ATB Interface 1 data1 Mask */\r
+\r
+#define TPI_ITFTTD0_ATB_IF1_data0_Pos 0U /*!< TPI ITFTTD0: ATB Interface 1 data0 Position */\r
+#define TPI_ITFTTD0_ATB_IF1_data0_Msk (0xFFUL /*<< TPI_ITFTTD0_ATB_IF1_data0_Pos*/) /*!< TPI ITFTTD0: ATB Interface 1 data0 Mask */\r
+\r
+/* TPI Integration Test ATB Control Register 2 Register Definitions */\r
+#define TPI_ITATBCTR2_AFVALID2S_Pos 1U /*!< TPI ITATBCTR2: AFVALID2S Position */\r
+#define TPI_ITATBCTR2_AFVALID2S_Msk (0x1UL << TPI_ITATBCTR2_AFVALID2S_Pos) /*!< TPI ITATBCTR2: AFVALID2SS Mask */\r
+\r
+#define TPI_ITATBCTR2_AFVALID1S_Pos 1U /*!< TPI ITATBCTR2: AFVALID1S Position */\r
+#define TPI_ITATBCTR2_AFVALID1S_Msk (0x1UL << TPI_ITATBCTR2_AFVALID1S_Pos) /*!< TPI ITATBCTR2: AFVALID1SS Mask */\r
+\r
+#define TPI_ITATBCTR2_ATREADY2S_Pos 0U /*!< TPI ITATBCTR2: ATREADY2S Position */\r
+#define TPI_ITATBCTR2_ATREADY2S_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY2S_Pos*/) /*!< TPI ITATBCTR2: ATREADY2S Mask */\r
+\r
+#define TPI_ITATBCTR2_ATREADY1S_Pos 0U /*!< TPI ITATBCTR2: ATREADY1S Position */\r
+#define TPI_ITATBCTR2_ATREADY1S_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY1S_Pos*/) /*!< TPI ITATBCTR2: ATREADY1S Mask */\r
+\r
+/* TPI Integration Test FIFO Test Data 1 Register Definitions */\r
+#define TPI_ITFTTD1_ATB_IF2_ATVALID_Pos 29U /*!< TPI ITFTTD1: ATB Interface 2 ATVALID Position */\r
+#define TPI_ITFTTD1_ATB_IF2_ATVALID_Msk (0x3UL << TPI_ITFTTD1_ATB_IF2_ATVALID_Pos) /*!< TPI ITFTTD1: ATB Interface 2 ATVALID Mask */\r
+\r
+#define TPI_ITFTTD1_ATB_IF2_bytecount_Pos 27U /*!< TPI ITFTTD1: ATB Interface 2 byte count Position */\r
+#define TPI_ITFTTD1_ATB_IF2_bytecount_Msk (0x3UL << TPI_ITFTTD1_ATB_IF2_bytecount_Pos) /*!< TPI ITFTTD1: ATB Interface 2 byte count Mask */\r
+\r
+#define TPI_ITFTTD1_ATB_IF1_ATVALID_Pos 26U /*!< TPI ITFTTD1: ATB Interface 1 ATVALID Position */\r
+#define TPI_ITFTTD1_ATB_IF1_ATVALID_Msk (0x3UL << TPI_ITFTTD1_ATB_IF1_ATVALID_Pos) /*!< TPI ITFTTD1: ATB Interface 1 ATVALID Mask */\r
+\r
+#define TPI_ITFTTD1_ATB_IF1_bytecount_Pos 24U /*!< TPI ITFTTD1: ATB Interface 1 byte count Position */\r
+#define TPI_ITFTTD1_ATB_IF1_bytecount_Msk (0x3UL << TPI_ITFTTD1_ATB_IF1_bytecount_Pos) /*!< TPI ITFTTD1: ATB Interface 1 byte countt Mask */\r
+\r
+#define TPI_ITFTTD1_ATB_IF2_data2_Pos 16U /*!< TPI ITFTTD1: ATB Interface 2 data2 Position */\r
+#define TPI_ITFTTD1_ATB_IF2_data2_Msk (0xFFUL << TPI_ITFTTD1_ATB_IF2_data1_Pos) /*!< TPI ITFTTD1: ATB Interface 2 data2 Mask */\r
+\r
+#define TPI_ITFTTD1_ATB_IF2_data1_Pos 8U /*!< TPI ITFTTD1: ATB Interface 2 data1 Position */\r
+#define TPI_ITFTTD1_ATB_IF2_data1_Msk (0xFFUL << TPI_ITFTTD1_ATB_IF2_data1_Pos) /*!< TPI ITFTTD1: ATB Interface 2 data1 Mask */\r
+\r
+#define TPI_ITFTTD1_ATB_IF2_data0_Pos 0U /*!< TPI ITFTTD1: ATB Interface 2 data0 Position */\r
+#define TPI_ITFTTD1_ATB_IF2_data0_Msk (0xFFUL /*<< TPI_ITFTTD1_ATB_IF2_data0_Pos*/) /*!< TPI ITFTTD1: ATB Interface 2 data0 Mask */\r
+\r
+/* TPI Integration Test ATB Control Register 0 Definitions */\r
+#define TPI_ITATBCTR0_AFVALID2S_Pos 1U /*!< TPI ITATBCTR0: AFVALID2S Position */\r
+#define TPI_ITATBCTR0_AFVALID2S_Msk (0x1UL << TPI_ITATBCTR0_AFVALID2S_Pos) /*!< TPI ITATBCTR0: AFVALID2SS Mask */\r
+\r
+#define TPI_ITATBCTR0_AFVALID1S_Pos 1U /*!< TPI ITATBCTR0: AFVALID1S Position */\r
+#define TPI_ITATBCTR0_AFVALID1S_Msk (0x1UL << TPI_ITATBCTR0_AFVALID1S_Pos) /*!< TPI ITATBCTR0: AFVALID1SS Mask */\r
+\r
+#define TPI_ITATBCTR0_ATREADY2S_Pos 0U /*!< TPI ITATBCTR0: ATREADY2S Position */\r
+#define TPI_ITATBCTR0_ATREADY2S_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY2S_Pos*/) /*!< TPI ITATBCTR0: ATREADY2S Mask */\r
+\r
+#define TPI_ITATBCTR0_ATREADY1S_Pos 0U /*!< TPI ITATBCTR0: ATREADY1S Position */\r
+#define TPI_ITATBCTR0_ATREADY1S_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY1S_Pos*/) /*!< TPI ITATBCTR0: ATREADY1S Mask */\r
+\r
+/* TPI Integration Mode Control Register Definitions */\r
+#define TPI_ITCTRL_Mode_Pos 0U /*!< TPI ITCTRL: Mode Position */\r
+#define TPI_ITCTRL_Mode_Msk (0x3UL /*<< TPI_ITCTRL_Mode_Pos*/) /*!< TPI ITCTRL: Mode Mask */\r
+\r
+/* TPI DEVID Register Definitions */\r
+#define TPI_DEVID_NRZVALID_Pos 11U /*!< TPI DEVID: NRZVALID Position */\r
+#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */\r
+\r
+#define TPI_DEVID_MANCVALID_Pos 10U /*!< TPI DEVID: MANCVALID Position */\r
+#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */\r
+\r
+#define TPI_DEVID_PTINVALID_Pos 9U /*!< TPI DEVID: PTINVALID Position */\r
+#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */\r
+\r
+#define TPI_DEVID_FIFOSZ_Pos 6U /*!< TPI DEVID: FIFOSZ Position */\r
+#define TPI_DEVID_FIFOSZ_Msk (0x7UL << TPI_DEVID_FIFOSZ_Pos) /*!< TPI DEVID: FIFOSZ Mask */\r
+\r
+#define TPI_DEVID_NrTraceInput_Pos 0U /*!< TPI DEVID: NrTraceInput Position */\r
+#define TPI_DEVID_NrTraceInput_Msk (0x3FUL /*<< TPI_DEVID_NrTraceInput_Pos*/) /*!< TPI DEVID: NrTraceInput Mask */\r
+\r
+/* TPI DEVTYPE Register Definitions */\r
+#define TPI_DEVTYPE_SubType_Pos 4U /*!< TPI DEVTYPE: SubType Position */\r
+#define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */\r
+\r
+#define TPI_DEVTYPE_MajorType_Pos 0U /*!< TPI DEVTYPE: MajorType Position */\r
+#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */\r
+\r
+/*@}*/ /* end of group CMSIS_TPI */\r
+\r
+\r
+#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)\r
+/**\r
+ \ingroup CMSIS_core_register\r
+ \defgroup CMSIS_MPU Memory Protection Unit (MPU)\r
+ \brief Type definitions for the Memory Protection Unit (MPU)\r
+ @{\r
+ */\r
+\r
+/**\r
+ \brief Structure type to access the Memory Protection Unit (MPU).\r
+ */\r
+typedef struct\r
+{\r
+ __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */\r
+ __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */\r
+ __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region Number Register */\r
+ __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */\r
+ __IOM uint32_t RLAR; /*!< Offset: 0x010 (R/W) MPU Region Limit Address Register */\r
+ __IOM uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Region Base Address Register Alias 1 */\r
+ __IOM uint32_t RLAR_A1; /*!< Offset: 0x018 (R/W) MPU Region Limit Address Register Alias 1 */\r
+ __IOM uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Region Base Address Register Alias 2 */\r
+ __IOM uint32_t RLAR_A2; /*!< Offset: 0x020 (R/W) MPU Region Limit Address Register Alias 2 */\r
+ __IOM uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Region Base Address Register Alias 3 */\r
+ __IOM uint32_t RLAR_A3; /*!< Offset: 0x028 (R/W) MPU Region Limit Address Register Alias 3 */\r
+ uint32_t RESERVED0[1];\r
+ union {\r
+ __IOM uint32_t MAIR[2];\r
+ struct {\r
+ __IOM uint32_t MAIR0; /*!< Offset: 0x030 (R/W) MPU Memory Attribute Indirection Register 0 */\r
+ __IOM uint32_t MAIR1; /*!< Offset: 0x034 (R/W) MPU Memory Attribute Indirection Register 1 */\r
+ };\r
+ };\r
+} MPU_Type;\r
+\r
+#define MPU_TYPE_RALIASES 4U\r
+\r
+/* MPU Type Register Definitions */\r
+#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */\r
+#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */\r
+\r
+#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */\r
+#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */\r
+\r
+#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */\r
+#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */\r
+\r
+/* MPU Control Register Definitions */\r
+#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */\r
+#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */\r
+\r
+#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */\r
+#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */\r
+\r
+#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */\r
+#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */\r
+\r
+/* MPU Region Number Register Definitions */\r
+#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */\r
+#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */\r
+\r
+/* MPU Region Base Address Register Definitions */\r
+#define MPU_RBAR_BASE_Pos 5U /*!< MPU RBAR: BASE Position */\r
+#define MPU_RBAR_BASE_Msk (0x7FFFFFFUL << MPU_RBAR_BASE_Pos) /*!< MPU RBAR: BASE Mask */\r
+\r
+#define MPU_RBAR_SH_Pos 3U /*!< MPU RBAR: SH Position */\r
+#define MPU_RBAR_SH_Msk (0x3UL << MPU_RBAR_SH_Pos) /*!< MPU RBAR: SH Mask */\r
+\r
+#define MPU_RBAR_AP_Pos 1U /*!< MPU RBAR: AP Position */\r
+#define MPU_RBAR_AP_Msk (0x3UL << MPU_RBAR_AP_Pos) /*!< MPU RBAR: AP Mask */\r
+\r
+#define MPU_RBAR_XN_Pos 0U /*!< MPU RBAR: XN Position */\r
+#define MPU_RBAR_XN_Msk (01UL /*<< MPU_RBAR_XN_Pos*/) /*!< MPU RBAR: XN Mask */\r
+\r
+/* MPU Region Limit Address Register Definitions */\r
+#define MPU_RLAR_LIMIT_Pos 5U /*!< MPU RLAR: LIMIT Position */\r
+#define MPU_RLAR_LIMIT_Msk (0x7FFFFFFUL << MPU_RLAR_LIMIT_Pos) /*!< MPU RLAR: LIMIT Mask */\r
+\r
+#define MPU_RLAR_AttrIndx_Pos 1U /*!< MPU RLAR: AttrIndx Position */\r
+#define MPU_RLAR_AttrIndx_Msk (0x7UL << MPU_RLAR_AttrIndx_Pos) /*!< MPU RLAR: AttrIndx Mask */\r
+\r
+#define MPU_RLAR_EN_Pos 0U /*!< MPU RLAR: Region enable bit Position */\r
+#define MPU_RLAR_EN_Msk (1UL /*<< MPU_RLAR_EN_Pos*/) /*!< MPU RLAR: Region enable bit Disable Mask */\r
+\r
+/* MPU Memory Attribute Indirection Register 0 Definitions */\r
+#define MPU_MAIR0_Attr3_Pos 24U /*!< MPU MAIR0: Attr3 Position */\r
+#define MPU_MAIR0_Attr3_Msk (0xFFUL << MPU_MAIR0_Attr3_Pos) /*!< MPU MAIR0: Attr3 Mask */\r
+\r
+#define MPU_MAIR0_Attr2_Pos 16U /*!< MPU MAIR0: Attr2 Position */\r
+#define MPU_MAIR0_Attr2_Msk (0xFFUL << MPU_MAIR0_Attr2_Pos) /*!< MPU MAIR0: Attr2 Mask */\r
+\r
+#define MPU_MAIR0_Attr1_Pos 8U /*!< MPU MAIR0: Attr1 Position */\r
+#define MPU_MAIR0_Attr1_Msk (0xFFUL << MPU_MAIR0_Attr1_Pos) /*!< MPU MAIR0: Attr1 Mask */\r
+\r
+#define MPU_MAIR0_Attr0_Pos 0U /*!< MPU MAIR0: Attr0 Position */\r
+#define MPU_MAIR0_Attr0_Msk (0xFFUL /*<< MPU_MAIR0_Attr0_Pos*/) /*!< MPU MAIR0: Attr0 Mask */\r
+\r
+/* MPU Memory Attribute Indirection Register 1 Definitions */\r
+#define MPU_MAIR1_Attr7_Pos 24U /*!< MPU MAIR1: Attr7 Position */\r
+#define MPU_MAIR1_Attr7_Msk (0xFFUL << MPU_MAIR1_Attr7_Pos) /*!< MPU MAIR1: Attr7 Mask */\r
+\r
+#define MPU_MAIR1_Attr6_Pos 16U /*!< MPU MAIR1: Attr6 Position */\r
+#define MPU_MAIR1_Attr6_Msk (0xFFUL << MPU_MAIR1_Attr6_Pos) /*!< MPU MAIR1: Attr6 Mask */\r
+\r
+#define MPU_MAIR1_Attr5_Pos 8U /*!< MPU MAIR1: Attr5 Position */\r
+#define MPU_MAIR1_Attr5_Msk (0xFFUL << MPU_MAIR1_Attr5_Pos) /*!< MPU MAIR1: Attr5 Mask */\r
+\r
+#define MPU_MAIR1_Attr4_Pos 0U /*!< MPU MAIR1: Attr4 Position */\r
+#define MPU_MAIR1_Attr4_Msk (0xFFUL /*<< MPU_MAIR1_Attr4_Pos*/) /*!< MPU MAIR1: Attr4 Mask */\r
+\r
+/*@} end of group CMSIS_MPU */\r
+#endif\r
+\r
+\r
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)\r
+/**\r
+ \ingroup CMSIS_core_register\r
+ \defgroup CMSIS_SAU Security Attribution Unit (SAU)\r
+ \brief Type definitions for the Security Attribution Unit (SAU)\r
+ @{\r
+ */\r
+\r
+/**\r
+ \brief Structure type to access the Security Attribution Unit (SAU).\r
+ */\r
+typedef struct\r
+{\r
+ __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SAU Control Register */\r
+ __IM uint32_t TYPE; /*!< Offset: 0x004 (R/ ) SAU Type Register */\r
+#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U)\r
+ __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) SAU Region Number Register */\r
+ __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) SAU Region Base Address Register */\r
+ __IOM uint32_t RLAR; /*!< Offset: 0x010 (R/W) SAU Region Limit Address Register */\r
+#else\r
+ uint32_t RESERVED0[3];\r
+#endif\r
+ __IOM uint32_t SFSR; /*!< Offset: 0x014 (R/W) Secure Fault Status Register */\r
+ __IOM uint32_t SFAR; /*!< Offset: 0x018 (R/W) Secure Fault Address Register */\r
+} SAU_Type;\r
+\r
+/* SAU Control Register Definitions */\r
+#define SAU_CTRL_ALLNS_Pos 1U /*!< SAU CTRL: ALLNS Position */\r
+#define SAU_CTRL_ALLNS_Msk (1UL << SAU_CTRL_ALLNS_Pos) /*!< SAU CTRL: ALLNS Mask */\r
+\r
+#define SAU_CTRL_ENABLE_Pos 0U /*!< SAU CTRL: ENABLE Position */\r
+#define SAU_CTRL_ENABLE_Msk (1UL /*<< SAU_CTRL_ENABLE_Pos*/) /*!< SAU CTRL: ENABLE Mask */\r
+\r
+/* SAU Type Register Definitions */\r
+#define SAU_TYPE_SREGION_Pos 0U /*!< SAU TYPE: SREGION Position */\r
+#define SAU_TYPE_SREGION_Msk (0xFFUL /*<< SAU_TYPE_SREGION_Pos*/) /*!< SAU TYPE: SREGION Mask */\r
+\r
+#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U)\r
+/* SAU Region Number Register Definitions */\r
+#define SAU_RNR_REGION_Pos 0U /*!< SAU RNR: REGION Position */\r
+#define SAU_RNR_REGION_Msk (0xFFUL /*<< SAU_RNR_REGION_Pos*/) /*!< SAU RNR: REGION Mask */\r
+\r
+/* SAU Region Base Address Register Definitions */\r
+#define SAU_RBAR_BADDR_Pos 5U /*!< SAU RBAR: BADDR Position */\r
+#define SAU_RBAR_BADDR_Msk (0x7FFFFFFUL << SAU_RBAR_BADDR_Pos) /*!< SAU RBAR: BADDR Mask */\r
+\r
+/* SAU Region Limit Address Register Definitions */\r
+#define SAU_RLAR_LADDR_Pos 5U /*!< SAU RLAR: LADDR Position */\r
+#define SAU_RLAR_LADDR_Msk (0x7FFFFFFUL << SAU_RLAR_LADDR_Pos) /*!< SAU RLAR: LADDR Mask */\r
+\r
+#define SAU_RLAR_NSC_Pos 1U /*!< SAU RLAR: NSC Position */\r
+#define SAU_RLAR_NSC_Msk (1UL << SAU_RLAR_NSC_Pos) /*!< SAU RLAR: NSC Mask */\r
+\r
+#define SAU_RLAR_ENABLE_Pos 0U /*!< SAU RLAR: ENABLE Position */\r
+#define SAU_RLAR_ENABLE_Msk (1UL /*<< SAU_RLAR_ENABLE_Pos*/) /*!< SAU RLAR: ENABLE Mask */\r
+\r
+#endif /* defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) */\r
+\r
+/* Secure Fault Status Register Definitions */\r
+#define SAU_SFSR_LSERR_Pos 7U /*!< SAU SFSR: LSERR Position */\r
+#define SAU_SFSR_LSERR_Msk (1UL << SAU_SFSR_LSERR_Pos) /*!< SAU SFSR: LSERR Mask */\r
+\r
+#define SAU_SFSR_SFARVALID_Pos 6U /*!< SAU SFSR: SFARVALID Position */\r
+#define SAU_SFSR_SFARVALID_Msk (1UL << SAU_SFSR_SFARVALID_Pos) /*!< SAU SFSR: SFARVALID Mask */\r
+\r
+#define SAU_SFSR_LSPERR_Pos 5U /*!< SAU SFSR: LSPERR Position */\r
+#define SAU_SFSR_LSPERR_Msk (1UL << SAU_SFSR_LSPERR_Pos) /*!< SAU SFSR: LSPERR Mask */\r
+\r
+#define SAU_SFSR_INVTRAN_Pos 4U /*!< SAU SFSR: INVTRAN Position */\r
+#define SAU_SFSR_INVTRAN_Msk (1UL << SAU_SFSR_INVTRAN_Pos) /*!< SAU SFSR: INVTRAN Mask */\r
+\r
+#define SAU_SFSR_AUVIOL_Pos 3U /*!< SAU SFSR: AUVIOL Position */\r
+#define SAU_SFSR_AUVIOL_Msk (1UL << SAU_SFSR_AUVIOL_Pos) /*!< SAU SFSR: AUVIOL Mask */\r
+\r
+#define SAU_SFSR_INVER_Pos 2U /*!< SAU SFSR: INVER Position */\r
+#define SAU_SFSR_INVER_Msk (1UL << SAU_SFSR_INVER_Pos) /*!< SAU SFSR: INVER Mask */\r
+\r
+#define SAU_SFSR_INVIS_Pos 1U /*!< SAU SFSR: INVIS Position */\r
+#define SAU_SFSR_INVIS_Msk (1UL << SAU_SFSR_INVIS_Pos) /*!< SAU SFSR: INVIS Mask */\r
+\r
+#define SAU_SFSR_INVEP_Pos 0U /*!< SAU SFSR: INVEP Position */\r
+#define SAU_SFSR_INVEP_Msk (1UL /*<< SAU_SFSR_INVEP_Pos*/) /*!< SAU SFSR: INVEP Mask */\r
+\r
+/*@} end of group CMSIS_SAU */\r
+#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */\r
+\r
+\r
+/**\r
+ \ingroup CMSIS_core_register\r
+ \defgroup CMSIS_FPU Floating Point Unit (FPU)\r
+ \brief Type definitions for the Floating Point Unit (FPU)\r
+ @{\r
+ */\r
+\r
+/**\r
+ \brief Structure type to access the Floating Point Unit (FPU).\r
+ */\r
+typedef struct\r
+{\r
+ uint32_t RESERVED0[1U];\r
+ __IOM uint32_t FPCCR; /*!< Offset: 0x004 (R/W) Floating-Point Context Control Register */\r
+ __IOM uint32_t FPCAR; /*!< Offset: 0x008 (R/W) Floating-Point Context Address Register */\r
+ __IOM uint32_t FPDSCR; /*!< Offset: 0x00C (R/W) Floating-Point Default Status Control Register */\r
+ __IM uint32_t MVFR0; /*!< Offset: 0x010 (R/ ) Media and FP Feature Register 0 */\r
+ __IM uint32_t MVFR1; /*!< Offset: 0x014 (R/ ) Media and FP Feature Register 1 */\r
+} FPU_Type;\r
+\r
+/* Floating-Point Context Control Register Definitions */\r
+#define FPU_FPCCR_ASPEN_Pos 31U /*!< FPCCR: ASPEN bit Position */\r
+#define FPU_FPCCR_ASPEN_Msk (1UL << FPU_FPCCR_ASPEN_Pos) /*!< FPCCR: ASPEN bit Mask */\r
+\r
+#define FPU_FPCCR_LSPEN_Pos 30U /*!< FPCCR: LSPEN Position */\r
+#define FPU_FPCCR_LSPEN_Msk (1UL << FPU_FPCCR_LSPEN_Pos) /*!< FPCCR: LSPEN bit Mask */\r
+\r
+#define FPU_FPCCR_LSPENS_Pos 29U /*!< FPCCR: LSPENS Position */\r
+#define FPU_FPCCR_LSPENS_Msk (1UL << FPU_FPCCR_LSPENS_Pos) /*!< FPCCR: LSPENS bit Mask */\r
+\r
+#define FPU_FPCCR_CLRONRET_Pos 28U /*!< FPCCR: CLRONRET Position */\r
+#define FPU_FPCCR_CLRONRET_Msk (1UL << FPU_FPCCR_CLRONRET_Pos) /*!< FPCCR: CLRONRET bit Mask */\r
+\r
+#define FPU_FPCCR_CLRONRETS_Pos 27U /*!< FPCCR: CLRONRETS Position */\r
+#define FPU_FPCCR_CLRONRETS_Msk (1UL << FPU_FPCCR_CLRONRETS_Pos) /*!< FPCCR: CLRONRETS bit Mask */\r
+\r
+#define FPU_FPCCR_TS_Pos 26U /*!< FPCCR: TS Position */\r
+#define FPU_FPCCR_TS_Msk (1UL << FPU_FPCCR_TS_Pos) /*!< FPCCR: TS bit Mask */\r
+\r
+#define FPU_FPCCR_UFRDY_Pos 10U /*!< FPCCR: UFRDY Position */\r
+#define FPU_FPCCR_UFRDY_Msk (1UL << FPU_FPCCR_UFRDY_Pos) /*!< FPCCR: UFRDY bit Mask */\r
+\r
+#define FPU_FPCCR_SPLIMVIOL_Pos 9U /*!< FPCCR: SPLIMVIOL Position */\r
+#define FPU_FPCCR_SPLIMVIOL_Msk (1UL << FPU_FPCCR_SPLIMVIOL_Pos) /*!< FPCCR: SPLIMVIOL bit Mask */\r
+\r
+#define FPU_FPCCR_MONRDY_Pos 8U /*!< FPCCR: MONRDY Position */\r
+#define FPU_FPCCR_MONRDY_Msk (1UL << FPU_FPCCR_MONRDY_Pos) /*!< FPCCR: MONRDY bit Mask */\r
+\r
+#define FPU_FPCCR_SFRDY_Pos 7U /*!< FPCCR: SFRDY Position */\r
+#define FPU_FPCCR_SFRDY_Msk (1UL << FPU_FPCCR_SFRDY_Pos) /*!< FPCCR: SFRDY bit Mask */\r
+\r
+#define FPU_FPCCR_BFRDY_Pos 6U /*!< FPCCR: BFRDY Position */\r
+#define FPU_FPCCR_BFRDY_Msk (1UL << FPU_FPCCR_BFRDY_Pos) /*!< FPCCR: BFRDY bit Mask */\r
+\r
+#define FPU_FPCCR_MMRDY_Pos 5U /*!< FPCCR: MMRDY Position */\r
+#define FPU_FPCCR_MMRDY_Msk (1UL << FPU_FPCCR_MMRDY_Pos) /*!< FPCCR: MMRDY bit Mask */\r
+\r
+#define FPU_FPCCR_HFRDY_Pos 4U /*!< FPCCR: HFRDY Position */\r
+#define FPU_FPCCR_HFRDY_Msk (1UL << FPU_FPCCR_HFRDY_Pos) /*!< FPCCR: HFRDY bit Mask */\r
+\r
+#define FPU_FPCCR_THREAD_Pos 3U /*!< FPCCR: processor mode bit Position */\r
+#define FPU_FPCCR_THREAD_Msk (1UL << FPU_FPCCR_THREAD_Pos) /*!< FPCCR: processor mode active bit Mask */\r
+\r
+#define FPU_FPCCR_S_Pos 2U /*!< FPCCR: Security status of the FP context bit Position */\r
+#define FPU_FPCCR_S_Msk (1UL << FPU_FPCCR_S_Pos) /*!< FPCCR: Security status of the FP context bit Mask */\r
+\r
+#define FPU_FPCCR_USER_Pos 1U /*!< FPCCR: privilege level bit Position */\r
+#define FPU_FPCCR_USER_Msk (1UL << FPU_FPCCR_USER_Pos) /*!< FPCCR: privilege level bit Mask */\r
+\r
+#define FPU_FPCCR_LSPACT_Pos 0U /*!< FPCCR: Lazy state preservation active bit Position */\r
+#define FPU_FPCCR_LSPACT_Msk (1UL /*<< FPU_FPCCR_LSPACT_Pos*/) /*!< FPCCR: Lazy state preservation active bit Mask */\r
+\r
+/* Floating-Point Context Address Register Definitions */\r
+#define FPU_FPCAR_ADDRESS_Pos 3U /*!< FPCAR: ADDRESS bit Position */\r
+#define FPU_FPCAR_ADDRESS_Msk (0x1FFFFFFFUL << FPU_FPCAR_ADDRESS_Pos) /*!< FPCAR: ADDRESS bit Mask */\r
+\r
+/* Floating-Point Default Status Control Register Definitions */\r
+#define FPU_FPDSCR_AHP_Pos 26U /*!< FPDSCR: AHP bit Position */\r
+#define FPU_FPDSCR_AHP_Msk (1UL << FPU_FPDSCR_AHP_Pos) /*!< FPDSCR: AHP bit Mask */\r
+\r
+#define FPU_FPDSCR_DN_Pos 25U /*!< FPDSCR: DN bit Position */\r
+#define FPU_FPDSCR_DN_Msk (1UL << FPU_FPDSCR_DN_Pos) /*!< FPDSCR: DN bit Mask */\r
+\r
+#define FPU_FPDSCR_FZ_Pos 24U /*!< FPDSCR: FZ bit Position */\r
+#define FPU_FPDSCR_FZ_Msk (1UL << FPU_FPDSCR_FZ_Pos) /*!< FPDSCR: FZ bit Mask */\r
+\r
+#define FPU_FPDSCR_RMode_Pos 22U /*!< FPDSCR: RMode bit Position */\r
+#define FPU_FPDSCR_RMode_Msk (3UL << FPU_FPDSCR_RMode_Pos) /*!< FPDSCR: RMode bit Mask */\r
+\r
+/* Media and FP Feature Register 0 Definitions */\r
+#define FPU_MVFR0_FP_rounding_modes_Pos 28U /*!< MVFR0: FP rounding modes bits Position */\r
+#define FPU_MVFR0_FP_rounding_modes_Msk (0xFUL << FPU_MVFR0_FP_rounding_modes_Pos) /*!< MVFR0: FP rounding modes bits Mask */\r
+\r
+#define FPU_MVFR0_Short_vectors_Pos 24U /*!< MVFR0: Short vectors bits Position */\r
+#define FPU_MVFR0_Short_vectors_Msk (0xFUL << FPU_MVFR0_Short_vectors_Pos) /*!< MVFR0: Short vectors bits Mask */\r
+\r
+#define FPU_MVFR0_Square_root_Pos 20U /*!< MVFR0: Square root bits Position */\r
+#define FPU_MVFR0_Square_root_Msk (0xFUL << FPU_MVFR0_Square_root_Pos) /*!< MVFR0: Square root bits Mask */\r
+\r
+#define FPU_MVFR0_Divide_Pos 16U /*!< MVFR0: Divide bits Position */\r
+#define FPU_MVFR0_Divide_Msk (0xFUL << FPU_MVFR0_Divide_Pos) /*!< MVFR0: Divide bits Mask */\r
+\r
+#define FPU_MVFR0_FP_excep_trapping_Pos 12U /*!< MVFR0: FP exception trapping bits Position */\r
+#define FPU_MVFR0_FP_excep_trapping_Msk (0xFUL << FPU_MVFR0_FP_excep_trapping_Pos) /*!< MVFR0: FP exception trapping bits Mask */\r
+\r
+#define FPU_MVFR0_Double_precision_Pos 8U /*!< MVFR0: Double-precision bits Position */\r
+#define FPU_MVFR0_Double_precision_Msk (0xFUL << FPU_MVFR0_Double_precision_Pos) /*!< MVFR0: Double-precision bits Mask */\r
+\r
+#define FPU_MVFR0_Single_precision_Pos 4U /*!< MVFR0: Single-precision bits Position */\r
+#define FPU_MVFR0_Single_precision_Msk (0xFUL << FPU_MVFR0_Single_precision_Pos) /*!< MVFR0: Single-precision bits Mask */\r
+\r
+#define FPU_MVFR0_A_SIMD_registers_Pos 0U /*!< MVFR0: A_SIMD registers bits Position */\r
+#define FPU_MVFR0_A_SIMD_registers_Msk (0xFUL /*<< FPU_MVFR0_A_SIMD_registers_Pos*/) /*!< MVFR0: A_SIMD registers bits Mask */\r
+\r
+/* Media and FP Feature Register 1 Definitions */\r
+#define FPU_MVFR1_FP_fused_MAC_Pos 28U /*!< MVFR1: FP fused MAC bits Position */\r
+#define FPU_MVFR1_FP_fused_MAC_Msk (0xFUL << FPU_MVFR1_FP_fused_MAC_Pos) /*!< MVFR1: FP fused MAC bits Mask */\r
+\r
+#define FPU_MVFR1_FP_HPFP_Pos 24U /*!< MVFR1: FP HPFP bits Position */\r
+#define FPU_MVFR1_FP_HPFP_Msk (0xFUL << FPU_MVFR1_FP_HPFP_Pos) /*!< MVFR1: FP HPFP bits Mask */\r
+\r
+#define FPU_MVFR1_D_NaN_mode_Pos 4U /*!< MVFR1: D_NaN mode bits Position */\r
+#define FPU_MVFR1_D_NaN_mode_Msk (0xFUL << FPU_MVFR1_D_NaN_mode_Pos) /*!< MVFR1: D_NaN mode bits Mask */\r
+\r
+#define FPU_MVFR1_FtZ_mode_Pos 0U /*!< MVFR1: FtZ mode bits Position */\r
+#define FPU_MVFR1_FtZ_mode_Msk (0xFUL /*<< FPU_MVFR1_FtZ_mode_Pos*/) /*!< MVFR1: FtZ mode bits Mask */\r
+\r
+/*@} end of group CMSIS_FPU */\r
+\r
+\r
+/**\r
+ \ingroup CMSIS_core_register\r
+ \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug)\r
+ \brief Type definitions for the Core Debug Registers\r
+ @{\r
+ */\r
+\r
+/**\r
+ \brief Structure type to access the Core Debug Register (CoreDebug).\r
+ */\r
+typedef struct\r
+{\r
+ __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */\r
+ __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */\r
+ __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */\r
+ __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */\r
+ uint32_t RESERVED4[1U];\r
+ __IOM uint32_t DAUTHCTRL; /*!< Offset: 0x014 (R/W) Debug Authentication Control Register */\r
+ __IOM uint32_t DSCSR; /*!< Offset: 0x018 (R/W) Debug Security Control and Status Register */\r
+} CoreDebug_Type;\r
+\r
+/* Debug Halting Control and Status Register Definitions */\r
+#define CoreDebug_DHCSR_DBGKEY_Pos 16U /*!< CoreDebug DHCSR: DBGKEY Position */\r
+#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */\r
+\r
+#define CoreDebug_DHCSR_S_RESTART_ST_Pos 26U /*!< CoreDebug DHCSR: S_RESTART_ST Position */\r
+#define CoreDebug_DHCSR_S_RESTART_ST_Msk (1UL << CoreDebug_DHCSR_S_RESTART_ST_Pos) /*!< CoreDebug DHCSR: S_RESTART_ST Mask */\r
+\r
+#define CoreDebug_DHCSR_S_RESET_ST_Pos 25U /*!< CoreDebug DHCSR: S_RESET_ST Position */\r
+#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */\r
+\r
+#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U /*!< CoreDebug DHCSR: S_RETIRE_ST Position */\r
+#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */\r
+\r
+#define CoreDebug_DHCSR_S_LOCKUP_Pos 19U /*!< CoreDebug DHCSR: S_LOCKUP Position */\r
+#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */\r
+\r
+#define CoreDebug_DHCSR_S_SLEEP_Pos 18U /*!< CoreDebug DHCSR: S_SLEEP Position */\r
+#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */\r
+\r
+#define CoreDebug_DHCSR_S_HALT_Pos 17U /*!< CoreDebug DHCSR: S_HALT Position */\r
+#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */\r
+\r
+#define CoreDebug_DHCSR_S_REGRDY_Pos 16U /*!< CoreDebug DHCSR: S_REGRDY Position */\r
+#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */\r
+\r
+#define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5U /*!< CoreDebug DHCSR: C_SNAPSTALL Position */\r
+#define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */\r
+\r
+#define CoreDebug_DHCSR_C_MASKINTS_Pos 3U /*!< CoreDebug DHCSR: C_MASKINTS Position */\r
+#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */\r
+\r
+#define CoreDebug_DHCSR_C_STEP_Pos 2U /*!< CoreDebug DHCSR: C_STEP Position */\r
+#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */\r
+\r
+#define CoreDebug_DHCSR_C_HALT_Pos 1U /*!< CoreDebug DHCSR: C_HALT Position */\r
+#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */\r
+\r
+#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U /*!< CoreDebug DHCSR: C_DEBUGEN Position */\r
+#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */\r
+\r
+/* Debug Core Register Selector Register Definitions */\r
+#define CoreDebug_DCRSR_REGWnR_Pos 16U /*!< CoreDebug DCRSR: REGWnR Position */\r
+#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */\r
+\r
+#define CoreDebug_DCRSR_REGSEL_Pos 0U /*!< CoreDebug DCRSR: REGSEL Position */\r
+#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/) /*!< CoreDebug DCRSR: REGSEL Mask */\r
+\r
+/* Debug Exception and Monitor Control Register Definitions */\r
+#define CoreDebug_DEMCR_TRCENA_Pos 24U /*!< CoreDebug DEMCR: TRCENA Position */\r
+#define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< CoreDebug DEMCR: TRCENA Mask */\r
+\r
+#define CoreDebug_DEMCR_MON_REQ_Pos 19U /*!< CoreDebug DEMCR: MON_REQ Position */\r
+#define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< CoreDebug DEMCR: MON_REQ Mask */\r
+\r
+#define CoreDebug_DEMCR_MON_STEP_Pos 18U /*!< CoreDebug DEMCR: MON_STEP Position */\r
+#define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< CoreDebug DEMCR: MON_STEP Mask */\r
+\r
+#define CoreDebug_DEMCR_MON_PEND_Pos 17U /*!< CoreDebug DEMCR: MON_PEND Position */\r
+#define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< CoreDebug DEMCR: MON_PEND Mask */\r
+\r
+#define CoreDebug_DEMCR_MON_EN_Pos 16U /*!< CoreDebug DEMCR: MON_EN Position */\r
+#define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< CoreDebug DEMCR: MON_EN Mask */\r
+\r
+#define CoreDebug_DEMCR_VC_HARDERR_Pos 10U /*!< CoreDebug DEMCR: VC_HARDERR Position */\r
+#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */\r
+\r
+#define CoreDebug_DEMCR_VC_INTERR_Pos 9U /*!< CoreDebug DEMCR: VC_INTERR Position */\r
+#define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< CoreDebug DEMCR: VC_INTERR Mask */\r
+\r
+#define CoreDebug_DEMCR_VC_BUSERR_Pos 8U /*!< CoreDebug DEMCR: VC_BUSERR Position */\r
+#define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< CoreDebug DEMCR: VC_BUSERR Mask */\r
+\r
+#define CoreDebug_DEMCR_VC_STATERR_Pos 7U /*!< CoreDebug DEMCR: VC_STATERR Position */\r
+#define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< CoreDebug DEMCR: VC_STATERR Mask */\r
+\r
+#define CoreDebug_DEMCR_VC_CHKERR_Pos 6U /*!< CoreDebug DEMCR: VC_CHKERR Position */\r
+#define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< CoreDebug DEMCR: VC_CHKERR Mask */\r
+\r
+#define CoreDebug_DEMCR_VC_NOCPERR_Pos 5U /*!< CoreDebug DEMCR: VC_NOCPERR Position */\r
+#define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< CoreDebug DEMCR: VC_NOCPERR Mask */\r
+\r
+#define CoreDebug_DEMCR_VC_MMERR_Pos 4U /*!< CoreDebug DEMCR: VC_MMERR Position */\r
+#define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< CoreDebug DEMCR: VC_MMERR Mask */\r
+\r
+#define CoreDebug_DEMCR_VC_CORERESET_Pos 0U /*!< CoreDebug DEMCR: VC_CORERESET Position */\r
+#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/) /*!< CoreDebug DEMCR: VC_CORERESET Mask */\r
+\r
+/* Debug Authentication Control Register Definitions */\r
+#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos 3U /*!< CoreDebug DAUTHCTRL: INTSPNIDEN, Position */\r
+#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos) /*!< CoreDebug DAUTHCTRL: INTSPNIDEN, Mask */\r
+\r
+#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos 2U /*!< CoreDebug DAUTHCTRL: SPNIDENSEL Position */\r
+#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Msk (1UL << CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos) /*!< CoreDebug DAUTHCTRL: SPNIDENSEL Mask */\r
+\r
+#define CoreDebug_DAUTHCTRL_INTSPIDEN_Pos 1U /*!< CoreDebug DAUTHCTRL: INTSPIDEN Position */\r
+#define CoreDebug_DAUTHCTRL_INTSPIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPIDEN_Pos) /*!< CoreDebug DAUTHCTRL: INTSPIDEN Mask */\r
+\r
+#define CoreDebug_DAUTHCTRL_SPIDENSEL_Pos 0U /*!< CoreDebug DAUTHCTRL: SPIDENSEL Position */\r
+#define CoreDebug_DAUTHCTRL_SPIDENSEL_Msk (1UL /*<< CoreDebug_DAUTHCTRL_SPIDENSEL_Pos*/) /*!< CoreDebug DAUTHCTRL: SPIDENSEL Mask */\r
+\r
+/* Debug Security Control and Status Register Definitions */\r
+#define CoreDebug_DSCSR_CDS_Pos 16U /*!< CoreDebug DSCSR: CDS Position */\r
+#define CoreDebug_DSCSR_CDS_Msk (1UL << CoreDebug_DSCSR_CDS_Pos) /*!< CoreDebug DSCSR: CDS Mask */\r
+\r
+#define CoreDebug_DSCSR_SBRSEL_Pos 1U /*!< CoreDebug DSCSR: SBRSEL Position */\r
+#define CoreDebug_DSCSR_SBRSEL_Msk (1UL << CoreDebug_DSCSR_SBRSEL_Pos) /*!< CoreDebug DSCSR: SBRSEL Mask */\r
+\r
+#define CoreDebug_DSCSR_SBRSELEN_Pos 0U /*!< CoreDebug DSCSR: SBRSELEN Position */\r
+#define CoreDebug_DSCSR_SBRSELEN_Msk (1UL /*<< CoreDebug_DSCSR_SBRSELEN_Pos*/) /*!< CoreDebug DSCSR: SBRSELEN Mask */\r
+\r
+/*@} end of group CMSIS_CoreDebug */\r
+\r
+\r
+/**\r
+ \ingroup CMSIS_core_register\r
+ \defgroup CMSIS_core_bitfield Core register bit field macros\r
+ \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk).\r
+ @{\r
+ */\r
+\r
+/**\r
+ \brief Mask and shift a bit field value for use in a register bit range.\r
+ \param[in] field Name of the register bit field.\r
+ \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type.\r
+ \return Masked and shifted value.\r
+*/\r
+#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk)\r
+\r
+/**\r
+ \brief Mask and shift a register value to extract a bit filed value.\r
+ \param[in] field Name of the register bit field.\r
+ \param[in] value Value of register. This parameter is interpreted as an uint32_t type.\r
+ \return Masked and shifted bit field value.\r
+*/\r
+#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos)\r
+\r
+/*@} end of group CMSIS_core_bitfield */\r
+\r
+\r
+/**\r
+ \ingroup CMSIS_core_register\r
+ \defgroup CMSIS_core_base Core Definitions\r
+ \brief Definitions for base addresses, unions, and structures.\r
+ @{\r
+ */\r
+\r
+/* Memory mapping of Core Hardware */\r
+ #define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */\r
+ #define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */\r
+ #define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */\r
+ #define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */\r
+ #define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */\r
+ #define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */\r
+ #define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */\r
+ #define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */\r
+\r
+ #define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */\r
+ #define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */\r
+ #define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */\r
+ #define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */\r
+ #define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */\r
+ #define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */\r
+ #define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */\r
+ #define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE ) /*!< Core Debug configuration struct */\r
+\r
+ #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)\r
+ #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */\r
+ #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */\r
+ #endif\r
+\r
+ #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)\r
+ #define SAU_BASE (SCS_BASE + 0x0DD0UL) /*!< Security Attribution Unit */\r
+ #define SAU ((SAU_Type *) SAU_BASE ) /*!< Security Attribution Unit */\r
+ #endif\r
+\r
+ #define FPU_BASE (SCS_BASE + 0x0F30UL) /*!< Floating Point Unit */\r
+ #define FPU ((FPU_Type *) FPU_BASE ) /*!< Floating Point Unit */\r
+\r
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)\r
+ #define SCS_BASE_NS (0xE002E000UL) /*!< System Control Space Base Address (non-secure address space) */\r
+ #define CoreDebug_BASE_NS (0xE002EDF0UL) /*!< Core Debug Base Address (non-secure address space) */\r
+ #define SysTick_BASE_NS (SCS_BASE_NS + 0x0010UL) /*!< SysTick Base Address (non-secure address space) */\r
+ #define NVIC_BASE_NS (SCS_BASE_NS + 0x0100UL) /*!< NVIC Base Address (non-secure address space) */\r
+ #define SCB_BASE_NS (SCS_BASE_NS + 0x0D00UL) /*!< System Control Block Base Address (non-secure address space) */\r
+\r
+ #define SCnSCB_NS ((SCnSCB_Type *) SCS_BASE_NS ) /*!< System control Register not in SCB(non-secure address space) */\r
+ #define SCB_NS ((SCB_Type *) SCB_BASE_NS ) /*!< SCB configuration struct (non-secure address space) */\r
+ #define SysTick_NS ((SysTick_Type *) SysTick_BASE_NS ) /*!< SysTick configuration struct (non-secure address space) */\r
+ #define NVIC_NS ((NVIC_Type *) NVIC_BASE_NS ) /*!< NVIC configuration struct (non-secure address space) */\r
+ #define CoreDebug_NS ((CoreDebug_Type *) CoreDebug_BASE_NS) /*!< Core Debug configuration struct (non-secure address space) */\r
+\r
+ #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)\r
+ #define MPU_BASE_NS (SCS_BASE_NS + 0x0D90UL) /*!< Memory Protection Unit (non-secure address space) */\r
+ #define MPU_NS ((MPU_Type *) MPU_BASE_NS ) /*!< Memory Protection Unit (non-secure address space) */\r
+ #endif\r
+\r
+ #define FPU_BASE_NS (SCS_BASE_NS + 0x0F30UL) /*!< Floating Point Unit (non-secure address space) */\r
+ #define FPU_NS ((FPU_Type *) FPU_BASE_NS ) /*!< Floating Point Unit (non-secure address space) */\r
+\r
+#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */\r
+/*@} */\r
+\r
+\r
+\r
+/*******************************************************************************\r
+ * Hardware Abstraction Layer\r
+ Core Function Interface contains:\r
+ - Core NVIC Functions\r
+ - Core SysTick Functions\r
+ - Core Debug Functions\r
+ - Core Register Access Functions\r
+ ******************************************************************************/\r
+/**\r
+ \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference\r
+*/\r
+\r
+\r
+\r
+/* ########################## NVIC functions #################################### */\r
+/**\r
+ \ingroup CMSIS_Core_FunctionInterface\r
+ \defgroup CMSIS_Core_NVICFunctions NVIC Functions\r
+ \brief Functions that manage interrupts and exceptions via the NVIC.\r
+ @{\r
+ */\r
+\r
+#ifdef CMSIS_NVIC_VIRTUAL\r
+ #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE\r
+ #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h"\r
+ #endif\r
+ #include CMSIS_NVIC_VIRTUAL_HEADER_FILE\r
+#else\r
+ #define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping\r
+ #define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping\r
+ #define NVIC_EnableIRQ __NVIC_EnableIRQ\r
+ #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ\r
+ #define NVIC_DisableIRQ __NVIC_DisableIRQ\r
+ #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ\r
+ #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ\r
+ #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ\r
+ #define NVIC_GetActive __NVIC_GetActive\r
+ #define NVIC_SetPriority __NVIC_SetPriority\r
+ #define NVIC_GetPriority __NVIC_GetPriority\r
+ #define NVIC_SystemReset __NVIC_SystemReset\r
+#endif /* CMSIS_NVIC_VIRTUAL */\r
+\r
+#ifdef CMSIS_VECTAB_VIRTUAL\r
+ #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE\r
+ #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h"\r
+ #endif\r
+ #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE\r
+#else\r
+ #define NVIC_SetVector __NVIC_SetVector\r
+ #define NVIC_GetVector __NVIC_GetVector\r
+#endif /* (CMSIS_VECTAB_VIRTUAL) */\r
+\r
+#define NVIC_USER_IRQ_OFFSET 16\r
+\r
+\r
+/* Special LR values for Secure/Non-Secure call handling and exception handling */\r
+\r
+/* Function Return Payload (from ARMv8-M Architecture Reference Manual) LR value on entry from Secure BLXNS */ \r
+#define FNC_RETURN (0xFEFFFFFFUL) /* bit [0] ignored when processing a branch */\r
+\r
+/* The following EXC_RETURN mask values are used to evaluate the LR on exception entry */\r
+#define EXC_RETURN_PREFIX (0xFF000000UL) /* bits [31:24] set to indicate an EXC_RETURN value */\r
+#define EXC_RETURN_S (0x00000040UL) /* bit [6] stack used to push registers: 0=Non-secure 1=Secure */\r
+#define EXC_RETURN_DCRS (0x00000020UL) /* bit [5] stacking rules for called registers: 0=skipped 1=saved */\r
+#define EXC_RETURN_FTYPE (0x00000010UL) /* bit [4] allocate stack for floating-point context: 0=done 1=skipped */\r
+#define EXC_RETURN_MODE (0x00000008UL) /* bit [3] processor mode for return: 0=Handler mode 1=Thread mode */\r
+#define EXC_RETURN_SPSEL (0x00000002UL) /* bit [1] stack pointer used to restore context: 0=MSP 1=PSP */\r
+#define EXC_RETURN_ES (0x00000001UL) /* bit [0] security state exception was taken to: 0=Non-secure 1=Secure */\r
+\r
+/* Integrity Signature (from ARMv8-M Architecture Reference Manual) for exception context stacking */\r
+#if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) /* Value for processors with floating-point extension: */\r
+#define EXC_INTEGRITY_SIGNATURE (0xFEFA125AUL) /* bit [0] SFTC must match LR bit[4] EXC_RETURN_FTYPE */\r
+#else \r
+#define EXC_INTEGRITY_SIGNATURE (0xFEFA125BUL) /* Value for processors without floating-point extension */\r
+#endif\r
+\r
+\r
+/**\r
+ \brief Set Priority Grouping\r
+ \details Sets the priority grouping field using the required unlock sequence.\r
+ The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field.\r
+ Only values from 0..7 are used.\r
+ In case of a conflict between priority grouping and available\r
+ priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.\r
+ \param [in] PriorityGroup Priority grouping field.\r
+ */\r
+__STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup)\r
+{\r
+ uint32_t reg_value;\r
+ uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */\r
+\r
+ reg_value = SCB->AIRCR; /* read old register configuration */\r
+ reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */\r
+ reg_value = (reg_value |\r
+ ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |\r
+ (PriorityGroupTmp << 8U) ); /* Insert write key and priority group */\r
+ SCB->AIRCR = reg_value;\r
+}\r
+\r
+\r
+/**\r
+ \brief Get Priority Grouping\r
+ \details Reads the priority grouping field from the NVIC Interrupt Controller.\r
+ \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field).\r
+ */\r
+__STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void)\r
+{\r
+ return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos));\r
+}\r
+\r
+\r
+/**\r
+ \brief Enable Interrupt\r
+ \details Enables a device specific interrupt in the NVIC interrupt controller.\r
+ \param [in] IRQn Device specific interrupt number.\r
+ \note IRQn must not be negative.\r
+ */\r
+__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn)\r
+{\r
+ if ((int32_t)(IRQn) >= 0)\r
+ {\r
+ NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));\r
+ }\r
+}\r
+\r
+\r
+/**\r
+ \brief Get Interrupt Enable status\r
+ \details Returns a device specific interrupt enable status from the NVIC interrupt controller.\r
+ \param [in] IRQn Device specific interrupt number.\r
+ \return 0 Interrupt is not enabled.\r
+ \return 1 Interrupt is enabled.\r
+ \note IRQn must not be negative.\r
+ */\r
+__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn)\r
+{\r
+ if ((int32_t)(IRQn) >= 0)\r
+ {\r
+ return((uint32_t)(((NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));\r
+ }\r
+ else\r
+ {\r
+ return(0U);\r
+ }\r
+}\r
+\r
+\r
+/**\r
+ \brief Disable Interrupt\r
+ \details Disables a device specific interrupt in the NVIC interrupt controller.\r
+ \param [in] IRQn Device specific interrupt number.\r
+ \note IRQn must not be negative.\r
+ */\r
+__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn)\r
+{\r
+ if ((int32_t)(IRQn) >= 0)\r
+ {\r
+ NVIC->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));\r
+ __DSB();\r
+ __ISB();\r
+ }\r
+}\r
+\r
+\r
+/**\r
+ \brief Get Pending Interrupt\r
+ \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt.\r
+ \param [in] IRQn Device specific interrupt number.\r
+ \return 0 Interrupt status is not pending.\r
+ \return 1 Interrupt status is pending.\r
+ \note IRQn must not be negative.\r
+ */\r
+__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn)\r
+{\r
+ if ((int32_t)(IRQn) >= 0)\r
+ {\r
+ return((uint32_t)(((NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));\r
+ }\r
+ else\r
+ {\r
+ return(0U);\r
+ }\r
+}\r
+\r
+\r
+/**\r
+ \brief Set Pending Interrupt\r
+ \details Sets the pending bit of a device specific interrupt in the NVIC pending register.\r
+ \param [in] IRQn Device specific interrupt number.\r
+ \note IRQn must not be negative.\r
+ */\r
+__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn)\r
+{\r
+ if ((int32_t)(IRQn) >= 0)\r
+ {\r
+ NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));\r
+ }\r
+}\r
+\r
+\r
+/**\r
+ \brief Clear Pending Interrupt\r
+ \details Clears the pending bit of a device specific interrupt in the NVIC pending register.\r
+ \param [in] IRQn Device specific interrupt number.\r
+ \note IRQn must not be negative.\r
+ */\r
+__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn)\r
+{\r
+ if ((int32_t)(IRQn) >= 0)\r
+ {\r
+ NVIC->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));\r
+ }\r
+}\r
+\r
+\r
+/**\r
+ \brief Get Active Interrupt\r
+ \details Reads the active register in the NVIC and returns the active bit for the device specific interrupt.\r
+ \param [in] IRQn Device specific interrupt number.\r
+ \return 0 Interrupt status is not active.\r
+ \return 1 Interrupt status is active.\r
+ \note IRQn must not be negative.\r
+ */\r
+__STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn)\r
+{\r
+ if ((int32_t)(IRQn) >= 0)\r
+ {\r
+ return((uint32_t)(((NVIC->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));\r
+ }\r
+ else\r
+ {\r
+ return(0U);\r
+ }\r
+}\r
+\r
+\r
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)\r
+/**\r
+ \brief Get Interrupt Target State\r
+ \details Reads the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt.\r
+ \param [in] IRQn Device specific interrupt number.\r
+ \return 0 if interrupt is assigned to Secure\r
+ \return 1 if interrupt is assigned to Non Secure\r
+ \note IRQn must not be negative.\r
+ */\r
+__STATIC_INLINE uint32_t NVIC_GetTargetState(IRQn_Type IRQn)\r
+{\r
+ if ((int32_t)(IRQn) >= 0)\r
+ {\r
+ return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));\r
+ }\r
+ else\r
+ {\r
+ return(0U);\r
+ }\r
+}\r
+\r
+\r
+/**\r
+ \brief Set Interrupt Target State\r
+ \details Sets the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt.\r
+ \param [in] IRQn Device specific interrupt number.\r
+ \return 0 if interrupt is assigned to Secure\r
+ 1 if interrupt is assigned to Non Secure\r
+ \note IRQn must not be negative.\r
+ */\r
+__STATIC_INLINE uint32_t NVIC_SetTargetState(IRQn_Type IRQn)\r
+{\r
+ if ((int32_t)(IRQn) >= 0)\r
+ {\r
+ NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] |= ((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)));\r
+ return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));\r
+ }\r
+ else\r
+ {\r
+ return(0U);\r
+ }\r
+}\r
+\r
+\r
+/**\r
+ \brief Clear Interrupt Target State\r
+ \details Clears the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt.\r
+ \param [in] IRQn Device specific interrupt number.\r
+ \return 0 if interrupt is assigned to Secure\r
+ 1 if interrupt is assigned to Non Secure\r
+ \note IRQn must not be negative.\r
+ */\r
+__STATIC_INLINE uint32_t NVIC_ClearTargetState(IRQn_Type IRQn)\r
+{\r
+ if ((int32_t)(IRQn) >= 0)\r
+ {\r
+ NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] &= ~((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)));\r
+ return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));\r
+ }\r
+ else\r
+ {\r
+ return(0U);\r
+ }\r
+}\r
+#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */\r
+\r
+\r
+/**\r
+ \brief Set Interrupt Priority\r
+ \details Sets the priority of a device specific interrupt or a processor exception.\r
+ The interrupt number can be positive to specify a device specific interrupt,\r
+ or negative to specify a processor exception.\r
+ \param [in] IRQn Interrupt number.\r
+ \param [in] priority Priority to set.\r
+ \note The priority cannot be set for every processor exception.\r
+ */\r
+__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)\r
+{\r
+ if ((int32_t)(IRQn) >= 0)\r
+ {\r
+ NVIC->IPR[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);\r
+ }\r
+ else\r
+ {\r
+ SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);\r
+ }\r
+}\r
+\r
+\r
+/**\r
+ \brief Get Interrupt Priority\r
+ \details Reads the priority of a device specific interrupt or a processor exception.\r
+ The interrupt number can be positive to specify a device specific interrupt,\r
+ or negative to specify a processor exception.\r
+ \param [in] IRQn Interrupt number.\r
+ \return Interrupt Priority.\r
+ Value is aligned automatically to the implemented priority bits of the microcontroller.\r
+ */\r
+__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn)\r
+{\r
+\r
+ if ((int32_t)(IRQn) >= 0)\r
+ {\r
+ return(((uint32_t)NVIC->IPR[((uint32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS)));\r
+ }\r
+ else\r
+ {\r
+ return(((uint32_t)SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS)));\r
+ }\r
+}\r
+\r
+\r
+/**\r
+ \brief Encode Priority\r
+ \details Encodes the priority for an interrupt with the given priority group,\r
+ preemptive priority value, and subpriority value.\r
+ In case of a conflict between priority grouping and available\r
+ priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.\r
+ \param [in] PriorityGroup Used priority group.\r
+ \param [in] PreemptPriority Preemptive priority value (starting from 0).\r
+ \param [in] SubPriority Subpriority value (starting from 0).\r
+ \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority().\r
+ */\r
+__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)\r
+{\r
+ uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */\r
+ uint32_t PreemptPriorityBits;\r
+ uint32_t SubPriorityBits;\r
+\r
+ PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);\r
+ SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));\r
+\r
+ return (\r
+ ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) |\r
+ ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL)))\r
+ );\r
+}\r
+\r
+\r
+/**\r
+ \brief Decode Priority\r
+ \details Decodes an interrupt priority value with a given priority group to\r
+ preemptive priority value and subpriority value.\r
+ In case of a conflict between priority grouping and available\r
+ priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set.\r
+ \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority().\r
+ \param [in] PriorityGroup Used priority group.\r
+ \param [out] pPreemptPriority Preemptive priority value (starting from 0).\r
+ \param [out] pSubPriority Subpriority value (starting from 0).\r
+ */\r
+__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority)\r
+{\r
+ uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */\r
+ uint32_t PreemptPriorityBits;\r
+ uint32_t SubPriorityBits;\r
+\r
+ PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);\r
+ SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));\r
+\r
+ *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL);\r
+ *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL);\r
+}\r
+\r
+\r
+/**\r
+ \brief Set Interrupt Vector\r
+ \details Sets an interrupt vector in SRAM based interrupt vector table.\r
+ The interrupt number can be positive to specify a device specific interrupt,\r
+ or negative to specify a processor exception.\r
+ VTOR must been relocated to SRAM before.\r
+ \param [in] IRQn Interrupt number\r
+ \param [in] vector Address of interrupt handler function\r
+ */\r
+__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector)\r
+{\r
+ uint32_t *vectors = (uint32_t *)SCB->VTOR;\r
+ vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector;\r
+}\r
+\r
+\r
+/**\r
+ \brief Get Interrupt Vector\r
+ \details Reads an interrupt vector from interrupt vector table.\r
+ The interrupt number can be positive to specify a device specific interrupt,\r
+ or negative to specify a processor exception.\r
+ \param [in] IRQn Interrupt number.\r
+ \return Address of interrupt handler function\r
+ */\r
+__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn)\r
+{\r
+ uint32_t *vectors = (uint32_t *)SCB->VTOR;\r
+ return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET];\r
+}\r
+\r
+\r
+/**\r
+ \brief System Reset\r
+ \details Initiates a system reset request to reset the MCU.\r
+ */\r
+__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void)\r
+{\r
+ __DSB(); /* Ensure all outstanding memory accesses included\r
+ buffered write are completed before reset */\r
+ SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |\r
+ (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) |\r
+ SCB_AIRCR_SYSRESETREQ_Msk ); /* Keep priority group unchanged */\r
+ __DSB(); /* Ensure completion of memory access */\r
+\r
+ for(;;) /* wait until reset */\r
+ {\r
+ __NOP();\r
+ }\r
+}\r
+\r
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)\r
+/**\r
+ \brief Set Priority Grouping (non-secure)\r
+ \details Sets the non-secure priority grouping field when in secure state using the required unlock sequence.\r
+ The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field.\r
+ Only values from 0..7 are used.\r
+ In case of a conflict between priority grouping and available\r
+ priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.\r
+ \param [in] PriorityGroup Priority grouping field.\r
+ */\r
+__STATIC_INLINE void TZ_NVIC_SetPriorityGrouping_NS(uint32_t PriorityGroup)\r
+{\r
+ uint32_t reg_value;\r
+ uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */\r
+\r
+ reg_value = SCB_NS->AIRCR; /* read old register configuration */\r
+ reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */\r
+ reg_value = (reg_value |\r
+ ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |\r
+ (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key and priority group */\r
+ SCB_NS->AIRCR = reg_value;\r
+}\r
+\r
+\r
+/**\r
+ \brief Get Priority Grouping (non-secure)\r
+ \details Reads the priority grouping field from the non-secure NVIC when in secure state.\r
+ \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field).\r
+ */\r
+__STATIC_INLINE uint32_t TZ_NVIC_GetPriorityGrouping_NS(void)\r
+{\r
+ return ((uint32_t)((SCB_NS->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos));\r
+}\r
+\r
+\r
+/**\r
+ \brief Enable Interrupt (non-secure)\r
+ \details Enables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state.\r
+ \param [in] IRQn Device specific interrupt number.\r
+ \note IRQn must not be negative.\r
+ */\r
+__STATIC_INLINE void TZ_NVIC_EnableIRQ_NS(IRQn_Type IRQn)\r
+{\r
+ if ((int32_t)(IRQn) >= 0)\r
+ {\r
+ NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));\r
+ }\r
+}\r
+\r
+\r
+/**\r
+ \brief Get Interrupt Enable status (non-secure)\r
+ \details Returns a device specific interrupt enable status from the non-secure NVIC interrupt controller when in secure state.\r
+ \param [in] IRQn Device specific interrupt number.\r
+ \return 0 Interrupt is not enabled.\r
+ \return 1 Interrupt is enabled.\r
+ \note IRQn must not be negative.\r
+ */\r
+__STATIC_INLINE uint32_t TZ_NVIC_GetEnableIRQ_NS(IRQn_Type IRQn)\r
+{\r
+ if ((int32_t)(IRQn) >= 0)\r
+ {\r
+ return((uint32_t)(((NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));\r
+ }\r
+ else\r
+ {\r
+ return(0U);\r
+ }\r
+}\r
+\r
+\r
+/**\r
+ \brief Disable Interrupt (non-secure)\r
+ \details Disables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state.\r
+ \param [in] IRQn Device specific interrupt number.\r
+ \note IRQn must not be negative.\r
+ */\r
+__STATIC_INLINE void TZ_NVIC_DisableIRQ_NS(IRQn_Type IRQn)\r
+{\r
+ if ((int32_t)(IRQn) >= 0)\r
+ {\r
+ NVIC_NS->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));\r
+ }\r
+}\r
+\r
+\r
+/**\r
+ \brief Get Pending Interrupt (non-secure)\r
+ \details Reads the NVIC pending register in the non-secure NVIC when in secure state and returns the pending bit for the specified device specific interrupt.\r
+ \param [in] IRQn Device specific interrupt number.\r
+ \return 0 Interrupt status is not pending.\r
+ \return 1 Interrupt status is pending.\r
+ \note IRQn must not be negative.\r
+ */\r
+__STATIC_INLINE uint32_t TZ_NVIC_GetPendingIRQ_NS(IRQn_Type IRQn)\r
+{\r
+ if ((int32_t)(IRQn) >= 0)\r
+ {\r
+ return((uint32_t)(((NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));\r
+ }\r
+ else\r
+ {\r
+ return(0U);\r
+ }\r
+}\r
+\r
+\r
+/**\r
+ \brief Set Pending Interrupt (non-secure)\r
+ \details Sets the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state.\r
+ \param [in] IRQn Device specific interrupt number.\r
+ \note IRQn must not be negative.\r
+ */\r
+__STATIC_INLINE void TZ_NVIC_SetPendingIRQ_NS(IRQn_Type IRQn)\r
+{\r
+ if ((int32_t)(IRQn) >= 0)\r
+ {\r
+ NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));\r
+ }\r
+}\r
+\r
+\r
+/**\r
+ \brief Clear Pending Interrupt (non-secure)\r
+ \details Clears the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state.\r
+ \param [in] IRQn Device specific interrupt number.\r
+ \note IRQn must not be negative.\r
+ */\r
+__STATIC_INLINE void TZ_NVIC_ClearPendingIRQ_NS(IRQn_Type IRQn)\r
+{\r
+ if ((int32_t)(IRQn) >= 0)\r
+ {\r
+ NVIC_NS->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));\r
+ }\r
+}\r
+\r
+\r
+/**\r
+ \brief Get Active Interrupt (non-secure)\r
+ \details Reads the active register in non-secure NVIC when in secure state and returns the active bit for the device specific interrupt.\r
+ \param [in] IRQn Device specific interrupt number.\r
+ \return 0 Interrupt status is not active.\r
+ \return 1 Interrupt status is active.\r
+ \note IRQn must not be negative.\r
+ */\r
+__STATIC_INLINE uint32_t TZ_NVIC_GetActive_NS(IRQn_Type IRQn)\r
+{\r
+ if ((int32_t)(IRQn) >= 0)\r
+ {\r
+ return((uint32_t)(((NVIC_NS->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));\r
+ }\r
+ else\r
+ {\r
+ return(0U);\r
+ }\r
+}\r
+\r
+\r
+/**\r
+ \brief Set Interrupt Priority (non-secure)\r
+ \details Sets the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state.\r
+ The interrupt number can be positive to specify a device specific interrupt,\r
+ or negative to specify a processor exception.\r
+ \param [in] IRQn Interrupt number.\r
+ \param [in] priority Priority to set.\r
+ \note The priority cannot be set for every non-secure processor exception.\r
+ */\r
+__STATIC_INLINE void TZ_NVIC_SetPriority_NS(IRQn_Type IRQn, uint32_t priority)\r
+{\r
+ if ((int32_t)(IRQn) >= 0)\r
+ {\r
+ NVIC_NS->IPR[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);\r
+ }\r
+ else\r
+ {\r
+ SCB_NS->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);\r
+ }\r
+}\r
+\r
+\r
+/**\r
+ \brief Get Interrupt Priority (non-secure)\r
+ \details Reads the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state.\r
+ The interrupt number can be positive to specify a device specific interrupt,\r
+ or negative to specify a processor exception.\r
+ \param [in] IRQn Interrupt number.\r
+ \return Interrupt Priority. Value is aligned automatically to the implemented priority bits of the microcontroller.\r
+ */\r
+__STATIC_INLINE uint32_t TZ_NVIC_GetPriority_NS(IRQn_Type IRQn)\r
+{\r
+\r
+ if ((int32_t)(IRQn) >= 0)\r
+ {\r
+ return(((uint32_t)NVIC_NS->IPR[((uint32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS)));\r
+ }\r
+ else\r
+ {\r
+ return(((uint32_t)SCB_NS->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS)));\r
+ }\r
+}\r
+#endif /* defined (__ARM_FEATURE_CMSE) &&(__ARM_FEATURE_CMSE == 3U) */\r
+\r
+/*@} end of CMSIS_Core_NVICFunctions */\r
+\r
+/* ########################## MPU functions #################################### */\r
+\r
+#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)\r
+\r
+#include "mpu_armv8.h"\r
+\r
+#endif\r
+\r
+/* ########################## FPU functions #################################### */\r
+/**\r
+ \ingroup CMSIS_Core_FunctionInterface\r
+ \defgroup CMSIS_Core_FpuFunctions FPU Functions\r
+ \brief Function that provides FPU type.\r
+ @{\r
+ */\r
+\r
+/**\r
+ \brief get FPU type\r
+ \details returns the FPU type\r
+ \returns\r
+ - \b 0: No FPU\r
+ - \b 1: Single precision FPU\r
+ - \b 2: Double + Single precision FPU\r
+ */\r
+__STATIC_INLINE uint32_t SCB_GetFPUType(void)\r
+{\r
+ uint32_t mvfr0;\r
+\r
+ mvfr0 = FPU->MVFR0;\r
+ if ((mvfr0 & (FPU_MVFR0_Single_precision_Msk | FPU_MVFR0_Double_precision_Msk)) == 0x220U)\r
+ {\r
+ return 2U; /* Double + Single precision FPU */\r
+ }\r
+ else if ((mvfr0 & (FPU_MVFR0_Single_precision_Msk | FPU_MVFR0_Double_precision_Msk)) == 0x020U)\r
+ {\r
+ return 1U; /* Single precision FPU */\r
+ }\r
+ else\r
+ {\r
+ return 0U; /* No FPU */\r
+ }\r
+}\r
+\r
+\r
+/*@} end of CMSIS_Core_FpuFunctions */\r
+\r
+\r
+\r
+/* ########################## SAU functions #################################### */\r
+/**\r
+ \ingroup CMSIS_Core_FunctionInterface\r
+ \defgroup CMSIS_Core_SAUFunctions SAU Functions\r
+ \brief Functions that configure the SAU.\r
+ @{\r
+ */\r
+\r
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)\r
+\r
+/**\r
+ \brief Enable SAU\r
+ \details Enables the Security Attribution Unit (SAU).\r
+ */\r
+__STATIC_INLINE void TZ_SAU_Enable(void)\r
+{\r
+ SAU->CTRL |= (SAU_CTRL_ENABLE_Msk);\r
+}\r
+\r
+\r
+\r
+/**\r
+ \brief Disable SAU\r
+ \details Disables the Security Attribution Unit (SAU).\r
+ */\r
+__STATIC_INLINE void TZ_SAU_Disable(void)\r
+{\r
+ SAU->CTRL &= ~(SAU_CTRL_ENABLE_Msk);\r
+}\r
+\r
+#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */\r
+\r
+/*@} end of CMSIS_Core_SAUFunctions */\r
+\r
+\r
+\r
+\r
+/* ################################## SysTick function ############################################ */\r
+/**\r
+ \ingroup CMSIS_Core_FunctionInterface\r
+ \defgroup CMSIS_Core_SysTickFunctions SysTick Functions\r
+ \brief Functions that configure the System.\r
+ @{\r
+ */\r
+\r
+#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U)\r
+\r
+/**\r
+ \brief System Tick Configuration\r
+ \details Initializes the System Timer and its interrupt, and starts the System Tick Timer.\r
+ Counter is in free running mode to generate periodic interrupts.\r
+ \param [in] ticks Number of ticks between two interrupts.\r
+ \return 0 Function succeeded.\r
+ \return 1 Function failed.\r
+ \note When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the\r
+ function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>\r
+ must contain a vendor-specific implementation of this function.\r
+ */\r
+__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)\r
+{\r
+ if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk)\r
+ {\r
+ return (1UL); /* Reload value impossible */\r
+ }\r
+\r
+ SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */\r
+ NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */\r
+ SysTick->VAL = 0UL; /* Load the SysTick Counter Value */\r
+ SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk |\r
+ SysTick_CTRL_TICKINT_Msk |\r
+ SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */\r
+ return (0UL); /* Function successful */\r
+}\r
+\r
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)\r
+/**\r
+ \brief System Tick Configuration (non-secure)\r
+ \details Initializes the non-secure System Timer and its interrupt when in secure state, and starts the System Tick Timer.\r
+ Counter is in free running mode to generate periodic interrupts.\r
+ \param [in] ticks Number of ticks between two interrupts.\r
+ \return 0 Function succeeded.\r
+ \return 1 Function failed.\r
+ \note When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the\r
+ function <b>TZ_SysTick_Config_NS</b> is not included. In this case, the file <b><i>device</i>.h</b>\r
+ must contain a vendor-specific implementation of this function.\r
+\r
+ */\r
+__STATIC_INLINE uint32_t TZ_SysTick_Config_NS(uint32_t ticks)\r
+{\r
+ if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk)\r
+ {\r
+ return (1UL); /* Reload value impossible */\r
+ }\r
+\r
+ SysTick_NS->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */\r
+ TZ_NVIC_SetPriority_NS (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */\r
+ SysTick_NS->VAL = 0UL; /* Load the SysTick Counter Value */\r
+ SysTick_NS->CTRL = SysTick_CTRL_CLKSOURCE_Msk |\r
+ SysTick_CTRL_TICKINT_Msk |\r
+ SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */\r
+ return (0UL); /* Function successful */\r
+}\r
+#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */\r
+\r
+#endif\r
+\r
+/*@} end of CMSIS_Core_SysTickFunctions */\r
+\r
+\r
+\r
+/* ##################################### Debug In/Output function ########################################### */\r
+/**\r
+ \ingroup CMSIS_Core_FunctionInterface\r
+ \defgroup CMSIS_core_DebugFunctions ITM Functions\r
+ \brief Functions that access the ITM debug interface.\r
+ @{\r
+ */\r
+\r
+extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters. */\r
+#define ITM_RXBUFFER_EMPTY ((int32_t)0x5AA55AA5U) /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */\r
+\r
+\r
+/**\r
+ \brief ITM Send Character\r
+ \details Transmits a character via the ITM channel 0, and\r
+ \li Just returns when no debugger is connected that has booked the output.\r
+ \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted.\r
+ \param [in] ch Character to transmit.\r
+ \returns Character to transmit.\r
+ */\r
+__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch)\r
+{\r
+ if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) && /* ITM enabled */\r
+ ((ITM->TER & 1UL ) != 0UL) ) /* ITM Port #0 enabled */\r
+ {\r
+ while (ITM->PORT[0U].u32 == 0UL)\r
+ {\r
+ __NOP();\r
+ }\r
+ ITM->PORT[0U].u8 = (uint8_t)ch;\r
+ }\r
+ return (ch);\r
+}\r
+\r
+\r
+/**\r
+ \brief ITM Receive Character\r
+ \details Inputs a character via the external variable \ref ITM_RxBuffer.\r
+ \return Received character.\r
+ \return -1 No character pending.\r
+ */\r
+__STATIC_INLINE int32_t ITM_ReceiveChar (void)\r
+{\r
+ int32_t ch = -1; /* no character available */\r
+\r
+ if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY)\r
+ {\r
+ ch = ITM_RxBuffer;\r
+ ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */\r
+ }\r
+\r
+ return (ch);\r
+}\r
+\r
+\r
+/**\r
+ \brief ITM Check Character\r
+ \details Checks whether a character is pending for reading in the variable \ref ITM_RxBuffer.\r
+ \return 0 No character available.\r
+ \return 1 Character available.\r
+ */\r
+__STATIC_INLINE int32_t ITM_CheckChar (void)\r
+{\r
+\r
+ if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY)\r
+ {\r
+ return (0); /* no character available */\r
+ }\r
+ else\r
+ {\r
+ return (1); /* character available */\r
+ }\r
+}\r
+\r
+/*@} end of CMSIS_core_DebugFunctions */\r
+\r
+\r
+\r
+\r
+#ifdef __cplusplus\r
+}\r
+#endif\r
+\r
+#endif /* __CORE_CM33_H_DEPENDANT */\r
+\r
+#endif /* __CMSIS_GENERIC */\r
--- /dev/null
+/**************************************************************************//**\r
+ * @file core_cm4.h\r
+ * @brief CMSIS Cortex-M4 Core Peripheral Access Layer Header File\r
+ * @version V5.0.8\r
+ * @date 04. June 2018\r
+ ******************************************************************************/\r
+/*\r
+ * Copyright (c) 2009-2018 Arm Limited. All rights reserved.\r
+ *\r
+ * SPDX-License-Identifier: Apache-2.0\r
+ *\r
+ * Licensed under the Apache License, Version 2.0 (the License); you may\r
+ * not use this file except in compliance with the License.\r
+ * You may obtain a copy of the License at\r
+ *\r
+ * www.apache.org/licenses/LICENSE-2.0\r
+ *\r
+ * Unless required by applicable law or agreed to in writing, software\r
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT\r
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\r
+ * See the License for the specific language governing permissions and\r
+ * limitations under the License.\r
+ */\r
+\r
+#if defined ( __ICCARM__ )\r
+ #pragma system_include /* treat file as system include file for MISRA check */\r
+#elif defined (__clang__)\r
+ #pragma clang system_header /* treat file as system include file */\r
+#endif\r
+\r
+#ifndef __CORE_CM4_H_GENERIC\r
+#define __CORE_CM4_H_GENERIC\r
+\r
+#include <stdint.h>\r
+\r
+#ifdef __cplusplus\r
+ extern "C" {\r
+#endif\r
+\r
+/**\r
+ \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions\r
+ CMSIS violates the following MISRA-C:2004 rules:\r
+\r
+ \li Required Rule 8.5, object/function definition in header file.<br>\r
+ Function definitions in header files are used to allow 'inlining'.\r
+\r
+ \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>\r
+ Unions are used for effective representation of core registers.\r
+\r
+ \li Advisory Rule 19.7, Function-like macro defined.<br>\r
+ Function-like macros are used to allow more efficient code.\r
+ */\r
+\r
+\r
+/*******************************************************************************\r
+ * CMSIS definitions\r
+ ******************************************************************************/\r
+/**\r
+ \ingroup Cortex_M4\r
+ @{\r
+ */\r
+\r
+#include "cmsis_version.h"\r
+\r
+/* CMSIS CM4 definitions */\r
+#define __CM4_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */\r
+#define __CM4_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */\r
+#define __CM4_CMSIS_VERSION ((__CM4_CMSIS_VERSION_MAIN << 16U) | \\r
+ __CM4_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */\r
+\r
+#define __CORTEX_M (4U) /*!< Cortex-M Core */\r
+\r
+/** __FPU_USED indicates whether an FPU is used or not.\r
+ For this, __FPU_PRESENT has to be checked prior to making use of FPU specific registers and functions.\r
+*/\r
+#if defined ( __CC_ARM )\r
+ #if defined __TARGET_FPU_VFP\r
+ #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)\r
+ #define __FPU_USED 1U\r
+ #else\r
+ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"\r
+ #define __FPU_USED 0U\r
+ #endif\r
+ #else\r
+ #define __FPU_USED 0U\r
+ #endif\r
+\r
+#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)\r
+ #if defined __ARM_PCS_VFP\r
+ #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)\r
+ #define __FPU_USED 1U\r
+ #else\r
+ #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"\r
+ #define __FPU_USED 0U\r
+ #endif\r
+ #else\r
+ #define __FPU_USED 0U\r
+ #endif\r
+\r
+#elif defined ( __GNUC__ )\r
+ #if defined (__VFP_FP__) && !defined(__SOFTFP__)\r
+ #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)\r
+ #define __FPU_USED 1U\r
+ #else\r
+ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"\r
+ #define __FPU_USED 0U\r
+ #endif\r
+ #else\r
+ #define __FPU_USED 0U\r
+ #endif\r
+\r
+#elif defined ( __ICCARM__ )\r
+ #if defined __ARMVFP__\r
+ #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)\r
+ #define __FPU_USED 1U\r
+ #else\r
+ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"\r
+ #define __FPU_USED 0U\r
+ #endif\r
+ #else\r
+ #define __FPU_USED 0U\r
+ #endif\r
+\r
+#elif defined ( __TI_ARM__ )\r
+ #if defined __TI_VFP_SUPPORT__\r
+ #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)\r
+ #define __FPU_USED 1U\r
+ #else\r
+ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"\r
+ #define __FPU_USED 0U\r
+ #endif\r
+ #else\r
+ #define __FPU_USED 0U\r
+ #endif\r
+\r
+#elif defined ( __TASKING__ )\r
+ #if defined __FPU_VFP__\r
+ #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)\r
+ #define __FPU_USED 1U\r
+ #else\r
+ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"\r
+ #define __FPU_USED 0U\r
+ #endif\r
+ #else\r
+ #define __FPU_USED 0U\r
+ #endif\r
+\r
+#elif defined ( __CSMC__ )\r
+ #if ( __CSMC__ & 0x400U)\r
+ #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)\r
+ #define __FPU_USED 1U\r
+ #else\r
+ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"\r
+ #define __FPU_USED 0U\r
+ #endif\r
+ #else\r
+ #define __FPU_USED 0U\r
+ #endif\r
+\r
+#endif\r
+\r
+#include "cmsis_compiler.h" /* CMSIS compiler specific defines */\r
+\r
+\r
+#ifdef __cplusplus\r
+}\r
+#endif\r
+\r
+#endif /* __CORE_CM4_H_GENERIC */\r
+\r
+#ifndef __CMSIS_GENERIC\r
+\r
+#ifndef __CORE_CM4_H_DEPENDANT\r
+#define __CORE_CM4_H_DEPENDANT\r
+\r
+#ifdef __cplusplus\r
+ extern "C" {\r
+#endif\r
+\r
+/* check device defines and use defaults */\r
+#if defined __CHECK_DEVICE_DEFINES\r
+ #ifndef __CM4_REV\r
+ #define __CM4_REV 0x0000U\r
+ #warning "__CM4_REV not defined in device header file; using default!"\r
+ #endif\r
+\r
+ #ifndef __FPU_PRESENT\r
+ #define __FPU_PRESENT 0U\r
+ #warning "__FPU_PRESENT not defined in device header file; using default!"\r
+ #endif\r
+\r
+ #ifndef __MPU_PRESENT\r
+ #define __MPU_PRESENT 0U\r
+ #warning "__MPU_PRESENT not defined in device header file; using default!"\r
+ #endif\r
+\r
+ #ifndef __NVIC_PRIO_BITS\r
+ #define __NVIC_PRIO_BITS 3U\r
+ #warning "__NVIC_PRIO_BITS not defined in device header file; using default!"\r
+ #endif\r
+\r
+ #ifndef __Vendor_SysTickConfig\r
+ #define __Vendor_SysTickConfig 0U\r
+ #warning "__Vendor_SysTickConfig not defined in device header file; using default!"\r
+ #endif\r
+#endif\r
+\r
+/* IO definitions (access restrictions to peripheral registers) */\r
+/**\r
+ \defgroup CMSIS_glob_defs CMSIS Global Defines\r
+\r
+ <strong>IO Type Qualifiers</strong> are used\r
+ \li to specify the access to peripheral variables.\r
+ \li for automatic generation of peripheral register debug information.\r
+*/\r
+#ifdef __cplusplus\r
+ #define __I volatile /*!< Defines 'read only' permissions */\r
+#else\r
+ #define __I volatile const /*!< Defines 'read only' permissions */\r
+#endif\r
+#define __O volatile /*!< Defines 'write only' permissions */\r
+#define __IO volatile /*!< Defines 'read / write' permissions */\r
+\r
+/* following defines should be used for structure members */\r
+#define __IM volatile const /*! Defines 'read only' structure member permissions */\r
+#define __OM volatile /*! Defines 'write only' structure member permissions */\r
+#define __IOM volatile /*! Defines 'read / write' structure member permissions */\r
+\r
+/*@} end of group Cortex_M4 */\r
+\r
+\r
+\r
+/*******************************************************************************\r
+ * Register Abstraction\r
+ Core Register contain:\r
+ - Core Register\r
+ - Core NVIC Register\r
+ - Core SCB Register\r
+ - Core SysTick Register\r
+ - Core Debug Register\r
+ - Core MPU Register\r
+ - Core FPU Register\r
+ ******************************************************************************/\r
+/**\r
+ \defgroup CMSIS_core_register Defines and Type Definitions\r
+ \brief Type definitions and defines for Cortex-M processor based devices.\r
+*/\r
+\r
+/**\r
+ \ingroup CMSIS_core_register\r
+ \defgroup CMSIS_CORE Status and Control Registers\r
+ \brief Core Register type definitions.\r
+ @{\r
+ */\r
+\r
+/**\r
+ \brief Union type to access the Application Program Status Register (APSR).\r
+ */\r
+typedef union\r
+{\r
+ struct\r
+ {\r
+ uint32_t _reserved0:16; /*!< bit: 0..15 Reserved */\r
+ uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */\r
+ uint32_t _reserved1:7; /*!< bit: 20..26 Reserved */\r
+ uint32_t Q:1; /*!< bit: 27 Saturation condition flag */\r
+ uint32_t V:1; /*!< bit: 28 Overflow condition code flag */\r
+ uint32_t C:1; /*!< bit: 29 Carry condition code flag */\r
+ uint32_t Z:1; /*!< bit: 30 Zero condition code flag */\r
+ uint32_t N:1; /*!< bit: 31 Negative condition code flag */\r
+ } b; /*!< Structure used for bit access */\r
+ uint32_t w; /*!< Type used for word access */\r
+} APSR_Type;\r
+\r
+/* APSR Register Definitions */\r
+#define APSR_N_Pos 31U /*!< APSR: N Position */\r
+#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */\r
+\r
+#define APSR_Z_Pos 30U /*!< APSR: Z Position */\r
+#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */\r
+\r
+#define APSR_C_Pos 29U /*!< APSR: C Position */\r
+#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */\r
+\r
+#define APSR_V_Pos 28U /*!< APSR: V Position */\r
+#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */\r
+\r
+#define APSR_Q_Pos 27U /*!< APSR: Q Position */\r
+#define APSR_Q_Msk (1UL << APSR_Q_Pos) /*!< APSR: Q Mask */\r
+\r
+#define APSR_GE_Pos 16U /*!< APSR: GE Position */\r
+#define APSR_GE_Msk (0xFUL << APSR_GE_Pos) /*!< APSR: GE Mask */\r
+\r
+\r
+/**\r
+ \brief Union type to access the Interrupt Program Status Register (IPSR).\r
+ */\r
+typedef union\r
+{\r
+ struct\r
+ {\r
+ uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */\r
+ uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */\r
+ } b; /*!< Structure used for bit access */\r
+ uint32_t w; /*!< Type used for word access */\r
+} IPSR_Type;\r
+\r
+/* IPSR Register Definitions */\r
+#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */\r
+#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */\r
+\r
+\r
+/**\r
+ \brief Union type to access the Special-Purpose Program Status Registers (xPSR).\r
+ */\r
+typedef union\r
+{\r
+ struct\r
+ {\r
+ uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */\r
+ uint32_t _reserved0:1; /*!< bit: 9 Reserved */\r
+ uint32_t ICI_IT_1:6; /*!< bit: 10..15 ICI/IT part 1 */\r
+ uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */\r
+ uint32_t _reserved1:4; /*!< bit: 20..23 Reserved */\r
+ uint32_t T:1; /*!< bit: 24 Thumb bit */\r
+ uint32_t ICI_IT_2:2; /*!< bit: 25..26 ICI/IT part 2 */\r
+ uint32_t Q:1; /*!< bit: 27 Saturation condition flag */\r
+ uint32_t V:1; /*!< bit: 28 Overflow condition code flag */\r
+ uint32_t C:1; /*!< bit: 29 Carry condition code flag */\r
+ uint32_t Z:1; /*!< bit: 30 Zero condition code flag */\r
+ uint32_t N:1; /*!< bit: 31 Negative condition code flag */\r
+ } b; /*!< Structure used for bit access */\r
+ uint32_t w; /*!< Type used for word access */\r
+} xPSR_Type;\r
+\r
+/* xPSR Register Definitions */\r
+#define xPSR_N_Pos 31U /*!< xPSR: N Position */\r
+#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */\r
+\r
+#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */\r
+#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */\r
+\r
+#define xPSR_C_Pos 29U /*!< xPSR: C Position */\r
+#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */\r
+\r
+#define xPSR_V_Pos 28U /*!< xPSR: V Position */\r
+#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */\r
+\r
+#define xPSR_Q_Pos 27U /*!< xPSR: Q Position */\r
+#define xPSR_Q_Msk (1UL << xPSR_Q_Pos) /*!< xPSR: Q Mask */\r
+\r
+#define xPSR_ICI_IT_2_Pos 25U /*!< xPSR: ICI/IT part 2 Position */\r
+#define xPSR_ICI_IT_2_Msk (3UL << xPSR_ICI_IT_2_Pos) /*!< xPSR: ICI/IT part 2 Mask */\r
+\r
+#define xPSR_T_Pos 24U /*!< xPSR: T Position */\r
+#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */\r
+\r
+#define xPSR_GE_Pos 16U /*!< xPSR: GE Position */\r
+#define xPSR_GE_Msk (0xFUL << xPSR_GE_Pos) /*!< xPSR: GE Mask */\r
+\r
+#define xPSR_ICI_IT_1_Pos 10U /*!< xPSR: ICI/IT part 1 Position */\r
+#define xPSR_ICI_IT_1_Msk (0x3FUL << xPSR_ICI_IT_1_Pos) /*!< xPSR: ICI/IT part 1 Mask */\r
+\r
+#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */\r
+#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */\r
+\r
+\r
+/**\r
+ \brief Union type to access the Control Registers (CONTROL).\r
+ */\r
+typedef union\r
+{\r
+ struct\r
+ {\r
+ uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */\r
+ uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */\r
+ uint32_t FPCA:1; /*!< bit: 2 FP extension active flag */\r
+ uint32_t _reserved0:29; /*!< bit: 3..31 Reserved */\r
+ } b; /*!< Structure used for bit access */\r
+ uint32_t w; /*!< Type used for word access */\r
+} CONTROL_Type;\r
+\r
+/* CONTROL Register Definitions */\r
+#define CONTROL_FPCA_Pos 2U /*!< CONTROL: FPCA Position */\r
+#define CONTROL_FPCA_Msk (1UL << CONTROL_FPCA_Pos) /*!< CONTROL: FPCA Mask */\r
+\r
+#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */\r
+#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */\r
+\r
+#define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */\r
+#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */\r
+\r
+/*@} end of group CMSIS_CORE */\r
+\r
+\r
+/**\r
+ \ingroup CMSIS_core_register\r
+ \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC)\r
+ \brief Type definitions for the NVIC Registers\r
+ @{\r
+ */\r
+\r
+/**\r
+ \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC).\r
+ */\r
+typedef struct\r
+{\r
+ __IOM uint32_t ISER[8U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */\r
+ uint32_t RESERVED0[24U];\r
+ __IOM uint32_t ICER[8U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */\r
+ uint32_t RSERVED1[24U];\r
+ __IOM uint32_t ISPR[8U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */\r
+ uint32_t RESERVED2[24U];\r
+ __IOM uint32_t ICPR[8U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */\r
+ uint32_t RESERVED3[24U];\r
+ __IOM uint32_t IABR[8U]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */\r
+ uint32_t RESERVED4[56U];\r
+ __IOM uint8_t IP[240U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */\r
+ uint32_t RESERVED5[644U];\r
+ __OM uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */\r
+} NVIC_Type;\r
+\r
+/* Software Triggered Interrupt Register Definitions */\r
+#define NVIC_STIR_INTID_Pos 0U /*!< STIR: INTLINESNUM Position */\r
+#define NVIC_STIR_INTID_Msk (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/) /*!< STIR: INTLINESNUM Mask */\r
+\r
+/*@} end of group CMSIS_NVIC */\r
+\r
+\r
+/**\r
+ \ingroup CMSIS_core_register\r
+ \defgroup CMSIS_SCB System Control Block (SCB)\r
+ \brief Type definitions for the System Control Block Registers\r
+ @{\r
+ */\r
+\r
+/**\r
+ \brief Structure type to access the System Control Block (SCB).\r
+ */\r
+typedef struct\r
+{\r
+ __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */\r
+ __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */\r
+ __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */\r
+ __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */\r
+ __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */\r
+ __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */\r
+ __IOM uint8_t SHP[12U]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */\r
+ __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */\r
+ __IOM uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */\r
+ __IOM uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */\r
+ __IOM uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */\r
+ __IOM uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */\r
+ __IOM uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */\r
+ __IOM uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */\r
+ __IM uint32_t PFR[2U]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */\r
+ __IM uint32_t DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */\r
+ __IM uint32_t ADR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */\r
+ __IM uint32_t MMFR[4U]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */\r
+ __IM uint32_t ISAR[5U]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */\r
+ uint32_t RESERVED0[5U];\r
+ __IOM uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */\r
+} SCB_Type;\r
+\r
+/* SCB CPUID Register Definitions */\r
+#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */\r
+#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */\r
+\r
+#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */\r
+#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */\r
+\r
+#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */\r
+#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */\r
+\r
+#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */\r
+#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */\r
+\r
+#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */\r
+#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */\r
+\r
+/* SCB Interrupt Control State Register Definitions */\r
+#define SCB_ICSR_NMIPENDSET_Pos 31U /*!< SCB ICSR: NMIPENDSET Position */\r
+#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */\r
+\r
+#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */\r
+#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */\r
+\r
+#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */\r
+#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */\r
+\r
+#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */\r
+#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */\r
+\r
+#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */\r
+#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */\r
+\r
+#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */\r
+#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */\r
+\r
+#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */\r
+#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */\r
+\r
+#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */\r
+#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */\r
+\r
+#define SCB_ICSR_RETTOBASE_Pos 11U /*!< SCB ICSR: RETTOBASE Position */\r
+#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */\r
+\r
+#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */\r
+#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */\r
+\r
+/* SCB Vector Table Offset Register Definitions */\r
+#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */\r
+#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */\r
+\r
+/* SCB Application Interrupt and Reset Control Register Definitions */\r
+#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */\r
+#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */\r
+\r
+#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */\r
+#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */\r
+\r
+#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */\r
+#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */\r
+\r
+#define SCB_AIRCR_PRIGROUP_Pos 8U /*!< SCB AIRCR: PRIGROUP Position */\r
+#define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */\r
+\r
+#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */\r
+#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */\r
+\r
+#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */\r
+#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */\r
+\r
+#define SCB_AIRCR_VECTRESET_Pos 0U /*!< SCB AIRCR: VECTRESET Position */\r
+#define SCB_AIRCR_VECTRESET_Msk (1UL /*<< SCB_AIRCR_VECTRESET_Pos*/) /*!< SCB AIRCR: VECTRESET Mask */\r
+\r
+/* SCB System Control Register Definitions */\r
+#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */\r
+#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */\r
+\r
+#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */\r
+#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */\r
+\r
+#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */\r
+#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */\r
+\r
+/* SCB Configuration Control Register Definitions */\r
+#define SCB_CCR_STKALIGN_Pos 9U /*!< SCB CCR: STKALIGN Position */\r
+#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */\r
+\r
+#define SCB_CCR_BFHFNMIGN_Pos 8U /*!< SCB CCR: BFHFNMIGN Position */\r
+#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */\r
+\r
+#define SCB_CCR_DIV_0_TRP_Pos 4U /*!< SCB CCR: DIV_0_TRP Position */\r
+#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */\r
+\r
+#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */\r
+#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */\r
+\r
+#define SCB_CCR_USERSETMPEND_Pos 1U /*!< SCB CCR: USERSETMPEND Position */\r
+#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */\r
+\r
+#define SCB_CCR_NONBASETHRDENA_Pos 0U /*!< SCB CCR: NONBASETHRDENA Position */\r
+#define SCB_CCR_NONBASETHRDENA_Msk (1UL /*<< SCB_CCR_NONBASETHRDENA_Pos*/) /*!< SCB CCR: NONBASETHRDENA Mask */\r
+\r
+/* SCB System Handler Control and State Register Definitions */\r
+#define SCB_SHCSR_USGFAULTENA_Pos 18U /*!< SCB SHCSR: USGFAULTENA Position */\r
+#define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */\r
+\r
+#define SCB_SHCSR_BUSFAULTENA_Pos 17U /*!< SCB SHCSR: BUSFAULTENA Position */\r
+#define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */\r
+\r
+#define SCB_SHCSR_MEMFAULTENA_Pos 16U /*!< SCB SHCSR: MEMFAULTENA Position */\r
+#define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */\r
+\r
+#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */\r
+#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */\r
+\r
+#define SCB_SHCSR_BUSFAULTPENDED_Pos 14U /*!< SCB SHCSR: BUSFAULTPENDED Position */\r
+#define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */\r
+\r
+#define SCB_SHCSR_MEMFAULTPENDED_Pos 13U /*!< SCB SHCSR: MEMFAULTPENDED Position */\r
+#define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */\r
+\r
+#define SCB_SHCSR_USGFAULTPENDED_Pos 12U /*!< SCB SHCSR: USGFAULTPENDED Position */\r
+#define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */\r
+\r
+#define SCB_SHCSR_SYSTICKACT_Pos 11U /*!< SCB SHCSR: SYSTICKACT Position */\r
+#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */\r
+\r
+#define SCB_SHCSR_PENDSVACT_Pos 10U /*!< SCB SHCSR: PENDSVACT Position */\r
+#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */\r
+\r
+#define SCB_SHCSR_MONITORACT_Pos 8U /*!< SCB SHCSR: MONITORACT Position */\r
+#define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */\r
+\r
+#define SCB_SHCSR_SVCALLACT_Pos 7U /*!< SCB SHCSR: SVCALLACT Position */\r
+#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */\r
+\r
+#define SCB_SHCSR_USGFAULTACT_Pos 3U /*!< SCB SHCSR: USGFAULTACT Position */\r
+#define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */\r
+\r
+#define SCB_SHCSR_BUSFAULTACT_Pos 1U /*!< SCB SHCSR: BUSFAULTACT Position */\r
+#define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */\r
+\r
+#define SCB_SHCSR_MEMFAULTACT_Pos 0U /*!< SCB SHCSR: MEMFAULTACT Position */\r
+#define SCB_SHCSR_MEMFAULTACT_Msk (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/) /*!< SCB SHCSR: MEMFAULTACT Mask */\r
+\r
+/* SCB Configurable Fault Status Register Definitions */\r
+#define SCB_CFSR_USGFAULTSR_Pos 16U /*!< SCB CFSR: Usage Fault Status Register Position */\r
+#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */\r
+\r
+#define SCB_CFSR_BUSFAULTSR_Pos 8U /*!< SCB CFSR: Bus Fault Status Register Position */\r
+#define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */\r
+\r
+#define SCB_CFSR_MEMFAULTSR_Pos 0U /*!< SCB CFSR: Memory Manage Fault Status Register Position */\r
+#define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */\r
+\r
+/* MemManage Fault Status Register (part of SCB Configurable Fault Status Register) */\r
+#define SCB_CFSR_MMARVALID_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 7U) /*!< SCB CFSR (MMFSR): MMARVALID Position */\r
+#define SCB_CFSR_MMARVALID_Msk (1UL << SCB_CFSR_MMARVALID_Pos) /*!< SCB CFSR (MMFSR): MMARVALID Mask */\r
+\r
+#define SCB_CFSR_MLSPERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 5U) /*!< SCB CFSR (MMFSR): MLSPERR Position */\r
+#define SCB_CFSR_MLSPERR_Msk (1UL << SCB_CFSR_MLSPERR_Pos) /*!< SCB CFSR (MMFSR): MLSPERR Mask */\r
+\r
+#define SCB_CFSR_MSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 4U) /*!< SCB CFSR (MMFSR): MSTKERR Position */\r
+#define SCB_CFSR_MSTKERR_Msk (1UL << SCB_CFSR_MSTKERR_Pos) /*!< SCB CFSR (MMFSR): MSTKERR Mask */\r
+\r
+#define SCB_CFSR_MUNSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 3U) /*!< SCB CFSR (MMFSR): MUNSTKERR Position */\r
+#define SCB_CFSR_MUNSTKERR_Msk (1UL << SCB_CFSR_MUNSTKERR_Pos) /*!< SCB CFSR (MMFSR): MUNSTKERR Mask */\r
+\r
+#define SCB_CFSR_DACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 1U) /*!< SCB CFSR (MMFSR): DACCVIOL Position */\r
+#define SCB_CFSR_DACCVIOL_Msk (1UL << SCB_CFSR_DACCVIOL_Pos) /*!< SCB CFSR (MMFSR): DACCVIOL Mask */\r
+\r
+#define SCB_CFSR_IACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 0U) /*!< SCB CFSR (MMFSR): IACCVIOL Position */\r
+#define SCB_CFSR_IACCVIOL_Msk (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/) /*!< SCB CFSR (MMFSR): IACCVIOL Mask */\r
+\r
+/* BusFault Status Register (part of SCB Configurable Fault Status Register) */\r
+#define SCB_CFSR_BFARVALID_Pos (SCB_CFSR_BUSFAULTSR_Pos + 7U) /*!< SCB CFSR (BFSR): BFARVALID Position */\r
+#define SCB_CFSR_BFARVALID_Msk (1UL << SCB_CFSR_BFARVALID_Pos) /*!< SCB CFSR (BFSR): BFARVALID Mask */\r
+\r
+#define SCB_CFSR_LSPERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 5U) /*!< SCB CFSR (BFSR): LSPERR Position */\r
+#define SCB_CFSR_LSPERR_Msk (1UL << SCB_CFSR_LSPERR_Pos) /*!< SCB CFSR (BFSR): LSPERR Mask */\r
+\r
+#define SCB_CFSR_STKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 4U) /*!< SCB CFSR (BFSR): STKERR Position */\r
+#define SCB_CFSR_STKERR_Msk (1UL << SCB_CFSR_STKERR_Pos) /*!< SCB CFSR (BFSR): STKERR Mask */\r
+\r
+#define SCB_CFSR_UNSTKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 3U) /*!< SCB CFSR (BFSR): UNSTKERR Position */\r
+#define SCB_CFSR_UNSTKERR_Msk (1UL << SCB_CFSR_UNSTKERR_Pos) /*!< SCB CFSR (BFSR): UNSTKERR Mask */\r
+\r
+#define SCB_CFSR_IMPRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 2U) /*!< SCB CFSR (BFSR): IMPRECISERR Position */\r
+#define SCB_CFSR_IMPRECISERR_Msk (1UL << SCB_CFSR_IMPRECISERR_Pos) /*!< SCB CFSR (BFSR): IMPRECISERR Mask */\r
+\r
+#define SCB_CFSR_PRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 1U) /*!< SCB CFSR (BFSR): PRECISERR Position */\r
+#define SCB_CFSR_PRECISERR_Msk (1UL << SCB_CFSR_PRECISERR_Pos) /*!< SCB CFSR (BFSR): PRECISERR Mask */\r
+\r
+#define SCB_CFSR_IBUSERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 0U) /*!< SCB CFSR (BFSR): IBUSERR Position */\r
+#define SCB_CFSR_IBUSERR_Msk (1UL << SCB_CFSR_IBUSERR_Pos) /*!< SCB CFSR (BFSR): IBUSERR Mask */\r
+\r
+/* UsageFault Status Register (part of SCB Configurable Fault Status Register) */\r
+#define SCB_CFSR_DIVBYZERO_Pos (SCB_CFSR_USGFAULTSR_Pos + 9U) /*!< SCB CFSR (UFSR): DIVBYZERO Position */\r
+#define SCB_CFSR_DIVBYZERO_Msk (1UL << SCB_CFSR_DIVBYZERO_Pos) /*!< SCB CFSR (UFSR): DIVBYZERO Mask */\r
+\r
+#define SCB_CFSR_UNALIGNED_Pos (SCB_CFSR_USGFAULTSR_Pos + 8U) /*!< SCB CFSR (UFSR): UNALIGNED Position */\r
+#define SCB_CFSR_UNALIGNED_Msk (1UL << SCB_CFSR_UNALIGNED_Pos) /*!< SCB CFSR (UFSR): UNALIGNED Mask */\r
+\r
+#define SCB_CFSR_NOCP_Pos (SCB_CFSR_USGFAULTSR_Pos + 3U) /*!< SCB CFSR (UFSR): NOCP Position */\r
+#define SCB_CFSR_NOCP_Msk (1UL << SCB_CFSR_NOCP_Pos) /*!< SCB CFSR (UFSR): NOCP Mask */\r
+\r
+#define SCB_CFSR_INVPC_Pos (SCB_CFSR_USGFAULTSR_Pos + 2U) /*!< SCB CFSR (UFSR): INVPC Position */\r
+#define SCB_CFSR_INVPC_Msk (1UL << SCB_CFSR_INVPC_Pos) /*!< SCB CFSR (UFSR): INVPC Mask */\r
+\r
+#define SCB_CFSR_INVSTATE_Pos (SCB_CFSR_USGFAULTSR_Pos + 1U) /*!< SCB CFSR (UFSR): INVSTATE Position */\r
+#define SCB_CFSR_INVSTATE_Msk (1UL << SCB_CFSR_INVSTATE_Pos) /*!< SCB CFSR (UFSR): INVSTATE Mask */\r
+\r
+#define SCB_CFSR_UNDEFINSTR_Pos (SCB_CFSR_USGFAULTSR_Pos + 0U) /*!< SCB CFSR (UFSR): UNDEFINSTR Position */\r
+#define SCB_CFSR_UNDEFINSTR_Msk (1UL << SCB_CFSR_UNDEFINSTR_Pos) /*!< SCB CFSR (UFSR): UNDEFINSTR Mask */\r
+\r
+/* SCB Hard Fault Status Register Definitions */\r
+#define SCB_HFSR_DEBUGEVT_Pos 31U /*!< SCB HFSR: DEBUGEVT Position */\r
+#define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */\r
+\r
+#define SCB_HFSR_FORCED_Pos 30U /*!< SCB HFSR: FORCED Position */\r
+#define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */\r
+\r
+#define SCB_HFSR_VECTTBL_Pos 1U /*!< SCB HFSR: VECTTBL Position */\r
+#define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */\r
+\r
+/* SCB Debug Fault Status Register Definitions */\r
+#define SCB_DFSR_EXTERNAL_Pos 4U /*!< SCB DFSR: EXTERNAL Position */\r
+#define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */\r
+\r
+#define SCB_DFSR_VCATCH_Pos 3U /*!< SCB DFSR: VCATCH Position */\r
+#define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */\r
+\r
+#define SCB_DFSR_DWTTRAP_Pos 2U /*!< SCB DFSR: DWTTRAP Position */\r
+#define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */\r
+\r
+#define SCB_DFSR_BKPT_Pos 1U /*!< SCB DFSR: BKPT Position */\r
+#define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */\r
+\r
+#define SCB_DFSR_HALTED_Pos 0U /*!< SCB DFSR: HALTED Position */\r
+#define SCB_DFSR_HALTED_Msk (1UL /*<< SCB_DFSR_HALTED_Pos*/) /*!< SCB DFSR: HALTED Mask */\r
+\r
+/*@} end of group CMSIS_SCB */\r
+\r
+\r
+/**\r
+ \ingroup CMSIS_core_register\r
+ \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB)\r
+ \brief Type definitions for the System Control and ID Register not in the SCB\r
+ @{\r
+ */\r
+\r
+/**\r
+ \brief Structure type to access the System Control and ID Register not in the SCB.\r
+ */\r
+typedef struct\r
+{\r
+ uint32_t RESERVED0[1U];\r
+ __IM uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */\r
+ __IOM uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */\r
+} SCnSCB_Type;\r
+\r
+/* Interrupt Controller Type Register Definitions */\r
+#define SCnSCB_ICTR_INTLINESNUM_Pos 0U /*!< ICTR: INTLINESNUM Position */\r
+#define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/) /*!< ICTR: INTLINESNUM Mask */\r
+\r
+/* Auxiliary Control Register Definitions */\r
+#define SCnSCB_ACTLR_DISOOFP_Pos 9U /*!< ACTLR: DISOOFP Position */\r
+#define SCnSCB_ACTLR_DISOOFP_Msk (1UL << SCnSCB_ACTLR_DISOOFP_Pos) /*!< ACTLR: DISOOFP Mask */\r
+\r
+#define SCnSCB_ACTLR_DISFPCA_Pos 8U /*!< ACTLR: DISFPCA Position */\r
+#define SCnSCB_ACTLR_DISFPCA_Msk (1UL << SCnSCB_ACTLR_DISFPCA_Pos) /*!< ACTLR: DISFPCA Mask */\r
+\r
+#define SCnSCB_ACTLR_DISFOLD_Pos 2U /*!< ACTLR: DISFOLD Position */\r
+#define SCnSCB_ACTLR_DISFOLD_Msk (1UL << SCnSCB_ACTLR_DISFOLD_Pos) /*!< ACTLR: DISFOLD Mask */\r
+\r
+#define SCnSCB_ACTLR_DISDEFWBUF_Pos 1U /*!< ACTLR: DISDEFWBUF Position */\r
+#define SCnSCB_ACTLR_DISDEFWBUF_Msk (1UL << SCnSCB_ACTLR_DISDEFWBUF_Pos) /*!< ACTLR: DISDEFWBUF Mask */\r
+\r
+#define SCnSCB_ACTLR_DISMCYCINT_Pos 0U /*!< ACTLR: DISMCYCINT Position */\r
+#define SCnSCB_ACTLR_DISMCYCINT_Msk (1UL /*<< SCnSCB_ACTLR_DISMCYCINT_Pos*/) /*!< ACTLR: DISMCYCINT Mask */\r
+\r
+/*@} end of group CMSIS_SCnotSCB */\r
+\r
+\r
+/**\r
+ \ingroup CMSIS_core_register\r
+ \defgroup CMSIS_SysTick System Tick Timer (SysTick)\r
+ \brief Type definitions for the System Timer Registers.\r
+ @{\r
+ */\r
+\r
+/**\r
+ \brief Structure type to access the System Timer (SysTick).\r
+ */\r
+typedef struct\r
+{\r
+ __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */\r
+ __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */\r
+ __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */\r
+ __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */\r
+} SysTick_Type;\r
+\r
+/* SysTick Control / Status Register Definitions */\r
+#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */\r
+#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */\r
+\r
+#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */\r
+#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */\r
+\r
+#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */\r
+#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */\r
+\r
+#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */\r
+#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */\r
+\r
+/* SysTick Reload Register Definitions */\r
+#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */\r
+#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */\r
+\r
+/* SysTick Current Register Definitions */\r
+#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */\r
+#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */\r
+\r
+/* SysTick Calibration Register Definitions */\r
+#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */\r
+#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */\r
+\r
+#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */\r
+#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */\r
+\r
+#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */\r
+#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */\r
+\r
+/*@} end of group CMSIS_SysTick */\r
+\r
+\r
+/**\r
+ \ingroup CMSIS_core_register\r
+ \defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM)\r
+ \brief Type definitions for the Instrumentation Trace Macrocell (ITM)\r
+ @{\r
+ */\r
+\r
+/**\r
+ \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM).\r
+ */\r
+typedef struct\r
+{\r
+ __OM union\r
+ {\r
+ __OM uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */\r
+ __OM uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */\r
+ __OM uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */\r
+ } PORT [32U]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */\r
+ uint32_t RESERVED0[864U];\r
+ __IOM uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */\r
+ uint32_t RESERVED1[15U];\r
+ __IOM uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */\r
+ uint32_t RESERVED2[15U];\r
+ __IOM uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */\r
+ uint32_t RESERVED3[29U];\r
+ __OM uint32_t IWR; /*!< Offset: 0xEF8 ( /W) ITM Integration Write Register */\r
+ __IM uint32_t IRR; /*!< Offset: 0xEFC (R/ ) ITM Integration Read Register */\r
+ __IOM uint32_t IMCR; /*!< Offset: 0xF00 (R/W) ITM Integration Mode Control Register */\r
+ uint32_t RESERVED4[43U];\r
+ __OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */\r
+ __IM uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */\r
+ uint32_t RESERVED5[6U];\r
+ __IM uint32_t PID4; /*!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 */\r
+ __IM uint32_t PID5; /*!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 */\r
+ __IM uint32_t PID6; /*!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 */\r
+ __IM uint32_t PID7; /*!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 */\r
+ __IM uint32_t PID0; /*!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 */\r
+ __IM uint32_t PID1; /*!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 */\r
+ __IM uint32_t PID2; /*!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 */\r
+ __IM uint32_t PID3; /*!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 */\r
+ __IM uint32_t CID0; /*!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 */\r
+ __IM uint32_t CID1; /*!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 */\r
+ __IM uint32_t CID2; /*!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 */\r
+ __IM uint32_t CID3; /*!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 */\r
+} ITM_Type;\r
+\r
+/* ITM Trace Privilege Register Definitions */\r
+#define ITM_TPR_PRIVMASK_Pos 0U /*!< ITM TPR: PRIVMASK Position */\r
+#define ITM_TPR_PRIVMASK_Msk (0xFFFFFFFFUL /*<< ITM_TPR_PRIVMASK_Pos*/) /*!< ITM TPR: PRIVMASK Mask */\r
+\r
+/* ITM Trace Control Register Definitions */\r
+#define ITM_TCR_BUSY_Pos 23U /*!< ITM TCR: BUSY Position */\r
+#define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */\r
+\r
+#define ITM_TCR_TraceBusID_Pos 16U /*!< ITM TCR: ATBID Position */\r
+#define ITM_TCR_TraceBusID_Msk (0x7FUL << ITM_TCR_TraceBusID_Pos) /*!< ITM TCR: ATBID Mask */\r
+\r
+#define ITM_TCR_GTSFREQ_Pos 10U /*!< ITM TCR: Global timestamp frequency Position */\r
+#define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */\r
+\r
+#define ITM_TCR_TSPrescale_Pos 8U /*!< ITM TCR: TSPrescale Position */\r
+#define ITM_TCR_TSPrescale_Msk (3UL << ITM_TCR_TSPrescale_Pos) /*!< ITM TCR: TSPrescale Mask */\r
+\r
+#define ITM_TCR_SWOENA_Pos 4U /*!< ITM TCR: SWOENA Position */\r
+#define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */\r
+\r
+#define ITM_TCR_DWTENA_Pos 3U /*!< ITM TCR: DWTENA Position */\r
+#define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */\r
+\r
+#define ITM_TCR_SYNCENA_Pos 2U /*!< ITM TCR: SYNCENA Position */\r
+#define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */\r
+\r
+#define ITM_TCR_TSENA_Pos 1U /*!< ITM TCR: TSENA Position */\r
+#define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */\r
+\r
+#define ITM_TCR_ITMENA_Pos 0U /*!< ITM TCR: ITM Enable bit Position */\r
+#define ITM_TCR_ITMENA_Msk (1UL /*<< ITM_TCR_ITMENA_Pos*/) /*!< ITM TCR: ITM Enable bit Mask */\r
+\r
+/* ITM Integration Write Register Definitions */\r
+#define ITM_IWR_ATVALIDM_Pos 0U /*!< ITM IWR: ATVALIDM Position */\r
+#define ITM_IWR_ATVALIDM_Msk (1UL /*<< ITM_IWR_ATVALIDM_Pos*/) /*!< ITM IWR: ATVALIDM Mask */\r
+\r
+/* ITM Integration Read Register Definitions */\r
+#define ITM_IRR_ATREADYM_Pos 0U /*!< ITM IRR: ATREADYM Position */\r
+#define ITM_IRR_ATREADYM_Msk (1UL /*<< ITM_IRR_ATREADYM_Pos*/) /*!< ITM IRR: ATREADYM Mask */\r
+\r
+/* ITM Integration Mode Control Register Definitions */\r
+#define ITM_IMCR_INTEGRATION_Pos 0U /*!< ITM IMCR: INTEGRATION Position */\r
+#define ITM_IMCR_INTEGRATION_Msk (1UL /*<< ITM_IMCR_INTEGRATION_Pos*/) /*!< ITM IMCR: INTEGRATION Mask */\r
+\r
+/* ITM Lock Status Register Definitions */\r
+#define ITM_LSR_ByteAcc_Pos 2U /*!< ITM LSR: ByteAcc Position */\r
+#define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */\r
+\r
+#define ITM_LSR_Access_Pos 1U /*!< ITM LSR: Access Position */\r
+#define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */\r
+\r
+#define ITM_LSR_Present_Pos 0U /*!< ITM LSR: Present Position */\r
+#define ITM_LSR_Present_Msk (1UL /*<< ITM_LSR_Present_Pos*/) /*!< ITM LSR: Present Mask */\r
+\r
+/*@}*/ /* end of group CMSIS_ITM */\r
+\r
+\r
+/**\r
+ \ingroup CMSIS_core_register\r
+ \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT)\r
+ \brief Type definitions for the Data Watchpoint and Trace (DWT)\r
+ @{\r
+ */\r
+\r
+/**\r
+ \brief Structure type to access the Data Watchpoint and Trace Register (DWT).\r
+ */\r
+typedef struct\r
+{\r
+ __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */\r
+ __IOM uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */\r
+ __IOM uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */\r
+ __IOM uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */\r
+ __IOM uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */\r
+ __IOM uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */\r
+ __IOM uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */\r
+ __IM uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */\r
+ __IOM uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */\r
+ __IOM uint32_t MASK0; /*!< Offset: 0x024 (R/W) Mask Register 0 */\r
+ __IOM uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */\r
+ uint32_t RESERVED0[1U];\r
+ __IOM uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */\r
+ __IOM uint32_t MASK1; /*!< Offset: 0x034 (R/W) Mask Register 1 */\r
+ __IOM uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */\r
+ uint32_t RESERVED1[1U];\r
+ __IOM uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */\r
+ __IOM uint32_t MASK2; /*!< Offset: 0x044 (R/W) Mask Register 2 */\r
+ __IOM uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */\r
+ uint32_t RESERVED2[1U];\r
+ __IOM uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */\r
+ __IOM uint32_t MASK3; /*!< Offset: 0x054 (R/W) Mask Register 3 */\r
+ __IOM uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */\r
+} DWT_Type;\r
+\r
+/* DWT Control Register Definitions */\r
+#define DWT_CTRL_NUMCOMP_Pos 28U /*!< DWT CTRL: NUMCOMP Position */\r
+#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */\r
+\r
+#define DWT_CTRL_NOTRCPKT_Pos 27U /*!< DWT CTRL: NOTRCPKT Position */\r
+#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */\r
+\r
+#define DWT_CTRL_NOEXTTRIG_Pos 26U /*!< DWT CTRL: NOEXTTRIG Position */\r
+#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */\r
+\r
+#define DWT_CTRL_NOCYCCNT_Pos 25U /*!< DWT CTRL: NOCYCCNT Position */\r
+#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */\r
+\r
+#define DWT_CTRL_NOPRFCNT_Pos 24U /*!< DWT CTRL: NOPRFCNT Position */\r
+#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */\r
+\r
+#define DWT_CTRL_CYCEVTENA_Pos 22U /*!< DWT CTRL: CYCEVTENA Position */\r
+#define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */\r
+\r
+#define DWT_CTRL_FOLDEVTENA_Pos 21U /*!< DWT CTRL: FOLDEVTENA Position */\r
+#define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */\r
+\r
+#define DWT_CTRL_LSUEVTENA_Pos 20U /*!< DWT CTRL: LSUEVTENA Position */\r
+#define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */\r
+\r
+#define DWT_CTRL_SLEEPEVTENA_Pos 19U /*!< DWT CTRL: SLEEPEVTENA Position */\r
+#define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */\r
+\r
+#define DWT_CTRL_EXCEVTENA_Pos 18U /*!< DWT CTRL: EXCEVTENA Position */\r
+#define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */\r
+\r
+#define DWT_CTRL_CPIEVTENA_Pos 17U /*!< DWT CTRL: CPIEVTENA Position */\r
+#define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */\r
+\r
+#define DWT_CTRL_EXCTRCENA_Pos 16U /*!< DWT CTRL: EXCTRCENA Position */\r
+#define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */\r
+\r
+#define DWT_CTRL_PCSAMPLENA_Pos 12U /*!< DWT CTRL: PCSAMPLENA Position */\r
+#define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */\r
+\r
+#define DWT_CTRL_SYNCTAP_Pos 10U /*!< DWT CTRL: SYNCTAP Position */\r
+#define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */\r
+\r
+#define DWT_CTRL_CYCTAP_Pos 9U /*!< DWT CTRL: CYCTAP Position */\r
+#define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */\r
+\r
+#define DWT_CTRL_POSTINIT_Pos 5U /*!< DWT CTRL: POSTINIT Position */\r
+#define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */\r
+\r
+#define DWT_CTRL_POSTPRESET_Pos 1U /*!< DWT CTRL: POSTPRESET Position */\r
+#define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */\r
+\r
+#define DWT_CTRL_CYCCNTENA_Pos 0U /*!< DWT CTRL: CYCCNTENA Position */\r
+#define DWT_CTRL_CYCCNTENA_Msk (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/) /*!< DWT CTRL: CYCCNTENA Mask */\r
+\r
+/* DWT CPI Count Register Definitions */\r
+#define DWT_CPICNT_CPICNT_Pos 0U /*!< DWT CPICNT: CPICNT Position */\r
+#define DWT_CPICNT_CPICNT_Msk (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/) /*!< DWT CPICNT: CPICNT Mask */\r
+\r
+/* DWT Exception Overhead Count Register Definitions */\r
+#define DWT_EXCCNT_EXCCNT_Pos 0U /*!< DWT EXCCNT: EXCCNT Position */\r
+#define DWT_EXCCNT_EXCCNT_Msk (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/) /*!< DWT EXCCNT: EXCCNT Mask */\r
+\r
+/* DWT Sleep Count Register Definitions */\r
+#define DWT_SLEEPCNT_SLEEPCNT_Pos 0U /*!< DWT SLEEPCNT: SLEEPCNT Position */\r
+#define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/) /*!< DWT SLEEPCNT: SLEEPCNT Mask */\r
+\r
+/* DWT LSU Count Register Definitions */\r
+#define DWT_LSUCNT_LSUCNT_Pos 0U /*!< DWT LSUCNT: LSUCNT Position */\r
+#define DWT_LSUCNT_LSUCNT_Msk (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/) /*!< DWT LSUCNT: LSUCNT Mask */\r
+\r
+/* DWT Folded-instruction Count Register Definitions */\r
+#define DWT_FOLDCNT_FOLDCNT_Pos 0U /*!< DWT FOLDCNT: FOLDCNT Position */\r
+#define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/) /*!< DWT FOLDCNT: FOLDCNT Mask */\r
+\r
+/* DWT Comparator Mask Register Definitions */\r
+#define DWT_MASK_MASK_Pos 0U /*!< DWT MASK: MASK Position */\r
+#define DWT_MASK_MASK_Msk (0x1FUL /*<< DWT_MASK_MASK_Pos*/) /*!< DWT MASK: MASK Mask */\r
+\r
+/* DWT Comparator Function Register Definitions */\r
+#define DWT_FUNCTION_MATCHED_Pos 24U /*!< DWT FUNCTION: MATCHED Position */\r
+#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */\r
+\r
+#define DWT_FUNCTION_DATAVADDR1_Pos 16U /*!< DWT FUNCTION: DATAVADDR1 Position */\r
+#define DWT_FUNCTION_DATAVADDR1_Msk (0xFUL << DWT_FUNCTION_DATAVADDR1_Pos) /*!< DWT FUNCTION: DATAVADDR1 Mask */\r
+\r
+#define DWT_FUNCTION_DATAVADDR0_Pos 12U /*!< DWT FUNCTION: DATAVADDR0 Position */\r
+#define DWT_FUNCTION_DATAVADDR0_Msk (0xFUL << DWT_FUNCTION_DATAVADDR0_Pos) /*!< DWT FUNCTION: DATAVADDR0 Mask */\r
+\r
+#define DWT_FUNCTION_DATAVSIZE_Pos 10U /*!< DWT FUNCTION: DATAVSIZE Position */\r
+#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */\r
+\r
+#define DWT_FUNCTION_LNK1ENA_Pos 9U /*!< DWT FUNCTION: LNK1ENA Position */\r
+#define DWT_FUNCTION_LNK1ENA_Msk (0x1UL << DWT_FUNCTION_LNK1ENA_Pos) /*!< DWT FUNCTION: LNK1ENA Mask */\r
+\r
+#define DWT_FUNCTION_DATAVMATCH_Pos 8U /*!< DWT FUNCTION: DATAVMATCH Position */\r
+#define DWT_FUNCTION_DATAVMATCH_Msk (0x1UL << DWT_FUNCTION_DATAVMATCH_Pos) /*!< DWT FUNCTION: DATAVMATCH Mask */\r
+\r
+#define DWT_FUNCTION_CYCMATCH_Pos 7U /*!< DWT FUNCTION: CYCMATCH Position */\r
+#define DWT_FUNCTION_CYCMATCH_Msk (0x1UL << DWT_FUNCTION_CYCMATCH_Pos) /*!< DWT FUNCTION: CYCMATCH Mask */\r
+\r
+#define DWT_FUNCTION_EMITRANGE_Pos 5U /*!< DWT FUNCTION: EMITRANGE Position */\r
+#define DWT_FUNCTION_EMITRANGE_Msk (0x1UL << DWT_FUNCTION_EMITRANGE_Pos) /*!< DWT FUNCTION: EMITRANGE Mask */\r
+\r
+#define DWT_FUNCTION_FUNCTION_Pos 0U /*!< DWT FUNCTION: FUNCTION Position */\r
+#define DWT_FUNCTION_FUNCTION_Msk (0xFUL /*<< DWT_FUNCTION_FUNCTION_Pos*/) /*!< DWT FUNCTION: FUNCTION Mask */\r
+\r
+/*@}*/ /* end of group CMSIS_DWT */\r
+\r
+\r
+/**\r
+ \ingroup CMSIS_core_register\r
+ \defgroup CMSIS_TPI Trace Port Interface (TPI)\r
+ \brief Type definitions for the Trace Port Interface (TPI)\r
+ @{\r
+ */\r
+\r
+/**\r
+ \brief Structure type to access the Trace Port Interface Register (TPI).\r
+ */\r
+typedef struct\r
+{\r
+ __IM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */\r
+ __IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */\r
+ uint32_t RESERVED0[2U];\r
+ __IOM uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */\r
+ uint32_t RESERVED1[55U];\r
+ __IOM uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */\r
+ uint32_t RESERVED2[131U];\r
+ __IM uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */\r
+ __IOM uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */\r
+ __IM uint32_t FSCR; /*!< Offset: 0x308 (R/ ) Formatter Synchronization Counter Register */\r
+ uint32_t RESERVED3[759U];\r
+ __IM uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER Register */\r
+ __IM uint32_t FIFO0; /*!< Offset: 0xEEC (R/ ) Integration ETM Data */\r
+ __IM uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/ ) ITATBCTR2 */\r
+ uint32_t RESERVED4[1U];\r
+ __IM uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) ITATBCTR0 */\r
+ __IM uint32_t FIFO1; /*!< Offset: 0xEFC (R/ ) Integration ITM Data */\r
+ __IOM uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */\r
+ uint32_t RESERVED5[39U];\r
+ __IOM uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */\r
+ __IOM uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */\r
+ uint32_t RESERVED7[8U];\r
+ __IM uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) TPIU_DEVID */\r
+ __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) TPIU_DEVTYPE */\r
+} TPI_Type;\r
+\r
+/* TPI Asynchronous Clock Prescaler Register Definitions */\r
+#define TPI_ACPR_PRESCALER_Pos 0U /*!< TPI ACPR: PRESCALER Position */\r
+#define TPI_ACPR_PRESCALER_Msk (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/) /*!< TPI ACPR: PRESCALER Mask */\r
+\r
+/* TPI Selected Pin Protocol Register Definitions */\r
+#define TPI_SPPR_TXMODE_Pos 0U /*!< TPI SPPR: TXMODE Position */\r
+#define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) /*!< TPI SPPR: TXMODE Mask */\r
+\r
+/* TPI Formatter and Flush Status Register Definitions */\r
+#define TPI_FFSR_FtNonStop_Pos 3U /*!< TPI FFSR: FtNonStop Position */\r
+#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */\r
+\r
+#define TPI_FFSR_TCPresent_Pos 2U /*!< TPI FFSR: TCPresent Position */\r
+#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */\r
+\r
+#define TPI_FFSR_FtStopped_Pos 1U /*!< TPI FFSR: FtStopped Position */\r
+#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */\r
+\r
+#define TPI_FFSR_FlInProg_Pos 0U /*!< TPI FFSR: FlInProg Position */\r
+#define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) /*!< TPI FFSR: FlInProg Mask */\r
+\r
+/* TPI Formatter and Flush Control Register Definitions */\r
+#define TPI_FFCR_TrigIn_Pos 8U /*!< TPI FFCR: TrigIn Position */\r
+#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */\r
+\r
+#define TPI_FFCR_EnFCont_Pos 1U /*!< TPI FFCR: EnFCont Position */\r
+#define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */\r
+\r
+/* TPI TRIGGER Register Definitions */\r
+#define TPI_TRIGGER_TRIGGER_Pos 0U /*!< TPI TRIGGER: TRIGGER Position */\r
+#define TPI_TRIGGER_TRIGGER_Msk (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/) /*!< TPI TRIGGER: TRIGGER Mask */\r
+\r
+/* TPI Integration ETM Data Register Definitions (FIFO0) */\r
+#define TPI_FIFO0_ITM_ATVALID_Pos 29U /*!< TPI FIFO0: ITM_ATVALID Position */\r
+#define TPI_FIFO0_ITM_ATVALID_Msk (0x3UL << TPI_FIFO0_ITM_ATVALID_Pos) /*!< TPI FIFO0: ITM_ATVALID Mask */\r
+\r
+#define TPI_FIFO0_ITM_bytecount_Pos 27U /*!< TPI FIFO0: ITM_bytecount Position */\r
+#define TPI_FIFO0_ITM_bytecount_Msk (0x3UL << TPI_FIFO0_ITM_bytecount_Pos) /*!< TPI FIFO0: ITM_bytecount Mask */\r
+\r
+#define TPI_FIFO0_ETM_ATVALID_Pos 26U /*!< TPI FIFO0: ETM_ATVALID Position */\r
+#define TPI_FIFO0_ETM_ATVALID_Msk (0x3UL << TPI_FIFO0_ETM_ATVALID_Pos) /*!< TPI FIFO0: ETM_ATVALID Mask */\r
+\r
+#define TPI_FIFO0_ETM_bytecount_Pos 24U /*!< TPI FIFO0: ETM_bytecount Position */\r
+#define TPI_FIFO0_ETM_bytecount_Msk (0x3UL << TPI_FIFO0_ETM_bytecount_Pos) /*!< TPI FIFO0: ETM_bytecount Mask */\r
+\r
+#define TPI_FIFO0_ETM2_Pos 16U /*!< TPI FIFO0: ETM2 Position */\r
+#define TPI_FIFO0_ETM2_Msk (0xFFUL << TPI_FIFO0_ETM2_Pos) /*!< TPI FIFO0: ETM2 Mask */\r
+\r
+#define TPI_FIFO0_ETM1_Pos 8U /*!< TPI FIFO0: ETM1 Position */\r
+#define TPI_FIFO0_ETM1_Msk (0xFFUL << TPI_FIFO0_ETM1_Pos) /*!< TPI FIFO0: ETM1 Mask */\r
+\r
+#define TPI_FIFO0_ETM0_Pos 0U /*!< TPI FIFO0: ETM0 Position */\r
+#define TPI_FIFO0_ETM0_Msk (0xFFUL /*<< TPI_FIFO0_ETM0_Pos*/) /*!< TPI FIFO0: ETM0 Mask */\r
+\r
+/* TPI ITATBCTR2 Register Definitions */\r
+#define TPI_ITATBCTR2_ATREADY2_Pos 0U /*!< TPI ITATBCTR2: ATREADY2 Position */\r
+#define TPI_ITATBCTR2_ATREADY2_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY2_Pos*/) /*!< TPI ITATBCTR2: ATREADY2 Mask */\r
+\r
+#define TPI_ITATBCTR2_ATREADY1_Pos 0U /*!< TPI ITATBCTR2: ATREADY1 Position */\r
+#define TPI_ITATBCTR2_ATREADY1_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY1_Pos*/) /*!< TPI ITATBCTR2: ATREADY1 Mask */\r
+\r
+/* TPI Integration ITM Data Register Definitions (FIFO1) */\r
+#define TPI_FIFO1_ITM_ATVALID_Pos 29U /*!< TPI FIFO1: ITM_ATVALID Position */\r
+#define TPI_FIFO1_ITM_ATVALID_Msk (0x3UL << TPI_FIFO1_ITM_ATVALID_Pos) /*!< TPI FIFO1: ITM_ATVALID Mask */\r
+\r
+#define TPI_FIFO1_ITM_bytecount_Pos 27U /*!< TPI FIFO1: ITM_bytecount Position */\r
+#define TPI_FIFO1_ITM_bytecount_Msk (0x3UL << TPI_FIFO1_ITM_bytecount_Pos) /*!< TPI FIFO1: ITM_bytecount Mask */\r
+\r
+#define TPI_FIFO1_ETM_ATVALID_Pos 26U /*!< TPI FIFO1: ETM_ATVALID Position */\r
+#define TPI_FIFO1_ETM_ATVALID_Msk (0x3UL << TPI_FIFO1_ETM_ATVALID_Pos) /*!< TPI FIFO1: ETM_ATVALID Mask */\r
+\r
+#define TPI_FIFO1_ETM_bytecount_Pos 24U /*!< TPI FIFO1: ETM_bytecount Position */\r
+#define TPI_FIFO1_ETM_bytecount_Msk (0x3UL << TPI_FIFO1_ETM_bytecount_Pos) /*!< TPI FIFO1: ETM_bytecount Mask */\r
+\r
+#define TPI_FIFO1_ITM2_Pos 16U /*!< TPI FIFO1: ITM2 Position */\r
+#define TPI_FIFO1_ITM2_Msk (0xFFUL << TPI_FIFO1_ITM2_Pos) /*!< TPI FIFO1: ITM2 Mask */\r
+\r
+#define TPI_FIFO1_ITM1_Pos 8U /*!< TPI FIFO1: ITM1 Position */\r
+#define TPI_FIFO1_ITM1_Msk (0xFFUL << TPI_FIFO1_ITM1_Pos) /*!< TPI FIFO1: ITM1 Mask */\r
+\r
+#define TPI_FIFO1_ITM0_Pos 0U /*!< TPI FIFO1: ITM0 Position */\r
+#define TPI_FIFO1_ITM0_Msk (0xFFUL /*<< TPI_FIFO1_ITM0_Pos*/) /*!< TPI FIFO1: ITM0 Mask */\r
+\r
+/* TPI ITATBCTR0 Register Definitions */\r
+#define TPI_ITATBCTR0_ATREADY2_Pos 0U /*!< TPI ITATBCTR0: ATREADY2 Position */\r
+#define TPI_ITATBCTR0_ATREADY2_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY2_Pos*/) /*!< TPI ITATBCTR0: ATREADY2 Mask */\r
+\r
+#define TPI_ITATBCTR0_ATREADY1_Pos 0U /*!< TPI ITATBCTR0: ATREADY1 Position */\r
+#define TPI_ITATBCTR0_ATREADY1_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY1_Pos*/) /*!< TPI ITATBCTR0: ATREADY1 Mask */\r
+\r
+/* TPI Integration Mode Control Register Definitions */\r
+#define TPI_ITCTRL_Mode_Pos 0U /*!< TPI ITCTRL: Mode Position */\r
+#define TPI_ITCTRL_Mode_Msk (0x3UL /*<< TPI_ITCTRL_Mode_Pos*/) /*!< TPI ITCTRL: Mode Mask */\r
+\r
+/* TPI DEVID Register Definitions */\r
+#define TPI_DEVID_NRZVALID_Pos 11U /*!< TPI DEVID: NRZVALID Position */\r
+#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */\r
+\r
+#define TPI_DEVID_MANCVALID_Pos 10U /*!< TPI DEVID: MANCVALID Position */\r
+#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */\r
+\r
+#define TPI_DEVID_PTINVALID_Pos 9U /*!< TPI DEVID: PTINVALID Position */\r
+#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */\r
+\r
+#define TPI_DEVID_MinBufSz_Pos 6U /*!< TPI DEVID: MinBufSz Position */\r
+#define TPI_DEVID_MinBufSz_Msk (0x7UL << TPI_DEVID_MinBufSz_Pos) /*!< TPI DEVID: MinBufSz Mask */\r
+\r
+#define TPI_DEVID_AsynClkIn_Pos 5U /*!< TPI DEVID: AsynClkIn Position */\r
+#define TPI_DEVID_AsynClkIn_Msk (0x1UL << TPI_DEVID_AsynClkIn_Pos) /*!< TPI DEVID: AsynClkIn Mask */\r
+\r
+#define TPI_DEVID_NrTraceInput_Pos 0U /*!< TPI DEVID: NrTraceInput Position */\r
+#define TPI_DEVID_NrTraceInput_Msk (0x1FUL /*<< TPI_DEVID_NrTraceInput_Pos*/) /*!< TPI DEVID: NrTraceInput Mask */\r
+\r
+/* TPI DEVTYPE Register Definitions */\r
+#define TPI_DEVTYPE_SubType_Pos 4U /*!< TPI DEVTYPE: SubType Position */\r
+#define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */\r
+\r
+#define TPI_DEVTYPE_MajorType_Pos 0U /*!< TPI DEVTYPE: MajorType Position */\r
+#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */\r
+\r
+/*@}*/ /* end of group CMSIS_TPI */\r
+\r
+\r
+#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)\r
+/**\r
+ \ingroup CMSIS_core_register\r
+ \defgroup CMSIS_MPU Memory Protection Unit (MPU)\r
+ \brief Type definitions for the Memory Protection Unit (MPU)\r
+ @{\r
+ */\r
+\r
+/**\r
+ \brief Structure type to access the Memory Protection Unit (MPU).\r
+ */\r
+typedef struct\r
+{\r
+ __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */\r
+ __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */\r
+ __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */\r
+ __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */\r
+ __IOM uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */\r
+ __IOM uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Alias 1 Region Base Address Register */\r
+ __IOM uint32_t RASR_A1; /*!< Offset: 0x018 (R/W) MPU Alias 1 Region Attribute and Size Register */\r
+ __IOM uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Alias 2 Region Base Address Register */\r
+ __IOM uint32_t RASR_A2; /*!< Offset: 0x020 (R/W) MPU Alias 2 Region Attribute and Size Register */\r
+ __IOM uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Alias 3 Region Base Address Register */\r
+ __IOM uint32_t RASR_A3; /*!< Offset: 0x028 (R/W) MPU Alias 3 Region Attribute and Size Register */\r
+} MPU_Type;\r
+\r
+#define MPU_TYPE_RALIASES 4U\r
+\r
+/* MPU Type Register Definitions */\r
+#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */\r
+#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */\r
+\r
+#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */\r
+#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */\r
+\r
+#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */\r
+#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */\r
+\r
+/* MPU Control Register Definitions */\r
+#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */\r
+#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */\r
+\r
+#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */\r
+#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */\r
+\r
+#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */\r
+#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */\r
+\r
+/* MPU Region Number Register Definitions */\r
+#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */\r
+#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */\r
+\r
+/* MPU Region Base Address Register Definitions */\r
+#define MPU_RBAR_ADDR_Pos 5U /*!< MPU RBAR: ADDR Position */\r
+#define MPU_RBAR_ADDR_Msk (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */\r
+\r
+#define MPU_RBAR_VALID_Pos 4U /*!< MPU RBAR: VALID Position */\r
+#define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */\r
+\r
+#define MPU_RBAR_REGION_Pos 0U /*!< MPU RBAR: REGION Position */\r
+#define MPU_RBAR_REGION_Msk (0xFUL /*<< MPU_RBAR_REGION_Pos*/) /*!< MPU RBAR: REGION Mask */\r
+\r
+/* MPU Region Attribute and Size Register Definitions */\r
+#define MPU_RASR_ATTRS_Pos 16U /*!< MPU RASR: MPU Region Attribute field Position */\r
+#define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */\r
+\r
+#define MPU_RASR_XN_Pos 28U /*!< MPU RASR: ATTRS.XN Position */\r
+#define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */\r
+\r
+#define MPU_RASR_AP_Pos 24U /*!< MPU RASR: ATTRS.AP Position */\r
+#define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */\r
+\r
+#define MPU_RASR_TEX_Pos 19U /*!< MPU RASR: ATTRS.TEX Position */\r
+#define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */\r
+\r
+#define MPU_RASR_S_Pos 18U /*!< MPU RASR: ATTRS.S Position */\r
+#define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */\r
+\r
+#define MPU_RASR_C_Pos 17U /*!< MPU RASR: ATTRS.C Position */\r
+#define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */\r
+\r
+#define MPU_RASR_B_Pos 16U /*!< MPU RASR: ATTRS.B Position */\r
+#define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */\r
+\r
+#define MPU_RASR_SRD_Pos 8U /*!< MPU RASR: Sub-Region Disable Position */\r
+#define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */\r
+\r
+#define MPU_RASR_SIZE_Pos 1U /*!< MPU RASR: Region Size Field Position */\r
+#define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */\r
+\r
+#define MPU_RASR_ENABLE_Pos 0U /*!< MPU RASR: Region enable bit Position */\r
+#define MPU_RASR_ENABLE_Msk (1UL /*<< MPU_RASR_ENABLE_Pos*/) /*!< MPU RASR: Region enable bit Disable Mask */\r
+\r
+/*@} end of group CMSIS_MPU */\r
+#endif /* defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) */\r
+\r
+\r
+/**\r
+ \ingroup CMSIS_core_register\r
+ \defgroup CMSIS_FPU Floating Point Unit (FPU)\r
+ \brief Type definitions for the Floating Point Unit (FPU)\r
+ @{\r
+ */\r
+\r
+/**\r
+ \brief Structure type to access the Floating Point Unit (FPU).\r
+ */\r
+typedef struct\r
+{\r
+ uint32_t RESERVED0[1U];\r
+ __IOM uint32_t FPCCR; /*!< Offset: 0x004 (R/W) Floating-Point Context Control Register */\r
+ __IOM uint32_t FPCAR; /*!< Offset: 0x008 (R/W) Floating-Point Context Address Register */\r
+ __IOM uint32_t FPDSCR; /*!< Offset: 0x00C (R/W) Floating-Point Default Status Control Register */\r
+ __IM uint32_t MVFR0; /*!< Offset: 0x010 (R/ ) Media and FP Feature Register 0 */\r
+ __IM uint32_t MVFR1; /*!< Offset: 0x014 (R/ ) Media and FP Feature Register 1 */\r
+} FPU_Type;\r
+\r
+/* Floating-Point Context Control Register Definitions */\r
+#define FPU_FPCCR_ASPEN_Pos 31U /*!< FPCCR: ASPEN bit Position */\r
+#define FPU_FPCCR_ASPEN_Msk (1UL << FPU_FPCCR_ASPEN_Pos) /*!< FPCCR: ASPEN bit Mask */\r
+\r
+#define FPU_FPCCR_LSPEN_Pos 30U /*!< FPCCR: LSPEN Position */\r
+#define FPU_FPCCR_LSPEN_Msk (1UL << FPU_FPCCR_LSPEN_Pos) /*!< FPCCR: LSPEN bit Mask */\r
+\r
+#define FPU_FPCCR_MONRDY_Pos 8U /*!< FPCCR: MONRDY Position */\r
+#define FPU_FPCCR_MONRDY_Msk (1UL << FPU_FPCCR_MONRDY_Pos) /*!< FPCCR: MONRDY bit Mask */\r
+\r
+#define FPU_FPCCR_BFRDY_Pos 6U /*!< FPCCR: BFRDY Position */\r
+#define FPU_FPCCR_BFRDY_Msk (1UL << FPU_FPCCR_BFRDY_Pos) /*!< FPCCR: BFRDY bit Mask */\r
+\r
+#define FPU_FPCCR_MMRDY_Pos 5U /*!< FPCCR: MMRDY Position */\r
+#define FPU_FPCCR_MMRDY_Msk (1UL << FPU_FPCCR_MMRDY_Pos) /*!< FPCCR: MMRDY bit Mask */\r
+\r
+#define FPU_FPCCR_HFRDY_Pos 4U /*!< FPCCR: HFRDY Position */\r
+#define FPU_FPCCR_HFRDY_Msk (1UL << FPU_FPCCR_HFRDY_Pos) /*!< FPCCR: HFRDY bit Mask */\r
+\r
+#define FPU_FPCCR_THREAD_Pos 3U /*!< FPCCR: processor mode bit Position */\r
+#define FPU_FPCCR_THREAD_Msk (1UL << FPU_FPCCR_THREAD_Pos) /*!< FPCCR: processor mode active bit Mask */\r
+\r
+#define FPU_FPCCR_USER_Pos 1U /*!< FPCCR: privilege level bit Position */\r
+#define FPU_FPCCR_USER_Msk (1UL << FPU_FPCCR_USER_Pos) /*!< FPCCR: privilege level bit Mask */\r
+\r
+#define FPU_FPCCR_LSPACT_Pos 0U /*!< FPCCR: Lazy state preservation active bit Position */\r
+#define FPU_FPCCR_LSPACT_Msk (1UL /*<< FPU_FPCCR_LSPACT_Pos*/) /*!< FPCCR: Lazy state preservation active bit Mask */\r
+\r
+/* Floating-Point Context Address Register Definitions */\r
+#define FPU_FPCAR_ADDRESS_Pos 3U /*!< FPCAR: ADDRESS bit Position */\r
+#define FPU_FPCAR_ADDRESS_Msk (0x1FFFFFFFUL << FPU_FPCAR_ADDRESS_Pos) /*!< FPCAR: ADDRESS bit Mask */\r
+\r
+/* Floating-Point Default Status Control Register Definitions */\r
+#define FPU_FPDSCR_AHP_Pos 26U /*!< FPDSCR: AHP bit Position */\r
+#define FPU_FPDSCR_AHP_Msk (1UL << FPU_FPDSCR_AHP_Pos) /*!< FPDSCR: AHP bit Mask */\r
+\r
+#define FPU_FPDSCR_DN_Pos 25U /*!< FPDSCR: DN bit Position */\r
+#define FPU_FPDSCR_DN_Msk (1UL << FPU_FPDSCR_DN_Pos) /*!< FPDSCR: DN bit Mask */\r
+\r
+#define FPU_FPDSCR_FZ_Pos 24U /*!< FPDSCR: FZ bit Position */\r
+#define FPU_FPDSCR_FZ_Msk (1UL << FPU_FPDSCR_FZ_Pos) /*!< FPDSCR: FZ bit Mask */\r
+\r
+#define FPU_FPDSCR_RMode_Pos 22U /*!< FPDSCR: RMode bit Position */\r
+#define FPU_FPDSCR_RMode_Msk (3UL << FPU_FPDSCR_RMode_Pos) /*!< FPDSCR: RMode bit Mask */\r
+\r
+/* Media and FP Feature Register 0 Definitions */\r
+#define FPU_MVFR0_FP_rounding_modes_Pos 28U /*!< MVFR0: FP rounding modes bits Position */\r
+#define FPU_MVFR0_FP_rounding_modes_Msk (0xFUL << FPU_MVFR0_FP_rounding_modes_Pos) /*!< MVFR0: FP rounding modes bits Mask */\r
+\r
+#define FPU_MVFR0_Short_vectors_Pos 24U /*!< MVFR0: Short vectors bits Position */\r
+#define FPU_MVFR0_Short_vectors_Msk (0xFUL << FPU_MVFR0_Short_vectors_Pos) /*!< MVFR0: Short vectors bits Mask */\r
+\r
+#define FPU_MVFR0_Square_root_Pos 20U /*!< MVFR0: Square root bits Position */\r
+#define FPU_MVFR0_Square_root_Msk (0xFUL << FPU_MVFR0_Square_root_Pos) /*!< MVFR0: Square root bits Mask */\r
+\r
+#define FPU_MVFR0_Divide_Pos 16U /*!< MVFR0: Divide bits Position */\r
+#define FPU_MVFR0_Divide_Msk (0xFUL << FPU_MVFR0_Divide_Pos) /*!< MVFR0: Divide bits Mask */\r
+\r
+#define FPU_MVFR0_FP_excep_trapping_Pos 12U /*!< MVFR0: FP exception trapping bits Position */\r
+#define FPU_MVFR0_FP_excep_trapping_Msk (0xFUL << FPU_MVFR0_FP_excep_trapping_Pos) /*!< MVFR0: FP exception trapping bits Mask */\r
+\r
+#define FPU_MVFR0_Double_precision_Pos 8U /*!< MVFR0: Double-precision bits Position */\r
+#define FPU_MVFR0_Double_precision_Msk (0xFUL << FPU_MVFR0_Double_precision_Pos) /*!< MVFR0: Double-precision bits Mask */\r
+\r
+#define FPU_MVFR0_Single_precision_Pos 4U /*!< MVFR0: Single-precision bits Position */\r
+#define FPU_MVFR0_Single_precision_Msk (0xFUL << FPU_MVFR0_Single_precision_Pos) /*!< MVFR0: Single-precision bits Mask */\r
+\r
+#define FPU_MVFR0_A_SIMD_registers_Pos 0U /*!< MVFR0: A_SIMD registers bits Position */\r
+#define FPU_MVFR0_A_SIMD_registers_Msk (0xFUL /*<< FPU_MVFR0_A_SIMD_registers_Pos*/) /*!< MVFR0: A_SIMD registers bits Mask */\r
+\r
+/* Media and FP Feature Register 1 Definitions */\r
+#define FPU_MVFR1_FP_fused_MAC_Pos 28U /*!< MVFR1: FP fused MAC bits Position */\r
+#define FPU_MVFR1_FP_fused_MAC_Msk (0xFUL << FPU_MVFR1_FP_fused_MAC_Pos) /*!< MVFR1: FP fused MAC bits Mask */\r
+\r
+#define FPU_MVFR1_FP_HPFP_Pos 24U /*!< MVFR1: FP HPFP bits Position */\r
+#define FPU_MVFR1_FP_HPFP_Msk (0xFUL << FPU_MVFR1_FP_HPFP_Pos) /*!< MVFR1: FP HPFP bits Mask */\r
+\r
+#define FPU_MVFR1_D_NaN_mode_Pos 4U /*!< MVFR1: D_NaN mode bits Position */\r
+#define FPU_MVFR1_D_NaN_mode_Msk (0xFUL << FPU_MVFR1_D_NaN_mode_Pos) /*!< MVFR1: D_NaN mode bits Mask */\r
+\r
+#define FPU_MVFR1_FtZ_mode_Pos 0U /*!< MVFR1: FtZ mode bits Position */\r
+#define FPU_MVFR1_FtZ_mode_Msk (0xFUL /*<< FPU_MVFR1_FtZ_mode_Pos*/) /*!< MVFR1: FtZ mode bits Mask */\r
+\r
+/*@} end of group CMSIS_FPU */\r
+\r
+\r
+/**\r
+ \ingroup CMSIS_core_register\r
+ \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug)\r
+ \brief Type definitions for the Core Debug Registers\r
+ @{\r
+ */\r
+\r
+/**\r
+ \brief Structure type to access the Core Debug Register (CoreDebug).\r
+ */\r
+typedef struct\r
+{\r
+ __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */\r
+ __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */\r
+ __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */\r
+ __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */\r
+} CoreDebug_Type;\r
+\r
+/* Debug Halting Control and Status Register Definitions */\r
+#define CoreDebug_DHCSR_DBGKEY_Pos 16U /*!< CoreDebug DHCSR: DBGKEY Position */\r
+#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */\r
+\r
+#define CoreDebug_DHCSR_S_RESET_ST_Pos 25U /*!< CoreDebug DHCSR: S_RESET_ST Position */\r
+#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */\r
+\r
+#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U /*!< CoreDebug DHCSR: S_RETIRE_ST Position */\r
+#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */\r
+\r
+#define CoreDebug_DHCSR_S_LOCKUP_Pos 19U /*!< CoreDebug DHCSR: S_LOCKUP Position */\r
+#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */\r
+\r
+#define CoreDebug_DHCSR_S_SLEEP_Pos 18U /*!< CoreDebug DHCSR: S_SLEEP Position */\r
+#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */\r
+\r
+#define CoreDebug_DHCSR_S_HALT_Pos 17U /*!< CoreDebug DHCSR: S_HALT Position */\r
+#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */\r
+\r
+#define CoreDebug_DHCSR_S_REGRDY_Pos 16U /*!< CoreDebug DHCSR: S_REGRDY Position */\r
+#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */\r
+\r
+#define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5U /*!< CoreDebug DHCSR: C_SNAPSTALL Position */\r
+#define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */\r
+\r
+#define CoreDebug_DHCSR_C_MASKINTS_Pos 3U /*!< CoreDebug DHCSR: C_MASKINTS Position */\r
+#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */\r
+\r
+#define CoreDebug_DHCSR_C_STEP_Pos 2U /*!< CoreDebug DHCSR: C_STEP Position */\r
+#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */\r
+\r
+#define CoreDebug_DHCSR_C_HALT_Pos 1U /*!< CoreDebug DHCSR: C_HALT Position */\r
+#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */\r
+\r
+#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U /*!< CoreDebug DHCSR: C_DEBUGEN Position */\r
+#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */\r
+\r
+/* Debug Core Register Selector Register Definitions */\r
+#define CoreDebug_DCRSR_REGWnR_Pos 16U /*!< CoreDebug DCRSR: REGWnR Position */\r
+#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */\r
+\r
+#define CoreDebug_DCRSR_REGSEL_Pos 0U /*!< CoreDebug DCRSR: REGSEL Position */\r
+#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/) /*!< CoreDebug DCRSR: REGSEL Mask */\r
+\r
+/* Debug Exception and Monitor Control Register Definitions */\r
+#define CoreDebug_DEMCR_TRCENA_Pos 24U /*!< CoreDebug DEMCR: TRCENA Position */\r
+#define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< CoreDebug DEMCR: TRCENA Mask */\r
+\r
+#define CoreDebug_DEMCR_MON_REQ_Pos 19U /*!< CoreDebug DEMCR: MON_REQ Position */\r
+#define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< CoreDebug DEMCR: MON_REQ Mask */\r
+\r
+#define CoreDebug_DEMCR_MON_STEP_Pos 18U /*!< CoreDebug DEMCR: MON_STEP Position */\r
+#define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< CoreDebug DEMCR: MON_STEP Mask */\r
+\r
+#define CoreDebug_DEMCR_MON_PEND_Pos 17U /*!< CoreDebug DEMCR: MON_PEND Position */\r
+#define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< CoreDebug DEMCR: MON_PEND Mask */\r
+\r
+#define CoreDebug_DEMCR_MON_EN_Pos 16U /*!< CoreDebug DEMCR: MON_EN Position */\r
+#define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< CoreDebug DEMCR: MON_EN Mask */\r
+\r
+#define CoreDebug_DEMCR_VC_HARDERR_Pos 10U /*!< CoreDebug DEMCR: VC_HARDERR Position */\r
+#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */\r
+\r
+#define CoreDebug_DEMCR_VC_INTERR_Pos 9U /*!< CoreDebug DEMCR: VC_INTERR Position */\r
+#define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< CoreDebug DEMCR: VC_INTERR Mask */\r
+\r
+#define CoreDebug_DEMCR_VC_BUSERR_Pos 8U /*!< CoreDebug DEMCR: VC_BUSERR Position */\r
+#define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< CoreDebug DEMCR: VC_BUSERR Mask */\r
+\r
+#define CoreDebug_DEMCR_VC_STATERR_Pos 7U /*!< CoreDebug DEMCR: VC_STATERR Position */\r
+#define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< CoreDebug DEMCR: VC_STATERR Mask */\r
+\r
+#define CoreDebug_DEMCR_VC_CHKERR_Pos 6U /*!< CoreDebug DEMCR: VC_CHKERR Position */\r
+#define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< CoreDebug DEMCR: VC_CHKERR Mask */\r
+\r
+#define CoreDebug_DEMCR_VC_NOCPERR_Pos 5U /*!< CoreDebug DEMCR: VC_NOCPERR Position */\r
+#define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< CoreDebug DEMCR: VC_NOCPERR Mask */\r
+\r
+#define CoreDebug_DEMCR_VC_MMERR_Pos 4U /*!< CoreDebug DEMCR: VC_MMERR Position */\r
+#define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< CoreDebug DEMCR: VC_MMERR Mask */\r
+\r
+#define CoreDebug_DEMCR_VC_CORERESET_Pos 0U /*!< CoreDebug DEMCR: VC_CORERESET Position */\r
+#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/) /*!< CoreDebug DEMCR: VC_CORERESET Mask */\r
+\r
+/*@} end of group CMSIS_CoreDebug */\r
+\r
+\r
+/**\r
+ \ingroup CMSIS_core_register\r
+ \defgroup CMSIS_core_bitfield Core register bit field macros\r
+ \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk).\r
+ @{\r
+ */\r
+\r
+/**\r
+ \brief Mask and shift a bit field value for use in a register bit range.\r
+ \param[in] field Name of the register bit field.\r
+ \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type.\r
+ \return Masked and shifted value.\r
+*/\r
+#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk)\r
+\r
+/**\r
+ \brief Mask and shift a register value to extract a bit filed value.\r
+ \param[in] field Name of the register bit field.\r
+ \param[in] value Value of register. This parameter is interpreted as an uint32_t type.\r
+ \return Masked and shifted bit field value.\r
+*/\r
+#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos)\r
+\r
+/*@} end of group CMSIS_core_bitfield */\r
+\r
+\r
+/**\r
+ \ingroup CMSIS_core_register\r
+ \defgroup CMSIS_core_base Core Definitions\r
+ \brief Definitions for base addresses, unions, and structures.\r
+ @{\r
+ */\r
+\r
+/* Memory mapping of Core Hardware */\r
+#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */\r
+#define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */\r
+#define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */\r
+#define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */\r
+#define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */\r
+#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */\r
+#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */\r
+#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */\r
+\r
+#define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */\r
+#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */\r
+#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */\r
+#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */\r
+#define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */\r
+#define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */\r
+#define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */\r
+#define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE) /*!< Core Debug configuration struct */\r
+\r
+#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)\r
+ #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */\r
+ #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */\r
+#endif\r
+\r
+#define FPU_BASE (SCS_BASE + 0x0F30UL) /*!< Floating Point Unit */\r
+#define FPU ((FPU_Type *) FPU_BASE ) /*!< Floating Point Unit */\r
+\r
+/*@} */\r
+\r
+\r
+\r
+/*******************************************************************************\r
+ * Hardware Abstraction Layer\r
+ Core Function Interface contains:\r
+ - Core NVIC Functions\r
+ - Core SysTick Functions\r
+ - Core Debug Functions\r
+ - Core Register Access Functions\r
+ ******************************************************************************/\r
+/**\r
+ \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference\r
+*/\r
+\r
+\r
+\r
+/* ########################## NVIC functions #################################### */\r
+/**\r
+ \ingroup CMSIS_Core_FunctionInterface\r
+ \defgroup CMSIS_Core_NVICFunctions NVIC Functions\r
+ \brief Functions that manage interrupts and exceptions via the NVIC.\r
+ @{\r
+ */\r
+\r
+#ifdef CMSIS_NVIC_VIRTUAL\r
+ #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE\r
+ #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h"\r
+ #endif\r
+ #include CMSIS_NVIC_VIRTUAL_HEADER_FILE\r
+#else\r
+ #define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping\r
+ #define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping\r
+ #define NVIC_EnableIRQ __NVIC_EnableIRQ\r
+ #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ\r
+ #define NVIC_DisableIRQ __NVIC_DisableIRQ\r
+ #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ\r
+ #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ\r
+ #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ\r
+ #define NVIC_GetActive __NVIC_GetActive\r
+ #define NVIC_SetPriority __NVIC_SetPriority\r
+ #define NVIC_GetPriority __NVIC_GetPriority\r
+ #define NVIC_SystemReset __NVIC_SystemReset\r
+#endif /* CMSIS_NVIC_VIRTUAL */\r
+\r
+#ifdef CMSIS_VECTAB_VIRTUAL\r
+ #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE\r
+ #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h"\r
+ #endif\r
+ #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE\r
+#else\r
+ #define NVIC_SetVector __NVIC_SetVector\r
+ #define NVIC_GetVector __NVIC_GetVector\r
+#endif /* (CMSIS_VECTAB_VIRTUAL) */\r
+\r
+#define NVIC_USER_IRQ_OFFSET 16\r
+\r
+\r
+/* The following EXC_RETURN values are saved the LR on exception entry */\r
+#define EXC_RETURN_HANDLER (0xFFFFFFF1UL) /* return to Handler mode, uses MSP after return */\r
+#define EXC_RETURN_THREAD_MSP (0xFFFFFFF9UL) /* return to Thread mode, uses MSP after return */\r
+#define EXC_RETURN_THREAD_PSP (0xFFFFFFFDUL) /* return to Thread mode, uses PSP after return */\r
+#define EXC_RETURN_HANDLER_FPU (0xFFFFFFE1UL) /* return to Handler mode, uses MSP after return, restore floating-point state */\r
+#define EXC_RETURN_THREAD_MSP_FPU (0xFFFFFFE9UL) /* return to Thread mode, uses MSP after return, restore floating-point state */\r
+#define EXC_RETURN_THREAD_PSP_FPU (0xFFFFFFEDUL) /* return to Thread mode, uses PSP after return, restore floating-point state */\r
+\r
+\r
+/**\r
+ \brief Set Priority Grouping\r
+ \details Sets the priority grouping field using the required unlock sequence.\r
+ The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field.\r
+ Only values from 0..7 are used.\r
+ In case of a conflict between priority grouping and available\r
+ priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.\r
+ \param [in] PriorityGroup Priority grouping field.\r
+ */\r
+__STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup)\r
+{\r
+ uint32_t reg_value;\r
+ uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */\r
+\r
+ reg_value = SCB->AIRCR; /* read old register configuration */\r
+ reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */\r
+ reg_value = (reg_value |\r
+ ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |\r
+ (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key and priority group */\r
+ SCB->AIRCR = reg_value;\r
+}\r
+\r
+\r
+/**\r
+ \brief Get Priority Grouping\r
+ \details Reads the priority grouping field from the NVIC Interrupt Controller.\r
+ \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field).\r
+ */\r
+__STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void)\r
+{\r
+ return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos));\r
+}\r
+\r
+\r
+/**\r
+ \brief Enable Interrupt\r
+ \details Enables a device specific interrupt in the NVIC interrupt controller.\r
+ \param [in] IRQn Device specific interrupt number.\r
+ \note IRQn must not be negative.\r
+ */\r
+__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn)\r
+{\r
+ if ((int32_t)(IRQn) >= 0)\r
+ {\r
+ NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));\r
+ }\r
+}\r
+\r
+\r
+/**\r
+ \brief Get Interrupt Enable status\r
+ \details Returns a device specific interrupt enable status from the NVIC interrupt controller.\r
+ \param [in] IRQn Device specific interrupt number.\r
+ \return 0 Interrupt is not enabled.\r
+ \return 1 Interrupt is enabled.\r
+ \note IRQn must not be negative.\r
+ */\r
+__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn)\r
+{\r
+ if ((int32_t)(IRQn) >= 0)\r
+ {\r
+ return((uint32_t)(((NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));\r
+ }\r
+ else\r
+ {\r
+ return(0U);\r
+ }\r
+}\r
+\r
+\r
+/**\r
+ \brief Disable Interrupt\r
+ \details Disables a device specific interrupt in the NVIC interrupt controller.\r
+ \param [in] IRQn Device specific interrupt number.\r
+ \note IRQn must not be negative.\r
+ */\r
+__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn)\r
+{\r
+ if ((int32_t)(IRQn) >= 0)\r
+ {\r
+ NVIC->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));\r
+ __DSB();\r
+ __ISB();\r
+ }\r
+}\r
+\r
+\r
+/**\r
+ \brief Get Pending Interrupt\r
+ \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt.\r
+ \param [in] IRQn Device specific interrupt number.\r
+ \return 0 Interrupt status is not pending.\r
+ \return 1 Interrupt status is pending.\r
+ \note IRQn must not be negative.\r
+ */\r
+__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn)\r
+{\r
+ if ((int32_t)(IRQn) >= 0)\r
+ {\r
+ return((uint32_t)(((NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));\r
+ }\r
+ else\r
+ {\r
+ return(0U);\r
+ }\r
+}\r
+\r
+\r
+/**\r
+ \brief Set Pending Interrupt\r
+ \details Sets the pending bit of a device specific interrupt in the NVIC pending register.\r
+ \param [in] IRQn Device specific interrupt number.\r
+ \note IRQn must not be negative.\r
+ */\r
+__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn)\r
+{\r
+ if ((int32_t)(IRQn) >= 0)\r
+ {\r
+ NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));\r
+ }\r
+}\r
+\r
+\r
+/**\r
+ \brief Clear Pending Interrupt\r
+ \details Clears the pending bit of a device specific interrupt in the NVIC pending register.\r
+ \param [in] IRQn Device specific interrupt number.\r
+ \note IRQn must not be negative.\r
+ */\r
+__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn)\r
+{\r
+ if ((int32_t)(IRQn) >= 0)\r
+ {\r
+ NVIC->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));\r
+ }\r
+}\r
+\r
+\r
+/**\r
+ \brief Get Active Interrupt\r
+ \details Reads the active register in the NVIC and returns the active bit for the device specific interrupt.\r
+ \param [in] IRQn Device specific interrupt number.\r
+ \return 0 Interrupt status is not active.\r
+ \return 1 Interrupt status is active.\r
+ \note IRQn must not be negative.\r
+ */\r
+__STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn)\r
+{\r
+ if ((int32_t)(IRQn) >= 0)\r
+ {\r
+ return((uint32_t)(((NVIC->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));\r
+ }\r
+ else\r
+ {\r
+ return(0U);\r
+ }\r
+}\r
+\r
+\r
+/**\r
+ \brief Set Interrupt Priority\r
+ \details Sets the priority of a device specific interrupt or a processor exception.\r
+ The interrupt number can be positive to specify a device specific interrupt,\r
+ or negative to specify a processor exception.\r
+ \param [in] IRQn Interrupt number.\r
+ \param [in] priority Priority to set.\r
+ \note The priority cannot be set for every processor exception.\r
+ */\r
+__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)\r
+{\r
+ if ((int32_t)(IRQn) >= 0)\r
+ {\r
+ NVIC->IP[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);\r
+ }\r
+ else\r
+ {\r
+ SCB->SHP[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);\r
+ }\r
+}\r
+\r
+\r
+/**\r
+ \brief Get Interrupt Priority\r
+ \details Reads the priority of a device specific interrupt or a processor exception.\r
+ The interrupt number can be positive to specify a device specific interrupt,\r
+ or negative to specify a processor exception.\r
+ \param [in] IRQn Interrupt number.\r
+ \return Interrupt Priority.\r
+ Value is aligned automatically to the implemented priority bits of the microcontroller.\r
+ */\r
+__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn)\r
+{\r
+\r
+ if ((int32_t)(IRQn) >= 0)\r
+ {\r
+ return(((uint32_t)NVIC->IP[((uint32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS)));\r
+ }\r
+ else\r
+ {\r
+ return(((uint32_t)SCB->SHP[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS)));\r
+ }\r
+}\r
+\r
+\r
+/**\r
+ \brief Encode Priority\r
+ \details Encodes the priority for an interrupt with the given priority group,\r
+ preemptive priority value, and subpriority value.\r
+ In case of a conflict between priority grouping and available\r
+ priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.\r
+ \param [in] PriorityGroup Used priority group.\r
+ \param [in] PreemptPriority Preemptive priority value (starting from 0).\r
+ \param [in] SubPriority Subpriority value (starting from 0).\r
+ \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority().\r
+ */\r
+__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)\r
+{\r
+ uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */\r
+ uint32_t PreemptPriorityBits;\r
+ uint32_t SubPriorityBits;\r
+\r
+ PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);\r
+ SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));\r
+\r
+ return (\r
+ ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) |\r
+ ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL)))\r
+ );\r
+}\r
+\r
+\r
+/**\r
+ \brief Decode Priority\r
+ \details Decodes an interrupt priority value with a given priority group to\r
+ preemptive priority value and subpriority value.\r
+ In case of a conflict between priority grouping and available\r
+ priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set.\r
+ \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority().\r
+ \param [in] PriorityGroup Used priority group.\r
+ \param [out] pPreemptPriority Preemptive priority value (starting from 0).\r
+ \param [out] pSubPriority Subpriority value (starting from 0).\r
+ */\r
+__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority)\r
+{\r
+ uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */\r
+ uint32_t PreemptPriorityBits;\r
+ uint32_t SubPriorityBits;\r
+\r
+ PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);\r
+ SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));\r
+\r
+ *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL);\r
+ *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL);\r
+}\r
+\r
+\r
+/**\r
+ \brief Set Interrupt Vector\r
+ \details Sets an interrupt vector in SRAM based interrupt vector table.\r
+ The interrupt number can be positive to specify a device specific interrupt,\r
+ or negative to specify a processor exception.\r
+ VTOR must been relocated to SRAM before.\r
+ \param [in] IRQn Interrupt number\r
+ \param [in] vector Address of interrupt handler function\r
+ */\r
+__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector)\r
+{\r
+ uint32_t *vectors = (uint32_t *)SCB->VTOR;\r
+ vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector;\r
+}\r
+\r
+\r
+/**\r
+ \brief Get Interrupt Vector\r
+ \details Reads an interrupt vector from interrupt vector table.\r
+ The interrupt number can be positive to specify a device specific interrupt,\r
+ or negative to specify a processor exception.\r
+ \param [in] IRQn Interrupt number.\r
+ \return Address of interrupt handler function\r
+ */\r
+__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn)\r
+{\r
+ uint32_t *vectors = (uint32_t *)SCB->VTOR;\r
+ return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET];\r
+}\r
+\r
+\r
+/**\r
+ \brief System Reset\r
+ \details Initiates a system reset request to reset the MCU.\r
+ */\r
+__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void)\r
+{\r
+ __DSB(); /* Ensure all outstanding memory accesses included\r
+ buffered write are completed before reset */\r
+ SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |\r
+ (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) |\r
+ SCB_AIRCR_SYSRESETREQ_Msk ); /* Keep priority group unchanged */\r
+ __DSB(); /* Ensure completion of memory access */\r
+\r
+ for(;;) /* wait until reset */\r
+ {\r
+ __NOP();\r
+ }\r
+}\r
+\r
+/*@} end of CMSIS_Core_NVICFunctions */\r
+\r
+/* ########################## MPU functions #################################### */\r
+\r
+#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)\r
+\r
+#include "mpu_armv7.h"\r
+\r
+#endif\r
+\r
+\r
+/* ########################## FPU functions #################################### */\r
+/**\r
+ \ingroup CMSIS_Core_FunctionInterface\r
+ \defgroup CMSIS_Core_FpuFunctions FPU Functions\r
+ \brief Function that provides FPU type.\r
+ @{\r
+ */\r
+\r
+/**\r
+ \brief get FPU type\r
+ \details returns the FPU type\r
+ \returns\r
+ - \b 0: No FPU\r
+ - \b 1: Single precision FPU\r
+ - \b 2: Double + Single precision FPU\r
+ */\r
+__STATIC_INLINE uint32_t SCB_GetFPUType(void)\r
+{\r
+ uint32_t mvfr0;\r
+\r
+ mvfr0 = FPU->MVFR0;\r
+ if ((mvfr0 & (FPU_MVFR0_Single_precision_Msk | FPU_MVFR0_Double_precision_Msk)) == 0x020U)\r
+ {\r
+ return 1U; /* Single precision FPU */\r
+ }\r
+ else\r
+ {\r
+ return 0U; /* No FPU */\r
+ }\r
+}\r
+\r
+\r
+/*@} end of CMSIS_Core_FpuFunctions */\r
+\r
+\r
+\r
+/* ################################## SysTick function ############################################ */\r
+/**\r
+ \ingroup CMSIS_Core_FunctionInterface\r
+ \defgroup CMSIS_Core_SysTickFunctions SysTick Functions\r
+ \brief Functions that configure the System.\r
+ @{\r
+ */\r
+\r
+#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U)\r
+\r
+/**\r
+ \brief System Tick Configuration\r
+ \details Initializes the System Timer and its interrupt, and starts the System Tick Timer.\r
+ Counter is in free running mode to generate periodic interrupts.\r
+ \param [in] ticks Number of ticks between two interrupts.\r
+ \return 0 Function succeeded.\r
+ \return 1 Function failed.\r
+ \note When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the\r
+ function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>\r
+ must contain a vendor-specific implementation of this function.\r
+ */\r
+__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)\r
+{\r
+ if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk)\r
+ {\r
+ return (1UL); /* Reload value impossible */\r
+ }\r
+\r
+ SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */\r
+ NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */\r
+ SysTick->VAL = 0UL; /* Load the SysTick Counter Value */\r
+ SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk |\r
+ SysTick_CTRL_TICKINT_Msk |\r
+ SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */\r
+ return (0UL); /* Function successful */\r
+}\r
+\r
+#endif\r
+\r
+/*@} end of CMSIS_Core_SysTickFunctions */\r
+\r
+\r
+\r
+/* ##################################### Debug In/Output function ########################################### */\r
+/**\r
+ \ingroup CMSIS_Core_FunctionInterface\r
+ \defgroup CMSIS_core_DebugFunctions ITM Functions\r
+ \brief Functions that access the ITM debug interface.\r
+ @{\r
+ */\r
+\r
+extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters. */\r
+#define ITM_RXBUFFER_EMPTY ((int32_t)0x5AA55AA5U) /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */\r
+\r
+\r
+/**\r
+ \brief ITM Send Character\r
+ \details Transmits a character via the ITM channel 0, and\r
+ \li Just returns when no debugger is connected that has booked the output.\r
+ \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted.\r
+ \param [in] ch Character to transmit.\r
+ \returns Character to transmit.\r
+ */\r
+__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch)\r
+{\r
+ if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) && /* ITM enabled */\r
+ ((ITM->TER & 1UL ) != 0UL) ) /* ITM Port #0 enabled */\r
+ {\r
+ while (ITM->PORT[0U].u32 == 0UL)\r
+ {\r
+ __NOP();\r
+ }\r
+ ITM->PORT[0U].u8 = (uint8_t)ch;\r
+ }\r
+ return (ch);\r
+}\r
+\r
+\r
+/**\r
+ \brief ITM Receive Character\r
+ \details Inputs a character via the external variable \ref ITM_RxBuffer.\r
+ \return Received character.\r
+ \return -1 No character pending.\r
+ */\r
+__STATIC_INLINE int32_t ITM_ReceiveChar (void)\r
+{\r
+ int32_t ch = -1; /* no character available */\r
+\r
+ if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY)\r
+ {\r
+ ch = ITM_RxBuffer;\r
+ ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */\r
+ }\r
+\r
+ return (ch);\r
+}\r
+\r
+\r
+/**\r
+ \brief ITM Check Character\r
+ \details Checks whether a character is pending for reading in the variable \ref ITM_RxBuffer.\r
+ \return 0 No character available.\r
+ \return 1 Character available.\r
+ */\r
+__STATIC_INLINE int32_t ITM_CheckChar (void)\r
+{\r
+\r
+ if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY)\r
+ {\r
+ return (0); /* no character available */\r
+ }\r
+ else\r
+ {\r
+ return (1); /* character available */\r
+ }\r
+}\r
+\r
+/*@} end of CMSIS_core_DebugFunctions */\r
+\r
+\r
+\r
+\r
+#ifdef __cplusplus\r
+}\r
+#endif\r
+\r
+#endif /* __CORE_CM4_H_DEPENDANT */\r
+\r
+#endif /* __CMSIS_GENERIC */\r
--- /dev/null
+/**************************************************************************//**\r
+ * @file core_cm7.h\r
+ * @brief CMSIS Cortex-M7 Core Peripheral Access Layer Header File\r
+ * @version V5.0.8\r
+ * @date 04. June 2018\r
+ ******************************************************************************/\r
+/*\r
+ * Copyright (c) 2009-2018 Arm Limited. All rights reserved.\r
+ *\r
+ * SPDX-License-Identifier: Apache-2.0\r
+ *\r
+ * Licensed under the Apache License, Version 2.0 (the License); you may\r
+ * not use this file except in compliance with the License.\r
+ * You may obtain a copy of the License at\r
+ *\r
+ * www.apache.org/licenses/LICENSE-2.0\r
+ *\r
+ * Unless required by applicable law or agreed to in writing, software\r
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT\r
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\r
+ * See the License for the specific language governing permissions and\r
+ * limitations under the License.\r
+ */\r
+\r
+#if defined ( __ICCARM__ )\r
+ #pragma system_include /* treat file as system include file for MISRA check */\r
+#elif defined (__clang__)\r
+ #pragma clang system_header /* treat file as system include file */\r
+#endif\r
+\r
+#ifndef __CORE_CM7_H_GENERIC\r
+#define __CORE_CM7_H_GENERIC\r
+\r
+#include <stdint.h>\r
+\r
+#ifdef __cplusplus\r
+ extern "C" {\r
+#endif\r
+\r
+/**\r
+ \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions\r
+ CMSIS violates the following MISRA-C:2004 rules:\r
+\r
+ \li Required Rule 8.5, object/function definition in header file.<br>\r
+ Function definitions in header files are used to allow 'inlining'.\r
+\r
+ \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>\r
+ Unions are used for effective representation of core registers.\r
+\r
+ \li Advisory Rule 19.7, Function-like macro defined.<br>\r
+ Function-like macros are used to allow more efficient code.\r
+ */\r
+\r
+\r
+/*******************************************************************************\r
+ * CMSIS definitions\r
+ ******************************************************************************/\r
+/**\r
+ \ingroup Cortex_M7\r
+ @{\r
+ */\r
+\r
+#include "cmsis_version.h"\r
+\r
+/* CMSIS CM7 definitions */\r
+#define __CM7_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */\r
+#define __CM7_CMSIS_VERSION_SUB ( __CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */\r
+#define __CM7_CMSIS_VERSION ((__CM7_CMSIS_VERSION_MAIN << 16U) | \\r
+ __CM7_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */\r
+\r
+#define __CORTEX_M (7U) /*!< Cortex-M Core */\r
+\r
+/** __FPU_USED indicates whether an FPU is used or not.\r
+ For this, __FPU_PRESENT has to be checked prior to making use of FPU specific registers and functions.\r
+*/\r
+#if defined ( __CC_ARM )\r
+ #if defined __TARGET_FPU_VFP\r
+ #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)\r
+ #define __FPU_USED 1U\r
+ #else\r
+ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"\r
+ #define __FPU_USED 0U\r
+ #endif\r
+ #else\r
+ #define __FPU_USED 0U\r
+ #endif\r
+\r
+#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)\r
+ #if defined __ARM_PCS_VFP\r
+ #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)\r
+ #define __FPU_USED 1U\r
+ #else\r
+ #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"\r
+ #define __FPU_USED 0U\r
+ #endif\r
+ #else\r
+ #define __FPU_USED 0U\r
+ #endif\r
+\r
+#elif defined ( __GNUC__ )\r
+ #if defined (__VFP_FP__) && !defined(__SOFTFP__)\r
+ #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)\r
+ #define __FPU_USED 1U\r
+ #else\r
+ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"\r
+ #define __FPU_USED 0U\r
+ #endif\r
+ #else\r
+ #define __FPU_USED 0U\r
+ #endif\r
+\r
+#elif defined ( __ICCARM__ )\r
+ #if defined __ARMVFP__\r
+ #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)\r
+ #define __FPU_USED 1U\r
+ #else\r
+ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"\r
+ #define __FPU_USED 0U\r
+ #endif\r
+ #else\r
+ #define __FPU_USED 0U\r
+ #endif\r
+\r
+#elif defined ( __TI_ARM__ )\r
+ #if defined __TI_VFP_SUPPORT__\r
+ #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)\r
+ #define __FPU_USED 1U\r
+ #else\r
+ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"\r
+ #define __FPU_USED 0U\r
+ #endif\r
+ #else\r
+ #define __FPU_USED 0U\r
+ #endif\r
+\r
+#elif defined ( __TASKING__ )\r
+ #if defined __FPU_VFP__\r
+ #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)\r
+ #define __FPU_USED 1U\r
+ #else\r
+ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"\r
+ #define __FPU_USED 0U\r
+ #endif\r
+ #else\r
+ #define __FPU_USED 0U\r
+ #endif\r
+\r
+#elif defined ( __CSMC__ )\r
+ #if ( __CSMC__ & 0x400U)\r
+ #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)\r
+ #define __FPU_USED 1U\r
+ #else\r
+ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"\r
+ #define __FPU_USED 0U\r
+ #endif\r
+ #else\r
+ #define __FPU_USED 0U\r
+ #endif\r
+\r
+#endif\r
+\r
+#include "cmsis_compiler.h" /* CMSIS compiler specific defines */\r
+\r
+\r
+#ifdef __cplusplus\r
+}\r
+#endif\r
+\r
+#endif /* __CORE_CM7_H_GENERIC */\r
+\r
+#ifndef __CMSIS_GENERIC\r
+\r
+#ifndef __CORE_CM7_H_DEPENDANT\r
+#define __CORE_CM7_H_DEPENDANT\r
+\r
+#ifdef __cplusplus\r
+ extern "C" {\r
+#endif\r
+\r
+/* check device defines and use defaults */\r
+#if defined __CHECK_DEVICE_DEFINES\r
+ #ifndef __CM7_REV\r
+ #define __CM7_REV 0x0000U\r
+ #warning "__CM7_REV not defined in device header file; using default!"\r
+ #endif\r
+\r
+ #ifndef __FPU_PRESENT\r
+ #define __FPU_PRESENT 0U\r
+ #warning "__FPU_PRESENT not defined in device header file; using default!"\r
+ #endif\r
+\r
+ #ifndef __MPU_PRESENT\r
+ #define __MPU_PRESENT 0U\r
+ #warning "__MPU_PRESENT not defined in device header file; using default!"\r
+ #endif\r
+\r
+ #ifndef __ICACHE_PRESENT\r
+ #define __ICACHE_PRESENT 0U\r
+ #warning "__ICACHE_PRESENT not defined in device header file; using default!"\r
+ #endif\r
+\r
+ #ifndef __DCACHE_PRESENT\r
+ #define __DCACHE_PRESENT 0U\r
+ #warning "__DCACHE_PRESENT not defined in device header file; using default!"\r
+ #endif\r
+\r
+ #ifndef __DTCM_PRESENT\r
+ #define __DTCM_PRESENT 0U\r
+ #warning "__DTCM_PRESENT not defined in device header file; using default!"\r
+ #endif\r
+\r
+ #ifndef __NVIC_PRIO_BITS\r
+ #define __NVIC_PRIO_BITS 3U\r
+ #warning "__NVIC_PRIO_BITS not defined in device header file; using default!"\r
+ #endif\r
+\r
+ #ifndef __Vendor_SysTickConfig\r
+ #define __Vendor_SysTickConfig 0U\r
+ #warning "__Vendor_SysTickConfig not defined in device header file; using default!"\r
+ #endif\r
+#endif\r
+\r
+/* IO definitions (access restrictions to peripheral registers) */\r
+/**\r
+ \defgroup CMSIS_glob_defs CMSIS Global Defines\r
+\r
+ <strong>IO Type Qualifiers</strong> are used\r
+ \li to specify the access to peripheral variables.\r
+ \li for automatic generation of peripheral register debug information.\r
+*/\r
+#ifdef __cplusplus\r
+ #define __I volatile /*!< Defines 'read only' permissions */\r
+#else\r
+ #define __I volatile const /*!< Defines 'read only' permissions */\r
+#endif\r
+#define __O volatile /*!< Defines 'write only' permissions */\r
+#define __IO volatile /*!< Defines 'read / write' permissions */\r
+\r
+/* following defines should be used for structure members */\r
+#define __IM volatile const /*! Defines 'read only' structure member permissions */\r
+#define __OM volatile /*! Defines 'write only' structure member permissions */\r
+#define __IOM volatile /*! Defines 'read / write' structure member permissions */\r
+\r
+/*@} end of group Cortex_M7 */\r
+\r
+\r
+\r
+/*******************************************************************************\r
+ * Register Abstraction\r
+ Core Register contain:\r
+ - Core Register\r
+ - Core NVIC Register\r
+ - Core SCB Register\r
+ - Core SysTick Register\r
+ - Core Debug Register\r
+ - Core MPU Register\r
+ - Core FPU Register\r
+ ******************************************************************************/\r
+/**\r
+ \defgroup CMSIS_core_register Defines and Type Definitions\r
+ \brief Type definitions and defines for Cortex-M processor based devices.\r
+*/\r
+\r
+/**\r
+ \ingroup CMSIS_core_register\r
+ \defgroup CMSIS_CORE Status and Control Registers\r
+ \brief Core Register type definitions.\r
+ @{\r
+ */\r
+\r
+/**\r
+ \brief Union type to access the Application Program Status Register (APSR).\r
+ */\r
+typedef union\r
+{\r
+ struct\r
+ {\r
+ uint32_t _reserved0:16; /*!< bit: 0..15 Reserved */\r
+ uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */\r
+ uint32_t _reserved1:7; /*!< bit: 20..26 Reserved */\r
+ uint32_t Q:1; /*!< bit: 27 Saturation condition flag */\r
+ uint32_t V:1; /*!< bit: 28 Overflow condition code flag */\r
+ uint32_t C:1; /*!< bit: 29 Carry condition code flag */\r
+ uint32_t Z:1; /*!< bit: 30 Zero condition code flag */\r
+ uint32_t N:1; /*!< bit: 31 Negative condition code flag */\r
+ } b; /*!< Structure used for bit access */\r
+ uint32_t w; /*!< Type used for word access */\r
+} APSR_Type;\r
+\r
+/* APSR Register Definitions */\r
+#define APSR_N_Pos 31U /*!< APSR: N Position */\r
+#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */\r
+\r
+#define APSR_Z_Pos 30U /*!< APSR: Z Position */\r
+#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */\r
+\r
+#define APSR_C_Pos 29U /*!< APSR: C Position */\r
+#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */\r
+\r
+#define APSR_V_Pos 28U /*!< APSR: V Position */\r
+#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */\r
+\r
+#define APSR_Q_Pos 27U /*!< APSR: Q Position */\r
+#define APSR_Q_Msk (1UL << APSR_Q_Pos) /*!< APSR: Q Mask */\r
+\r
+#define APSR_GE_Pos 16U /*!< APSR: GE Position */\r
+#define APSR_GE_Msk (0xFUL << APSR_GE_Pos) /*!< APSR: GE Mask */\r
+\r
+\r
+/**\r
+ \brief Union type to access the Interrupt Program Status Register (IPSR).\r
+ */\r
+typedef union\r
+{\r
+ struct\r
+ {\r
+ uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */\r
+ uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */\r
+ } b; /*!< Structure used for bit access */\r
+ uint32_t w; /*!< Type used for word access */\r
+} IPSR_Type;\r
+\r
+/* IPSR Register Definitions */\r
+#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */\r
+#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */\r
+\r
+\r
+/**\r
+ \brief Union type to access the Special-Purpose Program Status Registers (xPSR).\r
+ */\r
+typedef union\r
+{\r
+ struct\r
+ {\r
+ uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */\r
+ uint32_t _reserved0:1; /*!< bit: 9 Reserved */\r
+ uint32_t ICI_IT_1:6; /*!< bit: 10..15 ICI/IT part 1 */\r
+ uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */\r
+ uint32_t _reserved1:4; /*!< bit: 20..23 Reserved */\r
+ uint32_t T:1; /*!< bit: 24 Thumb bit */\r
+ uint32_t ICI_IT_2:2; /*!< bit: 25..26 ICI/IT part 2 */\r
+ uint32_t Q:1; /*!< bit: 27 Saturation condition flag */\r
+ uint32_t V:1; /*!< bit: 28 Overflow condition code flag */\r
+ uint32_t C:1; /*!< bit: 29 Carry condition code flag */\r
+ uint32_t Z:1; /*!< bit: 30 Zero condition code flag */\r
+ uint32_t N:1; /*!< bit: 31 Negative condition code flag */\r
+ } b; /*!< Structure used for bit access */\r
+ uint32_t w; /*!< Type used for word access */\r
+} xPSR_Type;\r
+\r
+/* xPSR Register Definitions */\r
+#define xPSR_N_Pos 31U /*!< xPSR: N Position */\r
+#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */\r
+\r
+#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */\r
+#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */\r
+\r
+#define xPSR_C_Pos 29U /*!< xPSR: C Position */\r
+#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */\r
+\r
+#define xPSR_V_Pos 28U /*!< xPSR: V Position */\r
+#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */\r
+\r
+#define xPSR_Q_Pos 27U /*!< xPSR: Q Position */\r
+#define xPSR_Q_Msk (1UL << xPSR_Q_Pos) /*!< xPSR: Q Mask */\r
+\r
+#define xPSR_ICI_IT_2_Pos 25U /*!< xPSR: ICI/IT part 2 Position */\r
+#define xPSR_ICI_IT_2_Msk (3UL << xPSR_ICI_IT_2_Pos) /*!< xPSR: ICI/IT part 2 Mask */\r
+\r
+#define xPSR_T_Pos 24U /*!< xPSR: T Position */\r
+#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */\r
+\r
+#define xPSR_GE_Pos 16U /*!< xPSR: GE Position */\r
+#define xPSR_GE_Msk (0xFUL << xPSR_GE_Pos) /*!< xPSR: GE Mask */\r
+\r
+#define xPSR_ICI_IT_1_Pos 10U /*!< xPSR: ICI/IT part 1 Position */\r
+#define xPSR_ICI_IT_1_Msk (0x3FUL << xPSR_ICI_IT_1_Pos) /*!< xPSR: ICI/IT part 1 Mask */\r
+\r
+#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */\r
+#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */\r
+\r
+\r
+/**\r
+ \brief Union type to access the Control Registers (CONTROL).\r
+ */\r
+typedef union\r
+{\r
+ struct\r
+ {\r
+ uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */\r
+ uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */\r
+ uint32_t FPCA:1; /*!< bit: 2 FP extension active flag */\r
+ uint32_t _reserved0:29; /*!< bit: 3..31 Reserved */\r
+ } b; /*!< Structure used for bit access */\r
+ uint32_t w; /*!< Type used for word access */\r
+} CONTROL_Type;\r
+\r
+/* CONTROL Register Definitions */\r
+#define CONTROL_FPCA_Pos 2U /*!< CONTROL: FPCA Position */\r
+#define CONTROL_FPCA_Msk (1UL << CONTROL_FPCA_Pos) /*!< CONTROL: FPCA Mask */\r
+\r
+#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */\r
+#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */\r
+\r
+#define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */\r
+#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */\r
+\r
+/*@} end of group CMSIS_CORE */\r
+\r
+\r
+/**\r
+ \ingroup CMSIS_core_register\r
+ \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC)\r
+ \brief Type definitions for the NVIC Registers\r
+ @{\r
+ */\r
+\r
+/**\r
+ \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC).\r
+ */\r
+typedef struct\r
+{\r
+ __IOM uint32_t ISER[8U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */\r
+ uint32_t RESERVED0[24U];\r
+ __IOM uint32_t ICER[8U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */\r
+ uint32_t RSERVED1[24U];\r
+ __IOM uint32_t ISPR[8U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */\r
+ uint32_t RESERVED2[24U];\r
+ __IOM uint32_t ICPR[8U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */\r
+ uint32_t RESERVED3[24U];\r
+ __IOM uint32_t IABR[8U]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */\r
+ uint32_t RESERVED4[56U];\r
+ __IOM uint8_t IP[240U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */\r
+ uint32_t RESERVED5[644U];\r
+ __OM uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */\r
+} NVIC_Type;\r
+\r
+/* Software Triggered Interrupt Register Definitions */\r
+#define NVIC_STIR_INTID_Pos 0U /*!< STIR: INTLINESNUM Position */\r
+#define NVIC_STIR_INTID_Msk (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/) /*!< STIR: INTLINESNUM Mask */\r
+\r
+/*@} end of group CMSIS_NVIC */\r
+\r
+\r
+/**\r
+ \ingroup CMSIS_core_register\r
+ \defgroup CMSIS_SCB System Control Block (SCB)\r
+ \brief Type definitions for the System Control Block Registers\r
+ @{\r
+ */\r
+\r
+/**\r
+ \brief Structure type to access the System Control Block (SCB).\r
+ */\r
+typedef struct\r
+{\r
+ __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */\r
+ __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */\r
+ __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */\r
+ __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */\r
+ __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */\r
+ __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */\r
+ __IOM uint8_t SHPR[12U]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */\r
+ __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */\r
+ __IOM uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */\r
+ __IOM uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */\r
+ __IOM uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */\r
+ __IOM uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */\r
+ __IOM uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */\r
+ __IOM uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */\r
+ __IM uint32_t ID_PFR[2U]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */\r
+ __IM uint32_t ID_DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */\r
+ __IM uint32_t ID_AFR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */\r
+ __IM uint32_t ID_MFR[4U]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */\r
+ __IM uint32_t ID_ISAR[5U]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */\r
+ uint32_t RESERVED0[1U];\r
+ __IM uint32_t CLIDR; /*!< Offset: 0x078 (R/ ) Cache Level ID register */\r
+ __IM uint32_t CTR; /*!< Offset: 0x07C (R/ ) Cache Type register */\r
+ __IM uint32_t CCSIDR; /*!< Offset: 0x080 (R/ ) Cache Size ID Register */\r
+ __IOM uint32_t CSSELR; /*!< Offset: 0x084 (R/W) Cache Size Selection Register */\r
+ __IOM uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */\r
+ uint32_t RESERVED3[93U];\r
+ __OM uint32_t STIR; /*!< Offset: 0x200 ( /W) Software Triggered Interrupt Register */\r
+ uint32_t RESERVED4[15U];\r
+ __IM uint32_t MVFR0; /*!< Offset: 0x240 (R/ ) Media and VFP Feature Register 0 */\r
+ __IM uint32_t MVFR1; /*!< Offset: 0x244 (R/ ) Media and VFP Feature Register 1 */\r
+ __IM uint32_t MVFR2; /*!< Offset: 0x248 (R/ ) Media and VFP Feature Register 2 */\r
+ uint32_t RESERVED5[1U];\r
+ __OM uint32_t ICIALLU; /*!< Offset: 0x250 ( /W) I-Cache Invalidate All to PoU */\r
+ uint32_t RESERVED6[1U];\r
+ __OM uint32_t ICIMVAU; /*!< Offset: 0x258 ( /W) I-Cache Invalidate by MVA to PoU */\r
+ __OM uint32_t DCIMVAC; /*!< Offset: 0x25C ( /W) D-Cache Invalidate by MVA to PoC */\r
+ __OM uint32_t DCISW; /*!< Offset: 0x260 ( /W) D-Cache Invalidate by Set-way */\r
+ __OM uint32_t DCCMVAU; /*!< Offset: 0x264 ( /W) D-Cache Clean by MVA to PoU */\r
+ __OM uint32_t DCCMVAC; /*!< Offset: 0x268 ( /W) D-Cache Clean by MVA to PoC */\r
+ __OM uint32_t DCCSW; /*!< Offset: 0x26C ( /W) D-Cache Clean by Set-way */\r
+ __OM uint32_t DCCIMVAC; /*!< Offset: 0x270 ( /W) D-Cache Clean and Invalidate by MVA to PoC */\r
+ __OM uint32_t DCCISW; /*!< Offset: 0x274 ( /W) D-Cache Clean and Invalidate by Set-way */\r
+ uint32_t RESERVED7[6U];\r
+ __IOM uint32_t ITCMCR; /*!< Offset: 0x290 (R/W) Instruction Tightly-Coupled Memory Control Register */\r
+ __IOM uint32_t DTCMCR; /*!< Offset: 0x294 (R/W) Data Tightly-Coupled Memory Control Registers */\r
+ __IOM uint32_t AHBPCR; /*!< Offset: 0x298 (R/W) AHBP Control Register */\r
+ __IOM uint32_t CACR; /*!< Offset: 0x29C (R/W) L1 Cache Control Register */\r
+ __IOM uint32_t AHBSCR; /*!< Offset: 0x2A0 (R/W) AHB Slave Control Register */\r
+ uint32_t RESERVED8[1U];\r
+ __IOM uint32_t ABFSR; /*!< Offset: 0x2A8 (R/W) Auxiliary Bus Fault Status Register */\r
+} SCB_Type;\r
+\r
+/* SCB CPUID Register Definitions */\r
+#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */\r
+#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */\r
+\r
+#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */\r
+#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */\r
+\r
+#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */\r
+#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */\r
+\r
+#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */\r
+#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */\r
+\r
+#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */\r
+#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */\r
+\r
+/* SCB Interrupt Control State Register Definitions */\r
+#define SCB_ICSR_NMIPENDSET_Pos 31U /*!< SCB ICSR: NMIPENDSET Position */\r
+#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */\r
+\r
+#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */\r
+#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */\r
+\r
+#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */\r
+#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */\r
+\r
+#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */\r
+#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */\r
+\r
+#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */\r
+#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */\r
+\r
+#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */\r
+#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */\r
+\r
+#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */\r
+#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */\r
+\r
+#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */\r
+#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */\r
+\r
+#define SCB_ICSR_RETTOBASE_Pos 11U /*!< SCB ICSR: RETTOBASE Position */\r
+#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */\r
+\r
+#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */\r
+#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */\r
+\r
+/* SCB Vector Table Offset Register Definitions */\r
+#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */\r
+#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */\r
+\r
+/* SCB Application Interrupt and Reset Control Register Definitions */\r
+#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */\r
+#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */\r
+\r
+#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */\r
+#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */\r
+\r
+#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */\r
+#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */\r
+\r
+#define SCB_AIRCR_PRIGROUP_Pos 8U /*!< SCB AIRCR: PRIGROUP Position */\r
+#define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */\r
+\r
+#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */\r
+#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */\r
+\r
+#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */\r
+#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */\r
+\r
+#define SCB_AIRCR_VECTRESET_Pos 0U /*!< SCB AIRCR: VECTRESET Position */\r
+#define SCB_AIRCR_VECTRESET_Msk (1UL /*<< SCB_AIRCR_VECTRESET_Pos*/) /*!< SCB AIRCR: VECTRESET Mask */\r
+\r
+/* SCB System Control Register Definitions */\r
+#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */\r
+#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */\r
+\r
+#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */\r
+#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */\r
+\r
+#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */\r
+#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */\r
+\r
+/* SCB Configuration Control Register Definitions */\r
+#define SCB_CCR_BP_Pos 18U /*!< SCB CCR: Branch prediction enable bit Position */\r
+#define SCB_CCR_BP_Msk (1UL << SCB_CCR_BP_Pos) /*!< SCB CCR: Branch prediction enable bit Mask */\r
+\r
+#define SCB_CCR_IC_Pos 17U /*!< SCB CCR: Instruction cache enable bit Position */\r
+#define SCB_CCR_IC_Msk (1UL << SCB_CCR_IC_Pos) /*!< SCB CCR: Instruction cache enable bit Mask */\r
+\r
+#define SCB_CCR_DC_Pos 16U /*!< SCB CCR: Cache enable bit Position */\r
+#define SCB_CCR_DC_Msk (1UL << SCB_CCR_DC_Pos) /*!< SCB CCR: Cache enable bit Mask */\r
+\r
+#define SCB_CCR_STKALIGN_Pos 9U /*!< SCB CCR: STKALIGN Position */\r
+#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */\r
+\r
+#define SCB_CCR_BFHFNMIGN_Pos 8U /*!< SCB CCR: BFHFNMIGN Position */\r
+#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */\r
+\r
+#define SCB_CCR_DIV_0_TRP_Pos 4U /*!< SCB CCR: DIV_0_TRP Position */\r
+#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */\r
+\r
+#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */\r
+#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */\r
+\r
+#define SCB_CCR_USERSETMPEND_Pos 1U /*!< SCB CCR: USERSETMPEND Position */\r
+#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */\r
+\r
+#define SCB_CCR_NONBASETHRDENA_Pos 0U /*!< SCB CCR: NONBASETHRDENA Position */\r
+#define SCB_CCR_NONBASETHRDENA_Msk (1UL /*<< SCB_CCR_NONBASETHRDENA_Pos*/) /*!< SCB CCR: NONBASETHRDENA Mask */\r
+\r
+/* SCB System Handler Control and State Register Definitions */\r
+#define SCB_SHCSR_USGFAULTENA_Pos 18U /*!< SCB SHCSR: USGFAULTENA Position */\r
+#define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */\r
+\r
+#define SCB_SHCSR_BUSFAULTENA_Pos 17U /*!< SCB SHCSR: BUSFAULTENA Position */\r
+#define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */\r
+\r
+#define SCB_SHCSR_MEMFAULTENA_Pos 16U /*!< SCB SHCSR: MEMFAULTENA Position */\r
+#define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */\r
+\r
+#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */\r
+#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */\r
+\r
+#define SCB_SHCSR_BUSFAULTPENDED_Pos 14U /*!< SCB SHCSR: BUSFAULTPENDED Position */\r
+#define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */\r
+\r
+#define SCB_SHCSR_MEMFAULTPENDED_Pos 13U /*!< SCB SHCSR: MEMFAULTPENDED Position */\r
+#define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */\r
+\r
+#define SCB_SHCSR_USGFAULTPENDED_Pos 12U /*!< SCB SHCSR: USGFAULTPENDED Position */\r
+#define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */\r
+\r
+#define SCB_SHCSR_SYSTICKACT_Pos 11U /*!< SCB SHCSR: SYSTICKACT Position */\r
+#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */\r
+\r
+#define SCB_SHCSR_PENDSVACT_Pos 10U /*!< SCB SHCSR: PENDSVACT Position */\r
+#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */\r
+\r
+#define SCB_SHCSR_MONITORACT_Pos 8U /*!< SCB SHCSR: MONITORACT Position */\r
+#define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */\r
+\r
+#define SCB_SHCSR_SVCALLACT_Pos 7U /*!< SCB SHCSR: SVCALLACT Position */\r
+#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */\r
+\r
+#define SCB_SHCSR_USGFAULTACT_Pos 3U /*!< SCB SHCSR: USGFAULTACT Position */\r
+#define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */\r
+\r
+#define SCB_SHCSR_BUSFAULTACT_Pos 1U /*!< SCB SHCSR: BUSFAULTACT Position */\r
+#define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */\r
+\r
+#define SCB_SHCSR_MEMFAULTACT_Pos 0U /*!< SCB SHCSR: MEMFAULTACT Position */\r
+#define SCB_SHCSR_MEMFAULTACT_Msk (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/) /*!< SCB SHCSR: MEMFAULTACT Mask */\r
+\r
+/* SCB Configurable Fault Status Register Definitions */\r
+#define SCB_CFSR_USGFAULTSR_Pos 16U /*!< SCB CFSR: Usage Fault Status Register Position */\r
+#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */\r
+\r
+#define SCB_CFSR_BUSFAULTSR_Pos 8U /*!< SCB CFSR: Bus Fault Status Register Position */\r
+#define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */\r
+\r
+#define SCB_CFSR_MEMFAULTSR_Pos 0U /*!< SCB CFSR: Memory Manage Fault Status Register Position */\r
+#define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */\r
+\r
+/* MemManage Fault Status Register (part of SCB Configurable Fault Status Register) */\r
+#define SCB_CFSR_MMARVALID_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 7U) /*!< SCB CFSR (MMFSR): MMARVALID Position */\r
+#define SCB_CFSR_MMARVALID_Msk (1UL << SCB_CFSR_MMARVALID_Pos) /*!< SCB CFSR (MMFSR): MMARVALID Mask */\r
+\r
+#define SCB_CFSR_MLSPERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 5U) /*!< SCB CFSR (MMFSR): MLSPERR Position */\r
+#define SCB_CFSR_MLSPERR_Msk (1UL << SCB_CFSR_MLSPERR_Pos) /*!< SCB CFSR (MMFSR): MLSPERR Mask */\r
+\r
+#define SCB_CFSR_MSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 4U) /*!< SCB CFSR (MMFSR): MSTKERR Position */\r
+#define SCB_CFSR_MSTKERR_Msk (1UL << SCB_CFSR_MSTKERR_Pos) /*!< SCB CFSR (MMFSR): MSTKERR Mask */\r
+\r
+#define SCB_CFSR_MUNSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 3U) /*!< SCB CFSR (MMFSR): MUNSTKERR Position */\r
+#define SCB_CFSR_MUNSTKERR_Msk (1UL << SCB_CFSR_MUNSTKERR_Pos) /*!< SCB CFSR (MMFSR): MUNSTKERR Mask */\r
+\r
+#define SCB_CFSR_DACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 1U) /*!< SCB CFSR (MMFSR): DACCVIOL Position */\r
+#define SCB_CFSR_DACCVIOL_Msk (1UL << SCB_CFSR_DACCVIOL_Pos) /*!< SCB CFSR (MMFSR): DACCVIOL Mask */\r
+\r
+#define SCB_CFSR_IACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 0U) /*!< SCB CFSR (MMFSR): IACCVIOL Position */\r
+#define SCB_CFSR_IACCVIOL_Msk (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/) /*!< SCB CFSR (MMFSR): IACCVIOL Mask */\r
+\r
+/* BusFault Status Register (part of SCB Configurable Fault Status Register) */\r
+#define SCB_CFSR_BFARVALID_Pos (SCB_CFSR_BUSFAULTSR_Pos + 7U) /*!< SCB CFSR (BFSR): BFARVALID Position */\r
+#define SCB_CFSR_BFARVALID_Msk (1UL << SCB_CFSR_BFARVALID_Pos) /*!< SCB CFSR (BFSR): BFARVALID Mask */\r
+\r
+#define SCB_CFSR_LSPERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 5U) /*!< SCB CFSR (BFSR): LSPERR Position */\r
+#define SCB_CFSR_LSPERR_Msk (1UL << SCB_CFSR_LSPERR_Pos) /*!< SCB CFSR (BFSR): LSPERR Mask */\r
+\r
+#define SCB_CFSR_STKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 4U) /*!< SCB CFSR (BFSR): STKERR Position */\r
+#define SCB_CFSR_STKERR_Msk (1UL << SCB_CFSR_STKERR_Pos) /*!< SCB CFSR (BFSR): STKERR Mask */\r
+\r
+#define SCB_CFSR_UNSTKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 3U) /*!< SCB CFSR (BFSR): UNSTKERR Position */\r
+#define SCB_CFSR_UNSTKERR_Msk (1UL << SCB_CFSR_UNSTKERR_Pos) /*!< SCB CFSR (BFSR): UNSTKERR Mask */\r
+\r
+#define SCB_CFSR_IMPRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 2U) /*!< SCB CFSR (BFSR): IMPRECISERR Position */\r
+#define SCB_CFSR_IMPRECISERR_Msk (1UL << SCB_CFSR_IMPRECISERR_Pos) /*!< SCB CFSR (BFSR): IMPRECISERR Mask */\r
+\r
+#define SCB_CFSR_PRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 1U) /*!< SCB CFSR (BFSR): PRECISERR Position */\r
+#define SCB_CFSR_PRECISERR_Msk (1UL << SCB_CFSR_PRECISERR_Pos) /*!< SCB CFSR (BFSR): PRECISERR Mask */\r
+\r
+#define SCB_CFSR_IBUSERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 0U) /*!< SCB CFSR (BFSR): IBUSERR Position */\r
+#define SCB_CFSR_IBUSERR_Msk (1UL << SCB_CFSR_IBUSERR_Pos) /*!< SCB CFSR (BFSR): IBUSERR Mask */\r
+\r
+/* UsageFault Status Register (part of SCB Configurable Fault Status Register) */\r
+#define SCB_CFSR_DIVBYZERO_Pos (SCB_CFSR_USGFAULTSR_Pos + 9U) /*!< SCB CFSR (UFSR): DIVBYZERO Position */\r
+#define SCB_CFSR_DIVBYZERO_Msk (1UL << SCB_CFSR_DIVBYZERO_Pos) /*!< SCB CFSR (UFSR): DIVBYZERO Mask */\r
+\r
+#define SCB_CFSR_UNALIGNED_Pos (SCB_CFSR_USGFAULTSR_Pos + 8U) /*!< SCB CFSR (UFSR): UNALIGNED Position */\r
+#define SCB_CFSR_UNALIGNED_Msk (1UL << SCB_CFSR_UNALIGNED_Pos) /*!< SCB CFSR (UFSR): UNALIGNED Mask */\r
+\r
+#define SCB_CFSR_NOCP_Pos (SCB_CFSR_USGFAULTSR_Pos + 3U) /*!< SCB CFSR (UFSR): NOCP Position */\r
+#define SCB_CFSR_NOCP_Msk (1UL << SCB_CFSR_NOCP_Pos) /*!< SCB CFSR (UFSR): NOCP Mask */\r
+\r
+#define SCB_CFSR_INVPC_Pos (SCB_CFSR_USGFAULTSR_Pos + 2U) /*!< SCB CFSR (UFSR): INVPC Position */\r
+#define SCB_CFSR_INVPC_Msk (1UL << SCB_CFSR_INVPC_Pos) /*!< SCB CFSR (UFSR): INVPC Mask */\r
+\r
+#define SCB_CFSR_INVSTATE_Pos (SCB_CFSR_USGFAULTSR_Pos + 1U) /*!< SCB CFSR (UFSR): INVSTATE Position */\r
+#define SCB_CFSR_INVSTATE_Msk (1UL << SCB_CFSR_INVSTATE_Pos) /*!< SCB CFSR (UFSR): INVSTATE Mask */\r
+\r
+#define SCB_CFSR_UNDEFINSTR_Pos (SCB_CFSR_USGFAULTSR_Pos + 0U) /*!< SCB CFSR (UFSR): UNDEFINSTR Position */\r
+#define SCB_CFSR_UNDEFINSTR_Msk (1UL << SCB_CFSR_UNDEFINSTR_Pos) /*!< SCB CFSR (UFSR): UNDEFINSTR Mask */\r
+\r
+/* SCB Hard Fault Status Register Definitions */\r
+#define SCB_HFSR_DEBUGEVT_Pos 31U /*!< SCB HFSR: DEBUGEVT Position */\r
+#define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */\r
+\r
+#define SCB_HFSR_FORCED_Pos 30U /*!< SCB HFSR: FORCED Position */\r
+#define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */\r
+\r
+#define SCB_HFSR_VECTTBL_Pos 1U /*!< SCB HFSR: VECTTBL Position */\r
+#define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */\r
+\r
+/* SCB Debug Fault Status Register Definitions */\r
+#define SCB_DFSR_EXTERNAL_Pos 4U /*!< SCB DFSR: EXTERNAL Position */\r
+#define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */\r
+\r
+#define SCB_DFSR_VCATCH_Pos 3U /*!< SCB DFSR: VCATCH Position */\r
+#define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */\r
+\r
+#define SCB_DFSR_DWTTRAP_Pos 2U /*!< SCB DFSR: DWTTRAP Position */\r
+#define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */\r
+\r
+#define SCB_DFSR_BKPT_Pos 1U /*!< SCB DFSR: BKPT Position */\r
+#define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */\r
+\r
+#define SCB_DFSR_HALTED_Pos 0U /*!< SCB DFSR: HALTED Position */\r
+#define SCB_DFSR_HALTED_Msk (1UL /*<< SCB_DFSR_HALTED_Pos*/) /*!< SCB DFSR: HALTED Mask */\r
+\r
+/* SCB Cache Level ID Register Definitions */\r
+#define SCB_CLIDR_LOUU_Pos 27U /*!< SCB CLIDR: LoUU Position */\r
+#define SCB_CLIDR_LOUU_Msk (7UL << SCB_CLIDR_LOUU_Pos) /*!< SCB CLIDR: LoUU Mask */\r
+\r
+#define SCB_CLIDR_LOC_Pos 24U /*!< SCB CLIDR: LoC Position */\r
+#define SCB_CLIDR_LOC_Msk (7UL << SCB_CLIDR_LOC_Pos) /*!< SCB CLIDR: LoC Mask */\r
+\r
+/* SCB Cache Type Register Definitions */\r
+#define SCB_CTR_FORMAT_Pos 29U /*!< SCB CTR: Format Position */\r
+#define SCB_CTR_FORMAT_Msk (7UL << SCB_CTR_FORMAT_Pos) /*!< SCB CTR: Format Mask */\r
+\r
+#define SCB_CTR_CWG_Pos 24U /*!< SCB CTR: CWG Position */\r
+#define SCB_CTR_CWG_Msk (0xFUL << SCB_CTR_CWG_Pos) /*!< SCB CTR: CWG Mask */\r
+\r
+#define SCB_CTR_ERG_Pos 20U /*!< SCB CTR: ERG Position */\r
+#define SCB_CTR_ERG_Msk (0xFUL << SCB_CTR_ERG_Pos) /*!< SCB CTR: ERG Mask */\r
+\r
+#define SCB_CTR_DMINLINE_Pos 16U /*!< SCB CTR: DminLine Position */\r
+#define SCB_CTR_DMINLINE_Msk (0xFUL << SCB_CTR_DMINLINE_Pos) /*!< SCB CTR: DminLine Mask */\r
+\r
+#define SCB_CTR_IMINLINE_Pos 0U /*!< SCB CTR: ImInLine Position */\r
+#define SCB_CTR_IMINLINE_Msk (0xFUL /*<< SCB_CTR_IMINLINE_Pos*/) /*!< SCB CTR: ImInLine Mask */\r
+\r
+/* SCB Cache Size ID Register Definitions */\r
+#define SCB_CCSIDR_WT_Pos 31U /*!< SCB CCSIDR: WT Position */\r
+#define SCB_CCSIDR_WT_Msk (1UL << SCB_CCSIDR_WT_Pos) /*!< SCB CCSIDR: WT Mask */\r
+\r
+#define SCB_CCSIDR_WB_Pos 30U /*!< SCB CCSIDR: WB Position */\r
+#define SCB_CCSIDR_WB_Msk (1UL << SCB_CCSIDR_WB_Pos) /*!< SCB CCSIDR: WB Mask */\r
+\r
+#define SCB_CCSIDR_RA_Pos 29U /*!< SCB CCSIDR: RA Position */\r
+#define SCB_CCSIDR_RA_Msk (1UL << SCB_CCSIDR_RA_Pos) /*!< SCB CCSIDR: RA Mask */\r
+\r
+#define SCB_CCSIDR_WA_Pos 28U /*!< SCB CCSIDR: WA Position */\r
+#define SCB_CCSIDR_WA_Msk (1UL << SCB_CCSIDR_WA_Pos) /*!< SCB CCSIDR: WA Mask */\r
+\r
+#define SCB_CCSIDR_NUMSETS_Pos 13U /*!< SCB CCSIDR: NumSets Position */\r
+#define SCB_CCSIDR_NUMSETS_Msk (0x7FFFUL << SCB_CCSIDR_NUMSETS_Pos) /*!< SCB CCSIDR: NumSets Mask */\r
+\r
+#define SCB_CCSIDR_ASSOCIATIVITY_Pos 3U /*!< SCB CCSIDR: Associativity Position */\r
+#define SCB_CCSIDR_ASSOCIATIVITY_Msk (0x3FFUL << SCB_CCSIDR_ASSOCIATIVITY_Pos) /*!< SCB CCSIDR: Associativity Mask */\r
+\r
+#define SCB_CCSIDR_LINESIZE_Pos 0U /*!< SCB CCSIDR: LineSize Position */\r
+#define SCB_CCSIDR_LINESIZE_Msk (7UL /*<< SCB_CCSIDR_LINESIZE_Pos*/) /*!< SCB CCSIDR: LineSize Mask */\r
+\r
+/* SCB Cache Size Selection Register Definitions */\r
+#define SCB_CSSELR_LEVEL_Pos 1U /*!< SCB CSSELR: Level Position */\r
+#define SCB_CSSELR_LEVEL_Msk (7UL << SCB_CSSELR_LEVEL_Pos) /*!< SCB CSSELR: Level Mask */\r
+\r
+#define SCB_CSSELR_IND_Pos 0U /*!< SCB CSSELR: InD Position */\r
+#define SCB_CSSELR_IND_Msk (1UL /*<< SCB_CSSELR_IND_Pos*/) /*!< SCB CSSELR: InD Mask */\r
+\r
+/* SCB Software Triggered Interrupt Register Definitions */\r
+#define SCB_STIR_INTID_Pos 0U /*!< SCB STIR: INTID Position */\r
+#define SCB_STIR_INTID_Msk (0x1FFUL /*<< SCB_STIR_INTID_Pos*/) /*!< SCB STIR: INTID Mask */\r
+\r
+/* SCB D-Cache Invalidate by Set-way Register Definitions */\r
+#define SCB_DCISW_WAY_Pos 30U /*!< SCB DCISW: Way Position */\r
+#define SCB_DCISW_WAY_Msk (3UL << SCB_DCISW_WAY_Pos) /*!< SCB DCISW: Way Mask */\r
+\r
+#define SCB_DCISW_SET_Pos 5U /*!< SCB DCISW: Set Position */\r
+#define SCB_DCISW_SET_Msk (0x1FFUL << SCB_DCISW_SET_Pos) /*!< SCB DCISW: Set Mask */\r
+\r
+/* SCB D-Cache Clean by Set-way Register Definitions */\r
+#define SCB_DCCSW_WAY_Pos 30U /*!< SCB DCCSW: Way Position */\r
+#define SCB_DCCSW_WAY_Msk (3UL << SCB_DCCSW_WAY_Pos) /*!< SCB DCCSW: Way Mask */\r
+\r
+#define SCB_DCCSW_SET_Pos 5U /*!< SCB DCCSW: Set Position */\r
+#define SCB_DCCSW_SET_Msk (0x1FFUL << SCB_DCCSW_SET_Pos) /*!< SCB DCCSW: Set Mask */\r
+\r
+/* SCB D-Cache Clean and Invalidate by Set-way Register Definitions */\r
+#define SCB_DCCISW_WAY_Pos 30U /*!< SCB DCCISW: Way Position */\r
+#define SCB_DCCISW_WAY_Msk (3UL << SCB_DCCISW_WAY_Pos) /*!< SCB DCCISW: Way Mask */\r
+\r
+#define SCB_DCCISW_SET_Pos 5U /*!< SCB DCCISW: Set Position */\r
+#define SCB_DCCISW_SET_Msk (0x1FFUL << SCB_DCCISW_SET_Pos) /*!< SCB DCCISW: Set Mask */\r
+\r
+/* Instruction Tightly-Coupled Memory Control Register Definitions */\r
+#define SCB_ITCMCR_SZ_Pos 3U /*!< SCB ITCMCR: SZ Position */\r
+#define SCB_ITCMCR_SZ_Msk (0xFUL << SCB_ITCMCR_SZ_Pos) /*!< SCB ITCMCR: SZ Mask */\r
+\r
+#define SCB_ITCMCR_RETEN_Pos 2U /*!< SCB ITCMCR: RETEN Position */\r
+#define SCB_ITCMCR_RETEN_Msk (1UL << SCB_ITCMCR_RETEN_Pos) /*!< SCB ITCMCR: RETEN Mask */\r
+\r
+#define SCB_ITCMCR_RMW_Pos 1U /*!< SCB ITCMCR: RMW Position */\r
+#define SCB_ITCMCR_RMW_Msk (1UL << SCB_ITCMCR_RMW_Pos) /*!< SCB ITCMCR: RMW Mask */\r
+\r
+#define SCB_ITCMCR_EN_Pos 0U /*!< SCB ITCMCR: EN Position */\r
+#define SCB_ITCMCR_EN_Msk (1UL /*<< SCB_ITCMCR_EN_Pos*/) /*!< SCB ITCMCR: EN Mask */\r
+\r
+/* Data Tightly-Coupled Memory Control Register Definitions */\r
+#define SCB_DTCMCR_SZ_Pos 3U /*!< SCB DTCMCR: SZ Position */\r
+#define SCB_DTCMCR_SZ_Msk (0xFUL << SCB_DTCMCR_SZ_Pos) /*!< SCB DTCMCR: SZ Mask */\r
+\r
+#define SCB_DTCMCR_RETEN_Pos 2U /*!< SCB DTCMCR: RETEN Position */\r
+#define SCB_DTCMCR_RETEN_Msk (1UL << SCB_DTCMCR_RETEN_Pos) /*!< SCB DTCMCR: RETEN Mask */\r
+\r
+#define SCB_DTCMCR_RMW_Pos 1U /*!< SCB DTCMCR: RMW Position */\r
+#define SCB_DTCMCR_RMW_Msk (1UL << SCB_DTCMCR_RMW_Pos) /*!< SCB DTCMCR: RMW Mask */\r
+\r
+#define SCB_DTCMCR_EN_Pos 0U /*!< SCB DTCMCR: EN Position */\r
+#define SCB_DTCMCR_EN_Msk (1UL /*<< SCB_DTCMCR_EN_Pos*/) /*!< SCB DTCMCR: EN Mask */\r
+\r
+/* AHBP Control Register Definitions */\r
+#define SCB_AHBPCR_SZ_Pos 1U /*!< SCB AHBPCR: SZ Position */\r
+#define SCB_AHBPCR_SZ_Msk (7UL << SCB_AHBPCR_SZ_Pos) /*!< SCB AHBPCR: SZ Mask */\r
+\r
+#define SCB_AHBPCR_EN_Pos 0U /*!< SCB AHBPCR: EN Position */\r
+#define SCB_AHBPCR_EN_Msk (1UL /*<< SCB_AHBPCR_EN_Pos*/) /*!< SCB AHBPCR: EN Mask */\r
+\r
+/* L1 Cache Control Register Definitions */\r
+#define SCB_CACR_FORCEWT_Pos 2U /*!< SCB CACR: FORCEWT Position */\r
+#define SCB_CACR_FORCEWT_Msk (1UL << SCB_CACR_FORCEWT_Pos) /*!< SCB CACR: FORCEWT Mask */\r
+\r
+#define SCB_CACR_ECCEN_Pos 1U /*!< SCB CACR: ECCEN Position */\r
+#define SCB_CACR_ECCEN_Msk (1UL << SCB_CACR_ECCEN_Pos) /*!< SCB CACR: ECCEN Mask */\r
+\r
+#define SCB_CACR_SIWT_Pos 0U /*!< SCB CACR: SIWT Position */\r
+#define SCB_CACR_SIWT_Msk (1UL /*<< SCB_CACR_SIWT_Pos*/) /*!< SCB CACR: SIWT Mask */\r
+\r
+/* AHBS Control Register Definitions */\r
+#define SCB_AHBSCR_INITCOUNT_Pos 11U /*!< SCB AHBSCR: INITCOUNT Position */\r
+#define SCB_AHBSCR_INITCOUNT_Msk (0x1FUL << SCB_AHBPCR_INITCOUNT_Pos) /*!< SCB AHBSCR: INITCOUNT Mask */\r
+\r
+#define SCB_AHBSCR_TPRI_Pos 2U /*!< SCB AHBSCR: TPRI Position */\r
+#define SCB_AHBSCR_TPRI_Msk (0x1FFUL << SCB_AHBPCR_TPRI_Pos) /*!< SCB AHBSCR: TPRI Mask */\r
+\r
+#define SCB_AHBSCR_CTL_Pos 0U /*!< SCB AHBSCR: CTL Position*/\r
+#define SCB_AHBSCR_CTL_Msk (3UL /*<< SCB_AHBPCR_CTL_Pos*/) /*!< SCB AHBSCR: CTL Mask */\r
+\r
+/* Auxiliary Bus Fault Status Register Definitions */\r
+#define SCB_ABFSR_AXIMTYPE_Pos 8U /*!< SCB ABFSR: AXIMTYPE Position*/\r
+#define SCB_ABFSR_AXIMTYPE_Msk (3UL << SCB_ABFSR_AXIMTYPE_Pos) /*!< SCB ABFSR: AXIMTYPE Mask */\r
+\r
+#define SCB_ABFSR_EPPB_Pos 4U /*!< SCB ABFSR: EPPB Position*/\r
+#define SCB_ABFSR_EPPB_Msk (1UL << SCB_ABFSR_EPPB_Pos) /*!< SCB ABFSR: EPPB Mask */\r
+\r
+#define SCB_ABFSR_AXIM_Pos 3U /*!< SCB ABFSR: AXIM Position*/\r
+#define SCB_ABFSR_AXIM_Msk (1UL << SCB_ABFSR_AXIM_Pos) /*!< SCB ABFSR: AXIM Mask */\r
+\r
+#define SCB_ABFSR_AHBP_Pos 2U /*!< SCB ABFSR: AHBP Position*/\r
+#define SCB_ABFSR_AHBP_Msk (1UL << SCB_ABFSR_AHBP_Pos) /*!< SCB ABFSR: AHBP Mask */\r
+\r
+#define SCB_ABFSR_DTCM_Pos 1U /*!< SCB ABFSR: DTCM Position*/\r
+#define SCB_ABFSR_DTCM_Msk (1UL << SCB_ABFSR_DTCM_Pos) /*!< SCB ABFSR: DTCM Mask */\r
+\r
+#define SCB_ABFSR_ITCM_Pos 0U /*!< SCB ABFSR: ITCM Position*/\r
+#define SCB_ABFSR_ITCM_Msk (1UL /*<< SCB_ABFSR_ITCM_Pos*/) /*!< SCB ABFSR: ITCM Mask */\r
+\r
+/*@} end of group CMSIS_SCB */\r
+\r
+\r
+/**\r
+ \ingroup CMSIS_core_register\r
+ \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB)\r
+ \brief Type definitions for the System Control and ID Register not in the SCB\r
+ @{\r
+ */\r
+\r
+/**\r
+ \brief Structure type to access the System Control and ID Register not in the SCB.\r
+ */\r
+typedef struct\r
+{\r
+ uint32_t RESERVED0[1U];\r
+ __IM uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */\r
+ __IOM uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */\r
+} SCnSCB_Type;\r
+\r
+/* Interrupt Controller Type Register Definitions */\r
+#define SCnSCB_ICTR_INTLINESNUM_Pos 0U /*!< ICTR: INTLINESNUM Position */\r
+#define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/) /*!< ICTR: INTLINESNUM Mask */\r
+\r
+/* Auxiliary Control Register Definitions */\r
+#define SCnSCB_ACTLR_DISITMATBFLUSH_Pos 12U /*!< ACTLR: DISITMATBFLUSH Position */\r
+#define SCnSCB_ACTLR_DISITMATBFLUSH_Msk (1UL << SCnSCB_ACTLR_DISITMATBFLUSH_Pos) /*!< ACTLR: DISITMATBFLUSH Mask */\r
+\r
+#define SCnSCB_ACTLR_DISRAMODE_Pos 11U /*!< ACTLR: DISRAMODE Position */\r
+#define SCnSCB_ACTLR_DISRAMODE_Msk (1UL << SCnSCB_ACTLR_DISRAMODE_Pos) /*!< ACTLR: DISRAMODE Mask */\r
+\r
+#define SCnSCB_ACTLR_FPEXCODIS_Pos 10U /*!< ACTLR: FPEXCODIS Position */\r
+#define SCnSCB_ACTLR_FPEXCODIS_Msk (1UL << SCnSCB_ACTLR_FPEXCODIS_Pos) /*!< ACTLR: FPEXCODIS Mask */\r
+\r
+#define SCnSCB_ACTLR_DISFOLD_Pos 2U /*!< ACTLR: DISFOLD Position */\r
+#define SCnSCB_ACTLR_DISFOLD_Msk (1UL << SCnSCB_ACTLR_DISFOLD_Pos) /*!< ACTLR: DISFOLD Mask */\r
+\r
+#define SCnSCB_ACTLR_DISMCYCINT_Pos 0U /*!< ACTLR: DISMCYCINT Position */\r
+#define SCnSCB_ACTLR_DISMCYCINT_Msk (1UL /*<< SCnSCB_ACTLR_DISMCYCINT_Pos*/) /*!< ACTLR: DISMCYCINT Mask */\r
+\r
+/*@} end of group CMSIS_SCnotSCB */\r
+\r
+\r
+/**\r
+ \ingroup CMSIS_core_register\r
+ \defgroup CMSIS_SysTick System Tick Timer (SysTick)\r
+ \brief Type definitions for the System Timer Registers.\r
+ @{\r
+ */\r
+\r
+/**\r
+ \brief Structure type to access the System Timer (SysTick).\r
+ */\r
+typedef struct\r
+{\r
+ __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */\r
+ __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */\r
+ __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */\r
+ __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */\r
+} SysTick_Type;\r
+\r
+/* SysTick Control / Status Register Definitions */\r
+#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */\r
+#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */\r
+\r
+#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */\r
+#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */\r
+\r
+#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */\r
+#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */\r
+\r
+#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */\r
+#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */\r
+\r
+/* SysTick Reload Register Definitions */\r
+#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */\r
+#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */\r
+\r
+/* SysTick Current Register Definitions */\r
+#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */\r
+#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */\r
+\r
+/* SysTick Calibration Register Definitions */\r
+#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */\r
+#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */\r
+\r
+#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */\r
+#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */\r
+\r
+#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */\r
+#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */\r
+\r
+/*@} end of group CMSIS_SysTick */\r
+\r
+\r
+/**\r
+ \ingroup CMSIS_core_register\r
+ \defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM)\r
+ \brief Type definitions for the Instrumentation Trace Macrocell (ITM)\r
+ @{\r
+ */\r
+\r
+/**\r
+ \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM).\r
+ */\r
+typedef struct\r
+{\r
+ __OM union\r
+ {\r
+ __OM uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */\r
+ __OM uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */\r
+ __OM uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */\r
+ } PORT [32U]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */\r
+ uint32_t RESERVED0[864U];\r
+ __IOM uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */\r
+ uint32_t RESERVED1[15U];\r
+ __IOM uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */\r
+ uint32_t RESERVED2[15U];\r
+ __IOM uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */\r
+ uint32_t RESERVED3[29U];\r
+ __OM uint32_t IWR; /*!< Offset: 0xEF8 ( /W) ITM Integration Write Register */\r
+ __IM uint32_t IRR; /*!< Offset: 0xEFC (R/ ) ITM Integration Read Register */\r
+ __IOM uint32_t IMCR; /*!< Offset: 0xF00 (R/W) ITM Integration Mode Control Register */\r
+ uint32_t RESERVED4[43U];\r
+ __OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */\r
+ __IM uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */\r
+ uint32_t RESERVED5[6U];\r
+ __IM uint32_t PID4; /*!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 */\r
+ __IM uint32_t PID5; /*!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 */\r
+ __IM uint32_t PID6; /*!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 */\r
+ __IM uint32_t PID7; /*!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 */\r
+ __IM uint32_t PID0; /*!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 */\r
+ __IM uint32_t PID1; /*!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 */\r
+ __IM uint32_t PID2; /*!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 */\r
+ __IM uint32_t PID3; /*!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 */\r
+ __IM uint32_t CID0; /*!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 */\r
+ __IM uint32_t CID1; /*!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 */\r
+ __IM uint32_t CID2; /*!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 */\r
+ __IM uint32_t CID3; /*!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 */\r
+} ITM_Type;\r
+\r
+/* ITM Trace Privilege Register Definitions */\r
+#define ITM_TPR_PRIVMASK_Pos 0U /*!< ITM TPR: PRIVMASK Position */\r
+#define ITM_TPR_PRIVMASK_Msk (0xFFFFFFFFUL /*<< ITM_TPR_PRIVMASK_Pos*/) /*!< ITM TPR: PRIVMASK Mask */\r
+\r
+/* ITM Trace Control Register Definitions */\r
+#define ITM_TCR_BUSY_Pos 23U /*!< ITM TCR: BUSY Position */\r
+#define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */\r
+\r
+#define ITM_TCR_TraceBusID_Pos 16U /*!< ITM TCR: ATBID Position */\r
+#define ITM_TCR_TraceBusID_Msk (0x7FUL << ITM_TCR_TraceBusID_Pos) /*!< ITM TCR: ATBID Mask */\r
+\r
+#define ITM_TCR_GTSFREQ_Pos 10U /*!< ITM TCR: Global timestamp frequency Position */\r
+#define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */\r
+\r
+#define ITM_TCR_TSPrescale_Pos 8U /*!< ITM TCR: TSPrescale Position */\r
+#define ITM_TCR_TSPrescale_Msk (3UL << ITM_TCR_TSPrescale_Pos) /*!< ITM TCR: TSPrescale Mask */\r
+\r
+#define ITM_TCR_SWOENA_Pos 4U /*!< ITM TCR: SWOENA Position */\r
+#define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */\r
+\r
+#define ITM_TCR_DWTENA_Pos 3U /*!< ITM TCR: DWTENA Position */\r
+#define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */\r
+\r
+#define ITM_TCR_SYNCENA_Pos 2U /*!< ITM TCR: SYNCENA Position */\r
+#define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */\r
+\r
+#define ITM_TCR_TSENA_Pos 1U /*!< ITM TCR: TSENA Position */\r
+#define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */\r
+\r
+#define ITM_TCR_ITMENA_Pos 0U /*!< ITM TCR: ITM Enable bit Position */\r
+#define ITM_TCR_ITMENA_Msk (1UL /*<< ITM_TCR_ITMENA_Pos*/) /*!< ITM TCR: ITM Enable bit Mask */\r
+\r
+/* ITM Integration Write Register Definitions */\r
+#define ITM_IWR_ATVALIDM_Pos 0U /*!< ITM IWR: ATVALIDM Position */\r
+#define ITM_IWR_ATVALIDM_Msk (1UL /*<< ITM_IWR_ATVALIDM_Pos*/) /*!< ITM IWR: ATVALIDM Mask */\r
+\r
+/* ITM Integration Read Register Definitions */\r
+#define ITM_IRR_ATREADYM_Pos 0U /*!< ITM IRR: ATREADYM Position */\r
+#define ITM_IRR_ATREADYM_Msk (1UL /*<< ITM_IRR_ATREADYM_Pos*/) /*!< ITM IRR: ATREADYM Mask */\r
+\r
+/* ITM Integration Mode Control Register Definitions */\r
+#define ITM_IMCR_INTEGRATION_Pos 0U /*!< ITM IMCR: INTEGRATION Position */\r
+#define ITM_IMCR_INTEGRATION_Msk (1UL /*<< ITM_IMCR_INTEGRATION_Pos*/) /*!< ITM IMCR: INTEGRATION Mask */\r
+\r
+/* ITM Lock Status Register Definitions */\r
+#define ITM_LSR_ByteAcc_Pos 2U /*!< ITM LSR: ByteAcc Position */\r
+#define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */\r
+\r
+#define ITM_LSR_Access_Pos 1U /*!< ITM LSR: Access Position */\r
+#define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */\r
+\r
+#define ITM_LSR_Present_Pos 0U /*!< ITM LSR: Present Position */\r
+#define ITM_LSR_Present_Msk (1UL /*<< ITM_LSR_Present_Pos*/) /*!< ITM LSR: Present Mask */\r
+\r
+/*@}*/ /* end of group CMSIS_ITM */\r
+\r
+\r
+/**\r
+ \ingroup CMSIS_core_register\r
+ \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT)\r
+ \brief Type definitions for the Data Watchpoint and Trace (DWT)\r
+ @{\r
+ */\r
+\r
+/**\r
+ \brief Structure type to access the Data Watchpoint and Trace Register (DWT).\r
+ */\r
+typedef struct\r
+{\r
+ __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */\r
+ __IOM uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */\r
+ __IOM uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */\r
+ __IOM uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */\r
+ __IOM uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */\r
+ __IOM uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */\r
+ __IOM uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */\r
+ __IM uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */\r
+ __IOM uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */\r
+ __IOM uint32_t MASK0; /*!< Offset: 0x024 (R/W) Mask Register 0 */\r
+ __IOM uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */\r
+ uint32_t RESERVED0[1U];\r
+ __IOM uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */\r
+ __IOM uint32_t MASK1; /*!< Offset: 0x034 (R/W) Mask Register 1 */\r
+ __IOM uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */\r
+ uint32_t RESERVED1[1U];\r
+ __IOM uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */\r
+ __IOM uint32_t MASK2; /*!< Offset: 0x044 (R/W) Mask Register 2 */\r
+ __IOM uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */\r
+ uint32_t RESERVED2[1U];\r
+ __IOM uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */\r
+ __IOM uint32_t MASK3; /*!< Offset: 0x054 (R/W) Mask Register 3 */\r
+ __IOM uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */\r
+ uint32_t RESERVED3[981U];\r
+ __OM uint32_t LAR; /*!< Offset: 0xFB0 ( W) Lock Access Register */\r
+ __IM uint32_t LSR; /*!< Offset: 0xFB4 (R ) Lock Status Register */\r
+} DWT_Type;\r
+\r
+/* DWT Control Register Definitions */\r
+#define DWT_CTRL_NUMCOMP_Pos 28U /*!< DWT CTRL: NUMCOMP Position */\r
+#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */\r
+\r
+#define DWT_CTRL_NOTRCPKT_Pos 27U /*!< DWT CTRL: NOTRCPKT Position */\r
+#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */\r
+\r
+#define DWT_CTRL_NOEXTTRIG_Pos 26U /*!< DWT CTRL: NOEXTTRIG Position */\r
+#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */\r
+\r
+#define DWT_CTRL_NOCYCCNT_Pos 25U /*!< DWT CTRL: NOCYCCNT Position */\r
+#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */\r
+\r
+#define DWT_CTRL_NOPRFCNT_Pos 24U /*!< DWT CTRL: NOPRFCNT Position */\r
+#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */\r
+\r
+#define DWT_CTRL_CYCEVTENA_Pos 22U /*!< DWT CTRL: CYCEVTENA Position */\r
+#define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */\r
+\r
+#define DWT_CTRL_FOLDEVTENA_Pos 21U /*!< DWT CTRL: FOLDEVTENA Position */\r
+#define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */\r
+\r
+#define DWT_CTRL_LSUEVTENA_Pos 20U /*!< DWT CTRL: LSUEVTENA Position */\r
+#define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */\r
+\r
+#define DWT_CTRL_SLEEPEVTENA_Pos 19U /*!< DWT CTRL: SLEEPEVTENA Position */\r
+#define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */\r
+\r
+#define DWT_CTRL_EXCEVTENA_Pos 18U /*!< DWT CTRL: EXCEVTENA Position */\r
+#define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */\r
+\r
+#define DWT_CTRL_CPIEVTENA_Pos 17U /*!< DWT CTRL: CPIEVTENA Position */\r
+#define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */\r
+\r
+#define DWT_CTRL_EXCTRCENA_Pos 16U /*!< DWT CTRL: EXCTRCENA Position */\r
+#define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */\r
+\r
+#define DWT_CTRL_PCSAMPLENA_Pos 12U /*!< DWT CTRL: PCSAMPLENA Position */\r
+#define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */\r
+\r
+#define DWT_CTRL_SYNCTAP_Pos 10U /*!< DWT CTRL: SYNCTAP Position */\r
+#define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */\r
+\r
+#define DWT_CTRL_CYCTAP_Pos 9U /*!< DWT CTRL: CYCTAP Position */\r
+#define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */\r
+\r
+#define DWT_CTRL_POSTINIT_Pos 5U /*!< DWT CTRL: POSTINIT Position */\r
+#define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */\r
+\r
+#define DWT_CTRL_POSTPRESET_Pos 1U /*!< DWT CTRL: POSTPRESET Position */\r
+#define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */\r
+\r
+#define DWT_CTRL_CYCCNTENA_Pos 0U /*!< DWT CTRL: CYCCNTENA Position */\r
+#define DWT_CTRL_CYCCNTENA_Msk (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/) /*!< DWT CTRL: CYCCNTENA Mask */\r
+\r
+/* DWT CPI Count Register Definitions */\r
+#define DWT_CPICNT_CPICNT_Pos 0U /*!< DWT CPICNT: CPICNT Position */\r
+#define DWT_CPICNT_CPICNT_Msk (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/) /*!< DWT CPICNT: CPICNT Mask */\r
+\r
+/* DWT Exception Overhead Count Register Definitions */\r
+#define DWT_EXCCNT_EXCCNT_Pos 0U /*!< DWT EXCCNT: EXCCNT Position */\r
+#define DWT_EXCCNT_EXCCNT_Msk (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/) /*!< DWT EXCCNT: EXCCNT Mask */\r
+\r
+/* DWT Sleep Count Register Definitions */\r
+#define DWT_SLEEPCNT_SLEEPCNT_Pos 0U /*!< DWT SLEEPCNT: SLEEPCNT Position */\r
+#define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/) /*!< DWT SLEEPCNT: SLEEPCNT Mask */\r
+\r
+/* DWT LSU Count Register Definitions */\r
+#define DWT_LSUCNT_LSUCNT_Pos 0U /*!< DWT LSUCNT: LSUCNT Position */\r
+#define DWT_LSUCNT_LSUCNT_Msk (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/) /*!< DWT LSUCNT: LSUCNT Mask */\r
+\r
+/* DWT Folded-instruction Count Register Definitions */\r
+#define DWT_FOLDCNT_FOLDCNT_Pos 0U /*!< DWT FOLDCNT: FOLDCNT Position */\r
+#define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/) /*!< DWT FOLDCNT: FOLDCNT Mask */\r
+\r
+/* DWT Comparator Mask Register Definitions */\r
+#define DWT_MASK_MASK_Pos 0U /*!< DWT MASK: MASK Position */\r
+#define DWT_MASK_MASK_Msk (0x1FUL /*<< DWT_MASK_MASK_Pos*/) /*!< DWT MASK: MASK Mask */\r
+\r
+/* DWT Comparator Function Register Definitions */\r
+#define DWT_FUNCTION_MATCHED_Pos 24U /*!< DWT FUNCTION: MATCHED Position */\r
+#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */\r
+\r
+#define DWT_FUNCTION_DATAVADDR1_Pos 16U /*!< DWT FUNCTION: DATAVADDR1 Position */\r
+#define DWT_FUNCTION_DATAVADDR1_Msk (0xFUL << DWT_FUNCTION_DATAVADDR1_Pos) /*!< DWT FUNCTION: DATAVADDR1 Mask */\r
+\r
+#define DWT_FUNCTION_DATAVADDR0_Pos 12U /*!< DWT FUNCTION: DATAVADDR0 Position */\r
+#define DWT_FUNCTION_DATAVADDR0_Msk (0xFUL << DWT_FUNCTION_DATAVADDR0_Pos) /*!< DWT FUNCTION: DATAVADDR0 Mask */\r
+\r
+#define DWT_FUNCTION_DATAVSIZE_Pos 10U /*!< DWT FUNCTION: DATAVSIZE Position */\r
+#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */\r
+\r
+#define DWT_FUNCTION_LNK1ENA_Pos 9U /*!< DWT FUNCTION: LNK1ENA Position */\r
+#define DWT_FUNCTION_LNK1ENA_Msk (0x1UL << DWT_FUNCTION_LNK1ENA_Pos) /*!< DWT FUNCTION: LNK1ENA Mask */\r
+\r
+#define DWT_FUNCTION_DATAVMATCH_Pos 8U /*!< DWT FUNCTION: DATAVMATCH Position */\r
+#define DWT_FUNCTION_DATAVMATCH_Msk (0x1UL << DWT_FUNCTION_DATAVMATCH_Pos) /*!< DWT FUNCTION: DATAVMATCH Mask */\r
+\r
+#define DWT_FUNCTION_CYCMATCH_Pos 7U /*!< DWT FUNCTION: CYCMATCH Position */\r
+#define DWT_FUNCTION_CYCMATCH_Msk (0x1UL << DWT_FUNCTION_CYCMATCH_Pos) /*!< DWT FUNCTION: CYCMATCH Mask */\r
+\r
+#define DWT_FUNCTION_EMITRANGE_Pos 5U /*!< DWT FUNCTION: EMITRANGE Position */\r
+#define DWT_FUNCTION_EMITRANGE_Msk (0x1UL << DWT_FUNCTION_EMITRANGE_Pos) /*!< DWT FUNCTION: EMITRANGE Mask */\r
+\r
+#define DWT_FUNCTION_FUNCTION_Pos 0U /*!< DWT FUNCTION: FUNCTION Position */\r
+#define DWT_FUNCTION_FUNCTION_Msk (0xFUL /*<< DWT_FUNCTION_FUNCTION_Pos*/) /*!< DWT FUNCTION: FUNCTION Mask */\r
+\r
+/*@}*/ /* end of group CMSIS_DWT */\r
+\r
+\r
+/**\r
+ \ingroup CMSIS_core_register\r
+ \defgroup CMSIS_TPI Trace Port Interface (TPI)\r
+ \brief Type definitions for the Trace Port Interface (TPI)\r
+ @{\r
+ */\r
+\r
+/**\r
+ \brief Structure type to access the Trace Port Interface Register (TPI).\r
+ */\r
+typedef struct\r
+{\r
+ __IM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */\r
+ __IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */\r
+ uint32_t RESERVED0[2U];\r
+ __IOM uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */\r
+ uint32_t RESERVED1[55U];\r
+ __IOM uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */\r
+ uint32_t RESERVED2[131U];\r
+ __IM uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */\r
+ __IOM uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */\r
+ __IM uint32_t FSCR; /*!< Offset: 0x308 (R/ ) Formatter Synchronization Counter Register */\r
+ uint32_t RESERVED3[759U];\r
+ __IM uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER Register */\r
+ __IM uint32_t FIFO0; /*!< Offset: 0xEEC (R/ ) Integration ETM Data */\r
+ __IM uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/ ) ITATBCTR2 */\r
+ uint32_t RESERVED4[1U];\r
+ __IM uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) ITATBCTR0 */\r
+ __IM uint32_t FIFO1; /*!< Offset: 0xEFC (R/ ) Integration ITM Data */\r
+ __IOM uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */\r
+ uint32_t RESERVED5[39U];\r
+ __IOM uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */\r
+ __IOM uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */\r
+ uint32_t RESERVED7[8U];\r
+ __IM uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) TPIU_DEVID */\r
+ __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) TPIU_DEVTYPE */\r
+} TPI_Type;\r
+\r
+/* TPI Asynchronous Clock Prescaler Register Definitions */\r
+#define TPI_ACPR_PRESCALER_Pos 0U /*!< TPI ACPR: PRESCALER Position */\r
+#define TPI_ACPR_PRESCALER_Msk (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/) /*!< TPI ACPR: PRESCALER Mask */\r
+\r
+/* TPI Selected Pin Protocol Register Definitions */\r
+#define TPI_SPPR_TXMODE_Pos 0U /*!< TPI SPPR: TXMODE Position */\r
+#define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) /*!< TPI SPPR: TXMODE Mask */\r
+\r
+/* TPI Formatter and Flush Status Register Definitions */\r
+#define TPI_FFSR_FtNonStop_Pos 3U /*!< TPI FFSR: FtNonStop Position */\r
+#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */\r
+\r
+#define TPI_FFSR_TCPresent_Pos 2U /*!< TPI FFSR: TCPresent Position */\r
+#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */\r
+\r
+#define TPI_FFSR_FtStopped_Pos 1U /*!< TPI FFSR: FtStopped Position */\r
+#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */\r
+\r
+#define TPI_FFSR_FlInProg_Pos 0U /*!< TPI FFSR: FlInProg Position */\r
+#define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) /*!< TPI FFSR: FlInProg Mask */\r
+\r
+/* TPI Formatter and Flush Control Register Definitions */\r
+#define TPI_FFCR_TrigIn_Pos 8U /*!< TPI FFCR: TrigIn Position */\r
+#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */\r
+\r
+#define TPI_FFCR_EnFCont_Pos 1U /*!< TPI FFCR: EnFCont Position */\r
+#define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */\r
+\r
+/* TPI TRIGGER Register Definitions */\r
+#define TPI_TRIGGER_TRIGGER_Pos 0U /*!< TPI TRIGGER: TRIGGER Position */\r
+#define TPI_TRIGGER_TRIGGER_Msk (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/) /*!< TPI TRIGGER: TRIGGER Mask */\r
+\r
+/* TPI Integration ETM Data Register Definitions (FIFO0) */\r
+#define TPI_FIFO0_ITM_ATVALID_Pos 29U /*!< TPI FIFO0: ITM_ATVALID Position */\r
+#define TPI_FIFO0_ITM_ATVALID_Msk (0x3UL << TPI_FIFO0_ITM_ATVALID_Pos) /*!< TPI FIFO0: ITM_ATVALID Mask */\r
+\r
+#define TPI_FIFO0_ITM_bytecount_Pos 27U /*!< TPI FIFO0: ITM_bytecount Position */\r
+#define TPI_FIFO0_ITM_bytecount_Msk (0x3UL << TPI_FIFO0_ITM_bytecount_Pos) /*!< TPI FIFO0: ITM_bytecount Mask */\r
+\r
+#define TPI_FIFO0_ETM_ATVALID_Pos 26U /*!< TPI FIFO0: ETM_ATVALID Position */\r
+#define TPI_FIFO0_ETM_ATVALID_Msk (0x3UL << TPI_FIFO0_ETM_ATVALID_Pos) /*!< TPI FIFO0: ETM_ATVALID Mask */\r
+\r
+#define TPI_FIFO0_ETM_bytecount_Pos 24U /*!< TPI FIFO0: ETM_bytecount Position */\r
+#define TPI_FIFO0_ETM_bytecount_Msk (0x3UL << TPI_FIFO0_ETM_bytecount_Pos) /*!< TPI FIFO0: ETM_bytecount Mask */\r
+\r
+#define TPI_FIFO0_ETM2_Pos 16U /*!< TPI FIFO0: ETM2 Position */\r
+#define TPI_FIFO0_ETM2_Msk (0xFFUL << TPI_FIFO0_ETM2_Pos) /*!< TPI FIFO0: ETM2 Mask */\r
+\r
+#define TPI_FIFO0_ETM1_Pos 8U /*!< TPI FIFO0: ETM1 Position */\r
+#define TPI_FIFO0_ETM1_Msk (0xFFUL << TPI_FIFO0_ETM1_Pos) /*!< TPI FIFO0: ETM1 Mask */\r
+\r
+#define TPI_FIFO0_ETM0_Pos 0U /*!< TPI FIFO0: ETM0 Position */\r
+#define TPI_FIFO0_ETM0_Msk (0xFFUL /*<< TPI_FIFO0_ETM0_Pos*/) /*!< TPI FIFO0: ETM0 Mask */\r
+\r
+/* TPI ITATBCTR2 Register Definitions */\r
+#define TPI_ITATBCTR2_ATREADY2_Pos 0U /*!< TPI ITATBCTR2: ATREADY2 Position */\r
+#define TPI_ITATBCTR2_ATREADY2_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY2_Pos*/) /*!< TPI ITATBCTR2: ATREADY2 Mask */\r
+\r
+#define TPI_ITATBCTR2_ATREADY1_Pos 0U /*!< TPI ITATBCTR2: ATREADY1 Position */\r
+#define TPI_ITATBCTR2_ATREADY1_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY1_Pos*/) /*!< TPI ITATBCTR2: ATREADY1 Mask */\r
+\r
+/* TPI Integration ITM Data Register Definitions (FIFO1) */\r
+#define TPI_FIFO1_ITM_ATVALID_Pos 29U /*!< TPI FIFO1: ITM_ATVALID Position */\r
+#define TPI_FIFO1_ITM_ATVALID_Msk (0x3UL << TPI_FIFO1_ITM_ATVALID_Pos) /*!< TPI FIFO1: ITM_ATVALID Mask */\r
+\r
+#define TPI_FIFO1_ITM_bytecount_Pos 27U /*!< TPI FIFO1: ITM_bytecount Position */\r
+#define TPI_FIFO1_ITM_bytecount_Msk (0x3UL << TPI_FIFO1_ITM_bytecount_Pos) /*!< TPI FIFO1: ITM_bytecount Mask */\r
+\r
+#define TPI_FIFO1_ETM_ATVALID_Pos 26U /*!< TPI FIFO1: ETM_ATVALID Position */\r
+#define TPI_FIFO1_ETM_ATVALID_Msk (0x3UL << TPI_FIFO1_ETM_ATVALID_Pos) /*!< TPI FIFO1: ETM_ATVALID Mask */\r
+\r
+#define TPI_FIFO1_ETM_bytecount_Pos 24U /*!< TPI FIFO1: ETM_bytecount Position */\r
+#define TPI_FIFO1_ETM_bytecount_Msk (0x3UL << TPI_FIFO1_ETM_bytecount_Pos) /*!< TPI FIFO1: ETM_bytecount Mask */\r
+\r
+#define TPI_FIFO1_ITM2_Pos 16U /*!< TPI FIFO1: ITM2 Position */\r
+#define TPI_FIFO1_ITM2_Msk (0xFFUL << TPI_FIFO1_ITM2_Pos) /*!< TPI FIFO1: ITM2 Mask */\r
+\r
+#define TPI_FIFO1_ITM1_Pos 8U /*!< TPI FIFO1: ITM1 Position */\r
+#define TPI_FIFO1_ITM1_Msk (0xFFUL << TPI_FIFO1_ITM1_Pos) /*!< TPI FIFO1: ITM1 Mask */\r
+\r
+#define TPI_FIFO1_ITM0_Pos 0U /*!< TPI FIFO1: ITM0 Position */\r
+#define TPI_FIFO1_ITM0_Msk (0xFFUL /*<< TPI_FIFO1_ITM0_Pos*/) /*!< TPI FIFO1: ITM0 Mask */\r
+\r
+/* TPI ITATBCTR0 Register Definitions */\r
+#define TPI_ITATBCTR0_ATREADY2_Pos 0U /*!< TPI ITATBCTR0: ATREADY2 Position */\r
+#define TPI_ITATBCTR0_ATREADY2_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY2_Pos*/) /*!< TPI ITATBCTR0: ATREADY2 Mask */\r
+\r
+#define TPI_ITATBCTR0_ATREADY1_Pos 0U /*!< TPI ITATBCTR0: ATREADY1 Position */\r
+#define TPI_ITATBCTR0_ATREADY1_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY1_Pos*/) /*!< TPI ITATBCTR0: ATREADY1 Mask */\r
+\r
+/* TPI Integration Mode Control Register Definitions */\r
+#define TPI_ITCTRL_Mode_Pos 0U /*!< TPI ITCTRL: Mode Position */\r
+#define TPI_ITCTRL_Mode_Msk (0x3UL /*<< TPI_ITCTRL_Mode_Pos*/) /*!< TPI ITCTRL: Mode Mask */\r
+\r
+/* TPI DEVID Register Definitions */\r
+#define TPI_DEVID_NRZVALID_Pos 11U /*!< TPI DEVID: NRZVALID Position */\r
+#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */\r
+\r
+#define TPI_DEVID_MANCVALID_Pos 10U /*!< TPI DEVID: MANCVALID Position */\r
+#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */\r
+\r
+#define TPI_DEVID_PTINVALID_Pos 9U /*!< TPI DEVID: PTINVALID Position */\r
+#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */\r
+\r
+#define TPI_DEVID_MinBufSz_Pos 6U /*!< TPI DEVID: MinBufSz Position */\r
+#define TPI_DEVID_MinBufSz_Msk (0x7UL << TPI_DEVID_MinBufSz_Pos) /*!< TPI DEVID: MinBufSz Mask */\r
+\r
+#define TPI_DEVID_AsynClkIn_Pos 5U /*!< TPI DEVID: AsynClkIn Position */\r
+#define TPI_DEVID_AsynClkIn_Msk (0x1UL << TPI_DEVID_AsynClkIn_Pos) /*!< TPI DEVID: AsynClkIn Mask */\r
+\r
+#define TPI_DEVID_NrTraceInput_Pos 0U /*!< TPI DEVID: NrTraceInput Position */\r
+#define TPI_DEVID_NrTraceInput_Msk (0x1FUL /*<< TPI_DEVID_NrTraceInput_Pos*/) /*!< TPI DEVID: NrTraceInput Mask */\r
+\r
+/* TPI DEVTYPE Register Definitions */\r
+#define TPI_DEVTYPE_SubType_Pos 4U /*!< TPI DEVTYPE: SubType Position */\r
+#define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */\r
+\r
+#define TPI_DEVTYPE_MajorType_Pos 0U /*!< TPI DEVTYPE: MajorType Position */\r
+#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */\r
+\r
+/*@}*/ /* end of group CMSIS_TPI */\r
+\r
+\r
+#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)\r
+/**\r
+ \ingroup CMSIS_core_register\r
+ \defgroup CMSIS_MPU Memory Protection Unit (MPU)\r
+ \brief Type definitions for the Memory Protection Unit (MPU)\r
+ @{\r
+ */\r
+\r
+/**\r
+ \brief Structure type to access the Memory Protection Unit (MPU).\r
+ */\r
+typedef struct\r
+{\r
+ __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */\r
+ __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */\r
+ __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */\r
+ __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */\r
+ __IOM uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */\r
+ __IOM uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Alias 1 Region Base Address Register */\r
+ __IOM uint32_t RASR_A1; /*!< Offset: 0x018 (R/W) MPU Alias 1 Region Attribute and Size Register */\r
+ __IOM uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Alias 2 Region Base Address Register */\r
+ __IOM uint32_t RASR_A2; /*!< Offset: 0x020 (R/W) MPU Alias 2 Region Attribute and Size Register */\r
+ __IOM uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Alias 3 Region Base Address Register */\r
+ __IOM uint32_t RASR_A3; /*!< Offset: 0x028 (R/W) MPU Alias 3 Region Attribute and Size Register */\r
+} MPU_Type;\r
+\r
+#define MPU_TYPE_RALIASES 4U\r
+\r
+/* MPU Type Register Definitions */\r
+#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */\r
+#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */\r
+\r
+#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */\r
+#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */\r
+\r
+#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */\r
+#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */\r
+\r
+/* MPU Control Register Definitions */\r
+#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */\r
+#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */\r
+\r
+#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */\r
+#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */\r
+\r
+#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */\r
+#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */\r
+\r
+/* MPU Region Number Register Definitions */\r
+#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */\r
+#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */\r
+\r
+/* MPU Region Base Address Register Definitions */\r
+#define MPU_RBAR_ADDR_Pos 5U /*!< MPU RBAR: ADDR Position */\r
+#define MPU_RBAR_ADDR_Msk (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */\r
+\r
+#define MPU_RBAR_VALID_Pos 4U /*!< MPU RBAR: VALID Position */\r
+#define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */\r
+\r
+#define MPU_RBAR_REGION_Pos 0U /*!< MPU RBAR: REGION Position */\r
+#define MPU_RBAR_REGION_Msk (0xFUL /*<< MPU_RBAR_REGION_Pos*/) /*!< MPU RBAR: REGION Mask */\r
+\r
+/* MPU Region Attribute and Size Register Definitions */\r
+#define MPU_RASR_ATTRS_Pos 16U /*!< MPU RASR: MPU Region Attribute field Position */\r
+#define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */\r
+\r
+#define MPU_RASR_XN_Pos 28U /*!< MPU RASR: ATTRS.XN Position */\r
+#define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */\r
+\r
+#define MPU_RASR_AP_Pos 24U /*!< MPU RASR: ATTRS.AP Position */\r
+#define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */\r
+\r
+#define MPU_RASR_TEX_Pos 19U /*!< MPU RASR: ATTRS.TEX Position */\r
+#define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */\r
+\r
+#define MPU_RASR_S_Pos 18U /*!< MPU RASR: ATTRS.S Position */\r
+#define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */\r
+\r
+#define MPU_RASR_C_Pos 17U /*!< MPU RASR: ATTRS.C Position */\r
+#define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */\r
+\r
+#define MPU_RASR_B_Pos 16U /*!< MPU RASR: ATTRS.B Position */\r
+#define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */\r
+\r
+#define MPU_RASR_SRD_Pos 8U /*!< MPU RASR: Sub-Region Disable Position */\r
+#define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */\r
+\r
+#define MPU_RASR_SIZE_Pos 1U /*!< MPU RASR: Region Size Field Position */\r
+#define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */\r
+\r
+#define MPU_RASR_ENABLE_Pos 0U /*!< MPU RASR: Region enable bit Position */\r
+#define MPU_RASR_ENABLE_Msk (1UL /*<< MPU_RASR_ENABLE_Pos*/) /*!< MPU RASR: Region enable bit Disable Mask */\r
+\r
+/*@} end of group CMSIS_MPU */\r
+#endif /* defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) */\r
+\r
+\r
+/**\r
+ \ingroup CMSIS_core_register\r
+ \defgroup CMSIS_FPU Floating Point Unit (FPU)\r
+ \brief Type definitions for the Floating Point Unit (FPU)\r
+ @{\r
+ */\r
+\r
+/**\r
+ \brief Structure type to access the Floating Point Unit (FPU).\r
+ */\r
+typedef struct\r
+{\r
+ uint32_t RESERVED0[1U];\r
+ __IOM uint32_t FPCCR; /*!< Offset: 0x004 (R/W) Floating-Point Context Control Register */\r
+ __IOM uint32_t FPCAR; /*!< Offset: 0x008 (R/W) Floating-Point Context Address Register */\r
+ __IOM uint32_t FPDSCR; /*!< Offset: 0x00C (R/W) Floating-Point Default Status Control Register */\r
+ __IM uint32_t MVFR0; /*!< Offset: 0x010 (R/ ) Media and FP Feature Register 0 */\r
+ __IM uint32_t MVFR1; /*!< Offset: 0x014 (R/ ) Media and FP Feature Register 1 */\r
+ __IM uint32_t MVFR2; /*!< Offset: 0x018 (R/ ) Media and FP Feature Register 2 */\r
+} FPU_Type;\r
+\r
+/* Floating-Point Context Control Register Definitions */\r
+#define FPU_FPCCR_ASPEN_Pos 31U /*!< FPCCR: ASPEN bit Position */\r
+#define FPU_FPCCR_ASPEN_Msk (1UL << FPU_FPCCR_ASPEN_Pos) /*!< FPCCR: ASPEN bit Mask */\r
+\r
+#define FPU_FPCCR_LSPEN_Pos 30U /*!< FPCCR: LSPEN Position */\r
+#define FPU_FPCCR_LSPEN_Msk (1UL << FPU_FPCCR_LSPEN_Pos) /*!< FPCCR: LSPEN bit Mask */\r
+\r
+#define FPU_FPCCR_MONRDY_Pos 8U /*!< FPCCR: MONRDY Position */\r
+#define FPU_FPCCR_MONRDY_Msk (1UL << FPU_FPCCR_MONRDY_Pos) /*!< FPCCR: MONRDY bit Mask */\r
+\r
+#define FPU_FPCCR_BFRDY_Pos 6U /*!< FPCCR: BFRDY Position */\r
+#define FPU_FPCCR_BFRDY_Msk (1UL << FPU_FPCCR_BFRDY_Pos) /*!< FPCCR: BFRDY bit Mask */\r
+\r
+#define FPU_FPCCR_MMRDY_Pos 5U /*!< FPCCR: MMRDY Position */\r
+#define FPU_FPCCR_MMRDY_Msk (1UL << FPU_FPCCR_MMRDY_Pos) /*!< FPCCR: MMRDY bit Mask */\r
+\r
+#define FPU_FPCCR_HFRDY_Pos 4U /*!< FPCCR: HFRDY Position */\r
+#define FPU_FPCCR_HFRDY_Msk (1UL << FPU_FPCCR_HFRDY_Pos) /*!< FPCCR: HFRDY bit Mask */\r
+\r
+#define FPU_FPCCR_THREAD_Pos 3U /*!< FPCCR: processor mode bit Position */\r
+#define FPU_FPCCR_THREAD_Msk (1UL << FPU_FPCCR_THREAD_Pos) /*!< FPCCR: processor mode active bit Mask */\r
+\r
+#define FPU_FPCCR_USER_Pos 1U /*!< FPCCR: privilege level bit Position */\r
+#define FPU_FPCCR_USER_Msk (1UL << FPU_FPCCR_USER_Pos) /*!< FPCCR: privilege level bit Mask */\r
+\r
+#define FPU_FPCCR_LSPACT_Pos 0U /*!< FPCCR: Lazy state preservation active bit Position */\r
+#define FPU_FPCCR_LSPACT_Msk (1UL /*<< FPU_FPCCR_LSPACT_Pos*/) /*!< FPCCR: Lazy state preservation active bit Mask */\r
+\r
+/* Floating-Point Context Address Register Definitions */\r
+#define FPU_FPCAR_ADDRESS_Pos 3U /*!< FPCAR: ADDRESS bit Position */\r
+#define FPU_FPCAR_ADDRESS_Msk (0x1FFFFFFFUL << FPU_FPCAR_ADDRESS_Pos) /*!< FPCAR: ADDRESS bit Mask */\r
+\r
+/* Floating-Point Default Status Control Register Definitions */\r
+#define FPU_FPDSCR_AHP_Pos 26U /*!< FPDSCR: AHP bit Position */\r
+#define FPU_FPDSCR_AHP_Msk (1UL << FPU_FPDSCR_AHP_Pos) /*!< FPDSCR: AHP bit Mask */\r
+\r
+#define FPU_FPDSCR_DN_Pos 25U /*!< FPDSCR: DN bit Position */\r
+#define FPU_FPDSCR_DN_Msk (1UL << FPU_FPDSCR_DN_Pos) /*!< FPDSCR: DN bit Mask */\r
+\r
+#define FPU_FPDSCR_FZ_Pos 24U /*!< FPDSCR: FZ bit Position */\r
+#define FPU_FPDSCR_FZ_Msk (1UL << FPU_FPDSCR_FZ_Pos) /*!< FPDSCR: FZ bit Mask */\r
+\r
+#define FPU_FPDSCR_RMode_Pos 22U /*!< FPDSCR: RMode bit Position */\r
+#define FPU_FPDSCR_RMode_Msk (3UL << FPU_FPDSCR_RMode_Pos) /*!< FPDSCR: RMode bit Mask */\r
+\r
+/* Media and FP Feature Register 0 Definitions */\r
+#define FPU_MVFR0_FP_rounding_modes_Pos 28U /*!< MVFR0: FP rounding modes bits Position */\r
+#define FPU_MVFR0_FP_rounding_modes_Msk (0xFUL << FPU_MVFR0_FP_rounding_modes_Pos) /*!< MVFR0: FP rounding modes bits Mask */\r
+\r
+#define FPU_MVFR0_Short_vectors_Pos 24U /*!< MVFR0: Short vectors bits Position */\r
+#define FPU_MVFR0_Short_vectors_Msk (0xFUL << FPU_MVFR0_Short_vectors_Pos) /*!< MVFR0: Short vectors bits Mask */\r
+\r
+#define FPU_MVFR0_Square_root_Pos 20U /*!< MVFR0: Square root bits Position */\r
+#define FPU_MVFR0_Square_root_Msk (0xFUL << FPU_MVFR0_Square_root_Pos) /*!< MVFR0: Square root bits Mask */\r
+\r
+#define FPU_MVFR0_Divide_Pos 16U /*!< MVFR0: Divide bits Position */\r
+#define FPU_MVFR0_Divide_Msk (0xFUL << FPU_MVFR0_Divide_Pos) /*!< MVFR0: Divide bits Mask */\r
+\r
+#define FPU_MVFR0_FP_excep_trapping_Pos 12U /*!< MVFR0: FP exception trapping bits Position */\r
+#define FPU_MVFR0_FP_excep_trapping_Msk (0xFUL << FPU_MVFR0_FP_excep_trapping_Pos) /*!< MVFR0: FP exception trapping bits Mask */\r
+\r
+#define FPU_MVFR0_Double_precision_Pos 8U /*!< MVFR0: Double-precision bits Position */\r
+#define FPU_MVFR0_Double_precision_Msk (0xFUL << FPU_MVFR0_Double_precision_Pos) /*!< MVFR0: Double-precision bits Mask */\r
+\r
+#define FPU_MVFR0_Single_precision_Pos 4U /*!< MVFR0: Single-precision bits Position */\r
+#define FPU_MVFR0_Single_precision_Msk (0xFUL << FPU_MVFR0_Single_precision_Pos) /*!< MVFR0: Single-precision bits Mask */\r
+\r
+#define FPU_MVFR0_A_SIMD_registers_Pos 0U /*!< MVFR0: A_SIMD registers bits Position */\r
+#define FPU_MVFR0_A_SIMD_registers_Msk (0xFUL /*<< FPU_MVFR0_A_SIMD_registers_Pos*/) /*!< MVFR0: A_SIMD registers bits Mask */\r
+\r
+/* Media and FP Feature Register 1 Definitions */\r
+#define FPU_MVFR1_FP_fused_MAC_Pos 28U /*!< MVFR1: FP fused MAC bits Position */\r
+#define FPU_MVFR1_FP_fused_MAC_Msk (0xFUL << FPU_MVFR1_FP_fused_MAC_Pos) /*!< MVFR1: FP fused MAC bits Mask */\r
+\r
+#define FPU_MVFR1_FP_HPFP_Pos 24U /*!< MVFR1: FP HPFP bits Position */\r
+#define FPU_MVFR1_FP_HPFP_Msk (0xFUL << FPU_MVFR1_FP_HPFP_Pos) /*!< MVFR1: FP HPFP bits Mask */\r
+\r
+#define FPU_MVFR1_D_NaN_mode_Pos 4U /*!< MVFR1: D_NaN mode bits Position */\r
+#define FPU_MVFR1_D_NaN_mode_Msk (0xFUL << FPU_MVFR1_D_NaN_mode_Pos) /*!< MVFR1: D_NaN mode bits Mask */\r
+\r
+#define FPU_MVFR1_FtZ_mode_Pos 0U /*!< MVFR1: FtZ mode bits Position */\r
+#define FPU_MVFR1_FtZ_mode_Msk (0xFUL /*<< FPU_MVFR1_FtZ_mode_Pos*/) /*!< MVFR1: FtZ mode bits Mask */\r
+\r
+/* Media and FP Feature Register 2 Definitions */\r
+\r
+/*@} end of group CMSIS_FPU */\r
+\r
+\r
+/**\r
+ \ingroup CMSIS_core_register\r
+ \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug)\r
+ \brief Type definitions for the Core Debug Registers\r
+ @{\r
+ */\r
+\r
+/**\r
+ \brief Structure type to access the Core Debug Register (CoreDebug).\r
+ */\r
+typedef struct\r
+{\r
+ __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */\r
+ __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */\r
+ __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */\r
+ __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */\r
+} CoreDebug_Type;\r
+\r
+/* Debug Halting Control and Status Register Definitions */\r
+#define CoreDebug_DHCSR_DBGKEY_Pos 16U /*!< CoreDebug DHCSR: DBGKEY Position */\r
+#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */\r
+\r
+#define CoreDebug_DHCSR_S_RESET_ST_Pos 25U /*!< CoreDebug DHCSR: S_RESET_ST Position */\r
+#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */\r
+\r
+#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U /*!< CoreDebug DHCSR: S_RETIRE_ST Position */\r
+#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */\r
+\r
+#define CoreDebug_DHCSR_S_LOCKUP_Pos 19U /*!< CoreDebug DHCSR: S_LOCKUP Position */\r
+#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */\r
+\r
+#define CoreDebug_DHCSR_S_SLEEP_Pos 18U /*!< CoreDebug DHCSR: S_SLEEP Position */\r
+#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */\r
+\r
+#define CoreDebug_DHCSR_S_HALT_Pos 17U /*!< CoreDebug DHCSR: S_HALT Position */\r
+#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */\r
+\r
+#define CoreDebug_DHCSR_S_REGRDY_Pos 16U /*!< CoreDebug DHCSR: S_REGRDY Position */\r
+#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */\r
+\r
+#define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5U /*!< CoreDebug DHCSR: C_SNAPSTALL Position */\r
+#define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */\r
+\r
+#define CoreDebug_DHCSR_C_MASKINTS_Pos 3U /*!< CoreDebug DHCSR: C_MASKINTS Position */\r
+#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */\r
+\r
+#define CoreDebug_DHCSR_C_STEP_Pos 2U /*!< CoreDebug DHCSR: C_STEP Position */\r
+#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */\r
+\r
+#define CoreDebug_DHCSR_C_HALT_Pos 1U /*!< CoreDebug DHCSR: C_HALT Position */\r
+#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */\r
+\r
+#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U /*!< CoreDebug DHCSR: C_DEBUGEN Position */\r
+#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */\r
+\r
+/* Debug Core Register Selector Register Definitions */\r
+#define CoreDebug_DCRSR_REGWnR_Pos 16U /*!< CoreDebug DCRSR: REGWnR Position */\r
+#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */\r
+\r
+#define CoreDebug_DCRSR_REGSEL_Pos 0U /*!< CoreDebug DCRSR: REGSEL Position */\r
+#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/) /*!< CoreDebug DCRSR: REGSEL Mask */\r
+\r
+/* Debug Exception and Monitor Control Register Definitions */\r
+#define CoreDebug_DEMCR_TRCENA_Pos 24U /*!< CoreDebug DEMCR: TRCENA Position */\r
+#define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< CoreDebug DEMCR: TRCENA Mask */\r
+\r
+#define CoreDebug_DEMCR_MON_REQ_Pos 19U /*!< CoreDebug DEMCR: MON_REQ Position */\r
+#define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< CoreDebug DEMCR: MON_REQ Mask */\r
+\r
+#define CoreDebug_DEMCR_MON_STEP_Pos 18U /*!< CoreDebug DEMCR: MON_STEP Position */\r
+#define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< CoreDebug DEMCR: MON_STEP Mask */\r
+\r
+#define CoreDebug_DEMCR_MON_PEND_Pos 17U /*!< CoreDebug DEMCR: MON_PEND Position */\r
+#define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< CoreDebug DEMCR: MON_PEND Mask */\r
+\r
+#define CoreDebug_DEMCR_MON_EN_Pos 16U /*!< CoreDebug DEMCR: MON_EN Position */\r
+#define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< CoreDebug DEMCR: MON_EN Mask */\r
+\r
+#define CoreDebug_DEMCR_VC_HARDERR_Pos 10U /*!< CoreDebug DEMCR: VC_HARDERR Position */\r
+#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */\r
+\r
+#define CoreDebug_DEMCR_VC_INTERR_Pos 9U /*!< CoreDebug DEMCR: VC_INTERR Position */\r
+#define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< CoreDebug DEMCR: VC_INTERR Mask */\r
+\r
+#define CoreDebug_DEMCR_VC_BUSERR_Pos 8U /*!< CoreDebug DEMCR: VC_BUSERR Position */\r
+#define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< CoreDebug DEMCR: VC_BUSERR Mask */\r
+\r
+#define CoreDebug_DEMCR_VC_STATERR_Pos 7U /*!< CoreDebug DEMCR: VC_STATERR Position */\r
+#define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< CoreDebug DEMCR: VC_STATERR Mask */\r
+\r
+#define CoreDebug_DEMCR_VC_CHKERR_Pos 6U /*!< CoreDebug DEMCR: VC_CHKERR Position */\r
+#define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< CoreDebug DEMCR: VC_CHKERR Mask */\r
+\r
+#define CoreDebug_DEMCR_VC_NOCPERR_Pos 5U /*!< CoreDebug DEMCR: VC_NOCPERR Position */\r
+#define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< CoreDebug DEMCR: VC_NOCPERR Mask */\r
+\r
+#define CoreDebug_DEMCR_VC_MMERR_Pos 4U /*!< CoreDebug DEMCR: VC_MMERR Position */\r
+#define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< CoreDebug DEMCR: VC_MMERR Mask */\r
+\r
+#define CoreDebug_DEMCR_VC_CORERESET_Pos 0U /*!< CoreDebug DEMCR: VC_CORERESET Position */\r
+#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/) /*!< CoreDebug DEMCR: VC_CORERESET Mask */\r
+\r
+/*@} end of group CMSIS_CoreDebug */\r
+\r
+\r
+/**\r
+ \ingroup CMSIS_core_register\r
+ \defgroup CMSIS_core_bitfield Core register bit field macros\r
+ \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk).\r
+ @{\r
+ */\r
+\r
+/**\r
+ \brief Mask and shift a bit field value for use in a register bit range.\r
+ \param[in] field Name of the register bit field.\r
+ \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type.\r
+ \return Masked and shifted value.\r
+*/\r
+#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk)\r
+\r
+/**\r
+ \brief Mask and shift a register value to extract a bit filed value.\r
+ \param[in] field Name of the register bit field.\r
+ \param[in] value Value of register. This parameter is interpreted as an uint32_t type.\r
+ \return Masked and shifted bit field value.\r
+*/\r
+#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos)\r
+\r
+/*@} end of group CMSIS_core_bitfield */\r
+\r
+\r
+/**\r
+ \ingroup CMSIS_core_register\r
+ \defgroup CMSIS_core_base Core Definitions\r
+ \brief Definitions for base addresses, unions, and structures.\r
+ @{\r
+ */\r
+\r
+/* Memory mapping of Core Hardware */\r
+#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */\r
+#define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */\r
+#define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */\r
+#define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */\r
+#define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */\r
+#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */\r
+#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */\r
+#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */\r
+\r
+#define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */\r
+#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */\r
+#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */\r
+#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */\r
+#define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */\r
+#define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */\r
+#define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */\r
+#define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE) /*!< Core Debug configuration struct */\r
+\r
+#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)\r
+ #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */\r
+ #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */\r
+#endif\r
+\r
+#define FPU_BASE (SCS_BASE + 0x0F30UL) /*!< Floating Point Unit */\r
+#define FPU ((FPU_Type *) FPU_BASE ) /*!< Floating Point Unit */\r
+\r
+/*@} */\r
+\r
+\r
+\r
+/*******************************************************************************\r
+ * Hardware Abstraction Layer\r
+ Core Function Interface contains:\r
+ - Core NVIC Functions\r
+ - Core SysTick Functions\r
+ - Core Debug Functions\r
+ - Core Register Access Functions\r
+ ******************************************************************************/\r
+/**\r
+ \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference\r
+*/\r
+\r
+\r
+\r
+/* ########################## NVIC functions #################################### */\r
+/**\r
+ \ingroup CMSIS_Core_FunctionInterface\r
+ \defgroup CMSIS_Core_NVICFunctions NVIC Functions\r
+ \brief Functions that manage interrupts and exceptions via the NVIC.\r
+ @{\r
+ */\r
+\r
+#ifdef CMSIS_NVIC_VIRTUAL\r
+ #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE\r
+ #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h"\r
+ #endif\r
+ #include CMSIS_NVIC_VIRTUAL_HEADER_FILE\r
+#else\r
+ #define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping\r
+ #define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping\r
+ #define NVIC_EnableIRQ __NVIC_EnableIRQ\r
+ #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ\r
+ #define NVIC_DisableIRQ __NVIC_DisableIRQ\r
+ #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ\r
+ #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ\r
+ #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ\r
+ #define NVIC_GetActive __NVIC_GetActive\r
+ #define NVIC_SetPriority __NVIC_SetPriority\r
+ #define NVIC_GetPriority __NVIC_GetPriority\r
+ #define NVIC_SystemReset __NVIC_SystemReset\r
+#endif /* CMSIS_NVIC_VIRTUAL */\r
+\r
+#ifdef CMSIS_VECTAB_VIRTUAL\r
+ #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE\r
+ #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h"\r
+ #endif\r
+ #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE\r
+#else\r
+ #define NVIC_SetVector __NVIC_SetVector\r
+ #define NVIC_GetVector __NVIC_GetVector\r
+#endif /* (CMSIS_VECTAB_VIRTUAL) */\r
+\r
+#define NVIC_USER_IRQ_OFFSET 16\r
+\r
+\r
+/* The following EXC_RETURN values are saved the LR on exception entry */\r
+#define EXC_RETURN_HANDLER (0xFFFFFFF1UL) /* return to Handler mode, uses MSP after return */\r
+#define EXC_RETURN_THREAD_MSP (0xFFFFFFF9UL) /* return to Thread mode, uses MSP after return */\r
+#define EXC_RETURN_THREAD_PSP (0xFFFFFFFDUL) /* return to Thread mode, uses PSP after return */\r
+#define EXC_RETURN_HANDLER_FPU (0xFFFFFFE1UL) /* return to Handler mode, uses MSP after return, restore floating-point state */\r
+#define EXC_RETURN_THREAD_MSP_FPU (0xFFFFFFE9UL) /* return to Thread mode, uses MSP after return, restore floating-point state */\r
+#define EXC_RETURN_THREAD_PSP_FPU (0xFFFFFFEDUL) /* return to Thread mode, uses PSP after return, restore floating-point state */\r
+\r
+\r
+/**\r
+ \brief Set Priority Grouping\r
+ \details Sets the priority grouping field using the required unlock sequence.\r
+ The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field.\r
+ Only values from 0..7 are used.\r
+ In case of a conflict between priority grouping and available\r
+ priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.\r
+ \param [in] PriorityGroup Priority grouping field.\r
+ */\r
+__STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup)\r
+{\r
+ uint32_t reg_value;\r
+ uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */\r
+\r
+ reg_value = SCB->AIRCR; /* read old register configuration */\r
+ reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */\r
+ reg_value = (reg_value |\r
+ ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |\r
+ (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key and priority group */\r
+ SCB->AIRCR = reg_value;\r
+}\r
+\r
+\r
+/**\r
+ \brief Get Priority Grouping\r
+ \details Reads the priority grouping field from the NVIC Interrupt Controller.\r
+ \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field).\r
+ */\r
+__STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void)\r
+{\r
+ return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos));\r
+}\r
+\r
+\r
+/**\r
+ \brief Enable Interrupt\r
+ \details Enables a device specific interrupt in the NVIC interrupt controller.\r
+ \param [in] IRQn Device specific interrupt number.\r
+ \note IRQn must not be negative.\r
+ */\r
+__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn)\r
+{\r
+ if ((int32_t)(IRQn) >= 0)\r
+ {\r
+ NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));\r
+ }\r
+}\r
+\r
+\r
+/**\r
+ \brief Get Interrupt Enable status\r
+ \details Returns a device specific interrupt enable status from the NVIC interrupt controller.\r
+ \param [in] IRQn Device specific interrupt number.\r
+ \return 0 Interrupt is not enabled.\r
+ \return 1 Interrupt is enabled.\r
+ \note IRQn must not be negative.\r
+ */\r
+__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn)\r
+{\r
+ if ((int32_t)(IRQn) >= 0)\r
+ {\r
+ return((uint32_t)(((NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));\r
+ }\r
+ else\r
+ {\r
+ return(0U);\r
+ }\r
+}\r
+\r
+\r
+/**\r
+ \brief Disable Interrupt\r
+ \details Disables a device specific interrupt in the NVIC interrupt controller.\r
+ \param [in] IRQn Device specific interrupt number.\r
+ \note IRQn must not be negative.\r
+ */\r
+__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn)\r
+{\r
+ if ((int32_t)(IRQn) >= 0)\r
+ {\r
+ NVIC->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));\r
+ __DSB();\r
+ __ISB();\r
+ }\r
+}\r
+\r
+\r
+/**\r
+ \brief Get Pending Interrupt\r
+ \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt.\r
+ \param [in] IRQn Device specific interrupt number.\r
+ \return 0 Interrupt status is not pending.\r
+ \return 1 Interrupt status is pending.\r
+ \note IRQn must not be negative.\r
+ */\r
+__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn)\r
+{\r
+ if ((int32_t)(IRQn) >= 0)\r
+ {\r
+ return((uint32_t)(((NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));\r
+ }\r
+ else\r
+ {\r
+ return(0U);\r
+ }\r
+}\r
+\r
+\r
+/**\r
+ \brief Set Pending Interrupt\r
+ \details Sets the pending bit of a device specific interrupt in the NVIC pending register.\r
+ \param [in] IRQn Device specific interrupt number.\r
+ \note IRQn must not be negative.\r
+ */\r
+__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn)\r
+{\r
+ if ((int32_t)(IRQn) >= 0)\r
+ {\r
+ NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));\r
+ }\r
+}\r
+\r
+\r
+/**\r
+ \brief Clear Pending Interrupt\r
+ \details Clears the pending bit of a device specific interrupt in the NVIC pending register.\r
+ \param [in] IRQn Device specific interrupt number.\r
+ \note IRQn must not be negative.\r
+ */\r
+__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn)\r
+{\r
+ if ((int32_t)(IRQn) >= 0)\r
+ {\r
+ NVIC->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));\r
+ }\r
+}\r
+\r
+\r
+/**\r
+ \brief Get Active Interrupt\r
+ \details Reads the active register in the NVIC and returns the active bit for the device specific interrupt.\r
+ \param [in] IRQn Device specific interrupt number.\r
+ \return 0 Interrupt status is not active.\r
+ \return 1 Interrupt status is active.\r
+ \note IRQn must not be negative.\r
+ */\r
+__STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn)\r
+{\r
+ if ((int32_t)(IRQn) >= 0)\r
+ {\r
+ return((uint32_t)(((NVIC->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));\r
+ }\r
+ else\r
+ {\r
+ return(0U);\r
+ }\r
+}\r
+\r
+\r
+/**\r
+ \brief Set Interrupt Priority\r
+ \details Sets the priority of a device specific interrupt or a processor exception.\r
+ The interrupt number can be positive to specify a device specific interrupt,\r
+ or negative to specify a processor exception.\r
+ \param [in] IRQn Interrupt number.\r
+ \param [in] priority Priority to set.\r
+ \note The priority cannot be set for every processor exception.\r
+ */\r
+__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)\r
+{\r
+ if ((int32_t)(IRQn) >= 0)\r
+ {\r
+ NVIC->IP[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);\r
+ }\r
+ else\r
+ {\r
+ SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);\r
+ }\r
+}\r
+\r
+\r
+/**\r
+ \brief Get Interrupt Priority\r
+ \details Reads the priority of a device specific interrupt or a processor exception.\r
+ The interrupt number can be positive to specify a device specific interrupt,\r
+ or negative to specify a processor exception.\r
+ \param [in] IRQn Interrupt number.\r
+ \return Interrupt Priority.\r
+ Value is aligned automatically to the implemented priority bits of the microcontroller.\r
+ */\r
+__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn)\r
+{\r
+\r
+ if ((int32_t)(IRQn) >= 0)\r
+ {\r
+ return(((uint32_t)NVIC->IP[((uint32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS)));\r
+ }\r
+ else\r
+ {\r
+ return(((uint32_t)SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS)));\r
+ }\r
+}\r
+\r
+\r
+/**\r
+ \brief Encode Priority\r
+ \details Encodes the priority for an interrupt with the given priority group,\r
+ preemptive priority value, and subpriority value.\r
+ In case of a conflict between priority grouping and available\r
+ priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.\r
+ \param [in] PriorityGroup Used priority group.\r
+ \param [in] PreemptPriority Preemptive priority value (starting from 0).\r
+ \param [in] SubPriority Subpriority value (starting from 0).\r
+ \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority().\r
+ */\r
+__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)\r
+{\r
+ uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */\r
+ uint32_t PreemptPriorityBits;\r
+ uint32_t SubPriorityBits;\r
+\r
+ PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);\r
+ SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));\r
+\r
+ return (\r
+ ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) |\r
+ ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL)))\r
+ );\r
+}\r
+\r
+\r
+/**\r
+ \brief Decode Priority\r
+ \details Decodes an interrupt priority value with a given priority group to\r
+ preemptive priority value and subpriority value.\r
+ In case of a conflict between priority grouping and available\r
+ priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set.\r
+ \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority().\r
+ \param [in] PriorityGroup Used priority group.\r
+ \param [out] pPreemptPriority Preemptive priority value (starting from 0).\r
+ \param [out] pSubPriority Subpriority value (starting from 0).\r
+ */\r
+__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority)\r
+{\r
+ uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */\r
+ uint32_t PreemptPriorityBits;\r
+ uint32_t SubPriorityBits;\r
+\r
+ PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);\r
+ SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));\r
+\r
+ *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL);\r
+ *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL);\r
+}\r
+\r
+\r
+/**\r
+ \brief Set Interrupt Vector\r
+ \details Sets an interrupt vector in SRAM based interrupt vector table.\r
+ The interrupt number can be positive to specify a device specific interrupt,\r
+ or negative to specify a processor exception.\r
+ VTOR must been relocated to SRAM before.\r
+ \param [in] IRQn Interrupt number\r
+ \param [in] vector Address of interrupt handler function\r
+ */\r
+__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector)\r
+{\r
+ uint32_t *vectors = (uint32_t *)SCB->VTOR;\r
+ vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector;\r
+}\r
+\r
+\r
+/**\r
+ \brief Get Interrupt Vector\r
+ \details Reads an interrupt vector from interrupt vector table.\r
+ The interrupt number can be positive to specify a device specific interrupt,\r
+ or negative to specify a processor exception.\r
+ \param [in] IRQn Interrupt number.\r
+ \return Address of interrupt handler function\r
+ */\r
+__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn)\r
+{\r
+ uint32_t *vectors = (uint32_t *)SCB->VTOR;\r
+ return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET];\r
+}\r
+\r
+\r
+/**\r
+ \brief System Reset\r
+ \details Initiates a system reset request to reset the MCU.\r
+ */\r
+__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void)\r
+{\r
+ __DSB(); /* Ensure all outstanding memory accesses included\r
+ buffered write are completed before reset */\r
+ SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |\r
+ (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) |\r
+ SCB_AIRCR_SYSRESETREQ_Msk ); /* Keep priority group unchanged */\r
+ __DSB(); /* Ensure completion of memory access */\r
+\r
+ for(;;) /* wait until reset */\r
+ {\r
+ __NOP();\r
+ }\r
+}\r
+\r
+/*@} end of CMSIS_Core_NVICFunctions */\r
+\r
+/* ########################## MPU functions #################################### */\r
+\r
+#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)\r
+\r
+#include "mpu_armv7.h"\r
+\r
+#endif\r
+\r
+/* ########################## FPU functions #################################### */\r
+/**\r
+ \ingroup CMSIS_Core_FunctionInterface\r
+ \defgroup CMSIS_Core_FpuFunctions FPU Functions\r
+ \brief Function that provides FPU type.\r
+ @{\r
+ */\r
+\r
+/**\r
+ \brief get FPU type\r
+ \details returns the FPU type\r
+ \returns\r
+ - \b 0: No FPU\r
+ - \b 1: Single precision FPU\r
+ - \b 2: Double + Single precision FPU\r
+ */\r
+__STATIC_INLINE uint32_t SCB_GetFPUType(void)\r
+{\r
+ uint32_t mvfr0;\r
+\r
+ mvfr0 = SCB->MVFR0;\r
+ if ((mvfr0 & (FPU_MVFR0_Single_precision_Msk | FPU_MVFR0_Double_precision_Msk)) == 0x220U)\r
+ {\r
+ return 2U; /* Double + Single precision FPU */\r
+ }\r
+ else if ((mvfr0 & (FPU_MVFR0_Single_precision_Msk | FPU_MVFR0_Double_precision_Msk)) == 0x020U)\r
+ {\r
+ return 1U; /* Single precision FPU */\r
+ }\r
+ else\r
+ {\r
+ return 0U; /* No FPU */\r
+ }\r
+}\r
+\r
+\r
+/*@} end of CMSIS_Core_FpuFunctions */\r
+\r
+\r
+\r
+/* ########################## Cache functions #################################### */\r
+/**\r
+ \ingroup CMSIS_Core_FunctionInterface\r
+ \defgroup CMSIS_Core_CacheFunctions Cache Functions\r
+ \brief Functions that configure Instruction and Data cache.\r
+ @{\r
+ */\r
+\r
+/* Cache Size ID Register Macros */\r
+#define CCSIDR_WAYS(x) (((x) & SCB_CCSIDR_ASSOCIATIVITY_Msk) >> SCB_CCSIDR_ASSOCIATIVITY_Pos)\r
+#define CCSIDR_SETS(x) (((x) & SCB_CCSIDR_NUMSETS_Msk ) >> SCB_CCSIDR_NUMSETS_Pos )\r
+\r
+\r
+/**\r
+ \brief Enable I-Cache\r
+ \details Turns on I-Cache\r
+ */\r
+__STATIC_INLINE void SCB_EnableICache (void)\r
+{\r
+ #if defined (__ICACHE_PRESENT) && (__ICACHE_PRESENT == 1U)\r
+ __DSB();\r
+ __ISB();\r
+ SCB->ICIALLU = 0UL; /* invalidate I-Cache */\r
+ __DSB();\r
+ __ISB();\r
+ SCB->CCR |= (uint32_t)SCB_CCR_IC_Msk; /* enable I-Cache */\r
+ __DSB();\r
+ __ISB();\r
+ #endif\r
+}\r
+\r
+\r
+/**\r
+ \brief Disable I-Cache\r
+ \details Turns off I-Cache\r
+ */\r
+__STATIC_INLINE void SCB_DisableICache (void)\r
+{\r
+ #if defined (__ICACHE_PRESENT) && (__ICACHE_PRESENT == 1U)\r
+ __DSB();\r
+ __ISB();\r
+ SCB->CCR &= ~(uint32_t)SCB_CCR_IC_Msk; /* disable I-Cache */\r
+ SCB->ICIALLU = 0UL; /* invalidate I-Cache */\r
+ __DSB();\r
+ __ISB();\r
+ #endif\r
+}\r
+\r
+\r
+/**\r
+ \brief Invalidate I-Cache\r
+ \details Invalidates I-Cache\r
+ */\r
+__STATIC_INLINE void SCB_InvalidateICache (void)\r
+{\r
+ #if defined (__ICACHE_PRESENT) && (__ICACHE_PRESENT == 1U)\r
+ __DSB();\r
+ __ISB();\r
+ SCB->ICIALLU = 0UL;\r
+ __DSB();\r
+ __ISB();\r
+ #endif\r
+}\r
+\r
+\r
+/**\r
+ \brief Enable D-Cache\r
+ \details Turns on D-Cache\r
+ */\r
+__STATIC_INLINE void SCB_EnableDCache (void)\r
+{\r
+ #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U)\r
+ uint32_t ccsidr;\r
+ uint32_t sets;\r
+ uint32_t ways;\r
+\r
+ SCB->CSSELR = 0U; /*(0U << 1U) | 0U;*/ /* Level 1 data cache */\r
+ __DSB();\r
+\r
+ ccsidr = SCB->CCSIDR;\r
+\r
+ /* invalidate D-Cache */\r
+ sets = (uint32_t)(CCSIDR_SETS(ccsidr));\r
+ do {\r
+ ways = (uint32_t)(CCSIDR_WAYS(ccsidr));\r
+ do {\r
+ SCB->DCISW = (((sets << SCB_DCISW_SET_Pos) & SCB_DCISW_SET_Msk) |\r
+ ((ways << SCB_DCISW_WAY_Pos) & SCB_DCISW_WAY_Msk) );\r
+ #if defined ( __CC_ARM )\r
+ __schedule_barrier();\r
+ #endif\r
+ } while (ways-- != 0U);\r
+ } while(sets-- != 0U);\r
+ __DSB();\r
+\r
+ SCB->CCR |= (uint32_t)SCB_CCR_DC_Msk; /* enable D-Cache */\r
+\r
+ __DSB();\r
+ __ISB();\r
+ #endif\r
+}\r
+\r
+\r
+/**\r
+ \brief Disable D-Cache\r
+ \details Turns off D-Cache\r
+ */\r
+__STATIC_INLINE void SCB_DisableDCache (void)\r
+{\r
+ #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U)\r
+ uint32_t ccsidr;\r
+ uint32_t sets;\r
+ uint32_t ways;\r
+\r
+ SCB->CSSELR = 0U; /*(0U << 1U) | 0U;*/ /* Level 1 data cache */\r
+ __DSB();\r
+\r
+ SCB->CCR &= ~(uint32_t)SCB_CCR_DC_Msk; /* disable D-Cache */\r
+ __DSB();\r
+\r
+ ccsidr = SCB->CCSIDR;\r
+\r
+ /* clean & invalidate D-Cache */\r
+ sets = (uint32_t)(CCSIDR_SETS(ccsidr));\r
+ do {\r
+ ways = (uint32_t)(CCSIDR_WAYS(ccsidr));\r
+ do {\r
+ SCB->DCCISW = (((sets << SCB_DCCISW_SET_Pos) & SCB_DCCISW_SET_Msk) |\r
+ ((ways << SCB_DCCISW_WAY_Pos) & SCB_DCCISW_WAY_Msk) );\r
+ #if defined ( __CC_ARM )\r
+ __schedule_barrier();\r
+ #endif\r
+ } while (ways-- != 0U);\r
+ } while(sets-- != 0U);\r
+\r
+ __DSB();\r
+ __ISB();\r
+ #endif\r
+}\r
+\r
+\r
+/**\r
+ \brief Invalidate D-Cache\r
+ \details Invalidates D-Cache\r
+ */\r
+__STATIC_INLINE void SCB_InvalidateDCache (void)\r
+{\r
+ #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U)\r
+ uint32_t ccsidr;\r
+ uint32_t sets;\r
+ uint32_t ways;\r
+\r
+ SCB->CSSELR = 0U; /*(0U << 1U) | 0U;*/ /* Level 1 data cache */\r
+ __DSB();\r
+\r
+ ccsidr = SCB->CCSIDR;\r
+\r
+ /* invalidate D-Cache */\r
+ sets = (uint32_t)(CCSIDR_SETS(ccsidr));\r
+ do {\r
+ ways = (uint32_t)(CCSIDR_WAYS(ccsidr));\r
+ do {\r
+ SCB->DCISW = (((sets << SCB_DCISW_SET_Pos) & SCB_DCISW_SET_Msk) |\r
+ ((ways << SCB_DCISW_WAY_Pos) & SCB_DCISW_WAY_Msk) );\r
+ #if defined ( __CC_ARM )\r
+ __schedule_barrier();\r
+ #endif\r
+ } while (ways-- != 0U);\r
+ } while(sets-- != 0U);\r
+\r
+ __DSB();\r
+ __ISB();\r
+ #endif\r
+}\r
+\r
+\r
+/**\r
+ \brief Clean D-Cache\r
+ \details Cleans D-Cache\r
+ */\r
+__STATIC_INLINE void SCB_CleanDCache (void)\r
+{\r
+ #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U)\r
+ uint32_t ccsidr;\r
+ uint32_t sets;\r
+ uint32_t ways;\r
+\r
+ SCB->CSSELR = 0U; /*(0U << 1U) | 0U;*/ /* Level 1 data cache */\r
+ __DSB();\r
+\r
+ ccsidr = SCB->CCSIDR;\r
+\r
+ /* clean D-Cache */\r
+ sets = (uint32_t)(CCSIDR_SETS(ccsidr));\r
+ do {\r
+ ways = (uint32_t)(CCSIDR_WAYS(ccsidr));\r
+ do {\r
+ SCB->DCCSW = (((sets << SCB_DCCSW_SET_Pos) & SCB_DCCSW_SET_Msk) |\r
+ ((ways << SCB_DCCSW_WAY_Pos) & SCB_DCCSW_WAY_Msk) );\r
+ #if defined ( __CC_ARM )\r
+ __schedule_barrier();\r
+ #endif\r
+ } while (ways-- != 0U);\r
+ } while(sets-- != 0U);\r
+\r
+ __DSB();\r
+ __ISB();\r
+ #endif\r
+}\r
+\r
+\r
+/**\r
+ \brief Clean & Invalidate D-Cache\r
+ \details Cleans and Invalidates D-Cache\r
+ */\r
+__STATIC_INLINE void SCB_CleanInvalidateDCache (void)\r
+{\r
+ #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U)\r
+ uint32_t ccsidr;\r
+ uint32_t sets;\r
+ uint32_t ways;\r
+\r
+ SCB->CSSELR = 0U; /*(0U << 1U) | 0U;*/ /* Level 1 data cache */\r
+ __DSB();\r
+\r
+ ccsidr = SCB->CCSIDR;\r
+\r
+ /* clean & invalidate D-Cache */\r
+ sets = (uint32_t)(CCSIDR_SETS(ccsidr));\r
+ do {\r
+ ways = (uint32_t)(CCSIDR_WAYS(ccsidr));\r
+ do {\r
+ SCB->DCCISW = (((sets << SCB_DCCISW_SET_Pos) & SCB_DCCISW_SET_Msk) |\r
+ ((ways << SCB_DCCISW_WAY_Pos) & SCB_DCCISW_WAY_Msk) );\r
+ #if defined ( __CC_ARM )\r
+ __schedule_barrier();\r
+ #endif\r
+ } while (ways-- != 0U);\r
+ } while(sets-- != 0U);\r
+\r
+ __DSB();\r
+ __ISB();\r
+ #endif\r
+}\r
+\r
+\r
+/**\r
+ \brief D-Cache Invalidate by address\r
+ \details Invalidates D-Cache for the given address\r
+ \param[in] addr address (aligned to 32-byte boundary)\r
+ \param[in] dsize size of memory block (in number of bytes)\r
+*/\r
+__STATIC_INLINE void SCB_InvalidateDCache_by_Addr (uint32_t *addr, int32_t dsize)\r
+{\r
+ #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U)\r
+ int32_t op_size = dsize;\r
+ uint32_t op_addr = (uint32_t)addr;\r
+ int32_t linesize = 32; /* in Cortex-M7 size of cache line is fixed to 8 words (32 bytes) */\r
+\r
+ __DSB();\r
+\r
+ while (op_size > 0) {\r
+ SCB->DCIMVAC = op_addr;\r
+ op_addr += (uint32_t)linesize;\r
+ op_size -= linesize;\r
+ }\r
+\r
+ __DSB();\r
+ __ISB();\r
+ #endif\r
+}\r
+\r
+\r
+/**\r
+ \brief D-Cache Clean by address\r
+ \details Cleans D-Cache for the given address\r
+ \param[in] addr address (aligned to 32-byte boundary)\r
+ \param[in] dsize size of memory block (in number of bytes)\r
+*/\r
+__STATIC_INLINE void SCB_CleanDCache_by_Addr (uint32_t *addr, int32_t dsize)\r
+{\r
+ #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U)\r
+ int32_t op_size = dsize;\r
+ uint32_t op_addr = (uint32_t) addr;\r
+ int32_t linesize = 32; /* in Cortex-M7 size of cache line is fixed to 8 words (32 bytes) */\r
+\r
+ __DSB();\r
+\r
+ while (op_size > 0) {\r
+ SCB->DCCMVAC = op_addr;\r
+ op_addr += (uint32_t)linesize;\r
+ op_size -= linesize;\r
+ }\r
+\r
+ __DSB();\r
+ __ISB();\r
+ #endif\r
+}\r
+\r
+\r
+/**\r
+ \brief D-Cache Clean and Invalidate by address\r
+ \details Cleans and invalidates D_Cache for the given address\r
+ \param[in] addr address (aligned to 32-byte boundary)\r
+ \param[in] dsize size of memory block (in number of bytes)\r
+*/\r
+__STATIC_INLINE void SCB_CleanInvalidateDCache_by_Addr (uint32_t *addr, int32_t dsize)\r
+{\r
+ #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U)\r
+ int32_t op_size = dsize;\r
+ uint32_t op_addr = (uint32_t) addr;\r
+ int32_t linesize = 32; /* in Cortex-M7 size of cache line is fixed to 8 words (32 bytes) */\r
+\r
+ __DSB();\r
+\r
+ while (op_size > 0) {\r
+ SCB->DCCIMVAC = op_addr;\r
+ op_addr += (uint32_t)linesize;\r
+ op_size -= linesize;\r
+ }\r
+\r
+ __DSB();\r
+ __ISB();\r
+ #endif\r
+}\r
+\r
+\r
+/*@} end of CMSIS_Core_CacheFunctions */\r
+\r
+\r
+\r
+/* ################################## SysTick function ############################################ */\r
+/**\r
+ \ingroup CMSIS_Core_FunctionInterface\r
+ \defgroup CMSIS_Core_SysTickFunctions SysTick Functions\r
+ \brief Functions that configure the System.\r
+ @{\r
+ */\r
+\r
+#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U)\r
+\r
+/**\r
+ \brief System Tick Configuration\r
+ \details Initializes the System Timer and its interrupt, and starts the System Tick Timer.\r
+ Counter is in free running mode to generate periodic interrupts.\r
+ \param [in] ticks Number of ticks between two interrupts.\r
+ \return 0 Function succeeded.\r
+ \return 1 Function failed.\r
+ \note When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the\r
+ function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>\r
+ must contain a vendor-specific implementation of this function.\r
+ */\r
+__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)\r
+{\r
+ if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk)\r
+ {\r
+ return (1UL); /* Reload value impossible */\r
+ }\r
+\r
+ SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */\r
+ NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */\r
+ SysTick->VAL = 0UL; /* Load the SysTick Counter Value */\r
+ SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk |\r
+ SysTick_CTRL_TICKINT_Msk |\r
+ SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */\r
+ return (0UL); /* Function successful */\r
+}\r
+\r
+#endif\r
+\r
+/*@} end of CMSIS_Core_SysTickFunctions */\r
+\r
+\r
+\r
+/* ##################################### Debug In/Output function ########################################### */\r
+/**\r
+ \ingroup CMSIS_Core_FunctionInterface\r
+ \defgroup CMSIS_core_DebugFunctions ITM Functions\r
+ \brief Functions that access the ITM debug interface.\r
+ @{\r
+ */\r
+\r
+extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters. */\r
+#define ITM_RXBUFFER_EMPTY ((int32_t)0x5AA55AA5U) /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */\r
+\r
+\r
+/**\r
+ \brief ITM Send Character\r
+ \details Transmits a character via the ITM channel 0, and\r
+ \li Just returns when no debugger is connected that has booked the output.\r
+ \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted.\r
+ \param [in] ch Character to transmit.\r
+ \returns Character to transmit.\r
+ */\r
+__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch)\r
+{\r
+ if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) && /* ITM enabled */\r
+ ((ITM->TER & 1UL ) != 0UL) ) /* ITM Port #0 enabled */\r
+ {\r
+ while (ITM->PORT[0U].u32 == 0UL)\r
+ {\r
+ __NOP();\r
+ }\r
+ ITM->PORT[0U].u8 = (uint8_t)ch;\r
+ }\r
+ return (ch);\r
+}\r
+\r
+\r
+/**\r
+ \brief ITM Receive Character\r
+ \details Inputs a character via the external variable \ref ITM_RxBuffer.\r
+ \return Received character.\r
+ \return -1 No character pending.\r
+ */\r
+__STATIC_INLINE int32_t ITM_ReceiveChar (void)\r
+{\r
+ int32_t ch = -1; /* no character available */\r
+\r
+ if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY)\r
+ {\r
+ ch = ITM_RxBuffer;\r
+ ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */\r
+ }\r
+\r
+ return (ch);\r
+}\r
+\r
+\r
+/**\r
+ \brief ITM Check Character\r
+ \details Checks whether a character is pending for reading in the variable \ref ITM_RxBuffer.\r
+ \return 0 No character available.\r
+ \return 1 Character available.\r
+ */\r
+__STATIC_INLINE int32_t ITM_CheckChar (void)\r
+{\r
+\r
+ if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY)\r
+ {\r
+ return (0); /* no character available */\r
+ }\r
+ else\r
+ {\r
+ return (1); /* character available */\r
+ }\r
+}\r
+\r
+/*@} end of CMSIS_core_DebugFunctions */\r
+\r
+\r
+\r
+\r
+#ifdef __cplusplus\r
+}\r
+#endif\r
+\r
+#endif /* __CORE_CM7_H_DEPENDANT */\r
+\r
+#endif /* __CMSIS_GENERIC */\r
--- /dev/null
+/**************************************************************************//**\r
+ * @file core_sc000.h\r
+ * @brief CMSIS SC000 Core Peripheral Access Layer Header File\r
+ * @version V5.0.5\r
+ * @date 28. May 2018\r
+ ******************************************************************************/\r
+/*\r
+ * Copyright (c) 2009-2018 Arm Limited. All rights reserved.\r
+ *\r
+ * SPDX-License-Identifier: Apache-2.0\r
+ *\r
+ * Licensed under the Apache License, Version 2.0 (the License); you may\r
+ * not use this file except in compliance with the License.\r
+ * You may obtain a copy of the License at\r
+ *\r
+ * www.apache.org/licenses/LICENSE-2.0\r
+ *\r
+ * Unless required by applicable law or agreed to in writing, software\r
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT\r
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\r
+ * See the License for the specific language governing permissions and\r
+ * limitations under the License.\r
+ */\r
+\r
+#if defined ( __ICCARM__ )\r
+ #pragma system_include /* treat file as system include file for MISRA check */\r
+#elif defined (__clang__)\r
+ #pragma clang system_header /* treat file as system include file */\r
+#endif\r
+\r
+#ifndef __CORE_SC000_H_GENERIC\r
+#define __CORE_SC000_H_GENERIC\r
+\r
+#include <stdint.h>\r
+\r
+#ifdef __cplusplus\r
+ extern "C" {\r
+#endif\r
+\r
+/**\r
+ \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions\r
+ CMSIS violates the following MISRA-C:2004 rules:\r
+\r
+ \li Required Rule 8.5, object/function definition in header file.<br>\r
+ Function definitions in header files are used to allow 'inlining'.\r
+\r
+ \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>\r
+ Unions are used for effective representation of core registers.\r
+\r
+ \li Advisory Rule 19.7, Function-like macro defined.<br>\r
+ Function-like macros are used to allow more efficient code.\r
+ */\r
+\r
+\r
+/*******************************************************************************\r
+ * CMSIS definitions\r
+ ******************************************************************************/\r
+/**\r
+ \ingroup SC000\r
+ @{\r
+ */\r
+\r
+#include "cmsis_version.h"\r
+\r
+/* CMSIS SC000 definitions */\r
+#define __SC000_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */\r
+#define __SC000_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */\r
+#define __SC000_CMSIS_VERSION ((__SC000_CMSIS_VERSION_MAIN << 16U) | \\r
+ __SC000_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */\r
+\r
+#define __CORTEX_SC (000U) /*!< Cortex secure core */\r
+\r
+/** __FPU_USED indicates whether an FPU is used or not.\r
+ This core does not support an FPU at all\r
+*/\r
+#define __FPU_USED 0U\r
+\r
+#if defined ( __CC_ARM )\r
+ #if defined __TARGET_FPU_VFP\r
+ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"\r
+ #endif\r
+\r
+#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)\r
+ #if defined __ARM_PCS_VFP\r
+ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"\r
+ #endif\r
+\r
+#elif defined ( __GNUC__ )\r
+ #if defined (__VFP_FP__) && !defined(__SOFTFP__)\r
+ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"\r
+ #endif\r
+\r
+#elif defined ( __ICCARM__ )\r
+ #if defined __ARMVFP__\r
+ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"\r
+ #endif\r
+\r
+#elif defined ( __TI_ARM__ )\r
+ #if defined __TI_VFP_SUPPORT__\r
+ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"\r
+ #endif\r
+\r
+#elif defined ( __TASKING__ )\r
+ #if defined __FPU_VFP__\r
+ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"\r
+ #endif\r
+\r
+#elif defined ( __CSMC__ )\r
+ #if ( __CSMC__ & 0x400U)\r
+ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"\r
+ #endif\r
+\r
+#endif\r
+\r
+#include "cmsis_compiler.h" /* CMSIS compiler specific defines */\r
+\r
+\r
+#ifdef __cplusplus\r
+}\r
+#endif\r
+\r
+#endif /* __CORE_SC000_H_GENERIC */\r
+\r
+#ifndef __CMSIS_GENERIC\r
+\r
+#ifndef __CORE_SC000_H_DEPENDANT\r
+#define __CORE_SC000_H_DEPENDANT\r
+\r
+#ifdef __cplusplus\r
+ extern "C" {\r
+#endif\r
+\r
+/* check device defines and use defaults */\r
+#if defined __CHECK_DEVICE_DEFINES\r
+ #ifndef __SC000_REV\r
+ #define __SC000_REV 0x0000U\r
+ #warning "__SC000_REV not defined in device header file; using default!"\r
+ #endif\r
+\r
+ #ifndef __MPU_PRESENT\r
+ #define __MPU_PRESENT 0U\r
+ #warning "__MPU_PRESENT not defined in device header file; using default!"\r
+ #endif\r
+\r
+ #ifndef __NVIC_PRIO_BITS\r
+ #define __NVIC_PRIO_BITS 2U\r
+ #warning "__NVIC_PRIO_BITS not defined in device header file; using default!"\r
+ #endif\r
+\r
+ #ifndef __Vendor_SysTickConfig\r
+ #define __Vendor_SysTickConfig 0U\r
+ #warning "__Vendor_SysTickConfig not defined in device header file; using default!"\r
+ #endif\r
+#endif\r
+\r
+/* IO definitions (access restrictions to peripheral registers) */\r
+/**\r
+ \defgroup CMSIS_glob_defs CMSIS Global Defines\r
+\r
+ <strong>IO Type Qualifiers</strong> are used\r
+ \li to specify the access to peripheral variables.\r
+ \li for automatic generation of peripheral register debug information.\r
+*/\r
+#ifdef __cplusplus\r
+ #define __I volatile /*!< Defines 'read only' permissions */\r
+#else\r
+ #define __I volatile const /*!< Defines 'read only' permissions */\r
+#endif\r
+#define __O volatile /*!< Defines 'write only' permissions */\r
+#define __IO volatile /*!< Defines 'read / write' permissions */\r
+\r
+/* following defines should be used for structure members */\r
+#define __IM volatile const /*! Defines 'read only' structure member permissions */\r
+#define __OM volatile /*! Defines 'write only' structure member permissions */\r
+#define __IOM volatile /*! Defines 'read / write' structure member permissions */\r
+\r
+/*@} end of group SC000 */\r
+\r
+\r
+\r
+/*******************************************************************************\r
+ * Register Abstraction\r
+ Core Register contain:\r
+ - Core Register\r
+ - Core NVIC Register\r
+ - Core SCB Register\r
+ - Core SysTick Register\r
+ - Core MPU Register\r
+ ******************************************************************************/\r
+/**\r
+ \defgroup CMSIS_core_register Defines and Type Definitions\r
+ \brief Type definitions and defines for Cortex-M processor based devices.\r
+*/\r
+\r
+/**\r
+ \ingroup CMSIS_core_register\r
+ \defgroup CMSIS_CORE Status and Control Registers\r
+ \brief Core Register type definitions.\r
+ @{\r
+ */\r
+\r
+/**\r
+ \brief Union type to access the Application Program Status Register (APSR).\r
+ */\r
+typedef union\r
+{\r
+ struct\r
+ {\r
+ uint32_t _reserved0:28; /*!< bit: 0..27 Reserved */\r
+ uint32_t V:1; /*!< bit: 28 Overflow condition code flag */\r
+ uint32_t C:1; /*!< bit: 29 Carry condition code flag */\r
+ uint32_t Z:1; /*!< bit: 30 Zero condition code flag */\r
+ uint32_t N:1; /*!< bit: 31 Negative condition code flag */\r
+ } b; /*!< Structure used for bit access */\r
+ uint32_t w; /*!< Type used for word access */\r
+} APSR_Type;\r
+\r
+/* APSR Register Definitions */\r
+#define APSR_N_Pos 31U /*!< APSR: N Position */\r
+#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */\r
+\r
+#define APSR_Z_Pos 30U /*!< APSR: Z Position */\r
+#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */\r
+\r
+#define APSR_C_Pos 29U /*!< APSR: C Position */\r
+#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */\r
+\r
+#define APSR_V_Pos 28U /*!< APSR: V Position */\r
+#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */\r
+\r
+\r
+/**\r
+ \brief Union type to access the Interrupt Program Status Register (IPSR).\r
+ */\r
+typedef union\r
+{\r
+ struct\r
+ {\r
+ uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */\r
+ uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */\r
+ } b; /*!< Structure used for bit access */\r
+ uint32_t w; /*!< Type used for word access */\r
+} IPSR_Type;\r
+\r
+/* IPSR Register Definitions */\r
+#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */\r
+#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */\r
+\r
+\r
+/**\r
+ \brief Union type to access the Special-Purpose Program Status Registers (xPSR).\r
+ */\r
+typedef union\r
+{\r
+ struct\r
+ {\r
+ uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */\r
+ uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */\r
+ uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */\r
+ uint32_t _reserved1:3; /*!< bit: 25..27 Reserved */\r
+ uint32_t V:1; /*!< bit: 28 Overflow condition code flag */\r
+ uint32_t C:1; /*!< bit: 29 Carry condition code flag */\r
+ uint32_t Z:1; /*!< bit: 30 Zero condition code flag */\r
+ uint32_t N:1; /*!< bit: 31 Negative condition code flag */\r
+ } b; /*!< Structure used for bit access */\r
+ uint32_t w; /*!< Type used for word access */\r
+} xPSR_Type;\r
+\r
+/* xPSR Register Definitions */\r
+#define xPSR_N_Pos 31U /*!< xPSR: N Position */\r
+#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */\r
+\r
+#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */\r
+#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */\r
+\r
+#define xPSR_C_Pos 29U /*!< xPSR: C Position */\r
+#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */\r
+\r
+#define xPSR_V_Pos 28U /*!< xPSR: V Position */\r
+#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */\r
+\r
+#define xPSR_T_Pos 24U /*!< xPSR: T Position */\r
+#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */\r
+\r
+#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */\r
+#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */\r
+\r
+\r
+/**\r
+ \brief Union type to access the Control Registers (CONTROL).\r
+ */\r
+typedef union\r
+{\r
+ struct\r
+ {\r
+ uint32_t _reserved0:1; /*!< bit: 0 Reserved */\r
+ uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */\r
+ uint32_t _reserved1:30; /*!< bit: 2..31 Reserved */\r
+ } b; /*!< Structure used for bit access */\r
+ uint32_t w; /*!< Type used for word access */\r
+} CONTROL_Type;\r
+\r
+/* CONTROL Register Definitions */\r
+#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */\r
+#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */\r
+\r
+/*@} end of group CMSIS_CORE */\r
+\r
+\r
+/**\r
+ \ingroup CMSIS_core_register\r
+ \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC)\r
+ \brief Type definitions for the NVIC Registers\r
+ @{\r
+ */\r
+\r
+/**\r
+ \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC).\r
+ */\r
+typedef struct\r
+{\r
+ __IOM uint32_t ISER[1U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */\r
+ uint32_t RESERVED0[31U];\r
+ __IOM uint32_t ICER[1U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */\r
+ uint32_t RSERVED1[31U];\r
+ __IOM uint32_t ISPR[1U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */\r
+ uint32_t RESERVED2[31U];\r
+ __IOM uint32_t ICPR[1U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */\r
+ uint32_t RESERVED3[31U];\r
+ uint32_t RESERVED4[64U];\r
+ __IOM uint32_t IP[8U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register */\r
+} NVIC_Type;\r
+\r
+/*@} end of group CMSIS_NVIC */\r
+\r
+\r
+/**\r
+ \ingroup CMSIS_core_register\r
+ \defgroup CMSIS_SCB System Control Block (SCB)\r
+ \brief Type definitions for the System Control Block Registers\r
+ @{\r
+ */\r
+\r
+/**\r
+ \brief Structure type to access the System Control Block (SCB).\r
+ */\r
+typedef struct\r
+{\r
+ __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */\r
+ __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */\r
+ __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */\r
+ __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */\r
+ __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */\r
+ __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */\r
+ uint32_t RESERVED0[1U];\r
+ __IOM uint32_t SHP[2U]; /*!< Offset: 0x01C (R/W) System Handlers Priority Registers. [0] is RESERVED */\r
+ __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */\r
+ uint32_t RESERVED1[154U];\r
+ __IOM uint32_t SFCR; /*!< Offset: 0x290 (R/W) Security Features Control Register */\r
+} SCB_Type;\r
+\r
+/* SCB CPUID Register Definitions */\r
+#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */\r
+#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */\r
+\r
+#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */\r
+#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */\r
+\r
+#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */\r
+#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */\r
+\r
+#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */\r
+#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */\r
+\r
+#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */\r
+#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */\r
+\r
+/* SCB Interrupt Control State Register Definitions */\r
+#define SCB_ICSR_NMIPENDSET_Pos 31U /*!< SCB ICSR: NMIPENDSET Position */\r
+#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */\r
+\r
+#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */\r
+#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */\r
+\r
+#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */\r
+#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */\r
+\r
+#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */\r
+#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */\r
+\r
+#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */\r
+#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */\r
+\r
+#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */\r
+#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */\r
+\r
+#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */\r
+#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */\r
+\r
+#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */\r
+#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */\r
+\r
+#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */\r
+#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */\r
+\r
+/* SCB Interrupt Control State Register Definitions */\r
+#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */\r
+#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */\r
+\r
+/* SCB Application Interrupt and Reset Control Register Definitions */\r
+#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */\r
+#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */\r
+\r
+#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */\r
+#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */\r
+\r
+#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */\r
+#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */\r
+\r
+#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */\r
+#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */\r
+\r
+#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */\r
+#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */\r
+\r
+/* SCB System Control Register Definitions */\r
+#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */\r
+#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */\r
+\r
+#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */\r
+#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */\r
+\r
+#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */\r
+#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */\r
+\r
+/* SCB Configuration Control Register Definitions */\r
+#define SCB_CCR_STKALIGN_Pos 9U /*!< SCB CCR: STKALIGN Position */\r
+#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */\r
+\r
+#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */\r
+#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */\r
+\r
+/* SCB System Handler Control and State Register Definitions */\r
+#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */\r
+#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */\r
+\r
+/*@} end of group CMSIS_SCB */\r
+\r
+\r
+/**\r
+ \ingroup CMSIS_core_register\r
+ \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB)\r
+ \brief Type definitions for the System Control and ID Register not in the SCB\r
+ @{\r
+ */\r
+\r
+/**\r
+ \brief Structure type to access the System Control and ID Register not in the SCB.\r
+ */\r
+typedef struct\r
+{\r
+ uint32_t RESERVED0[2U];\r
+ __IOM uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */\r
+} SCnSCB_Type;\r
+\r
+/* Auxiliary Control Register Definitions */\r
+#define SCnSCB_ACTLR_DISMCYCINT_Pos 0U /*!< ACTLR: DISMCYCINT Position */\r
+#define SCnSCB_ACTLR_DISMCYCINT_Msk (1UL /*<< SCnSCB_ACTLR_DISMCYCINT_Pos*/) /*!< ACTLR: DISMCYCINT Mask */\r
+\r
+/*@} end of group CMSIS_SCnotSCB */\r
+\r
+\r
+/**\r
+ \ingroup CMSIS_core_register\r
+ \defgroup CMSIS_SysTick System Tick Timer (SysTick)\r
+ \brief Type definitions for the System Timer Registers.\r
+ @{\r
+ */\r
+\r
+/**\r
+ \brief Structure type to access the System Timer (SysTick).\r
+ */\r
+typedef struct\r
+{\r
+ __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */\r
+ __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */\r
+ __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */\r
+ __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */\r
+} SysTick_Type;\r
+\r
+/* SysTick Control / Status Register Definitions */\r
+#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */\r
+#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */\r
+\r
+#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */\r
+#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */\r
+\r
+#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */\r
+#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */\r
+\r
+#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */\r
+#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */\r
+\r
+/* SysTick Reload Register Definitions */\r
+#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */\r
+#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */\r
+\r
+/* SysTick Current Register Definitions */\r
+#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */\r
+#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */\r
+\r
+/* SysTick Calibration Register Definitions */\r
+#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */\r
+#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */\r
+\r
+#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */\r
+#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */\r
+\r
+#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */\r
+#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */\r
+\r
+/*@} end of group CMSIS_SysTick */\r
+\r
+#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)\r
+/**\r
+ \ingroup CMSIS_core_register\r
+ \defgroup CMSIS_MPU Memory Protection Unit (MPU)\r
+ \brief Type definitions for the Memory Protection Unit (MPU)\r
+ @{\r
+ */\r
+\r
+/**\r
+ \brief Structure type to access the Memory Protection Unit (MPU).\r
+ */\r
+typedef struct\r
+{\r
+ __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */\r
+ __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */\r
+ __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */\r
+ __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */\r
+ __IOM uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */\r
+} MPU_Type;\r
+\r
+/* MPU Type Register Definitions */\r
+#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */\r
+#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */\r
+\r
+#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */\r
+#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */\r
+\r
+#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */\r
+#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */\r
+\r
+/* MPU Control Register Definitions */\r
+#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */\r
+#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */\r
+\r
+#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */\r
+#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */\r
+\r
+#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */\r
+#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */\r
+\r
+/* MPU Region Number Register Definitions */\r
+#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */\r
+#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */\r
+\r
+/* MPU Region Base Address Register Definitions */\r
+#define MPU_RBAR_ADDR_Pos 8U /*!< MPU RBAR: ADDR Position */\r
+#define MPU_RBAR_ADDR_Msk (0xFFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */\r
+\r
+#define MPU_RBAR_VALID_Pos 4U /*!< MPU RBAR: VALID Position */\r
+#define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */\r
+\r
+#define MPU_RBAR_REGION_Pos 0U /*!< MPU RBAR: REGION Position */\r
+#define MPU_RBAR_REGION_Msk (0xFUL /*<< MPU_RBAR_REGION_Pos*/) /*!< MPU RBAR: REGION Mask */\r
+\r
+/* MPU Region Attribute and Size Register Definitions */\r
+#define MPU_RASR_ATTRS_Pos 16U /*!< MPU RASR: MPU Region Attribute field Position */\r
+#define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */\r
+\r
+#define MPU_RASR_XN_Pos 28U /*!< MPU RASR: ATTRS.XN Position */\r
+#define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */\r
+\r
+#define MPU_RASR_AP_Pos 24U /*!< MPU RASR: ATTRS.AP Position */\r
+#define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */\r
+\r
+#define MPU_RASR_TEX_Pos 19U /*!< MPU RASR: ATTRS.TEX Position */\r
+#define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */\r
+\r
+#define MPU_RASR_S_Pos 18U /*!< MPU RASR: ATTRS.S Position */\r
+#define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */\r
+\r
+#define MPU_RASR_C_Pos 17U /*!< MPU RASR: ATTRS.C Position */\r
+#define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */\r
+\r
+#define MPU_RASR_B_Pos 16U /*!< MPU RASR: ATTRS.B Position */\r
+#define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */\r
+\r
+#define MPU_RASR_SRD_Pos 8U /*!< MPU RASR: Sub-Region Disable Position */\r
+#define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */\r
+\r
+#define MPU_RASR_SIZE_Pos 1U /*!< MPU RASR: Region Size Field Position */\r
+#define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */\r
+\r
+#define MPU_RASR_ENABLE_Pos 0U /*!< MPU RASR: Region enable bit Position */\r
+#define MPU_RASR_ENABLE_Msk (1UL /*<< MPU_RASR_ENABLE_Pos*/) /*!< MPU RASR: Region enable bit Disable Mask */\r
+\r
+/*@} end of group CMSIS_MPU */\r
+#endif\r
+\r
+\r
+/**\r
+ \ingroup CMSIS_core_register\r
+ \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug)\r
+ \brief SC000 Core Debug Registers (DCB registers, SHCSR, and DFSR) are only accessible over DAP and not via processor.\r
+ Therefore they are not covered by the SC000 header file.\r
+ @{\r
+ */\r
+/*@} end of group CMSIS_CoreDebug */\r
+\r
+\r
+/**\r
+ \ingroup CMSIS_core_register\r
+ \defgroup CMSIS_core_bitfield Core register bit field macros\r
+ \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk).\r
+ @{\r
+ */\r
+\r
+/**\r
+ \brief Mask and shift a bit field value for use in a register bit range.\r
+ \param[in] field Name of the register bit field.\r
+ \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type.\r
+ \return Masked and shifted value.\r
+*/\r
+#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk)\r
+\r
+/**\r
+ \brief Mask and shift a register value to extract a bit filed value.\r
+ \param[in] field Name of the register bit field.\r
+ \param[in] value Value of register. This parameter is interpreted as an uint32_t type.\r
+ \return Masked and shifted bit field value.\r
+*/\r
+#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos)\r
+\r
+/*@} end of group CMSIS_core_bitfield */\r
+\r
+\r
+/**\r
+ \ingroup CMSIS_core_register\r
+ \defgroup CMSIS_core_base Core Definitions\r
+ \brief Definitions for base addresses, unions, and structures.\r
+ @{\r
+ */\r
+\r
+/* Memory mapping of Core Hardware */\r
+#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */\r
+#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */\r
+#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */\r
+#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */\r
+\r
+#define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */\r
+#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */\r
+#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */\r
+#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */\r
+\r
+#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)\r
+ #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */\r
+ #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */\r
+#endif\r
+\r
+/*@} */\r
+\r
+\r
+\r
+/*******************************************************************************\r
+ * Hardware Abstraction Layer\r
+ Core Function Interface contains:\r
+ - Core NVIC Functions\r
+ - Core SysTick Functions\r
+ - Core Register Access Functions\r
+ ******************************************************************************/\r
+/**\r
+ \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference\r
+*/\r
+\r
+\r
+\r
+/* ########################## NVIC functions #################################### */\r
+/**\r
+ \ingroup CMSIS_Core_FunctionInterface\r
+ \defgroup CMSIS_Core_NVICFunctions NVIC Functions\r
+ \brief Functions that manage interrupts and exceptions via the NVIC.\r
+ @{\r
+ */\r
+\r
+#ifdef CMSIS_NVIC_VIRTUAL\r
+ #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE\r
+ #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h"\r
+ #endif\r
+ #include CMSIS_NVIC_VIRTUAL_HEADER_FILE\r
+#else\r
+/*#define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping not available for SC000 */\r
+/*#define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping not available for SC000 */\r
+ #define NVIC_EnableIRQ __NVIC_EnableIRQ\r
+ #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ\r
+ #define NVIC_DisableIRQ __NVIC_DisableIRQ\r
+ #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ\r
+ #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ\r
+ #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ\r
+/*#define NVIC_GetActive __NVIC_GetActive not available for SC000 */\r
+ #define NVIC_SetPriority __NVIC_SetPriority\r
+ #define NVIC_GetPriority __NVIC_GetPriority\r
+ #define NVIC_SystemReset __NVIC_SystemReset\r
+#endif /* CMSIS_NVIC_VIRTUAL */\r
+\r
+#ifdef CMSIS_VECTAB_VIRTUAL\r
+ #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE\r
+ #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h"\r
+ #endif\r
+ #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE\r
+#else\r
+ #define NVIC_SetVector __NVIC_SetVector\r
+ #define NVIC_GetVector __NVIC_GetVector\r
+#endif /* (CMSIS_VECTAB_VIRTUAL) */\r
+\r
+#define NVIC_USER_IRQ_OFFSET 16\r
+\r
+\r
+/* The following EXC_RETURN values are saved the LR on exception entry */\r
+#define EXC_RETURN_HANDLER (0xFFFFFFF1UL) /* return to Handler mode, uses MSP after return */\r
+#define EXC_RETURN_THREAD_MSP (0xFFFFFFF9UL) /* return to Thread mode, uses MSP after return */\r
+#define EXC_RETURN_THREAD_PSP (0xFFFFFFFDUL) /* return to Thread mode, uses PSP after return */\r
+\r
+\r
+/* Interrupt Priorities are WORD accessible only under Armv6-M */\r
+/* The following MACROS handle generation of the register offset and byte masks */\r
+#define _BIT_SHIFT(IRQn) ( ((((uint32_t)(int32_t)(IRQn)) ) & 0x03UL) * 8UL)\r
+#define _SHP_IDX(IRQn) ( (((((uint32_t)(int32_t)(IRQn)) & 0x0FUL)-8UL) >> 2UL) )\r
+#define _IP_IDX(IRQn) ( (((uint32_t)(int32_t)(IRQn)) >> 2UL) )\r
+\r
+\r
+/**\r
+ \brief Enable Interrupt\r
+ \details Enables a device specific interrupt in the NVIC interrupt controller.\r
+ \param [in] IRQn Device specific interrupt number.\r
+ \note IRQn must not be negative.\r
+ */\r
+__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn)\r
+{\r
+ if ((int32_t)(IRQn) >= 0)\r
+ {\r
+ NVIC->ISER[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));\r
+ }\r
+}\r
+\r
+\r
+/**\r
+ \brief Get Interrupt Enable status\r
+ \details Returns a device specific interrupt enable status from the NVIC interrupt controller.\r
+ \param [in] IRQn Device specific interrupt number.\r
+ \return 0 Interrupt is not enabled.\r
+ \return 1 Interrupt is enabled.\r
+ \note IRQn must not be negative.\r
+ */\r
+__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn)\r
+{\r
+ if ((int32_t)(IRQn) >= 0)\r
+ {\r
+ return((uint32_t)(((NVIC->ISER[0U] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));\r
+ }\r
+ else\r
+ {\r
+ return(0U);\r
+ }\r
+}\r
+\r
+\r
+/**\r
+ \brief Disable Interrupt\r
+ \details Disables a device specific interrupt in the NVIC interrupt controller.\r
+ \param [in] IRQn Device specific interrupt number.\r
+ \note IRQn must not be negative.\r
+ */\r
+__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn)\r
+{\r
+ if ((int32_t)(IRQn) >= 0)\r
+ {\r
+ NVIC->ICER[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));\r
+ __DSB();\r
+ __ISB();\r
+ }\r
+}\r
+\r
+\r
+/**\r
+ \brief Get Pending Interrupt\r
+ \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt.\r
+ \param [in] IRQn Device specific interrupt number.\r
+ \return 0 Interrupt status is not pending.\r
+ \return 1 Interrupt status is pending.\r
+ \note IRQn must not be negative.\r
+ */\r
+__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn)\r
+{\r
+ if ((int32_t)(IRQn) >= 0)\r
+ {\r
+ return((uint32_t)(((NVIC->ISPR[0U] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));\r
+ }\r
+ else\r
+ {\r
+ return(0U);\r
+ }\r
+}\r
+\r
+\r
+/**\r
+ \brief Set Pending Interrupt\r
+ \details Sets the pending bit of a device specific interrupt in the NVIC pending register.\r
+ \param [in] IRQn Device specific interrupt number.\r
+ \note IRQn must not be negative.\r
+ */\r
+__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn)\r
+{\r
+ if ((int32_t)(IRQn) >= 0)\r
+ {\r
+ NVIC->ISPR[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));\r
+ }\r
+}\r
+\r
+\r
+/**\r
+ \brief Clear Pending Interrupt\r
+ \details Clears the pending bit of a device specific interrupt in the NVIC pending register.\r
+ \param [in] IRQn Device specific interrupt number.\r
+ \note IRQn must not be negative.\r
+ */\r
+__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn)\r
+{\r
+ if ((int32_t)(IRQn) >= 0)\r
+ {\r
+ NVIC->ICPR[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));\r
+ }\r
+}\r
+\r
+\r
+/**\r
+ \brief Set Interrupt Priority\r
+ \details Sets the priority of a device specific interrupt or a processor exception.\r
+ The interrupt number can be positive to specify a device specific interrupt,\r
+ or negative to specify a processor exception.\r
+ \param [in] IRQn Interrupt number.\r
+ \param [in] priority Priority to set.\r
+ \note The priority cannot be set for every processor exception.\r
+ */\r
+__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)\r
+{\r
+ if ((int32_t)(IRQn) >= 0)\r
+ {\r
+ NVIC->IP[_IP_IDX(IRQn)] = ((uint32_t)(NVIC->IP[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |\r
+ (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));\r
+ }\r
+ else\r
+ {\r
+ SCB->SHP[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |\r
+ (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));\r
+ }\r
+}\r
+\r
+\r
+/**\r
+ \brief Get Interrupt Priority\r
+ \details Reads the priority of a device specific interrupt or a processor exception.\r
+ The interrupt number can be positive to specify a device specific interrupt,\r
+ or negative to specify a processor exception.\r
+ \param [in] IRQn Interrupt number.\r
+ \return Interrupt Priority.\r
+ Value is aligned automatically to the implemented priority bits of the microcontroller.\r
+ */\r
+__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn)\r
+{\r
+\r
+ if ((int32_t)(IRQn) >= 0)\r
+ {\r
+ return((uint32_t)(((NVIC->IP[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));\r
+ }\r
+ else\r
+ {\r
+ return((uint32_t)(((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));\r
+ }\r
+}\r
+\r
+\r
+/**\r
+ \brief Set Interrupt Vector\r
+ \details Sets an interrupt vector in SRAM based interrupt vector table.\r
+ The interrupt number can be positive to specify a device specific interrupt,\r
+ or negative to specify a processor exception.\r
+ VTOR must been relocated to SRAM before.\r
+ \param [in] IRQn Interrupt number\r
+ \param [in] vector Address of interrupt handler function\r
+ */\r
+__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector)\r
+{\r
+ uint32_t *vectors = (uint32_t *)SCB->VTOR;\r
+ vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector;\r
+}\r
+\r
+\r
+/**\r
+ \brief Get Interrupt Vector\r
+ \details Reads an interrupt vector from interrupt vector table.\r
+ The interrupt number can be positive to specify a device specific interrupt,\r
+ or negative to specify a processor exception.\r
+ \param [in] IRQn Interrupt number.\r
+ \return Address of interrupt handler function\r
+ */\r
+__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn)\r
+{\r
+ uint32_t *vectors = (uint32_t *)SCB->VTOR;\r
+ return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET];\r
+}\r
+\r
+\r
+/**\r
+ \brief System Reset\r
+ \details Initiates a system reset request to reset the MCU.\r
+ */\r
+__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void)\r
+{\r
+ __DSB(); /* Ensure all outstanding memory accesses included\r
+ buffered write are completed before reset */\r
+ SCB->AIRCR = ((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |\r
+ SCB_AIRCR_SYSRESETREQ_Msk);\r
+ __DSB(); /* Ensure completion of memory access */\r
+\r
+ for(;;) /* wait until reset */\r
+ {\r
+ __NOP();\r
+ }\r
+}\r
+\r
+/*@} end of CMSIS_Core_NVICFunctions */\r
+\r
+\r
+/* ########################## FPU functions #################################### */\r
+/**\r
+ \ingroup CMSIS_Core_FunctionInterface\r
+ \defgroup CMSIS_Core_FpuFunctions FPU Functions\r
+ \brief Function that provides FPU type.\r
+ @{\r
+ */\r
+\r
+/**\r
+ \brief get FPU type\r
+ \details returns the FPU type\r
+ \returns\r
+ - \b 0: No FPU\r
+ - \b 1: Single precision FPU\r
+ - \b 2: Double + Single precision FPU\r
+ */\r
+__STATIC_INLINE uint32_t SCB_GetFPUType(void)\r
+{\r
+ return 0U; /* No FPU */\r
+}\r
+\r
+\r
+/*@} end of CMSIS_Core_FpuFunctions */\r
+\r
+\r
+\r
+/* ################################## SysTick function ############################################ */\r
+/**\r
+ \ingroup CMSIS_Core_FunctionInterface\r
+ \defgroup CMSIS_Core_SysTickFunctions SysTick Functions\r
+ \brief Functions that configure the System.\r
+ @{\r
+ */\r
+\r
+#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U)\r
+\r
+/**\r
+ \brief System Tick Configuration\r
+ \details Initializes the System Timer and its interrupt, and starts the System Tick Timer.\r
+ Counter is in free running mode to generate periodic interrupts.\r
+ \param [in] ticks Number of ticks between two interrupts.\r
+ \return 0 Function succeeded.\r
+ \return 1 Function failed.\r
+ \note When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the\r
+ function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>\r
+ must contain a vendor-specific implementation of this function.\r
+ */\r
+__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)\r
+{\r
+ if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk)\r
+ {\r
+ return (1UL); /* Reload value impossible */\r
+ }\r
+\r
+ SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */\r
+ NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */\r
+ SysTick->VAL = 0UL; /* Load the SysTick Counter Value */\r
+ SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk |\r
+ SysTick_CTRL_TICKINT_Msk |\r
+ SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */\r
+ return (0UL); /* Function successful */\r
+}\r
+\r
+#endif\r
+\r
+/*@} end of CMSIS_Core_SysTickFunctions */\r
+\r
+\r
+\r
+\r
+#ifdef __cplusplus\r
+}\r
+#endif\r
+\r
+#endif /* __CORE_SC000_H_DEPENDANT */\r
+\r
+#endif /* __CMSIS_GENERIC */\r
--- /dev/null
+/**************************************************************************//**\r
+ * @file core_sc300.h\r
+ * @brief CMSIS SC300 Core Peripheral Access Layer Header File\r
+ * @version V5.0.6\r
+ * @date 04. June 2018\r
+ ******************************************************************************/\r
+/*\r
+ * Copyright (c) 2009-2018 Arm Limited. All rights reserved.\r
+ *\r
+ * SPDX-License-Identifier: Apache-2.0\r
+ *\r
+ * Licensed under the Apache License, Version 2.0 (the License); you may\r
+ * not use this file except in compliance with the License.\r
+ * You may obtain a copy of the License at\r
+ *\r
+ * www.apache.org/licenses/LICENSE-2.0\r
+ *\r
+ * Unless required by applicable law or agreed to in writing, software\r
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT\r
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\r
+ * See the License for the specific language governing permissions and\r
+ * limitations under the License.\r
+ */\r
+\r
+#if defined ( __ICCARM__ )\r
+ #pragma system_include /* treat file as system include file for MISRA check */\r
+#elif defined (__clang__)\r
+ #pragma clang system_header /* treat file as system include file */\r
+#endif\r
+\r
+#ifndef __CORE_SC300_H_GENERIC\r
+#define __CORE_SC300_H_GENERIC\r
+\r
+#include <stdint.h>\r
+\r
+#ifdef __cplusplus\r
+ extern "C" {\r
+#endif\r
+\r
+/**\r
+ \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions\r
+ CMSIS violates the following MISRA-C:2004 rules:\r
+\r
+ \li Required Rule 8.5, object/function definition in header file.<br>\r
+ Function definitions in header files are used to allow 'inlining'.\r
+\r
+ \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>\r
+ Unions are used for effective representation of core registers.\r
+\r
+ \li Advisory Rule 19.7, Function-like macro defined.<br>\r
+ Function-like macros are used to allow more efficient code.\r
+ */\r
+\r
+\r
+/*******************************************************************************\r
+ * CMSIS definitions\r
+ ******************************************************************************/\r
+/**\r
+ \ingroup SC3000\r
+ @{\r
+ */\r
+\r
+#include "cmsis_version.h"\r
+\r
+/* CMSIS SC300 definitions */\r
+#define __SC300_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */\r
+#define __SC300_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */\r
+#define __SC300_CMSIS_VERSION ((__SC300_CMSIS_VERSION_MAIN << 16U) | \\r
+ __SC300_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */\r
+\r
+#define __CORTEX_SC (300U) /*!< Cortex secure core */\r
+\r
+/** __FPU_USED indicates whether an FPU is used or not.\r
+ This core does not support an FPU at all\r
+*/\r
+#define __FPU_USED 0U\r
+\r
+#if defined ( __CC_ARM )\r
+ #if defined __TARGET_FPU_VFP\r
+ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"\r
+ #endif\r
+\r
+#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)\r
+ #if defined __ARM_PCS_VFP\r
+ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"\r
+ #endif\r
+\r
+#elif defined ( __GNUC__ )\r
+ #if defined (__VFP_FP__) && !defined(__SOFTFP__)\r
+ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"\r
+ #endif\r
+\r
+#elif defined ( __ICCARM__ )\r
+ #if defined __ARMVFP__\r
+ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"\r
+ #endif\r
+\r
+#elif defined ( __TI_ARM__ )\r
+ #if defined __TI_VFP_SUPPORT__\r
+ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"\r
+ #endif\r
+\r
+#elif defined ( __TASKING__ )\r
+ #if defined __FPU_VFP__\r
+ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"\r
+ #endif\r
+\r
+#elif defined ( __CSMC__ )\r
+ #if ( __CSMC__ & 0x400U)\r
+ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"\r
+ #endif\r
+\r
+#endif\r
+\r
+#include "cmsis_compiler.h" /* CMSIS compiler specific defines */\r
+\r
+\r
+#ifdef __cplusplus\r
+}\r
+#endif\r
+\r
+#endif /* __CORE_SC300_H_GENERIC */\r
+\r
+#ifndef __CMSIS_GENERIC\r
+\r
+#ifndef __CORE_SC300_H_DEPENDANT\r
+#define __CORE_SC300_H_DEPENDANT\r
+\r
+#ifdef __cplusplus\r
+ extern "C" {\r
+#endif\r
+\r
+/* check device defines and use defaults */\r
+#if defined __CHECK_DEVICE_DEFINES\r
+ #ifndef __SC300_REV\r
+ #define __SC300_REV 0x0000U\r
+ #warning "__SC300_REV not defined in device header file; using default!"\r
+ #endif\r
+\r
+ #ifndef __MPU_PRESENT\r
+ #define __MPU_PRESENT 0U\r
+ #warning "__MPU_PRESENT not defined in device header file; using default!"\r
+ #endif\r
+\r
+ #ifndef __NVIC_PRIO_BITS\r
+ #define __NVIC_PRIO_BITS 3U\r
+ #warning "__NVIC_PRIO_BITS not defined in device header file; using default!"\r
+ #endif\r
+\r
+ #ifndef __Vendor_SysTickConfig\r
+ #define __Vendor_SysTickConfig 0U\r
+ #warning "__Vendor_SysTickConfig not defined in device header file; using default!"\r
+ #endif\r
+#endif\r
+\r
+/* IO definitions (access restrictions to peripheral registers) */\r
+/**\r
+ \defgroup CMSIS_glob_defs CMSIS Global Defines\r
+\r
+ <strong>IO Type Qualifiers</strong> are used\r
+ \li to specify the access to peripheral variables.\r
+ \li for automatic generation of peripheral register debug information.\r
+*/\r
+#ifdef __cplusplus\r
+ #define __I volatile /*!< Defines 'read only' permissions */\r
+#else\r
+ #define __I volatile const /*!< Defines 'read only' permissions */\r
+#endif\r
+#define __O volatile /*!< Defines 'write only' permissions */\r
+#define __IO volatile /*!< Defines 'read / write' permissions */\r
+\r
+/* following defines should be used for structure members */\r
+#define __IM volatile const /*! Defines 'read only' structure member permissions */\r
+#define __OM volatile /*! Defines 'write only' structure member permissions */\r
+#define __IOM volatile /*! Defines 'read / write' structure member permissions */\r
+\r
+/*@} end of group SC300 */\r
+\r
+\r
+\r
+/*******************************************************************************\r
+ * Register Abstraction\r
+ Core Register contain:\r
+ - Core Register\r
+ - Core NVIC Register\r
+ - Core SCB Register\r
+ - Core SysTick Register\r
+ - Core Debug Register\r
+ - Core MPU Register\r
+ ******************************************************************************/\r
+/**\r
+ \defgroup CMSIS_core_register Defines and Type Definitions\r
+ \brief Type definitions and defines for Cortex-M processor based devices.\r
+*/\r
+\r
+/**\r
+ \ingroup CMSIS_core_register\r
+ \defgroup CMSIS_CORE Status and Control Registers\r
+ \brief Core Register type definitions.\r
+ @{\r
+ */\r
+\r
+/**\r
+ \brief Union type to access the Application Program Status Register (APSR).\r
+ */\r
+typedef union\r
+{\r
+ struct\r
+ {\r
+ uint32_t _reserved0:27; /*!< bit: 0..26 Reserved */\r
+ uint32_t Q:1; /*!< bit: 27 Saturation condition flag */\r
+ uint32_t V:1; /*!< bit: 28 Overflow condition code flag */\r
+ uint32_t C:1; /*!< bit: 29 Carry condition code flag */\r
+ uint32_t Z:1; /*!< bit: 30 Zero condition code flag */\r
+ uint32_t N:1; /*!< bit: 31 Negative condition code flag */\r
+ } b; /*!< Structure used for bit access */\r
+ uint32_t w; /*!< Type used for word access */\r
+} APSR_Type;\r
+\r
+/* APSR Register Definitions */\r
+#define APSR_N_Pos 31U /*!< APSR: N Position */\r
+#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */\r
+\r
+#define APSR_Z_Pos 30U /*!< APSR: Z Position */\r
+#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */\r
+\r
+#define APSR_C_Pos 29U /*!< APSR: C Position */\r
+#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */\r
+\r
+#define APSR_V_Pos 28U /*!< APSR: V Position */\r
+#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */\r
+\r
+#define APSR_Q_Pos 27U /*!< APSR: Q Position */\r
+#define APSR_Q_Msk (1UL << APSR_Q_Pos) /*!< APSR: Q Mask */\r
+\r
+\r
+/**\r
+ \brief Union type to access the Interrupt Program Status Register (IPSR).\r
+ */\r
+typedef union\r
+{\r
+ struct\r
+ {\r
+ uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */\r
+ uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */\r
+ } b; /*!< Structure used for bit access */\r
+ uint32_t w; /*!< Type used for word access */\r
+} IPSR_Type;\r
+\r
+/* IPSR Register Definitions */\r
+#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */\r
+#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */\r
+\r
+\r
+/**\r
+ \brief Union type to access the Special-Purpose Program Status Registers (xPSR).\r
+ */\r
+typedef union\r
+{\r
+ struct\r
+ {\r
+ uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */\r
+ uint32_t _reserved0:1; /*!< bit: 9 Reserved */\r
+ uint32_t ICI_IT_1:6; /*!< bit: 10..15 ICI/IT part 1 */\r
+ uint32_t _reserved1:8; /*!< bit: 16..23 Reserved */\r
+ uint32_t T:1; /*!< bit: 24 Thumb bit */\r
+ uint32_t ICI_IT_2:2; /*!< bit: 25..26 ICI/IT part 2 */\r
+ uint32_t Q:1; /*!< bit: 27 Saturation condition flag */\r
+ uint32_t V:1; /*!< bit: 28 Overflow condition code flag */\r
+ uint32_t C:1; /*!< bit: 29 Carry condition code flag */\r
+ uint32_t Z:1; /*!< bit: 30 Zero condition code flag */\r
+ uint32_t N:1; /*!< bit: 31 Negative condition code flag */\r
+ } b; /*!< Structure used for bit access */\r
+ uint32_t w; /*!< Type used for word access */\r
+} xPSR_Type;\r
+\r
+/* xPSR Register Definitions */\r
+#define xPSR_N_Pos 31U /*!< xPSR: N Position */\r
+#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */\r
+\r
+#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */\r
+#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */\r
+\r
+#define xPSR_C_Pos 29U /*!< xPSR: C Position */\r
+#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */\r
+\r
+#define xPSR_V_Pos 28U /*!< xPSR: V Position */\r
+#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */\r
+\r
+#define xPSR_Q_Pos 27U /*!< xPSR: Q Position */\r
+#define xPSR_Q_Msk (1UL << xPSR_Q_Pos) /*!< xPSR: Q Mask */\r
+\r
+#define xPSR_ICI_IT_2_Pos 25U /*!< xPSR: ICI/IT part 2 Position */\r
+#define xPSR_ICI_IT_2_Msk (3UL << xPSR_ICI_IT_2_Pos) /*!< xPSR: ICI/IT part 2 Mask */\r
+\r
+#define xPSR_T_Pos 24U /*!< xPSR: T Position */\r
+#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */\r
+\r
+#define xPSR_ICI_IT_1_Pos 10U /*!< xPSR: ICI/IT part 1 Position */\r
+#define xPSR_ICI_IT_1_Msk (0x3FUL << xPSR_ICI_IT_1_Pos) /*!< xPSR: ICI/IT part 1 Mask */\r
+\r
+#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */\r
+#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */\r
+\r
+\r
+/**\r
+ \brief Union type to access the Control Registers (CONTROL).\r
+ */\r
+typedef union\r
+{\r
+ struct\r
+ {\r
+ uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */\r
+ uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */\r
+ uint32_t _reserved1:30; /*!< bit: 2..31 Reserved */\r
+ } b; /*!< Structure used for bit access */\r
+ uint32_t w; /*!< Type used for word access */\r
+} CONTROL_Type;\r
+\r
+/* CONTROL Register Definitions */\r
+#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */\r
+#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */\r
+\r
+#define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */\r
+#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */\r
+\r
+/*@} end of group CMSIS_CORE */\r
+\r
+\r
+/**\r
+ \ingroup CMSIS_core_register\r
+ \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC)\r
+ \brief Type definitions for the NVIC Registers\r
+ @{\r
+ */\r
+\r
+/**\r
+ \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC).\r
+ */\r
+typedef struct\r
+{\r
+ __IOM uint32_t ISER[8U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */\r
+ uint32_t RESERVED0[24U];\r
+ __IOM uint32_t ICER[8U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */\r
+ uint32_t RSERVED1[24U];\r
+ __IOM uint32_t ISPR[8U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */\r
+ uint32_t RESERVED2[24U];\r
+ __IOM uint32_t ICPR[8U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */\r
+ uint32_t RESERVED3[24U];\r
+ __IOM uint32_t IABR[8U]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */\r
+ uint32_t RESERVED4[56U];\r
+ __IOM uint8_t IP[240U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */\r
+ uint32_t RESERVED5[644U];\r
+ __OM uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */\r
+} NVIC_Type;\r
+\r
+/* Software Triggered Interrupt Register Definitions */\r
+#define NVIC_STIR_INTID_Pos 0U /*!< STIR: INTLINESNUM Position */\r
+#define NVIC_STIR_INTID_Msk (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/) /*!< STIR: INTLINESNUM Mask */\r
+\r
+/*@} end of group CMSIS_NVIC */\r
+\r
+\r
+/**\r
+ \ingroup CMSIS_core_register\r
+ \defgroup CMSIS_SCB System Control Block (SCB)\r
+ \brief Type definitions for the System Control Block Registers\r
+ @{\r
+ */\r
+\r
+/**\r
+ \brief Structure type to access the System Control Block (SCB).\r
+ */\r
+typedef struct\r
+{\r
+ __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */\r
+ __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */\r
+ __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */\r
+ __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */\r
+ __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */\r
+ __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */\r
+ __IOM uint8_t SHP[12U]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */\r
+ __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */\r
+ __IOM uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */\r
+ __IOM uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */\r
+ __IOM uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */\r
+ __IOM uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */\r
+ __IOM uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */\r
+ __IOM uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */\r
+ __IM uint32_t PFR[2U]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */\r
+ __IM uint32_t DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */\r
+ __IM uint32_t ADR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */\r
+ __IM uint32_t MMFR[4U]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */\r
+ __IM uint32_t ISAR[5U]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */\r
+ uint32_t RESERVED0[5U];\r
+ __IOM uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */\r
+ uint32_t RESERVED1[129U];\r
+ __IOM uint32_t SFCR; /*!< Offset: 0x290 (R/W) Security Features Control Register */\r
+} SCB_Type;\r
+\r
+/* SCB CPUID Register Definitions */\r
+#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */\r
+#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */\r
+\r
+#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */\r
+#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */\r
+\r
+#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */\r
+#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */\r
+\r
+#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */\r
+#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */\r
+\r
+#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */\r
+#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */\r
+\r
+/* SCB Interrupt Control State Register Definitions */\r
+#define SCB_ICSR_NMIPENDSET_Pos 31U /*!< SCB ICSR: NMIPENDSET Position */\r
+#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */\r
+\r
+#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */\r
+#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */\r
+\r
+#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */\r
+#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */\r
+\r
+#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */\r
+#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */\r
+\r
+#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */\r
+#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */\r
+\r
+#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */\r
+#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */\r
+\r
+#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */\r
+#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */\r
+\r
+#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */\r
+#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */\r
+\r
+#define SCB_ICSR_RETTOBASE_Pos 11U /*!< SCB ICSR: RETTOBASE Position */\r
+#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */\r
+\r
+#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */\r
+#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */\r
+\r
+/* SCB Vector Table Offset Register Definitions */\r
+#define SCB_VTOR_TBLBASE_Pos 29U /*!< SCB VTOR: TBLBASE Position */\r
+#define SCB_VTOR_TBLBASE_Msk (1UL << SCB_VTOR_TBLBASE_Pos) /*!< SCB VTOR: TBLBASE Mask */\r
+\r
+#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */\r
+#define SCB_VTOR_TBLOFF_Msk (0x3FFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */\r
+\r
+/* SCB Application Interrupt and Reset Control Register Definitions */\r
+#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */\r
+#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */\r
+\r
+#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */\r
+#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */\r
+\r
+#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */\r
+#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */\r
+\r
+#define SCB_AIRCR_PRIGROUP_Pos 8U /*!< SCB AIRCR: PRIGROUP Position */\r
+#define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */\r
+\r
+#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */\r
+#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */\r
+\r
+#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */\r
+#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */\r
+\r
+#define SCB_AIRCR_VECTRESET_Pos 0U /*!< SCB AIRCR: VECTRESET Position */\r
+#define SCB_AIRCR_VECTRESET_Msk (1UL /*<< SCB_AIRCR_VECTRESET_Pos*/) /*!< SCB AIRCR: VECTRESET Mask */\r
+\r
+/* SCB System Control Register Definitions */\r
+#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */\r
+#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */\r
+\r
+#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */\r
+#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */\r
+\r
+#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */\r
+#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */\r
+\r
+/* SCB Configuration Control Register Definitions */\r
+#define SCB_CCR_STKALIGN_Pos 9U /*!< SCB CCR: STKALIGN Position */\r
+#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */\r
+\r
+#define SCB_CCR_BFHFNMIGN_Pos 8U /*!< SCB CCR: BFHFNMIGN Position */\r
+#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */\r
+\r
+#define SCB_CCR_DIV_0_TRP_Pos 4U /*!< SCB CCR: DIV_0_TRP Position */\r
+#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */\r
+\r
+#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */\r
+#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */\r
+\r
+#define SCB_CCR_USERSETMPEND_Pos 1U /*!< SCB CCR: USERSETMPEND Position */\r
+#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */\r
+\r
+#define SCB_CCR_NONBASETHRDENA_Pos 0U /*!< SCB CCR: NONBASETHRDENA Position */\r
+#define SCB_CCR_NONBASETHRDENA_Msk (1UL /*<< SCB_CCR_NONBASETHRDENA_Pos*/) /*!< SCB CCR: NONBASETHRDENA Mask */\r
+\r
+/* SCB System Handler Control and State Register Definitions */\r
+#define SCB_SHCSR_USGFAULTENA_Pos 18U /*!< SCB SHCSR: USGFAULTENA Position */\r
+#define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */\r
+\r
+#define SCB_SHCSR_BUSFAULTENA_Pos 17U /*!< SCB SHCSR: BUSFAULTENA Position */\r
+#define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */\r
+\r
+#define SCB_SHCSR_MEMFAULTENA_Pos 16U /*!< SCB SHCSR: MEMFAULTENA Position */\r
+#define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */\r
+\r
+#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */\r
+#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */\r
+\r
+#define SCB_SHCSR_BUSFAULTPENDED_Pos 14U /*!< SCB SHCSR: BUSFAULTPENDED Position */\r
+#define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */\r
+\r
+#define SCB_SHCSR_MEMFAULTPENDED_Pos 13U /*!< SCB SHCSR: MEMFAULTPENDED Position */\r
+#define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */\r
+\r
+#define SCB_SHCSR_USGFAULTPENDED_Pos 12U /*!< SCB SHCSR: USGFAULTPENDED Position */\r
+#define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */\r
+\r
+#define SCB_SHCSR_SYSTICKACT_Pos 11U /*!< SCB SHCSR: SYSTICKACT Position */\r
+#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */\r
+\r
+#define SCB_SHCSR_PENDSVACT_Pos 10U /*!< SCB SHCSR: PENDSVACT Position */\r
+#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */\r
+\r
+#define SCB_SHCSR_MONITORACT_Pos 8U /*!< SCB SHCSR: MONITORACT Position */\r
+#define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */\r
+\r
+#define SCB_SHCSR_SVCALLACT_Pos 7U /*!< SCB SHCSR: SVCALLACT Position */\r
+#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */\r
+\r
+#define SCB_SHCSR_USGFAULTACT_Pos 3U /*!< SCB SHCSR: USGFAULTACT Position */\r
+#define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */\r
+\r
+#define SCB_SHCSR_BUSFAULTACT_Pos 1U /*!< SCB SHCSR: BUSFAULTACT Position */\r
+#define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */\r
+\r
+#define SCB_SHCSR_MEMFAULTACT_Pos 0U /*!< SCB SHCSR: MEMFAULTACT Position */\r
+#define SCB_SHCSR_MEMFAULTACT_Msk (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/) /*!< SCB SHCSR: MEMFAULTACT Mask */\r
+\r
+/* SCB Configurable Fault Status Register Definitions */\r
+#define SCB_CFSR_USGFAULTSR_Pos 16U /*!< SCB CFSR: Usage Fault Status Register Position */\r
+#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */\r
+\r
+#define SCB_CFSR_BUSFAULTSR_Pos 8U /*!< SCB CFSR: Bus Fault Status Register Position */\r
+#define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */\r
+\r
+#define SCB_CFSR_MEMFAULTSR_Pos 0U /*!< SCB CFSR: Memory Manage Fault Status Register Position */\r
+#define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */\r
+\r
+/* MemManage Fault Status Register (part of SCB Configurable Fault Status Register) */\r
+#define SCB_CFSR_MMARVALID_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 7U) /*!< SCB CFSR (MMFSR): MMARVALID Position */\r
+#define SCB_CFSR_MMARVALID_Msk (1UL << SCB_CFSR_MMARVALID_Pos) /*!< SCB CFSR (MMFSR): MMARVALID Mask */\r
+\r
+#define SCB_CFSR_MSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 4U) /*!< SCB CFSR (MMFSR): MSTKERR Position */\r
+#define SCB_CFSR_MSTKERR_Msk (1UL << SCB_CFSR_MSTKERR_Pos) /*!< SCB CFSR (MMFSR): MSTKERR Mask */\r
+\r
+#define SCB_CFSR_MUNSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 3U) /*!< SCB CFSR (MMFSR): MUNSTKERR Position */\r
+#define SCB_CFSR_MUNSTKERR_Msk (1UL << SCB_CFSR_MUNSTKERR_Pos) /*!< SCB CFSR (MMFSR): MUNSTKERR Mask */\r
+\r
+#define SCB_CFSR_DACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 1U) /*!< SCB CFSR (MMFSR): DACCVIOL Position */\r
+#define SCB_CFSR_DACCVIOL_Msk (1UL << SCB_CFSR_DACCVIOL_Pos) /*!< SCB CFSR (MMFSR): DACCVIOL Mask */\r
+\r
+#define SCB_CFSR_IACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 0U) /*!< SCB CFSR (MMFSR): IACCVIOL Position */\r
+#define SCB_CFSR_IACCVIOL_Msk (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/) /*!< SCB CFSR (MMFSR): IACCVIOL Mask */\r
+\r
+/* BusFault Status Register (part of SCB Configurable Fault Status Register) */\r
+#define SCB_CFSR_BFARVALID_Pos (SCB_CFSR_BUSFAULTSR_Pos + 7U) /*!< SCB CFSR (BFSR): BFARVALID Position */\r
+#define SCB_CFSR_BFARVALID_Msk (1UL << SCB_CFSR_BFARVALID_Pos) /*!< SCB CFSR (BFSR): BFARVALID Mask */\r
+\r
+#define SCB_CFSR_STKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 4U) /*!< SCB CFSR (BFSR): STKERR Position */\r
+#define SCB_CFSR_STKERR_Msk (1UL << SCB_CFSR_STKERR_Pos) /*!< SCB CFSR (BFSR): STKERR Mask */\r
+\r
+#define SCB_CFSR_UNSTKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 3U) /*!< SCB CFSR (BFSR): UNSTKERR Position */\r
+#define SCB_CFSR_UNSTKERR_Msk (1UL << SCB_CFSR_UNSTKERR_Pos) /*!< SCB CFSR (BFSR): UNSTKERR Mask */\r
+\r
+#define SCB_CFSR_IMPRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 2U) /*!< SCB CFSR (BFSR): IMPRECISERR Position */\r
+#define SCB_CFSR_IMPRECISERR_Msk (1UL << SCB_CFSR_IMPRECISERR_Pos) /*!< SCB CFSR (BFSR): IMPRECISERR Mask */\r
+\r
+#define SCB_CFSR_PRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 1U) /*!< SCB CFSR (BFSR): PRECISERR Position */\r
+#define SCB_CFSR_PRECISERR_Msk (1UL << SCB_CFSR_PRECISERR_Pos) /*!< SCB CFSR (BFSR): PRECISERR Mask */\r
+\r
+#define SCB_CFSR_IBUSERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 0U) /*!< SCB CFSR (BFSR): IBUSERR Position */\r
+#define SCB_CFSR_IBUSERR_Msk (1UL << SCB_CFSR_IBUSERR_Pos) /*!< SCB CFSR (BFSR): IBUSERR Mask */\r
+\r
+/* UsageFault Status Register (part of SCB Configurable Fault Status Register) */\r
+#define SCB_CFSR_DIVBYZERO_Pos (SCB_CFSR_USGFAULTSR_Pos + 9U) /*!< SCB CFSR (UFSR): DIVBYZERO Position */\r
+#define SCB_CFSR_DIVBYZERO_Msk (1UL << SCB_CFSR_DIVBYZERO_Pos) /*!< SCB CFSR (UFSR): DIVBYZERO Mask */\r
+\r
+#define SCB_CFSR_UNALIGNED_Pos (SCB_CFSR_USGFAULTSR_Pos + 8U) /*!< SCB CFSR (UFSR): UNALIGNED Position */\r
+#define SCB_CFSR_UNALIGNED_Msk (1UL << SCB_CFSR_UNALIGNED_Pos) /*!< SCB CFSR (UFSR): UNALIGNED Mask */\r
+\r
+#define SCB_CFSR_NOCP_Pos (SCB_CFSR_USGFAULTSR_Pos + 3U) /*!< SCB CFSR (UFSR): NOCP Position */\r
+#define SCB_CFSR_NOCP_Msk (1UL << SCB_CFSR_NOCP_Pos) /*!< SCB CFSR (UFSR): NOCP Mask */\r
+\r
+#define SCB_CFSR_INVPC_Pos (SCB_CFSR_USGFAULTSR_Pos + 2U) /*!< SCB CFSR (UFSR): INVPC Position */\r
+#define SCB_CFSR_INVPC_Msk (1UL << SCB_CFSR_INVPC_Pos) /*!< SCB CFSR (UFSR): INVPC Mask */\r
+\r
+#define SCB_CFSR_INVSTATE_Pos (SCB_CFSR_USGFAULTSR_Pos + 1U) /*!< SCB CFSR (UFSR): INVSTATE Position */\r
+#define SCB_CFSR_INVSTATE_Msk (1UL << SCB_CFSR_INVSTATE_Pos) /*!< SCB CFSR (UFSR): INVSTATE Mask */\r
+\r
+#define SCB_CFSR_UNDEFINSTR_Pos (SCB_CFSR_USGFAULTSR_Pos + 0U) /*!< SCB CFSR (UFSR): UNDEFINSTR Position */\r
+#define SCB_CFSR_UNDEFINSTR_Msk (1UL << SCB_CFSR_UNDEFINSTR_Pos) /*!< SCB CFSR (UFSR): UNDEFINSTR Mask */\r
+\r
+/* SCB Hard Fault Status Register Definitions */\r
+#define SCB_HFSR_DEBUGEVT_Pos 31U /*!< SCB HFSR: DEBUGEVT Position */\r
+#define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */\r
+\r
+#define SCB_HFSR_FORCED_Pos 30U /*!< SCB HFSR: FORCED Position */\r
+#define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */\r
+\r
+#define SCB_HFSR_VECTTBL_Pos 1U /*!< SCB HFSR: VECTTBL Position */\r
+#define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */\r
+\r
+/* SCB Debug Fault Status Register Definitions */\r
+#define SCB_DFSR_EXTERNAL_Pos 4U /*!< SCB DFSR: EXTERNAL Position */\r
+#define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */\r
+\r
+#define SCB_DFSR_VCATCH_Pos 3U /*!< SCB DFSR: VCATCH Position */\r
+#define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */\r
+\r
+#define SCB_DFSR_DWTTRAP_Pos 2U /*!< SCB DFSR: DWTTRAP Position */\r
+#define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */\r
+\r
+#define SCB_DFSR_BKPT_Pos 1U /*!< SCB DFSR: BKPT Position */\r
+#define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */\r
+\r
+#define SCB_DFSR_HALTED_Pos 0U /*!< SCB DFSR: HALTED Position */\r
+#define SCB_DFSR_HALTED_Msk (1UL /*<< SCB_DFSR_HALTED_Pos*/) /*!< SCB DFSR: HALTED Mask */\r
+\r
+/*@} end of group CMSIS_SCB */\r
+\r
+\r
+/**\r
+ \ingroup CMSIS_core_register\r
+ \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB)\r
+ \brief Type definitions for the System Control and ID Register not in the SCB\r
+ @{\r
+ */\r
+\r
+/**\r
+ \brief Structure type to access the System Control and ID Register not in the SCB.\r
+ */\r
+typedef struct\r
+{\r
+ uint32_t RESERVED0[1U];\r
+ __IM uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */\r
+ uint32_t RESERVED1[1U];\r
+} SCnSCB_Type;\r
+\r
+/* Interrupt Controller Type Register Definitions */\r
+#define SCnSCB_ICTR_INTLINESNUM_Pos 0U /*!< ICTR: INTLINESNUM Position */\r
+#define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/) /*!< ICTR: INTLINESNUM Mask */\r
+\r
+/*@} end of group CMSIS_SCnotSCB */\r
+\r
+\r
+/**\r
+ \ingroup CMSIS_core_register\r
+ \defgroup CMSIS_SysTick System Tick Timer (SysTick)\r
+ \brief Type definitions for the System Timer Registers.\r
+ @{\r
+ */\r
+\r
+/**\r
+ \brief Structure type to access the System Timer (SysTick).\r
+ */\r
+typedef struct\r
+{\r
+ __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */\r
+ __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */\r
+ __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */\r
+ __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */\r
+} SysTick_Type;\r
+\r
+/* SysTick Control / Status Register Definitions */\r
+#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */\r
+#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */\r
+\r
+#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */\r
+#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */\r
+\r
+#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */\r
+#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */\r
+\r
+#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */\r
+#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */\r
+\r
+/* SysTick Reload Register Definitions */\r
+#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */\r
+#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */\r
+\r
+/* SysTick Current Register Definitions */\r
+#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */\r
+#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */\r
+\r
+/* SysTick Calibration Register Definitions */\r
+#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */\r
+#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */\r
+\r
+#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */\r
+#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */\r
+\r
+#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */\r
+#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */\r
+\r
+/*@} end of group CMSIS_SysTick */\r
+\r
+\r
+/**\r
+ \ingroup CMSIS_core_register\r
+ \defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM)\r
+ \brief Type definitions for the Instrumentation Trace Macrocell (ITM)\r
+ @{\r
+ */\r
+\r
+/**\r
+ \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM).\r
+ */\r
+typedef struct\r
+{\r
+ __OM union\r
+ {\r
+ __OM uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */\r
+ __OM uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */\r
+ __OM uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */\r
+ } PORT [32U]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */\r
+ uint32_t RESERVED0[864U];\r
+ __IOM uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */\r
+ uint32_t RESERVED1[15U];\r
+ __IOM uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */\r
+ uint32_t RESERVED2[15U];\r
+ __IOM uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */\r
+ uint32_t RESERVED3[29U];\r
+ __OM uint32_t IWR; /*!< Offset: 0xEF8 ( /W) ITM Integration Write Register */\r
+ __IM uint32_t IRR; /*!< Offset: 0xEFC (R/ ) ITM Integration Read Register */\r
+ __IOM uint32_t IMCR; /*!< Offset: 0xF00 (R/W) ITM Integration Mode Control Register */\r
+ uint32_t RESERVED4[43U];\r
+ __OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */\r
+ __IM uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */\r
+ uint32_t RESERVED5[6U];\r
+ __IM uint32_t PID4; /*!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 */\r
+ __IM uint32_t PID5; /*!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 */\r
+ __IM uint32_t PID6; /*!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 */\r
+ __IM uint32_t PID7; /*!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 */\r
+ __IM uint32_t PID0; /*!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 */\r
+ __IM uint32_t PID1; /*!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 */\r
+ __IM uint32_t PID2; /*!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 */\r
+ __IM uint32_t PID3; /*!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 */\r
+ __IM uint32_t CID0; /*!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 */\r
+ __IM uint32_t CID1; /*!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 */\r
+ __IM uint32_t CID2; /*!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 */\r
+ __IM uint32_t CID3; /*!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 */\r
+} ITM_Type;\r
+\r
+/* ITM Trace Privilege Register Definitions */\r
+#define ITM_TPR_PRIVMASK_Pos 0U /*!< ITM TPR: PRIVMASK Position */\r
+#define ITM_TPR_PRIVMASK_Msk (0xFUL /*<< ITM_TPR_PRIVMASK_Pos*/) /*!< ITM TPR: PRIVMASK Mask */\r
+\r
+/* ITM Trace Control Register Definitions */\r
+#define ITM_TCR_BUSY_Pos 23U /*!< ITM TCR: BUSY Position */\r
+#define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */\r
+\r
+#define ITM_TCR_TraceBusID_Pos 16U /*!< ITM TCR: ATBID Position */\r
+#define ITM_TCR_TraceBusID_Msk (0x7FUL << ITM_TCR_TraceBusID_Pos) /*!< ITM TCR: ATBID Mask */\r
+\r
+#define ITM_TCR_GTSFREQ_Pos 10U /*!< ITM TCR: Global timestamp frequency Position */\r
+#define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */\r
+\r
+#define ITM_TCR_TSPrescale_Pos 8U /*!< ITM TCR: TSPrescale Position */\r
+#define ITM_TCR_TSPrescale_Msk (3UL << ITM_TCR_TSPrescale_Pos) /*!< ITM TCR: TSPrescale Mask */\r
+\r
+#define ITM_TCR_SWOENA_Pos 4U /*!< ITM TCR: SWOENA Position */\r
+#define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */\r
+\r
+#define ITM_TCR_DWTENA_Pos 3U /*!< ITM TCR: DWTENA Position */\r
+#define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */\r
+\r
+#define ITM_TCR_SYNCENA_Pos 2U /*!< ITM TCR: SYNCENA Position */\r
+#define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */\r
+\r
+#define ITM_TCR_TSENA_Pos 1U /*!< ITM TCR: TSENA Position */\r
+#define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */\r
+\r
+#define ITM_TCR_ITMENA_Pos 0U /*!< ITM TCR: ITM Enable bit Position */\r
+#define ITM_TCR_ITMENA_Msk (1UL /*<< ITM_TCR_ITMENA_Pos*/) /*!< ITM TCR: ITM Enable bit Mask */\r
+\r
+/* ITM Integration Write Register Definitions */\r
+#define ITM_IWR_ATVALIDM_Pos 0U /*!< ITM IWR: ATVALIDM Position */\r
+#define ITM_IWR_ATVALIDM_Msk (1UL /*<< ITM_IWR_ATVALIDM_Pos*/) /*!< ITM IWR: ATVALIDM Mask */\r
+\r
+/* ITM Integration Read Register Definitions */\r
+#define ITM_IRR_ATREADYM_Pos 0U /*!< ITM IRR: ATREADYM Position */\r
+#define ITM_IRR_ATREADYM_Msk (1UL /*<< ITM_IRR_ATREADYM_Pos*/) /*!< ITM IRR: ATREADYM Mask */\r
+\r
+/* ITM Integration Mode Control Register Definitions */\r
+#define ITM_IMCR_INTEGRATION_Pos 0U /*!< ITM IMCR: INTEGRATION Position */\r
+#define ITM_IMCR_INTEGRATION_Msk (1UL /*<< ITM_IMCR_INTEGRATION_Pos*/) /*!< ITM IMCR: INTEGRATION Mask */\r
+\r
+/* ITM Lock Status Register Definitions */\r
+#define ITM_LSR_ByteAcc_Pos 2U /*!< ITM LSR: ByteAcc Position */\r
+#define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */\r
+\r
+#define ITM_LSR_Access_Pos 1U /*!< ITM LSR: Access Position */\r
+#define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */\r
+\r
+#define ITM_LSR_Present_Pos 0U /*!< ITM LSR: Present Position */\r
+#define ITM_LSR_Present_Msk (1UL /*<< ITM_LSR_Present_Pos*/) /*!< ITM LSR: Present Mask */\r
+\r
+/*@}*/ /* end of group CMSIS_ITM */\r
+\r
+\r
+/**\r
+ \ingroup CMSIS_core_register\r
+ \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT)\r
+ \brief Type definitions for the Data Watchpoint and Trace (DWT)\r
+ @{\r
+ */\r
+\r
+/**\r
+ \brief Structure type to access the Data Watchpoint and Trace Register (DWT).\r
+ */\r
+typedef struct\r
+{\r
+ __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */\r
+ __IOM uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */\r
+ __IOM uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */\r
+ __IOM uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */\r
+ __IOM uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */\r
+ __IOM uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */\r
+ __IOM uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */\r
+ __IM uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */\r
+ __IOM uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */\r
+ __IOM uint32_t MASK0; /*!< Offset: 0x024 (R/W) Mask Register 0 */\r
+ __IOM uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */\r
+ uint32_t RESERVED0[1U];\r
+ __IOM uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */\r
+ __IOM uint32_t MASK1; /*!< Offset: 0x034 (R/W) Mask Register 1 */\r
+ __IOM uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */\r
+ uint32_t RESERVED1[1U];\r
+ __IOM uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */\r
+ __IOM uint32_t MASK2; /*!< Offset: 0x044 (R/W) Mask Register 2 */\r
+ __IOM uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */\r
+ uint32_t RESERVED2[1U];\r
+ __IOM uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */\r
+ __IOM uint32_t MASK3; /*!< Offset: 0x054 (R/W) Mask Register 3 */\r
+ __IOM uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */\r
+} DWT_Type;\r
+\r
+/* DWT Control Register Definitions */\r
+#define DWT_CTRL_NUMCOMP_Pos 28U /*!< DWT CTRL: NUMCOMP Position */\r
+#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */\r
+\r
+#define DWT_CTRL_NOTRCPKT_Pos 27U /*!< DWT CTRL: NOTRCPKT Position */\r
+#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */\r
+\r
+#define DWT_CTRL_NOEXTTRIG_Pos 26U /*!< DWT CTRL: NOEXTTRIG Position */\r
+#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */\r
+\r
+#define DWT_CTRL_NOCYCCNT_Pos 25U /*!< DWT CTRL: NOCYCCNT Position */\r
+#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */\r
+\r
+#define DWT_CTRL_NOPRFCNT_Pos 24U /*!< DWT CTRL: NOPRFCNT Position */\r
+#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */\r
+\r
+#define DWT_CTRL_CYCEVTENA_Pos 22U /*!< DWT CTRL: CYCEVTENA Position */\r
+#define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */\r
+\r
+#define DWT_CTRL_FOLDEVTENA_Pos 21U /*!< DWT CTRL: FOLDEVTENA Position */\r
+#define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */\r
+\r
+#define DWT_CTRL_LSUEVTENA_Pos 20U /*!< DWT CTRL: LSUEVTENA Position */\r
+#define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */\r
+\r
+#define DWT_CTRL_SLEEPEVTENA_Pos 19U /*!< DWT CTRL: SLEEPEVTENA Position */\r
+#define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */\r
+\r
+#define DWT_CTRL_EXCEVTENA_Pos 18U /*!< DWT CTRL: EXCEVTENA Position */\r
+#define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */\r
+\r
+#define DWT_CTRL_CPIEVTENA_Pos 17U /*!< DWT CTRL: CPIEVTENA Position */\r
+#define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */\r
+\r
+#define DWT_CTRL_EXCTRCENA_Pos 16U /*!< DWT CTRL: EXCTRCENA Position */\r
+#define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */\r
+\r
+#define DWT_CTRL_PCSAMPLENA_Pos 12U /*!< DWT CTRL: PCSAMPLENA Position */\r
+#define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */\r
+\r
+#define DWT_CTRL_SYNCTAP_Pos 10U /*!< DWT CTRL: SYNCTAP Position */\r
+#define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */\r
+\r
+#define DWT_CTRL_CYCTAP_Pos 9U /*!< DWT CTRL: CYCTAP Position */\r
+#define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */\r
+\r
+#define DWT_CTRL_POSTINIT_Pos 5U /*!< DWT CTRL: POSTINIT Position */\r
+#define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */\r
+\r
+#define DWT_CTRL_POSTPRESET_Pos 1U /*!< DWT CTRL: POSTPRESET Position */\r
+#define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */\r
+\r
+#define DWT_CTRL_CYCCNTENA_Pos 0U /*!< DWT CTRL: CYCCNTENA Position */\r
+#define DWT_CTRL_CYCCNTENA_Msk (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/) /*!< DWT CTRL: CYCCNTENA Mask */\r
+\r
+/* DWT CPI Count Register Definitions */\r
+#define DWT_CPICNT_CPICNT_Pos 0U /*!< DWT CPICNT: CPICNT Position */\r
+#define DWT_CPICNT_CPICNT_Msk (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/) /*!< DWT CPICNT: CPICNT Mask */\r
+\r
+/* DWT Exception Overhead Count Register Definitions */\r
+#define DWT_EXCCNT_EXCCNT_Pos 0U /*!< DWT EXCCNT: EXCCNT Position */\r
+#define DWT_EXCCNT_EXCCNT_Msk (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/) /*!< DWT EXCCNT: EXCCNT Mask */\r
+\r
+/* DWT Sleep Count Register Definitions */\r
+#define DWT_SLEEPCNT_SLEEPCNT_Pos 0U /*!< DWT SLEEPCNT: SLEEPCNT Position */\r
+#define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/) /*!< DWT SLEEPCNT: SLEEPCNT Mask */\r
+\r
+/* DWT LSU Count Register Definitions */\r
+#define DWT_LSUCNT_LSUCNT_Pos 0U /*!< DWT LSUCNT: LSUCNT Position */\r
+#define DWT_LSUCNT_LSUCNT_Msk (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/) /*!< DWT LSUCNT: LSUCNT Mask */\r
+\r
+/* DWT Folded-instruction Count Register Definitions */\r
+#define DWT_FOLDCNT_FOLDCNT_Pos 0U /*!< DWT FOLDCNT: FOLDCNT Position */\r
+#define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/) /*!< DWT FOLDCNT: FOLDCNT Mask */\r
+\r
+/* DWT Comparator Mask Register Definitions */\r
+#define DWT_MASK_MASK_Pos 0U /*!< DWT MASK: MASK Position */\r
+#define DWT_MASK_MASK_Msk (0x1FUL /*<< DWT_MASK_MASK_Pos*/) /*!< DWT MASK: MASK Mask */\r
+\r
+/* DWT Comparator Function Register Definitions */\r
+#define DWT_FUNCTION_MATCHED_Pos 24U /*!< DWT FUNCTION: MATCHED Position */\r
+#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */\r
+\r
+#define DWT_FUNCTION_DATAVADDR1_Pos 16U /*!< DWT FUNCTION: DATAVADDR1 Position */\r
+#define DWT_FUNCTION_DATAVADDR1_Msk (0xFUL << DWT_FUNCTION_DATAVADDR1_Pos) /*!< DWT FUNCTION: DATAVADDR1 Mask */\r
+\r
+#define DWT_FUNCTION_DATAVADDR0_Pos 12U /*!< DWT FUNCTION: DATAVADDR0 Position */\r
+#define DWT_FUNCTION_DATAVADDR0_Msk (0xFUL << DWT_FUNCTION_DATAVADDR0_Pos) /*!< DWT FUNCTION: DATAVADDR0 Mask */\r
+\r
+#define DWT_FUNCTION_DATAVSIZE_Pos 10U /*!< DWT FUNCTION: DATAVSIZE Position */\r
+#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */\r
+\r
+#define DWT_FUNCTION_LNK1ENA_Pos 9U /*!< DWT FUNCTION: LNK1ENA Position */\r
+#define DWT_FUNCTION_LNK1ENA_Msk (0x1UL << DWT_FUNCTION_LNK1ENA_Pos) /*!< DWT FUNCTION: LNK1ENA Mask */\r
+\r
+#define DWT_FUNCTION_DATAVMATCH_Pos 8U /*!< DWT FUNCTION: DATAVMATCH Position */\r
+#define DWT_FUNCTION_DATAVMATCH_Msk (0x1UL << DWT_FUNCTION_DATAVMATCH_Pos) /*!< DWT FUNCTION: DATAVMATCH Mask */\r
+\r
+#define DWT_FUNCTION_CYCMATCH_Pos 7U /*!< DWT FUNCTION: CYCMATCH Position */\r
+#define DWT_FUNCTION_CYCMATCH_Msk (0x1UL << DWT_FUNCTION_CYCMATCH_Pos) /*!< DWT FUNCTION: CYCMATCH Mask */\r
+\r
+#define DWT_FUNCTION_EMITRANGE_Pos 5U /*!< DWT FUNCTION: EMITRANGE Position */\r
+#define DWT_FUNCTION_EMITRANGE_Msk (0x1UL << DWT_FUNCTION_EMITRANGE_Pos) /*!< DWT FUNCTION: EMITRANGE Mask */\r
+\r
+#define DWT_FUNCTION_FUNCTION_Pos 0U /*!< DWT FUNCTION: FUNCTION Position */\r
+#define DWT_FUNCTION_FUNCTION_Msk (0xFUL /*<< DWT_FUNCTION_FUNCTION_Pos*/) /*!< DWT FUNCTION: FUNCTION Mask */\r
+\r
+/*@}*/ /* end of group CMSIS_DWT */\r
+\r
+\r
+/**\r
+ \ingroup CMSIS_core_register\r
+ \defgroup CMSIS_TPI Trace Port Interface (TPI)\r
+ \brief Type definitions for the Trace Port Interface (TPI)\r
+ @{\r
+ */\r
+\r
+/**\r
+ \brief Structure type to access the Trace Port Interface Register (TPI).\r
+ */\r
+typedef struct\r
+{\r
+ __IM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */\r
+ __IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */\r
+ uint32_t RESERVED0[2U];\r
+ __IOM uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */\r
+ uint32_t RESERVED1[55U];\r
+ __IOM uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */\r
+ uint32_t RESERVED2[131U];\r
+ __IM uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */\r
+ __IOM uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */\r
+ __IM uint32_t FSCR; /*!< Offset: 0x308 (R/ ) Formatter Synchronization Counter Register */\r
+ uint32_t RESERVED3[759U];\r
+ __IM uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER Register */\r
+ __IM uint32_t FIFO0; /*!< Offset: 0xEEC (R/ ) Integration ETM Data */\r
+ __IM uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/ ) ITATBCTR2 */\r
+ uint32_t RESERVED4[1U];\r
+ __IM uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) ITATBCTR0 */\r
+ __IM uint32_t FIFO1; /*!< Offset: 0xEFC (R/ ) Integration ITM Data */\r
+ __IOM uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */\r
+ uint32_t RESERVED5[39U];\r
+ __IOM uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */\r
+ __IOM uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */\r
+ uint32_t RESERVED7[8U];\r
+ __IM uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) TPIU_DEVID */\r
+ __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) TPIU_DEVTYPE */\r
+} TPI_Type;\r
+\r
+/* TPI Asynchronous Clock Prescaler Register Definitions */\r
+#define TPI_ACPR_PRESCALER_Pos 0U /*!< TPI ACPR: PRESCALER Position */\r
+#define TPI_ACPR_PRESCALER_Msk (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/) /*!< TPI ACPR: PRESCALER Mask */\r
+\r
+/* TPI Selected Pin Protocol Register Definitions */\r
+#define TPI_SPPR_TXMODE_Pos 0U /*!< TPI SPPR: TXMODE Position */\r
+#define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) /*!< TPI SPPR: TXMODE Mask */\r
+\r
+/* TPI Formatter and Flush Status Register Definitions */\r
+#define TPI_FFSR_FtNonStop_Pos 3U /*!< TPI FFSR: FtNonStop Position */\r
+#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */\r
+\r
+#define TPI_FFSR_TCPresent_Pos 2U /*!< TPI FFSR: TCPresent Position */\r
+#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */\r
+\r
+#define TPI_FFSR_FtStopped_Pos 1U /*!< TPI FFSR: FtStopped Position */\r
+#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */\r
+\r
+#define TPI_FFSR_FlInProg_Pos 0U /*!< TPI FFSR: FlInProg Position */\r
+#define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) /*!< TPI FFSR: FlInProg Mask */\r
+\r
+/* TPI Formatter and Flush Control Register Definitions */\r
+#define TPI_FFCR_TrigIn_Pos 8U /*!< TPI FFCR: TrigIn Position */\r
+#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */\r
+\r
+#define TPI_FFCR_EnFCont_Pos 1U /*!< TPI FFCR: EnFCont Position */\r
+#define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */\r
+\r
+/* TPI TRIGGER Register Definitions */\r
+#define TPI_TRIGGER_TRIGGER_Pos 0U /*!< TPI TRIGGER: TRIGGER Position */\r
+#define TPI_TRIGGER_TRIGGER_Msk (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/) /*!< TPI TRIGGER: TRIGGER Mask */\r
+\r
+/* TPI Integration ETM Data Register Definitions (FIFO0) */\r
+#define TPI_FIFO0_ITM_ATVALID_Pos 29U /*!< TPI FIFO0: ITM_ATVALID Position */\r
+#define TPI_FIFO0_ITM_ATVALID_Msk (0x3UL << TPI_FIFO0_ITM_ATVALID_Pos) /*!< TPI FIFO0: ITM_ATVALID Mask */\r
+\r
+#define TPI_FIFO0_ITM_bytecount_Pos 27U /*!< TPI FIFO0: ITM_bytecount Position */\r
+#define TPI_FIFO0_ITM_bytecount_Msk (0x3UL << TPI_FIFO0_ITM_bytecount_Pos) /*!< TPI FIFO0: ITM_bytecount Mask */\r
+\r
+#define TPI_FIFO0_ETM_ATVALID_Pos 26U /*!< TPI FIFO0: ETM_ATVALID Position */\r
+#define TPI_FIFO0_ETM_ATVALID_Msk (0x3UL << TPI_FIFO0_ETM_ATVALID_Pos) /*!< TPI FIFO0: ETM_ATVALID Mask */\r
+\r
+#define TPI_FIFO0_ETM_bytecount_Pos 24U /*!< TPI FIFO0: ETM_bytecount Position */\r
+#define TPI_FIFO0_ETM_bytecount_Msk (0x3UL << TPI_FIFO0_ETM_bytecount_Pos) /*!< TPI FIFO0: ETM_bytecount Mask */\r
+\r
+#define TPI_FIFO0_ETM2_Pos 16U /*!< TPI FIFO0: ETM2 Position */\r
+#define TPI_FIFO0_ETM2_Msk (0xFFUL << TPI_FIFO0_ETM2_Pos) /*!< TPI FIFO0: ETM2 Mask */\r
+\r
+#define TPI_FIFO0_ETM1_Pos 8U /*!< TPI FIFO0: ETM1 Position */\r
+#define TPI_FIFO0_ETM1_Msk (0xFFUL << TPI_FIFO0_ETM1_Pos) /*!< TPI FIFO0: ETM1 Mask */\r
+\r
+#define TPI_FIFO0_ETM0_Pos 0U /*!< TPI FIFO0: ETM0 Position */\r
+#define TPI_FIFO0_ETM0_Msk (0xFFUL /*<< TPI_FIFO0_ETM0_Pos*/) /*!< TPI FIFO0: ETM0 Mask */\r
+\r
+/* TPI ITATBCTR2 Register Definitions */\r
+#define TPI_ITATBCTR2_ATREADY2_Pos 0U /*!< TPI ITATBCTR2: ATREADY2 Position */\r
+#define TPI_ITATBCTR2_ATREADY2_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY2_Pos*/) /*!< TPI ITATBCTR2: ATREADY2 Mask */\r
+\r
+#define TPI_ITATBCTR2_ATREADY1_Pos 0U /*!< TPI ITATBCTR2: ATREADY1 Position */\r
+#define TPI_ITATBCTR2_ATREADY1_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY1_Pos*/) /*!< TPI ITATBCTR2: ATREADY1 Mask */\r
+\r
+/* TPI Integration ITM Data Register Definitions (FIFO1) */\r
+#define TPI_FIFO1_ITM_ATVALID_Pos 29U /*!< TPI FIFO1: ITM_ATVALID Position */\r
+#define TPI_FIFO1_ITM_ATVALID_Msk (0x3UL << TPI_FIFO1_ITM_ATVALID_Pos) /*!< TPI FIFO1: ITM_ATVALID Mask */\r
+\r
+#define TPI_FIFO1_ITM_bytecount_Pos 27U /*!< TPI FIFO1: ITM_bytecount Position */\r
+#define TPI_FIFO1_ITM_bytecount_Msk (0x3UL << TPI_FIFO1_ITM_bytecount_Pos) /*!< TPI FIFO1: ITM_bytecount Mask */\r
+\r
+#define TPI_FIFO1_ETM_ATVALID_Pos 26U /*!< TPI FIFO1: ETM_ATVALID Position */\r
+#define TPI_FIFO1_ETM_ATVALID_Msk (0x3UL << TPI_FIFO1_ETM_ATVALID_Pos) /*!< TPI FIFO1: ETM_ATVALID Mask */\r
+\r
+#define TPI_FIFO1_ETM_bytecount_Pos 24U /*!< TPI FIFO1: ETM_bytecount Position */\r
+#define TPI_FIFO1_ETM_bytecount_Msk (0x3UL << TPI_FIFO1_ETM_bytecount_Pos) /*!< TPI FIFO1: ETM_bytecount Mask */\r
+\r
+#define TPI_FIFO1_ITM2_Pos 16U /*!< TPI FIFO1: ITM2 Position */\r
+#define TPI_FIFO1_ITM2_Msk (0xFFUL << TPI_FIFO1_ITM2_Pos) /*!< TPI FIFO1: ITM2 Mask */\r
+\r
+#define TPI_FIFO1_ITM1_Pos 8U /*!< TPI FIFO1: ITM1 Position */\r
+#define TPI_FIFO1_ITM1_Msk (0xFFUL << TPI_FIFO1_ITM1_Pos) /*!< TPI FIFO1: ITM1 Mask */\r
+\r
+#define TPI_FIFO1_ITM0_Pos 0U /*!< TPI FIFO1: ITM0 Position */\r
+#define TPI_FIFO1_ITM0_Msk (0xFFUL /*<< TPI_FIFO1_ITM0_Pos*/) /*!< TPI FIFO1: ITM0 Mask */\r
+\r
+/* TPI ITATBCTR0 Register Definitions */\r
+#define TPI_ITATBCTR0_ATREADY2_Pos 0U /*!< TPI ITATBCTR0: ATREADY2 Position */\r
+#define TPI_ITATBCTR0_ATREADY2_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY2_Pos*/) /*!< TPI ITATBCTR0: ATREADY2 Mask */\r
+\r
+#define TPI_ITATBCTR0_ATREADY1_Pos 0U /*!< TPI ITATBCTR0: ATREADY1 Position */\r
+#define TPI_ITATBCTR0_ATREADY1_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY1_Pos*/) /*!< TPI ITATBCTR0: ATREADY1 Mask */\r
+\r
+/* TPI Integration Mode Control Register Definitions */\r
+#define TPI_ITCTRL_Mode_Pos 0U /*!< TPI ITCTRL: Mode Position */\r
+#define TPI_ITCTRL_Mode_Msk (0x3UL /*<< TPI_ITCTRL_Mode_Pos*/) /*!< TPI ITCTRL: Mode Mask */\r
+\r
+/* TPI DEVID Register Definitions */\r
+#define TPI_DEVID_NRZVALID_Pos 11U /*!< TPI DEVID: NRZVALID Position */\r
+#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */\r
+\r
+#define TPI_DEVID_MANCVALID_Pos 10U /*!< TPI DEVID: MANCVALID Position */\r
+#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */\r
+\r
+#define TPI_DEVID_PTINVALID_Pos 9U /*!< TPI DEVID: PTINVALID Position */\r
+#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */\r
+\r
+#define TPI_DEVID_MinBufSz_Pos 6U /*!< TPI DEVID: MinBufSz Position */\r
+#define TPI_DEVID_MinBufSz_Msk (0x7UL << TPI_DEVID_MinBufSz_Pos) /*!< TPI DEVID: MinBufSz Mask */\r
+\r
+#define TPI_DEVID_AsynClkIn_Pos 5U /*!< TPI DEVID: AsynClkIn Position */\r
+#define TPI_DEVID_AsynClkIn_Msk (0x1UL << TPI_DEVID_AsynClkIn_Pos) /*!< TPI DEVID: AsynClkIn Mask */\r
+\r
+#define TPI_DEVID_NrTraceInput_Pos 0U /*!< TPI DEVID: NrTraceInput Position */\r
+#define TPI_DEVID_NrTraceInput_Msk (0x1FUL /*<< TPI_DEVID_NrTraceInput_Pos*/) /*!< TPI DEVID: NrTraceInput Mask */\r
+\r
+/* TPI DEVTYPE Register Definitions */\r
+#define TPI_DEVTYPE_SubType_Pos 4U /*!< TPI DEVTYPE: SubType Position */\r
+#define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */\r
+\r
+#define TPI_DEVTYPE_MajorType_Pos 0U /*!< TPI DEVTYPE: MajorType Position */\r
+#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */\r
+\r
+/*@}*/ /* end of group CMSIS_TPI */\r
+\r
+\r
+#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)\r
+/**\r
+ \ingroup CMSIS_core_register\r
+ \defgroup CMSIS_MPU Memory Protection Unit (MPU)\r
+ \brief Type definitions for the Memory Protection Unit (MPU)\r
+ @{\r
+ */\r
+\r
+/**\r
+ \brief Structure type to access the Memory Protection Unit (MPU).\r
+ */\r
+typedef struct\r
+{\r
+ __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */\r
+ __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */\r
+ __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */\r
+ __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */\r
+ __IOM uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */\r
+ __IOM uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Alias 1 Region Base Address Register */\r
+ __IOM uint32_t RASR_A1; /*!< Offset: 0x018 (R/W) MPU Alias 1 Region Attribute and Size Register */\r
+ __IOM uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Alias 2 Region Base Address Register */\r
+ __IOM uint32_t RASR_A2; /*!< Offset: 0x020 (R/W) MPU Alias 2 Region Attribute and Size Register */\r
+ __IOM uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Alias 3 Region Base Address Register */\r
+ __IOM uint32_t RASR_A3; /*!< Offset: 0x028 (R/W) MPU Alias 3 Region Attribute and Size Register */\r
+} MPU_Type;\r
+\r
+/* MPU Type Register Definitions */\r
+#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */\r
+#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */\r
+\r
+#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */\r
+#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */\r
+\r
+#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */\r
+#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */\r
+\r
+/* MPU Control Register Definitions */\r
+#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */\r
+#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */\r
+\r
+#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */\r
+#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */\r
+\r
+#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */\r
+#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */\r
+\r
+/* MPU Region Number Register Definitions */\r
+#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */\r
+#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */\r
+\r
+/* MPU Region Base Address Register Definitions */\r
+#define MPU_RBAR_ADDR_Pos 5U /*!< MPU RBAR: ADDR Position */\r
+#define MPU_RBAR_ADDR_Msk (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */\r
+\r
+#define MPU_RBAR_VALID_Pos 4U /*!< MPU RBAR: VALID Position */\r
+#define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */\r
+\r
+#define MPU_RBAR_REGION_Pos 0U /*!< MPU RBAR: REGION Position */\r
+#define MPU_RBAR_REGION_Msk (0xFUL /*<< MPU_RBAR_REGION_Pos*/) /*!< MPU RBAR: REGION Mask */\r
+\r
+/* MPU Region Attribute and Size Register Definitions */\r
+#define MPU_RASR_ATTRS_Pos 16U /*!< MPU RASR: MPU Region Attribute field Position */\r
+#define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */\r
+\r
+#define MPU_RASR_XN_Pos 28U /*!< MPU RASR: ATTRS.XN Position */\r
+#define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */\r
+\r
+#define MPU_RASR_AP_Pos 24U /*!< MPU RASR: ATTRS.AP Position */\r
+#define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */\r
+\r
+#define MPU_RASR_TEX_Pos 19U /*!< MPU RASR: ATTRS.TEX Position */\r
+#define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */\r
+\r
+#define MPU_RASR_S_Pos 18U /*!< MPU RASR: ATTRS.S Position */\r
+#define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */\r
+\r
+#define MPU_RASR_C_Pos 17U /*!< MPU RASR: ATTRS.C Position */\r
+#define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */\r
+\r
+#define MPU_RASR_B_Pos 16U /*!< MPU RASR: ATTRS.B Position */\r
+#define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */\r
+\r
+#define MPU_RASR_SRD_Pos 8U /*!< MPU RASR: Sub-Region Disable Position */\r
+#define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */\r
+\r
+#define MPU_RASR_SIZE_Pos 1U /*!< MPU RASR: Region Size Field Position */\r
+#define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */\r
+\r
+#define MPU_RASR_ENABLE_Pos 0U /*!< MPU RASR: Region enable bit Position */\r
+#define MPU_RASR_ENABLE_Msk (1UL /*<< MPU_RASR_ENABLE_Pos*/) /*!< MPU RASR: Region enable bit Disable Mask */\r
+\r
+/*@} end of group CMSIS_MPU */\r
+#endif\r
+\r
+\r
+/**\r
+ \ingroup CMSIS_core_register\r
+ \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug)\r
+ \brief Type definitions for the Core Debug Registers\r
+ @{\r
+ */\r
+\r
+/**\r
+ \brief Structure type to access the Core Debug Register (CoreDebug).\r
+ */\r
+typedef struct\r
+{\r
+ __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */\r
+ __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */\r
+ __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */\r
+ __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */\r
+} CoreDebug_Type;\r
+\r
+/* Debug Halting Control and Status Register Definitions */\r
+#define CoreDebug_DHCSR_DBGKEY_Pos 16U /*!< CoreDebug DHCSR: DBGKEY Position */\r
+#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */\r
+\r
+#define CoreDebug_DHCSR_S_RESET_ST_Pos 25U /*!< CoreDebug DHCSR: S_RESET_ST Position */\r
+#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */\r
+\r
+#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U /*!< CoreDebug DHCSR: S_RETIRE_ST Position */\r
+#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */\r
+\r
+#define CoreDebug_DHCSR_S_LOCKUP_Pos 19U /*!< CoreDebug DHCSR: S_LOCKUP Position */\r
+#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */\r
+\r
+#define CoreDebug_DHCSR_S_SLEEP_Pos 18U /*!< CoreDebug DHCSR: S_SLEEP Position */\r
+#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */\r
+\r
+#define CoreDebug_DHCSR_S_HALT_Pos 17U /*!< CoreDebug DHCSR: S_HALT Position */\r
+#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */\r
+\r
+#define CoreDebug_DHCSR_S_REGRDY_Pos 16U /*!< CoreDebug DHCSR: S_REGRDY Position */\r
+#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */\r
+\r
+#define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5U /*!< CoreDebug DHCSR: C_SNAPSTALL Position */\r
+#define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */\r
+\r
+#define CoreDebug_DHCSR_C_MASKINTS_Pos 3U /*!< CoreDebug DHCSR: C_MASKINTS Position */\r
+#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */\r
+\r
+#define CoreDebug_DHCSR_C_STEP_Pos 2U /*!< CoreDebug DHCSR: C_STEP Position */\r
+#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */\r
+\r
+#define CoreDebug_DHCSR_C_HALT_Pos 1U /*!< CoreDebug DHCSR: C_HALT Position */\r
+#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */\r
+\r
+#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U /*!< CoreDebug DHCSR: C_DEBUGEN Position */\r
+#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */\r
+\r
+/* Debug Core Register Selector Register Definitions */\r
+#define CoreDebug_DCRSR_REGWnR_Pos 16U /*!< CoreDebug DCRSR: REGWnR Position */\r
+#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */\r
+\r
+#define CoreDebug_DCRSR_REGSEL_Pos 0U /*!< CoreDebug DCRSR: REGSEL Position */\r
+#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/) /*!< CoreDebug DCRSR: REGSEL Mask */\r
+\r
+/* Debug Exception and Monitor Control Register Definitions */\r
+#define CoreDebug_DEMCR_TRCENA_Pos 24U /*!< CoreDebug DEMCR: TRCENA Position */\r
+#define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< CoreDebug DEMCR: TRCENA Mask */\r
+\r
+#define CoreDebug_DEMCR_MON_REQ_Pos 19U /*!< CoreDebug DEMCR: MON_REQ Position */\r
+#define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< CoreDebug DEMCR: MON_REQ Mask */\r
+\r
+#define CoreDebug_DEMCR_MON_STEP_Pos 18U /*!< CoreDebug DEMCR: MON_STEP Position */\r
+#define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< CoreDebug DEMCR: MON_STEP Mask */\r
+\r
+#define CoreDebug_DEMCR_MON_PEND_Pos 17U /*!< CoreDebug DEMCR: MON_PEND Position */\r
+#define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< CoreDebug DEMCR: MON_PEND Mask */\r
+\r
+#define CoreDebug_DEMCR_MON_EN_Pos 16U /*!< CoreDebug DEMCR: MON_EN Position */\r
+#define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< CoreDebug DEMCR: MON_EN Mask */\r
+\r
+#define CoreDebug_DEMCR_VC_HARDERR_Pos 10U /*!< CoreDebug DEMCR: VC_HARDERR Position */\r
+#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */\r
+\r
+#define CoreDebug_DEMCR_VC_INTERR_Pos 9U /*!< CoreDebug DEMCR: VC_INTERR Position */\r
+#define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< CoreDebug DEMCR: VC_INTERR Mask */\r
+\r
+#define CoreDebug_DEMCR_VC_BUSERR_Pos 8U /*!< CoreDebug DEMCR: VC_BUSERR Position */\r
+#define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< CoreDebug DEMCR: VC_BUSERR Mask */\r
+\r
+#define CoreDebug_DEMCR_VC_STATERR_Pos 7U /*!< CoreDebug DEMCR: VC_STATERR Position */\r
+#define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< CoreDebug DEMCR: VC_STATERR Mask */\r
+\r
+#define CoreDebug_DEMCR_VC_CHKERR_Pos 6U /*!< CoreDebug DEMCR: VC_CHKERR Position */\r
+#define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< CoreDebug DEMCR: VC_CHKERR Mask */\r
+\r
+#define CoreDebug_DEMCR_VC_NOCPERR_Pos 5U /*!< CoreDebug DEMCR: VC_NOCPERR Position */\r
+#define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< CoreDebug DEMCR: VC_NOCPERR Mask */\r
+\r
+#define CoreDebug_DEMCR_VC_MMERR_Pos 4U /*!< CoreDebug DEMCR: VC_MMERR Position */\r
+#define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< CoreDebug DEMCR: VC_MMERR Mask */\r
+\r
+#define CoreDebug_DEMCR_VC_CORERESET_Pos 0U /*!< CoreDebug DEMCR: VC_CORERESET Position */\r
+#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/) /*!< CoreDebug DEMCR: VC_CORERESET Mask */\r
+\r
+/*@} end of group CMSIS_CoreDebug */\r
+\r
+\r
+/**\r
+ \ingroup CMSIS_core_register\r
+ \defgroup CMSIS_core_bitfield Core register bit field macros\r
+ \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk).\r
+ @{\r
+ */\r
+\r
+/**\r
+ \brief Mask and shift a bit field value for use in a register bit range.\r
+ \param[in] field Name of the register bit field.\r
+ \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type.\r
+ \return Masked and shifted value.\r
+*/\r
+#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk)\r
+\r
+/**\r
+ \brief Mask and shift a register value to extract a bit filed value.\r
+ \param[in] field Name of the register bit field.\r
+ \param[in] value Value of register. This parameter is interpreted as an uint32_t type.\r
+ \return Masked and shifted bit field value.\r
+*/\r
+#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos)\r
+\r
+/*@} end of group CMSIS_core_bitfield */\r
+\r
+\r
+/**\r
+ \ingroup CMSIS_core_register\r
+ \defgroup CMSIS_core_base Core Definitions\r
+ \brief Definitions for base addresses, unions, and structures.\r
+ @{\r
+ */\r
+\r
+/* Memory mapping of Core Hardware */\r
+#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */\r
+#define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */\r
+#define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */\r
+#define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */\r
+#define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */\r
+#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */\r
+#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */\r
+#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */\r
+\r
+#define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */\r
+#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */\r
+#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */\r
+#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */\r
+#define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */\r
+#define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */\r
+#define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */\r
+#define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE) /*!< Core Debug configuration struct */\r
+\r
+#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)\r
+ #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */\r
+ #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */\r
+#endif\r
+\r
+/*@} */\r
+\r
+\r
+\r
+/*******************************************************************************\r
+ * Hardware Abstraction Layer\r
+ Core Function Interface contains:\r
+ - Core NVIC Functions\r
+ - Core SysTick Functions\r
+ - Core Debug Functions\r
+ - Core Register Access Functions\r
+ ******************************************************************************/\r
+/**\r
+ \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference\r
+*/\r
+\r
+\r
+\r
+/* ########################## NVIC functions #################################### */\r
+/**\r
+ \ingroup CMSIS_Core_FunctionInterface\r
+ \defgroup CMSIS_Core_NVICFunctions NVIC Functions\r
+ \brief Functions that manage interrupts and exceptions via the NVIC.\r
+ @{\r
+ */\r
+\r
+#ifdef CMSIS_NVIC_VIRTUAL\r
+ #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE\r
+ #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h"\r
+ #endif\r
+ #include CMSIS_NVIC_VIRTUAL_HEADER_FILE\r
+#else\r
+ #define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping\r
+ #define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping\r
+ #define NVIC_EnableIRQ __NVIC_EnableIRQ\r
+ #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ\r
+ #define NVIC_DisableIRQ __NVIC_DisableIRQ\r
+ #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ\r
+ #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ\r
+ #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ\r
+ #define NVIC_GetActive __NVIC_GetActive\r
+ #define NVIC_SetPriority __NVIC_SetPriority\r
+ #define NVIC_GetPriority __NVIC_GetPriority\r
+ #define NVIC_SystemReset __NVIC_SystemReset\r
+#endif /* CMSIS_NVIC_VIRTUAL */\r
+\r
+#ifdef CMSIS_VECTAB_VIRTUAL\r
+ #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE\r
+ #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h"\r
+ #endif\r
+ #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE\r
+#else\r
+ #define NVIC_SetVector __NVIC_SetVector\r
+ #define NVIC_GetVector __NVIC_GetVector\r
+#endif /* (CMSIS_VECTAB_VIRTUAL) */\r
+\r
+#define NVIC_USER_IRQ_OFFSET 16\r
+\r
+\r
+/* The following EXC_RETURN values are saved the LR on exception entry */\r
+#define EXC_RETURN_HANDLER (0xFFFFFFF1UL) /* return to Handler mode, uses MSP after return */\r
+#define EXC_RETURN_THREAD_MSP (0xFFFFFFF9UL) /* return to Thread mode, uses MSP after return */\r
+#define EXC_RETURN_THREAD_PSP (0xFFFFFFFDUL) /* return to Thread mode, uses PSP after return */\r
+\r
+\r
+\r
+/**\r
+ \brief Set Priority Grouping\r
+ \details Sets the priority grouping field using the required unlock sequence.\r
+ The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field.\r
+ Only values from 0..7 are used.\r
+ In case of a conflict between priority grouping and available\r
+ priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.\r
+ \param [in] PriorityGroup Priority grouping field.\r
+ */\r
+__STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup)\r
+{\r
+ uint32_t reg_value;\r
+ uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */\r
+\r
+ reg_value = SCB->AIRCR; /* read old register configuration */\r
+ reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */\r
+ reg_value = (reg_value |\r
+ ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |\r
+ (PriorityGroupTmp << 8U) ); /* Insert write key and priorty group */\r
+ SCB->AIRCR = reg_value;\r
+}\r
+\r
+\r
+/**\r
+ \brief Get Priority Grouping\r
+ \details Reads the priority grouping field from the NVIC Interrupt Controller.\r
+ \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field).\r
+ */\r
+__STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void)\r
+{\r
+ return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos));\r
+}\r
+\r
+\r
+/**\r
+ \brief Enable Interrupt\r
+ \details Enables a device specific interrupt in the NVIC interrupt controller.\r
+ \param [in] IRQn Device specific interrupt number.\r
+ \note IRQn must not be negative.\r
+ */\r
+__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn)\r
+{\r
+ if ((int32_t)(IRQn) >= 0)\r
+ {\r
+ NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));\r
+ }\r
+}\r
+\r
+\r
+/**\r
+ \brief Get Interrupt Enable status\r
+ \details Returns a device specific interrupt enable status from the NVIC interrupt controller.\r
+ \param [in] IRQn Device specific interrupt number.\r
+ \return 0 Interrupt is not enabled.\r
+ \return 1 Interrupt is enabled.\r
+ \note IRQn must not be negative.\r
+ */\r
+__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn)\r
+{\r
+ if ((int32_t)(IRQn) >= 0)\r
+ {\r
+ return((uint32_t)(((NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));\r
+ }\r
+ else\r
+ {\r
+ return(0U);\r
+ }\r
+}\r
+\r
+\r
+/**\r
+ \brief Disable Interrupt\r
+ \details Disables a device specific interrupt in the NVIC interrupt controller.\r
+ \param [in] IRQn Device specific interrupt number.\r
+ \note IRQn must not be negative.\r
+ */\r
+__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn)\r
+{\r
+ if ((int32_t)(IRQn) >= 0)\r
+ {\r
+ NVIC->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));\r
+ __DSB();\r
+ __ISB();\r
+ }\r
+}\r
+\r
+\r
+/**\r
+ \brief Get Pending Interrupt\r
+ \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt.\r
+ \param [in] IRQn Device specific interrupt number.\r
+ \return 0 Interrupt status is not pending.\r
+ \return 1 Interrupt status is pending.\r
+ \note IRQn must not be negative.\r
+ */\r
+__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn)\r
+{\r
+ if ((int32_t)(IRQn) >= 0)\r
+ {\r
+ return((uint32_t)(((NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));\r
+ }\r
+ else\r
+ {\r
+ return(0U);\r
+ }\r
+}\r
+\r
+\r
+/**\r
+ \brief Set Pending Interrupt\r
+ \details Sets the pending bit of a device specific interrupt in the NVIC pending register.\r
+ \param [in] IRQn Device specific interrupt number.\r
+ \note IRQn must not be negative.\r
+ */\r
+__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn)\r
+{\r
+ if ((int32_t)(IRQn) >= 0)\r
+ {\r
+ NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));\r
+ }\r
+}\r
+\r
+\r
+/**\r
+ \brief Clear Pending Interrupt\r
+ \details Clears the pending bit of a device specific interrupt in the NVIC pending register.\r
+ \param [in] IRQn Device specific interrupt number.\r
+ \note IRQn must not be negative.\r
+ */\r
+__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn)\r
+{\r
+ if ((int32_t)(IRQn) >= 0)\r
+ {\r
+ NVIC->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));\r
+ }\r
+}\r
+\r
+\r
+/**\r
+ \brief Get Active Interrupt\r
+ \details Reads the active register in the NVIC and returns the active bit for the device specific interrupt.\r
+ \param [in] IRQn Device specific interrupt number.\r
+ \return 0 Interrupt status is not active.\r
+ \return 1 Interrupt status is active.\r
+ \note IRQn must not be negative.\r
+ */\r
+__STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn)\r
+{\r
+ if ((int32_t)(IRQn) >= 0)\r
+ {\r
+ return((uint32_t)(((NVIC->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));\r
+ }\r
+ else\r
+ {\r
+ return(0U);\r
+ }\r
+}\r
+\r
+\r
+/**\r
+ \brief Set Interrupt Priority\r
+ \details Sets the priority of a device specific interrupt or a processor exception.\r
+ The interrupt number can be positive to specify a device specific interrupt,\r
+ or negative to specify a processor exception.\r
+ \param [in] IRQn Interrupt number.\r
+ \param [in] priority Priority to set.\r
+ \note The priority cannot be set for every processor exception.\r
+ */\r
+__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)\r
+{\r
+ if ((int32_t)(IRQn) >= 0)\r
+ {\r
+ NVIC->IP[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);\r
+ }\r
+ else\r
+ {\r
+ SCB->SHP[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);\r
+ }\r
+}\r
+\r
+\r
+/**\r
+ \brief Get Interrupt Priority\r
+ \details Reads the priority of a device specific interrupt or a processor exception.\r
+ The interrupt number can be positive to specify a device specific interrupt,\r
+ or negative to specify a processor exception.\r
+ \param [in] IRQn Interrupt number.\r
+ \return Interrupt Priority.\r
+ Value is aligned automatically to the implemented priority bits of the microcontroller.\r
+ */\r
+__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn)\r
+{\r
+\r
+ if ((int32_t)(IRQn) >= 0)\r
+ {\r
+ return(((uint32_t)NVIC->IP[((uint32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS)));\r
+ }\r
+ else\r
+ {\r
+ return(((uint32_t)SCB->SHP[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS)));\r
+ }\r
+}\r
+\r
+\r
+/**\r
+ \brief Encode Priority\r
+ \details Encodes the priority for an interrupt with the given priority group,\r
+ preemptive priority value, and subpriority value.\r
+ In case of a conflict between priority grouping and available\r
+ priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.\r
+ \param [in] PriorityGroup Used priority group.\r
+ \param [in] PreemptPriority Preemptive priority value (starting from 0).\r
+ \param [in] SubPriority Subpriority value (starting from 0).\r
+ \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority().\r
+ */\r
+__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)\r
+{\r
+ uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */\r
+ uint32_t PreemptPriorityBits;\r
+ uint32_t SubPriorityBits;\r
+\r
+ PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);\r
+ SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));\r
+\r
+ return (\r
+ ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) |\r
+ ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL)))\r
+ );\r
+}\r
+\r
+\r
+/**\r
+ \brief Decode Priority\r
+ \details Decodes an interrupt priority value with a given priority group to\r
+ preemptive priority value and subpriority value.\r
+ In case of a conflict between priority grouping and available\r
+ priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set.\r
+ \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority().\r
+ \param [in] PriorityGroup Used priority group.\r
+ \param [out] pPreemptPriority Preemptive priority value (starting from 0).\r
+ \param [out] pSubPriority Subpriority value (starting from 0).\r
+ */\r
+__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority)\r
+{\r
+ uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */\r
+ uint32_t PreemptPriorityBits;\r
+ uint32_t SubPriorityBits;\r
+\r
+ PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);\r
+ SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));\r
+\r
+ *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL);\r
+ *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL);\r
+}\r
+\r
+\r
+/**\r
+ \brief Set Interrupt Vector\r
+ \details Sets an interrupt vector in SRAM based interrupt vector table.\r
+ The interrupt number can be positive to specify a device specific interrupt,\r
+ or negative to specify a processor exception.\r
+ VTOR must been relocated to SRAM before.\r
+ \param [in] IRQn Interrupt number\r
+ \param [in] vector Address of interrupt handler function\r
+ */\r
+__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector)\r
+{\r
+ uint32_t *vectors = (uint32_t *)SCB->VTOR;\r
+ vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector;\r
+}\r
+\r
+\r
+/**\r
+ \brief Get Interrupt Vector\r
+ \details Reads an interrupt vector from interrupt vector table.\r
+ The interrupt number can be positive to specify a device specific interrupt,\r
+ or negative to specify a processor exception.\r
+ \param [in] IRQn Interrupt number.\r
+ \return Address of interrupt handler function\r
+ */\r
+__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn)\r
+{\r
+ uint32_t *vectors = (uint32_t *)SCB->VTOR;\r
+ return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET];\r
+}\r
+\r
+\r
+/**\r
+ \brief System Reset\r
+ \details Initiates a system reset request to reset the MCU.\r
+ */\r
+__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void)\r
+{\r
+ __DSB(); /* Ensure all outstanding memory accesses included\r
+ buffered write are completed before reset */\r
+ SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |\r
+ (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) |\r
+ SCB_AIRCR_SYSRESETREQ_Msk ); /* Keep priority group unchanged */\r
+ __DSB(); /* Ensure completion of memory access */\r
+\r
+ for(;;) /* wait until reset */\r
+ {\r
+ __NOP();\r
+ }\r
+}\r
+\r
+/*@} end of CMSIS_Core_NVICFunctions */\r
+\r
+\r
+/* ########################## FPU functions #################################### */\r
+/**\r
+ \ingroup CMSIS_Core_FunctionInterface\r
+ \defgroup CMSIS_Core_FpuFunctions FPU Functions\r
+ \brief Function that provides FPU type.\r
+ @{\r
+ */\r
+\r
+/**\r
+ \brief get FPU type\r
+ \details returns the FPU type\r
+ \returns\r
+ - \b 0: No FPU\r
+ - \b 1: Single precision FPU\r
+ - \b 2: Double + Single precision FPU\r
+ */\r
+__STATIC_INLINE uint32_t SCB_GetFPUType(void)\r
+{\r
+ return 0U; /* No FPU */\r
+}\r
+\r
+\r
+/*@} end of CMSIS_Core_FpuFunctions */\r
+\r
+\r
+\r
+/* ################################## SysTick function ############################################ */\r
+/**\r
+ \ingroup CMSIS_Core_FunctionInterface\r
+ \defgroup CMSIS_Core_SysTickFunctions SysTick Functions\r
+ \brief Functions that configure the System.\r
+ @{\r
+ */\r
+\r
+#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U)\r
+\r
+/**\r
+ \brief System Tick Configuration\r
+ \details Initializes the System Timer and its interrupt, and starts the System Tick Timer.\r
+ Counter is in free running mode to generate periodic interrupts.\r
+ \param [in] ticks Number of ticks between two interrupts.\r
+ \return 0 Function succeeded.\r
+ \return 1 Function failed.\r
+ \note When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the\r
+ function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>\r
+ must contain a vendor-specific implementation of this function.\r
+ */\r
+__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)\r
+{\r
+ if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk)\r
+ {\r
+ return (1UL); /* Reload value impossible */\r
+ }\r
+\r
+ SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */\r
+ NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */\r
+ SysTick->VAL = 0UL; /* Load the SysTick Counter Value */\r
+ SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk |\r
+ SysTick_CTRL_TICKINT_Msk |\r
+ SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */\r
+ return (0UL); /* Function successful */\r
+}\r
+\r
+#endif\r
+\r
+/*@} end of CMSIS_Core_SysTickFunctions */\r
+\r
+\r
+\r
+/* ##################################### Debug In/Output function ########################################### */\r
+/**\r
+ \ingroup CMSIS_Core_FunctionInterface\r
+ \defgroup CMSIS_core_DebugFunctions ITM Functions\r
+ \brief Functions that access the ITM debug interface.\r
+ @{\r
+ */\r
+\r
+extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters. */\r
+#define ITM_RXBUFFER_EMPTY ((int32_t)0x5AA55AA5U) /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */\r
+\r
+\r
+/**\r
+ \brief ITM Send Character\r
+ \details Transmits a character via the ITM channel 0, and\r
+ \li Just returns when no debugger is connected that has booked the output.\r
+ \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted.\r
+ \param [in] ch Character to transmit.\r
+ \returns Character to transmit.\r
+ */\r
+__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch)\r
+{\r
+ if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) && /* ITM enabled */\r
+ ((ITM->TER & 1UL ) != 0UL) ) /* ITM Port #0 enabled */\r
+ {\r
+ while (ITM->PORT[0U].u32 == 0UL)\r
+ {\r
+ __NOP();\r
+ }\r
+ ITM->PORT[0U].u8 = (uint8_t)ch;\r
+ }\r
+ return (ch);\r
+}\r
+\r
+\r
+/**\r
+ \brief ITM Receive Character\r
+ \details Inputs a character via the external variable \ref ITM_RxBuffer.\r
+ \return Received character.\r
+ \return -1 No character pending.\r
+ */\r
+__STATIC_INLINE int32_t ITM_ReceiveChar (void)\r
+{\r
+ int32_t ch = -1; /* no character available */\r
+\r
+ if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY)\r
+ {\r
+ ch = ITM_RxBuffer;\r
+ ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */\r
+ }\r
+\r
+ return (ch);\r
+}\r
+\r
+\r
+/**\r
+ \brief ITM Check Character\r
+ \details Checks whether a character is pending for reading in the variable \ref ITM_RxBuffer.\r
+ \return 0 No character available.\r
+ \return 1 Character available.\r
+ */\r
+__STATIC_INLINE int32_t ITM_CheckChar (void)\r
+{\r
+\r
+ if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY)\r
+ {\r
+ return (0); /* no character available */\r
+ }\r
+ else\r
+ {\r
+ return (1); /* character available */\r
+ }\r
+}\r
+\r
+/*@} end of CMSIS_core_DebugFunctions */\r
+\r
+\r
+\r
+\r
+#ifdef __cplusplus\r
+}\r
+#endif\r
+\r
+#endif /* __CORE_SC300_H_DEPENDANT */\r
+\r
+#endif /* __CMSIS_GENERIC */\r
--- /dev/null
+/******************************************************************************\r
+ * @file mpu_armv7.h\r
+ * @brief CMSIS MPU API for Armv7-M MPU\r
+ * @version V5.0.4\r
+ * @date 10. January 2018\r
+ ******************************************************************************/\r
+/*\r
+ * Copyright (c) 2017-2018 Arm Limited. All rights reserved.\r
+ *\r
+ * SPDX-License-Identifier: Apache-2.0\r
+ *\r
+ * Licensed under the Apache License, Version 2.0 (the License); you may\r
+ * not use this file except in compliance with the License.\r
+ * You may obtain a copy of the License at\r
+ *\r
+ * www.apache.org/licenses/LICENSE-2.0\r
+ *\r
+ * Unless required by applicable law or agreed to in writing, software\r
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT\r
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\r
+ * See the License for the specific language governing permissions and\r
+ * limitations under the License.\r
+ */\r
+ \r
+#if defined ( __ICCARM__ )\r
+ #pragma system_include /* treat file as system include file for MISRA check */\r
+#elif defined (__clang__)\r
+ #pragma clang system_header /* treat file as system include file */\r
+#endif\r
+ \r
+#ifndef ARM_MPU_ARMV7_H\r
+#define ARM_MPU_ARMV7_H\r
+\r
+#define ARM_MPU_REGION_SIZE_32B ((uint8_t)0x04U) ///!< MPU Region Size 32 Bytes\r
+#define ARM_MPU_REGION_SIZE_64B ((uint8_t)0x05U) ///!< MPU Region Size 64 Bytes\r
+#define ARM_MPU_REGION_SIZE_128B ((uint8_t)0x06U) ///!< MPU Region Size 128 Bytes\r
+#define ARM_MPU_REGION_SIZE_256B ((uint8_t)0x07U) ///!< MPU Region Size 256 Bytes\r
+#define ARM_MPU_REGION_SIZE_512B ((uint8_t)0x08U) ///!< MPU Region Size 512 Bytes\r
+#define ARM_MPU_REGION_SIZE_1KB ((uint8_t)0x09U) ///!< MPU Region Size 1 KByte\r
+#define ARM_MPU_REGION_SIZE_2KB ((uint8_t)0x0AU) ///!< MPU Region Size 2 KBytes\r
+#define ARM_MPU_REGION_SIZE_4KB ((uint8_t)0x0BU) ///!< MPU Region Size 4 KBytes\r
+#define ARM_MPU_REGION_SIZE_8KB ((uint8_t)0x0CU) ///!< MPU Region Size 8 KBytes\r
+#define ARM_MPU_REGION_SIZE_16KB ((uint8_t)0x0DU) ///!< MPU Region Size 16 KBytes\r
+#define ARM_MPU_REGION_SIZE_32KB ((uint8_t)0x0EU) ///!< MPU Region Size 32 KBytes\r
+#define ARM_MPU_REGION_SIZE_64KB ((uint8_t)0x0FU) ///!< MPU Region Size 64 KBytes\r
+#define ARM_MPU_REGION_SIZE_128KB ((uint8_t)0x10U) ///!< MPU Region Size 128 KBytes\r
+#define ARM_MPU_REGION_SIZE_256KB ((uint8_t)0x11U) ///!< MPU Region Size 256 KBytes\r
+#define ARM_MPU_REGION_SIZE_512KB ((uint8_t)0x12U) ///!< MPU Region Size 512 KBytes\r
+#define ARM_MPU_REGION_SIZE_1MB ((uint8_t)0x13U) ///!< MPU Region Size 1 MByte\r
+#define ARM_MPU_REGION_SIZE_2MB ((uint8_t)0x14U) ///!< MPU Region Size 2 MBytes\r
+#define ARM_MPU_REGION_SIZE_4MB ((uint8_t)0x15U) ///!< MPU Region Size 4 MBytes\r
+#define ARM_MPU_REGION_SIZE_8MB ((uint8_t)0x16U) ///!< MPU Region Size 8 MBytes\r
+#define ARM_MPU_REGION_SIZE_16MB ((uint8_t)0x17U) ///!< MPU Region Size 16 MBytes\r
+#define ARM_MPU_REGION_SIZE_32MB ((uint8_t)0x18U) ///!< MPU Region Size 32 MBytes\r
+#define ARM_MPU_REGION_SIZE_64MB ((uint8_t)0x19U) ///!< MPU Region Size 64 MBytes\r
+#define ARM_MPU_REGION_SIZE_128MB ((uint8_t)0x1AU) ///!< MPU Region Size 128 MBytes\r
+#define ARM_MPU_REGION_SIZE_256MB ((uint8_t)0x1BU) ///!< MPU Region Size 256 MBytes\r
+#define ARM_MPU_REGION_SIZE_512MB ((uint8_t)0x1CU) ///!< MPU Region Size 512 MBytes\r
+#define ARM_MPU_REGION_SIZE_1GB ((uint8_t)0x1DU) ///!< MPU Region Size 1 GByte\r
+#define ARM_MPU_REGION_SIZE_2GB ((uint8_t)0x1EU) ///!< MPU Region Size 2 GBytes\r
+#define ARM_MPU_REGION_SIZE_4GB ((uint8_t)0x1FU) ///!< MPU Region Size 4 GBytes\r
+\r
+#define ARM_MPU_AP_NONE 0U ///!< MPU Access Permission no access\r
+#define ARM_MPU_AP_PRIV 1U ///!< MPU Access Permission privileged access only\r
+#define ARM_MPU_AP_URO 2U ///!< MPU Access Permission unprivileged access read-only\r
+#define ARM_MPU_AP_FULL 3U ///!< MPU Access Permission full access\r
+#define ARM_MPU_AP_PRO 5U ///!< MPU Access Permission privileged access read-only\r
+#define ARM_MPU_AP_RO 6U ///!< MPU Access Permission read-only access\r
+\r
+/** MPU Region Base Address Register Value\r
+*\r
+* \param Region The region to be configured, number 0 to 15.\r
+* \param BaseAddress The base address for the region.\r
+*/\r
+#define ARM_MPU_RBAR(Region, BaseAddress) \\r
+ (((BaseAddress) & MPU_RBAR_ADDR_Msk) | \\r
+ ((Region) & MPU_RBAR_REGION_Msk) | \\r
+ (MPU_RBAR_VALID_Msk))\r
+\r
+/**\r
+* MPU Memory Access Attributes\r
+* \r
+* \param TypeExtField Type extension field, allows you to configure memory access type, for example strongly ordered, peripheral.\r
+* \param IsShareable Region is shareable between multiple bus masters.\r
+* \param IsCacheable Region is cacheable, i.e. its value may be kept in cache.\r
+* \param IsBufferable Region is bufferable, i.e. using write-back caching. Cacheable but non-bufferable regions use write-through policy.\r
+*/ \r
+#define ARM_MPU_ACCESS_(TypeExtField, IsShareable, IsCacheable, IsBufferable) \\r
+ ((((TypeExtField ) << MPU_RASR_TEX_Pos) & MPU_RASR_TEX_Msk) | \\r
+ (((IsShareable ) << MPU_RASR_S_Pos) & MPU_RASR_S_Msk) | \\r
+ (((IsCacheable ) << MPU_RASR_C_Pos) & MPU_RASR_C_Msk) | \\r
+ (((IsBufferable ) << MPU_RASR_B_Pos) & MPU_RASR_B_Msk))\r
+\r
+/**\r
+* MPU Region Attribute and Size Register Value\r
+* \r
+* \param DisableExec Instruction access disable bit, 1= disable instruction fetches.\r
+* \param AccessPermission Data access permissions, allows you to configure read/write access for User and Privileged mode.\r
+* \param AccessAttributes Memory access attribution, see \ref ARM_MPU_ACCESS_.\r
+* \param SubRegionDisable Sub-region disable field.\r
+* \param Size Region size of the region to be configured, for example 4K, 8K.\r
+*/\r
+#define ARM_MPU_RASR_EX(DisableExec, AccessPermission, AccessAttributes, SubRegionDisable, Size) \\r
+ ((((DisableExec ) << MPU_RASR_XN_Pos) & MPU_RASR_XN_Msk) | \\r
+ (((AccessPermission) << MPU_RASR_AP_Pos) & MPU_RASR_AP_Msk) | \\r
+ (((AccessAttributes) ) & (MPU_RASR_TEX_Msk | MPU_RASR_S_Msk | MPU_RASR_C_Msk | MPU_RASR_B_Msk)))\r
+ \r
+/**\r
+* MPU Region Attribute and Size Register Value\r
+* \r
+* \param DisableExec Instruction access disable bit, 1= disable instruction fetches.\r
+* \param AccessPermission Data access permissions, allows you to configure read/write access for User and Privileged mode.\r
+* \param TypeExtField Type extension field, allows you to configure memory access type, for example strongly ordered, peripheral.\r
+* \param IsShareable Region is shareable between multiple bus masters.\r
+* \param IsCacheable Region is cacheable, i.e. its value may be kept in cache.\r
+* \param IsBufferable Region is bufferable, i.e. using write-back caching. Cacheable but non-bufferable regions use write-through policy.\r
+* \param SubRegionDisable Sub-region disable field.\r
+* \param Size Region size of the region to be configured, for example 4K, 8K.\r
+*/ \r
+#define ARM_MPU_RASR(DisableExec, AccessPermission, TypeExtField, IsShareable, IsCacheable, IsBufferable, SubRegionDisable, Size) \\r
+ ARM_MPU_RASR_EX(DisableExec, AccessPermission, ARM_MPU_ACCESS_(TypeExtField, IsShareable, IsCacheable, IsBufferable), SubRegionDisable, Size)\r
+\r
+/**\r
+* MPU Memory Access Attribute for strongly ordered memory.\r
+* - TEX: 000b\r
+* - Shareable\r
+* - Non-cacheable\r
+* - Non-bufferable\r
+*/ \r
+#define ARM_MPU_ACCESS_ORDERED ARM_MPU_ACCESS_(0U, 1U, 0U, 0U)\r
+\r
+/**\r
+* MPU Memory Access Attribute for device memory.\r
+* - TEX: 000b (if non-shareable) or 010b (if shareable)\r
+* - Shareable or non-shareable\r
+* - Non-cacheable\r
+* - Bufferable (if shareable) or non-bufferable (if non-shareable)\r
+*\r
+* \param IsShareable Configures the device memory as shareable or non-shareable.\r
+*/ \r
+#define ARM_MPU_ACCESS_DEVICE(IsShareable) ((IsShareable) ? ARM_MPU_ACCESS_(0U, 1U, 0U, 1U) : ARM_MPU_ACCESS_(2U, 0U, 0U, 0U))\r
+\r
+/**\r
+* MPU Memory Access Attribute for normal memory.\r
+* - TEX: 1BBb (reflecting outer cacheability rules)\r
+* - Shareable or non-shareable\r
+* - Cacheable or non-cacheable (reflecting inner cacheability rules)\r
+* - Bufferable or non-bufferable (reflecting inner cacheability rules)\r
+*\r
+* \param OuterCp Configures the outer cache policy.\r
+* \param InnerCp Configures the inner cache policy.\r
+* \param IsShareable Configures the memory as shareable or non-shareable.\r
+*/ \r
+#define ARM_MPU_ACCESS_NORMAL(OuterCp, InnerCp, IsShareable) ARM_MPU_ACCESS_((4U | (OuterCp)), IsShareable, ((InnerCp) & 2U), ((InnerCp) & 1U))\r
+\r
+/**\r
+* MPU Memory Access Attribute non-cacheable policy.\r
+*/\r
+#define ARM_MPU_CACHEP_NOCACHE 0U\r
+\r
+/**\r
+* MPU Memory Access Attribute write-back, write and read allocate policy.\r
+*/\r
+#define ARM_MPU_CACHEP_WB_WRA 1U\r
+\r
+/**\r
+* MPU Memory Access Attribute write-through, no write allocate policy.\r
+*/\r
+#define ARM_MPU_CACHEP_WT_NWA 2U\r
+\r
+/**\r
+* MPU Memory Access Attribute write-back, no write allocate policy.\r
+*/\r
+#define ARM_MPU_CACHEP_WB_NWA 3U\r
+\r
+\r
+/**\r
+* Struct for a single MPU Region\r
+*/\r
+typedef struct {\r
+ uint32_t RBAR; //!< The region base address register value (RBAR)\r
+ uint32_t RASR; //!< The region attribute and size register value (RASR) \ref MPU_RASR\r
+} ARM_MPU_Region_t;\r
+ \r
+/** Enable the MPU.\r
+* \param MPU_Control Default access permissions for unconfigured regions.\r
+*/\r
+__STATIC_INLINE void ARM_MPU_Enable(uint32_t MPU_Control)\r
+{\r
+ __DSB();\r
+ __ISB();\r
+ MPU->CTRL = MPU_Control | MPU_CTRL_ENABLE_Msk;\r
+#ifdef SCB_SHCSR_MEMFAULTENA_Msk\r
+ SCB->SHCSR |= SCB_SHCSR_MEMFAULTENA_Msk;\r
+#endif\r
+}\r
+\r
+/** Disable the MPU.\r
+*/\r
+__STATIC_INLINE void ARM_MPU_Disable(void)\r
+{\r
+ __DSB();\r
+ __ISB();\r
+#ifdef SCB_SHCSR_MEMFAULTENA_Msk\r
+ SCB->SHCSR &= ~SCB_SHCSR_MEMFAULTENA_Msk;\r
+#endif\r
+ MPU->CTRL &= ~MPU_CTRL_ENABLE_Msk;\r
+}\r
+\r
+/** Clear and disable the given MPU region.\r
+* \param rnr Region number to be cleared.\r
+*/\r
+__STATIC_INLINE void ARM_MPU_ClrRegion(uint32_t rnr)\r
+{\r
+ MPU->RNR = rnr;\r
+ MPU->RASR = 0U;\r
+}\r
+\r
+/** Configure an MPU region.\r
+* \param rbar Value for RBAR register.\r
+* \param rsar Value for RSAR register.\r
+*/ \r
+__STATIC_INLINE void ARM_MPU_SetRegion(uint32_t rbar, uint32_t rasr)\r
+{\r
+ MPU->RBAR = rbar;\r
+ MPU->RASR = rasr;\r
+}\r
+\r
+/** Configure the given MPU region.\r
+* \param rnr Region number to be configured.\r
+* \param rbar Value for RBAR register.\r
+* \param rsar Value for RSAR register.\r
+*/ \r
+__STATIC_INLINE void ARM_MPU_SetRegionEx(uint32_t rnr, uint32_t rbar, uint32_t rasr)\r
+{\r
+ MPU->RNR = rnr;\r
+ MPU->RBAR = rbar;\r
+ MPU->RASR = rasr;\r
+}\r
+\r
+/** Memcopy with strictly ordered memory access, e.g. for register targets.\r
+* \param dst Destination data is copied to.\r
+* \param src Source data is copied from.\r
+* \param len Amount of data words to be copied.\r
+*/\r
+__STATIC_INLINE void orderedCpy(volatile uint32_t* dst, const uint32_t* __RESTRICT src, uint32_t len)\r
+{\r
+ uint32_t i;\r
+ for (i = 0U; i < len; ++i) \r
+ {\r
+ dst[i] = src[i];\r
+ }\r
+}\r
+\r
+/** Load the given number of MPU regions from a table.\r
+* \param table Pointer to the MPU configuration table.\r
+* \param cnt Amount of regions to be configured.\r
+*/\r
+__STATIC_INLINE void ARM_MPU_Load(ARM_MPU_Region_t const* table, uint32_t cnt) \r
+{\r
+ const uint32_t rowWordSize = sizeof(ARM_MPU_Region_t)/4U;\r
+ while (cnt > MPU_TYPE_RALIASES) {\r
+ orderedCpy(&(MPU->RBAR), &(table->RBAR), MPU_TYPE_RALIASES*rowWordSize);\r
+ table += MPU_TYPE_RALIASES;\r
+ cnt -= MPU_TYPE_RALIASES;\r
+ }\r
+ orderedCpy(&(MPU->RBAR), &(table->RBAR), cnt*rowWordSize);\r
+}\r
+\r
+#endif\r
--- /dev/null
+/******************************************************************************\r
+ * @file mpu_armv8.h\r
+ * @brief CMSIS MPU API for Armv8-M MPU\r
+ * @version V5.0.4\r
+ * @date 10. January 2018\r
+ ******************************************************************************/\r
+/*\r
+ * Copyright (c) 2017-2018 Arm Limited. All rights reserved.\r
+ *\r
+ * SPDX-License-Identifier: Apache-2.0\r
+ *\r
+ * Licensed under the Apache License, Version 2.0 (the License); you may\r
+ * not use this file except in compliance with the License.\r
+ * You may obtain a copy of the License at\r
+ *\r
+ * www.apache.org/licenses/LICENSE-2.0\r
+ *\r
+ * Unless required by applicable law or agreed to in writing, software\r
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT\r
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\r
+ * See the License for the specific language governing permissions and\r
+ * limitations under the License.\r
+ */\r
+\r
+#if defined ( __ICCARM__ )\r
+ #pragma system_include /* treat file as system include file for MISRA check */\r
+#elif defined (__clang__)\r
+ #pragma clang system_header /* treat file as system include file */\r
+#endif\r
+\r
+#ifndef ARM_MPU_ARMV8_H\r
+#define ARM_MPU_ARMV8_H\r
+\r
+/** \brief Attribute for device memory (outer only) */\r
+#define ARM_MPU_ATTR_DEVICE ( 0U )\r
+\r
+/** \brief Attribute for non-cacheable, normal memory */\r
+#define ARM_MPU_ATTR_NON_CACHEABLE ( 4U )\r
+\r
+/** \brief Attribute for normal memory (outer and inner)\r
+* \param NT Non-Transient: Set to 1 for non-transient data.\r
+* \param WB Write-Back: Set to 1 to use write-back update policy.\r
+* \param RA Read Allocation: Set to 1 to use cache allocation on read miss.\r
+* \param WA Write Allocation: Set to 1 to use cache allocation on write miss.\r
+*/\r
+#define ARM_MPU_ATTR_MEMORY_(NT, WB, RA, WA) \\r
+ (((NT & 1U) << 3U) | ((WB & 1U) << 2U) | ((RA & 1U) << 1U) | (WA & 1U))\r
+\r
+/** \brief Device memory type non Gathering, non Re-ordering, non Early Write Acknowledgement */\r
+#define ARM_MPU_ATTR_DEVICE_nGnRnE (0U)\r
+\r
+/** \brief Device memory type non Gathering, non Re-ordering, Early Write Acknowledgement */\r
+#define ARM_MPU_ATTR_DEVICE_nGnRE (1U)\r
+\r
+/** \brief Device memory type non Gathering, Re-ordering, Early Write Acknowledgement */\r
+#define ARM_MPU_ATTR_DEVICE_nGRE (2U)\r
+\r
+/** \brief Device memory type Gathering, Re-ordering, Early Write Acknowledgement */\r
+#define ARM_MPU_ATTR_DEVICE_GRE (3U)\r
+\r
+/** \brief Memory Attribute\r
+* \param O Outer memory attributes\r
+* \param I O == ARM_MPU_ATTR_DEVICE: Device memory attributes, else: Inner memory attributes\r
+*/\r
+#define ARM_MPU_ATTR(O, I) (((O & 0xFU) << 4U) | (((O & 0xFU) != 0U) ? (I & 0xFU) : ((I & 0x3U) << 2U)))\r
+\r
+/** \brief Normal memory non-shareable */\r
+#define ARM_MPU_SH_NON (0U)\r
+\r
+/** \brief Normal memory outer shareable */\r
+#define ARM_MPU_SH_OUTER (2U)\r
+\r
+/** \brief Normal memory inner shareable */\r
+#define ARM_MPU_SH_INNER (3U)\r
+\r
+/** \brief Memory access permissions\r
+* \param RO Read-Only: Set to 1 for read-only memory.\r
+* \param NP Non-Privileged: Set to 1 for non-privileged memory.\r
+*/\r
+#define ARM_MPU_AP_(RO, NP) (((RO & 1U) << 1U) | (NP & 1U))\r
+\r
+/** \brief Region Base Address Register value\r
+* \param BASE The base address bits [31:5] of a memory region. The value is zero extended. Effective address gets 32 byte aligned.\r
+* \param SH Defines the Shareability domain for this memory region.\r
+* \param RO Read-Only: Set to 1 for a read-only memory region.\r
+* \param NP Non-Privileged: Set to 1 for a non-privileged memory region.\r
+* \oaram XN eXecute Never: Set to 1 for a non-executable memory region.\r
+*/\r
+#define ARM_MPU_RBAR(BASE, SH, RO, NP, XN) \\r
+ ((BASE & MPU_RBAR_BASE_Msk) | \\r
+ ((SH << MPU_RBAR_SH_Pos) & MPU_RBAR_SH_Msk) | \\r
+ ((ARM_MPU_AP_(RO, NP) << MPU_RBAR_AP_Pos) & MPU_RBAR_AP_Msk) | \\r
+ ((XN << MPU_RBAR_XN_Pos) & MPU_RBAR_XN_Msk))\r
+\r
+/** \brief Region Limit Address Register value\r
+* \param LIMIT The limit address bits [31:5] for this memory region. The value is one extended.\r
+* \param IDX The attribute index to be associated with this memory region.\r
+*/\r
+#define ARM_MPU_RLAR(LIMIT, IDX) \\r
+ ((LIMIT & MPU_RLAR_LIMIT_Msk) | \\r
+ ((IDX << MPU_RLAR_AttrIndx_Pos) & MPU_RLAR_AttrIndx_Msk) | \\r
+ (MPU_RLAR_EN_Msk))\r
+\r
+/**\r
+* Struct for a single MPU Region\r
+*/\r
+typedef struct {\r
+ uint32_t RBAR; /*!< Region Base Address Register value */\r
+ uint32_t RLAR; /*!< Region Limit Address Register value */\r
+} ARM_MPU_Region_t;\r
+ \r
+/** Enable the MPU.\r
+* \param MPU_Control Default access permissions for unconfigured regions.\r
+*/\r
+__STATIC_INLINE void ARM_MPU_Enable(uint32_t MPU_Control)\r
+{\r
+ __DSB();\r
+ __ISB();\r
+ MPU->CTRL = MPU_Control | MPU_CTRL_ENABLE_Msk;\r
+#ifdef SCB_SHCSR_MEMFAULTENA_Msk\r
+ SCB->SHCSR |= SCB_SHCSR_MEMFAULTENA_Msk;\r
+#endif\r
+}\r
+\r
+/** Disable the MPU.\r
+*/\r
+__STATIC_INLINE void ARM_MPU_Disable(void)\r
+{\r
+ __DSB();\r
+ __ISB();\r
+#ifdef SCB_SHCSR_MEMFAULTENA_Msk\r
+ SCB->SHCSR &= ~SCB_SHCSR_MEMFAULTENA_Msk;\r
+#endif\r
+ MPU->CTRL &= ~MPU_CTRL_ENABLE_Msk;\r
+}\r
+\r
+#ifdef MPU_NS\r
+/** Enable the Non-secure MPU.\r
+* \param MPU_Control Default access permissions for unconfigured regions.\r
+*/\r
+__STATIC_INLINE void ARM_MPU_Enable_NS(uint32_t MPU_Control)\r
+{\r
+ __DSB();\r
+ __ISB();\r
+ MPU_NS->CTRL = MPU_Control | MPU_CTRL_ENABLE_Msk;\r
+#ifdef SCB_SHCSR_MEMFAULTENA_Msk\r
+ SCB_NS->SHCSR |= SCB_SHCSR_MEMFAULTENA_Msk;\r
+#endif\r
+}\r
+\r
+/** Disable the Non-secure MPU.\r
+*/\r
+__STATIC_INLINE void ARM_MPU_Disable_NS(void)\r
+{\r
+ __DSB();\r
+ __ISB();\r
+#ifdef SCB_SHCSR_MEMFAULTENA_Msk\r
+ SCB_NS->SHCSR &= ~SCB_SHCSR_MEMFAULTENA_Msk;\r
+#endif\r
+ MPU_NS->CTRL &= ~MPU_CTRL_ENABLE_Msk;\r
+}\r
+#endif\r
+\r
+/** Set the memory attribute encoding to the given MPU.\r
+* \param mpu Pointer to the MPU to be configured.\r
+* \param idx The attribute index to be set [0-7]\r
+* \param attr The attribute value to be set.\r
+*/\r
+__STATIC_INLINE void ARM_MPU_SetMemAttrEx(MPU_Type* mpu, uint8_t idx, uint8_t attr)\r
+{\r
+ const uint8_t reg = idx / 4U;\r
+ const uint32_t pos = ((idx % 4U) * 8U);\r
+ const uint32_t mask = 0xFFU << pos;\r
+ \r
+ if (reg >= (sizeof(mpu->MAIR) / sizeof(mpu->MAIR[0]))) {\r
+ return; // invalid index\r
+ }\r
+ \r
+ mpu->MAIR[reg] = ((mpu->MAIR[reg] & ~mask) | ((attr << pos) & mask));\r
+}\r
+\r
+/** Set the memory attribute encoding.\r
+* \param idx The attribute index to be set [0-7]\r
+* \param attr The attribute value to be set.\r
+*/\r
+__STATIC_INLINE void ARM_MPU_SetMemAttr(uint8_t idx, uint8_t attr)\r
+{\r
+ ARM_MPU_SetMemAttrEx(MPU, idx, attr);\r
+}\r
+\r
+#ifdef MPU_NS\r
+/** Set the memory attribute encoding to the Non-secure MPU.\r
+* \param idx The attribute index to be set [0-7]\r
+* \param attr The attribute value to be set.\r
+*/\r
+__STATIC_INLINE void ARM_MPU_SetMemAttr_NS(uint8_t idx, uint8_t attr)\r
+{\r
+ ARM_MPU_SetMemAttrEx(MPU_NS, idx, attr);\r
+}\r
+#endif\r
+\r
+/** Clear and disable the given MPU region of the given MPU.\r
+* \param mpu Pointer to MPU to be used.\r
+* \param rnr Region number to be cleared.\r
+*/\r
+__STATIC_INLINE void ARM_MPU_ClrRegionEx(MPU_Type* mpu, uint32_t rnr)\r
+{\r
+ mpu->RNR = rnr;\r
+ mpu->RLAR = 0U;\r
+}\r
+\r
+/** Clear and disable the given MPU region.\r
+* \param rnr Region number to be cleared.\r
+*/\r
+__STATIC_INLINE void ARM_MPU_ClrRegion(uint32_t rnr)\r
+{\r
+ ARM_MPU_ClrRegionEx(MPU, rnr);\r
+}\r
+\r
+#ifdef MPU_NS\r
+/** Clear and disable the given Non-secure MPU region.\r
+* \param rnr Region number to be cleared.\r
+*/\r
+__STATIC_INLINE void ARM_MPU_ClrRegion_NS(uint32_t rnr)\r
+{ \r
+ ARM_MPU_ClrRegionEx(MPU_NS, rnr);\r
+}\r
+#endif\r
+\r
+/** Configure the given MPU region of the given MPU.\r
+* \param mpu Pointer to MPU to be used.\r
+* \param rnr Region number to be configured.\r
+* \param rbar Value for RBAR register.\r
+* \param rlar Value for RLAR register.\r
+*/ \r
+__STATIC_INLINE void ARM_MPU_SetRegionEx(MPU_Type* mpu, uint32_t rnr, uint32_t rbar, uint32_t rlar)\r
+{\r
+ mpu->RNR = rnr;\r
+ mpu->RBAR = rbar;\r
+ mpu->RLAR = rlar;\r
+}\r
+\r
+/** Configure the given MPU region.\r
+* \param rnr Region number to be configured.\r
+* \param rbar Value for RBAR register.\r
+* \param rlar Value for RLAR register.\r
+*/ \r
+__STATIC_INLINE void ARM_MPU_SetRegion(uint32_t rnr, uint32_t rbar, uint32_t rlar)\r
+{\r
+ ARM_MPU_SetRegionEx(MPU, rnr, rbar, rlar);\r
+}\r
+\r
+#ifdef MPU_NS\r
+/** Configure the given Non-secure MPU region.\r
+* \param rnr Region number to be configured.\r
+* \param rbar Value for RBAR register.\r
+* \param rlar Value for RLAR register.\r
+*/ \r
+__STATIC_INLINE void ARM_MPU_SetRegion_NS(uint32_t rnr, uint32_t rbar, uint32_t rlar)\r
+{\r
+ ARM_MPU_SetRegionEx(MPU_NS, rnr, rbar, rlar); \r
+}\r
+#endif\r
+\r
+/** Memcopy with strictly ordered memory access, e.g. for register targets.\r
+* \param dst Destination data is copied to.\r
+* \param src Source data is copied from.\r
+* \param len Amount of data words to be copied.\r
+*/\r
+__STATIC_INLINE void orderedCpy(volatile uint32_t* dst, const uint32_t* __RESTRICT src, uint32_t len)\r
+{\r
+ uint32_t i;\r
+ for (i = 0U; i < len; ++i) \r
+ {\r
+ dst[i] = src[i];\r
+ }\r
+}\r
+\r
+/** Load the given number of MPU regions from a table to the given MPU.\r
+* \param mpu Pointer to the MPU registers to be used.\r
+* \param rnr First region number to be configured.\r
+* \param table Pointer to the MPU configuration table.\r
+* \param cnt Amount of regions to be configured.\r
+*/\r
+__STATIC_INLINE void ARM_MPU_LoadEx(MPU_Type* mpu, uint32_t rnr, ARM_MPU_Region_t const* table, uint32_t cnt) \r
+{\r
+ const uint32_t rowWordSize = sizeof(ARM_MPU_Region_t)/4U;\r
+ if (cnt == 1U) {\r
+ mpu->RNR = rnr;\r
+ orderedCpy(&(mpu->RBAR), &(table->RBAR), rowWordSize);\r
+ } else {\r
+ uint32_t rnrBase = rnr & ~(MPU_TYPE_RALIASES-1U);\r
+ uint32_t rnrOffset = rnr % MPU_TYPE_RALIASES;\r
+ \r
+ mpu->RNR = rnrBase;\r
+ while ((rnrOffset + cnt) > MPU_TYPE_RALIASES) {\r
+ uint32_t c = MPU_TYPE_RALIASES - rnrOffset;\r
+ orderedCpy(&(mpu->RBAR)+(rnrOffset*2U), &(table->RBAR), c*rowWordSize);\r
+ table += c;\r
+ cnt -= c;\r
+ rnrOffset = 0U;\r
+ rnrBase += MPU_TYPE_RALIASES;\r
+ mpu->RNR = rnrBase;\r
+ }\r
+ \r
+ orderedCpy(&(mpu->RBAR)+(rnrOffset*2U), &(table->RBAR), cnt*rowWordSize);\r
+ }\r
+}\r
+\r
+/** Load the given number of MPU regions from a table.\r
+* \param rnr First region number to be configured.\r
+* \param table Pointer to the MPU configuration table.\r
+* \param cnt Amount of regions to be configured.\r
+*/\r
+__STATIC_INLINE void ARM_MPU_Load(uint32_t rnr, ARM_MPU_Region_t const* table, uint32_t cnt) \r
+{\r
+ ARM_MPU_LoadEx(MPU, rnr, table, cnt);\r
+}\r
+\r
+#ifdef MPU_NS\r
+/** Load the given number of MPU regions from a table to the Non-secure MPU.\r
+* \param rnr First region number to be configured.\r
+* \param table Pointer to the MPU configuration table.\r
+* \param cnt Amount of regions to be configured.\r
+*/\r
+__STATIC_INLINE void ARM_MPU_Load_NS(uint32_t rnr, ARM_MPU_Region_t const* table, uint32_t cnt) \r
+{\r
+ ARM_MPU_LoadEx(MPU_NS, rnr, table, cnt);\r
+}\r
+#endif\r
+\r
+#endif\r
+\r
--- /dev/null
+/******************************************************************************\r
+ * @file tz_context.h\r
+ * @brief Context Management for Armv8-M TrustZone\r
+ * @version V1.0.1\r
+ * @date 10. January 2018\r
+ ******************************************************************************/\r
+/*\r
+ * Copyright (c) 2017-2018 Arm Limited. All rights reserved.\r
+ *\r
+ * SPDX-License-Identifier: Apache-2.0\r
+ *\r
+ * Licensed under the Apache License, Version 2.0 (the License); you may\r
+ * not use this file except in compliance with the License.\r
+ * You may obtain a copy of the License at\r
+ *\r
+ * www.apache.org/licenses/LICENSE-2.0\r
+ *\r
+ * Unless required by applicable law or agreed to in writing, software\r
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT\r
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\r
+ * See the License for the specific language governing permissions and\r
+ * limitations under the License.\r
+ */\r
+\r
+#if defined ( __ICCARM__ )\r
+ #pragma system_include /* treat file as system include file for MISRA check */\r
+#elif defined (__clang__)\r
+ #pragma clang system_header /* treat file as system include file */\r
+#endif\r
+\r
+#ifndef TZ_CONTEXT_H\r
+#define TZ_CONTEXT_H\r
+ \r
+#include <stdint.h>\r
+ \r
+#ifndef TZ_MODULEID_T\r
+#define TZ_MODULEID_T\r
+/// \details Data type that identifies secure software modules called by a process.\r
+typedef uint32_t TZ_ModuleId_t;\r
+#endif\r
+ \r
+/// \details TZ Memory ID identifies an allocated memory slot.\r
+typedef uint32_t TZ_MemoryId_t;\r
+ \r
+/// Initialize secure context memory system\r
+/// \return execution status (1: success, 0: error)\r
+uint32_t TZ_InitContextSystem_S (void);\r
+ \r
+/// Allocate context memory for calling secure software modules in TrustZone\r
+/// \param[in] module identifies software modules called from non-secure mode\r
+/// \return value != 0 id TrustZone memory slot identifier\r
+/// \return value 0 no memory available or internal error\r
+TZ_MemoryId_t TZ_AllocModuleContext_S (TZ_ModuleId_t module);\r
+ \r
+/// Free context memory that was previously allocated with \ref TZ_AllocModuleContext_S\r
+/// \param[in] id TrustZone memory slot identifier\r
+/// \return execution status (1: success, 0: error)\r
+uint32_t TZ_FreeModuleContext_S (TZ_MemoryId_t id);\r
+ \r
+/// Load secure context (called on RTOS thread context switch)\r
+/// \param[in] id TrustZone memory slot identifier\r
+/// \return execution status (1: success, 0: error)\r
+uint32_t TZ_LoadContext_S (TZ_MemoryId_t id);\r
+ \r
+/// Store secure context (called on RTOS thread context switch)\r
+/// \param[in] id TrustZone memory slot identifier\r
+/// \return execution status (1: success, 0: error)\r
+uint32_t TZ_StoreContext_S (TZ_MemoryId_t id);\r
+ \r
+#endif // TZ_CONTEXT_H\r
--- /dev/null
+/**\r
+ ******************************************************************************\r
+ * @file stm32_hal_legacy.h\r
+ * @author MCD Application Team\r
+ * @brief This file contains aliases definition for the STM32Cube HAL constants\r
+ * macros and functions maintained for legacy purpose.\r
+ ******************************************************************************\r
+ * @attention\r
+ *\r
+ * <h2><center>© Copyright (c) 2018 STMicroelectronics.\r
+ * All rights reserved.</center></h2>\r
+ *\r
+ * This software component is licensed by ST under BSD 3-Clause license,\r
+ * the "License"; You may not use this file except in compliance with the\r
+ * License. You may obtain a copy of the License at:\r
+ * opensource.org/licenses/BSD-3-Clause\r
+ *\r
+ ******************************************************************************\r
+ */\r
+\r
+/* Define to prevent recursive inclusion -------------------------------------*/\r
+#ifndef STM32_HAL_LEGACY\r
+#define STM32_HAL_LEGACY\r
+\r
+#ifdef __cplusplus\r
+ extern "C" {\r
+#endif\r
+\r
+/* Includes ------------------------------------------------------------------*/\r
+/* Exported types ------------------------------------------------------------*/\r
+/* Exported constants --------------------------------------------------------*/\r
+\r
+/** @defgroup HAL_AES_Aliased_Defines HAL CRYP Aliased Defines maintained for legacy purpose\r
+ * @{\r
+ */\r
+#define AES_FLAG_RDERR CRYP_FLAG_RDERR\r
+#define AES_FLAG_WRERR CRYP_FLAG_WRERR\r
+#define AES_CLEARFLAG_CCF CRYP_CLEARFLAG_CCF\r
+#define AES_CLEARFLAG_RDERR CRYP_CLEARFLAG_RDERR\r
+#define AES_CLEARFLAG_WRERR CRYP_CLEARFLAG_WRERR\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup HAL_ADC_Aliased_Defines HAL ADC Aliased Defines maintained for legacy purpose\r
+ * @{\r
+ */\r
+#define ADC_RESOLUTION12b ADC_RESOLUTION_12B\r
+#define ADC_RESOLUTION10b ADC_RESOLUTION_10B\r
+#define ADC_RESOLUTION8b ADC_RESOLUTION_8B\r
+#define ADC_RESOLUTION6b ADC_RESOLUTION_6B\r
+#define OVR_DATA_OVERWRITTEN ADC_OVR_DATA_OVERWRITTEN\r
+#define OVR_DATA_PRESERVED ADC_OVR_DATA_PRESERVED\r
+#define EOC_SINGLE_CONV ADC_EOC_SINGLE_CONV\r
+#define EOC_SEQ_CONV ADC_EOC_SEQ_CONV\r
+#define EOC_SINGLE_SEQ_CONV ADC_EOC_SINGLE_SEQ_CONV\r
+#define REGULAR_GROUP ADC_REGULAR_GROUP\r
+#define INJECTED_GROUP ADC_INJECTED_GROUP\r
+#define REGULAR_INJECTED_GROUP ADC_REGULAR_INJECTED_GROUP\r
+#define AWD_EVENT ADC_AWD_EVENT\r
+#define AWD1_EVENT ADC_AWD1_EVENT\r
+#define AWD2_EVENT ADC_AWD2_EVENT\r
+#define AWD3_EVENT ADC_AWD3_EVENT\r
+#define OVR_EVENT ADC_OVR_EVENT\r
+#define JQOVF_EVENT ADC_JQOVF_EVENT\r
+#define ALL_CHANNELS ADC_ALL_CHANNELS\r
+#define REGULAR_CHANNELS ADC_REGULAR_CHANNELS\r
+#define INJECTED_CHANNELS ADC_INJECTED_CHANNELS\r
+#define SYSCFG_FLAG_SENSOR_ADC ADC_FLAG_SENSOR\r
+#define SYSCFG_FLAG_VREF_ADC ADC_FLAG_VREFINT\r
+#define ADC_CLOCKPRESCALER_PCLK_DIV1 ADC_CLOCK_SYNC_PCLK_DIV1\r
+#define ADC_CLOCKPRESCALER_PCLK_DIV2 ADC_CLOCK_SYNC_PCLK_DIV2\r
+#define ADC_CLOCKPRESCALER_PCLK_DIV4 ADC_CLOCK_SYNC_PCLK_DIV4\r
+#define ADC_CLOCKPRESCALER_PCLK_DIV6 ADC_CLOCK_SYNC_PCLK_DIV6\r
+#define ADC_CLOCKPRESCALER_PCLK_DIV8 ADC_CLOCK_SYNC_PCLK_DIV8\r
+#define ADC_EXTERNALTRIG0_T6_TRGO ADC_EXTERNALTRIGCONV_T6_TRGO\r
+#define ADC_EXTERNALTRIG1_T21_CC2 ADC_EXTERNALTRIGCONV_T21_CC2\r
+#define ADC_EXTERNALTRIG2_T2_TRGO ADC_EXTERNALTRIGCONV_T2_TRGO\r
+#define ADC_EXTERNALTRIG3_T2_CC4 ADC_EXTERNALTRIGCONV_T2_CC4\r
+#define ADC_EXTERNALTRIG4_T22_TRGO ADC_EXTERNALTRIGCONV_T22_TRGO\r
+#define ADC_EXTERNALTRIG7_EXT_IT11 ADC_EXTERNALTRIGCONV_EXT_IT11\r
+#define ADC_CLOCK_ASYNC ADC_CLOCK_ASYNC_DIV1\r
+#define ADC_EXTERNALTRIG_EDGE_NONE ADC_EXTERNALTRIGCONVEDGE_NONE\r
+#define ADC_EXTERNALTRIG_EDGE_RISING ADC_EXTERNALTRIGCONVEDGE_RISING\r
+#define ADC_EXTERNALTRIG_EDGE_FALLING ADC_EXTERNALTRIGCONVEDGE_FALLING\r
+#define ADC_EXTERNALTRIG_EDGE_RISINGFALLING ADC_EXTERNALTRIGCONVEDGE_RISINGFALLING\r
+#define ADC_SAMPLETIME_2CYCLE_5 ADC_SAMPLETIME_2CYCLES_5\r
+\r
+#define HAL_ADC_STATE_BUSY_REG HAL_ADC_STATE_REG_BUSY\r
+#define HAL_ADC_STATE_BUSY_INJ HAL_ADC_STATE_INJ_BUSY\r
+#define HAL_ADC_STATE_EOC_REG HAL_ADC_STATE_REG_EOC\r
+#define HAL_ADC_STATE_EOC_INJ HAL_ADC_STATE_INJ_EOC\r
+#define HAL_ADC_STATE_ERROR HAL_ADC_STATE_ERROR_INTERNAL\r
+#define HAL_ADC_STATE_BUSY HAL_ADC_STATE_BUSY_INTERNAL\r
+#define HAL_ADC_STATE_AWD HAL_ADC_STATE_AWD1\r
+\r
+#if defined(STM32H7)\r
+#define ADC_CHANNEL_VBAT_DIV4 ADC_CHANNEL_VBAT\r
+#endif /* STM32H7 */\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup HAL_CEC_Aliased_Defines HAL CEC Aliased Defines maintained for legacy purpose\r
+ * @{\r
+ */\r
+\r
+#define __HAL_CEC_GET_IT __HAL_CEC_GET_FLAG\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup HAL_COMP_Aliased_Defines HAL COMP Aliased Defines maintained for legacy purpose\r
+ * @{\r
+ */\r
+#define COMP_WINDOWMODE_DISABLED COMP_WINDOWMODE_DISABLE\r
+#define COMP_WINDOWMODE_ENABLED COMP_WINDOWMODE_ENABLE\r
+#define COMP_EXTI_LINE_COMP1_EVENT COMP_EXTI_LINE_COMP1\r
+#define COMP_EXTI_LINE_COMP2_EVENT COMP_EXTI_LINE_COMP2\r
+#define COMP_EXTI_LINE_COMP3_EVENT COMP_EXTI_LINE_COMP3\r
+#define COMP_EXTI_LINE_COMP4_EVENT COMP_EXTI_LINE_COMP4\r
+#define COMP_EXTI_LINE_COMP5_EVENT COMP_EXTI_LINE_COMP5\r
+#define COMP_EXTI_LINE_COMP6_EVENT COMP_EXTI_LINE_COMP6\r
+#define COMP_EXTI_LINE_COMP7_EVENT COMP_EXTI_LINE_COMP7\r
+#if defined(STM32L0)\r
+#define COMP_LPTIMCONNECTION_ENABLED ((uint32_t)0x00000003U) /*!< COMPX output generic naming: connected to LPTIM input 1 for COMP1, LPTIM input 2 for COMP2 */\r
+#endif\r
+#define COMP_OUTPUT_COMP6TIM2OCREFCLR COMP_OUTPUT_COMP6_TIM2OCREFCLR\r
+#if defined(STM32F373xC) || defined(STM32F378xx)\r
+#define COMP_OUTPUT_TIM3IC1 COMP_OUTPUT_COMP1_TIM3IC1\r
+#define COMP_OUTPUT_TIM3OCREFCLR COMP_OUTPUT_COMP1_TIM3OCREFCLR\r
+#endif /* STM32F373xC || STM32F378xx */\r
+\r
+#if defined(STM32L0) || defined(STM32L4)\r
+#define COMP_WINDOWMODE_ENABLE COMP_WINDOWMODE_COMP1_INPUT_PLUS_COMMON\r
+\r
+#define COMP_NONINVERTINGINPUT_IO1 COMP_INPUT_PLUS_IO1\r
+#define COMP_NONINVERTINGINPUT_IO2 COMP_INPUT_PLUS_IO2\r
+#define COMP_NONINVERTINGINPUT_IO3 COMP_INPUT_PLUS_IO3\r
+#define COMP_NONINVERTINGINPUT_IO4 COMP_INPUT_PLUS_IO4\r
+#define COMP_NONINVERTINGINPUT_IO5 COMP_INPUT_PLUS_IO5\r
+#define COMP_NONINVERTINGINPUT_IO6 COMP_INPUT_PLUS_IO6\r
+\r
+#define COMP_INVERTINGINPUT_1_4VREFINT COMP_INPUT_MINUS_1_4VREFINT\r
+#define COMP_INVERTINGINPUT_1_2VREFINT COMP_INPUT_MINUS_1_2VREFINT\r
+#define COMP_INVERTINGINPUT_3_4VREFINT COMP_INPUT_MINUS_3_4VREFINT\r
+#define COMP_INVERTINGINPUT_VREFINT COMP_INPUT_MINUS_VREFINT\r
+#define COMP_INVERTINGINPUT_DAC1_CH1 COMP_INPUT_MINUS_DAC1_CH1\r
+#define COMP_INVERTINGINPUT_DAC1_CH2 COMP_INPUT_MINUS_DAC1_CH2\r
+#define COMP_INVERTINGINPUT_DAC1 COMP_INPUT_MINUS_DAC1_CH1\r
+#define COMP_INVERTINGINPUT_DAC2 COMP_INPUT_MINUS_DAC1_CH2\r
+#define COMP_INVERTINGINPUT_IO1 COMP_INPUT_MINUS_IO1\r
+#if defined(STM32L0)\r
+/* Issue fixed on STM32L0 COMP driver: only 2 dedicated IO (IO1 and IO2), */\r
+/* IO2 was wrongly assigned to IO shared with DAC and IO3 was corresponding */\r
+/* to the second dedicated IO (only for COMP2). */\r
+#define COMP_INVERTINGINPUT_IO2 COMP_INPUT_MINUS_DAC1_CH2\r
+#define COMP_INVERTINGINPUT_IO3 COMP_INPUT_MINUS_IO2\r
+#else\r
+#define COMP_INVERTINGINPUT_IO2 COMP_INPUT_MINUS_IO2\r
+#define COMP_INVERTINGINPUT_IO3 COMP_INPUT_MINUS_IO3\r
+#endif\r
+#define COMP_INVERTINGINPUT_IO4 COMP_INPUT_MINUS_IO4\r
+#define COMP_INVERTINGINPUT_IO5 COMP_INPUT_MINUS_IO5\r
+\r
+#define COMP_OUTPUTLEVEL_LOW COMP_OUTPUT_LEVEL_LOW\r
+#define COMP_OUTPUTLEVEL_HIGH COMP_OUTPUT_LEVEL_HIGH\r
+\r
+/* Note: Literal "COMP_FLAG_LOCK" kept for legacy purpose. */\r
+/* To check COMP lock state, use macro "__HAL_COMP_IS_LOCKED()". */\r
+#if defined(COMP_CSR_LOCK)\r
+#define COMP_FLAG_LOCK COMP_CSR_LOCK\r
+#elif defined(COMP_CSR_COMP1LOCK)\r
+#define COMP_FLAG_LOCK COMP_CSR_COMP1LOCK\r
+#elif defined(COMP_CSR_COMPxLOCK)\r
+#define COMP_FLAG_LOCK COMP_CSR_COMPxLOCK\r
+#endif\r
+\r
+#if defined(STM32L4)\r
+#define COMP_BLANKINGSRCE_TIM1OC5 COMP_BLANKINGSRC_TIM1_OC5_COMP1\r
+#define COMP_BLANKINGSRCE_TIM2OC3 COMP_BLANKINGSRC_TIM2_OC3_COMP1\r
+#define COMP_BLANKINGSRCE_TIM3OC3 COMP_BLANKINGSRC_TIM3_OC3_COMP1\r
+#define COMP_BLANKINGSRCE_TIM3OC4 COMP_BLANKINGSRC_TIM3_OC4_COMP2\r
+#define COMP_BLANKINGSRCE_TIM8OC5 COMP_BLANKINGSRC_TIM8_OC5_COMP2\r
+#define COMP_BLANKINGSRCE_TIM15OC1 COMP_BLANKINGSRC_TIM15_OC1_COMP2\r
+#define COMP_BLANKINGSRCE_NONE COMP_BLANKINGSRC_NONE\r
+#endif\r
+\r
+#if defined(STM32L0)\r
+#define COMP_MODE_HIGHSPEED COMP_POWERMODE_MEDIUMSPEED\r
+#define COMP_MODE_LOWSPEED COMP_POWERMODE_ULTRALOWPOWER\r
+#else\r
+#define COMP_MODE_HIGHSPEED COMP_POWERMODE_HIGHSPEED\r
+#define COMP_MODE_MEDIUMSPEED COMP_POWERMODE_MEDIUMSPEED\r
+#define COMP_MODE_LOWPOWER COMP_POWERMODE_LOWPOWER\r
+#define COMP_MODE_ULTRALOWPOWER COMP_POWERMODE_ULTRALOWPOWER\r
+#endif\r
+\r
+#endif\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup HAL_CORTEX_Aliased_Defines HAL CORTEX Aliased Defines maintained for legacy purpose\r
+ * @{\r
+ */\r
+#define __HAL_CORTEX_SYSTICKCLK_CONFIG HAL_SYSTICK_CLKSourceConfig\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup HAL_CRC_Aliased_Defines HAL CRC Aliased Defines maintained for legacy purpose\r
+ * @{\r
+ */\r
+\r
+#define CRC_OUTPUTDATA_INVERSION_DISABLED CRC_OUTPUTDATA_INVERSION_DISABLE\r
+#define CRC_OUTPUTDATA_INVERSION_ENABLED CRC_OUTPUTDATA_INVERSION_ENABLE\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup HAL_DAC_Aliased_Defines HAL DAC Aliased Defines maintained for legacy purpose\r
+ * @{\r
+ */\r
+\r
+#define DAC1_CHANNEL_1 DAC_CHANNEL_1\r
+#define DAC1_CHANNEL_2 DAC_CHANNEL_2\r
+#define DAC2_CHANNEL_1 DAC_CHANNEL_1\r
+#define DAC_WAVE_NONE 0x00000000U\r
+#define DAC_WAVE_NOISE DAC_CR_WAVE1_0\r
+#define DAC_WAVE_TRIANGLE DAC_CR_WAVE1_1\r
+#define DAC_WAVEGENERATION_NONE DAC_WAVE_NONE\r
+#define DAC_WAVEGENERATION_NOISE DAC_WAVE_NOISE\r
+#define DAC_WAVEGENERATION_TRIANGLE DAC_WAVE_TRIANGLE\r
+\r
+#if defined(STM32L1) || defined(STM32L4) || defined(STM32G0)\r
+#define HAL_DAC_MSP_INIT_CB_ID HAL_DAC_MSPINIT_CB_ID\r
+#define HAL_DAC_MSP_DEINIT_CB_ID HAL_DAC_MSPDEINIT_CB_ID\r
+#endif\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup HAL_DMA_Aliased_Defines HAL DMA Aliased Defines maintained for legacy purpose\r
+ * @{\r
+ */\r
+#define HAL_REMAPDMA_ADC_DMA_CH2 DMA_REMAP_ADC_DMA_CH2\r
+#define HAL_REMAPDMA_USART1_TX_DMA_CH4 DMA_REMAP_USART1_TX_DMA_CH4\r
+#define HAL_REMAPDMA_USART1_RX_DMA_CH5 DMA_REMAP_USART1_RX_DMA_CH5\r
+#define HAL_REMAPDMA_TIM16_DMA_CH4 DMA_REMAP_TIM16_DMA_CH4\r
+#define HAL_REMAPDMA_TIM17_DMA_CH2 DMA_REMAP_TIM17_DMA_CH2\r
+#define HAL_REMAPDMA_USART3_DMA_CH32 DMA_REMAP_USART3_DMA_CH32\r
+#define HAL_REMAPDMA_TIM16_DMA_CH6 DMA_REMAP_TIM16_DMA_CH6\r
+#define HAL_REMAPDMA_TIM17_DMA_CH7 DMA_REMAP_TIM17_DMA_CH7\r
+#define HAL_REMAPDMA_SPI2_DMA_CH67 DMA_REMAP_SPI2_DMA_CH67\r
+#define HAL_REMAPDMA_USART2_DMA_CH67 DMA_REMAP_USART2_DMA_CH67\r
+#define HAL_REMAPDMA_I2C1_DMA_CH76 DMA_REMAP_I2C1_DMA_CH76\r
+#define HAL_REMAPDMA_TIM1_DMA_CH6 DMA_REMAP_TIM1_DMA_CH6\r
+#define HAL_REMAPDMA_TIM2_DMA_CH7 DMA_REMAP_TIM2_DMA_CH7\r
+#define HAL_REMAPDMA_TIM3_DMA_CH6 DMA_REMAP_TIM3_DMA_CH6\r
+\r
+#define IS_HAL_REMAPDMA IS_DMA_REMAP\r
+#define __HAL_REMAPDMA_CHANNEL_ENABLE __HAL_DMA_REMAP_CHANNEL_ENABLE\r
+#define __HAL_REMAPDMA_CHANNEL_DISABLE __HAL_DMA_REMAP_CHANNEL_DISABLE\r
+\r
+#if defined(STM32L4)\r
+\r
+#define HAL_DMAMUX1_REQUEST_GEN_EXTI0 HAL_DMAMUX1_REQ_GEN_EXTI0\r
+#define HAL_DMAMUX1_REQUEST_GEN_EXTI1 HAL_DMAMUX1_REQ_GEN_EXTI1\r
+#define HAL_DMAMUX1_REQUEST_GEN_EXTI2 HAL_DMAMUX1_REQ_GEN_EXTI2\r
+#define HAL_DMAMUX1_REQUEST_GEN_EXTI3 HAL_DMAMUX1_REQ_GEN_EXTI3\r
+#define HAL_DMAMUX1_REQUEST_GEN_EXTI4 HAL_DMAMUX1_REQ_GEN_EXTI4\r
+#define HAL_DMAMUX1_REQUEST_GEN_EXTI5 HAL_DMAMUX1_REQ_GEN_EXTI5\r
+#define HAL_DMAMUX1_REQUEST_GEN_EXTI6 HAL_DMAMUX1_REQ_GEN_EXTI6\r
+#define HAL_DMAMUX1_REQUEST_GEN_EXTI7 HAL_DMAMUX1_REQ_GEN_EXTI7\r
+#define HAL_DMAMUX1_REQUEST_GEN_EXTI8 HAL_DMAMUX1_REQ_GEN_EXTI8\r
+#define HAL_DMAMUX1_REQUEST_GEN_EXTI9 HAL_DMAMUX1_REQ_GEN_EXTI9\r
+#define HAL_DMAMUX1_REQUEST_GEN_EXTI10 HAL_DMAMUX1_REQ_GEN_EXTI10\r
+#define HAL_DMAMUX1_REQUEST_GEN_EXTI11 HAL_DMAMUX1_REQ_GEN_EXTI11\r
+#define HAL_DMAMUX1_REQUEST_GEN_EXTI12 HAL_DMAMUX1_REQ_GEN_EXTI12\r
+#define HAL_DMAMUX1_REQUEST_GEN_EXTI13 HAL_DMAMUX1_REQ_GEN_EXTI13\r
+#define HAL_DMAMUX1_REQUEST_GEN_EXTI14 HAL_DMAMUX1_REQ_GEN_EXTI14\r
+#define HAL_DMAMUX1_REQUEST_GEN_EXTI15 HAL_DMAMUX1_REQ_GEN_EXTI15\r
+#define HAL_DMAMUX1_REQUEST_GEN_DMAMUX1_CH0_EVT HAL_DMAMUX1_REQ_GEN_DMAMUX1_CH0_EVT\r
+#define HAL_DMAMUX1_REQUEST_GEN_DMAMUX1_CH1_EVT HAL_DMAMUX1_REQ_GEN_DMAMUX1_CH1_EVT\r
+#define HAL_DMAMUX1_REQUEST_GEN_DMAMUX1_CH2_EVT HAL_DMAMUX1_REQ_GEN_DMAMUX1_CH2_EVT\r
+#define HAL_DMAMUX1_REQUEST_GEN_DMAMUX1_CH3_EVT HAL_DMAMUX1_REQ_GEN_DMAMUX1_CH3_EVT\r
+#define HAL_DMAMUX1_REQUEST_GEN_LPTIM1_OUT HAL_DMAMUX1_REQ_GEN_LPTIM1_OUT\r
+#define HAL_DMAMUX1_REQUEST_GEN_LPTIM2_OUT HAL_DMAMUX1_REQ_GEN_LPTIM2_OUT\r
+#define HAL_DMAMUX1_REQUEST_GEN_DSI_TE HAL_DMAMUX1_REQ_GEN_DSI_TE\r
+#define HAL_DMAMUX1_REQUEST_GEN_DSI_EOT HAL_DMAMUX1_REQ_GEN_DSI_EOT\r
+#define HAL_DMAMUX1_REQUEST_GEN_DMA2D_EOT HAL_DMAMUX1_REQ_GEN_DMA2D_EOT\r
+#define HAL_DMAMUX1_REQUEST_GEN_LTDC_IT HAL_DMAMUX1_REQ_GEN_LTDC_IT\r
+\r
+#define HAL_DMAMUX_REQUEST_GEN_NO_EVENT HAL_DMAMUX_REQ_GEN_NO_EVENT\r
+#define HAL_DMAMUX_REQUEST_GEN_RISING HAL_DMAMUX_REQ_GEN_RISING\r
+#define HAL_DMAMUX_REQUEST_GEN_FALLING HAL_DMAMUX_REQ_GEN_FALLING\r
+#define HAL_DMAMUX_REQUEST_GEN_RISING_FALLING HAL_DMAMUX_REQ_GEN_RISING_FALLING\r
+\r
+#endif /* STM32L4 */\r
+\r
+#if defined(STM32H7)\r
+\r
+#define DMA_REQUEST_DAC1 DMA_REQUEST_DAC1_CH1\r
+#define DMA_REQUEST_DAC2 DMA_REQUEST_DAC1_CH2\r
+\r
+#define BDMA_REQUEST_LP_UART1_RX BDMA_REQUEST_LPUART1_RX\r
+#define BDMA_REQUEST_LP_UART1_TX BDMA_REQUEST_LPUART1_TX\r
+\r
+#define HAL_DMAMUX1_REQUEST_GEN_DMAMUX1_CH0_EVT HAL_DMAMUX1_REQ_GEN_DMAMUX1_CH0_EVT\r
+#define HAL_DMAMUX1_REQUEST_GEN_DMAMUX1_CH1_EVT HAL_DMAMUX1_REQ_GEN_DMAMUX1_CH1_EVT\r
+#define HAL_DMAMUX1_REQUEST_GEN_DMAMUX1_CH2_EVT HAL_DMAMUX1_REQ_GEN_DMAMUX1_CH2_EVT\r
+#define HAL_DMAMUX1_REQUEST_GEN_LPTIM1_OUT HAL_DMAMUX1_REQ_GEN_LPTIM1_OUT\r
+#define HAL_DMAMUX1_REQUEST_GEN_LPTIM2_OUT HAL_DMAMUX1_REQ_GEN_LPTIM2_OUT\r
+#define HAL_DMAMUX1_REQUEST_GEN_LPTIM3_OUT HAL_DMAMUX1_REQ_GEN_LPTIM3_OUT\r
+#define HAL_DMAMUX1_REQUEST_GEN_EXTI0 HAL_DMAMUX1_REQ_GEN_EXTI0\r
+#define HAL_DMAMUX1_REQUEST_GEN_TIM12_TRGO HAL_DMAMUX1_REQ_GEN_TIM12_TRGO\r
+\r
+#define HAL_DMAMUX2_REQUEST_GEN_DMAMUX2_CH0_EVT HAL_DMAMUX2_REQ_GEN_DMAMUX2_CH0_EVT\r
+#define HAL_DMAMUX2_REQUEST_GEN_DMAMUX2_CH1_EVT HAL_DMAMUX2_REQ_GEN_DMAMUX2_CH1_EVT\r
+#define HAL_DMAMUX2_REQUEST_GEN_DMAMUX2_CH2_EVT HAL_DMAMUX2_REQ_GEN_DMAMUX2_CH2_EVT\r
+#define HAL_DMAMUX2_REQUEST_GEN_DMAMUX2_CH3_EVT HAL_DMAMUX2_REQ_GEN_DMAMUX2_CH3_EVT\r
+#define HAL_DMAMUX2_REQUEST_GEN_DMAMUX2_CH4_EVT HAL_DMAMUX2_REQ_GEN_DMAMUX2_CH4_EVT\r
+#define HAL_DMAMUX2_REQUEST_GEN_DMAMUX2_CH5_EVT HAL_DMAMUX2_REQ_GEN_DMAMUX2_CH5_EVT\r
+#define HAL_DMAMUX2_REQUEST_GEN_DMAMUX2_CH6_EVT HAL_DMAMUX2_REQ_GEN_DMAMUX2_CH6_EVT\r
+#define HAL_DMAMUX2_REQUEST_GEN_LPUART1_RX_WKUP HAL_DMAMUX2_REQ_GEN_LPUART1_RX_WKUP\r
+#define HAL_DMAMUX2_REQUEST_GEN_LPUART1_TX_WKUP HAL_DMAMUX2_REQ_GEN_LPUART1_TX_WKUP\r
+#define HAL_DMAMUX2_REQUEST_GEN_LPTIM2_WKUP HAL_DMAMUX2_REQ_GEN_LPTIM2_WKUP\r
+#define HAL_DMAMUX2_REQUEST_GEN_LPTIM2_OUT HAL_DMAMUX2_REQ_GEN_LPTIM2_OUT\r
+#define HAL_DMAMUX2_REQUEST_GEN_LPTIM3_WKUP HAL_DMAMUX2_REQ_GEN_LPTIM3_WKUP\r
+#define HAL_DMAMUX2_REQUEST_GEN_LPTIM3_OUT HAL_DMAMUX2_REQ_GEN_LPTIM3_OUT\r
+#define HAL_DMAMUX2_REQUEST_GEN_LPTIM4_WKUP HAL_DMAMUX2_REQ_GEN_LPTIM4_WKUP\r
+#define HAL_DMAMUX2_REQUEST_GEN_LPTIM5_WKUP HAL_DMAMUX2_REQ_GEN_LPTIM5_WKUP\r
+#define HAL_DMAMUX2_REQUEST_GEN_I2C4_WKUP HAL_DMAMUX2_REQ_GEN_I2C4_WKUP\r
+#define HAL_DMAMUX2_REQUEST_GEN_SPI6_WKUP HAL_DMAMUX2_REQ_GEN_SPI6_WKUP\r
+#define HAL_DMAMUX2_REQUEST_GEN_COMP1_OUT HAL_DMAMUX2_REQ_GEN_COMP1_OUT\r
+#define HAL_DMAMUX2_REQUEST_GEN_COMP2_OUT HAL_DMAMUX2_REQ_GEN_COMP2_OUT\r
+#define HAL_DMAMUX2_REQUEST_GEN_RTC_WKUP HAL_DMAMUX2_REQ_GEN_RTC_WKUP\r
+#define HAL_DMAMUX2_REQUEST_GEN_EXTI0 HAL_DMAMUX2_REQ_GEN_EXTI0\r
+#define HAL_DMAMUX2_REQUEST_GEN_EXTI2 HAL_DMAMUX2_REQ_GEN_EXTI2\r
+#define HAL_DMAMUX2_REQUEST_GEN_I2C4_IT_EVT HAL_DMAMUX2_REQ_GEN_I2C4_IT_EVT\r
+#define HAL_DMAMUX2_REQUEST_GEN_SPI6_IT HAL_DMAMUX2_REQ_GEN_SPI6_IT\r
+#define HAL_DMAMUX2_REQUEST_GEN_LPUART1_TX_IT HAL_DMAMUX2_REQ_GEN_LPUART1_TX_IT\r
+#define HAL_DMAMUX2_REQUEST_GEN_LPUART1_RX_IT HAL_DMAMUX2_REQ_GEN_LPUART1_RX_IT\r
+#define HAL_DMAMUX2_REQUEST_GEN_ADC3_IT HAL_DMAMUX2_REQ_GEN_ADC3_IT\r
+#define HAL_DMAMUX2_REQUEST_GEN_ADC3_AWD1_OUT HAL_DMAMUX2_REQ_GEN_ADC3_AWD1_OUT\r
+#define HAL_DMAMUX2_REQUEST_GEN_BDMA_CH0_IT HAL_DMAMUX2_REQ_GEN_BDMA_CH0_IT\r
+#define HAL_DMAMUX2_REQUEST_GEN_BDMA_CH1_IT HAL_DMAMUX2_REQ_GEN_BDMA_CH1_IT\r
+\r
+#define HAL_DMAMUX_REQUEST_GEN_NO_EVENT HAL_DMAMUX_REQ_GEN_NO_EVENT\r
+#define HAL_DMAMUX_REQUEST_GEN_RISING HAL_DMAMUX_REQ_GEN_RISING\r
+#define HAL_DMAMUX_REQUEST_GEN_FALLING HAL_DMAMUX_REQ_GEN_FALLING\r
+#define HAL_DMAMUX_REQUEST_GEN_RISING_FALLING HAL_DMAMUX_REQ_GEN_RISING_FALLING\r
+\r
+#define DFSDM_FILTER_EXT_TRIG_LPTIM1 DFSDM_FILTER_EXT_TRIG_LPTIM1_OUT\r
+#define DFSDM_FILTER_EXT_TRIG_LPTIM2 DFSDM_FILTER_EXT_TRIG_LPTIM2_OUT\r
+#define DFSDM_FILTER_EXT_TRIG_LPTIM3 DFSDM_FILTER_EXT_TRIG_LPTIM3_OUT\r
+\r
+#endif /* STM32H7 */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup HAL_FLASH_Aliased_Defines HAL FLASH Aliased Defines maintained for legacy purpose\r
+ * @{\r
+ */\r
+\r
+#define TYPEPROGRAM_BYTE FLASH_TYPEPROGRAM_BYTE\r
+#define TYPEPROGRAM_HALFWORD FLASH_TYPEPROGRAM_HALFWORD\r
+#define TYPEPROGRAM_WORD FLASH_TYPEPROGRAM_WORD\r
+#define TYPEPROGRAM_DOUBLEWORD FLASH_TYPEPROGRAM_DOUBLEWORD\r
+#define TYPEERASE_SECTORS FLASH_TYPEERASE_SECTORS\r
+#define TYPEERASE_PAGES FLASH_TYPEERASE_PAGES\r
+#define TYPEERASE_PAGEERASE FLASH_TYPEERASE_PAGES\r
+#define TYPEERASE_MASSERASE FLASH_TYPEERASE_MASSERASE\r
+#define WRPSTATE_DISABLE OB_WRPSTATE_DISABLE\r
+#define WRPSTATE_ENABLE OB_WRPSTATE_ENABLE\r
+#define HAL_FLASH_TIMEOUT_VALUE FLASH_TIMEOUT_VALUE\r
+#define OBEX_PCROP OPTIONBYTE_PCROP\r
+#define OBEX_BOOTCONFIG OPTIONBYTE_BOOTCONFIG\r
+#define PCROPSTATE_DISABLE OB_PCROP_STATE_DISABLE\r
+#define PCROPSTATE_ENABLE OB_PCROP_STATE_ENABLE\r
+#define TYPEERASEDATA_BYTE FLASH_TYPEERASEDATA_BYTE\r
+#define TYPEERASEDATA_HALFWORD FLASH_TYPEERASEDATA_HALFWORD\r
+#define TYPEERASEDATA_WORD FLASH_TYPEERASEDATA_WORD\r
+#define TYPEPROGRAMDATA_BYTE FLASH_TYPEPROGRAMDATA_BYTE\r
+#define TYPEPROGRAMDATA_HALFWORD FLASH_TYPEPROGRAMDATA_HALFWORD\r
+#define TYPEPROGRAMDATA_WORD FLASH_TYPEPROGRAMDATA_WORD\r
+#define TYPEPROGRAMDATA_FASTBYTE FLASH_TYPEPROGRAMDATA_FASTBYTE\r
+#define TYPEPROGRAMDATA_FASTHALFWORD FLASH_TYPEPROGRAMDATA_FASTHALFWORD\r
+#define TYPEPROGRAMDATA_FASTWORD FLASH_TYPEPROGRAMDATA_FASTWORD\r
+#define PAGESIZE FLASH_PAGE_SIZE\r
+#define TYPEPROGRAM_FASTBYTE FLASH_TYPEPROGRAM_BYTE\r
+#define TYPEPROGRAM_FASTHALFWORD FLASH_TYPEPROGRAM_HALFWORD\r
+#define TYPEPROGRAM_FASTWORD FLASH_TYPEPROGRAM_WORD\r
+#define VOLTAGE_RANGE_1 FLASH_VOLTAGE_RANGE_1\r
+#define VOLTAGE_RANGE_2 FLASH_VOLTAGE_RANGE_2\r
+#define VOLTAGE_RANGE_3 FLASH_VOLTAGE_RANGE_3\r
+#define VOLTAGE_RANGE_4 FLASH_VOLTAGE_RANGE_4\r
+#define TYPEPROGRAM_FAST FLASH_TYPEPROGRAM_FAST\r
+#define TYPEPROGRAM_FAST_AND_LAST FLASH_TYPEPROGRAM_FAST_AND_LAST\r
+#define WRPAREA_BANK1_AREAA OB_WRPAREA_BANK1_AREAA\r
+#define WRPAREA_BANK1_AREAB OB_WRPAREA_BANK1_AREAB\r
+#define WRPAREA_BANK2_AREAA OB_WRPAREA_BANK2_AREAA\r
+#define WRPAREA_BANK2_AREAB OB_WRPAREA_BANK2_AREAB\r
+#define IWDG_STDBY_FREEZE OB_IWDG_STDBY_FREEZE\r
+#define IWDG_STDBY_ACTIVE OB_IWDG_STDBY_RUN\r
+#define IWDG_STOP_FREEZE OB_IWDG_STOP_FREEZE\r
+#define IWDG_STOP_ACTIVE OB_IWDG_STOP_RUN\r
+#define FLASH_ERROR_NONE HAL_FLASH_ERROR_NONE\r
+#define FLASH_ERROR_RD HAL_FLASH_ERROR_RD\r
+#define FLASH_ERROR_PG HAL_FLASH_ERROR_PROG\r
+#define FLASH_ERROR_PGP HAL_FLASH_ERROR_PGS\r
+#define FLASH_ERROR_WRP HAL_FLASH_ERROR_WRP\r
+#define FLASH_ERROR_OPTV HAL_FLASH_ERROR_OPTV\r
+#define FLASH_ERROR_OPTVUSR HAL_FLASH_ERROR_OPTVUSR\r
+#define FLASH_ERROR_PROG HAL_FLASH_ERROR_PROG\r
+#define FLASH_ERROR_OP HAL_FLASH_ERROR_OPERATION\r
+#define FLASH_ERROR_PGA HAL_FLASH_ERROR_PGA\r
+#define FLASH_ERROR_SIZE HAL_FLASH_ERROR_SIZE\r
+#define FLASH_ERROR_SIZ HAL_FLASH_ERROR_SIZE\r
+#define FLASH_ERROR_PGS HAL_FLASH_ERROR_PGS\r
+#define FLASH_ERROR_MIS HAL_FLASH_ERROR_MIS\r
+#define FLASH_ERROR_FAST HAL_FLASH_ERROR_FAST\r
+#define FLASH_ERROR_FWWERR HAL_FLASH_ERROR_FWWERR\r
+#define FLASH_ERROR_NOTZERO HAL_FLASH_ERROR_NOTZERO\r
+#define FLASH_ERROR_OPERATION HAL_FLASH_ERROR_OPERATION\r
+#define FLASH_ERROR_ERS HAL_FLASH_ERROR_ERS\r
+#define OB_WDG_SW OB_IWDG_SW\r
+#define OB_WDG_HW OB_IWDG_HW\r
+#define OB_SDADC12_VDD_MONITOR_SET OB_SDACD_VDD_MONITOR_SET\r
+#define OB_SDADC12_VDD_MONITOR_RESET OB_SDACD_VDD_MONITOR_RESET\r
+#define OB_RAM_PARITY_CHECK_SET OB_SRAM_PARITY_SET\r
+#define OB_RAM_PARITY_CHECK_RESET OB_SRAM_PARITY_RESET\r
+#define IS_OB_SDADC12_VDD_MONITOR IS_OB_SDACD_VDD_MONITOR\r
+#define OB_RDP_LEVEL0 OB_RDP_LEVEL_0\r
+#define OB_RDP_LEVEL1 OB_RDP_LEVEL_1\r
+#define OB_RDP_LEVEL2 OB_RDP_LEVEL_2\r
+#if defined(STM32G0)\r
+#define OB_BOOT_LOCK_DISABLE OB_BOOT_ENTRY_FORCED_NONE\r
+#define OB_BOOT_LOCK_ENABLE OB_BOOT_ENTRY_FORCED_FLASH\r
+#else\r
+#define OB_BOOT_ENTRY_FORCED_NONE OB_BOOT_LOCK_DISABLE\r
+#define OB_BOOT_ENTRY_FORCED_FLASH OB_BOOT_LOCK_ENABLE\r
+#endif\r
+#if defined(STM32H7)\r
+#define FLASH_FLAG_SNECCE_BANK1RR FLASH_FLAG_SNECCERR_BANK1\r
+#define FLASH_FLAG_DBECCE_BANK1RR FLASH_FLAG_DBECCERR_BANK1\r
+#define FLASH_FLAG_STRBER_BANK1R FLASH_FLAG_STRBERR_BANK1\r
+#define FLASH_FLAG_SNECCE_BANK2RR FLASH_FLAG_SNECCERR_BANK2\r
+#define FLASH_FLAG_DBECCE_BANK2RR FLASH_FLAG_DBECCERR_BANK2\r
+#define FLASH_FLAG_STRBER_BANK2R FLASH_FLAG_STRBERR_BANK2\r
+#endif\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup HAL_JPEG_Aliased_Macros HAL JPEG Aliased Macros maintained for legacy purpose\r
+ * @{\r
+ */\r
+\r
+#if defined(STM32H7)\r
+#define __HAL_RCC_JPEG_CLK_ENABLE __HAL_RCC_JPGDECEN_CLK_ENABLE\r
+#define __HAL_RCC_JPEG_CLK_DISABLE __HAL_RCC_JPGDECEN_CLK_DISABLE\r
+#define __HAL_RCC_JPEG_FORCE_RESET __HAL_RCC_JPGDECRST_FORCE_RESET\r
+#define __HAL_RCC_JPEG_RELEASE_RESET __HAL_RCC_JPGDECRST_RELEASE_RESET\r
+#define __HAL_RCC_JPEG_CLK_SLEEP_ENABLE __HAL_RCC_JPGDEC_CLK_SLEEP_ENABLE\r
+#define __HAL_RCC_JPEG_CLK_SLEEP_DISABLE __HAL_RCC_JPGDEC_CLK_SLEEP_DISABLE\r
+#endif /* STM32H7 */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup HAL_SYSCFG_Aliased_Defines HAL SYSCFG Aliased Defines maintained for legacy purpose\r
+ * @{\r
+ */\r
+\r
+#define HAL_SYSCFG_FASTMODEPLUS_I2C_PA9 I2C_FASTMODEPLUS_PA9\r
+#define HAL_SYSCFG_FASTMODEPLUS_I2C_PA10 I2C_FASTMODEPLUS_PA10\r
+#define HAL_SYSCFG_FASTMODEPLUS_I2C_PB6 I2C_FASTMODEPLUS_PB6\r
+#define HAL_SYSCFG_FASTMODEPLUS_I2C_PB7 I2C_FASTMODEPLUS_PB7\r
+#define HAL_SYSCFG_FASTMODEPLUS_I2C_PB8 I2C_FASTMODEPLUS_PB8\r
+#define HAL_SYSCFG_FASTMODEPLUS_I2C_PB9 I2C_FASTMODEPLUS_PB9\r
+#define HAL_SYSCFG_FASTMODEPLUS_I2C1 I2C_FASTMODEPLUS_I2C1\r
+#define HAL_SYSCFG_FASTMODEPLUS_I2C2 I2C_FASTMODEPLUS_I2C2\r
+#define HAL_SYSCFG_FASTMODEPLUS_I2C3 I2C_FASTMODEPLUS_I2C3\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+\r
+/** @defgroup LL_FMC_Aliased_Defines LL FMC Aliased Defines maintained for compatibility purpose\r
+ * @{\r
+ */\r
+#if defined(STM32L4) || defined(STM32F7) || defined(STM32H7)\r
+#define FMC_NAND_PCC_WAIT_FEATURE_DISABLE FMC_NAND_WAIT_FEATURE_DISABLE\r
+#define FMC_NAND_PCC_WAIT_FEATURE_ENABLE FMC_NAND_WAIT_FEATURE_ENABLE\r
+#define FMC_NAND_PCC_MEM_BUS_WIDTH_8 FMC_NAND_MEM_BUS_WIDTH_8\r
+#define FMC_NAND_PCC_MEM_BUS_WIDTH_16 FMC_NAND_MEM_BUS_WIDTH_16\r
+#elif defined(STM32F1) || defined(STM32F2) || defined(STM32F3) || defined(STM32F4)\r
+#define FMC_NAND_WAIT_FEATURE_DISABLE FMC_NAND_PCC_WAIT_FEATURE_DISABLE\r
+#define FMC_NAND_WAIT_FEATURE_ENABLE FMC_NAND_PCC_WAIT_FEATURE_ENABLE\r
+#define FMC_NAND_MEM_BUS_WIDTH_8 FMC_NAND_PCC_MEM_BUS_WIDTH_8\r
+#define FMC_NAND_MEM_BUS_WIDTH_16 FMC_NAND_PCC_MEM_BUS_WIDTH_16\r
+#endif\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup LL_FSMC_Aliased_Defines LL FSMC Aliased Defines maintained for legacy purpose\r
+ * @{\r
+ */\r
+\r
+#define FSMC_NORSRAM_TYPEDEF FSMC_NORSRAM_TypeDef\r
+#define FSMC_NORSRAM_EXTENDED_TYPEDEF FSMC_NORSRAM_EXTENDED_TypeDef\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup HAL_GPIO_Aliased_Macros HAL GPIO Aliased Macros maintained for legacy purpose\r
+ * @{\r
+ */\r
+#define GET_GPIO_SOURCE GPIO_GET_INDEX\r
+#define GET_GPIO_INDEX GPIO_GET_INDEX\r
+\r
+#if defined(STM32F4)\r
+#define GPIO_AF12_SDMMC GPIO_AF12_SDIO\r
+#define GPIO_AF12_SDMMC1 GPIO_AF12_SDIO\r
+#endif\r
+\r
+#if defined(STM32F7)\r
+#define GPIO_AF12_SDIO GPIO_AF12_SDMMC1\r
+#define GPIO_AF12_SDMMC GPIO_AF12_SDMMC1\r
+#endif\r
+\r
+#if defined(STM32L4)\r
+#define GPIO_AF12_SDIO GPIO_AF12_SDMMC1\r
+#define GPIO_AF12_SDMMC GPIO_AF12_SDMMC1\r
+#endif\r
+\r
+#if defined(STM32H7)\r
+#define GPIO_AF7_SDIO1 GPIO_AF7_SDMMC1\r
+#define GPIO_AF8_SDIO1 GPIO_AF8_SDMMC1\r
+#define GPIO_AF12_SDIO1 GPIO_AF12_SDMMC1\r
+#define GPIO_AF9_SDIO2 GPIO_AF9_SDMMC2\r
+#define GPIO_AF10_SDIO2 GPIO_AF10_SDMMC2\r
+#define GPIO_AF11_SDIO2 GPIO_AF11_SDMMC2\r
+#endif\r
+\r
+#define GPIO_AF0_LPTIM GPIO_AF0_LPTIM1\r
+#define GPIO_AF1_LPTIM GPIO_AF1_LPTIM1\r
+#define GPIO_AF2_LPTIM GPIO_AF2_LPTIM1\r
+\r
+#if defined(STM32L0) || defined(STM32L4) || defined(STM32F4) || defined(STM32F2) || defined(STM32F7) || defined(STM32H7)\r
+#define GPIO_SPEED_LOW GPIO_SPEED_FREQ_LOW\r
+#define GPIO_SPEED_MEDIUM GPIO_SPEED_FREQ_MEDIUM\r
+#define GPIO_SPEED_FAST GPIO_SPEED_FREQ_HIGH\r
+#define GPIO_SPEED_HIGH GPIO_SPEED_FREQ_VERY_HIGH\r
+#endif /* STM32L0 || STM32L4 || STM32F4 || STM32F2 || STM32F7 || STM32H7*/\r
+\r
+#if defined(STM32L1)\r
+ #define GPIO_SPEED_VERY_LOW GPIO_SPEED_FREQ_LOW\r
+ #define GPIO_SPEED_LOW GPIO_SPEED_FREQ_MEDIUM\r
+ #define GPIO_SPEED_MEDIUM GPIO_SPEED_FREQ_HIGH\r
+ #define GPIO_SPEED_HIGH GPIO_SPEED_FREQ_VERY_HIGH\r
+#endif /* STM32L1 */\r
+\r
+#if defined(STM32F0) || defined(STM32F3) || defined(STM32F1)\r
+ #define GPIO_SPEED_LOW GPIO_SPEED_FREQ_LOW\r
+ #define GPIO_SPEED_MEDIUM GPIO_SPEED_FREQ_MEDIUM\r
+ #define GPIO_SPEED_HIGH GPIO_SPEED_FREQ_HIGH\r
+#endif /* STM32F0 || STM32F3 || STM32F1 */\r
+\r
+#define GPIO_AF6_DFSDM GPIO_AF6_DFSDM1\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup HAL_HRTIM_Aliased_Macros HAL HRTIM Aliased Macros maintained for legacy purpose\r
+ * @{\r
+ */\r
+#define HRTIM_TIMDELAYEDPROTECTION_DISABLED HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DISABLED\r
+#define HRTIM_TIMDELAYEDPROTECTION_DELAYEDOUT1_EEV68 HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DELAYEDOUT1_EEV6\r
+#define HRTIM_TIMDELAYEDPROTECTION_DELAYEDOUT2_EEV68 HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DELAYEDOUT2_EEV6\r
+#define HRTIM_TIMDELAYEDPROTECTION_DELAYEDBOTH_EEV68 HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DELAYEDBOTH_EEV6\r
+#define HRTIM_TIMDELAYEDPROTECTION_BALANCED_EEV68 HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_BALANCED_EEV6\r
+#define HRTIM_TIMDELAYEDPROTECTION_DELAYEDOUT1_DEEV79 HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DELAYEDOUT1_DEEV7\r
+#define HRTIM_TIMDELAYEDPROTECTION_DELAYEDOUT2_DEEV79 HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DELAYEDOUT2_DEEV7\r
+#define HRTIM_TIMDELAYEDPROTECTION_DELAYEDBOTH_EEV79 HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DELAYEDBOTH_EEV7\r
+#define HRTIM_TIMDELAYEDPROTECTION_BALANCED_EEV79 HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_BALANCED_EEV7\r
+\r
+#define __HAL_HRTIM_SetCounter __HAL_HRTIM_SETCOUNTER\r
+#define __HAL_HRTIM_GetCounter __HAL_HRTIM_GETCOUNTER\r
+#define __HAL_HRTIM_SetPeriod __HAL_HRTIM_SETPERIOD\r
+#define __HAL_HRTIM_GetPeriod __HAL_HRTIM_GETPERIOD\r
+#define __HAL_HRTIM_SetClockPrescaler __HAL_HRTIM_SETCLOCKPRESCALER\r
+#define __HAL_HRTIM_GetClockPrescaler __HAL_HRTIM_GETCLOCKPRESCALER\r
+#define __HAL_HRTIM_SetCompare __HAL_HRTIM_SETCOMPARE\r
+#define __HAL_HRTIM_GetCompare __HAL_HRTIM_GETCOMPARE\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup HAL_I2C_Aliased_Defines HAL I2C Aliased Defines maintained for legacy purpose\r
+ * @{\r
+ */\r
+#define I2C_DUALADDRESS_DISABLED I2C_DUALADDRESS_DISABLE\r
+#define I2C_DUALADDRESS_ENABLED I2C_DUALADDRESS_ENABLE\r
+#define I2C_GENERALCALL_DISABLED I2C_GENERALCALL_DISABLE\r
+#define I2C_GENERALCALL_ENABLED I2C_GENERALCALL_ENABLE\r
+#define I2C_NOSTRETCH_DISABLED I2C_NOSTRETCH_DISABLE\r
+#define I2C_NOSTRETCH_ENABLED I2C_NOSTRETCH_ENABLE\r
+#define I2C_ANALOGFILTER_ENABLED I2C_ANALOGFILTER_ENABLE\r
+#define I2C_ANALOGFILTER_DISABLED I2C_ANALOGFILTER_DISABLE\r
+#if defined(STM32F0) || defined(STM32F1) || defined(STM32F3) || defined(STM32G0) || defined(STM32L4) || defined(STM32L1) || defined(STM32F7)\r
+#define HAL_I2C_STATE_MEM_BUSY_TX HAL_I2C_STATE_BUSY_TX\r
+#define HAL_I2C_STATE_MEM_BUSY_RX HAL_I2C_STATE_BUSY_RX\r
+#define HAL_I2C_STATE_MASTER_BUSY_TX HAL_I2C_STATE_BUSY_TX\r
+#define HAL_I2C_STATE_MASTER_BUSY_RX HAL_I2C_STATE_BUSY_RX\r
+#define HAL_I2C_STATE_SLAVE_BUSY_TX HAL_I2C_STATE_BUSY_TX\r
+#define HAL_I2C_STATE_SLAVE_BUSY_RX HAL_I2C_STATE_BUSY_RX\r
+#endif\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup HAL_IRDA_Aliased_Defines HAL IRDA Aliased Defines maintained for legacy purpose\r
+ * @{\r
+ */\r
+#define IRDA_ONE_BIT_SAMPLE_DISABLED IRDA_ONE_BIT_SAMPLE_DISABLE\r
+#define IRDA_ONE_BIT_SAMPLE_ENABLED IRDA_ONE_BIT_SAMPLE_ENABLE\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup HAL_IWDG_Aliased_Defines HAL IWDG Aliased Defines maintained for legacy purpose\r
+ * @{\r
+ */\r
+#define KR_KEY_RELOAD IWDG_KEY_RELOAD\r
+#define KR_KEY_ENABLE IWDG_KEY_ENABLE\r
+#define KR_KEY_EWA IWDG_KEY_WRITE_ACCESS_ENABLE\r
+#define KR_KEY_DWA IWDG_KEY_WRITE_ACCESS_DISABLE\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup HAL_LPTIM_Aliased_Defines HAL LPTIM Aliased Defines maintained for legacy purpose\r
+ * @{\r
+ */\r
+\r
+#define LPTIM_CLOCKSAMPLETIME_DIRECTTRANSISTION LPTIM_CLOCKSAMPLETIME_DIRECTTRANSITION\r
+#define LPTIM_CLOCKSAMPLETIME_2TRANSISTIONS LPTIM_CLOCKSAMPLETIME_2TRANSITIONS\r
+#define LPTIM_CLOCKSAMPLETIME_4TRANSISTIONS LPTIM_CLOCKSAMPLETIME_4TRANSITIONS\r
+#define LPTIM_CLOCKSAMPLETIME_8TRANSISTIONS LPTIM_CLOCKSAMPLETIME_8TRANSITIONS\r
+\r
+#define LPTIM_CLOCKPOLARITY_RISINGEDGE LPTIM_CLOCKPOLARITY_RISING\r
+#define LPTIM_CLOCKPOLARITY_FALLINGEDGE LPTIM_CLOCKPOLARITY_FALLING\r
+#define LPTIM_CLOCKPOLARITY_BOTHEDGES LPTIM_CLOCKPOLARITY_RISING_FALLING\r
+\r
+#define LPTIM_TRIGSAMPLETIME_DIRECTTRANSISTION LPTIM_TRIGSAMPLETIME_DIRECTTRANSITION\r
+#define LPTIM_TRIGSAMPLETIME_2TRANSISTIONS LPTIM_TRIGSAMPLETIME_2TRANSITIONS\r
+#define LPTIM_TRIGSAMPLETIME_4TRANSISTIONS LPTIM_TRIGSAMPLETIME_4TRANSITIONS\r
+#define LPTIM_TRIGSAMPLETIME_8TRANSISTIONS LPTIM_TRIGSAMPLETIME_8TRANSITIONS\r
+\r
+/* The following 3 definition have also been present in a temporary version of lptim.h */\r
+/* They need to be renamed also to the right name, just in case */\r
+#define LPTIM_TRIGSAMPLETIME_2TRANSITION LPTIM_TRIGSAMPLETIME_2TRANSITIONS\r
+#define LPTIM_TRIGSAMPLETIME_4TRANSITION LPTIM_TRIGSAMPLETIME_4TRANSITIONS\r
+#define LPTIM_TRIGSAMPLETIME_8TRANSITION LPTIM_TRIGSAMPLETIME_8TRANSITIONS\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup HAL_NAND_Aliased_Defines HAL NAND Aliased Defines maintained for legacy purpose\r
+ * @{\r
+ */\r
+#define HAL_NAND_Read_Page HAL_NAND_Read_Page_8b\r
+#define HAL_NAND_Write_Page HAL_NAND_Write_Page_8b\r
+#define HAL_NAND_Read_SpareArea HAL_NAND_Read_SpareArea_8b\r
+#define HAL_NAND_Write_SpareArea HAL_NAND_Write_SpareArea_8b\r
+\r
+#define NAND_AddressTypedef NAND_AddressTypeDef\r
+\r
+#define __ARRAY_ADDRESS ARRAY_ADDRESS\r
+#define __ADDR_1st_CYCLE ADDR_1ST_CYCLE\r
+#define __ADDR_2nd_CYCLE ADDR_2ND_CYCLE\r
+#define __ADDR_3rd_CYCLE ADDR_3RD_CYCLE\r
+#define __ADDR_4th_CYCLE ADDR_4TH_CYCLE\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup HAL_NOR_Aliased_Defines HAL NOR Aliased Defines maintained for legacy purpose\r
+ * @{\r
+ */\r
+#define NOR_StatusTypedef HAL_NOR_StatusTypeDef\r
+#define NOR_SUCCESS HAL_NOR_STATUS_SUCCESS\r
+#define NOR_ONGOING HAL_NOR_STATUS_ONGOING\r
+#define NOR_ERROR HAL_NOR_STATUS_ERROR\r
+#define NOR_TIMEOUT HAL_NOR_STATUS_TIMEOUT\r
+\r
+#define __NOR_WRITE NOR_WRITE\r
+#define __NOR_ADDR_SHIFT NOR_ADDR_SHIFT\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup HAL_OPAMP_Aliased_Defines HAL OPAMP Aliased Defines maintained for legacy purpose\r
+ * @{\r
+ */\r
+\r
+#define OPAMP_NONINVERTINGINPUT_VP0 OPAMP_NONINVERTINGINPUT_IO0\r
+#define OPAMP_NONINVERTINGINPUT_VP1 OPAMP_NONINVERTINGINPUT_IO1\r
+#define OPAMP_NONINVERTINGINPUT_VP2 OPAMP_NONINVERTINGINPUT_IO2\r
+#define OPAMP_NONINVERTINGINPUT_VP3 OPAMP_NONINVERTINGINPUT_IO3\r
+\r
+#define OPAMP_SEC_NONINVERTINGINPUT_VP0 OPAMP_SEC_NONINVERTINGINPUT_IO0\r
+#define OPAMP_SEC_NONINVERTINGINPUT_VP1 OPAMP_SEC_NONINVERTINGINPUT_IO1\r
+#define OPAMP_SEC_NONINVERTINGINPUT_VP2 OPAMP_SEC_NONINVERTINGINPUT_IO2\r
+#define OPAMP_SEC_NONINVERTINGINPUT_VP3 OPAMP_SEC_NONINVERTINGINPUT_IO3\r
+\r
+#define OPAMP_INVERTINGINPUT_VM0 OPAMP_INVERTINGINPUT_IO0\r
+#define OPAMP_INVERTINGINPUT_VM1 OPAMP_INVERTINGINPUT_IO1\r
+\r
+#define IOPAMP_INVERTINGINPUT_VM0 OPAMP_INVERTINGINPUT_IO0\r
+#define IOPAMP_INVERTINGINPUT_VM1 OPAMP_INVERTINGINPUT_IO1\r
+\r
+#define OPAMP_SEC_INVERTINGINPUT_VM0 OPAMP_SEC_INVERTINGINPUT_IO0\r
+#define OPAMP_SEC_INVERTINGINPUT_VM1 OPAMP_SEC_INVERTINGINPUT_IO1\r
+\r
+#define OPAMP_INVERTINGINPUT_VINM OPAMP_SEC_INVERTINGINPUT_IO1\r
+\r
+#define OPAMP_PGACONNECT_NO OPAMP_PGA_CONNECT_INVERTINGINPUT_NO\r
+#define OPAMP_PGACONNECT_VM0 OPAMP_PGA_CONNECT_INVERTINGINPUT_IO0\r
+#define OPAMP_PGACONNECT_VM1 OPAMP_PGA_CONNECT_INVERTINGINPUT_IO1\r
+\r
+#if defined(STM32L1) || defined(STM32L4)\r
+#define HAL_OPAMP_MSP_INIT_CB_ID HAL_OPAMP_MSPINIT_CB_ID\r
+#define HAL_OPAMP_MSP_DEINIT_CB_ID HAL_OPAMP_MSPDEINIT_CB_ID\r
+#endif\r
+\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup HAL_I2S_Aliased_Defines HAL I2S Aliased Defines maintained for legacy purpose\r
+ * @{\r
+ */\r
+#define I2S_STANDARD_PHILLIPS I2S_STANDARD_PHILIPS\r
+\r
+#if defined(STM32H7)\r
+ #define I2S_IT_TXE I2S_IT_TXP\r
+ #define I2S_IT_RXNE I2S_IT_RXP\r
+\r
+ #define I2S_FLAG_TXE I2S_FLAG_TXP\r
+ #define I2S_FLAG_RXNE I2S_FLAG_RXP\r
+#endif\r
+\r
+#if defined(STM32F7)\r
+ #define I2S_CLOCK_SYSCLK I2S_CLOCK_PLL\r
+#endif\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup HAL_PCCARD_Aliased_Defines HAL PCCARD Aliased Defines maintained for legacy purpose\r
+ * @{\r
+ */\r
+\r
+/* Compact Flash-ATA registers description */\r
+#define CF_DATA ATA_DATA\r
+#define CF_SECTOR_COUNT ATA_SECTOR_COUNT\r
+#define CF_SECTOR_NUMBER ATA_SECTOR_NUMBER\r
+#define CF_CYLINDER_LOW ATA_CYLINDER_LOW\r
+#define CF_CYLINDER_HIGH ATA_CYLINDER_HIGH\r
+#define CF_CARD_HEAD ATA_CARD_HEAD\r
+#define CF_STATUS_CMD ATA_STATUS_CMD\r
+#define CF_STATUS_CMD_ALTERNATE ATA_STATUS_CMD_ALTERNATE\r
+#define CF_COMMON_DATA_AREA ATA_COMMON_DATA_AREA\r
+\r
+/* Compact Flash-ATA commands */\r
+#define CF_READ_SECTOR_CMD ATA_READ_SECTOR_CMD\r
+#define CF_WRITE_SECTOR_CMD ATA_WRITE_SECTOR_CMD\r
+#define CF_ERASE_SECTOR_CMD ATA_ERASE_SECTOR_CMD\r
+#define CF_IDENTIFY_CMD ATA_IDENTIFY_CMD\r
+\r
+#define PCCARD_StatusTypedef HAL_PCCARD_StatusTypeDef\r
+#define PCCARD_SUCCESS HAL_PCCARD_STATUS_SUCCESS\r
+#define PCCARD_ONGOING HAL_PCCARD_STATUS_ONGOING\r
+#define PCCARD_ERROR HAL_PCCARD_STATUS_ERROR\r
+#define PCCARD_TIMEOUT HAL_PCCARD_STATUS_TIMEOUT\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup HAL_RTC_Aliased_Defines HAL RTC Aliased Defines maintained for legacy purpose\r
+ * @{\r
+ */\r
+\r
+#define FORMAT_BIN RTC_FORMAT_BIN\r
+#define FORMAT_BCD RTC_FORMAT_BCD\r
+\r
+#define RTC_ALARMSUBSECONDMASK_None RTC_ALARMSUBSECONDMASK_NONE\r
+#define RTC_TAMPERERASEBACKUP_DISABLED RTC_TAMPER_ERASE_BACKUP_DISABLE\r
+#define RTC_TAMPERMASK_FLAG_DISABLED RTC_TAMPERMASK_FLAG_DISABLE\r
+#define RTC_TAMPERMASK_FLAG_ENABLED RTC_TAMPERMASK_FLAG_ENABLE\r
+\r
+#define RTC_MASKTAMPERFLAG_DISABLED RTC_TAMPERMASK_FLAG_DISABLE\r
+#define RTC_MASKTAMPERFLAG_ENABLED RTC_TAMPERMASK_FLAG_ENABLE\r
+#define RTC_TAMPERERASEBACKUP_ENABLED RTC_TAMPER_ERASE_BACKUP_ENABLE\r
+#define RTC_TAMPER1_2_INTERRUPT RTC_ALL_TAMPER_INTERRUPT\r
+#define RTC_TAMPER1_2_3_INTERRUPT RTC_ALL_TAMPER_INTERRUPT\r
+\r
+#define RTC_TIMESTAMPPIN_PC13 RTC_TIMESTAMPPIN_DEFAULT\r
+#define RTC_TIMESTAMPPIN_PA0 RTC_TIMESTAMPPIN_POS1\r
+#define RTC_TIMESTAMPPIN_PI8 RTC_TIMESTAMPPIN_POS1\r
+#define RTC_TIMESTAMPPIN_PC1 RTC_TIMESTAMPPIN_POS2\r
+\r
+#define RTC_OUTPUT_REMAP_PC13 RTC_OUTPUT_REMAP_NONE\r
+#define RTC_OUTPUT_REMAP_PB14 RTC_OUTPUT_REMAP_POS1\r
+#define RTC_OUTPUT_REMAP_PB2 RTC_OUTPUT_REMAP_POS1\r
+\r
+#define RTC_TAMPERPIN_PC13 RTC_TAMPERPIN_DEFAULT\r
+#define RTC_TAMPERPIN_PA0 RTC_TAMPERPIN_POS1\r
+#define RTC_TAMPERPIN_PI8 RTC_TAMPERPIN_POS1\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+\r
+/** @defgroup HAL_SMARTCARD_Aliased_Defines HAL SMARTCARD Aliased Defines maintained for legacy purpose\r
+ * @{\r
+ */\r
+#define SMARTCARD_NACK_ENABLED SMARTCARD_NACK_ENABLE\r
+#define SMARTCARD_NACK_DISABLED SMARTCARD_NACK_DISABLE\r
+\r
+#define SMARTCARD_ONEBIT_SAMPLING_DISABLED SMARTCARD_ONE_BIT_SAMPLE_DISABLE\r
+#define SMARTCARD_ONEBIT_SAMPLING_ENABLED SMARTCARD_ONE_BIT_SAMPLE_ENABLE\r
+#define SMARTCARD_ONEBIT_SAMPLING_DISABLE SMARTCARD_ONE_BIT_SAMPLE_DISABLE\r
+#define SMARTCARD_ONEBIT_SAMPLING_ENABLE SMARTCARD_ONE_BIT_SAMPLE_ENABLE\r
+\r
+#define SMARTCARD_TIMEOUT_DISABLED SMARTCARD_TIMEOUT_DISABLE\r
+#define SMARTCARD_TIMEOUT_ENABLED SMARTCARD_TIMEOUT_ENABLE\r
+\r
+#define SMARTCARD_LASTBIT_DISABLED SMARTCARD_LASTBIT_DISABLE\r
+#define SMARTCARD_LASTBIT_ENABLED SMARTCARD_LASTBIT_ENABLE\r
+/**\r
+ * @}\r
+ */\r
+\r
+\r
+/** @defgroup HAL_SMBUS_Aliased_Defines HAL SMBUS Aliased Defines maintained for legacy purpose\r
+ * @{\r
+ */\r
+#define SMBUS_DUALADDRESS_DISABLED SMBUS_DUALADDRESS_DISABLE\r
+#define SMBUS_DUALADDRESS_ENABLED SMBUS_DUALADDRESS_ENABLE\r
+#define SMBUS_GENERALCALL_DISABLED SMBUS_GENERALCALL_DISABLE\r
+#define SMBUS_GENERALCALL_ENABLED SMBUS_GENERALCALL_ENABLE\r
+#define SMBUS_NOSTRETCH_DISABLED SMBUS_NOSTRETCH_DISABLE\r
+#define SMBUS_NOSTRETCH_ENABLED SMBUS_NOSTRETCH_ENABLE\r
+#define SMBUS_ANALOGFILTER_ENABLED SMBUS_ANALOGFILTER_ENABLE\r
+#define SMBUS_ANALOGFILTER_DISABLED SMBUS_ANALOGFILTER_DISABLE\r
+#define SMBUS_PEC_DISABLED SMBUS_PEC_DISABLE\r
+#define SMBUS_PEC_ENABLED SMBUS_PEC_ENABLE\r
+#define HAL_SMBUS_STATE_SLAVE_LISTEN HAL_SMBUS_STATE_LISTEN\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup HAL_SPI_Aliased_Defines HAL SPI Aliased Defines maintained for legacy purpose\r
+ * @{\r
+ */\r
+#define SPI_TIMODE_DISABLED SPI_TIMODE_DISABLE\r
+#define SPI_TIMODE_ENABLED SPI_TIMODE_ENABLE\r
+\r
+#define SPI_CRCCALCULATION_DISABLED SPI_CRCCALCULATION_DISABLE\r
+#define SPI_CRCCALCULATION_ENABLED SPI_CRCCALCULATION_ENABLE\r
+\r
+#define SPI_NSS_PULSE_DISABLED SPI_NSS_PULSE_DISABLE\r
+#define SPI_NSS_PULSE_ENABLED SPI_NSS_PULSE_ENABLE\r
+\r
+#if defined(STM32H7)\r
+\r
+ #define SPI_FLAG_TXE SPI_FLAG_TXP\r
+ #define SPI_FLAG_RXNE SPI_FLAG_RXP\r
+\r
+ #define SPI_IT_TXE SPI_IT_TXP\r
+ #define SPI_IT_RXNE SPI_IT_RXP\r
+\r
+ #define SPI_FRLVL_EMPTY SPI_RX_FIFO_0PACKET\r
+ #define SPI_FRLVL_QUARTER_FULL SPI_RX_FIFO_1PACKET\r
+ #define SPI_FRLVL_HALF_FULL SPI_RX_FIFO_2PACKET\r
+ #define SPI_FRLVL_FULL SPI_RX_FIFO_3PACKET\r
+\r
+#endif /* STM32H7 */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup HAL_TIM_Aliased_Defines HAL TIM Aliased Defines maintained for legacy purpose\r
+ * @{\r
+ */\r
+#define CCER_CCxE_MASK TIM_CCER_CCxE_MASK\r
+#define CCER_CCxNE_MASK TIM_CCER_CCxNE_MASK\r
+\r
+#define TIM_DMABase_CR1 TIM_DMABASE_CR1\r
+#define TIM_DMABase_CR2 TIM_DMABASE_CR2\r
+#define TIM_DMABase_SMCR TIM_DMABASE_SMCR\r
+#define TIM_DMABase_DIER TIM_DMABASE_DIER\r
+#define TIM_DMABase_SR TIM_DMABASE_SR\r
+#define TIM_DMABase_EGR TIM_DMABASE_EGR\r
+#define TIM_DMABase_CCMR1 TIM_DMABASE_CCMR1\r
+#define TIM_DMABase_CCMR2 TIM_DMABASE_CCMR2\r
+#define TIM_DMABase_CCER TIM_DMABASE_CCER\r
+#define TIM_DMABase_CNT TIM_DMABASE_CNT\r
+#define TIM_DMABase_PSC TIM_DMABASE_PSC\r
+#define TIM_DMABase_ARR TIM_DMABASE_ARR\r
+#define TIM_DMABase_RCR TIM_DMABASE_RCR\r
+#define TIM_DMABase_CCR1 TIM_DMABASE_CCR1\r
+#define TIM_DMABase_CCR2 TIM_DMABASE_CCR2\r
+#define TIM_DMABase_CCR3 TIM_DMABASE_CCR3\r
+#define TIM_DMABase_CCR4 TIM_DMABASE_CCR4\r
+#define TIM_DMABase_BDTR TIM_DMABASE_BDTR\r
+#define TIM_DMABase_DCR TIM_DMABASE_DCR\r
+#define TIM_DMABase_DMAR TIM_DMABASE_DMAR\r
+#define TIM_DMABase_OR1 TIM_DMABASE_OR1\r
+#define TIM_DMABase_CCMR3 TIM_DMABASE_CCMR3\r
+#define TIM_DMABase_CCR5 TIM_DMABASE_CCR5\r
+#define TIM_DMABase_CCR6 TIM_DMABASE_CCR6\r
+#define TIM_DMABase_OR2 TIM_DMABASE_OR2\r
+#define TIM_DMABase_OR3 TIM_DMABASE_OR3\r
+#define TIM_DMABase_OR TIM_DMABASE_OR\r
+\r
+#define TIM_EventSource_Update TIM_EVENTSOURCE_UPDATE\r
+#define TIM_EventSource_CC1 TIM_EVENTSOURCE_CC1\r
+#define TIM_EventSource_CC2 TIM_EVENTSOURCE_CC2\r
+#define TIM_EventSource_CC3 TIM_EVENTSOURCE_CC3\r
+#define TIM_EventSource_CC4 TIM_EVENTSOURCE_CC4\r
+#define TIM_EventSource_COM TIM_EVENTSOURCE_COM\r
+#define TIM_EventSource_Trigger TIM_EVENTSOURCE_TRIGGER\r
+#define TIM_EventSource_Break TIM_EVENTSOURCE_BREAK\r
+#define TIM_EventSource_Break2 TIM_EVENTSOURCE_BREAK2\r
+\r
+#define TIM_DMABurstLength_1Transfer TIM_DMABURSTLENGTH_1TRANSFER\r
+#define TIM_DMABurstLength_2Transfers TIM_DMABURSTLENGTH_2TRANSFERS\r
+#define TIM_DMABurstLength_3Transfers TIM_DMABURSTLENGTH_3TRANSFERS\r
+#define TIM_DMABurstLength_4Transfers TIM_DMABURSTLENGTH_4TRANSFERS\r
+#define TIM_DMABurstLength_5Transfers TIM_DMABURSTLENGTH_5TRANSFERS\r
+#define TIM_DMABurstLength_6Transfers TIM_DMABURSTLENGTH_6TRANSFERS\r
+#define TIM_DMABurstLength_7Transfers TIM_DMABURSTLENGTH_7TRANSFERS\r
+#define TIM_DMABurstLength_8Transfers TIM_DMABURSTLENGTH_8TRANSFERS\r
+#define TIM_DMABurstLength_9Transfers TIM_DMABURSTLENGTH_9TRANSFERS\r
+#define TIM_DMABurstLength_10Transfers TIM_DMABURSTLENGTH_10TRANSFERS\r
+#define TIM_DMABurstLength_11Transfers TIM_DMABURSTLENGTH_11TRANSFERS\r
+#define TIM_DMABurstLength_12Transfers TIM_DMABURSTLENGTH_12TRANSFERS\r
+#define TIM_DMABurstLength_13Transfers TIM_DMABURSTLENGTH_13TRANSFERS\r
+#define TIM_DMABurstLength_14Transfers TIM_DMABURSTLENGTH_14TRANSFERS\r
+#define TIM_DMABurstLength_15Transfers TIM_DMABURSTLENGTH_15TRANSFERS\r
+#define TIM_DMABurstLength_16Transfers TIM_DMABURSTLENGTH_16TRANSFERS\r
+#define TIM_DMABurstLength_17Transfers TIM_DMABURSTLENGTH_17TRANSFERS\r
+#define TIM_DMABurstLength_18Transfers TIM_DMABURSTLENGTH_18TRANSFERS\r
+\r
+#if defined(STM32L0)\r
+#define TIM22_TI1_GPIO1 TIM22_TI1_GPIO\r
+#define TIM22_TI1_GPIO2 TIM22_TI1_GPIO\r
+#endif\r
+\r
+#if defined(STM32F3)\r
+#define IS_TIM_HALL_INTERFACE_INSTANCE IS_TIM_HALL_SENSOR_INTERFACE_INSTANCE\r
+#endif\r
+\r
+#if defined(STM32H7)\r
+#define TIM_TIM1_ETR_COMP1_OUT TIM_TIM1_ETR_COMP1\r
+#define TIM_TIM1_ETR_COMP2_OUT TIM_TIM1_ETR_COMP2\r
+#define TIM_TIM8_ETR_COMP1_OUT TIM_TIM8_ETR_COMP1\r
+#define TIM_TIM8_ETR_COMP2_OUT TIM_TIM8_ETR_COMP2\r
+#define TIM_TIM2_ETR_COMP1_OUT TIM_TIM2_ETR_COMP1\r
+#define TIM_TIM2_ETR_COMP2_OUT TIM_TIM2_ETR_COMP2\r
+#define TIM_TIM3_ETR_COMP1_OUT TIM_TIM3_ETR_COMP1\r
+#define TIM_TIM1_TI1_COMP1_OUT TIM_TIM1_TI1_COMP1\r
+#define TIM_TIM8_TI1_COMP2_OUT TIM_TIM8_TI1_COMP2\r
+#define TIM_TIM2_TI4_COMP1_OUT TIM_TIM2_TI4_COMP1\r
+#define TIM_TIM2_TI4_COMP2_OUT TIM_TIM2_TI4_COMP2\r
+#define TIM_TIM2_TI4_COMP1COMP2_OUT TIM_TIM2_TI4_COMP1_COMP2\r
+#define TIM_TIM3_TI1_COMP1_OUT TIM_TIM3_TI1_COMP1\r
+#define TIM_TIM3_TI1_COMP2_OUT TIM_TIM3_TI1_COMP2\r
+#define TIM_TIM3_TI1_COMP1COMP2_OUT TIM_TIM3_TI1_COMP1_COMP2\r
+#endif\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup HAL_TSC_Aliased_Defines HAL TSC Aliased Defines maintained for legacy purpose\r
+ * @{\r
+ */\r
+#define TSC_SYNC_POL_FALL TSC_SYNC_POLARITY_FALLING\r
+#define TSC_SYNC_POL_RISE_HIGH TSC_SYNC_POLARITY_RISING\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup HAL_UART_Aliased_Defines HAL UART Aliased Defines maintained for legacy purpose\r
+ * @{\r
+ */\r
+#define UART_ONEBIT_SAMPLING_DISABLED UART_ONE_BIT_SAMPLE_DISABLE\r
+#define UART_ONEBIT_SAMPLING_ENABLED UART_ONE_BIT_SAMPLE_ENABLE\r
+#define UART_ONE_BIT_SAMPLE_DISABLED UART_ONE_BIT_SAMPLE_DISABLE\r
+#define UART_ONE_BIT_SAMPLE_ENABLED UART_ONE_BIT_SAMPLE_ENABLE\r
+\r
+#define __HAL_UART_ONEBIT_ENABLE __HAL_UART_ONE_BIT_SAMPLE_ENABLE\r
+#define __HAL_UART_ONEBIT_DISABLE __HAL_UART_ONE_BIT_SAMPLE_DISABLE\r
+\r
+#define __DIV_SAMPLING16 UART_DIV_SAMPLING16\r
+#define __DIVMANT_SAMPLING16 UART_DIVMANT_SAMPLING16\r
+#define __DIVFRAQ_SAMPLING16 UART_DIVFRAQ_SAMPLING16\r
+#define __UART_BRR_SAMPLING16 UART_BRR_SAMPLING16\r
+\r
+#define __DIV_SAMPLING8 UART_DIV_SAMPLING8\r
+#define __DIVMANT_SAMPLING8 UART_DIVMANT_SAMPLING8\r
+#define __DIVFRAQ_SAMPLING8 UART_DIVFRAQ_SAMPLING8\r
+#define __UART_BRR_SAMPLING8 UART_BRR_SAMPLING8\r
+\r
+#define __DIV_LPUART UART_DIV_LPUART\r
+\r
+#define UART_WAKEUPMETHODE_IDLELINE UART_WAKEUPMETHOD_IDLELINE\r
+#define UART_WAKEUPMETHODE_ADDRESSMARK UART_WAKEUPMETHOD_ADDRESSMARK\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+\r
+/** @defgroup HAL_USART_Aliased_Defines HAL USART Aliased Defines maintained for legacy purpose\r
+ * @{\r
+ */\r
+\r
+#define USART_CLOCK_DISABLED USART_CLOCK_DISABLE\r
+#define USART_CLOCK_ENABLED USART_CLOCK_ENABLE\r
+\r
+#define USARTNACK_ENABLED USART_NACK_ENABLE\r
+#define USARTNACK_DISABLED USART_NACK_DISABLE\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup HAL_WWDG_Aliased_Defines HAL WWDG Aliased Defines maintained for legacy purpose\r
+ * @{\r
+ */\r
+#define CFR_BASE WWDG_CFR_BASE\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup HAL_CAN_Aliased_Defines HAL CAN Aliased Defines maintained for legacy purpose\r
+ * @{\r
+ */\r
+#define CAN_FilterFIFO0 CAN_FILTER_FIFO0\r
+#define CAN_FilterFIFO1 CAN_FILTER_FIFO1\r
+#define CAN_IT_RQCP0 CAN_IT_TME\r
+#define CAN_IT_RQCP1 CAN_IT_TME\r
+#define CAN_IT_RQCP2 CAN_IT_TME\r
+#define INAK_TIMEOUT CAN_TIMEOUT_VALUE\r
+#define SLAK_TIMEOUT CAN_TIMEOUT_VALUE\r
+#define CAN_TXSTATUS_FAILED ((uint8_t)0x00U)\r
+#define CAN_TXSTATUS_OK ((uint8_t)0x01U)\r
+#define CAN_TXSTATUS_PENDING ((uint8_t)0x02U)\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup HAL_ETH_Aliased_Defines HAL ETH Aliased Defines maintained for legacy purpose\r
+ * @{\r
+ */\r
+\r
+#define VLAN_TAG ETH_VLAN_TAG\r
+#define MIN_ETH_PAYLOAD ETH_MIN_ETH_PAYLOAD\r
+#define MAX_ETH_PAYLOAD ETH_MAX_ETH_PAYLOAD\r
+#define JUMBO_FRAME_PAYLOAD ETH_JUMBO_FRAME_PAYLOAD\r
+#define MACMIIAR_CR_MASK ETH_MACMIIAR_CR_MASK\r
+#define MACCR_CLEAR_MASK ETH_MACCR_CLEAR_MASK\r
+#define MACFCR_CLEAR_MASK ETH_MACFCR_CLEAR_MASK\r
+#define DMAOMR_CLEAR_MASK ETH_DMAOMR_CLEAR_MASK\r
+\r
+#define ETH_MMCCR 0x00000100U\r
+#define ETH_MMCRIR 0x00000104U\r
+#define ETH_MMCTIR 0x00000108U\r
+#define ETH_MMCRIMR 0x0000010CU\r
+#define ETH_MMCTIMR 0x00000110U\r
+#define ETH_MMCTGFSCCR 0x0000014CU\r
+#define ETH_MMCTGFMSCCR 0x00000150U\r
+#define ETH_MMCTGFCR 0x00000168U\r
+#define ETH_MMCRFCECR 0x00000194U\r
+#define ETH_MMCRFAECR 0x00000198U\r
+#define ETH_MMCRGUFCR 0x000001C4U\r
+\r
+#define ETH_MAC_TXFIFO_FULL 0x02000000U /* Tx FIFO full */\r
+#define ETH_MAC_TXFIFONOT_EMPTY 0x01000000U /* Tx FIFO not empty */\r
+#define ETH_MAC_TXFIFO_WRITE_ACTIVE 0x00400000U /* Tx FIFO write active */\r
+#define ETH_MAC_TXFIFO_IDLE 0x00000000U /* Tx FIFO read status: Idle */\r
+#define ETH_MAC_TXFIFO_READ 0x00100000U /* Tx FIFO read status: Read (transferring data to the MAC transmitter) */\r
+#define ETH_MAC_TXFIFO_WAITING 0x00200000U /* Tx FIFO read status: Waiting for TxStatus from MAC transmitter */\r
+#define ETH_MAC_TXFIFO_WRITING 0x00300000U /* Tx FIFO read status: Writing the received TxStatus or flushing the TxFIFO */\r
+#define ETH_MAC_TRANSMISSION_PAUSE 0x00080000U /* MAC transmitter in pause */\r
+#define ETH_MAC_TRANSMITFRAMECONTROLLER_IDLE 0x00000000U /* MAC transmit frame controller: Idle */\r
+#define ETH_MAC_TRANSMITFRAMECONTROLLER_WAITING 0x00020000U /* MAC transmit frame controller: Waiting for Status of previous frame or IFG/backoff period to be over */\r
+#define ETH_MAC_TRANSMITFRAMECONTROLLER_GENRATING_PCF 0x00040000U /* MAC transmit frame controller: Generating and transmitting a Pause control frame (in full duplex mode) */\r
+#define ETH_MAC_TRANSMITFRAMECONTROLLER_TRANSFERRING 0x00060000U /* MAC transmit frame controller: Transferring input frame for transmission */\r
+#define ETH_MAC_MII_TRANSMIT_ACTIVE 0x00010000U /* MAC MII transmit engine active */\r
+#define ETH_MAC_RXFIFO_EMPTY 0x00000000U /* Rx FIFO fill level: empty */\r
+#define ETH_MAC_RXFIFO_BELOW_THRESHOLD 0x00000100U /* Rx FIFO fill level: fill-level below flow-control de-activate threshold */\r
+#define ETH_MAC_RXFIFO_ABOVE_THRESHOLD 0x00000200U /* Rx FIFO fill level: fill-level above flow-control activate threshold */\r
+#define ETH_MAC_RXFIFO_FULL 0x00000300U /* Rx FIFO fill level: full */\r
+#if defined(STM32F1)\r
+#else\r
+#define ETH_MAC_READCONTROLLER_IDLE 0x00000000U /* Rx FIFO read controller IDLE state */\r
+#define ETH_MAC_READCONTROLLER_READING_DATA 0x00000020U /* Rx FIFO read controller Reading frame data */\r
+#define ETH_MAC_READCONTROLLER_READING_STATUS 0x00000040U /* Rx FIFO read controller Reading frame status (or time-stamp) */\r
+#endif\r
+#define ETH_MAC_READCONTROLLER_FLUSHING 0x00000060U /* Rx FIFO read controller Flushing the frame data and status */\r
+#define ETH_MAC_RXFIFO_WRITE_ACTIVE 0x00000010U /* Rx FIFO write controller active */\r
+#define ETH_MAC_SMALL_FIFO_NOTACTIVE 0x00000000U /* MAC small FIFO read / write controllers not active */\r
+#define ETH_MAC_SMALL_FIFO_READ_ACTIVE 0x00000002U /* MAC small FIFO read controller active */\r
+#define ETH_MAC_SMALL_FIFO_WRITE_ACTIVE 0x00000004U /* MAC small FIFO write controller active */\r
+#define ETH_MAC_SMALL_FIFO_RW_ACTIVE 0x00000006U /* MAC small FIFO read / write controllers active */\r
+#define ETH_MAC_MII_RECEIVE_PROTOCOL_ACTIVE 0x00000001U /* MAC MII receive protocol engine active */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup HAL_DCMI_Aliased_Defines HAL DCMI Aliased Defines maintained for legacy purpose\r
+ * @{\r
+ */\r
+#define HAL_DCMI_ERROR_OVF HAL_DCMI_ERROR_OVR\r
+#define DCMI_IT_OVF DCMI_IT_OVR\r
+#define DCMI_FLAG_OVFRI DCMI_FLAG_OVRRI\r
+#define DCMI_FLAG_OVFMI DCMI_FLAG_OVRMI\r
+\r
+#define HAL_DCMI_ConfigCROP HAL_DCMI_ConfigCrop\r
+#define HAL_DCMI_EnableCROP HAL_DCMI_EnableCrop\r
+#define HAL_DCMI_DisableCROP HAL_DCMI_DisableCrop\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+#if defined(STM32L4) || defined(STM32F7) || defined(STM32F427xx) || defined(STM32F437xx) \\r
+ || defined(STM32F429xx) || defined(STM32F439xx) || defined(STM32F469xx) || defined(STM32F479xx) \\r
+ || defined(STM32H7)\r
+/** @defgroup HAL_DMA2D_Aliased_Defines HAL DMA2D Aliased Defines maintained for legacy purpose\r
+ * @{\r
+ */\r
+#define DMA2D_ARGB8888 DMA2D_OUTPUT_ARGB8888\r
+#define DMA2D_RGB888 DMA2D_OUTPUT_RGB888\r
+#define DMA2D_RGB565 DMA2D_OUTPUT_RGB565\r
+#define DMA2D_ARGB1555 DMA2D_OUTPUT_ARGB1555\r
+#define DMA2D_ARGB4444 DMA2D_OUTPUT_ARGB4444\r
+\r
+#define CM_ARGB8888 DMA2D_INPUT_ARGB8888\r
+#define CM_RGB888 DMA2D_INPUT_RGB888\r
+#define CM_RGB565 DMA2D_INPUT_RGB565\r
+#define CM_ARGB1555 DMA2D_INPUT_ARGB1555\r
+#define CM_ARGB4444 DMA2D_INPUT_ARGB4444\r
+#define CM_L8 DMA2D_INPUT_L8\r
+#define CM_AL44 DMA2D_INPUT_AL44\r
+#define CM_AL88 DMA2D_INPUT_AL88\r
+#define CM_L4 DMA2D_INPUT_L4\r
+#define CM_A8 DMA2D_INPUT_A8\r
+#define CM_A4 DMA2D_INPUT_A4\r
+/**\r
+ * @}\r
+ */\r
+#endif /* STM32L4 || STM32F7 || STM32F4 || STM32H7 */\r
+\r
+/** @defgroup HAL_PPP_Aliased_Defines HAL PPP Aliased Defines maintained for legacy purpose\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/* Exported functions --------------------------------------------------------*/\r
+\r
+/** @defgroup HAL_CRYP_Aliased_Functions HAL CRYP Aliased Functions maintained for legacy purpose\r
+ * @{\r
+ */\r
+#define HAL_CRYP_ComputationCpltCallback HAL_CRYPEx_ComputationCpltCallback\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup HAL_HASH_Aliased_Functions HAL HASH Aliased Functions maintained for legacy purpose\r
+ * @{\r
+ */\r
+#define HAL_HASH_STATETypeDef HAL_HASH_StateTypeDef\r
+#define HAL_HASHPhaseTypeDef HAL_HASH_PhaseTypeDef\r
+#define HAL_HMAC_MD5_Finish HAL_HASH_MD5_Finish\r
+#define HAL_HMAC_SHA1_Finish HAL_HASH_SHA1_Finish\r
+#define HAL_HMAC_SHA224_Finish HAL_HASH_SHA224_Finish\r
+#define HAL_HMAC_SHA256_Finish HAL_HASH_SHA256_Finish\r
+\r
+/*HASH Algorithm Selection*/\r
+\r
+#define HASH_AlgoSelection_SHA1 HASH_ALGOSELECTION_SHA1\r
+#define HASH_AlgoSelection_SHA224 HASH_ALGOSELECTION_SHA224\r
+#define HASH_AlgoSelection_SHA256 HASH_ALGOSELECTION_SHA256\r
+#define HASH_AlgoSelection_MD5 HASH_ALGOSELECTION_MD5\r
+\r
+#define HASH_AlgoMode_HASH HASH_ALGOMODE_HASH\r
+#define HASH_AlgoMode_HMAC HASH_ALGOMODE_HMAC\r
+\r
+#define HASH_HMACKeyType_ShortKey HASH_HMAC_KEYTYPE_SHORTKEY\r
+#define HASH_HMACKeyType_LongKey HASH_HMAC_KEYTYPE_LONGKEY\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup HAL_Aliased_Functions HAL Generic Aliased Functions maintained for legacy purpose\r
+ * @{\r
+ */\r
+#define HAL_EnableDBGSleepMode HAL_DBGMCU_EnableDBGSleepMode\r
+#define HAL_DisableDBGSleepMode HAL_DBGMCU_DisableDBGSleepMode\r
+#define HAL_EnableDBGStopMode HAL_DBGMCU_EnableDBGStopMode\r
+#define HAL_DisableDBGStopMode HAL_DBGMCU_DisableDBGStopMode\r
+#define HAL_EnableDBGStandbyMode HAL_DBGMCU_EnableDBGStandbyMode\r
+#define HAL_DisableDBGStandbyMode HAL_DBGMCU_DisableDBGStandbyMode\r
+#define HAL_DBG_LowPowerConfig(Periph, cmd) (((cmd)==ENABLE)? HAL_DBGMCU_DBG_EnableLowPowerConfig(Periph) : HAL_DBGMCU_DBG_DisableLowPowerConfig(Periph))\r
+#define HAL_VREFINT_OutputSelect HAL_SYSCFG_VREFINT_OutputSelect\r
+#define HAL_Lock_Cmd(cmd) (((cmd)==ENABLE) ? HAL_SYSCFG_Enable_Lock_VREFINT() : HAL_SYSCFG_Disable_Lock_VREFINT())\r
+#if defined(STM32L0)\r
+#else\r
+#define HAL_VREFINT_Cmd(cmd) (((cmd)==ENABLE)? HAL_SYSCFG_EnableVREFINT() : HAL_SYSCFG_DisableVREFINT())\r
+#endif\r
+#define HAL_ADC_EnableBuffer_Cmd(cmd) (((cmd)==ENABLE) ? HAL_ADCEx_EnableVREFINT() : HAL_ADCEx_DisableVREFINT())\r
+#define HAL_ADC_EnableBufferSensor_Cmd(cmd) (((cmd)==ENABLE) ? HAL_ADCEx_EnableVREFINTTempSensor() : HAL_ADCEx_DisableVREFINTTempSensor())\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup HAL_FLASH_Aliased_Functions HAL FLASH Aliased Functions maintained for legacy purpose\r
+ * @{\r
+ */\r
+#define FLASH_HalfPageProgram HAL_FLASHEx_HalfPageProgram\r
+#define FLASH_EnableRunPowerDown HAL_FLASHEx_EnableRunPowerDown\r
+#define FLASH_DisableRunPowerDown HAL_FLASHEx_DisableRunPowerDown\r
+#define HAL_DATA_EEPROMEx_Unlock HAL_FLASHEx_DATAEEPROM_Unlock\r
+#define HAL_DATA_EEPROMEx_Lock HAL_FLASHEx_DATAEEPROM_Lock\r
+#define HAL_DATA_EEPROMEx_Erase HAL_FLASHEx_DATAEEPROM_Erase\r
+#define HAL_DATA_EEPROMEx_Program HAL_FLASHEx_DATAEEPROM_Program\r
+\r
+ /**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup HAL_I2C_Aliased_Functions HAL I2C Aliased Functions maintained for legacy purpose\r
+ * @{\r
+ */\r
+#define HAL_I2CEx_AnalogFilter_Config HAL_I2CEx_ConfigAnalogFilter\r
+#define HAL_I2CEx_DigitalFilter_Config HAL_I2CEx_ConfigDigitalFilter\r
+#define HAL_FMPI2CEx_AnalogFilter_Config HAL_FMPI2CEx_ConfigAnalogFilter\r
+#define HAL_FMPI2CEx_DigitalFilter_Config HAL_FMPI2CEx_ConfigDigitalFilter\r
+\r
+#define HAL_I2CFastModePlusConfig(SYSCFG_I2CFastModePlus, cmd) (((cmd)==ENABLE)? HAL_I2CEx_EnableFastModePlus(SYSCFG_I2CFastModePlus): HAL_I2CEx_DisableFastModePlus(SYSCFG_I2CFastModePlus))\r
+\r
+#if defined(STM32H7) || defined(STM32WB) || defined(STM32G0) || defined(STM32F4) || defined(STM32F7) || defined(STM32L0) || defined(STM32L4)\r
+#define HAL_I2C_Master_Sequential_Transmit_IT HAL_I2C_Master_Seq_Transmit_IT\r
+#define HAL_I2C_Master_Sequential_Receive_IT HAL_I2C_Master_Seq_Receive_IT\r
+#define HAL_I2C_Slave_Sequential_Transmit_IT HAL_I2C_Slave_Seq_Transmit_IT\r
+#define HAL_I2C_Slave_Sequential_Receive_IT HAL_I2C_Slave_Seq_Receive_IT\r
+#define HAL_I2C_Master_Sequential_Transmit_DMA HAL_I2C_Master_Seq_Transmit_DMA\r
+#define HAL_I2C_Master_Sequential_Receive_DMA HAL_I2C_Master_Seq_Receive_DMA\r
+#define HAL_I2C_Slave_Sequential_Transmit_DMA HAL_I2C_Slave_Seq_Transmit_DMA\r
+#define HAL_I2C_Slave_Sequential_Receive_DMA HAL_I2C_Slave_Seq_Receive_DMA\r
+#endif /* STM32H7 || STM32WB || STM32G0 || STM32F4 || STM32F7 || STM32L0 || STM32L4 */\r
+\r
+#if defined(STM32F4)\r
+#define HAL_FMPI2C_Master_Sequential_Transmit_IT HAL_FMPI2C_Master_Seq_Transmit_IT\r
+#define HAL_FMPI2C_Master_Sequential_Receive_IT HAL_FMPI2C_Master_Seq_Receive_IT\r
+#define HAL_FMPI2C_Slave_Sequential_Transmit_IT HAL_FMPI2C_Slave_Seq_Transmit_IT\r
+#define HAL_FMPI2C_Slave_Sequential_Receive_IT HAL_FMPI2C_Slave_Seq_Receive_IT\r
+#define HAL_FMPI2C_Master_Sequential_Transmit_DMA HAL_FMPI2C_Master_Seq_Transmit_DMA\r
+#define HAL_FMPI2C_Master_Sequential_Receive_DMA HAL_FMPI2C_Master_Seq_Receive_DMA\r
+#define HAL_FMPI2C_Slave_Sequential_Transmit_DMA HAL_FMPI2C_Slave_Seq_Transmit_DMA\r
+#define HAL_FMPI2C_Slave_Sequential_Receive_DMA HAL_FMPI2C_Slave_Seq_Receive_DMA\r
+#endif /* STM32F4 */\r
+ /**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup HAL_PWR_Aliased HAL PWR Aliased maintained for legacy purpose\r
+ * @{\r
+ */\r
+#define HAL_PWR_PVDConfig HAL_PWR_ConfigPVD\r
+#define HAL_PWR_DisableBkUpReg HAL_PWREx_DisableBkUpReg\r
+#define HAL_PWR_DisableFlashPowerDown HAL_PWREx_DisableFlashPowerDown\r
+#define HAL_PWR_DisableVddio2Monitor HAL_PWREx_DisableVddio2Monitor\r
+#define HAL_PWR_EnableBkUpReg HAL_PWREx_EnableBkUpReg\r
+#define HAL_PWR_EnableFlashPowerDown HAL_PWREx_EnableFlashPowerDown\r
+#define HAL_PWR_EnableVddio2Monitor HAL_PWREx_EnableVddio2Monitor\r
+#define HAL_PWR_PVD_PVM_IRQHandler HAL_PWREx_PVD_PVM_IRQHandler\r
+#define HAL_PWR_PVDLevelConfig HAL_PWR_ConfigPVD\r
+#define HAL_PWR_Vddio2Monitor_IRQHandler HAL_PWREx_Vddio2Monitor_IRQHandler\r
+#define HAL_PWR_Vddio2MonitorCallback HAL_PWREx_Vddio2MonitorCallback\r
+#define HAL_PWREx_ActivateOverDrive HAL_PWREx_EnableOverDrive\r
+#define HAL_PWREx_DeactivateOverDrive HAL_PWREx_DisableOverDrive\r
+#define HAL_PWREx_DisableSDADCAnalog HAL_PWREx_DisableSDADC\r
+#define HAL_PWREx_EnableSDADCAnalog HAL_PWREx_EnableSDADC\r
+#define HAL_PWREx_PVMConfig HAL_PWREx_ConfigPVM\r
+\r
+#define PWR_MODE_NORMAL PWR_PVD_MODE_NORMAL\r
+#define PWR_MODE_IT_RISING PWR_PVD_MODE_IT_RISING\r
+#define PWR_MODE_IT_FALLING PWR_PVD_MODE_IT_FALLING\r
+#define PWR_MODE_IT_RISING_FALLING PWR_PVD_MODE_IT_RISING_FALLING\r
+#define PWR_MODE_EVENT_RISING PWR_PVD_MODE_EVENT_RISING\r
+#define PWR_MODE_EVENT_FALLING PWR_PVD_MODE_EVENT_FALLING\r
+#define PWR_MODE_EVENT_RISING_FALLING PWR_PVD_MODE_EVENT_RISING_FALLING\r
+\r
+#define CR_OFFSET_BB PWR_CR_OFFSET_BB\r
+#define CSR_OFFSET_BB PWR_CSR_OFFSET_BB\r
+#define PMODE_BIT_NUMBER VOS_BIT_NUMBER\r
+#define CR_PMODE_BB CR_VOS_BB\r
+\r
+#define DBP_BitNumber DBP_BIT_NUMBER\r
+#define PVDE_BitNumber PVDE_BIT_NUMBER\r
+#define PMODE_BitNumber PMODE_BIT_NUMBER\r
+#define EWUP_BitNumber EWUP_BIT_NUMBER\r
+#define FPDS_BitNumber FPDS_BIT_NUMBER\r
+#define ODEN_BitNumber ODEN_BIT_NUMBER\r
+#define ODSWEN_BitNumber ODSWEN_BIT_NUMBER\r
+#define MRLVDS_BitNumber MRLVDS_BIT_NUMBER\r
+#define LPLVDS_BitNumber LPLVDS_BIT_NUMBER\r
+#define BRE_BitNumber BRE_BIT_NUMBER\r
+\r
+#define PWR_MODE_EVT PWR_PVD_MODE_NORMAL\r
+\r
+ /**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup HAL_SMBUS_Aliased_Functions HAL SMBUS Aliased Functions maintained for legacy purpose\r
+ * @{\r
+ */\r
+#define HAL_SMBUS_Slave_Listen_IT HAL_SMBUS_EnableListen_IT\r
+#define HAL_SMBUS_SlaveAddrCallback HAL_SMBUS_AddrCallback\r
+#define HAL_SMBUS_SlaveListenCpltCallback HAL_SMBUS_ListenCpltCallback\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup HAL_SPI_Aliased_Functions HAL SPI Aliased Functions maintained for legacy purpose\r
+ * @{\r
+ */\r
+#define HAL_SPI_FlushRxFifo HAL_SPIEx_FlushRxFifo\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup HAL_TIM_Aliased_Functions HAL TIM Aliased Functions maintained for legacy purpose\r
+ * @{\r
+ */\r
+#define HAL_TIM_DMADelayPulseCplt TIM_DMADelayPulseCplt\r
+#define HAL_TIM_DMAError TIM_DMAError\r
+#define HAL_TIM_DMACaptureCplt TIM_DMACaptureCplt\r
+#define HAL_TIMEx_DMACommutationCplt TIMEx_DMACommutationCplt\r
+#if defined(STM32H7) || defined(STM32G0) || defined(STM32F7) || defined(STM32F4) || defined(STM32L0) || defined(STM32L4)\r
+#define HAL_TIM_SlaveConfigSynchronization HAL_TIM_SlaveConfigSynchro\r
+#define HAL_TIM_SlaveConfigSynchronization_IT HAL_TIM_SlaveConfigSynchro_IT\r
+#define HAL_TIMEx_CommutationCallback HAL_TIMEx_CommutCallback\r
+#define HAL_TIMEx_ConfigCommutationEvent HAL_TIMEx_ConfigCommutEvent\r
+#define HAL_TIMEx_ConfigCommutationEvent_IT HAL_TIMEx_ConfigCommutEvent_IT\r
+#define HAL_TIMEx_ConfigCommutationEvent_DMA HAL_TIMEx_ConfigCommutEvent_DMA\r
+#endif /* STM32H7 || STM32G0 || STM32F7 || STM32F4 || STM32L0 */\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup HAL_UART_Aliased_Functions HAL UART Aliased Functions maintained for legacy purpose\r
+ * @{\r
+ */\r
+#define HAL_UART_WakeupCallback HAL_UARTEx_WakeupCallback\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup HAL_LTDC_Aliased_Functions HAL LTDC Aliased Functions maintained for legacy purpose\r
+ * @{\r
+ */\r
+#define HAL_LTDC_LineEvenCallback HAL_LTDC_LineEventCallback\r
+#define HAL_LTDC_Relaod HAL_LTDC_Reload\r
+#define HAL_LTDC_StructInitFromVideoConfig HAL_LTDCEx_StructInitFromVideoConfig\r
+#define HAL_LTDC_StructInitFromAdaptedCommandConfig HAL_LTDCEx_StructInitFromAdaptedCommandConfig\r
+/**\r
+ * @}\r
+ */\r
+\r
+\r
+/** @defgroup HAL_PPP_Aliased_Functions HAL PPP Aliased Functions maintained for legacy purpose\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/* Exported macros ------------------------------------------------------------*/\r
+\r
+/** @defgroup HAL_AES_Aliased_Macros HAL CRYP Aliased Macros maintained for legacy purpose\r
+ * @{\r
+ */\r
+#define AES_IT_CC CRYP_IT_CC\r
+#define AES_IT_ERR CRYP_IT_ERR\r
+#define AES_FLAG_CCF CRYP_FLAG_CCF\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup HAL_Aliased_Macros HAL Generic Aliased Macros maintained for legacy purpose\r
+ * @{\r
+ */\r
+#define __HAL_GET_BOOT_MODE __HAL_SYSCFG_GET_BOOT_MODE\r
+#define __HAL_REMAPMEMORY_FLASH __HAL_SYSCFG_REMAPMEMORY_FLASH\r
+#define __HAL_REMAPMEMORY_SYSTEMFLASH __HAL_SYSCFG_REMAPMEMORY_SYSTEMFLASH\r
+#define __HAL_REMAPMEMORY_SRAM __HAL_SYSCFG_REMAPMEMORY_SRAM\r
+#define __HAL_REMAPMEMORY_FMC __HAL_SYSCFG_REMAPMEMORY_FMC\r
+#define __HAL_REMAPMEMORY_FMC_SDRAM __HAL_SYSCFG_REMAPMEMORY_FMC_SDRAM\r
+#define __HAL_REMAPMEMORY_FSMC __HAL_SYSCFG_REMAPMEMORY_FSMC\r
+#define __HAL_REMAPMEMORY_QUADSPI __HAL_SYSCFG_REMAPMEMORY_QUADSPI\r
+#define __HAL_FMC_BANK __HAL_SYSCFG_FMC_BANK\r
+#define __HAL_GET_FLAG __HAL_SYSCFG_GET_FLAG\r
+#define __HAL_CLEAR_FLAG __HAL_SYSCFG_CLEAR_FLAG\r
+#define __HAL_VREFINT_OUT_ENABLE __HAL_SYSCFG_VREFINT_OUT_ENABLE\r
+#define __HAL_VREFINT_OUT_DISABLE __HAL_SYSCFG_VREFINT_OUT_DISABLE\r
+#define __HAL_SYSCFG_SRAM2_WRP_ENABLE __HAL_SYSCFG_SRAM2_WRP_0_31_ENABLE\r
+\r
+#define SYSCFG_FLAG_VREF_READY SYSCFG_FLAG_VREFINT_READY\r
+#define SYSCFG_FLAG_RC48 RCC_FLAG_HSI48\r
+#define IS_SYSCFG_FASTMODEPLUS_CONFIG IS_I2C_FASTMODEPLUS\r
+#define UFB_MODE_BitNumber UFB_MODE_BIT_NUMBER\r
+#define CMP_PD_BitNumber CMP_PD_BIT_NUMBER\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+\r
+/** @defgroup HAL_ADC_Aliased_Macros HAL ADC Aliased Macros maintained for legacy purpose\r
+ * @{\r
+ */\r
+#define __ADC_ENABLE __HAL_ADC_ENABLE\r
+#define __ADC_DISABLE __HAL_ADC_DISABLE\r
+#define __HAL_ADC_ENABLING_CONDITIONS ADC_ENABLING_CONDITIONS\r
+#define __HAL_ADC_DISABLING_CONDITIONS ADC_DISABLING_CONDITIONS\r
+#define __HAL_ADC_IS_ENABLED ADC_IS_ENABLE\r
+#define __ADC_IS_ENABLED ADC_IS_ENABLE\r
+#define __HAL_ADC_IS_SOFTWARE_START_REGULAR ADC_IS_SOFTWARE_START_REGULAR\r
+#define __HAL_ADC_IS_SOFTWARE_START_INJECTED ADC_IS_SOFTWARE_START_INJECTED\r
+#define __HAL_ADC_IS_CONVERSION_ONGOING_REGULAR_INJECTED ADC_IS_CONVERSION_ONGOING_REGULAR_INJECTED\r
+#define __HAL_ADC_IS_CONVERSION_ONGOING_REGULAR ADC_IS_CONVERSION_ONGOING_REGULAR\r
+#define __HAL_ADC_IS_CONVERSION_ONGOING_INJECTED ADC_IS_CONVERSION_ONGOING_INJECTED\r
+#define __HAL_ADC_IS_CONVERSION_ONGOING ADC_IS_CONVERSION_ONGOING\r
+#define __HAL_ADC_CLEAR_ERRORCODE ADC_CLEAR_ERRORCODE\r
+\r
+#define __HAL_ADC_GET_RESOLUTION ADC_GET_RESOLUTION\r
+#define __HAL_ADC_JSQR_RK ADC_JSQR_RK\r
+#define __HAL_ADC_CFGR_AWD1CH ADC_CFGR_AWD1CH_SHIFT\r
+#define __HAL_ADC_CFGR_AWD23CR ADC_CFGR_AWD23CR\r
+#define __HAL_ADC_CFGR_INJECT_AUTO_CONVERSION ADC_CFGR_INJECT_AUTO_CONVERSION\r
+#define __HAL_ADC_CFGR_INJECT_CONTEXT_QUEUE ADC_CFGR_INJECT_CONTEXT_QUEUE\r
+#define __HAL_ADC_CFGR_INJECT_DISCCONTINUOUS ADC_CFGR_INJECT_DISCCONTINUOUS\r
+#define __HAL_ADC_CFGR_REG_DISCCONTINUOUS ADC_CFGR_REG_DISCCONTINUOUS\r
+#define __HAL_ADC_CFGR_DISCONTINUOUS_NUM ADC_CFGR_DISCONTINUOUS_NUM\r
+#define __HAL_ADC_CFGR_AUTOWAIT ADC_CFGR_AUTOWAIT\r
+#define __HAL_ADC_CFGR_CONTINUOUS ADC_CFGR_CONTINUOUS\r
+#define __HAL_ADC_CFGR_OVERRUN ADC_CFGR_OVERRUN\r
+#define __HAL_ADC_CFGR_DMACONTREQ ADC_CFGR_DMACONTREQ\r
+#define __HAL_ADC_CFGR_EXTSEL ADC_CFGR_EXTSEL_SET\r
+#define __HAL_ADC_JSQR_JEXTSEL ADC_JSQR_JEXTSEL_SET\r
+#define __HAL_ADC_OFR_CHANNEL ADC_OFR_CHANNEL\r
+#define __HAL_ADC_DIFSEL_CHANNEL ADC_DIFSEL_CHANNEL\r
+#define __HAL_ADC_CALFACT_DIFF_SET ADC_CALFACT_DIFF_SET\r
+#define __HAL_ADC_CALFACT_DIFF_GET ADC_CALFACT_DIFF_GET\r
+#define __HAL_ADC_TRX_HIGHTHRESHOLD ADC_TRX_HIGHTHRESHOLD\r
+\r
+#define __HAL_ADC_OFFSET_SHIFT_RESOLUTION ADC_OFFSET_SHIFT_RESOLUTION\r
+#define __HAL_ADC_AWD1THRESHOLD_SHIFT_RESOLUTION ADC_AWD1THRESHOLD_SHIFT_RESOLUTION\r
+#define __HAL_ADC_AWD23THRESHOLD_SHIFT_RESOLUTION ADC_AWD23THRESHOLD_SHIFT_RESOLUTION\r
+#define __HAL_ADC_COMMON_REGISTER ADC_COMMON_REGISTER\r
+#define __HAL_ADC_COMMON_CCR_MULTI ADC_COMMON_CCR_MULTI\r
+#define __HAL_ADC_MULTIMODE_IS_ENABLED ADC_MULTIMODE_IS_ENABLE\r
+#define __ADC_MULTIMODE_IS_ENABLED ADC_MULTIMODE_IS_ENABLE\r
+#define __HAL_ADC_NONMULTIMODE_OR_MULTIMODEMASTER ADC_NONMULTIMODE_OR_MULTIMODEMASTER\r
+#define __HAL_ADC_COMMON_ADC_OTHER ADC_COMMON_ADC_OTHER\r
+#define __HAL_ADC_MULTI_SLAVE ADC_MULTI_SLAVE\r
+\r
+#define __HAL_ADC_SQR1_L ADC_SQR1_L_SHIFT\r
+#define __HAL_ADC_JSQR_JL ADC_JSQR_JL_SHIFT\r
+#define __HAL_ADC_JSQR_RK_JL ADC_JSQR_RK_JL\r
+#define __HAL_ADC_CR1_DISCONTINUOUS_NUM ADC_CR1_DISCONTINUOUS_NUM\r
+#define __HAL_ADC_CR1_SCAN ADC_CR1_SCAN_SET\r
+#define __HAL_ADC_CONVCYCLES_MAX_RANGE ADC_CONVCYCLES_MAX_RANGE\r
+#define __HAL_ADC_CLOCK_PRESCALER_RANGE ADC_CLOCK_PRESCALER_RANGE\r
+#define __HAL_ADC_GET_CLOCK_PRESCALER ADC_GET_CLOCK_PRESCALER\r
+\r
+#define __HAL_ADC_SQR1 ADC_SQR1\r
+#define __HAL_ADC_SMPR1 ADC_SMPR1\r
+#define __HAL_ADC_SMPR2 ADC_SMPR2\r
+#define __HAL_ADC_SQR3_RK ADC_SQR3_RK\r
+#define __HAL_ADC_SQR2_RK ADC_SQR2_RK\r
+#define __HAL_ADC_SQR1_RK ADC_SQR1_RK\r
+#define __HAL_ADC_CR2_CONTINUOUS ADC_CR2_CONTINUOUS\r
+#define __HAL_ADC_CR1_DISCONTINUOUS ADC_CR1_DISCONTINUOUS\r
+#define __HAL_ADC_CR1_SCANCONV ADC_CR1_SCANCONV\r
+#define __HAL_ADC_CR2_EOCSelection ADC_CR2_EOCSelection\r
+#define __HAL_ADC_CR2_DMAContReq ADC_CR2_DMAContReq\r
+#define __HAL_ADC_JSQR ADC_JSQR\r
+\r
+#define __HAL_ADC_CHSELR_CHANNEL ADC_CHSELR_CHANNEL\r
+#define __HAL_ADC_CFGR1_REG_DISCCONTINUOUS ADC_CFGR1_REG_DISCCONTINUOUS\r
+#define __HAL_ADC_CFGR1_AUTOOFF ADC_CFGR1_AUTOOFF\r
+#define __HAL_ADC_CFGR1_AUTOWAIT ADC_CFGR1_AUTOWAIT\r
+#define __HAL_ADC_CFGR1_CONTINUOUS ADC_CFGR1_CONTINUOUS\r
+#define __HAL_ADC_CFGR1_OVERRUN ADC_CFGR1_OVERRUN\r
+#define __HAL_ADC_CFGR1_SCANDIR ADC_CFGR1_SCANDIR\r
+#define __HAL_ADC_CFGR1_DMACONTREQ ADC_CFGR1_DMACONTREQ\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup HAL_DAC_Aliased_Macros HAL DAC Aliased Macros maintained for legacy purpose\r
+ * @{\r
+ */\r
+#define __HAL_DHR12R1_ALIGNEMENT DAC_DHR12R1_ALIGNMENT\r
+#define __HAL_DHR12R2_ALIGNEMENT DAC_DHR12R2_ALIGNMENT\r
+#define __HAL_DHR12RD_ALIGNEMENT DAC_DHR12RD_ALIGNMENT\r
+#define IS_DAC_GENERATE_WAVE IS_DAC_WAVE\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup HAL_DBGMCU_Aliased_Macros HAL DBGMCU Aliased Macros maintained for legacy purpose\r
+ * @{\r
+ */\r
+#define __HAL_FREEZE_TIM1_DBGMCU __HAL_DBGMCU_FREEZE_TIM1\r
+#define __HAL_UNFREEZE_TIM1_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM1\r
+#define __HAL_FREEZE_TIM2_DBGMCU __HAL_DBGMCU_FREEZE_TIM2\r
+#define __HAL_UNFREEZE_TIM2_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM2\r
+#define __HAL_FREEZE_TIM3_DBGMCU __HAL_DBGMCU_FREEZE_TIM3\r
+#define __HAL_UNFREEZE_TIM3_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM3\r
+#define __HAL_FREEZE_TIM4_DBGMCU __HAL_DBGMCU_FREEZE_TIM4\r
+#define __HAL_UNFREEZE_TIM4_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM4\r
+#define __HAL_FREEZE_TIM5_DBGMCU __HAL_DBGMCU_FREEZE_TIM5\r
+#define __HAL_UNFREEZE_TIM5_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM5\r
+#define __HAL_FREEZE_TIM6_DBGMCU __HAL_DBGMCU_FREEZE_TIM6\r
+#define __HAL_UNFREEZE_TIM6_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM6\r
+#define __HAL_FREEZE_TIM7_DBGMCU __HAL_DBGMCU_FREEZE_TIM7\r
+#define __HAL_UNFREEZE_TIM7_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM7\r
+#define __HAL_FREEZE_TIM8_DBGMCU __HAL_DBGMCU_FREEZE_TIM8\r
+#define __HAL_UNFREEZE_TIM8_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM8\r
+\r
+#define __HAL_FREEZE_TIM9_DBGMCU __HAL_DBGMCU_FREEZE_TIM9\r
+#define __HAL_UNFREEZE_TIM9_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM9\r
+#define __HAL_FREEZE_TIM10_DBGMCU __HAL_DBGMCU_FREEZE_TIM10\r
+#define __HAL_UNFREEZE_TIM10_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM10\r
+#define __HAL_FREEZE_TIM11_DBGMCU __HAL_DBGMCU_FREEZE_TIM11\r
+#define __HAL_UNFREEZE_TIM11_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM11\r
+#define __HAL_FREEZE_TIM12_DBGMCU __HAL_DBGMCU_FREEZE_TIM12\r
+#define __HAL_UNFREEZE_TIM12_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM12\r
+#define __HAL_FREEZE_TIM13_DBGMCU __HAL_DBGMCU_FREEZE_TIM13\r
+#define __HAL_UNFREEZE_TIM13_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM13\r
+#define __HAL_FREEZE_TIM14_DBGMCU __HAL_DBGMCU_FREEZE_TIM14\r
+#define __HAL_UNFREEZE_TIM14_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM14\r
+#define __HAL_FREEZE_CAN2_DBGMCU __HAL_DBGMCU_FREEZE_CAN2\r
+#define __HAL_UNFREEZE_CAN2_DBGMCU __HAL_DBGMCU_UNFREEZE_CAN2\r
+\r
+\r
+#define __HAL_FREEZE_TIM15_DBGMCU __HAL_DBGMCU_FREEZE_TIM15\r
+#define __HAL_UNFREEZE_TIM15_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM15\r
+#define __HAL_FREEZE_TIM16_DBGMCU __HAL_DBGMCU_FREEZE_TIM16\r
+#define __HAL_UNFREEZE_TIM16_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM16\r
+#define __HAL_FREEZE_TIM17_DBGMCU __HAL_DBGMCU_FREEZE_TIM17\r
+#define __HAL_UNFREEZE_TIM17_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM17\r
+#define __HAL_FREEZE_RTC_DBGMCU __HAL_DBGMCU_FREEZE_RTC\r
+#define __HAL_UNFREEZE_RTC_DBGMCU __HAL_DBGMCU_UNFREEZE_RTC\r
+#if defined(STM32H7)\r
+ #define __HAL_FREEZE_WWDG_DBGMCU __HAL_DBGMCU_FREEZE_WWDG1\r
+ #define __HAL_UNFREEZE_WWDG_DBGMCU __HAL_DBGMCU_UnFreeze_WWDG1\r
+ #define __HAL_FREEZE_IWDG_DBGMCU __HAL_DBGMCU_FREEZE_IWDG1\r
+ #define __HAL_UNFREEZE_IWDG_DBGMCU __HAL_DBGMCU_UnFreeze_IWDG1\r
+#else\r
+ #define __HAL_FREEZE_WWDG_DBGMCU __HAL_DBGMCU_FREEZE_WWDG\r
+ #define __HAL_UNFREEZE_WWDG_DBGMCU __HAL_DBGMCU_UNFREEZE_WWDG\r
+ #define __HAL_FREEZE_IWDG_DBGMCU __HAL_DBGMCU_FREEZE_IWDG\r
+ #define __HAL_UNFREEZE_IWDG_DBGMCU __HAL_DBGMCU_UNFREEZE_IWDG\r
+#endif /* STM32H7 */\r
+#define __HAL_FREEZE_I2C1_TIMEOUT_DBGMCU __HAL_DBGMCU_FREEZE_I2C1_TIMEOUT\r
+#define __HAL_UNFREEZE_I2C1_TIMEOUT_DBGMCU __HAL_DBGMCU_UNFREEZE_I2C1_TIMEOUT\r
+#define __HAL_FREEZE_I2C2_TIMEOUT_DBGMCU __HAL_DBGMCU_FREEZE_I2C2_TIMEOUT\r
+#define __HAL_UNFREEZE_I2C2_TIMEOUT_DBGMCU __HAL_DBGMCU_UNFREEZE_I2C2_TIMEOUT\r
+#define __HAL_FREEZE_I2C3_TIMEOUT_DBGMCU __HAL_DBGMCU_FREEZE_I2C3_TIMEOUT\r
+#define __HAL_UNFREEZE_I2C3_TIMEOUT_DBGMCU __HAL_DBGMCU_UNFREEZE_I2C3_TIMEOUT\r
+#define __HAL_FREEZE_CAN1_DBGMCU __HAL_DBGMCU_FREEZE_CAN1\r
+#define __HAL_UNFREEZE_CAN1_DBGMCU __HAL_DBGMCU_UNFREEZE_CAN1\r
+#define __HAL_FREEZE_LPTIM1_DBGMCU __HAL_DBGMCU_FREEZE_LPTIM1\r
+#define __HAL_UNFREEZE_LPTIM1_DBGMCU __HAL_DBGMCU_UNFREEZE_LPTIM1\r
+#define __HAL_FREEZE_LPTIM2_DBGMCU __HAL_DBGMCU_FREEZE_LPTIM2\r
+#define __HAL_UNFREEZE_LPTIM2_DBGMCU __HAL_DBGMCU_UNFREEZE_LPTIM2\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup HAL_COMP_Aliased_Macros HAL COMP Aliased Macros maintained for legacy purpose\r
+ * @{\r
+ */\r
+#if defined(STM32F3)\r
+#define COMP_START __HAL_COMP_ENABLE\r
+#define COMP_STOP __HAL_COMP_DISABLE\r
+#define COMP_LOCK __HAL_COMP_LOCK\r
+\r
+#if defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx) || defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx)\r
+#define __HAL_COMP_EXTI_RISING_IT_ENABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_ENABLE_RISING_EDGE() : \\r
+ ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_ENABLE_RISING_EDGE() : \\r
+ __HAL_COMP_COMP6_EXTI_ENABLE_RISING_EDGE())\r
+#define __HAL_COMP_EXTI_RISING_IT_DISABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_DISABLE_RISING_EDGE() : \\r
+ ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_DISABLE_RISING_EDGE() : \\r
+ __HAL_COMP_COMP6_EXTI_DISABLE_RISING_EDGE())\r
+#define __HAL_COMP_EXTI_FALLING_IT_ENABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_ENABLE_FALLING_EDGE() : \\r
+ ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_ENABLE_FALLING_EDGE() : \\r
+ __HAL_COMP_COMP6_EXTI_ENABLE_FALLING_EDGE())\r
+#define __HAL_COMP_EXTI_FALLING_IT_DISABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_DISABLE_FALLING_EDGE() : \\r
+ ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_DISABLE_FALLING_EDGE() : \\r
+ __HAL_COMP_COMP6_EXTI_DISABLE_FALLING_EDGE())\r
+#define __HAL_COMP_EXTI_ENABLE_IT(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_ENABLE_IT() : \\r
+ ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_ENABLE_IT() : \\r
+ __HAL_COMP_COMP6_EXTI_ENABLE_IT())\r
+#define __HAL_COMP_EXTI_DISABLE_IT(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_DISABLE_IT() : \\r
+ ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_DISABLE_IT() : \\r
+ __HAL_COMP_COMP6_EXTI_DISABLE_IT())\r
+#define __HAL_COMP_EXTI_GET_FLAG(__FLAG__) (((__FLAG__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_GET_FLAG() : \\r
+ ((__FLAG__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_GET_FLAG() : \\r
+ __HAL_COMP_COMP6_EXTI_GET_FLAG())\r
+#define __HAL_COMP_EXTI_CLEAR_FLAG(__FLAG__) (((__FLAG__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_CLEAR_FLAG() : \\r
+ ((__FLAG__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_CLEAR_FLAG() : \\r
+ __HAL_COMP_COMP6_EXTI_CLEAR_FLAG())\r
+# endif\r
+# if defined(STM32F302xE) || defined(STM32F302xC)\r
+#define __HAL_COMP_EXTI_RISING_IT_ENABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_RISING_EDGE() : \\r
+ ((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_ENABLE_RISING_EDGE() : \\r
+ ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_ENABLE_RISING_EDGE() : \\r
+ __HAL_COMP_COMP6_EXTI_ENABLE_RISING_EDGE())\r
+#define __HAL_COMP_EXTI_RISING_IT_DISABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_RISING_EDGE() : \\r
+ ((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_DISABLE_RISING_EDGE() : \\r
+ ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_DISABLE_RISING_EDGE() : \\r
+ __HAL_COMP_COMP6_EXTI_DISABLE_RISING_EDGE())\r
+#define __HAL_COMP_EXTI_FALLING_IT_ENABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_FALLING_EDGE() : \\r
+ ((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_ENABLE_FALLING_EDGE() : \\r
+ ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_ENABLE_FALLING_EDGE() : \\r
+ __HAL_COMP_COMP6_EXTI_ENABLE_FALLING_EDGE())\r
+#define __HAL_COMP_EXTI_FALLING_IT_DISABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_FALLING_EDGE() : \\r
+ ((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_DISABLE_FALLING_EDGE() : \\r
+ ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_DISABLE_FALLING_EDGE() : \\r
+ __HAL_COMP_COMP6_EXTI_DISABLE_FALLING_EDGE())\r
+#define __HAL_COMP_EXTI_ENABLE_IT(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_IT() : \\r
+ ((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_ENABLE_IT() : \\r
+ ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_ENABLE_IT() : \\r
+ __HAL_COMP_COMP6_EXTI_ENABLE_IT())\r
+#define __HAL_COMP_EXTI_DISABLE_IT(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_IT() : \\r
+ ((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_DISABLE_IT() : \\r
+ ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_DISABLE_IT() : \\r
+ __HAL_COMP_COMP6_EXTI_DISABLE_IT())\r
+#define __HAL_COMP_EXTI_GET_FLAG(__FLAG__) (((__FLAG__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_GET_FLAG() : \\r
+ ((__FLAG__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_GET_FLAG() : \\r
+ ((__FLAG__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_GET_FLAG() : \\r
+ __HAL_COMP_COMP6_EXTI_GET_FLAG())\r
+#define __HAL_COMP_EXTI_CLEAR_FLAG(__FLAG__) (((__FLAG__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_CLEAR_FLAG() : \\r
+ ((__FLAG__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_CLEAR_FLAG() : \\r
+ ((__FLAG__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_CLEAR_FLAG() : \\r
+ __HAL_COMP_COMP6_EXTI_CLEAR_FLAG())\r
+# endif\r
+# if defined(STM32F303xE) || defined(STM32F398xx) || defined(STM32F303xC) || defined(STM32F358xx)\r
+#define __HAL_COMP_EXTI_RISING_IT_ENABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_RISING_EDGE() : \\r
+ ((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_ENABLE_RISING_EDGE() : \\r
+ ((__EXTILINE__) == COMP_EXTI_LINE_COMP3) ? __HAL_COMP_COMP3_EXTI_ENABLE_RISING_EDGE() : \\r
+ ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_ENABLE_RISING_EDGE() : \\r
+ ((__EXTILINE__) == COMP_EXTI_LINE_COMP5) ? __HAL_COMP_COMP5_EXTI_ENABLE_RISING_EDGE() : \\r
+ ((__EXTILINE__) == COMP_EXTI_LINE_COMP6) ? __HAL_COMP_COMP6_EXTI_ENABLE_RISING_EDGE() : \\r
+ __HAL_COMP_COMP7_EXTI_ENABLE_RISING_EDGE())\r
+#define __HAL_COMP_EXTI_RISING_IT_DISABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_RISING_EDGE() : \\r
+ ((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_DISABLE_RISING_EDGE() : \\r
+ ((__EXTILINE__) == COMP_EXTI_LINE_COMP3) ? __HAL_COMP_COMP3_EXTI_DISABLE_RISING_EDGE() : \\r
+ ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_DISABLE_RISING_EDGE() : \\r
+ ((__EXTILINE__) == COMP_EXTI_LINE_COMP5) ? __HAL_COMP_COMP5_EXTI_DISABLE_RISING_EDGE() : \\r
+ ((__EXTILINE__) == COMP_EXTI_LINE_COMP6) ? __HAL_COMP_COMP6_EXTI_DISABLE_RISING_EDGE() : \\r
+ __HAL_COMP_COMP7_EXTI_DISABLE_RISING_EDGE())\r
+#define __HAL_COMP_EXTI_FALLING_IT_ENABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_FALLING_EDGE() : \\r
+ ((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_ENABLE_FALLING_EDGE() : \\r
+ ((__EXTILINE__) == COMP_EXTI_LINE_COMP3) ? __HAL_COMP_COMP3_EXTI_ENABLE_FALLING_EDGE() : \\r
+ ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_ENABLE_FALLING_EDGE() : \\r
+ ((__EXTILINE__) == COMP_EXTI_LINE_COMP5) ? __HAL_COMP_COMP5_EXTI_ENABLE_FALLING_EDGE() : \\r
+ ((__EXTILINE__) == COMP_EXTI_LINE_COMP6) ? __HAL_COMP_COMP6_EXTI_ENABLE_FALLING_EDGE() : \\r
+ __HAL_COMP_COMP7_EXTI_ENABLE_FALLING_EDGE())\r
+#define __HAL_COMP_EXTI_FALLING_IT_DISABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_FALLING_EDGE() : \\r
+ ((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_DISABLE_FALLING_EDGE() : \\r
+ ((__EXTILINE__) == COMP_EXTI_LINE_COMP3) ? __HAL_COMP_COMP3_EXTI_DISABLE_FALLING_EDGE() : \\r
+ ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_DISABLE_FALLING_EDGE() : \\r
+ ((__EXTILINE__) == COMP_EXTI_LINE_COMP5) ? __HAL_COMP_COMP5_EXTI_DISABLE_FALLING_EDGE() : \\r
+ ((__EXTILINE__) == COMP_EXTI_LINE_COMP6) ? __HAL_COMP_COMP6_EXTI_DISABLE_FALLING_EDGE() : \\r
+ __HAL_COMP_COMP7_EXTI_DISABLE_FALLING_EDGE())\r
+#define __HAL_COMP_EXTI_ENABLE_IT(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_IT() : \\r
+ ((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_ENABLE_IT() : \\r
+ ((__EXTILINE__) == COMP_EXTI_LINE_COMP3) ? __HAL_COMP_COMP3_EXTI_ENABLE_IT() : \\r
+ ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_ENABLE_IT() : \\r
+ ((__EXTILINE__) == COMP_EXTI_LINE_COMP5) ? __HAL_COMP_COMP5_EXTI_ENABLE_IT() : \\r
+ ((__EXTILINE__) == COMP_EXTI_LINE_COMP6) ? __HAL_COMP_COMP6_EXTI_ENABLE_IT() : \\r
+ __HAL_COMP_COMP7_EXTI_ENABLE_IT())\r
+#define __HAL_COMP_EXTI_DISABLE_IT(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_IT() : \\r
+ ((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_DISABLE_IT() : \\r
+ ((__EXTILINE__) == COMP_EXTI_LINE_COMP3) ? __HAL_COMP_COMP3_EXTI_DISABLE_IT() : \\r
+ ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_DISABLE_IT() : \\r
+ ((__EXTILINE__) == COMP_EXTI_LINE_COMP5) ? __HAL_COMP_COMP5_EXTI_DISABLE_IT() : \\r
+ ((__EXTILINE__) == COMP_EXTI_LINE_COMP6) ? __HAL_COMP_COMP6_EXTI_DISABLE_IT() : \\r
+ __HAL_COMP_COMP7_EXTI_DISABLE_IT())\r
+#define __HAL_COMP_EXTI_GET_FLAG(__FLAG__) (((__FLAG__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_GET_FLAG() : \\r
+ ((__FLAG__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_GET_FLAG() : \\r
+ ((__FLAG__) == COMP_EXTI_LINE_COMP3) ? __HAL_COMP_COMP3_EXTI_GET_FLAG() : \\r
+ ((__FLAG__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_GET_FLAG() : \\r
+ ((__FLAG__) == COMP_EXTI_LINE_COMP5) ? __HAL_COMP_COMP5_EXTI_GET_FLAG() : \\r
+ ((__FLAG__) == COMP_EXTI_LINE_COMP6) ? __HAL_COMP_COMP6_EXTI_GET_FLAG() : \\r
+ __HAL_COMP_COMP7_EXTI_GET_FLAG())\r
+#define __HAL_COMP_EXTI_CLEAR_FLAG(__FLAG__) (((__FLAG__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_CLEAR_FLAG() : \\r
+ ((__FLAG__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_CLEAR_FLAG() : \\r
+ ((__FLAG__) == COMP_EXTI_LINE_COMP3) ? __HAL_COMP_COMP3_EXTI_CLEAR_FLAG() : \\r
+ ((__FLAG__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_CLEAR_FLAG() : \\r
+ ((__FLAG__) == COMP_EXTI_LINE_COMP5) ? __HAL_COMP_COMP5_EXTI_CLEAR_FLAG() : \\r
+ ((__FLAG__) == COMP_EXTI_LINE_COMP6) ? __HAL_COMP_COMP6_EXTI_CLEAR_FLAG() : \\r
+ __HAL_COMP_COMP7_EXTI_CLEAR_FLAG())\r
+# endif\r
+# if defined(STM32F373xC) ||defined(STM32F378xx)\r
+#define __HAL_COMP_EXTI_RISING_IT_ENABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_RISING_EDGE() : \\r
+ __HAL_COMP_COMP2_EXTI_ENABLE_RISING_EDGE())\r
+#define __HAL_COMP_EXTI_RISING_IT_DISABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_RISING_EDGE() : \\r
+ __HAL_COMP_COMP2_EXTI_DISABLE_RISING_EDGE())\r
+#define __HAL_COMP_EXTI_FALLING_IT_ENABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_FALLING_EDGE() : \\r
+ __HAL_COMP_COMP2_EXTI_ENABLE_FALLING_EDGE())\r
+#define __HAL_COMP_EXTI_FALLING_IT_DISABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_FALLING_EDGE() : \\r
+ __HAL_COMP_COMP2_EXTI_DISABLE_FALLING_EDGE())\r
+#define __HAL_COMP_EXTI_ENABLE_IT(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_IT() : \\r
+ __HAL_COMP_COMP2_EXTI_ENABLE_IT())\r
+#define __HAL_COMP_EXTI_DISABLE_IT(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_IT() : \\r
+ __HAL_COMP_COMP2_EXTI_DISABLE_IT())\r
+#define __HAL_COMP_EXTI_GET_FLAG(__FLAG__) (((__FLAG__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_GET_FLAG() : \\r
+ __HAL_COMP_COMP2_EXTI_GET_FLAG())\r
+#define __HAL_COMP_EXTI_CLEAR_FLAG(__FLAG__) (((__FLAG__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_CLEAR_FLAG() : \\r
+ __HAL_COMP_COMP2_EXTI_CLEAR_FLAG())\r
+# endif\r
+#else\r
+#define __HAL_COMP_EXTI_RISING_IT_ENABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_RISING_EDGE() : \\r
+ __HAL_COMP_COMP2_EXTI_ENABLE_RISING_EDGE())\r
+#define __HAL_COMP_EXTI_RISING_IT_DISABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_RISING_EDGE() : \\r
+ __HAL_COMP_COMP2_EXTI_DISABLE_RISING_EDGE())\r
+#define __HAL_COMP_EXTI_FALLING_IT_ENABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_FALLING_EDGE() : \\r
+ __HAL_COMP_COMP2_EXTI_ENABLE_FALLING_EDGE())\r
+#define __HAL_COMP_EXTI_FALLING_IT_DISABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_FALLING_EDGE() : \\r
+ __HAL_COMP_COMP2_EXTI_DISABLE_FALLING_EDGE())\r
+#define __HAL_COMP_EXTI_ENABLE_IT(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_IT() : \\r
+ __HAL_COMP_COMP2_EXTI_ENABLE_IT())\r
+#define __HAL_COMP_EXTI_DISABLE_IT(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_IT() : \\r
+ __HAL_COMP_COMP2_EXTI_DISABLE_IT())\r
+#define __HAL_COMP_EXTI_GET_FLAG(__FLAG__) (((__FLAG__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_GET_FLAG() : \\r
+ __HAL_COMP_COMP2_EXTI_GET_FLAG())\r
+#define __HAL_COMP_EXTI_CLEAR_FLAG(__FLAG__) (((__FLAG__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_CLEAR_FLAG() : \\r
+ __HAL_COMP_COMP2_EXTI_CLEAR_FLAG())\r
+#endif\r
+\r
+#define __HAL_COMP_GET_EXTI_LINE COMP_GET_EXTI_LINE\r
+\r
+#if defined(STM32L0) || defined(STM32L4)\r
+/* Note: On these STM32 families, the only argument of this macro */\r
+/* is COMP_FLAG_LOCK. */\r
+/* This macro is replaced by __HAL_COMP_IS_LOCKED with only HAL handle */\r
+/* argument. */\r
+#define __HAL_COMP_GET_FLAG(__HANDLE__, __FLAG__) (__HAL_COMP_IS_LOCKED(__HANDLE__))\r
+#endif\r
+/**\r
+ * @}\r
+ */\r
+\r
+#if defined(STM32L0) || defined(STM32L4)\r
+/** @defgroup HAL_COMP_Aliased_Functions HAL COMP Aliased Functions maintained for legacy purpose\r
+ * @{\r
+ */\r
+#define HAL_COMP_Start_IT HAL_COMP_Start /* Function considered as legacy as EXTI event or IT configuration is done into HAL_COMP_Init() */\r
+#define HAL_COMP_Stop_IT HAL_COMP_Stop /* Function considered as legacy as EXTI event or IT configuration is done into HAL_COMP_Init() */\r
+/**\r
+ * @}\r
+ */\r
+#endif\r
+\r
+/** @defgroup HAL_DAC_Aliased_Macros HAL DAC Aliased Macros maintained for legacy purpose\r
+ * @{\r
+ */\r
+\r
+#define IS_DAC_WAVE(WAVE) (((WAVE) == DAC_WAVE_NONE) || \\r
+ ((WAVE) == DAC_WAVE_NOISE)|| \\r
+ ((WAVE) == DAC_WAVE_TRIANGLE))\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup HAL_FLASH_Aliased_Macros HAL FLASH Aliased Macros maintained for legacy purpose\r
+ * @{\r
+ */\r
+\r
+#define IS_WRPAREA IS_OB_WRPAREA\r
+#define IS_TYPEPROGRAM IS_FLASH_TYPEPROGRAM\r
+#define IS_TYPEPROGRAMFLASH IS_FLASH_TYPEPROGRAM\r
+#define IS_TYPEERASE IS_FLASH_TYPEERASE\r
+#define IS_NBSECTORS IS_FLASH_NBSECTORS\r
+#define IS_OB_WDG_SOURCE IS_OB_IWDG_SOURCE\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup HAL_I2C_Aliased_Macros HAL I2C Aliased Macros maintained for legacy purpose\r
+ * @{\r
+ */\r
+\r
+#define __HAL_I2C_RESET_CR2 I2C_RESET_CR2\r
+#define __HAL_I2C_GENERATE_START I2C_GENERATE_START\r
+#if defined(STM32F1)\r
+#define __HAL_I2C_FREQ_RANGE I2C_FREQRANGE\r
+#else\r
+#define __HAL_I2C_FREQ_RANGE I2C_FREQ_RANGE\r
+#endif /* STM32F1 */\r
+#define __HAL_I2C_RISE_TIME I2C_RISE_TIME\r
+#define __HAL_I2C_SPEED_STANDARD I2C_SPEED_STANDARD\r
+#define __HAL_I2C_SPEED_FAST I2C_SPEED_FAST\r
+#define __HAL_I2C_SPEED I2C_SPEED\r
+#define __HAL_I2C_7BIT_ADD_WRITE I2C_7BIT_ADD_WRITE\r
+#define __HAL_I2C_7BIT_ADD_READ I2C_7BIT_ADD_READ\r
+#define __HAL_I2C_10BIT_ADDRESS I2C_10BIT_ADDRESS\r
+#define __HAL_I2C_10BIT_HEADER_WRITE I2C_10BIT_HEADER_WRITE\r
+#define __HAL_I2C_10BIT_HEADER_READ I2C_10BIT_HEADER_READ\r
+#define __HAL_I2C_MEM_ADD_MSB I2C_MEM_ADD_MSB\r
+#define __HAL_I2C_MEM_ADD_LSB I2C_MEM_ADD_LSB\r
+#define __HAL_I2C_FREQRANGE I2C_FREQRANGE\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup HAL_I2S_Aliased_Macros HAL I2S Aliased Macros maintained for legacy purpose\r
+ * @{\r
+ */\r
+\r
+#define IS_I2S_INSTANCE IS_I2S_ALL_INSTANCE\r
+#define IS_I2S_INSTANCE_EXT IS_I2S_ALL_INSTANCE_EXT\r
+\r
+#if defined(STM32H7)\r
+ #define __HAL_I2S_CLEAR_FREFLAG __HAL_I2S_CLEAR_TIFREFLAG\r
+#endif\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup HAL_IRDA_Aliased_Macros HAL IRDA Aliased Macros maintained for legacy purpose\r
+ * @{\r
+ */\r
+\r
+#define __IRDA_DISABLE __HAL_IRDA_DISABLE\r
+#define __IRDA_ENABLE __HAL_IRDA_ENABLE\r
+\r
+#define __HAL_IRDA_GETCLOCKSOURCE IRDA_GETCLOCKSOURCE\r
+#define __HAL_IRDA_MASK_COMPUTATION IRDA_MASK_COMPUTATION\r
+#define __IRDA_GETCLOCKSOURCE IRDA_GETCLOCKSOURCE\r
+#define __IRDA_MASK_COMPUTATION IRDA_MASK_COMPUTATION\r
+\r
+#define IS_IRDA_ONEBIT_SAMPLE IS_IRDA_ONE_BIT_SAMPLE\r
+\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+\r
+/** @defgroup HAL_IWDG_Aliased_Macros HAL IWDG Aliased Macros maintained for legacy purpose\r
+ * @{\r
+ */\r
+#define __HAL_IWDG_ENABLE_WRITE_ACCESS IWDG_ENABLE_WRITE_ACCESS\r
+#define __HAL_IWDG_DISABLE_WRITE_ACCESS IWDG_DISABLE_WRITE_ACCESS\r
+/**\r
+ * @}\r
+ */\r
+\r
+\r
+/** @defgroup HAL_LPTIM_Aliased_Macros HAL LPTIM Aliased Macros maintained for legacy purpose\r
+ * @{\r
+ */\r
+\r
+#define __HAL_LPTIM_ENABLE_INTERRUPT __HAL_LPTIM_ENABLE_IT\r
+#define __HAL_LPTIM_DISABLE_INTERRUPT __HAL_LPTIM_DISABLE_IT\r
+#define __HAL_LPTIM_GET_ITSTATUS __HAL_LPTIM_GET_IT_SOURCE\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+\r
+/** @defgroup HAL_OPAMP_Aliased_Macros HAL OPAMP Aliased Macros maintained for legacy purpose\r
+ * @{\r
+ */\r
+#define __OPAMP_CSR_OPAXPD OPAMP_CSR_OPAXPD\r
+#define __OPAMP_CSR_S3SELX OPAMP_CSR_S3SELX\r
+#define __OPAMP_CSR_S4SELX OPAMP_CSR_S4SELX\r
+#define __OPAMP_CSR_S5SELX OPAMP_CSR_S5SELX\r
+#define __OPAMP_CSR_S6SELX OPAMP_CSR_S6SELX\r
+#define __OPAMP_CSR_OPAXCAL_L OPAMP_CSR_OPAXCAL_L\r
+#define __OPAMP_CSR_OPAXCAL_H OPAMP_CSR_OPAXCAL_H\r
+#define __OPAMP_CSR_OPAXLPM OPAMP_CSR_OPAXLPM\r
+#define __OPAMP_CSR_ALL_SWITCHES OPAMP_CSR_ALL_SWITCHES\r
+#define __OPAMP_CSR_ANAWSELX OPAMP_CSR_ANAWSELX\r
+#define __OPAMP_CSR_OPAXCALOUT OPAMP_CSR_OPAXCALOUT\r
+#define __OPAMP_OFFSET_TRIM_BITSPOSITION OPAMP_OFFSET_TRIM_BITSPOSITION\r
+#define __OPAMP_OFFSET_TRIM_SET OPAMP_OFFSET_TRIM_SET\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+\r
+/** @defgroup HAL_PWR_Aliased_Macros HAL PWR Aliased Macros maintained for legacy purpose\r
+ * @{\r
+ */\r
+#define __HAL_PVD_EVENT_DISABLE __HAL_PWR_PVD_EXTI_DISABLE_EVENT\r
+#define __HAL_PVD_EVENT_ENABLE __HAL_PWR_PVD_EXTI_ENABLE_EVENT\r
+#define __HAL_PVD_EXTI_FALLINGTRIGGER_DISABLE __HAL_PWR_PVD_EXTI_DISABLE_FALLING_EDGE\r
+#define __HAL_PVD_EXTI_FALLINGTRIGGER_ENABLE __HAL_PWR_PVD_EXTI_ENABLE_FALLING_EDGE\r
+#define __HAL_PVD_EXTI_RISINGTRIGGER_DISABLE __HAL_PWR_PVD_EXTI_DISABLE_RISING_EDGE\r
+#define __HAL_PVD_EXTI_RISINGTRIGGER_ENABLE __HAL_PWR_PVD_EXTI_ENABLE_RISING_EDGE\r
+#define __HAL_PVM_EVENT_DISABLE __HAL_PWR_PVM_EVENT_DISABLE\r
+#define __HAL_PVM_EVENT_ENABLE __HAL_PWR_PVM_EVENT_ENABLE\r
+#define __HAL_PVM_EXTI_FALLINGTRIGGER_DISABLE __HAL_PWR_PVM_EXTI_FALLINGTRIGGER_DISABLE\r
+#define __HAL_PVM_EXTI_FALLINGTRIGGER_ENABLE __HAL_PWR_PVM_EXTI_FALLINGTRIGGER_ENABLE\r
+#define __HAL_PVM_EXTI_RISINGTRIGGER_DISABLE __HAL_PWR_PVM_EXTI_RISINGTRIGGER_DISABLE\r
+#define __HAL_PVM_EXTI_RISINGTRIGGER_ENABLE __HAL_PWR_PVM_EXTI_RISINGTRIGGER_ENABLE\r
+#define __HAL_PWR_INTERNALWAKEUP_DISABLE HAL_PWREx_DisableInternalWakeUpLine\r
+#define __HAL_PWR_INTERNALWAKEUP_ENABLE HAL_PWREx_EnableInternalWakeUpLine\r
+#define __HAL_PWR_PULL_UP_DOWN_CONFIG_DISABLE HAL_PWREx_DisablePullUpPullDownConfig\r
+#define __HAL_PWR_PULL_UP_DOWN_CONFIG_ENABLE HAL_PWREx_EnablePullUpPullDownConfig\r
+#define __HAL_PWR_PVD_EXTI_CLEAR_EGDE_TRIGGER() do { __HAL_PWR_PVD_EXTI_DISABLE_RISING_EDGE();__HAL_PWR_PVD_EXTI_DISABLE_FALLING_EDGE(); } while(0)\r
+#define __HAL_PWR_PVD_EXTI_EVENT_DISABLE __HAL_PWR_PVD_EXTI_DISABLE_EVENT\r
+#define __HAL_PWR_PVD_EXTI_EVENT_ENABLE __HAL_PWR_PVD_EXTI_ENABLE_EVENT\r
+#define __HAL_PWR_PVD_EXTI_FALLINGTRIGGER_DISABLE __HAL_PWR_PVD_EXTI_DISABLE_FALLING_EDGE\r
+#define __HAL_PWR_PVD_EXTI_FALLINGTRIGGER_ENABLE __HAL_PWR_PVD_EXTI_ENABLE_FALLING_EDGE\r
+#define __HAL_PWR_PVD_EXTI_RISINGTRIGGER_DISABLE __HAL_PWR_PVD_EXTI_DISABLE_RISING_EDGE\r
+#define __HAL_PWR_PVD_EXTI_RISINGTRIGGER_ENABLE __HAL_PWR_PVD_EXTI_ENABLE_RISING_EDGE\r
+#define __HAL_PWR_PVD_EXTI_SET_FALLING_EGDE_TRIGGER __HAL_PWR_PVD_EXTI_ENABLE_FALLING_EDGE\r
+#define __HAL_PWR_PVD_EXTI_SET_RISING_EDGE_TRIGGER __HAL_PWR_PVD_EXTI_ENABLE_RISING_EDGE\r
+#define __HAL_PWR_PVM_DISABLE() do { HAL_PWREx_DisablePVM1();HAL_PWREx_DisablePVM2();HAL_PWREx_DisablePVM3();HAL_PWREx_DisablePVM4(); } while(0)\r
+#define __HAL_PWR_PVM_ENABLE() do { HAL_PWREx_EnablePVM1();HAL_PWREx_EnablePVM2();HAL_PWREx_EnablePVM3();HAL_PWREx_EnablePVM4(); } while(0)\r
+#define __HAL_PWR_SRAM2CONTENT_PRESERVE_DISABLE HAL_PWREx_DisableSRAM2ContentRetention\r
+#define __HAL_PWR_SRAM2CONTENT_PRESERVE_ENABLE HAL_PWREx_EnableSRAM2ContentRetention\r
+#define __HAL_PWR_VDDIO2_DISABLE HAL_PWREx_DisableVddIO2\r
+#define __HAL_PWR_VDDIO2_ENABLE HAL_PWREx_EnableVddIO2\r
+#define __HAL_PWR_VDDIO2_EXTI_CLEAR_EGDE_TRIGGER __HAL_PWR_VDDIO2_EXTI_DISABLE_FALLING_EDGE\r
+#define __HAL_PWR_VDDIO2_EXTI_SET_FALLING_EGDE_TRIGGER __HAL_PWR_VDDIO2_EXTI_ENABLE_FALLING_EDGE\r
+#define __HAL_PWR_VDDUSB_DISABLE HAL_PWREx_DisableVddUSB\r
+#define __HAL_PWR_VDDUSB_ENABLE HAL_PWREx_EnableVddUSB\r
+\r
+#if defined (STM32F4)\r
+#define __HAL_PVD_EXTI_ENABLE_IT(PWR_EXTI_LINE_PVD) __HAL_PWR_PVD_EXTI_ENABLE_IT()\r
+#define __HAL_PVD_EXTI_DISABLE_IT(PWR_EXTI_LINE_PVD) __HAL_PWR_PVD_EXTI_DISABLE_IT()\r
+#define __HAL_PVD_EXTI_GET_FLAG(PWR_EXTI_LINE_PVD) __HAL_PWR_PVD_EXTI_GET_FLAG()\r
+#define __HAL_PVD_EXTI_CLEAR_FLAG(PWR_EXTI_LINE_PVD) __HAL_PWR_PVD_EXTI_CLEAR_FLAG()\r
+#define __HAL_PVD_EXTI_GENERATE_SWIT(PWR_EXTI_LINE_PVD) __HAL_PWR_PVD_EXTI_GENERATE_SWIT()\r
+#else\r
+#define __HAL_PVD_EXTI_CLEAR_FLAG __HAL_PWR_PVD_EXTI_CLEAR_FLAG\r
+#define __HAL_PVD_EXTI_DISABLE_IT __HAL_PWR_PVD_EXTI_DISABLE_IT\r
+#define __HAL_PVD_EXTI_ENABLE_IT __HAL_PWR_PVD_EXTI_ENABLE_IT\r
+#define __HAL_PVD_EXTI_GENERATE_SWIT __HAL_PWR_PVD_EXTI_GENERATE_SWIT\r
+#define __HAL_PVD_EXTI_GET_FLAG __HAL_PWR_PVD_EXTI_GET_FLAG\r
+#endif /* STM32F4 */\r
+/**\r
+ * @}\r
+ */\r
+\r
+\r
+/** @defgroup HAL_RCC_Aliased HAL RCC Aliased maintained for legacy purpose\r
+ * @{\r
+ */\r
+\r
+#define RCC_StopWakeUpClock_MSI RCC_STOP_WAKEUPCLOCK_MSI\r
+#define RCC_StopWakeUpClock_HSI RCC_STOP_WAKEUPCLOCK_HSI\r
+\r
+#define HAL_RCC_CCSCallback HAL_RCC_CSSCallback\r
+#define HAL_RC48_EnableBuffer_Cmd(cmd) (((cmd)==ENABLE) ? HAL_RCCEx_EnableHSI48_VREFINT() : HAL_RCCEx_DisableHSI48_VREFINT())\r
+\r
+#define __ADC_CLK_DISABLE __HAL_RCC_ADC_CLK_DISABLE\r
+#define __ADC_CLK_ENABLE __HAL_RCC_ADC_CLK_ENABLE\r
+#define __ADC_CLK_SLEEP_DISABLE __HAL_RCC_ADC_CLK_SLEEP_DISABLE\r
+#define __ADC_CLK_SLEEP_ENABLE __HAL_RCC_ADC_CLK_SLEEP_ENABLE\r
+#define __ADC_FORCE_RESET __HAL_RCC_ADC_FORCE_RESET\r
+#define __ADC_RELEASE_RESET __HAL_RCC_ADC_RELEASE_RESET\r
+#define __ADC1_CLK_DISABLE __HAL_RCC_ADC1_CLK_DISABLE\r
+#define __ADC1_CLK_ENABLE __HAL_RCC_ADC1_CLK_ENABLE\r
+#define __ADC1_FORCE_RESET __HAL_RCC_ADC1_FORCE_RESET\r
+#define __ADC1_RELEASE_RESET __HAL_RCC_ADC1_RELEASE_RESET\r
+#define __ADC1_CLK_SLEEP_ENABLE __HAL_RCC_ADC1_CLK_SLEEP_ENABLE\r
+#define __ADC1_CLK_SLEEP_DISABLE __HAL_RCC_ADC1_CLK_SLEEP_DISABLE\r
+#define __ADC2_CLK_DISABLE __HAL_RCC_ADC2_CLK_DISABLE\r
+#define __ADC2_CLK_ENABLE __HAL_RCC_ADC2_CLK_ENABLE\r
+#define __ADC2_FORCE_RESET __HAL_RCC_ADC2_FORCE_RESET\r
+#define __ADC2_RELEASE_RESET __HAL_RCC_ADC2_RELEASE_RESET\r
+#define __ADC3_CLK_DISABLE __HAL_RCC_ADC3_CLK_DISABLE\r
+#define __ADC3_CLK_ENABLE __HAL_RCC_ADC3_CLK_ENABLE\r
+#define __ADC3_FORCE_RESET __HAL_RCC_ADC3_FORCE_RESET\r
+#define __ADC3_RELEASE_RESET __HAL_RCC_ADC3_RELEASE_RESET\r
+#define __AES_CLK_DISABLE __HAL_RCC_AES_CLK_DISABLE\r
+#define __AES_CLK_ENABLE __HAL_RCC_AES_CLK_ENABLE\r
+#define __AES_CLK_SLEEP_DISABLE __HAL_RCC_AES_CLK_SLEEP_DISABLE\r
+#define __AES_CLK_SLEEP_ENABLE __HAL_RCC_AES_CLK_SLEEP_ENABLE\r
+#define __AES_FORCE_RESET __HAL_RCC_AES_FORCE_RESET\r
+#define __AES_RELEASE_RESET __HAL_RCC_AES_RELEASE_RESET\r
+#define __CRYP_CLK_SLEEP_ENABLE __HAL_RCC_CRYP_CLK_SLEEP_ENABLE\r
+#define __CRYP_CLK_SLEEP_DISABLE __HAL_RCC_CRYP_CLK_SLEEP_DISABLE\r
+#define __CRYP_CLK_ENABLE __HAL_RCC_CRYP_CLK_ENABLE\r
+#define __CRYP_CLK_DISABLE __HAL_RCC_CRYP_CLK_DISABLE\r
+#define __CRYP_FORCE_RESET __HAL_RCC_CRYP_FORCE_RESET\r
+#define __CRYP_RELEASE_RESET __HAL_RCC_CRYP_RELEASE_RESET\r
+#define __AFIO_CLK_DISABLE __HAL_RCC_AFIO_CLK_DISABLE\r
+#define __AFIO_CLK_ENABLE __HAL_RCC_AFIO_CLK_ENABLE\r
+#define __AFIO_FORCE_RESET __HAL_RCC_AFIO_FORCE_RESET\r
+#define __AFIO_RELEASE_RESET __HAL_RCC_AFIO_RELEASE_RESET\r
+#define __AHB_FORCE_RESET __HAL_RCC_AHB_FORCE_RESET\r
+#define __AHB_RELEASE_RESET __HAL_RCC_AHB_RELEASE_RESET\r
+#define __AHB1_FORCE_RESET __HAL_RCC_AHB1_FORCE_RESET\r
+#define __AHB1_RELEASE_RESET __HAL_RCC_AHB1_RELEASE_RESET\r
+#define __AHB2_FORCE_RESET __HAL_RCC_AHB2_FORCE_RESET\r
+#define __AHB2_RELEASE_RESET __HAL_RCC_AHB2_RELEASE_RESET\r
+#define __AHB3_FORCE_RESET __HAL_RCC_AHB3_FORCE_RESET\r
+#define __AHB3_RELEASE_RESET __HAL_RCC_AHB3_RELEASE_RESET\r
+#define __APB1_FORCE_RESET __HAL_RCC_APB1_FORCE_RESET\r
+#define __APB1_RELEASE_RESET __HAL_RCC_APB1_RELEASE_RESET\r
+#define __APB2_FORCE_RESET __HAL_RCC_APB2_FORCE_RESET\r
+#define __APB2_RELEASE_RESET __HAL_RCC_APB2_RELEASE_RESET\r
+#define __BKP_CLK_DISABLE __HAL_RCC_BKP_CLK_DISABLE\r
+#define __BKP_CLK_ENABLE __HAL_RCC_BKP_CLK_ENABLE\r
+#define __BKP_FORCE_RESET __HAL_RCC_BKP_FORCE_RESET\r
+#define __BKP_RELEASE_RESET __HAL_RCC_BKP_RELEASE_RESET\r
+#define __CAN1_CLK_DISABLE __HAL_RCC_CAN1_CLK_DISABLE\r
+#define __CAN1_CLK_ENABLE __HAL_RCC_CAN1_CLK_ENABLE\r
+#define __CAN1_CLK_SLEEP_DISABLE __HAL_RCC_CAN1_CLK_SLEEP_DISABLE\r
+#define __CAN1_CLK_SLEEP_ENABLE __HAL_RCC_CAN1_CLK_SLEEP_ENABLE\r
+#define __CAN1_FORCE_RESET __HAL_RCC_CAN1_FORCE_RESET\r
+#define __CAN1_RELEASE_RESET __HAL_RCC_CAN1_RELEASE_RESET\r
+#define __CAN_CLK_DISABLE __HAL_RCC_CAN1_CLK_DISABLE\r
+#define __CAN_CLK_ENABLE __HAL_RCC_CAN1_CLK_ENABLE\r
+#define __CAN_FORCE_RESET __HAL_RCC_CAN1_FORCE_RESET\r
+#define __CAN_RELEASE_RESET __HAL_RCC_CAN1_RELEASE_RESET\r
+#define __CAN2_CLK_DISABLE __HAL_RCC_CAN2_CLK_DISABLE\r
+#define __CAN2_CLK_ENABLE __HAL_RCC_CAN2_CLK_ENABLE\r
+#define __CAN2_FORCE_RESET __HAL_RCC_CAN2_FORCE_RESET\r
+#define __CAN2_RELEASE_RESET __HAL_RCC_CAN2_RELEASE_RESET\r
+#define __CEC_CLK_DISABLE __HAL_RCC_CEC_CLK_DISABLE\r
+#define __CEC_CLK_ENABLE __HAL_RCC_CEC_CLK_ENABLE\r
+#define __COMP_CLK_DISABLE __HAL_RCC_COMP_CLK_DISABLE\r
+#define __COMP_CLK_ENABLE __HAL_RCC_COMP_CLK_ENABLE\r
+#define __COMP_FORCE_RESET __HAL_RCC_COMP_FORCE_RESET\r
+#define __COMP_RELEASE_RESET __HAL_RCC_COMP_RELEASE_RESET\r
+#define __COMP_CLK_SLEEP_ENABLE __HAL_RCC_COMP_CLK_SLEEP_ENABLE\r
+#define __COMP_CLK_SLEEP_DISABLE __HAL_RCC_COMP_CLK_SLEEP_DISABLE\r
+#define __CEC_FORCE_RESET __HAL_RCC_CEC_FORCE_RESET\r
+#define __CEC_RELEASE_RESET __HAL_RCC_CEC_RELEASE_RESET\r
+#define __CRC_CLK_DISABLE __HAL_RCC_CRC_CLK_DISABLE\r
+#define __CRC_CLK_ENABLE __HAL_RCC_CRC_CLK_ENABLE\r
+#define __CRC_CLK_SLEEP_DISABLE __HAL_RCC_CRC_CLK_SLEEP_DISABLE\r
+#define __CRC_CLK_SLEEP_ENABLE __HAL_RCC_CRC_CLK_SLEEP_ENABLE\r
+#define __CRC_FORCE_RESET __HAL_RCC_CRC_FORCE_RESET\r
+#define __CRC_RELEASE_RESET __HAL_RCC_CRC_RELEASE_RESET\r
+#define __DAC_CLK_DISABLE __HAL_RCC_DAC_CLK_DISABLE\r
+#define __DAC_CLK_ENABLE __HAL_RCC_DAC_CLK_ENABLE\r
+#define __DAC_FORCE_RESET __HAL_RCC_DAC_FORCE_RESET\r
+#define __DAC_RELEASE_RESET __HAL_RCC_DAC_RELEASE_RESET\r
+#define __DAC1_CLK_DISABLE __HAL_RCC_DAC1_CLK_DISABLE\r
+#define __DAC1_CLK_ENABLE __HAL_RCC_DAC1_CLK_ENABLE\r
+#define __DAC1_CLK_SLEEP_DISABLE __HAL_RCC_DAC1_CLK_SLEEP_DISABLE\r
+#define __DAC1_CLK_SLEEP_ENABLE __HAL_RCC_DAC1_CLK_SLEEP_ENABLE\r
+#define __DAC1_FORCE_RESET __HAL_RCC_DAC1_FORCE_RESET\r
+#define __DAC1_RELEASE_RESET __HAL_RCC_DAC1_RELEASE_RESET\r
+#define __DBGMCU_CLK_ENABLE __HAL_RCC_DBGMCU_CLK_ENABLE\r
+#define __DBGMCU_CLK_DISABLE __HAL_RCC_DBGMCU_CLK_DISABLE\r
+#define __DBGMCU_FORCE_RESET __HAL_RCC_DBGMCU_FORCE_RESET\r
+#define __DBGMCU_RELEASE_RESET __HAL_RCC_DBGMCU_RELEASE_RESET\r
+#define __DFSDM_CLK_DISABLE __HAL_RCC_DFSDM_CLK_DISABLE\r
+#define __DFSDM_CLK_ENABLE __HAL_RCC_DFSDM_CLK_ENABLE\r
+#define __DFSDM_CLK_SLEEP_DISABLE __HAL_RCC_DFSDM_CLK_SLEEP_DISABLE\r
+#define __DFSDM_CLK_SLEEP_ENABLE __HAL_RCC_DFSDM_CLK_SLEEP_ENABLE\r
+#define __DFSDM_FORCE_RESET __HAL_RCC_DFSDM_FORCE_RESET\r
+#define __DFSDM_RELEASE_RESET __HAL_RCC_DFSDM_RELEASE_RESET\r
+#define __DMA1_CLK_DISABLE __HAL_RCC_DMA1_CLK_DISABLE\r
+#define __DMA1_CLK_ENABLE __HAL_RCC_DMA1_CLK_ENABLE\r
+#define __DMA1_CLK_SLEEP_DISABLE __HAL_RCC_DMA1_CLK_SLEEP_DISABLE\r
+#define __DMA1_CLK_SLEEP_ENABLE __HAL_RCC_DMA1_CLK_SLEEP_ENABLE\r
+#define __DMA1_FORCE_RESET __HAL_RCC_DMA1_FORCE_RESET\r
+#define __DMA1_RELEASE_RESET __HAL_RCC_DMA1_RELEASE_RESET\r
+#define __DMA2_CLK_DISABLE __HAL_RCC_DMA2_CLK_DISABLE\r
+#define __DMA2_CLK_ENABLE __HAL_RCC_DMA2_CLK_ENABLE\r
+#define __DMA2_CLK_SLEEP_DISABLE __HAL_RCC_DMA2_CLK_SLEEP_DISABLE\r
+#define __DMA2_CLK_SLEEP_ENABLE __HAL_RCC_DMA2_CLK_SLEEP_ENABLE\r
+#define __DMA2_FORCE_RESET __HAL_RCC_DMA2_FORCE_RESET\r
+#define __DMA2_RELEASE_RESET __HAL_RCC_DMA2_RELEASE_RESET\r
+#define __ETHMAC_CLK_DISABLE __HAL_RCC_ETHMAC_CLK_DISABLE\r
+#define __ETHMAC_CLK_ENABLE __HAL_RCC_ETHMAC_CLK_ENABLE\r
+#define __ETHMAC_FORCE_RESET __HAL_RCC_ETHMAC_FORCE_RESET\r
+#define __ETHMAC_RELEASE_RESET __HAL_RCC_ETHMAC_RELEASE_RESET\r
+#define __ETHMACRX_CLK_DISABLE __HAL_RCC_ETHMACRX_CLK_DISABLE\r
+#define __ETHMACRX_CLK_ENABLE __HAL_RCC_ETHMACRX_CLK_ENABLE\r
+#define __ETHMACTX_CLK_DISABLE __HAL_RCC_ETHMACTX_CLK_DISABLE\r
+#define __ETHMACTX_CLK_ENABLE __HAL_RCC_ETHMACTX_CLK_ENABLE\r
+#define __FIREWALL_CLK_DISABLE __HAL_RCC_FIREWALL_CLK_DISABLE\r
+#define __FIREWALL_CLK_ENABLE __HAL_RCC_FIREWALL_CLK_ENABLE\r
+#define __FLASH_CLK_DISABLE __HAL_RCC_FLASH_CLK_DISABLE\r
+#define __FLASH_CLK_ENABLE __HAL_RCC_FLASH_CLK_ENABLE\r
+#define __FLASH_CLK_SLEEP_DISABLE __HAL_RCC_FLASH_CLK_SLEEP_DISABLE\r
+#define __FLASH_CLK_SLEEP_ENABLE __HAL_RCC_FLASH_CLK_SLEEP_ENABLE\r
+#define __FLASH_FORCE_RESET __HAL_RCC_FLASH_FORCE_RESET\r
+#define __FLASH_RELEASE_RESET __HAL_RCC_FLASH_RELEASE_RESET\r
+#define __FLITF_CLK_DISABLE __HAL_RCC_FLITF_CLK_DISABLE\r
+#define __FLITF_CLK_ENABLE __HAL_RCC_FLITF_CLK_ENABLE\r
+#define __FLITF_FORCE_RESET __HAL_RCC_FLITF_FORCE_RESET\r
+#define __FLITF_RELEASE_RESET __HAL_RCC_FLITF_RELEASE_RESET\r
+#define __FLITF_CLK_SLEEP_ENABLE __HAL_RCC_FLITF_CLK_SLEEP_ENABLE\r
+#define __FLITF_CLK_SLEEP_DISABLE __HAL_RCC_FLITF_CLK_SLEEP_DISABLE\r
+#define __FMC_CLK_DISABLE __HAL_RCC_FMC_CLK_DISABLE\r
+#define __FMC_CLK_ENABLE __HAL_RCC_FMC_CLK_ENABLE\r
+#define __FMC_CLK_SLEEP_DISABLE __HAL_RCC_FMC_CLK_SLEEP_DISABLE\r
+#define __FMC_CLK_SLEEP_ENABLE __HAL_RCC_FMC_CLK_SLEEP_ENABLE\r
+#define __FMC_FORCE_RESET __HAL_RCC_FMC_FORCE_RESET\r
+#define __FMC_RELEASE_RESET __HAL_RCC_FMC_RELEASE_RESET\r
+#define __FSMC_CLK_DISABLE __HAL_RCC_FSMC_CLK_DISABLE\r
+#define __FSMC_CLK_ENABLE __HAL_RCC_FSMC_CLK_ENABLE\r
+#define __GPIOA_CLK_DISABLE __HAL_RCC_GPIOA_CLK_DISABLE\r
+#define __GPIOA_CLK_ENABLE __HAL_RCC_GPIOA_CLK_ENABLE\r
+#define __GPIOA_CLK_SLEEP_DISABLE __HAL_RCC_GPIOA_CLK_SLEEP_DISABLE\r
+#define __GPIOA_CLK_SLEEP_ENABLE __HAL_RCC_GPIOA_CLK_SLEEP_ENABLE\r
+#define __GPIOA_FORCE_RESET __HAL_RCC_GPIOA_FORCE_RESET\r
+#define __GPIOA_RELEASE_RESET __HAL_RCC_GPIOA_RELEASE_RESET\r
+#define __GPIOB_CLK_DISABLE __HAL_RCC_GPIOB_CLK_DISABLE\r
+#define __GPIOB_CLK_ENABLE __HAL_RCC_GPIOB_CLK_ENABLE\r
+#define __GPIOB_CLK_SLEEP_DISABLE __HAL_RCC_GPIOB_CLK_SLEEP_DISABLE\r
+#define __GPIOB_CLK_SLEEP_ENABLE __HAL_RCC_GPIOB_CLK_SLEEP_ENABLE\r
+#define __GPIOB_FORCE_RESET __HAL_RCC_GPIOB_FORCE_RESET\r
+#define __GPIOB_RELEASE_RESET __HAL_RCC_GPIOB_RELEASE_RESET\r
+#define __GPIOC_CLK_DISABLE __HAL_RCC_GPIOC_CLK_DISABLE\r
+#define __GPIOC_CLK_ENABLE __HAL_RCC_GPIOC_CLK_ENABLE\r
+#define __GPIOC_CLK_SLEEP_DISABLE __HAL_RCC_GPIOC_CLK_SLEEP_DISABLE\r
+#define __GPIOC_CLK_SLEEP_ENABLE __HAL_RCC_GPIOC_CLK_SLEEP_ENABLE\r
+#define __GPIOC_FORCE_RESET __HAL_RCC_GPIOC_FORCE_RESET\r
+#define __GPIOC_RELEASE_RESET __HAL_RCC_GPIOC_RELEASE_RESET\r
+#define __GPIOD_CLK_DISABLE __HAL_RCC_GPIOD_CLK_DISABLE\r
+#define __GPIOD_CLK_ENABLE __HAL_RCC_GPIOD_CLK_ENABLE\r
+#define __GPIOD_CLK_SLEEP_DISABLE __HAL_RCC_GPIOD_CLK_SLEEP_DISABLE\r
+#define __GPIOD_CLK_SLEEP_ENABLE __HAL_RCC_GPIOD_CLK_SLEEP_ENABLE\r
+#define __GPIOD_FORCE_RESET __HAL_RCC_GPIOD_FORCE_RESET\r
+#define __GPIOD_RELEASE_RESET __HAL_RCC_GPIOD_RELEASE_RESET\r
+#define __GPIOE_CLK_DISABLE __HAL_RCC_GPIOE_CLK_DISABLE\r
+#define __GPIOE_CLK_ENABLE __HAL_RCC_GPIOE_CLK_ENABLE\r
+#define __GPIOE_CLK_SLEEP_DISABLE __HAL_RCC_GPIOE_CLK_SLEEP_DISABLE\r
+#define __GPIOE_CLK_SLEEP_ENABLE __HAL_RCC_GPIOE_CLK_SLEEP_ENABLE\r
+#define __GPIOE_FORCE_RESET __HAL_RCC_GPIOE_FORCE_RESET\r
+#define __GPIOE_RELEASE_RESET __HAL_RCC_GPIOE_RELEASE_RESET\r
+#define __GPIOF_CLK_DISABLE __HAL_RCC_GPIOF_CLK_DISABLE\r
+#define __GPIOF_CLK_ENABLE __HAL_RCC_GPIOF_CLK_ENABLE\r
+#define __GPIOF_CLK_SLEEP_DISABLE __HAL_RCC_GPIOF_CLK_SLEEP_DISABLE\r
+#define __GPIOF_CLK_SLEEP_ENABLE __HAL_RCC_GPIOF_CLK_SLEEP_ENABLE\r
+#define __GPIOF_FORCE_RESET __HAL_RCC_GPIOF_FORCE_RESET\r
+#define __GPIOF_RELEASE_RESET __HAL_RCC_GPIOF_RELEASE_RESET\r
+#define __GPIOG_CLK_DISABLE __HAL_RCC_GPIOG_CLK_DISABLE\r
+#define __GPIOG_CLK_ENABLE __HAL_RCC_GPIOG_CLK_ENABLE\r
+#define __GPIOG_CLK_SLEEP_DISABLE __HAL_RCC_GPIOG_CLK_SLEEP_DISABLE\r
+#define __GPIOG_CLK_SLEEP_ENABLE __HAL_RCC_GPIOG_CLK_SLEEP_ENABLE\r
+#define __GPIOG_FORCE_RESET __HAL_RCC_GPIOG_FORCE_RESET\r
+#define __GPIOG_RELEASE_RESET __HAL_RCC_GPIOG_RELEASE_RESET\r
+#define __GPIOH_CLK_DISABLE __HAL_RCC_GPIOH_CLK_DISABLE\r
+#define __GPIOH_CLK_ENABLE __HAL_RCC_GPIOH_CLK_ENABLE\r
+#define __GPIOH_CLK_SLEEP_DISABLE __HAL_RCC_GPIOH_CLK_SLEEP_DISABLE\r
+#define __GPIOH_CLK_SLEEP_ENABLE __HAL_RCC_GPIOH_CLK_SLEEP_ENABLE\r
+#define __GPIOH_FORCE_RESET __HAL_RCC_GPIOH_FORCE_RESET\r
+#define __GPIOH_RELEASE_RESET __HAL_RCC_GPIOH_RELEASE_RESET\r
+#define __I2C1_CLK_DISABLE __HAL_RCC_I2C1_CLK_DISABLE\r
+#define __I2C1_CLK_ENABLE __HAL_RCC_I2C1_CLK_ENABLE\r
+#define __I2C1_CLK_SLEEP_DISABLE __HAL_RCC_I2C1_CLK_SLEEP_DISABLE\r
+#define __I2C1_CLK_SLEEP_ENABLE __HAL_RCC_I2C1_CLK_SLEEP_ENABLE\r
+#define __I2C1_FORCE_RESET __HAL_RCC_I2C1_FORCE_RESET\r
+#define __I2C1_RELEASE_RESET __HAL_RCC_I2C1_RELEASE_RESET\r
+#define __I2C2_CLK_DISABLE __HAL_RCC_I2C2_CLK_DISABLE\r
+#define __I2C2_CLK_ENABLE __HAL_RCC_I2C2_CLK_ENABLE\r
+#define __I2C2_CLK_SLEEP_DISABLE __HAL_RCC_I2C2_CLK_SLEEP_DISABLE\r
+#define __I2C2_CLK_SLEEP_ENABLE __HAL_RCC_I2C2_CLK_SLEEP_ENABLE\r
+#define __I2C2_FORCE_RESET __HAL_RCC_I2C2_FORCE_RESET\r
+#define __I2C2_RELEASE_RESET __HAL_RCC_I2C2_RELEASE_RESET\r
+#define __I2C3_CLK_DISABLE __HAL_RCC_I2C3_CLK_DISABLE\r
+#define __I2C3_CLK_ENABLE __HAL_RCC_I2C3_CLK_ENABLE\r
+#define __I2C3_CLK_SLEEP_DISABLE __HAL_RCC_I2C3_CLK_SLEEP_DISABLE\r
+#define __I2C3_CLK_SLEEP_ENABLE __HAL_RCC_I2C3_CLK_SLEEP_ENABLE\r
+#define __I2C3_FORCE_RESET __HAL_RCC_I2C3_FORCE_RESET\r
+#define __I2C3_RELEASE_RESET __HAL_RCC_I2C3_RELEASE_RESET\r
+#define __LCD_CLK_DISABLE __HAL_RCC_LCD_CLK_DISABLE\r
+#define __LCD_CLK_ENABLE __HAL_RCC_LCD_CLK_ENABLE\r
+#define __LCD_CLK_SLEEP_DISABLE __HAL_RCC_LCD_CLK_SLEEP_DISABLE\r
+#define __LCD_CLK_SLEEP_ENABLE __HAL_RCC_LCD_CLK_SLEEP_ENABLE\r
+#define __LCD_FORCE_RESET __HAL_RCC_LCD_FORCE_RESET\r
+#define __LCD_RELEASE_RESET __HAL_RCC_LCD_RELEASE_RESET\r
+#define __LPTIM1_CLK_DISABLE __HAL_RCC_LPTIM1_CLK_DISABLE\r
+#define __LPTIM1_CLK_ENABLE __HAL_RCC_LPTIM1_CLK_ENABLE\r
+#define __LPTIM1_CLK_SLEEP_DISABLE __HAL_RCC_LPTIM1_CLK_SLEEP_DISABLE\r
+#define __LPTIM1_CLK_SLEEP_ENABLE __HAL_RCC_LPTIM1_CLK_SLEEP_ENABLE\r
+#define __LPTIM1_FORCE_RESET __HAL_RCC_LPTIM1_FORCE_RESET\r
+#define __LPTIM1_RELEASE_RESET __HAL_RCC_LPTIM1_RELEASE_RESET\r
+#define __LPTIM2_CLK_DISABLE __HAL_RCC_LPTIM2_CLK_DISABLE\r
+#define __LPTIM2_CLK_ENABLE __HAL_RCC_LPTIM2_CLK_ENABLE\r
+#define __LPTIM2_CLK_SLEEP_DISABLE __HAL_RCC_LPTIM2_CLK_SLEEP_DISABLE\r
+#define __LPTIM2_CLK_SLEEP_ENABLE __HAL_RCC_LPTIM2_CLK_SLEEP_ENABLE\r
+#define __LPTIM2_FORCE_RESET __HAL_RCC_LPTIM2_FORCE_RESET\r
+#define __LPTIM2_RELEASE_RESET __HAL_RCC_LPTIM2_RELEASE_RESET\r
+#define __LPUART1_CLK_DISABLE __HAL_RCC_LPUART1_CLK_DISABLE\r
+#define __LPUART1_CLK_ENABLE __HAL_RCC_LPUART1_CLK_ENABLE\r
+#define __LPUART1_CLK_SLEEP_DISABLE __HAL_RCC_LPUART1_CLK_SLEEP_DISABLE\r
+#define __LPUART1_CLK_SLEEP_ENABLE __HAL_RCC_LPUART1_CLK_SLEEP_ENABLE\r
+#define __LPUART1_FORCE_RESET __HAL_RCC_LPUART1_FORCE_RESET\r
+#define __LPUART1_RELEASE_RESET __HAL_RCC_LPUART1_RELEASE_RESET\r
+#define __OPAMP_CLK_DISABLE __HAL_RCC_OPAMP_CLK_DISABLE\r
+#define __OPAMP_CLK_ENABLE __HAL_RCC_OPAMP_CLK_ENABLE\r
+#define __OPAMP_CLK_SLEEP_DISABLE __HAL_RCC_OPAMP_CLK_SLEEP_DISABLE\r
+#define __OPAMP_CLK_SLEEP_ENABLE __HAL_RCC_OPAMP_CLK_SLEEP_ENABLE\r
+#define __OPAMP_FORCE_RESET __HAL_RCC_OPAMP_FORCE_RESET\r
+#define __OPAMP_RELEASE_RESET __HAL_RCC_OPAMP_RELEASE_RESET\r
+#define __OTGFS_CLK_DISABLE __HAL_RCC_OTGFS_CLK_DISABLE\r
+#define __OTGFS_CLK_ENABLE __HAL_RCC_OTGFS_CLK_ENABLE\r
+#define __OTGFS_CLK_SLEEP_DISABLE __HAL_RCC_OTGFS_CLK_SLEEP_DISABLE\r
+#define __OTGFS_CLK_SLEEP_ENABLE __HAL_RCC_OTGFS_CLK_SLEEP_ENABLE\r
+#define __OTGFS_FORCE_RESET __HAL_RCC_OTGFS_FORCE_RESET\r
+#define __OTGFS_RELEASE_RESET __HAL_RCC_OTGFS_RELEASE_RESET\r
+#define __PWR_CLK_DISABLE __HAL_RCC_PWR_CLK_DISABLE\r
+#define __PWR_CLK_ENABLE __HAL_RCC_PWR_CLK_ENABLE\r
+#define __PWR_CLK_SLEEP_DISABLE __HAL_RCC_PWR_CLK_SLEEP_DISABLE\r
+#define __PWR_CLK_SLEEP_ENABLE __HAL_RCC_PWR_CLK_SLEEP_ENABLE\r
+#define __PWR_FORCE_RESET __HAL_RCC_PWR_FORCE_RESET\r
+#define __PWR_RELEASE_RESET __HAL_RCC_PWR_RELEASE_RESET\r
+#define __QSPI_CLK_DISABLE __HAL_RCC_QSPI_CLK_DISABLE\r
+#define __QSPI_CLK_ENABLE __HAL_RCC_QSPI_CLK_ENABLE\r
+#define __QSPI_CLK_SLEEP_DISABLE __HAL_RCC_QSPI_CLK_SLEEP_DISABLE\r
+#define __QSPI_CLK_SLEEP_ENABLE __HAL_RCC_QSPI_CLK_SLEEP_ENABLE\r
+#define __QSPI_FORCE_RESET __HAL_RCC_QSPI_FORCE_RESET\r
+#define __QSPI_RELEASE_RESET __HAL_RCC_QSPI_RELEASE_RESET\r
+\r
+#if defined(STM32WB)\r
+#define __HAL_RCC_QSPI_CLK_DISABLE __HAL_RCC_QUADSPI_CLK_DISABLE\r
+#define __HAL_RCC_QSPI_CLK_ENABLE __HAL_RCC_QUADSPI_CLK_ENABLE\r
+#define __HAL_RCC_QSPI_CLK_SLEEP_DISABLE __HAL_RCC_QUADSPI_CLK_SLEEP_DISABLE\r
+#define __HAL_RCC_QSPI_CLK_SLEEP_ENABLE __HAL_RCC_QUADSPI_CLK_SLEEP_ENABLE\r
+#define __HAL_RCC_QSPI_FORCE_RESET __HAL_RCC_QUADSPI_FORCE_RESET\r
+#define __HAL_RCC_QSPI_RELEASE_RESET __HAL_RCC_QUADSPI_RELEASE_RESET\r
+#define __HAL_RCC_QSPI_IS_CLK_ENABLED __HAL_RCC_QUADSPI_IS_CLK_ENABLED\r
+#define __HAL_RCC_QSPI_IS_CLK_DISABLED __HAL_RCC_QUADSPI_IS_CLK_DISABLED\r
+#define __HAL_RCC_QSPI_IS_CLK_SLEEP_ENABLED __HAL_RCC_QUADSPI_IS_CLK_SLEEP_ENABLED\r
+#define __HAL_RCC_QSPI_IS_CLK_SLEEP_DISABLED __HAL_RCC_QUADSPI_IS_CLK_SLEEP_DISABLED\r
+#define QSPI_IRQHandler QUADSPI_IRQHandler\r
+#endif /* __HAL_RCC_QUADSPI_CLK_ENABLE */\r
+\r
+#define __RNG_CLK_DISABLE __HAL_RCC_RNG_CLK_DISABLE\r
+#define __RNG_CLK_ENABLE __HAL_RCC_RNG_CLK_ENABLE\r
+#define __RNG_CLK_SLEEP_DISABLE __HAL_RCC_RNG_CLK_SLEEP_DISABLE\r
+#define __RNG_CLK_SLEEP_ENABLE __HAL_RCC_RNG_CLK_SLEEP_ENABLE\r
+#define __RNG_FORCE_RESET __HAL_RCC_RNG_FORCE_RESET\r
+#define __RNG_RELEASE_RESET __HAL_RCC_RNG_RELEASE_RESET\r
+#define __SAI1_CLK_DISABLE __HAL_RCC_SAI1_CLK_DISABLE\r
+#define __SAI1_CLK_ENABLE __HAL_RCC_SAI1_CLK_ENABLE\r
+#define __SAI1_CLK_SLEEP_DISABLE __HAL_RCC_SAI1_CLK_SLEEP_DISABLE\r
+#define __SAI1_CLK_SLEEP_ENABLE __HAL_RCC_SAI1_CLK_SLEEP_ENABLE\r
+#define __SAI1_FORCE_RESET __HAL_RCC_SAI1_FORCE_RESET\r
+#define __SAI1_RELEASE_RESET __HAL_RCC_SAI1_RELEASE_RESET\r
+#define __SAI2_CLK_DISABLE __HAL_RCC_SAI2_CLK_DISABLE\r
+#define __SAI2_CLK_ENABLE __HAL_RCC_SAI2_CLK_ENABLE\r
+#define __SAI2_CLK_SLEEP_DISABLE __HAL_RCC_SAI2_CLK_SLEEP_DISABLE\r
+#define __SAI2_CLK_SLEEP_ENABLE __HAL_RCC_SAI2_CLK_SLEEP_ENABLE\r
+#define __SAI2_FORCE_RESET __HAL_RCC_SAI2_FORCE_RESET\r
+#define __SAI2_RELEASE_RESET __HAL_RCC_SAI2_RELEASE_RESET\r
+#define __SDIO_CLK_DISABLE __HAL_RCC_SDIO_CLK_DISABLE\r
+#define __SDIO_CLK_ENABLE __HAL_RCC_SDIO_CLK_ENABLE\r
+#define __SDMMC_CLK_DISABLE __HAL_RCC_SDMMC_CLK_DISABLE\r
+#define __SDMMC_CLK_ENABLE __HAL_RCC_SDMMC_CLK_ENABLE\r
+#define __SDMMC_CLK_SLEEP_DISABLE __HAL_RCC_SDMMC_CLK_SLEEP_DISABLE\r
+#define __SDMMC_CLK_SLEEP_ENABLE __HAL_RCC_SDMMC_CLK_SLEEP_ENABLE\r
+#define __SDMMC_FORCE_RESET __HAL_RCC_SDMMC_FORCE_RESET\r
+#define __SDMMC_RELEASE_RESET __HAL_RCC_SDMMC_RELEASE_RESET\r
+#define __SPI1_CLK_DISABLE __HAL_RCC_SPI1_CLK_DISABLE\r
+#define __SPI1_CLK_ENABLE __HAL_RCC_SPI1_CLK_ENABLE\r
+#define __SPI1_CLK_SLEEP_DISABLE __HAL_RCC_SPI1_CLK_SLEEP_DISABLE\r
+#define __SPI1_CLK_SLEEP_ENABLE __HAL_RCC_SPI1_CLK_SLEEP_ENABLE\r
+#define __SPI1_FORCE_RESET __HAL_RCC_SPI1_FORCE_RESET\r
+#define __SPI1_RELEASE_RESET __HAL_RCC_SPI1_RELEASE_RESET\r
+#define __SPI2_CLK_DISABLE __HAL_RCC_SPI2_CLK_DISABLE\r
+#define __SPI2_CLK_ENABLE __HAL_RCC_SPI2_CLK_ENABLE\r
+#define __SPI2_CLK_SLEEP_DISABLE __HAL_RCC_SPI2_CLK_SLEEP_DISABLE\r
+#define __SPI2_CLK_SLEEP_ENABLE __HAL_RCC_SPI2_CLK_SLEEP_ENABLE\r
+#define __SPI2_FORCE_RESET __HAL_RCC_SPI2_FORCE_RESET\r
+#define __SPI2_RELEASE_RESET __HAL_RCC_SPI2_RELEASE_RESET\r
+#define __SPI3_CLK_DISABLE __HAL_RCC_SPI3_CLK_DISABLE\r
+#define __SPI3_CLK_ENABLE __HAL_RCC_SPI3_CLK_ENABLE\r
+#define __SPI3_CLK_SLEEP_DISABLE __HAL_RCC_SPI3_CLK_SLEEP_DISABLE\r
+#define __SPI3_CLK_SLEEP_ENABLE __HAL_RCC_SPI3_CLK_SLEEP_ENABLE\r
+#define __SPI3_FORCE_RESET __HAL_RCC_SPI3_FORCE_RESET\r
+#define __SPI3_RELEASE_RESET __HAL_RCC_SPI3_RELEASE_RESET\r
+#define __SRAM_CLK_DISABLE __HAL_RCC_SRAM_CLK_DISABLE\r
+#define __SRAM_CLK_ENABLE __HAL_RCC_SRAM_CLK_ENABLE\r
+#define __SRAM1_CLK_SLEEP_DISABLE __HAL_RCC_SRAM1_CLK_SLEEP_DISABLE\r
+#define __SRAM1_CLK_SLEEP_ENABLE __HAL_RCC_SRAM1_CLK_SLEEP_ENABLE\r
+#define __SRAM2_CLK_SLEEP_DISABLE __HAL_RCC_SRAM2_CLK_SLEEP_DISABLE\r
+#define __SRAM2_CLK_SLEEP_ENABLE __HAL_RCC_SRAM2_CLK_SLEEP_ENABLE\r
+#define __SWPMI1_CLK_DISABLE __HAL_RCC_SWPMI1_CLK_DISABLE\r
+#define __SWPMI1_CLK_ENABLE __HAL_RCC_SWPMI1_CLK_ENABLE\r
+#define __SWPMI1_CLK_SLEEP_DISABLE __HAL_RCC_SWPMI1_CLK_SLEEP_DISABLE\r
+#define __SWPMI1_CLK_SLEEP_ENABLE __HAL_RCC_SWPMI1_CLK_SLEEP_ENABLE\r
+#define __SWPMI1_FORCE_RESET __HAL_RCC_SWPMI1_FORCE_RESET\r
+#define __SWPMI1_RELEASE_RESET __HAL_RCC_SWPMI1_RELEASE_RESET\r
+#define __SYSCFG_CLK_DISABLE __HAL_RCC_SYSCFG_CLK_DISABLE\r
+#define __SYSCFG_CLK_ENABLE __HAL_RCC_SYSCFG_CLK_ENABLE\r
+#define __SYSCFG_CLK_SLEEP_DISABLE __HAL_RCC_SYSCFG_CLK_SLEEP_DISABLE\r
+#define __SYSCFG_CLK_SLEEP_ENABLE __HAL_RCC_SYSCFG_CLK_SLEEP_ENABLE\r
+#define __SYSCFG_FORCE_RESET __HAL_RCC_SYSCFG_FORCE_RESET\r
+#define __SYSCFG_RELEASE_RESET __HAL_RCC_SYSCFG_RELEASE_RESET\r
+#define __TIM1_CLK_DISABLE __HAL_RCC_TIM1_CLK_DISABLE\r
+#define __TIM1_CLK_ENABLE __HAL_RCC_TIM1_CLK_ENABLE\r
+#define __TIM1_CLK_SLEEP_DISABLE __HAL_RCC_TIM1_CLK_SLEEP_DISABLE\r
+#define __TIM1_CLK_SLEEP_ENABLE __HAL_RCC_TIM1_CLK_SLEEP_ENABLE\r
+#define __TIM1_FORCE_RESET __HAL_RCC_TIM1_FORCE_RESET\r
+#define __TIM1_RELEASE_RESET __HAL_RCC_TIM1_RELEASE_RESET\r
+#define __TIM10_CLK_DISABLE __HAL_RCC_TIM10_CLK_DISABLE\r
+#define __TIM10_CLK_ENABLE __HAL_RCC_TIM10_CLK_ENABLE\r
+#define __TIM10_FORCE_RESET __HAL_RCC_TIM10_FORCE_RESET\r
+#define __TIM10_RELEASE_RESET __HAL_RCC_TIM10_RELEASE_RESET\r
+#define __TIM11_CLK_DISABLE __HAL_RCC_TIM11_CLK_DISABLE\r
+#define __TIM11_CLK_ENABLE __HAL_RCC_TIM11_CLK_ENABLE\r
+#define __TIM11_FORCE_RESET __HAL_RCC_TIM11_FORCE_RESET\r
+#define __TIM11_RELEASE_RESET __HAL_RCC_TIM11_RELEASE_RESET\r
+#define __TIM12_CLK_DISABLE __HAL_RCC_TIM12_CLK_DISABLE\r
+#define __TIM12_CLK_ENABLE __HAL_RCC_TIM12_CLK_ENABLE\r
+#define __TIM12_FORCE_RESET __HAL_RCC_TIM12_FORCE_RESET\r
+#define __TIM12_RELEASE_RESET __HAL_RCC_TIM12_RELEASE_RESET\r
+#define __TIM13_CLK_DISABLE __HAL_RCC_TIM13_CLK_DISABLE\r
+#define __TIM13_CLK_ENABLE __HAL_RCC_TIM13_CLK_ENABLE\r
+#define __TIM13_FORCE_RESET __HAL_RCC_TIM13_FORCE_RESET\r
+#define __TIM13_RELEASE_RESET __HAL_RCC_TIM13_RELEASE_RESET\r
+#define __TIM14_CLK_DISABLE __HAL_RCC_TIM14_CLK_DISABLE\r
+#define __TIM14_CLK_ENABLE __HAL_RCC_TIM14_CLK_ENABLE\r
+#define __TIM14_FORCE_RESET __HAL_RCC_TIM14_FORCE_RESET\r
+#define __TIM14_RELEASE_RESET __HAL_RCC_TIM14_RELEASE_RESET\r
+#define __TIM15_CLK_DISABLE __HAL_RCC_TIM15_CLK_DISABLE\r
+#define __TIM15_CLK_ENABLE __HAL_RCC_TIM15_CLK_ENABLE\r
+#define __TIM15_CLK_SLEEP_DISABLE __HAL_RCC_TIM15_CLK_SLEEP_DISABLE\r
+#define __TIM15_CLK_SLEEP_ENABLE __HAL_RCC_TIM15_CLK_SLEEP_ENABLE\r
+#define __TIM15_FORCE_RESET __HAL_RCC_TIM15_FORCE_RESET\r
+#define __TIM15_RELEASE_RESET __HAL_RCC_TIM15_RELEASE_RESET\r
+#define __TIM16_CLK_DISABLE __HAL_RCC_TIM16_CLK_DISABLE\r
+#define __TIM16_CLK_ENABLE __HAL_RCC_TIM16_CLK_ENABLE\r
+#define __TIM16_CLK_SLEEP_DISABLE __HAL_RCC_TIM16_CLK_SLEEP_DISABLE\r
+#define __TIM16_CLK_SLEEP_ENABLE __HAL_RCC_TIM16_CLK_SLEEP_ENABLE\r
+#define __TIM16_FORCE_RESET __HAL_RCC_TIM16_FORCE_RESET\r
+#define __TIM16_RELEASE_RESET __HAL_RCC_TIM16_RELEASE_RESET\r
+#define __TIM17_CLK_DISABLE __HAL_RCC_TIM17_CLK_DISABLE\r
+#define __TIM17_CLK_ENABLE __HAL_RCC_TIM17_CLK_ENABLE\r
+#define __TIM17_CLK_SLEEP_DISABLE __HAL_RCC_TIM17_CLK_SLEEP_DISABLE\r
+#define __TIM17_CLK_SLEEP_ENABLE __HAL_RCC_TIM17_CLK_SLEEP_ENABLE\r
+#define __TIM17_FORCE_RESET __HAL_RCC_TIM17_FORCE_RESET\r
+#define __TIM17_RELEASE_RESET __HAL_RCC_TIM17_RELEASE_RESET\r
+#define __TIM2_CLK_DISABLE __HAL_RCC_TIM2_CLK_DISABLE\r
+#define __TIM2_CLK_ENABLE __HAL_RCC_TIM2_CLK_ENABLE\r
+#define __TIM2_CLK_SLEEP_DISABLE __HAL_RCC_TIM2_CLK_SLEEP_DISABLE\r
+#define __TIM2_CLK_SLEEP_ENABLE __HAL_RCC_TIM2_CLK_SLEEP_ENABLE\r
+#define __TIM2_FORCE_RESET __HAL_RCC_TIM2_FORCE_RESET\r
+#define __TIM2_RELEASE_RESET __HAL_RCC_TIM2_RELEASE_RESET\r
+#define __TIM3_CLK_DISABLE __HAL_RCC_TIM3_CLK_DISABLE\r
+#define __TIM3_CLK_ENABLE __HAL_RCC_TIM3_CLK_ENABLE\r
+#define __TIM3_CLK_SLEEP_DISABLE __HAL_RCC_TIM3_CLK_SLEEP_DISABLE\r
+#define __TIM3_CLK_SLEEP_ENABLE __HAL_RCC_TIM3_CLK_SLEEP_ENABLE\r
+#define __TIM3_FORCE_RESET __HAL_RCC_TIM3_FORCE_RESET\r
+#define __TIM3_RELEASE_RESET __HAL_RCC_TIM3_RELEASE_RESET\r
+#define __TIM4_CLK_DISABLE __HAL_RCC_TIM4_CLK_DISABLE\r
+#define __TIM4_CLK_ENABLE __HAL_RCC_TIM4_CLK_ENABLE\r
+#define __TIM4_CLK_SLEEP_DISABLE __HAL_RCC_TIM4_CLK_SLEEP_DISABLE\r
+#define __TIM4_CLK_SLEEP_ENABLE __HAL_RCC_TIM4_CLK_SLEEP_ENABLE\r
+#define __TIM4_FORCE_RESET __HAL_RCC_TIM4_FORCE_RESET\r
+#define __TIM4_RELEASE_RESET __HAL_RCC_TIM4_RELEASE_RESET\r
+#define __TIM5_CLK_DISABLE __HAL_RCC_TIM5_CLK_DISABLE\r
+#define __TIM5_CLK_ENABLE __HAL_RCC_TIM5_CLK_ENABLE\r
+#define __TIM5_CLK_SLEEP_DISABLE __HAL_RCC_TIM5_CLK_SLEEP_DISABLE\r
+#define __TIM5_CLK_SLEEP_ENABLE __HAL_RCC_TIM5_CLK_SLEEP_ENABLE\r
+#define __TIM5_FORCE_RESET __HAL_RCC_TIM5_FORCE_RESET\r
+#define __TIM5_RELEASE_RESET __HAL_RCC_TIM5_RELEASE_RESET\r
+#define __TIM6_CLK_DISABLE __HAL_RCC_TIM6_CLK_DISABLE\r
+#define __TIM6_CLK_ENABLE __HAL_RCC_TIM6_CLK_ENABLE\r
+#define __TIM6_CLK_SLEEP_DISABLE __HAL_RCC_TIM6_CLK_SLEEP_DISABLE\r
+#define __TIM6_CLK_SLEEP_ENABLE __HAL_RCC_TIM6_CLK_SLEEP_ENABLE\r
+#define __TIM6_FORCE_RESET __HAL_RCC_TIM6_FORCE_RESET\r
+#define __TIM6_RELEASE_RESET __HAL_RCC_TIM6_RELEASE_RESET\r
+#define __TIM7_CLK_DISABLE __HAL_RCC_TIM7_CLK_DISABLE\r
+#define __TIM7_CLK_ENABLE __HAL_RCC_TIM7_CLK_ENABLE\r
+#define __TIM7_CLK_SLEEP_DISABLE __HAL_RCC_TIM7_CLK_SLEEP_DISABLE\r
+#define __TIM7_CLK_SLEEP_ENABLE __HAL_RCC_TIM7_CLK_SLEEP_ENABLE\r
+#define __TIM7_FORCE_RESET __HAL_RCC_TIM7_FORCE_RESET\r
+#define __TIM7_RELEASE_RESET __HAL_RCC_TIM7_RELEASE_RESET\r
+#define __TIM8_CLK_DISABLE __HAL_RCC_TIM8_CLK_DISABLE\r
+#define __TIM8_CLK_ENABLE __HAL_RCC_TIM8_CLK_ENABLE\r
+#define __TIM8_CLK_SLEEP_DISABLE __HAL_RCC_TIM8_CLK_SLEEP_DISABLE\r
+#define __TIM8_CLK_SLEEP_ENABLE __HAL_RCC_TIM8_CLK_SLEEP_ENABLE\r
+#define __TIM8_FORCE_RESET __HAL_RCC_TIM8_FORCE_RESET\r
+#define __TIM8_RELEASE_RESET __HAL_RCC_TIM8_RELEASE_RESET\r
+#define __TIM9_CLK_DISABLE __HAL_RCC_TIM9_CLK_DISABLE\r
+#define __TIM9_CLK_ENABLE __HAL_RCC_TIM9_CLK_ENABLE\r
+#define __TIM9_FORCE_RESET __HAL_RCC_TIM9_FORCE_RESET\r
+#define __TIM9_RELEASE_RESET __HAL_RCC_TIM9_RELEASE_RESET\r
+#define __TSC_CLK_DISABLE __HAL_RCC_TSC_CLK_DISABLE\r
+#define __TSC_CLK_ENABLE __HAL_RCC_TSC_CLK_ENABLE\r
+#define __TSC_CLK_SLEEP_DISABLE __HAL_RCC_TSC_CLK_SLEEP_DISABLE\r
+#define __TSC_CLK_SLEEP_ENABLE __HAL_RCC_TSC_CLK_SLEEP_ENABLE\r
+#define __TSC_FORCE_RESET __HAL_RCC_TSC_FORCE_RESET\r
+#define __TSC_RELEASE_RESET __HAL_RCC_TSC_RELEASE_RESET\r
+#define __UART4_CLK_DISABLE __HAL_RCC_UART4_CLK_DISABLE\r
+#define __UART4_CLK_ENABLE __HAL_RCC_UART4_CLK_ENABLE\r
+#define __UART4_CLK_SLEEP_DISABLE __HAL_RCC_UART4_CLK_SLEEP_DISABLE\r
+#define __UART4_CLK_SLEEP_ENABLE __HAL_RCC_UART4_CLK_SLEEP_ENABLE\r
+#define __UART4_FORCE_RESET __HAL_RCC_UART4_FORCE_RESET\r
+#define __UART4_RELEASE_RESET __HAL_RCC_UART4_RELEASE_RESET\r
+#define __UART5_CLK_DISABLE __HAL_RCC_UART5_CLK_DISABLE\r
+#define __UART5_CLK_ENABLE __HAL_RCC_UART5_CLK_ENABLE\r
+#define __UART5_CLK_SLEEP_DISABLE __HAL_RCC_UART5_CLK_SLEEP_DISABLE\r
+#define __UART5_CLK_SLEEP_ENABLE __HAL_RCC_UART5_CLK_SLEEP_ENABLE\r
+#define __UART5_FORCE_RESET __HAL_RCC_UART5_FORCE_RESET\r
+#define __UART5_RELEASE_RESET __HAL_RCC_UART5_RELEASE_RESET\r
+#define __USART1_CLK_DISABLE __HAL_RCC_USART1_CLK_DISABLE\r
+#define __USART1_CLK_ENABLE __HAL_RCC_USART1_CLK_ENABLE\r
+#define __USART1_CLK_SLEEP_DISABLE __HAL_RCC_USART1_CLK_SLEEP_DISABLE\r
+#define __USART1_CLK_SLEEP_ENABLE __HAL_RCC_USART1_CLK_SLEEP_ENABLE\r
+#define __USART1_FORCE_RESET __HAL_RCC_USART1_FORCE_RESET\r
+#define __USART1_RELEASE_RESET __HAL_RCC_USART1_RELEASE_RESET\r
+#define __USART2_CLK_DISABLE __HAL_RCC_USART2_CLK_DISABLE\r
+#define __USART2_CLK_ENABLE __HAL_RCC_USART2_CLK_ENABLE\r
+#define __USART2_CLK_SLEEP_DISABLE __HAL_RCC_USART2_CLK_SLEEP_DISABLE\r
+#define __USART2_CLK_SLEEP_ENABLE __HAL_RCC_USART2_CLK_SLEEP_ENABLE\r
+#define __USART2_FORCE_RESET __HAL_RCC_USART2_FORCE_RESET\r
+#define __USART2_RELEASE_RESET __HAL_RCC_USART2_RELEASE_RESET\r
+#define __USART3_CLK_DISABLE __HAL_RCC_USART3_CLK_DISABLE\r
+#define __USART3_CLK_ENABLE __HAL_RCC_USART3_CLK_ENABLE\r
+#define __USART3_CLK_SLEEP_DISABLE __HAL_RCC_USART3_CLK_SLEEP_DISABLE\r
+#define __USART3_CLK_SLEEP_ENABLE __HAL_RCC_USART3_CLK_SLEEP_ENABLE\r
+#define __USART3_FORCE_RESET __HAL_RCC_USART3_FORCE_RESET\r
+#define __USART3_RELEASE_RESET __HAL_RCC_USART3_RELEASE_RESET\r
+#define __USART4_CLK_DISABLE __HAL_RCC_UART4_CLK_DISABLE\r
+#define __USART4_CLK_ENABLE __HAL_RCC_UART4_CLK_ENABLE\r
+#define __USART4_CLK_SLEEP_ENABLE __HAL_RCC_UART4_CLK_SLEEP_ENABLE\r
+#define __USART4_CLK_SLEEP_DISABLE __HAL_RCC_UART4_CLK_SLEEP_DISABLE\r
+#define __USART4_FORCE_RESET __HAL_RCC_UART4_FORCE_RESET\r
+#define __USART4_RELEASE_RESET __HAL_RCC_UART4_RELEASE_RESET\r
+#define __USART5_CLK_DISABLE __HAL_RCC_UART5_CLK_DISABLE\r
+#define __USART5_CLK_ENABLE __HAL_RCC_UART5_CLK_ENABLE\r
+#define __USART5_CLK_SLEEP_ENABLE __HAL_RCC_UART5_CLK_SLEEP_ENABLE\r
+#define __USART5_CLK_SLEEP_DISABLE __HAL_RCC_UART5_CLK_SLEEP_DISABLE\r
+#define __USART5_FORCE_RESET __HAL_RCC_UART5_FORCE_RESET\r
+#define __USART5_RELEASE_RESET __HAL_RCC_UART5_RELEASE_RESET\r
+#define __USART7_CLK_DISABLE __HAL_RCC_UART7_CLK_DISABLE\r
+#define __USART7_CLK_ENABLE __HAL_RCC_UART7_CLK_ENABLE\r
+#define __USART7_FORCE_RESET __HAL_RCC_UART7_FORCE_RESET\r
+#define __USART7_RELEASE_RESET __HAL_RCC_UART7_RELEASE_RESET\r
+#define __USART8_CLK_DISABLE __HAL_RCC_UART8_CLK_DISABLE\r
+#define __USART8_CLK_ENABLE __HAL_RCC_UART8_CLK_ENABLE\r
+#define __USART8_FORCE_RESET __HAL_RCC_UART8_FORCE_RESET\r
+#define __USART8_RELEASE_RESET __HAL_RCC_UART8_RELEASE_RESET\r
+#define __USB_CLK_DISABLE __HAL_RCC_USB_CLK_DISABLE\r
+#define __USB_CLK_ENABLE __HAL_RCC_USB_CLK_ENABLE\r
+#define __USB_FORCE_RESET __HAL_RCC_USB_FORCE_RESET\r
+#define __USB_CLK_SLEEP_ENABLE __HAL_RCC_USB_CLK_SLEEP_ENABLE\r
+#define __USB_CLK_SLEEP_DISABLE __HAL_RCC_USB_CLK_SLEEP_DISABLE\r
+#define __USB_OTG_FS_CLK_DISABLE __HAL_RCC_USB_OTG_FS_CLK_DISABLE\r
+#define __USB_OTG_FS_CLK_ENABLE __HAL_RCC_USB_OTG_FS_CLK_ENABLE\r
+#define __USB_RELEASE_RESET __HAL_RCC_USB_RELEASE_RESET\r
+\r
+#if defined(STM32H7)\r
+#define __HAL_RCC_WWDG_CLK_DISABLE __HAL_RCC_WWDG1_CLK_DISABLE\r
+#define __HAL_RCC_WWDG_CLK_ENABLE __HAL_RCC_WWDG1_CLK_ENABLE\r
+#define __HAL_RCC_WWDG_CLK_SLEEP_DISABLE __HAL_RCC_WWDG1_CLK_SLEEP_DISABLE\r
+#define __HAL_RCC_WWDG_CLK_SLEEP_ENABLE __HAL_RCC_WWDG1_CLK_SLEEP_ENABLE\r
+\r
+#define __HAL_RCC_WWDG_FORCE_RESET ((void)0U) /* Not available on the STM32H7*/\r
+#define __HAL_RCC_WWDG_RELEASE_RESET ((void)0U) /* Not available on the STM32H7*/\r
+\r
+\r
+#define __HAL_RCC_WWDG_IS_CLK_ENABLED __HAL_RCC_WWDG1_IS_CLK_ENABLED\r
+#define __HAL_RCC_WWDG_IS_CLK_DISABLED __HAL_RCC_WWDG1_IS_CLK_DISABLED\r
+#endif\r
+\r
+#define __WWDG_CLK_DISABLE __HAL_RCC_WWDG_CLK_DISABLE\r
+#define __WWDG_CLK_ENABLE __HAL_RCC_WWDG_CLK_ENABLE\r
+#define __WWDG_CLK_SLEEP_DISABLE __HAL_RCC_WWDG_CLK_SLEEP_DISABLE\r
+#define __WWDG_CLK_SLEEP_ENABLE __HAL_RCC_WWDG_CLK_SLEEP_ENABLE\r
+#define __WWDG_FORCE_RESET __HAL_RCC_WWDG_FORCE_RESET\r
+#define __WWDG_RELEASE_RESET __HAL_RCC_WWDG_RELEASE_RESET\r
+\r
+#define __TIM21_CLK_ENABLE __HAL_RCC_TIM21_CLK_ENABLE\r
+#define __TIM21_CLK_DISABLE __HAL_RCC_TIM21_CLK_DISABLE\r
+#define __TIM21_FORCE_RESET __HAL_RCC_TIM21_FORCE_RESET\r
+#define __TIM21_RELEASE_RESET __HAL_RCC_TIM21_RELEASE_RESET\r
+#define __TIM21_CLK_SLEEP_ENABLE __HAL_RCC_TIM21_CLK_SLEEP_ENABLE\r
+#define __TIM21_CLK_SLEEP_DISABLE __HAL_RCC_TIM21_CLK_SLEEP_DISABLE\r
+#define __TIM22_CLK_ENABLE __HAL_RCC_TIM22_CLK_ENABLE\r
+#define __TIM22_CLK_DISABLE __HAL_RCC_TIM22_CLK_DISABLE\r
+#define __TIM22_FORCE_RESET __HAL_RCC_TIM22_FORCE_RESET\r
+#define __TIM22_RELEASE_RESET __HAL_RCC_TIM22_RELEASE_RESET\r
+#define __TIM22_CLK_SLEEP_ENABLE __HAL_RCC_TIM22_CLK_SLEEP_ENABLE\r
+#define __TIM22_CLK_SLEEP_DISABLE __HAL_RCC_TIM22_CLK_SLEEP_DISABLE\r
+#define __CRS_CLK_DISABLE __HAL_RCC_CRS_CLK_DISABLE\r
+#define __CRS_CLK_ENABLE __HAL_RCC_CRS_CLK_ENABLE\r
+#define __CRS_CLK_SLEEP_DISABLE __HAL_RCC_CRS_CLK_SLEEP_DISABLE\r
+#define __CRS_CLK_SLEEP_ENABLE __HAL_RCC_CRS_CLK_SLEEP_ENABLE\r
+#define __CRS_FORCE_RESET __HAL_RCC_CRS_FORCE_RESET\r
+#define __CRS_RELEASE_RESET __HAL_RCC_CRS_RELEASE_RESET\r
+#define __RCC_BACKUPRESET_FORCE __HAL_RCC_BACKUPRESET_FORCE\r
+#define __RCC_BACKUPRESET_RELEASE __HAL_RCC_BACKUPRESET_RELEASE\r
+\r
+#define __USB_OTG_FS_FORCE_RESET __HAL_RCC_USB_OTG_FS_FORCE_RESET\r
+#define __USB_OTG_FS_RELEASE_RESET __HAL_RCC_USB_OTG_FS_RELEASE_RESET\r
+#define __USB_OTG_FS_CLK_SLEEP_ENABLE __HAL_RCC_USB_OTG_FS_CLK_SLEEP_ENABLE\r
+#define __USB_OTG_FS_CLK_SLEEP_DISABLE __HAL_RCC_USB_OTG_FS_CLK_SLEEP_DISABLE\r
+#define __USB_OTG_HS_CLK_DISABLE __HAL_RCC_USB_OTG_HS_CLK_DISABLE\r
+#define __USB_OTG_HS_CLK_ENABLE __HAL_RCC_USB_OTG_HS_CLK_ENABLE\r
+#define __USB_OTG_HS_ULPI_CLK_ENABLE __HAL_RCC_USB_OTG_HS_ULPI_CLK_ENABLE\r
+#define __USB_OTG_HS_ULPI_CLK_DISABLE __HAL_RCC_USB_OTG_HS_ULPI_CLK_DISABLE\r
+#define __TIM9_CLK_SLEEP_ENABLE __HAL_RCC_TIM9_CLK_SLEEP_ENABLE\r
+#define __TIM9_CLK_SLEEP_DISABLE __HAL_RCC_TIM9_CLK_SLEEP_DISABLE\r
+#define __TIM10_CLK_SLEEP_ENABLE __HAL_RCC_TIM10_CLK_SLEEP_ENABLE\r
+#define __TIM10_CLK_SLEEP_DISABLE __HAL_RCC_TIM10_CLK_SLEEP_DISABLE\r
+#define __TIM11_CLK_SLEEP_ENABLE __HAL_RCC_TIM11_CLK_SLEEP_ENABLE\r
+#define __TIM11_CLK_SLEEP_DISABLE __HAL_RCC_TIM11_CLK_SLEEP_DISABLE\r
+#define __ETHMACPTP_CLK_SLEEP_ENABLE __HAL_RCC_ETHMACPTP_CLK_SLEEP_ENABLE\r
+#define __ETHMACPTP_CLK_SLEEP_DISABLE __HAL_RCC_ETHMACPTP_CLK_SLEEP_DISABLE\r
+#define __ETHMACPTP_CLK_ENABLE __HAL_RCC_ETHMACPTP_CLK_ENABLE\r
+#define __ETHMACPTP_CLK_DISABLE __HAL_RCC_ETHMACPTP_CLK_DISABLE\r
+#define __HASH_CLK_ENABLE __HAL_RCC_HASH_CLK_ENABLE\r
+#define __HASH_FORCE_RESET __HAL_RCC_HASH_FORCE_RESET\r
+#define __HASH_RELEASE_RESET __HAL_RCC_HASH_RELEASE_RESET\r
+#define __HASH_CLK_SLEEP_ENABLE __HAL_RCC_HASH_CLK_SLEEP_ENABLE\r
+#define __HASH_CLK_SLEEP_DISABLE __HAL_RCC_HASH_CLK_SLEEP_DISABLE\r
+#define __HASH_CLK_DISABLE __HAL_RCC_HASH_CLK_DISABLE\r
+#define __SPI5_CLK_ENABLE __HAL_RCC_SPI5_CLK_ENABLE\r
+#define __SPI5_CLK_DISABLE __HAL_RCC_SPI5_CLK_DISABLE\r
+#define __SPI5_FORCE_RESET __HAL_RCC_SPI5_FORCE_RESET\r
+#define __SPI5_RELEASE_RESET __HAL_RCC_SPI5_RELEASE_RESET\r
+#define __SPI5_CLK_SLEEP_ENABLE __HAL_RCC_SPI5_CLK_SLEEP_ENABLE\r
+#define __SPI5_CLK_SLEEP_DISABLE __HAL_RCC_SPI5_CLK_SLEEP_DISABLE\r
+#define __SPI6_CLK_ENABLE __HAL_RCC_SPI6_CLK_ENABLE\r
+#define __SPI6_CLK_DISABLE __HAL_RCC_SPI6_CLK_DISABLE\r
+#define __SPI6_FORCE_RESET __HAL_RCC_SPI6_FORCE_RESET\r
+#define __SPI6_RELEASE_RESET __HAL_RCC_SPI6_RELEASE_RESET\r
+#define __SPI6_CLK_SLEEP_ENABLE __HAL_RCC_SPI6_CLK_SLEEP_ENABLE\r
+#define __SPI6_CLK_SLEEP_DISABLE __HAL_RCC_SPI6_CLK_SLEEP_DISABLE\r
+#define __LTDC_CLK_ENABLE __HAL_RCC_LTDC_CLK_ENABLE\r
+#define __LTDC_CLK_DISABLE __HAL_RCC_LTDC_CLK_DISABLE\r
+#define __LTDC_FORCE_RESET __HAL_RCC_LTDC_FORCE_RESET\r
+#define __LTDC_RELEASE_RESET __HAL_RCC_LTDC_RELEASE_RESET\r
+#define __LTDC_CLK_SLEEP_ENABLE __HAL_RCC_LTDC_CLK_SLEEP_ENABLE\r
+#define __ETHMAC_CLK_SLEEP_ENABLE __HAL_RCC_ETHMAC_CLK_SLEEP_ENABLE\r
+#define __ETHMAC_CLK_SLEEP_DISABLE __HAL_RCC_ETHMAC_CLK_SLEEP_DISABLE\r
+#define __ETHMACTX_CLK_SLEEP_ENABLE __HAL_RCC_ETHMACTX_CLK_SLEEP_ENABLE\r
+#define __ETHMACTX_CLK_SLEEP_DISABLE __HAL_RCC_ETHMACTX_CLK_SLEEP_DISABLE\r
+#define __ETHMACRX_CLK_SLEEP_ENABLE __HAL_RCC_ETHMACRX_CLK_SLEEP_ENABLE\r
+#define __ETHMACRX_CLK_SLEEP_DISABLE __HAL_RCC_ETHMACRX_CLK_SLEEP_DISABLE\r
+#define __TIM12_CLK_SLEEP_ENABLE __HAL_RCC_TIM12_CLK_SLEEP_ENABLE\r
+#define __TIM12_CLK_SLEEP_DISABLE __HAL_RCC_TIM12_CLK_SLEEP_DISABLE\r
+#define __TIM13_CLK_SLEEP_ENABLE __HAL_RCC_TIM13_CLK_SLEEP_ENABLE\r
+#define __TIM13_CLK_SLEEP_DISABLE __HAL_RCC_TIM13_CLK_SLEEP_DISABLE\r
+#define __TIM14_CLK_SLEEP_ENABLE __HAL_RCC_TIM14_CLK_SLEEP_ENABLE\r
+#define __TIM14_CLK_SLEEP_DISABLE __HAL_RCC_TIM14_CLK_SLEEP_DISABLE\r
+#define __BKPSRAM_CLK_ENABLE __HAL_RCC_BKPSRAM_CLK_ENABLE\r
+#define __BKPSRAM_CLK_DISABLE __HAL_RCC_BKPSRAM_CLK_DISABLE\r
+#define __BKPSRAM_CLK_SLEEP_ENABLE __HAL_RCC_BKPSRAM_CLK_SLEEP_ENABLE\r
+#define __BKPSRAM_CLK_SLEEP_DISABLE __HAL_RCC_BKPSRAM_CLK_SLEEP_DISABLE\r
+#define __CCMDATARAMEN_CLK_ENABLE __HAL_RCC_CCMDATARAMEN_CLK_ENABLE\r
+#define __CCMDATARAMEN_CLK_DISABLE __HAL_RCC_CCMDATARAMEN_CLK_DISABLE\r
+#define __USART6_CLK_ENABLE __HAL_RCC_USART6_CLK_ENABLE\r
+#define __USART6_CLK_DISABLE __HAL_RCC_USART6_CLK_DISABLE\r
+#define __USART6_FORCE_RESET __HAL_RCC_USART6_FORCE_RESET\r
+#define __USART6_RELEASE_RESET __HAL_RCC_USART6_RELEASE_RESET\r
+#define __USART6_CLK_SLEEP_ENABLE __HAL_RCC_USART6_CLK_SLEEP_ENABLE\r
+#define __USART6_CLK_SLEEP_DISABLE __HAL_RCC_USART6_CLK_SLEEP_DISABLE\r
+#define __SPI4_CLK_ENABLE __HAL_RCC_SPI4_CLK_ENABLE\r
+#define __SPI4_CLK_DISABLE __HAL_RCC_SPI4_CLK_DISABLE\r
+#define __SPI4_FORCE_RESET __HAL_RCC_SPI4_FORCE_RESET\r
+#define __SPI4_RELEASE_RESET __HAL_RCC_SPI4_RELEASE_RESET\r
+#define __SPI4_CLK_SLEEP_ENABLE __HAL_RCC_SPI4_CLK_SLEEP_ENABLE\r
+#define __SPI4_CLK_SLEEP_DISABLE __HAL_RCC_SPI4_CLK_SLEEP_DISABLE\r
+#define __GPIOI_CLK_ENABLE __HAL_RCC_GPIOI_CLK_ENABLE\r
+#define __GPIOI_CLK_DISABLE __HAL_RCC_GPIOI_CLK_DISABLE\r
+#define __GPIOI_FORCE_RESET __HAL_RCC_GPIOI_FORCE_RESET\r
+#define __GPIOI_RELEASE_RESET __HAL_RCC_GPIOI_RELEASE_RESET\r
+#define __GPIOI_CLK_SLEEP_ENABLE __HAL_RCC_GPIOI_CLK_SLEEP_ENABLE\r
+#define __GPIOI_CLK_SLEEP_DISABLE __HAL_RCC_GPIOI_CLK_SLEEP_DISABLE\r
+#define __GPIOJ_CLK_ENABLE __HAL_RCC_GPIOJ_CLK_ENABLE\r
+#define __GPIOJ_CLK_DISABLE __HAL_RCC_GPIOJ_CLK_DISABLE\r
+#define __GPIOJ_FORCE_RESET __HAL_RCC_GPIOJ_FORCE_RESET\r
+#define __GPIOJ_RELEASE_RESET __HAL_RCC_GPIOJ_RELEASE_RESET\r
+#define __GPIOJ_CLK_SLEEP_ENABLE __HAL_RCC_GPIOJ_CLK_SLEEP_ENABLE\r
+#define __GPIOJ_CLK_SLEEP_DISABLE __HAL_RCC_GPIOJ_CLK_SLEEP_DISABLE\r
+#define __GPIOK_CLK_ENABLE __HAL_RCC_GPIOK_CLK_ENABLE\r
+#define __GPIOK_CLK_DISABLE __HAL_RCC_GPIOK_CLK_DISABLE\r
+#define __GPIOK_RELEASE_RESET __HAL_RCC_GPIOK_RELEASE_RESET\r
+#define __GPIOK_CLK_SLEEP_ENABLE __HAL_RCC_GPIOK_CLK_SLEEP_ENABLE\r
+#define __GPIOK_CLK_SLEEP_DISABLE __HAL_RCC_GPIOK_CLK_SLEEP_DISABLE\r
+#define __ETH_CLK_ENABLE __HAL_RCC_ETH_CLK_ENABLE\r
+#define __ETH_CLK_DISABLE __HAL_RCC_ETH_CLK_DISABLE\r
+#define __DCMI_CLK_ENABLE __HAL_RCC_DCMI_CLK_ENABLE\r
+#define __DCMI_CLK_DISABLE __HAL_RCC_DCMI_CLK_DISABLE\r
+#define __DCMI_FORCE_RESET __HAL_RCC_DCMI_FORCE_RESET\r
+#define __DCMI_RELEASE_RESET __HAL_RCC_DCMI_RELEASE_RESET\r
+#define __DCMI_CLK_SLEEP_ENABLE __HAL_RCC_DCMI_CLK_SLEEP_ENABLE\r
+#define __DCMI_CLK_SLEEP_DISABLE __HAL_RCC_DCMI_CLK_SLEEP_DISABLE\r
+#define __UART7_CLK_ENABLE __HAL_RCC_UART7_CLK_ENABLE\r
+#define __UART7_CLK_DISABLE __HAL_RCC_UART7_CLK_DISABLE\r
+#define __UART7_RELEASE_RESET __HAL_RCC_UART7_RELEASE_RESET\r
+#define __UART7_FORCE_RESET __HAL_RCC_UART7_FORCE_RESET\r
+#define __UART7_CLK_SLEEP_ENABLE __HAL_RCC_UART7_CLK_SLEEP_ENABLE\r
+#define __UART7_CLK_SLEEP_DISABLE __HAL_RCC_UART7_CLK_SLEEP_DISABLE\r
+#define __UART8_CLK_ENABLE __HAL_RCC_UART8_CLK_ENABLE\r
+#define __UART8_CLK_DISABLE __HAL_RCC_UART8_CLK_DISABLE\r
+#define __UART8_FORCE_RESET __HAL_RCC_UART8_FORCE_RESET\r
+#define __UART8_RELEASE_RESET __HAL_RCC_UART8_RELEASE_RESET\r
+#define __UART8_CLK_SLEEP_ENABLE __HAL_RCC_UART8_CLK_SLEEP_ENABLE\r
+#define __UART8_CLK_SLEEP_DISABLE __HAL_RCC_UART8_CLK_SLEEP_DISABLE\r
+#define __OTGHS_CLK_SLEEP_ENABLE __HAL_RCC_USB_OTG_HS_CLK_SLEEP_ENABLE\r
+#define __OTGHS_CLK_SLEEP_DISABLE __HAL_RCC_USB_OTG_HS_CLK_SLEEP_DISABLE\r
+#define __OTGHS_FORCE_RESET __HAL_RCC_USB_OTG_HS_FORCE_RESET\r
+#define __OTGHS_RELEASE_RESET __HAL_RCC_USB_OTG_HS_RELEASE_RESET\r
+#define __OTGHSULPI_CLK_SLEEP_ENABLE __HAL_RCC_USB_OTG_HS_ULPI_CLK_SLEEP_ENABLE\r
+#define __OTGHSULPI_CLK_SLEEP_DISABLE __HAL_RCC_USB_OTG_HS_ULPI_CLK_SLEEP_DISABLE\r
+#define __HAL_RCC_OTGHS_CLK_SLEEP_ENABLE __HAL_RCC_USB_OTG_HS_CLK_SLEEP_ENABLE\r
+#define __HAL_RCC_OTGHS_CLK_SLEEP_DISABLE __HAL_RCC_USB_OTG_HS_CLK_SLEEP_DISABLE\r
+#define __HAL_RCC_OTGHS_IS_CLK_SLEEP_ENABLED __HAL_RCC_USB_OTG_HS_IS_CLK_SLEEP_ENABLED\r
+#define __HAL_RCC_OTGHS_IS_CLK_SLEEP_DISABLED __HAL_RCC_USB_OTG_HS_IS_CLK_SLEEP_DISABLED\r
+#define __HAL_RCC_OTGHS_FORCE_RESET __HAL_RCC_USB_OTG_HS_FORCE_RESET\r
+#define __HAL_RCC_OTGHS_RELEASE_RESET __HAL_RCC_USB_OTG_HS_RELEASE_RESET\r
+#define __HAL_RCC_OTGHSULPI_CLK_SLEEP_ENABLE __HAL_RCC_USB_OTG_HS_ULPI_CLK_SLEEP_ENABLE\r
+#define __HAL_RCC_OTGHSULPI_CLK_SLEEP_DISABLE __HAL_RCC_USB_OTG_HS_ULPI_CLK_SLEEP_DISABLE\r
+#define __HAL_RCC_OTGHSULPI_IS_CLK_SLEEP_ENABLED __HAL_RCC_USB_OTG_HS_ULPI_IS_CLK_SLEEP_ENABLED\r
+#define __HAL_RCC_OTGHSULPI_IS_CLK_SLEEP_DISABLED __HAL_RCC_USB_OTG_HS_ULPI_IS_CLK_SLEEP_DISABLED\r
+#define __SRAM3_CLK_SLEEP_ENABLE __HAL_RCC_SRAM3_CLK_SLEEP_ENABLE\r
+#define __CAN2_CLK_SLEEP_ENABLE __HAL_RCC_CAN2_CLK_SLEEP_ENABLE\r
+#define __CAN2_CLK_SLEEP_DISABLE __HAL_RCC_CAN2_CLK_SLEEP_DISABLE\r
+#define __DAC_CLK_SLEEP_ENABLE __HAL_RCC_DAC_CLK_SLEEP_ENABLE\r
+#define __DAC_CLK_SLEEP_DISABLE __HAL_RCC_DAC_CLK_SLEEP_DISABLE\r
+#define __ADC2_CLK_SLEEP_ENABLE __HAL_RCC_ADC2_CLK_SLEEP_ENABLE\r
+#define __ADC2_CLK_SLEEP_DISABLE __HAL_RCC_ADC2_CLK_SLEEP_DISABLE\r
+#define __ADC3_CLK_SLEEP_ENABLE __HAL_RCC_ADC3_CLK_SLEEP_ENABLE\r
+#define __ADC3_CLK_SLEEP_DISABLE __HAL_RCC_ADC3_CLK_SLEEP_DISABLE\r
+#define __FSMC_FORCE_RESET __HAL_RCC_FSMC_FORCE_RESET\r
+#define __FSMC_RELEASE_RESET __HAL_RCC_FSMC_RELEASE_RESET\r
+#define __FSMC_CLK_SLEEP_ENABLE __HAL_RCC_FSMC_CLK_SLEEP_ENABLE\r
+#define __FSMC_CLK_SLEEP_DISABLE __HAL_RCC_FSMC_CLK_SLEEP_DISABLE\r
+#define __SDIO_FORCE_RESET __HAL_RCC_SDIO_FORCE_RESET\r
+#define __SDIO_RELEASE_RESET __HAL_RCC_SDIO_RELEASE_RESET\r
+#define __SDIO_CLK_SLEEP_DISABLE __HAL_RCC_SDIO_CLK_SLEEP_DISABLE\r
+#define __SDIO_CLK_SLEEP_ENABLE __HAL_RCC_SDIO_CLK_SLEEP_ENABLE\r
+#define __DMA2D_CLK_ENABLE __HAL_RCC_DMA2D_CLK_ENABLE\r
+#define __DMA2D_CLK_DISABLE __HAL_RCC_DMA2D_CLK_DISABLE\r
+#define __DMA2D_FORCE_RESET __HAL_RCC_DMA2D_FORCE_RESET\r
+#define __DMA2D_RELEASE_RESET __HAL_RCC_DMA2D_RELEASE_RESET\r
+#define __DMA2D_CLK_SLEEP_ENABLE __HAL_RCC_DMA2D_CLK_SLEEP_ENABLE\r
+#define __DMA2D_CLK_SLEEP_DISABLE __HAL_RCC_DMA2D_CLK_SLEEP_DISABLE\r
+\r
+/* alias define maintained for legacy */\r
+#define __HAL_RCC_OTGFS_FORCE_RESET __HAL_RCC_USB_OTG_FS_FORCE_RESET\r
+#define __HAL_RCC_OTGFS_RELEASE_RESET __HAL_RCC_USB_OTG_FS_RELEASE_RESET\r
+\r
+#define __ADC12_CLK_ENABLE __HAL_RCC_ADC12_CLK_ENABLE\r
+#define __ADC12_CLK_DISABLE __HAL_RCC_ADC12_CLK_DISABLE\r
+#define __ADC34_CLK_ENABLE __HAL_RCC_ADC34_CLK_ENABLE\r
+#define __ADC34_CLK_DISABLE __HAL_RCC_ADC34_CLK_DISABLE\r
+#define __DAC2_CLK_ENABLE __HAL_RCC_DAC2_CLK_ENABLE\r
+#define __DAC2_CLK_DISABLE __HAL_RCC_DAC2_CLK_DISABLE\r
+#define __TIM18_CLK_ENABLE __HAL_RCC_TIM18_CLK_ENABLE\r
+#define __TIM18_CLK_DISABLE __HAL_RCC_TIM18_CLK_DISABLE\r
+#define __TIM19_CLK_ENABLE __HAL_RCC_TIM19_CLK_ENABLE\r
+#define __TIM19_CLK_DISABLE __HAL_RCC_TIM19_CLK_DISABLE\r
+#define __TIM20_CLK_ENABLE __HAL_RCC_TIM20_CLK_ENABLE\r
+#define __TIM20_CLK_DISABLE __HAL_RCC_TIM20_CLK_DISABLE\r
+#define __HRTIM1_CLK_ENABLE __HAL_RCC_HRTIM1_CLK_ENABLE\r
+#define __HRTIM1_CLK_DISABLE __HAL_RCC_HRTIM1_CLK_DISABLE\r
+#define __SDADC1_CLK_ENABLE __HAL_RCC_SDADC1_CLK_ENABLE\r
+#define __SDADC2_CLK_ENABLE __HAL_RCC_SDADC2_CLK_ENABLE\r
+#define __SDADC3_CLK_ENABLE __HAL_RCC_SDADC3_CLK_ENABLE\r
+#define __SDADC1_CLK_DISABLE __HAL_RCC_SDADC1_CLK_DISABLE\r
+#define __SDADC2_CLK_DISABLE __HAL_RCC_SDADC2_CLK_DISABLE\r
+#define __SDADC3_CLK_DISABLE __HAL_RCC_SDADC3_CLK_DISABLE\r
+\r
+#define __ADC12_FORCE_RESET __HAL_RCC_ADC12_FORCE_RESET\r
+#define __ADC12_RELEASE_RESET __HAL_RCC_ADC12_RELEASE_RESET\r
+#define __ADC34_FORCE_RESET __HAL_RCC_ADC34_FORCE_RESET\r
+#define __ADC34_RELEASE_RESET __HAL_RCC_ADC34_RELEASE_RESET\r
+#define __DAC2_FORCE_RESET __HAL_RCC_DAC2_FORCE_RESET\r
+#define __DAC2_RELEASE_RESET __HAL_RCC_DAC2_RELEASE_RESET\r
+#define __TIM18_FORCE_RESET __HAL_RCC_TIM18_FORCE_RESET\r
+#define __TIM18_RELEASE_RESET __HAL_RCC_TIM18_RELEASE_RESET\r
+#define __TIM19_FORCE_RESET __HAL_RCC_TIM19_FORCE_RESET\r
+#define __TIM19_RELEASE_RESET __HAL_RCC_TIM19_RELEASE_RESET\r
+#define __TIM20_FORCE_RESET __HAL_RCC_TIM20_FORCE_RESET\r
+#define __TIM20_RELEASE_RESET __HAL_RCC_TIM20_RELEASE_RESET\r
+#define __HRTIM1_FORCE_RESET __HAL_RCC_HRTIM1_FORCE_RESET\r
+#define __HRTIM1_RELEASE_RESET __HAL_RCC_HRTIM1_RELEASE_RESET\r
+#define __SDADC1_FORCE_RESET __HAL_RCC_SDADC1_FORCE_RESET\r
+#define __SDADC2_FORCE_RESET __HAL_RCC_SDADC2_FORCE_RESET\r
+#define __SDADC3_FORCE_RESET __HAL_RCC_SDADC3_FORCE_RESET\r
+#define __SDADC1_RELEASE_RESET __HAL_RCC_SDADC1_RELEASE_RESET\r
+#define __SDADC2_RELEASE_RESET __HAL_RCC_SDADC2_RELEASE_RESET\r
+#define __SDADC3_RELEASE_RESET __HAL_RCC_SDADC3_RELEASE_RESET\r
+\r
+#define __ADC1_IS_CLK_ENABLED __HAL_RCC_ADC1_IS_CLK_ENABLED\r
+#define __ADC1_IS_CLK_DISABLED __HAL_RCC_ADC1_IS_CLK_DISABLED\r
+#define __ADC12_IS_CLK_ENABLED __HAL_RCC_ADC12_IS_CLK_ENABLED\r
+#define __ADC12_IS_CLK_DISABLED __HAL_RCC_ADC12_IS_CLK_DISABLED\r
+#define __ADC34_IS_CLK_ENABLED __HAL_RCC_ADC34_IS_CLK_ENABLED\r
+#define __ADC34_IS_CLK_DISABLED __HAL_RCC_ADC34_IS_CLK_DISABLED\r
+#define __CEC_IS_CLK_ENABLED __HAL_RCC_CEC_IS_CLK_ENABLED\r
+#define __CEC_IS_CLK_DISABLED __HAL_RCC_CEC_IS_CLK_DISABLED\r
+#define __CRC_IS_CLK_ENABLED __HAL_RCC_CRC_IS_CLK_ENABLED\r
+#define __CRC_IS_CLK_DISABLED __HAL_RCC_CRC_IS_CLK_DISABLED\r
+#define __DAC1_IS_CLK_ENABLED __HAL_RCC_DAC1_IS_CLK_ENABLED\r
+#define __DAC1_IS_CLK_DISABLED __HAL_RCC_DAC1_IS_CLK_DISABLED\r
+#define __DAC2_IS_CLK_ENABLED __HAL_RCC_DAC2_IS_CLK_ENABLED\r
+#define __DAC2_IS_CLK_DISABLED __HAL_RCC_DAC2_IS_CLK_DISABLED\r
+#define __DMA1_IS_CLK_ENABLED __HAL_RCC_DMA1_IS_CLK_ENABLED\r
+#define __DMA1_IS_CLK_DISABLED __HAL_RCC_DMA1_IS_CLK_DISABLED\r
+#define __DMA2_IS_CLK_ENABLED __HAL_RCC_DMA2_IS_CLK_ENABLED\r
+#define __DMA2_IS_CLK_DISABLED __HAL_RCC_DMA2_IS_CLK_DISABLED\r
+#define __FLITF_IS_CLK_ENABLED __HAL_RCC_FLITF_IS_CLK_ENABLED\r
+#define __FLITF_IS_CLK_DISABLED __HAL_RCC_FLITF_IS_CLK_DISABLED\r
+#define __FMC_IS_CLK_ENABLED __HAL_RCC_FMC_IS_CLK_ENABLED\r
+#define __FMC_IS_CLK_DISABLED __HAL_RCC_FMC_IS_CLK_DISABLED\r
+#define __GPIOA_IS_CLK_ENABLED __HAL_RCC_GPIOA_IS_CLK_ENABLED\r
+#define __GPIOA_IS_CLK_DISABLED __HAL_RCC_GPIOA_IS_CLK_DISABLED\r
+#define __GPIOB_IS_CLK_ENABLED __HAL_RCC_GPIOB_IS_CLK_ENABLED\r
+#define __GPIOB_IS_CLK_DISABLED __HAL_RCC_GPIOB_IS_CLK_DISABLED\r
+#define __GPIOC_IS_CLK_ENABLED __HAL_RCC_GPIOC_IS_CLK_ENABLED\r
+#define __GPIOC_IS_CLK_DISABLED __HAL_RCC_GPIOC_IS_CLK_DISABLED\r
+#define __GPIOD_IS_CLK_ENABLED __HAL_RCC_GPIOD_IS_CLK_ENABLED\r
+#define __GPIOD_IS_CLK_DISABLED __HAL_RCC_GPIOD_IS_CLK_DISABLED\r
+#define __GPIOE_IS_CLK_ENABLED __HAL_RCC_GPIOE_IS_CLK_ENABLED\r
+#define __GPIOE_IS_CLK_DISABLED __HAL_RCC_GPIOE_IS_CLK_DISABLED\r
+#define __GPIOF_IS_CLK_ENABLED __HAL_RCC_GPIOF_IS_CLK_ENABLED\r
+#define __GPIOF_IS_CLK_DISABLED __HAL_RCC_GPIOF_IS_CLK_DISABLED\r
+#define __GPIOG_IS_CLK_ENABLED __HAL_RCC_GPIOG_IS_CLK_ENABLED\r
+#define __GPIOG_IS_CLK_DISABLED __HAL_RCC_GPIOG_IS_CLK_DISABLED\r
+#define __GPIOH_IS_CLK_ENABLED __HAL_RCC_GPIOH_IS_CLK_ENABLED\r
+#define __GPIOH_IS_CLK_DISABLED __HAL_RCC_GPIOH_IS_CLK_DISABLED\r
+#define __HRTIM1_IS_CLK_ENABLED __HAL_RCC_HRTIM1_IS_CLK_ENABLED\r
+#define __HRTIM1_IS_CLK_DISABLED __HAL_RCC_HRTIM1_IS_CLK_DISABLED\r
+#define __I2C1_IS_CLK_ENABLED __HAL_RCC_I2C1_IS_CLK_ENABLED\r
+#define __I2C1_IS_CLK_DISABLED __HAL_RCC_I2C1_IS_CLK_DISABLED\r
+#define __I2C2_IS_CLK_ENABLED __HAL_RCC_I2C2_IS_CLK_ENABLED\r
+#define __I2C2_IS_CLK_DISABLED __HAL_RCC_I2C2_IS_CLK_DISABLED\r
+#define __I2C3_IS_CLK_ENABLED __HAL_RCC_I2C3_IS_CLK_ENABLED\r
+#define __I2C3_IS_CLK_DISABLED __HAL_RCC_I2C3_IS_CLK_DISABLED\r
+#define __PWR_IS_CLK_ENABLED __HAL_RCC_PWR_IS_CLK_ENABLED\r
+#define __PWR_IS_CLK_DISABLED __HAL_RCC_PWR_IS_CLK_DISABLED\r
+#define __SYSCFG_IS_CLK_ENABLED __HAL_RCC_SYSCFG_IS_CLK_ENABLED\r
+#define __SYSCFG_IS_CLK_DISABLED __HAL_RCC_SYSCFG_IS_CLK_DISABLED\r
+#define __SPI1_IS_CLK_ENABLED __HAL_RCC_SPI1_IS_CLK_ENABLED\r
+#define __SPI1_IS_CLK_DISABLED __HAL_RCC_SPI1_IS_CLK_DISABLED\r
+#define __SPI2_IS_CLK_ENABLED __HAL_RCC_SPI2_IS_CLK_ENABLED\r
+#define __SPI2_IS_CLK_DISABLED __HAL_RCC_SPI2_IS_CLK_DISABLED\r
+#define __SPI3_IS_CLK_ENABLED __HAL_RCC_SPI3_IS_CLK_ENABLED\r
+#define __SPI3_IS_CLK_DISABLED __HAL_RCC_SPI3_IS_CLK_DISABLED\r
+#define __SPI4_IS_CLK_ENABLED __HAL_RCC_SPI4_IS_CLK_ENABLED\r
+#define __SPI4_IS_CLK_DISABLED __HAL_RCC_SPI4_IS_CLK_DISABLED\r
+#define __SDADC1_IS_CLK_ENABLED __HAL_RCC_SDADC1_IS_CLK_ENABLED\r
+#define __SDADC1_IS_CLK_DISABLED __HAL_RCC_SDADC1_IS_CLK_DISABLED\r
+#define __SDADC2_IS_CLK_ENABLED __HAL_RCC_SDADC2_IS_CLK_ENABLED\r
+#define __SDADC2_IS_CLK_DISABLED __HAL_RCC_SDADC2_IS_CLK_DISABLED\r
+#define __SDADC3_IS_CLK_ENABLED __HAL_RCC_SDADC3_IS_CLK_ENABLED\r
+#define __SDADC3_IS_CLK_DISABLED __HAL_RCC_SDADC3_IS_CLK_DISABLED\r
+#define __SRAM_IS_CLK_ENABLED __HAL_RCC_SRAM_IS_CLK_ENABLED\r
+#define __SRAM_IS_CLK_DISABLED __HAL_RCC_SRAM_IS_CLK_DISABLED\r
+#define __TIM1_IS_CLK_ENABLED __HAL_RCC_TIM1_IS_CLK_ENABLED\r
+#define __TIM1_IS_CLK_DISABLED __HAL_RCC_TIM1_IS_CLK_DISABLED\r
+#define __TIM2_IS_CLK_ENABLED __HAL_RCC_TIM2_IS_CLK_ENABLED\r
+#define __TIM2_IS_CLK_DISABLED __HAL_RCC_TIM2_IS_CLK_DISABLED\r
+#define __TIM3_IS_CLK_ENABLED __HAL_RCC_TIM3_IS_CLK_ENABLED\r
+#define __TIM3_IS_CLK_DISABLED __HAL_RCC_TIM3_IS_CLK_DISABLED\r
+#define __TIM4_IS_CLK_ENABLED __HAL_RCC_TIM4_IS_CLK_ENABLED\r
+#define __TIM4_IS_CLK_DISABLED __HAL_RCC_TIM4_IS_CLK_DISABLED\r
+#define __TIM5_IS_CLK_ENABLED __HAL_RCC_TIM5_IS_CLK_ENABLED\r
+#define __TIM5_IS_CLK_DISABLED __HAL_RCC_TIM5_IS_CLK_DISABLED\r
+#define __TIM6_IS_CLK_ENABLED __HAL_RCC_TIM6_IS_CLK_ENABLED\r
+#define __TIM6_IS_CLK_DISABLED __HAL_RCC_TIM6_IS_CLK_DISABLED\r
+#define __TIM7_IS_CLK_ENABLED __HAL_RCC_TIM7_IS_CLK_ENABLED\r
+#define __TIM7_IS_CLK_DISABLED __HAL_RCC_TIM7_IS_CLK_DISABLED\r
+#define __TIM8_IS_CLK_ENABLED __HAL_RCC_TIM8_IS_CLK_ENABLED\r
+#define __TIM8_IS_CLK_DISABLED __HAL_RCC_TIM8_IS_CLK_DISABLED\r
+#define __TIM12_IS_CLK_ENABLED __HAL_RCC_TIM12_IS_CLK_ENABLED\r
+#define __TIM12_IS_CLK_DISABLED __HAL_RCC_TIM12_IS_CLK_DISABLED\r
+#define __TIM13_IS_CLK_ENABLED __HAL_RCC_TIM13_IS_CLK_ENABLED\r
+#define __TIM13_IS_CLK_DISABLED __HAL_RCC_TIM13_IS_CLK_DISABLED\r
+#define __TIM14_IS_CLK_ENABLED __HAL_RCC_TIM14_IS_CLK_ENABLED\r
+#define __TIM14_IS_CLK_DISABLED __HAL_RCC_TIM14_IS_CLK_DISABLED\r
+#define __TIM15_IS_CLK_ENABLED __HAL_RCC_TIM15_IS_CLK_ENABLED\r
+#define __TIM15_IS_CLK_DISABLED __HAL_RCC_TIM15_IS_CLK_DISABLED\r
+#define __TIM16_IS_CLK_ENABLED __HAL_RCC_TIM16_IS_CLK_ENABLED\r
+#define __TIM16_IS_CLK_DISABLED __HAL_RCC_TIM16_IS_CLK_DISABLED\r
+#define __TIM17_IS_CLK_ENABLED __HAL_RCC_TIM17_IS_CLK_ENABLED\r
+#define __TIM17_IS_CLK_DISABLED __HAL_RCC_TIM17_IS_CLK_DISABLED\r
+#define __TIM18_IS_CLK_ENABLED __HAL_RCC_TIM18_IS_CLK_ENABLED\r
+#define __TIM18_IS_CLK_DISABLED __HAL_RCC_TIM18_IS_CLK_DISABLED\r
+#define __TIM19_IS_CLK_ENABLED __HAL_RCC_TIM19_IS_CLK_ENABLED\r
+#define __TIM19_IS_CLK_DISABLED __HAL_RCC_TIM19_IS_CLK_DISABLED\r
+#define __TIM20_IS_CLK_ENABLED __HAL_RCC_TIM20_IS_CLK_ENABLED\r
+#define __TIM20_IS_CLK_DISABLED __HAL_RCC_TIM20_IS_CLK_DISABLED\r
+#define __TSC_IS_CLK_ENABLED __HAL_RCC_TSC_IS_CLK_ENABLED\r
+#define __TSC_IS_CLK_DISABLED __HAL_RCC_TSC_IS_CLK_DISABLED\r
+#define __UART4_IS_CLK_ENABLED __HAL_RCC_UART4_IS_CLK_ENABLED\r
+#define __UART4_IS_CLK_DISABLED __HAL_RCC_UART4_IS_CLK_DISABLED\r
+#define __UART5_IS_CLK_ENABLED __HAL_RCC_UART5_IS_CLK_ENABLED\r
+#define __UART5_IS_CLK_DISABLED __HAL_RCC_UART5_IS_CLK_DISABLED\r
+#define __USART1_IS_CLK_ENABLED __HAL_RCC_USART1_IS_CLK_ENABLED\r
+#define __USART1_IS_CLK_DISABLED __HAL_RCC_USART1_IS_CLK_DISABLED\r
+#define __USART2_IS_CLK_ENABLED __HAL_RCC_USART2_IS_CLK_ENABLED\r
+#define __USART2_IS_CLK_DISABLED __HAL_RCC_USART2_IS_CLK_DISABLED\r
+#define __USART3_IS_CLK_ENABLED __HAL_RCC_USART3_IS_CLK_ENABLED\r
+#define __USART3_IS_CLK_DISABLED __HAL_RCC_USART3_IS_CLK_DISABLED\r
+#define __USB_IS_CLK_ENABLED __HAL_RCC_USB_IS_CLK_ENABLED\r
+#define __USB_IS_CLK_DISABLED __HAL_RCC_USB_IS_CLK_DISABLED\r
+#define __WWDG_IS_CLK_ENABLED __HAL_RCC_WWDG_IS_CLK_ENABLED\r
+#define __WWDG_IS_CLK_DISABLED __HAL_RCC_WWDG_IS_CLK_DISABLED\r
+\r
+#if defined(STM32L1)\r
+#define __HAL_RCC_CRYP_CLK_DISABLE __HAL_RCC_AES_CLK_DISABLE\r
+#define __HAL_RCC_CRYP_CLK_ENABLE __HAL_RCC_AES_CLK_ENABLE\r
+#define __HAL_RCC_CRYP_CLK_SLEEP_DISABLE __HAL_RCC_AES_CLK_SLEEP_DISABLE\r
+#define __HAL_RCC_CRYP_CLK_SLEEP_ENABLE __HAL_RCC_AES_CLK_SLEEP_ENABLE\r
+#define __HAL_RCC_CRYP_FORCE_RESET __HAL_RCC_AES_FORCE_RESET\r
+#define __HAL_RCC_CRYP_RELEASE_RESET __HAL_RCC_AES_RELEASE_RESET\r
+#endif /* STM32L1 */\r
+\r
+#if defined(STM32F4)\r
+#define __HAL_RCC_SDMMC1_FORCE_RESET __HAL_RCC_SDIO_FORCE_RESET\r
+#define __HAL_RCC_SDMMC1_RELEASE_RESET __HAL_RCC_SDIO_RELEASE_RESET\r
+#define __HAL_RCC_SDMMC1_CLK_SLEEP_ENABLE __HAL_RCC_SDIO_CLK_SLEEP_ENABLE\r
+#define __HAL_RCC_SDMMC1_CLK_SLEEP_DISABLE __HAL_RCC_SDIO_CLK_SLEEP_DISABLE\r
+#define __HAL_RCC_SDMMC1_CLK_ENABLE __HAL_RCC_SDIO_CLK_ENABLE\r
+#define __HAL_RCC_SDMMC1_CLK_DISABLE __HAL_RCC_SDIO_CLK_DISABLE\r
+#define __HAL_RCC_SDMMC1_IS_CLK_ENABLED __HAL_RCC_SDIO_IS_CLK_ENABLED\r
+#define __HAL_RCC_SDMMC1_IS_CLK_DISABLED __HAL_RCC_SDIO_IS_CLK_DISABLED\r
+#define Sdmmc1ClockSelection SdioClockSelection\r
+#define RCC_PERIPHCLK_SDMMC1 RCC_PERIPHCLK_SDIO\r
+#define RCC_SDMMC1CLKSOURCE_CLK48 RCC_SDIOCLKSOURCE_CK48\r
+#define RCC_SDMMC1CLKSOURCE_SYSCLK RCC_SDIOCLKSOURCE_SYSCLK\r
+#define __HAL_RCC_SDMMC1_CONFIG __HAL_RCC_SDIO_CONFIG\r
+#define __HAL_RCC_GET_SDMMC1_SOURCE __HAL_RCC_GET_SDIO_SOURCE\r
+#endif\r
+\r
+#if defined(STM32F7) || defined(STM32L4)\r
+#define __HAL_RCC_SDIO_FORCE_RESET __HAL_RCC_SDMMC1_FORCE_RESET\r
+#define __HAL_RCC_SDIO_RELEASE_RESET __HAL_RCC_SDMMC1_RELEASE_RESET\r
+#define __HAL_RCC_SDIO_CLK_SLEEP_ENABLE __HAL_RCC_SDMMC1_CLK_SLEEP_ENABLE\r
+#define __HAL_RCC_SDIO_CLK_SLEEP_DISABLE __HAL_RCC_SDMMC1_CLK_SLEEP_DISABLE\r
+#define __HAL_RCC_SDIO_CLK_ENABLE __HAL_RCC_SDMMC1_CLK_ENABLE\r
+#define __HAL_RCC_SDIO_CLK_DISABLE __HAL_RCC_SDMMC1_CLK_DISABLE\r
+#define __HAL_RCC_SDIO_IS_CLK_ENABLED __HAL_RCC_SDMMC1_IS_CLK_ENABLED\r
+#define __HAL_RCC_SDIO_IS_CLK_DISABLED __HAL_RCC_SDMMC1_IS_CLK_DISABLED\r
+#define SdioClockSelection Sdmmc1ClockSelection\r
+#define RCC_PERIPHCLK_SDIO RCC_PERIPHCLK_SDMMC1\r
+#define __HAL_RCC_SDIO_CONFIG __HAL_RCC_SDMMC1_CONFIG\r
+#define __HAL_RCC_GET_SDIO_SOURCE __HAL_RCC_GET_SDMMC1_SOURCE\r
+#endif\r
+\r
+#if defined(STM32F7)\r
+#define RCC_SDIOCLKSOURCE_CLK48 RCC_SDMMC1CLKSOURCE_CLK48\r
+#define RCC_SDIOCLKSOURCE_SYSCLK RCC_SDMMC1CLKSOURCE_SYSCLK\r
+#endif\r
+\r
+#if defined(STM32H7)\r
+#define __HAL_RCC_USB_OTG_HS_CLK_ENABLE() __HAL_RCC_USB1_OTG_HS_CLK_ENABLE()\r
+#define __HAL_RCC_USB_OTG_HS_ULPI_CLK_ENABLE() __HAL_RCC_USB1_OTG_HS_ULPI_CLK_ENABLE()\r
+#define __HAL_RCC_USB_OTG_HS_CLK_DISABLE() __HAL_RCC_USB1_OTG_HS_CLK_DISABLE()\r
+#define __HAL_RCC_USB_OTG_HS_ULPI_CLK_DISABLE() __HAL_RCC_USB1_OTG_HS_ULPI_CLK_DISABLE()\r
+#define __HAL_RCC_USB_OTG_HS_FORCE_RESET() __HAL_RCC_USB1_OTG_HS_FORCE_RESET()\r
+#define __HAL_RCC_USB_OTG_HS_RELEASE_RESET() __HAL_RCC_USB1_OTG_HS_RELEASE_RESET()\r
+#define __HAL_RCC_USB_OTG_HS_CLK_SLEEP_ENABLE() __HAL_RCC_USB1_OTG_HS_CLK_SLEEP_ENABLE()\r
+#define __HAL_RCC_USB_OTG_HS_ULPI_CLK_SLEEP_ENABLE() __HAL_RCC_USB1_OTG_HS_ULPI_CLK_SLEEP_ENABLE()\r
+#define __HAL_RCC_USB_OTG_HS_CLK_SLEEP_DISABLE() __HAL_RCC_USB1_OTG_HS_CLK_SLEEP_DISABLE()\r
+#define __HAL_RCC_USB_OTG_HS_ULPI_CLK_SLEEP_DISABLE() __HAL_RCC_USB1_OTG_HS_ULPI_CLK_SLEEP_DISABLE()\r
+\r
+#define __HAL_RCC_USB_OTG_FS_CLK_ENABLE() __HAL_RCC_USB2_OTG_FS_CLK_ENABLE()\r
+#define __HAL_RCC_USB_OTG_FS_ULPI_CLK_ENABLE() __HAL_RCC_USB2_OTG_FS_ULPI_CLK_ENABLE()\r
+#define __HAL_RCC_USB_OTG_FS_CLK_DISABLE() __HAL_RCC_USB2_OTG_FS_CLK_DISABLE()\r
+#define __HAL_RCC_USB_OTG_FS_ULPI_CLK_DISABLE() __HAL_RCC_USB2_OTG_FS_ULPI_CLK_DISABLE()\r
+#define __HAL_RCC_USB_OTG_FS_FORCE_RESET() __HAL_RCC_USB2_OTG_FS_FORCE_RESET()\r
+#define __HAL_RCC_USB_OTG_FS_RELEASE_RESET() __HAL_RCC_USB2_OTG_FS_RELEASE_RESET()\r
+#define __HAL_RCC_USB_OTG_FS_CLK_SLEEP_ENABLE() __HAL_RCC_USB2_OTG_FS_CLK_SLEEP_ENABLE()\r
+#define __HAL_RCC_USB_OTG_FS_ULPI_CLK_SLEEP_ENABLE() __HAL_RCC_USB2_OTG_FS_ULPI_CLK_SLEEP_ENABLE()\r
+#define __HAL_RCC_USB_OTG_FS_CLK_SLEEP_DISABLE() __HAL_RCC_USB2_OTG_FS_CLK_SLEEP_DISABLE()\r
+#define __HAL_RCC_USB_OTG_FS_ULPI_CLK_SLEEP_DISABLE() __HAL_RCC_USB2_OTG_FS_ULPI_CLK_SLEEP_DISABLE()\r
+#endif\r
+\r
+#define __HAL_RCC_I2SCLK __HAL_RCC_I2S_CONFIG\r
+#define __HAL_RCC_I2SCLK_CONFIG __HAL_RCC_I2S_CONFIG\r
+\r
+#define __RCC_PLLSRC RCC_GET_PLL_OSCSOURCE\r
+\r
+#define IS_RCC_MSIRANGE IS_RCC_MSI_CLOCK_RANGE\r
+#define IS_RCC_RTCCLK_SOURCE IS_RCC_RTCCLKSOURCE\r
+#define IS_RCC_SYSCLK_DIV IS_RCC_HCLK\r
+#define IS_RCC_HCLK_DIV IS_RCC_PCLK\r
+#define IS_RCC_PERIPHCLK IS_RCC_PERIPHCLOCK\r
+\r
+#define RCC_IT_HSI14 RCC_IT_HSI14RDY\r
+\r
+#define RCC_IT_CSSLSE RCC_IT_LSECSS\r
+#define RCC_IT_CSSHSE RCC_IT_CSS\r
+\r
+#define RCC_PLLMUL_3 RCC_PLL_MUL3\r
+#define RCC_PLLMUL_4 RCC_PLL_MUL4\r
+#define RCC_PLLMUL_6 RCC_PLL_MUL6\r
+#define RCC_PLLMUL_8 RCC_PLL_MUL8\r
+#define RCC_PLLMUL_12 RCC_PLL_MUL12\r
+#define RCC_PLLMUL_16 RCC_PLL_MUL16\r
+#define RCC_PLLMUL_24 RCC_PLL_MUL24\r
+#define RCC_PLLMUL_32 RCC_PLL_MUL32\r
+#define RCC_PLLMUL_48 RCC_PLL_MUL48\r
+\r
+#define RCC_PLLDIV_2 RCC_PLL_DIV2\r
+#define RCC_PLLDIV_3 RCC_PLL_DIV3\r
+#define RCC_PLLDIV_4 RCC_PLL_DIV4\r
+\r
+#define IS_RCC_MCOSOURCE IS_RCC_MCO1SOURCE\r
+#define __HAL_RCC_MCO_CONFIG __HAL_RCC_MCO1_CONFIG\r
+#define RCC_MCO_NODIV RCC_MCODIV_1\r
+#define RCC_MCO_DIV1 RCC_MCODIV_1\r
+#define RCC_MCO_DIV2 RCC_MCODIV_2\r
+#define RCC_MCO_DIV4 RCC_MCODIV_4\r
+#define RCC_MCO_DIV8 RCC_MCODIV_8\r
+#define RCC_MCO_DIV16 RCC_MCODIV_16\r
+#define RCC_MCO_DIV32 RCC_MCODIV_32\r
+#define RCC_MCO_DIV64 RCC_MCODIV_64\r
+#define RCC_MCO_DIV128 RCC_MCODIV_128\r
+#define RCC_MCOSOURCE_NONE RCC_MCO1SOURCE_NOCLOCK\r
+#define RCC_MCOSOURCE_LSI RCC_MCO1SOURCE_LSI\r
+#define RCC_MCOSOURCE_LSE RCC_MCO1SOURCE_LSE\r
+#define RCC_MCOSOURCE_SYSCLK RCC_MCO1SOURCE_SYSCLK\r
+#define RCC_MCOSOURCE_HSI RCC_MCO1SOURCE_HSI\r
+#define RCC_MCOSOURCE_HSI14 RCC_MCO1SOURCE_HSI14\r
+#define RCC_MCOSOURCE_HSI48 RCC_MCO1SOURCE_HSI48\r
+#define RCC_MCOSOURCE_HSE RCC_MCO1SOURCE_HSE\r
+#define RCC_MCOSOURCE_PLLCLK_DIV1 RCC_MCO1SOURCE_PLLCLK\r
+#define RCC_MCOSOURCE_PLLCLK_NODIV RCC_MCO1SOURCE_PLLCLK\r
+#define RCC_MCOSOURCE_PLLCLK_DIV2 RCC_MCO1SOURCE_PLLCLK_DIV2\r
+\r
+#if defined(STM32L4)\r
+#define RCC_RTCCLKSOURCE_NO_CLK RCC_RTCCLKSOURCE_NONE\r
+#elif defined(STM32WB) || defined(STM32G0)\r
+#else\r
+#define RCC_RTCCLKSOURCE_NONE RCC_RTCCLKSOURCE_NO_CLK\r
+#endif\r
+\r
+#define RCC_USBCLK_PLLSAI1 RCC_USBCLKSOURCE_PLLSAI1\r
+#define RCC_USBCLK_PLL RCC_USBCLKSOURCE_PLL\r
+#define RCC_USBCLK_MSI RCC_USBCLKSOURCE_MSI\r
+#define RCC_USBCLKSOURCE_PLLCLK RCC_USBCLKSOURCE_PLL\r
+#define RCC_USBPLLCLK_DIV1 RCC_USBCLKSOURCE_PLL\r
+#define RCC_USBPLLCLK_DIV1_5 RCC_USBCLKSOURCE_PLL_DIV1_5\r
+#define RCC_USBPLLCLK_DIV2 RCC_USBCLKSOURCE_PLL_DIV2\r
+#define RCC_USBPLLCLK_DIV3 RCC_USBCLKSOURCE_PLL_DIV3\r
+\r
+#define HSION_BitNumber RCC_HSION_BIT_NUMBER\r
+#define HSION_BITNUMBER RCC_HSION_BIT_NUMBER\r
+#define HSEON_BitNumber RCC_HSEON_BIT_NUMBER\r
+#define HSEON_BITNUMBER RCC_HSEON_BIT_NUMBER\r
+#define MSION_BITNUMBER RCC_MSION_BIT_NUMBER\r
+#define CSSON_BitNumber RCC_CSSON_BIT_NUMBER\r
+#define CSSON_BITNUMBER RCC_CSSON_BIT_NUMBER\r
+#define PLLON_BitNumber RCC_PLLON_BIT_NUMBER\r
+#define PLLON_BITNUMBER RCC_PLLON_BIT_NUMBER\r
+#define PLLI2SON_BitNumber RCC_PLLI2SON_BIT_NUMBER\r
+#define I2SSRC_BitNumber RCC_I2SSRC_BIT_NUMBER\r
+#define RTCEN_BitNumber RCC_RTCEN_BIT_NUMBER\r
+#define RTCEN_BITNUMBER RCC_RTCEN_BIT_NUMBER\r
+#define BDRST_BitNumber RCC_BDRST_BIT_NUMBER\r
+#define BDRST_BITNUMBER RCC_BDRST_BIT_NUMBER\r
+#define RTCRST_BITNUMBER RCC_RTCRST_BIT_NUMBER\r
+#define LSION_BitNumber RCC_LSION_BIT_NUMBER\r
+#define LSION_BITNUMBER RCC_LSION_BIT_NUMBER\r
+#define LSEON_BitNumber RCC_LSEON_BIT_NUMBER\r
+#define LSEON_BITNUMBER RCC_LSEON_BIT_NUMBER\r
+#define LSEBYP_BITNUMBER RCC_LSEBYP_BIT_NUMBER\r
+#define PLLSAION_BitNumber RCC_PLLSAION_BIT_NUMBER\r
+#define TIMPRE_BitNumber RCC_TIMPRE_BIT_NUMBER\r
+#define RMVF_BitNumber RCC_RMVF_BIT_NUMBER\r
+#define RMVF_BITNUMBER RCC_RMVF_BIT_NUMBER\r
+#define RCC_CR2_HSI14TRIM_BitNumber RCC_HSI14TRIM_BIT_NUMBER\r
+#define CR_BYTE2_ADDRESS RCC_CR_BYTE2_ADDRESS\r
+#define CIR_BYTE1_ADDRESS RCC_CIR_BYTE1_ADDRESS\r
+#define CIR_BYTE2_ADDRESS RCC_CIR_BYTE2_ADDRESS\r
+#define BDCR_BYTE0_ADDRESS RCC_BDCR_BYTE0_ADDRESS\r
+#define DBP_TIMEOUT_VALUE RCC_DBP_TIMEOUT_VALUE\r
+#define LSE_TIMEOUT_VALUE RCC_LSE_TIMEOUT_VALUE\r
+\r
+#define CR_HSION_BB RCC_CR_HSION_BB\r
+#define CR_CSSON_BB RCC_CR_CSSON_BB\r
+#define CR_PLLON_BB RCC_CR_PLLON_BB\r
+#define CR_PLLI2SON_BB RCC_CR_PLLI2SON_BB\r
+#define CR_MSION_BB RCC_CR_MSION_BB\r
+#define CSR_LSION_BB RCC_CSR_LSION_BB\r
+#define CSR_LSEON_BB RCC_CSR_LSEON_BB\r
+#define CSR_LSEBYP_BB RCC_CSR_LSEBYP_BB\r
+#define CSR_RTCEN_BB RCC_CSR_RTCEN_BB\r
+#define CSR_RTCRST_BB RCC_CSR_RTCRST_BB\r
+#define CFGR_I2SSRC_BB RCC_CFGR_I2SSRC_BB\r
+#define BDCR_RTCEN_BB RCC_BDCR_RTCEN_BB\r
+#define BDCR_BDRST_BB RCC_BDCR_BDRST_BB\r
+#define CR_HSEON_BB RCC_CR_HSEON_BB\r
+#define CSR_RMVF_BB RCC_CSR_RMVF_BB\r
+#define CR_PLLSAION_BB RCC_CR_PLLSAION_BB\r
+#define DCKCFGR_TIMPRE_BB RCC_DCKCFGR_TIMPRE_BB\r
+\r
+#define __HAL_RCC_CRS_ENABLE_FREQ_ERROR_COUNTER __HAL_RCC_CRS_FREQ_ERROR_COUNTER_ENABLE\r
+#define __HAL_RCC_CRS_DISABLE_FREQ_ERROR_COUNTER __HAL_RCC_CRS_FREQ_ERROR_COUNTER_DISABLE\r
+#define __HAL_RCC_CRS_ENABLE_AUTOMATIC_CALIB __HAL_RCC_CRS_AUTOMATIC_CALIB_ENABLE\r
+#define __HAL_RCC_CRS_DISABLE_AUTOMATIC_CALIB __HAL_RCC_CRS_AUTOMATIC_CALIB_DISABLE\r
+#define __HAL_RCC_CRS_CALCULATE_RELOADVALUE __HAL_RCC_CRS_RELOADVALUE_CALCULATE\r
+\r
+#define __HAL_RCC_GET_IT_SOURCE __HAL_RCC_GET_IT\r
+\r
+#define RCC_CRS_SYNCWARM RCC_CRS_SYNCWARN\r
+#define RCC_CRS_TRIMOV RCC_CRS_TRIMOVF\r
+\r
+#define RCC_PERIPHCLK_CK48 RCC_PERIPHCLK_CLK48\r
+#define RCC_CK48CLKSOURCE_PLLQ RCC_CLK48CLKSOURCE_PLLQ\r
+#define RCC_CK48CLKSOURCE_PLLSAIP RCC_CLK48CLKSOURCE_PLLSAIP\r
+#define RCC_CK48CLKSOURCE_PLLI2SQ RCC_CLK48CLKSOURCE_PLLI2SQ\r
+#define IS_RCC_CK48CLKSOURCE IS_RCC_CLK48CLKSOURCE\r
+#define RCC_SDIOCLKSOURCE_CK48 RCC_SDIOCLKSOURCE_CLK48\r
+\r
+#define __HAL_RCC_DFSDM_CLK_ENABLE __HAL_RCC_DFSDM1_CLK_ENABLE\r
+#define __HAL_RCC_DFSDM_CLK_DISABLE __HAL_RCC_DFSDM1_CLK_DISABLE\r
+#define __HAL_RCC_DFSDM_IS_CLK_ENABLED __HAL_RCC_DFSDM1_IS_CLK_ENABLED\r
+#define __HAL_RCC_DFSDM_IS_CLK_DISABLED __HAL_RCC_DFSDM1_IS_CLK_DISABLED\r
+#define __HAL_RCC_DFSDM_FORCE_RESET __HAL_RCC_DFSDM1_FORCE_RESET\r
+#define __HAL_RCC_DFSDM_RELEASE_RESET __HAL_RCC_DFSDM1_RELEASE_RESET\r
+#define __HAL_RCC_DFSDM_CLK_SLEEP_ENABLE __HAL_RCC_DFSDM1_CLK_SLEEP_ENABLE\r
+#define __HAL_RCC_DFSDM_CLK_SLEEP_DISABLE __HAL_RCC_DFSDM1_CLK_SLEEP_DISABLE\r
+#define __HAL_RCC_DFSDM_IS_CLK_SLEEP_ENABLED __HAL_RCC_DFSDM1_IS_CLK_SLEEP_ENABLED\r
+#define __HAL_RCC_DFSDM_IS_CLK_SLEEP_DISABLED __HAL_RCC_DFSDM1_IS_CLK_SLEEP_DISABLED\r
+#define DfsdmClockSelection Dfsdm1ClockSelection\r
+#define RCC_PERIPHCLK_DFSDM RCC_PERIPHCLK_DFSDM1\r
+#define RCC_DFSDMCLKSOURCE_PCLK RCC_DFSDM1CLKSOURCE_PCLK2\r
+#define RCC_DFSDMCLKSOURCE_SYSCLK RCC_DFSDM1CLKSOURCE_SYSCLK\r
+#define __HAL_RCC_DFSDM_CONFIG __HAL_RCC_DFSDM1_CONFIG\r
+#define __HAL_RCC_GET_DFSDM_SOURCE __HAL_RCC_GET_DFSDM1_SOURCE\r
+#define RCC_DFSDM1CLKSOURCE_PCLK RCC_DFSDM1CLKSOURCE_PCLK2\r
+#define RCC_SWPMI1CLKSOURCE_PCLK RCC_SWPMI1CLKSOURCE_PCLK1\r
+#define RCC_LPTIM1CLKSOURCE_PCLK RCC_LPTIM1CLKSOURCE_PCLK1\r
+#define RCC_LPTIM2CLKSOURCE_PCLK RCC_LPTIM2CLKSOURCE_PCLK1\r
+\r
+#define RCC_DFSDM1AUDIOCLKSOURCE_I2SAPB1 RCC_DFSDM1AUDIOCLKSOURCE_I2S1\r
+#define RCC_DFSDM1AUDIOCLKSOURCE_I2SAPB2 RCC_DFSDM1AUDIOCLKSOURCE_I2S2\r
+#define RCC_DFSDM2AUDIOCLKSOURCE_I2SAPB1 RCC_DFSDM2AUDIOCLKSOURCE_I2S1\r
+#define RCC_DFSDM2AUDIOCLKSOURCE_I2SAPB2 RCC_DFSDM2AUDIOCLKSOURCE_I2S2\r
+#define RCC_DFSDM1CLKSOURCE_APB2 RCC_DFSDM1CLKSOURCE_PCLK2\r
+#define RCC_DFSDM2CLKSOURCE_APB2 RCC_DFSDM2CLKSOURCE_PCLK2\r
+#define RCC_FMPI2C1CLKSOURCE_APB RCC_FMPI2C1CLKSOURCE_PCLK1\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup HAL_RNG_Aliased_Macros HAL RNG Aliased Macros maintained for legacy purpose\r
+ * @{\r
+ */\r
+#define HAL_RNG_ReadyCallback(__HANDLE__) HAL_RNG_ReadyDataCallback((__HANDLE__), uint32_t random32bit)\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup HAL_RTC_Aliased_Macros HAL RTC Aliased Macros maintained for legacy purpose\r
+ * @{\r
+ */\r
+#if defined (STM32G0) || defined (STM32L412xx) || defined (STM32L422xx)\r
+#else\r
+#define __HAL_RTC_CLEAR_FLAG __HAL_RTC_EXTI_CLEAR_FLAG\r
+#endif\r
+#define __HAL_RTC_DISABLE_IT __HAL_RTC_EXTI_DISABLE_IT\r
+#define __HAL_RTC_ENABLE_IT __HAL_RTC_EXTI_ENABLE_IT\r
+\r
+#if defined (STM32F1)\r
+#define __HAL_RTC_EXTI_CLEAR_FLAG(RTC_EXTI_LINE_ALARM_EVENT) __HAL_RTC_ALARM_EXTI_CLEAR_FLAG()\r
+\r
+#define __HAL_RTC_EXTI_ENABLE_IT(RTC_EXTI_LINE_ALARM_EVENT) __HAL_RTC_ALARM_EXTI_ENABLE_IT()\r
+\r
+#define __HAL_RTC_EXTI_DISABLE_IT(RTC_EXTI_LINE_ALARM_EVENT) __HAL_RTC_ALARM_EXTI_DISABLE_IT()\r
+\r
+#define __HAL_RTC_EXTI_GET_FLAG(RTC_EXTI_LINE_ALARM_EVENT) __HAL_RTC_ALARM_EXTI_GET_FLAG()\r
+\r
+#define __HAL_RTC_EXTI_GENERATE_SWIT(RTC_EXTI_LINE_ALARM_EVENT) __HAL_RTC_ALARM_EXTI_GENERATE_SWIT()\r
+#else\r
+#define __HAL_RTC_EXTI_CLEAR_FLAG(__EXTI_LINE__) (((__EXTI_LINE__) == RTC_EXTI_LINE_ALARM_EVENT) ? __HAL_RTC_ALARM_EXTI_CLEAR_FLAG() : \\r
+ (((__EXTI_LINE__) == RTC_EXTI_LINE_WAKEUPTIMER_EVENT) ? __HAL_RTC_WAKEUPTIMER_EXTI_CLEAR_FLAG() : \\r
+ __HAL_RTC_TAMPER_TIMESTAMP_EXTI_CLEAR_FLAG()))\r
+#define __HAL_RTC_EXTI_ENABLE_IT(__EXTI_LINE__) (((__EXTI_LINE__) == RTC_EXTI_LINE_ALARM_EVENT) ? __HAL_RTC_ALARM_EXTI_ENABLE_IT() : \\r
+ (((__EXTI_LINE__) == RTC_EXTI_LINE_WAKEUPTIMER_EVENT) ? __HAL_RTC_WAKEUPTIMER_EXTI_ENABLE_IT() : \\r
+ __HAL_RTC_TAMPER_TIMESTAMP_EXTI_ENABLE_IT()))\r
+#define __HAL_RTC_EXTI_DISABLE_IT(__EXTI_LINE__) (((__EXTI_LINE__) == RTC_EXTI_LINE_ALARM_EVENT) ? __HAL_RTC_ALARM_EXTI_DISABLE_IT() : \\r
+ (((__EXTI_LINE__) == RTC_EXTI_LINE_WAKEUPTIMER_EVENT) ? __HAL_RTC_WAKEUPTIMER_EXTI_DISABLE_IT() : \\r
+ __HAL_RTC_TAMPER_TIMESTAMP_EXTI_DISABLE_IT()))\r
+#define __HAL_RTC_EXTI_GET_FLAG(__EXTI_LINE__) (((__EXTI_LINE__) == RTC_EXTI_LINE_ALARM_EVENT) ? __HAL_RTC_ALARM_EXTI_GET_FLAG() : \\r
+ (((__EXTI_LINE__) == RTC_EXTI_LINE_WAKEUPTIMER_EVENT) ? __HAL_RTC_WAKEUPTIMER_EXTI_GET_FLAG() : \\r
+ __HAL_RTC_TAMPER_TIMESTAMP_EXTI_GET_FLAG()))\r
+#define __HAL_RTC_EXTI_GENERATE_SWIT(__EXTI_LINE__) (((__EXTI_LINE__) == RTC_EXTI_LINE_ALARM_EVENT) ? __HAL_RTC_ALARM_EXTI_GENERATE_SWIT() : \\r
+ (((__EXTI_LINE__) == RTC_EXTI_LINE_WAKEUPTIMER_EVENT) ? __HAL_RTC_WAKEUPTIMER_EXTI_GENERATE_SWIT() : \\r
+ __HAL_RTC_TAMPER_TIMESTAMP_EXTI_GENERATE_SWIT()))\r
+#endif /* STM32F1 */\r
+\r
+#define IS_ALARM IS_RTC_ALARM\r
+#define IS_ALARM_MASK IS_RTC_ALARM_MASK\r
+#define IS_TAMPER IS_RTC_TAMPER\r
+#define IS_TAMPER_ERASE_MODE IS_RTC_TAMPER_ERASE_MODE\r
+#define IS_TAMPER_FILTER IS_RTC_TAMPER_FILTER\r
+#define IS_TAMPER_INTERRUPT IS_RTC_TAMPER_INTERRUPT\r
+#define IS_TAMPER_MASKFLAG_STATE IS_RTC_TAMPER_MASKFLAG_STATE\r
+#define IS_TAMPER_PRECHARGE_DURATION IS_RTC_TAMPER_PRECHARGE_DURATION\r
+#define IS_TAMPER_PULLUP_STATE IS_RTC_TAMPER_PULLUP_STATE\r
+#define IS_TAMPER_SAMPLING_FREQ IS_RTC_TAMPER_SAMPLING_FREQ\r
+#define IS_TAMPER_TIMESTAMPONTAMPER_DETECTION IS_RTC_TAMPER_TIMESTAMPONTAMPER_DETECTION\r
+#define IS_TAMPER_TRIGGER IS_RTC_TAMPER_TRIGGER\r
+#define IS_WAKEUP_CLOCK IS_RTC_WAKEUP_CLOCK\r
+#define IS_WAKEUP_COUNTER IS_RTC_WAKEUP_COUNTER\r
+\r
+#define __RTC_WRITEPROTECTION_ENABLE __HAL_RTC_WRITEPROTECTION_ENABLE\r
+#define __RTC_WRITEPROTECTION_DISABLE __HAL_RTC_WRITEPROTECTION_DISABLE\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup HAL_SD_Aliased_Macros HAL SD Aliased Macros maintained for legacy purpose\r
+ * @{\r
+ */\r
+\r
+#define SD_OCR_CID_CSD_OVERWRIETE SD_OCR_CID_CSD_OVERWRITE\r
+#define SD_CMD_SD_APP_STAUS SD_CMD_SD_APP_STATUS\r
+\r
+#if defined(STM32F4) || defined(STM32F2)\r
+#define SD_SDMMC_DISABLED SD_SDIO_DISABLED\r
+#define SD_SDMMC_FUNCTION_BUSY SD_SDIO_FUNCTION_BUSY\r
+#define SD_SDMMC_FUNCTION_FAILED SD_SDIO_FUNCTION_FAILED\r
+#define SD_SDMMC_UNKNOWN_FUNCTION SD_SDIO_UNKNOWN_FUNCTION\r
+#define SD_CMD_SDMMC_SEN_OP_COND SD_CMD_SDIO_SEN_OP_COND\r
+#define SD_CMD_SDMMC_RW_DIRECT SD_CMD_SDIO_RW_DIRECT\r
+#define SD_CMD_SDMMC_RW_EXTENDED SD_CMD_SDIO_RW_EXTENDED\r
+#define __HAL_SD_SDMMC_ENABLE __HAL_SD_SDIO_ENABLE\r
+#define __HAL_SD_SDMMC_DISABLE __HAL_SD_SDIO_DISABLE\r
+#define __HAL_SD_SDMMC_DMA_ENABLE __HAL_SD_SDIO_DMA_ENABLE\r
+#define __HAL_SD_SDMMC_DMA_DISABLE __HAL_SD_SDIO_DMA_DISABL\r
+#define __HAL_SD_SDMMC_ENABLE_IT __HAL_SD_SDIO_ENABLE_IT\r
+#define __HAL_SD_SDMMC_DISABLE_IT __HAL_SD_SDIO_DISABLE_IT\r
+#define __HAL_SD_SDMMC_GET_FLAG __HAL_SD_SDIO_GET_FLAG\r
+#define __HAL_SD_SDMMC_CLEAR_FLAG __HAL_SD_SDIO_CLEAR_FLAG\r
+#define __HAL_SD_SDMMC_GET_IT __HAL_SD_SDIO_GET_IT\r
+#define __HAL_SD_SDMMC_CLEAR_IT __HAL_SD_SDIO_CLEAR_IT\r
+#define SDMMC_STATIC_FLAGS SDIO_STATIC_FLAGS\r
+#define SDMMC_CMD0TIMEOUT SDIO_CMD0TIMEOUT\r
+#define SD_SDMMC_SEND_IF_COND SD_SDIO_SEND_IF_COND\r
+/* alias CMSIS */\r
+#define SDMMC1_IRQn SDIO_IRQn\r
+#define SDMMC1_IRQHandler SDIO_IRQHandler\r
+#endif\r
+\r
+#if defined(STM32F7) || defined(STM32L4)\r
+#define SD_SDIO_DISABLED SD_SDMMC_DISABLED\r
+#define SD_SDIO_FUNCTION_BUSY SD_SDMMC_FUNCTION_BUSY\r
+#define SD_SDIO_FUNCTION_FAILED SD_SDMMC_FUNCTION_FAILED\r
+#define SD_SDIO_UNKNOWN_FUNCTION SD_SDMMC_UNKNOWN_FUNCTION\r
+#define SD_CMD_SDIO_SEN_OP_COND SD_CMD_SDMMC_SEN_OP_COND\r
+#define SD_CMD_SDIO_RW_DIRECT SD_CMD_SDMMC_RW_DIRECT\r
+#define SD_CMD_SDIO_RW_EXTENDED SD_CMD_SDMMC_RW_EXTENDED\r
+#define __HAL_SD_SDIO_ENABLE __HAL_SD_SDMMC_ENABLE\r
+#define __HAL_SD_SDIO_DISABLE __HAL_SD_SDMMC_DISABLE\r
+#define __HAL_SD_SDIO_DMA_ENABLE __HAL_SD_SDMMC_DMA_ENABLE\r
+#define __HAL_SD_SDIO_DMA_DISABL __HAL_SD_SDMMC_DMA_DISABLE\r
+#define __HAL_SD_SDIO_ENABLE_IT __HAL_SD_SDMMC_ENABLE_IT\r
+#define __HAL_SD_SDIO_DISABLE_IT __HAL_SD_SDMMC_DISABLE_IT\r
+#define __HAL_SD_SDIO_GET_FLAG __HAL_SD_SDMMC_GET_FLAG\r
+#define __HAL_SD_SDIO_CLEAR_FLAG __HAL_SD_SDMMC_CLEAR_FLAG\r
+#define __HAL_SD_SDIO_GET_IT __HAL_SD_SDMMC_GET_IT\r
+#define __HAL_SD_SDIO_CLEAR_IT __HAL_SD_SDMMC_CLEAR_IT\r
+#define SDIO_STATIC_FLAGS SDMMC_STATIC_FLAGS\r
+#define SDIO_CMD0TIMEOUT SDMMC_CMD0TIMEOUT\r
+#define SD_SDIO_SEND_IF_COND SD_SDMMC_SEND_IF_COND\r
+/* alias CMSIS for compatibilities */\r
+#define SDIO_IRQn SDMMC1_IRQn\r
+#define SDIO_IRQHandler SDMMC1_IRQHandler\r
+#endif\r
+\r
+#if defined(STM32F7) || defined(STM32F4) || defined(STM32F2) || defined(STM32L4)\r
+#define HAL_SD_CardCIDTypedef HAL_SD_CardCIDTypeDef\r
+#define HAL_SD_CardCSDTypedef HAL_SD_CardCSDTypeDef\r
+#define HAL_SD_CardStatusTypedef HAL_SD_CardStatusTypeDef\r
+#define HAL_SD_CardStateTypedef HAL_SD_CardStateTypeDef\r
+#endif\r
+\r
+#if defined(STM32H7)\r
+#define HAL_MMCEx_Read_DMADoubleBuffer0CpltCallback HAL_MMCEx_Read_DMADoubleBuf0CpltCallback\r
+#define HAL_MMCEx_Read_DMADoubleBuffer1CpltCallback HAL_MMCEx_Read_DMADoubleBuf1CpltCallback\r
+#define HAL_MMCEx_Write_DMADoubleBuffer0CpltCallback HAL_MMCEx_Write_DMADoubleBuf0CpltCallback\r
+#define HAL_MMCEx_Write_DMADoubleBuffer1CpltCallback HAL_MMCEx_Write_DMADoubleBuf1CpltCallback\r
+#define HAL_SDEx_Read_DMADoubleBuffer0CpltCallback HAL_SDEx_Read_DMADoubleBuf0CpltCallback\r
+#define HAL_SDEx_Read_DMADoubleBuffer1CpltCallback HAL_SDEx_Read_DMADoubleBuf1CpltCallback\r
+#define HAL_SDEx_Write_DMADoubleBuffer0CpltCallback HAL_SDEx_Write_DMADoubleBuf0CpltCallback\r
+#define HAL_SDEx_Write_DMADoubleBuffer1CpltCallback HAL_SDEx_Write_DMADoubleBuf1CpltCallback\r
+#define HAL_SD_DriveTransciver_1_8V_Callback HAL_SD_DriveTransceiver_1_8V_Callback\r
+#endif\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup HAL_SMARTCARD_Aliased_Macros HAL SMARTCARD Aliased Macros maintained for legacy purpose\r
+ * @{\r
+ */\r
+\r
+#define __SMARTCARD_ENABLE_IT __HAL_SMARTCARD_ENABLE_IT\r
+#define __SMARTCARD_DISABLE_IT __HAL_SMARTCARD_DISABLE_IT\r
+#define __SMARTCARD_ENABLE __HAL_SMARTCARD_ENABLE\r
+#define __SMARTCARD_DISABLE __HAL_SMARTCARD_DISABLE\r
+#define __SMARTCARD_DMA_REQUEST_ENABLE __HAL_SMARTCARD_DMA_REQUEST_ENABLE\r
+#define __SMARTCARD_DMA_REQUEST_DISABLE __HAL_SMARTCARD_DMA_REQUEST_DISABLE\r
+\r
+#define __HAL_SMARTCARD_GETCLOCKSOURCE SMARTCARD_GETCLOCKSOURCE\r
+#define __SMARTCARD_GETCLOCKSOURCE SMARTCARD_GETCLOCKSOURCE\r
+\r
+#define IS_SMARTCARD_ONEBIT_SAMPLING IS_SMARTCARD_ONE_BIT_SAMPLE\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup HAL_SMBUS_Aliased_Macros HAL SMBUS Aliased Macros maintained for legacy purpose\r
+ * @{\r
+ */\r
+#define __HAL_SMBUS_RESET_CR1 SMBUS_RESET_CR1\r
+#define __HAL_SMBUS_RESET_CR2 SMBUS_RESET_CR2\r
+#define __HAL_SMBUS_GENERATE_START SMBUS_GENERATE_START\r
+#define __HAL_SMBUS_GET_ADDR_MATCH SMBUS_GET_ADDR_MATCH\r
+#define __HAL_SMBUS_GET_DIR SMBUS_GET_DIR\r
+#define __HAL_SMBUS_GET_STOP_MODE SMBUS_GET_STOP_MODE\r
+#define __HAL_SMBUS_GET_PEC_MODE SMBUS_GET_PEC_MODE\r
+#define __HAL_SMBUS_GET_ALERT_ENABLED SMBUS_GET_ALERT_ENABLED\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup HAL_SPI_Aliased_Macros HAL SPI Aliased Macros maintained for legacy purpose\r
+ * @{\r
+ */\r
+\r
+#define __HAL_SPI_1LINE_TX SPI_1LINE_TX\r
+#define __HAL_SPI_1LINE_RX SPI_1LINE_RX\r
+#define __HAL_SPI_RESET_CRC SPI_RESET_CRC\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup HAL_UART_Aliased_Macros HAL UART Aliased Macros maintained for legacy purpose\r
+ * @{\r
+ */\r
+\r
+#define __HAL_UART_GETCLOCKSOURCE UART_GETCLOCKSOURCE\r
+#define __HAL_UART_MASK_COMPUTATION UART_MASK_COMPUTATION\r
+#define __UART_GETCLOCKSOURCE UART_GETCLOCKSOURCE\r
+#define __UART_MASK_COMPUTATION UART_MASK_COMPUTATION\r
+\r
+#define IS_UART_WAKEUPMETHODE IS_UART_WAKEUPMETHOD\r
+\r
+#define IS_UART_ONEBIT_SAMPLE IS_UART_ONE_BIT_SAMPLE\r
+#define IS_UART_ONEBIT_SAMPLING IS_UART_ONE_BIT_SAMPLE\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+\r
+/** @defgroup HAL_USART_Aliased_Macros HAL USART Aliased Macros maintained for legacy purpose\r
+ * @{\r
+ */\r
+\r
+#define __USART_ENABLE_IT __HAL_USART_ENABLE_IT\r
+#define __USART_DISABLE_IT __HAL_USART_DISABLE_IT\r
+#define __USART_ENABLE __HAL_USART_ENABLE\r
+#define __USART_DISABLE __HAL_USART_DISABLE\r
+\r
+#define __HAL_USART_GETCLOCKSOURCE USART_GETCLOCKSOURCE\r
+#define __USART_GETCLOCKSOURCE USART_GETCLOCKSOURCE\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup HAL_USB_Aliased_Macros HAL USB Aliased Macros maintained for legacy purpose\r
+ * @{\r
+ */\r
+#define USB_EXTI_LINE_WAKEUP USB_WAKEUP_EXTI_LINE\r
+\r
+#define USB_FS_EXTI_TRIGGER_RISING_EDGE USB_OTG_FS_WAKEUP_EXTI_RISING_EDGE\r
+#define USB_FS_EXTI_TRIGGER_FALLING_EDGE USB_OTG_FS_WAKEUP_EXTI_FALLING_EDGE\r
+#define USB_FS_EXTI_TRIGGER_BOTH_EDGE USB_OTG_FS_WAKEUP_EXTI_RISING_FALLING_EDGE\r
+#define USB_FS_EXTI_LINE_WAKEUP USB_OTG_FS_WAKEUP_EXTI_LINE\r
+\r
+#define USB_HS_EXTI_TRIGGER_RISING_EDGE USB_OTG_HS_WAKEUP_EXTI_RISING_EDGE\r
+#define USB_HS_EXTI_TRIGGER_FALLING_EDGE USB_OTG_HS_WAKEUP_EXTI_FALLING_EDGE\r
+#define USB_HS_EXTI_TRIGGER_BOTH_EDGE USB_OTG_HS_WAKEUP_EXTI_RISING_FALLING_EDGE\r
+#define USB_HS_EXTI_LINE_WAKEUP USB_OTG_HS_WAKEUP_EXTI_LINE\r
+\r
+#define __HAL_USB_EXTI_ENABLE_IT __HAL_USB_WAKEUP_EXTI_ENABLE_IT\r
+#define __HAL_USB_EXTI_DISABLE_IT __HAL_USB_WAKEUP_EXTI_DISABLE_IT\r
+#define __HAL_USB_EXTI_GET_FLAG __HAL_USB_WAKEUP_EXTI_GET_FLAG\r
+#define __HAL_USB_EXTI_CLEAR_FLAG __HAL_USB_WAKEUP_EXTI_CLEAR_FLAG\r
+#define __HAL_USB_EXTI_SET_RISING_EDGE_TRIGGER __HAL_USB_WAKEUP_EXTI_ENABLE_RISING_EDGE\r
+#define __HAL_USB_EXTI_SET_FALLING_EDGE_TRIGGER __HAL_USB_WAKEUP_EXTI_ENABLE_FALLING_EDGE\r
+#define __HAL_USB_EXTI_SET_FALLINGRISING_TRIGGER __HAL_USB_WAKEUP_EXTI_ENABLE_RISING_FALLING_EDGE\r
+\r
+#define __HAL_USB_FS_EXTI_ENABLE_IT __HAL_USB_OTG_FS_WAKEUP_EXTI_ENABLE_IT\r
+#define __HAL_USB_FS_EXTI_DISABLE_IT __HAL_USB_OTG_FS_WAKEUP_EXTI_DISABLE_IT\r
+#define __HAL_USB_FS_EXTI_GET_FLAG __HAL_USB_OTG_FS_WAKEUP_EXTI_GET_FLAG\r
+#define __HAL_USB_FS_EXTI_CLEAR_FLAG __HAL_USB_OTG_FS_WAKEUP_EXTI_CLEAR_FLAG\r
+#define __HAL_USB_FS_EXTI_SET_RISING_EGDE_TRIGGER __HAL_USB_OTG_FS_WAKEUP_EXTI_ENABLE_RISING_EDGE\r
+#define __HAL_USB_FS_EXTI_SET_FALLING_EGDE_TRIGGER __HAL_USB_OTG_FS_WAKEUP_EXTI_ENABLE_FALLING_EDGE\r
+#define __HAL_USB_FS_EXTI_SET_FALLINGRISING_TRIGGER __HAL_USB_OTG_FS_WAKEUP_EXTI_ENABLE_RISING_FALLING_EDGE\r
+#define __HAL_USB_FS_EXTI_GENERATE_SWIT __HAL_USB_OTG_FS_WAKEUP_EXTI_GENERATE_SWIT\r
+\r
+#define __HAL_USB_HS_EXTI_ENABLE_IT __HAL_USB_OTG_HS_WAKEUP_EXTI_ENABLE_IT\r
+#define __HAL_USB_HS_EXTI_DISABLE_IT __HAL_USB_OTG_HS_WAKEUP_EXTI_DISABLE_IT\r
+#define __HAL_USB_HS_EXTI_GET_FLAG __HAL_USB_OTG_HS_WAKEUP_EXTI_GET_FLAG\r
+#define __HAL_USB_HS_EXTI_CLEAR_FLAG __HAL_USB_OTG_HS_WAKEUP_EXTI_CLEAR_FLAG\r
+#define __HAL_USB_HS_EXTI_SET_RISING_EGDE_TRIGGER __HAL_USB_OTG_HS_WAKEUP_EXTI_ENABLE_RISING_EDGE\r
+#define __HAL_USB_HS_EXTI_SET_FALLING_EGDE_TRIGGER __HAL_USB_OTG_HS_WAKEUP_EXTI_ENABLE_FALLING_EDGE\r
+#define __HAL_USB_HS_EXTI_SET_FALLINGRISING_TRIGGER __HAL_USB_OTG_HS_WAKEUP_EXTI_ENABLE_RISING_FALLING_EDGE\r
+#define __HAL_USB_HS_EXTI_GENERATE_SWIT __HAL_USB_OTG_HS_WAKEUP_EXTI_GENERATE_SWIT\r
+\r
+#define HAL_PCD_ActiveRemoteWakeup HAL_PCD_ActivateRemoteWakeup\r
+#define HAL_PCD_DeActiveRemoteWakeup HAL_PCD_DeActivateRemoteWakeup\r
+\r
+#define HAL_PCD_SetTxFiFo HAL_PCDEx_SetTxFiFo\r
+#define HAL_PCD_SetRxFiFo HAL_PCDEx_SetRxFiFo\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup HAL_TIM_Aliased_Macros HAL TIM Aliased Macros maintained for legacy purpose\r
+ * @{\r
+ */\r
+#define __HAL_TIM_SetICPrescalerValue TIM_SET_ICPRESCALERVALUE\r
+#define __HAL_TIM_ResetICPrescalerValue TIM_RESET_ICPRESCALERVALUE\r
+\r
+#define TIM_GET_ITSTATUS __HAL_TIM_GET_IT_SOURCE\r
+#define TIM_GET_CLEAR_IT __HAL_TIM_CLEAR_IT\r
+\r
+#define __HAL_TIM_GET_ITSTATUS __HAL_TIM_GET_IT_SOURCE\r
+\r
+#define __HAL_TIM_DIRECTION_STATUS __HAL_TIM_IS_TIM_COUNTING_DOWN\r
+#define __HAL_TIM_PRESCALER __HAL_TIM_SET_PRESCALER\r
+#define __HAL_TIM_SetCounter __HAL_TIM_SET_COUNTER\r
+#define __HAL_TIM_GetCounter __HAL_TIM_GET_COUNTER\r
+#define __HAL_TIM_SetAutoreload __HAL_TIM_SET_AUTORELOAD\r
+#define __HAL_TIM_GetAutoreload __HAL_TIM_GET_AUTORELOAD\r
+#define __HAL_TIM_SetClockDivision __HAL_TIM_SET_CLOCKDIVISION\r
+#define __HAL_TIM_GetClockDivision __HAL_TIM_GET_CLOCKDIVISION\r
+#define __HAL_TIM_SetICPrescaler __HAL_TIM_SET_ICPRESCALER\r
+#define __HAL_TIM_GetICPrescaler __HAL_TIM_GET_ICPRESCALER\r
+#define __HAL_TIM_SetCompare __HAL_TIM_SET_COMPARE\r
+#define __HAL_TIM_GetCompare __HAL_TIM_GET_COMPARE\r
+\r
+#define TIM_BREAKINPUTSOURCE_DFSDM TIM_BREAKINPUTSOURCE_DFSDM1\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup HAL_ETH_Aliased_Macros HAL ETH Aliased Macros maintained for legacy purpose\r
+ * @{\r
+ */\r
+\r
+#define __HAL_ETH_EXTI_ENABLE_IT __HAL_ETH_WAKEUP_EXTI_ENABLE_IT\r
+#define __HAL_ETH_EXTI_DISABLE_IT __HAL_ETH_WAKEUP_EXTI_DISABLE_IT\r
+#define __HAL_ETH_EXTI_GET_FLAG __HAL_ETH_WAKEUP_EXTI_GET_FLAG\r
+#define __HAL_ETH_EXTI_CLEAR_FLAG __HAL_ETH_WAKEUP_EXTI_CLEAR_FLAG\r
+#define __HAL_ETH_EXTI_SET_RISING_EGDE_TRIGGER __HAL_ETH_WAKEUP_EXTI_ENABLE_RISING_EDGE_TRIGGER\r
+#define __HAL_ETH_EXTI_SET_FALLING_EGDE_TRIGGER __HAL_ETH_WAKEUP_EXTI_ENABLE_FALLING_EDGE_TRIGGER\r
+#define __HAL_ETH_EXTI_SET_FALLINGRISING_TRIGGER __HAL_ETH_WAKEUP_EXTI_ENABLE_FALLINGRISING_TRIGGER\r
+\r
+#define ETH_PROMISCIOUSMODE_ENABLE ETH_PROMISCUOUS_MODE_ENABLE\r
+#define ETH_PROMISCIOUSMODE_DISABLE ETH_PROMISCUOUS_MODE_DISABLE\r
+#define IS_ETH_PROMISCIOUS_MODE IS_ETH_PROMISCUOUS_MODE\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup HAL_LTDC_Aliased_Macros HAL LTDC Aliased Macros maintained for legacy purpose\r
+ * @{\r
+ */\r
+#define __HAL_LTDC_LAYER LTDC_LAYER\r
+#define __HAL_LTDC_RELOAD_CONFIG __HAL_LTDC_RELOAD_IMMEDIATE_CONFIG\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup HAL_SAI_Aliased_Macros HAL SAI Aliased Macros maintained for legacy purpose\r
+ * @{\r
+ */\r
+#define SAI_OUTPUTDRIVE_DISABLED SAI_OUTPUTDRIVE_DISABLE\r
+#define SAI_OUTPUTDRIVE_ENABLED SAI_OUTPUTDRIVE_ENABLE\r
+#define SAI_MASTERDIVIDER_ENABLED SAI_MASTERDIVIDER_ENABLE\r
+#define SAI_MASTERDIVIDER_DISABLED SAI_MASTERDIVIDER_DISABLE\r
+#define SAI_STREOMODE SAI_STEREOMODE\r
+#define SAI_FIFOStatus_Empty SAI_FIFOSTATUS_EMPTY\r
+#define SAI_FIFOStatus_Less1QuarterFull SAI_FIFOSTATUS_LESS1QUARTERFULL\r
+#define SAI_FIFOStatus_1QuarterFull SAI_FIFOSTATUS_1QUARTERFULL\r
+#define SAI_FIFOStatus_HalfFull SAI_FIFOSTATUS_HALFFULL\r
+#define SAI_FIFOStatus_3QuartersFull SAI_FIFOSTATUS_3QUARTERFULL\r
+#define SAI_FIFOStatus_Full SAI_FIFOSTATUS_FULL\r
+#define IS_SAI_BLOCK_MONO_STREO_MODE IS_SAI_BLOCK_MONO_STEREO_MODE\r
+#define SAI_SYNCHRONOUS_EXT SAI_SYNCHRONOUS_EXT_SAI1\r
+#define SAI_SYNCEXT_IN_ENABLE SAI_SYNCEXT_OUTBLOCKA_ENABLE\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup HAL_SPDIFRX_Aliased_Macros HAL SPDIFRX Aliased Macros maintained for legacy purpose\r
+ * @{\r
+ */\r
+#if defined(STM32H7)\r
+#define HAL_SPDIFRX_ReceiveControlFlow HAL_SPDIFRX_ReceiveCtrlFlow\r
+#define HAL_SPDIFRX_ReceiveControlFlow_IT HAL_SPDIFRX_ReceiveCtrlFlow_IT\r
+#define HAL_SPDIFRX_ReceiveControlFlow_DMA HAL_SPDIFRX_ReceiveCtrlFlow_DMA\r
+#endif\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup HAL_HRTIM_Aliased_Functions HAL HRTIM Aliased Functions maintained for legacy purpose\r
+ * @{\r
+ */\r
+#if defined (STM32H7) || defined (STM32F3)\r
+#define HAL_HRTIM_WaveformCounterStart_IT HAL_HRTIM_WaveformCountStart_IT\r
+#define HAL_HRTIM_WaveformCounterStart_DMA HAL_HRTIM_WaveformCountStart_DMA\r
+#define HAL_HRTIM_WaveformCounterStart HAL_HRTIM_WaveformCountStart\r
+#define HAL_HRTIM_WaveformCounterStop_IT HAL_HRTIM_WaveformCountStop_IT\r
+#define HAL_HRTIM_WaveformCounterStop_DMA HAL_HRTIM_WaveformCountStop_DMA\r
+#define HAL_HRTIM_WaveformCounterStop HAL_HRTIM_WaveformCountStop\r
+#endif\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup HAL_QSPI_Aliased_Macros HAL QSPI Aliased Macros maintained for legacy purpose\r
+ * @{\r
+ */\r
+#if defined (STM32L4)\r
+#define HAL_QPSI_TIMEOUT_DEFAULT_VALUE HAL_QSPI_TIMEOUT_DEFAULT_VALUE\r
+#endif\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup HAL_PPP_Aliased_Macros HAL PPP Aliased Macros maintained for legacy purpose\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+#ifdef __cplusplus\r
+}\r
+#endif\r
+\r
+#endif /* STM32_HAL_LEGACY */\r
+\r
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\r
+\r
--- /dev/null
+/**\r
+ ******************************************************************************\r
+ * @file stm32l1xx_hal.h\r
+ * @author MCD Application Team\r
+ * @brief This file contains all the functions prototypes for the HAL\r
+ * module driver.\r
+ ******************************************************************************\r
+ * @attention\r
+ *\r
+ * <h2><center>© Copyright (c) 2017 STMicroelectronics.\r
+ * All rights reserved.</center></h2>\r
+ *\r
+ * This software component is licensed by ST under BSD 3-Clause license,\r
+ * the "License"; You may not use this file except in compliance with the\r
+ * License. You may obtain a copy of the License at:\r
+ * opensource.org/licenses/BSD-3-Clause\r
+ *\r
+ ******************************************************************************\r
+ */\r
+\r
+/* Define to prevent recursive inclusion -------------------------------------*/\r
+#ifndef __STM32L1xx_HAL_H\r
+#define __STM32L1xx_HAL_H\r
+\r
+#ifdef __cplusplus\r
+ extern "C" {\r
+#endif\r
+\r
+/* Includes ------------------------------------------------------------------*/\r
+#include "stm32l1xx_hal_conf.h"\r
+\r
+/** @addtogroup STM32L1xx_HAL_Driver\r
+ * @{\r
+ */\r
+\r
+/** @addtogroup HAL\r
+ * @{\r
+ */\r
+\r
+/* Exported types ------------------------------------------------------------*/\r
+/* Exported constants --------------------------------------------------------*/\r
+\r
+/** @defgroup HAL_Exported_Constants HAL Exported Constants\r
+ * @{\r
+ */\r
+\r
+/** @defgroup HAL_TICK_FREQ Tick Frequency\r
+ * @{\r
+ */\r
+#define HAL_TICK_FREQ_10HZ 100U\r
+#define HAL_TICK_FREQ_100HZ 10U\r
+#define HAL_TICK_FREQ_1KHZ 1U\r
+#define HAL_TICK_FREQ_DEFAULT HAL_TICK_FREQ_1KHZ\r
+\r
+#define IS_TICKFREQ(__FREQ__) (((__FREQ__) == HAL_TICK_FREQ_10HZ) || \\r
+ ((__FREQ__) == HAL_TICK_FREQ_100HZ) || \\r
+ ((__FREQ__) == HAL_TICK_FREQ_1KHZ))\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup SYSCFG_Exported_Constants SYSCFG Exported Constants\r
+ * @{\r
+ */\r
+\r
+/** @defgroup SYSCFG_Constants SYSCFG: SYStem ConFiG\r
+ * @{\r
+ */\r
+\r
+/** @defgroup SYSCFG_BootMode Boot Mode\r
+ * @{\r
+ */\r
+\r
+#define SYSCFG_BOOT_MAINFLASH (0x00000000U)\r
+#define SYSCFG_BOOT_SYSTEMFLASH ((uint32_t)SYSCFG_MEMRMP_BOOT_MODE_0)\r
+#if defined(FSMC_R_BASE)\r
+#define SYSCFG_BOOT_FSMC ((uint32_t)SYSCFG_MEMRMP_BOOT_MODE_1)\r
+#endif /* FSMC_R_BASE */\r
+#define SYSCFG_BOOT_SRAM ((uint32_t)SYSCFG_MEMRMP_BOOT_MODE)\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup RI_Constants RI: Routing Interface\r
+ * @{\r
+ */\r
+\r
+/** @defgroup RI_InputCapture Input Capture\r
+ * @{\r
+ */\r
+\r
+#define RI_INPUTCAPTURE_IC1 RI_ICR_IC1 /*!< Input Capture 1 */\r
+#define RI_INPUTCAPTURE_IC2 RI_ICR_IC2 /*!< Input Capture 2 */\r
+#define RI_INPUTCAPTURE_IC3 RI_ICR_IC3 /*!< Input Capture 3 */\r
+#define RI_INPUTCAPTURE_IC4 RI_ICR_IC4 /*!< Input Capture 4 */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup TIM_Select TIM Select\r
+ * @{\r
+ */\r
+\r
+#define TIM_SELECT_NONE (0x00000000U) /*!< None selected */\r
+#define TIM_SELECT_TIM2 ((uint32_t)RI_ICR_TIM_0) /*!< Timer 2 selected */\r
+#define TIM_SELECT_TIM3 ((uint32_t)RI_ICR_TIM_1) /*!< Timer 3 selected */\r
+#define TIM_SELECT_TIM4 ((uint32_t)RI_ICR_TIM) /*!< Timer 4 selected */\r
+\r
+#define IS_RI_TIM(__TIM__) (((__TIM__) == TIM_SELECT_NONE) || \\r
+ ((__TIM__) == TIM_SELECT_TIM2) || \\r
+ ((__TIM__) == TIM_SELECT_TIM3) || \\r
+ ((__TIM__) == TIM_SELECT_TIM4))\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup RI_InputCaptureRouting Input Capture Routing\r
+ * @{\r
+ */\r
+ /* TIMx_IC1 TIMx_IC2 TIMx_IC3 TIMx_IC4 */\r
+#define RI_INPUTCAPTUREROUTING_0 (0x00000000U) /* PA0 PA1 PA2 PA3 */\r
+#define RI_INPUTCAPTUREROUTING_1 (0x00000001U) /* PA4 PA5 PA6 PA7 */\r
+#define RI_INPUTCAPTUREROUTING_2 (0x00000002U) /* PA8 PA9 PA10 PA11 */\r
+#define RI_INPUTCAPTUREROUTING_3 (0x00000003U) /* PA12 PA13 PA14 PA15 */\r
+#define RI_INPUTCAPTUREROUTING_4 (0x00000004U) /* PC0 PC1 PC2 PC3 */\r
+#define RI_INPUTCAPTUREROUTING_5 (0x00000005U) /* PC4 PC5 PC6 PC7 */\r
+#define RI_INPUTCAPTUREROUTING_6 (0x00000006U) /* PC8 PC9 PC10 PC11 */\r
+#define RI_INPUTCAPTUREROUTING_7 (0x00000007U) /* PC12 PC13 PC14 PC15 */\r
+#define RI_INPUTCAPTUREROUTING_8 (0x00000008U) /* PD0 PD1 PD2 PD3 */\r
+#define RI_INPUTCAPTUREROUTING_9 (0x00000009U) /* PD4 PD5 PD6 PD7 */\r
+#define RI_INPUTCAPTUREROUTING_10 (0x0000000AU) /* PD8 PD9 PD10 PD11 */\r
+#define RI_INPUTCAPTUREROUTING_11 (0x0000000BU) /* PD12 PD13 PD14 PD15 */\r
+#define RI_INPUTCAPTUREROUTING_12 (0x0000000CU) /* PE0 PE1 PE2 PE3 */\r
+#define RI_INPUTCAPTUREROUTING_13 (0x0000000DU) /* PE4 PE5 PE6 PE7 */\r
+#define RI_INPUTCAPTUREROUTING_14 (0x0000000EU) /* PE8 PE9 PE10 PE11 */\r
+#define RI_INPUTCAPTUREROUTING_15 (0x0000000FU) /* PE12 PE13 PE14 PE15 */\r
+\r
+#define IS_RI_INPUTCAPTURE_ROUTING(__ROUTING__) (((__ROUTING__) == RI_INPUTCAPTUREROUTING_0) || \\r
+ ((__ROUTING__) == RI_INPUTCAPTUREROUTING_1) || \\r
+ ((__ROUTING__) == RI_INPUTCAPTUREROUTING_2) || \\r
+ ((__ROUTING__) == RI_INPUTCAPTUREROUTING_3) || \\r
+ ((__ROUTING__) == RI_INPUTCAPTUREROUTING_4) || \\r
+ ((__ROUTING__) == RI_INPUTCAPTUREROUTING_5) || \\r
+ ((__ROUTING__) == RI_INPUTCAPTUREROUTING_6) || \\r
+ ((__ROUTING__) == RI_INPUTCAPTUREROUTING_7) || \\r
+ ((__ROUTING__) == RI_INPUTCAPTUREROUTING_8) || \\r
+ ((__ROUTING__) == RI_INPUTCAPTUREROUTING_9) || \\r
+ ((__ROUTING__) == RI_INPUTCAPTUREROUTING_10) || \\r
+ ((__ROUTING__) == RI_INPUTCAPTUREROUTING_11) || \\r
+ ((__ROUTING__) == RI_INPUTCAPTUREROUTING_12) || \\r
+ ((__ROUTING__) == RI_INPUTCAPTUREROUTING_13) || \\r
+ ((__ROUTING__) == RI_INPUTCAPTUREROUTING_14) || \\r
+ ((__ROUTING__) == RI_INPUTCAPTUREROUTING_15))\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup RI_IOSwitch IO Switch\r
+ * @{\r
+ */\r
+#define RI_ASCR1_REGISTER (0x80000000U)\r
+/* ASCR1 I/O switch: bit 31 is set to '1' to indicate that the mask is in ASCR1 register */\r
+#define RI_IOSWITCH_CH0 ((uint32_t)RI_ASCR1_REGISTER | RI_ASCR1_CH_0)\r
+#define RI_IOSWITCH_CH1 ((uint32_t)RI_ASCR1_REGISTER | RI_ASCR1_CH_1)\r
+#define RI_IOSWITCH_CH2 ((uint32_t)RI_ASCR1_REGISTER | RI_ASCR1_CH_2)\r
+#define RI_IOSWITCH_CH3 ((uint32_t)RI_ASCR1_REGISTER | RI_ASCR1_CH_3)\r
+#define RI_IOSWITCH_CH4 ((uint32_t)RI_ASCR1_REGISTER | RI_ASCR1_CH_4)\r
+#define RI_IOSWITCH_CH5 ((uint32_t)RI_ASCR1_REGISTER | RI_ASCR1_CH_5)\r
+#define RI_IOSWITCH_CH6 ((uint32_t)RI_ASCR1_REGISTER | RI_ASCR1_CH_6)\r
+#define RI_IOSWITCH_CH7 ((uint32_t)RI_ASCR1_REGISTER | RI_ASCR1_CH_7)\r
+#define RI_IOSWITCH_CH8 ((uint32_t)RI_ASCR1_REGISTER | RI_ASCR1_CH_8)\r
+#define RI_IOSWITCH_CH9 ((uint32_t)RI_ASCR1_REGISTER | RI_ASCR1_CH_9)\r
+#define RI_IOSWITCH_CH10 ((uint32_t)RI_ASCR1_REGISTER | RI_ASCR1_CH_10)\r
+#define RI_IOSWITCH_CH11 ((uint32_t)RI_ASCR1_REGISTER | RI_ASCR1_CH_11)\r
+#define RI_IOSWITCH_CH12 ((uint32_t)RI_ASCR1_REGISTER | RI_ASCR1_CH_12)\r
+#define RI_IOSWITCH_CH13 ((uint32_t)RI_ASCR1_REGISTER | RI_ASCR1_CH_13)\r
+#define RI_IOSWITCH_CH14 ((uint32_t)RI_ASCR1_REGISTER | RI_ASCR1_CH_14)\r
+#define RI_IOSWITCH_CH15 ((uint32_t)RI_ASCR1_REGISTER | RI_ASCR1_CH_15)\r
+#define RI_IOSWITCH_CH18 ((uint32_t)RI_ASCR1_REGISTER | RI_ASCR1_CH_18)\r
+#define RI_IOSWITCH_CH19 ((uint32_t)RI_ASCR1_REGISTER | RI_ASCR1_CH_19)\r
+#define RI_IOSWITCH_CH20 ((uint32_t)RI_ASCR1_REGISTER | RI_ASCR1_CH_20)\r
+#define RI_IOSWITCH_CH21 ((uint32_t)RI_ASCR1_REGISTER | RI_ASCR1_CH_21)\r
+#define RI_IOSWITCH_CH22 ((uint32_t)RI_ASCR1_REGISTER | RI_ASCR1_CH_22)\r
+#define RI_IOSWITCH_CH23 ((uint32_t)RI_ASCR1_REGISTER | RI_ASCR1_CH_23)\r
+#define RI_IOSWITCH_CH24 ((uint32_t)RI_ASCR1_REGISTER | RI_ASCR1_CH_24)\r
+#define RI_IOSWITCH_CH25 ((uint32_t)RI_ASCR1_REGISTER | RI_ASCR1_CH_25)\r
+#define RI_IOSWITCH_VCOMP ((uint32_t)RI_ASCR1_REGISTER | RI_ASCR1_VCOMP) /* VCOMP (ADC channel 26) is an internal switch used to connect selected channel to COMP1 non inverting input */\r
+#if defined (RI_ASCR2_CH1b) /* STM32L1 devices category Cat.4 and Cat.5 */\r
+#define RI_IOSWITCH_CH27 ((uint32_t)RI_ASCR1_REGISTER | RI_ASCR1_CH_27)\r
+#define RI_IOSWITCH_CH28 ((uint32_t)RI_ASCR1_REGISTER | RI_ASCR1_CH_28)\r
+#define RI_IOSWITCH_CH29 ((uint32_t)RI_ASCR1_REGISTER | RI_ASCR1_CH_29)\r
+#define RI_IOSWITCH_CH30 ((uint32_t)RI_ASCR1_REGISTER | RI_ASCR1_CH_30)\r
+#define RI_IOSWITCH_CH31 ((uint32_t)RI_ASCR1_REGISTER | RI_ASCR1_CH_31)\r
+#endif /* RI_ASCR2_CH1b */\r
+\r
+/* ASCR2 IO switch: bit 31 is set to '0' to indicate that the mask is in ASCR2 register */\r
+#define RI_IOSWITCH_GR10_1 ((uint32_t)RI_ASCR2_GR10_1)\r
+#define RI_IOSWITCH_GR10_2 ((uint32_t)RI_ASCR2_GR10_2)\r
+#define RI_IOSWITCH_GR10_3 ((uint32_t)RI_ASCR2_GR10_3)\r
+#define RI_IOSWITCH_GR10_4 ((uint32_t)RI_ASCR2_GR10_4)\r
+#define RI_IOSWITCH_GR6_1 ((uint32_t)RI_ASCR2_GR6_1)\r
+#define RI_IOSWITCH_GR6_2 ((uint32_t)RI_ASCR2_GR6_2)\r
+#define RI_IOSWITCH_GR5_1 ((uint32_t)RI_ASCR2_GR5_1)\r
+#define RI_IOSWITCH_GR5_2 ((uint32_t)RI_ASCR2_GR5_2)\r
+#define RI_IOSWITCH_GR5_3 ((uint32_t)RI_ASCR2_GR5_3)\r
+#define RI_IOSWITCH_GR4_1 ((uint32_t)RI_ASCR2_GR4_1)\r
+#define RI_IOSWITCH_GR4_2 ((uint32_t)RI_ASCR2_GR4_2)\r
+#define RI_IOSWITCH_GR4_3 ((uint32_t)RI_ASCR2_GR4_3)\r
+#if defined (RI_ASCR2_CH0b) /* STM32L1 devices category Cat.3, Cat.4 and Cat.5 */\r
+#define RI_IOSWITCH_CH0b ((uint32_t)RI_ASCR2_CH0b)\r
+#if defined (RI_ASCR2_CH1b) /* STM32L1 devices category Cat.4 and Cat.5 */\r
+#define RI_IOSWITCH_CH1b ((uint32_t)RI_ASCR2_CH1b)\r
+#define RI_IOSWITCH_CH2b ((uint32_t)RI_ASCR2_CH2b)\r
+#define RI_IOSWITCH_CH3b ((uint32_t)RI_ASCR2_CH3b)\r
+#define RI_IOSWITCH_CH6b ((uint32_t)RI_ASCR2_CH6b)\r
+#define RI_IOSWITCH_CH7b ((uint32_t)RI_ASCR2_CH7b)\r
+#define RI_IOSWITCH_CH8b ((uint32_t)RI_ASCR2_CH8b)\r
+#define RI_IOSWITCH_CH9b ((uint32_t)RI_ASCR2_CH9b)\r
+#define RI_IOSWITCH_CH10b ((uint32_t)RI_ASCR2_CH10b)\r
+#define RI_IOSWITCH_CH11b ((uint32_t)RI_ASCR2_CH11b)\r
+#define RI_IOSWITCH_CH12b ((uint32_t)RI_ASCR2_CH12b)\r
+#endif /* RI_ASCR2_CH1b */\r
+#define RI_IOSWITCH_GR6_3 ((uint32_t)RI_ASCR2_GR6_3)\r
+#define RI_IOSWITCH_GR6_4 ((uint32_t)RI_ASCR2_GR6_4)\r
+#endif /* RI_ASCR2_CH0b */\r
+\r
+\r
+#if defined (RI_ASCR2_CH1b) /* STM32L1 devices category Cat.4 and Cat.5 */\r
+\r
+#define IS_RI_IOSWITCH(__IOSWITCH__) (((__IOSWITCH__) == RI_IOSWITCH_CH0) || ((__IOSWITCH__) == RI_IOSWITCH_CH1) || \\r
+ ((__IOSWITCH__) == RI_IOSWITCH_CH2) || ((__IOSWITCH__) == RI_IOSWITCH_CH3) || \\r
+ ((__IOSWITCH__) == RI_IOSWITCH_CH4) || ((__IOSWITCH__) == RI_IOSWITCH_CH5) || \\r
+ ((__IOSWITCH__) == RI_IOSWITCH_CH6) || ((__IOSWITCH__) == RI_IOSWITCH_CH7) || \\r
+ ((__IOSWITCH__) == RI_IOSWITCH_CH8) || ((__IOSWITCH__) == RI_IOSWITCH_CH9) || \\r
+ ((__IOSWITCH__) == RI_IOSWITCH_CH10) || ((__IOSWITCH__) == RI_IOSWITCH_CH11) || \\r
+ ((__IOSWITCH__) == RI_IOSWITCH_CH12) || ((__IOSWITCH__) == RI_IOSWITCH_CH13) || \\r
+ ((__IOSWITCH__) == RI_IOSWITCH_CH14) || ((__IOSWITCH__) == RI_IOSWITCH_CH15) || \\r
+ ((__IOSWITCH__) == RI_IOSWITCH_CH18) || ((__IOSWITCH__) == RI_IOSWITCH_CH19) || \\r
+ ((__IOSWITCH__) == RI_IOSWITCH_CH20) || ((__IOSWITCH__) == RI_IOSWITCH_CH21) || \\r
+ ((__IOSWITCH__) == RI_IOSWITCH_CH22) || ((__IOSWITCH__) == RI_IOSWITCH_CH23) || \\r
+ ((__IOSWITCH__) == RI_IOSWITCH_CH24) || ((__IOSWITCH__) == RI_IOSWITCH_CH25) || \\r
+ ((__IOSWITCH__) == RI_IOSWITCH_VCOMP) || ((__IOSWITCH__) == RI_IOSWITCH_CH27) || \\r
+ ((__IOSWITCH__) == RI_IOSWITCH_CH28) || ((__IOSWITCH__) == RI_IOSWITCH_CH29) || \\r
+ ((__IOSWITCH__) == RI_IOSWITCH_CH30) || ((__IOSWITCH__) == RI_IOSWITCH_CH31) || \\r
+ ((__IOSWITCH__) == RI_IOSWITCH_GR10_1) || ((__IOSWITCH__) == RI_IOSWITCH_GR10_2) || \\r
+ ((__IOSWITCH__) == RI_IOSWITCH_GR10_3) || ((__IOSWITCH__) == RI_IOSWITCH_GR10_4) || \\r
+ ((__IOSWITCH__) == RI_IOSWITCH_GR6_1) || ((__IOSWITCH__) == RI_IOSWITCH_GR6_2) || \\r
+ ((__IOSWITCH__) == RI_IOSWITCH_GR6_3) || ((__IOSWITCH__) == RI_IOSWITCH_GR6_4) || \\r
+ ((__IOSWITCH__) == RI_IOSWITCH_GR5_1) || ((__IOSWITCH__) == RI_IOSWITCH_GR5_2) || \\r
+ ((__IOSWITCH__) == RI_IOSWITCH_GR5_3) || ((__IOSWITCH__) == RI_IOSWITCH_GR4_1) || \\r
+ ((__IOSWITCH__) == RI_IOSWITCH_GR4_2) || ((__IOSWITCH__) == RI_IOSWITCH_GR4_3) || \\r
+ ((__IOSWITCH__) == RI_IOSWITCH_CH0b) || ((__IOSWITCH__) == RI_IOSWITCH_CH1b) || \\r
+ ((__IOSWITCH__) == RI_IOSWITCH_CH2b) || ((__IOSWITCH__) == RI_IOSWITCH_CH3b) || \\r
+ ((__IOSWITCH__) == RI_IOSWITCH_CH6b) || ((__IOSWITCH__) == RI_IOSWITCH_CH7b) || \\r
+ ((__IOSWITCH__) == RI_IOSWITCH_CH8b) || ((__IOSWITCH__) == RI_IOSWITCH_CH9b) || \\r
+ ((__IOSWITCH__) == RI_IOSWITCH_CH10b) || ((__IOSWITCH__) == RI_IOSWITCH_CH11b) || \\r
+ ((__IOSWITCH__) == RI_IOSWITCH_CH12b))\r
+\r
+#else /* !RI_ASCR2_CH1b */\r
+\r
+#if defined (RI_ASCR2_CH0b) /* STM32L1 devices category Cat.3 */\r
+\r
+#define IS_RI_IOSWITCH(__IOSWITCH__) (((__IOSWITCH__) == RI_IOSWITCH_CH0) || ((__IOSWITCH__) == RI_IOSWITCH_CH1) || \\r
+ ((__IOSWITCH__) == RI_IOSWITCH_CH2) || ((__IOSWITCH__) == RI_IOSWITCH_CH3) || \\r
+ ((__IOSWITCH__) == RI_IOSWITCH_CH4) || ((__IOSWITCH__) == RI_IOSWITCH_CH5) || \\r
+ ((__IOSWITCH__) == RI_IOSWITCH_CH6) || ((__IOSWITCH__) == RI_IOSWITCH_CH7) || \\r
+ ((__IOSWITCH__) == RI_IOSWITCH_CH8) || ((__IOSWITCH__) == RI_IOSWITCH_CH9) || \\r
+ ((__IOSWITCH__) == RI_IOSWITCH_CH10) || ((__IOSWITCH__) == RI_IOSWITCH_CH11) || \\r
+ ((__IOSWITCH__) == RI_IOSWITCH_CH12) || ((__IOSWITCH__) == RI_IOSWITCH_CH13) || \\r
+ ((__IOSWITCH__) == RI_IOSWITCH_CH14) || ((__IOSWITCH__) == RI_IOSWITCH_CH15) || \\r
+ ((__IOSWITCH__) == RI_IOSWITCH_CH18) || ((__IOSWITCH__) == RI_IOSWITCH_CH19) || \\r
+ ((__IOSWITCH__) == RI_IOSWITCH_CH20) || ((__IOSWITCH__) == RI_IOSWITCH_CH21) || \\r
+ ((__IOSWITCH__) == RI_IOSWITCH_CH22) || ((__IOSWITCH__) == RI_IOSWITCH_CH23) || \\r
+ ((__IOSWITCH__) == RI_IOSWITCH_CH24) || ((__IOSWITCH__) == RI_IOSWITCH_CH25) || \\r
+ ((__IOSWITCH__) == RI_IOSWITCH_VCOMP) || ((__IOSWITCH__) == RI_IOSWITCH_GR10_1) || \\r
+ ((__IOSWITCH__) == RI_IOSWITCH_GR10_2) || ((__IOSWITCH__) == RI_IOSWITCH_GR10_3) || \\r
+ ((__IOSWITCH__) == RI_IOSWITCH_GR10_4) || ((__IOSWITCH__) == RI_IOSWITCH_GR6_1) || \\r
+ ((__IOSWITCH__) == RI_IOSWITCH_GR6_2) || ((__IOSWITCH__) == RI_IOSWITCH_GR5_1) || \\r
+ ((__IOSWITCH__) == RI_IOSWITCH_GR5_2) || ((__IOSWITCH__) == RI_IOSWITCH_GR5_3) || \\r
+ ((__IOSWITCH__) == RI_IOSWITCH_GR4_1) || ((__IOSWITCH__) == RI_IOSWITCH_GR4_2) || \\r
+ ((__IOSWITCH__) == RI_IOSWITCH_GR4_3) || ((__IOSWITCH__) == RI_IOSWITCH_CH0b))\r
+\r
+#else /* !RI_ASCR2_CH0b */ /* STM32L1 devices category Cat.1 and Cat.2 */\r
+\r
+#define IS_RI_IOSWITCH(__IOSWITCH__) (((__IOSWITCH__) == RI_IOSWITCH_CH0) || ((__IOSWITCH__) == RI_IOSWITCH_CH1) || \\r
+ ((__IOSWITCH__) == RI_IOSWITCH_CH2) || ((__IOSWITCH__) == RI_IOSWITCH_CH3) || \\r
+ ((__IOSWITCH__) == RI_IOSWITCH_CH4) || ((__IOSWITCH__) == RI_IOSWITCH_CH5) || \\r
+ ((__IOSWITCH__) == RI_IOSWITCH_CH6) || ((__IOSWITCH__) == RI_IOSWITCH_CH7) || \\r
+ ((__IOSWITCH__) == RI_IOSWITCH_CH8) || ((__IOSWITCH__) == RI_IOSWITCH_CH9) || \\r
+ ((__IOSWITCH__) == RI_IOSWITCH_CH10) || ((__IOSWITCH__) == RI_IOSWITCH_CH11) || \\r
+ ((__IOSWITCH__) == RI_IOSWITCH_CH12) || ((__IOSWITCH__) == RI_IOSWITCH_CH13) || \\r
+ ((__IOSWITCH__) == RI_IOSWITCH_CH14) || ((__IOSWITCH__) == RI_IOSWITCH_CH15) || \\r
+ ((__IOSWITCH__) == RI_IOSWITCH_CH18) || ((__IOSWITCH__) == RI_IOSWITCH_CH19) || \\r
+ ((__IOSWITCH__) == RI_IOSWITCH_CH20) || ((__IOSWITCH__) == RI_IOSWITCH_CH21) || \\r
+ ((__IOSWITCH__) == RI_IOSWITCH_CH22) || ((__IOSWITCH__) == RI_IOSWITCH_CH23) || \\r
+ ((__IOSWITCH__) == RI_IOSWITCH_CH24) || ((__IOSWITCH__) == RI_IOSWITCH_CH25) || \\r
+ ((__IOSWITCH__) == RI_IOSWITCH_VCOMP) || ((__IOSWITCH__) == RI_IOSWITCH_GR10_1) || \\r
+ ((__IOSWITCH__) == RI_IOSWITCH_GR10_2) || ((__IOSWITCH__) == RI_IOSWITCH_GR10_3) || \\r
+ ((__IOSWITCH__) == RI_IOSWITCH_GR10_4) || ((__IOSWITCH__) == RI_IOSWITCH_GR6_1) || \\r
+ ((__IOSWITCH__) == RI_IOSWITCH_GR6_2) || ((__IOSWITCH__) == RI_IOSWITCH_GR5_1) || \\r
+ ((__IOSWITCH__) == RI_IOSWITCH_GR5_2) || ((__IOSWITCH__) == RI_IOSWITCH_GR5_3) || \\r
+ ((__IOSWITCH__) == RI_IOSWITCH_GR4_1) || ((__IOSWITCH__) == RI_IOSWITCH_GR4_2) || \\r
+ ((__IOSWITCH__) == RI_IOSWITCH_GR4_3))\r
+\r
+#endif /* RI_ASCR2_CH0b */\r
+#endif /* RI_ASCR2_CH1b */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup RI_Pin PIN define\r
+ * @{\r
+ */\r
+#define RI_PIN_0 ((uint16_t)0x0001) /*!< Pin 0 selected */\r
+#define RI_PIN_1 ((uint16_t)0x0002) /*!< Pin 1 selected */\r
+#define RI_PIN_2 ((uint16_t)0x0004) /*!< Pin 2 selected */\r
+#define RI_PIN_3 ((uint16_t)0x0008) /*!< Pin 3 selected */\r
+#define RI_PIN_4 ((uint16_t)0x0010) /*!< Pin 4 selected */\r
+#define RI_PIN_5 ((uint16_t)0x0020) /*!< Pin 5 selected */\r
+#define RI_PIN_6 ((uint16_t)0x0040) /*!< Pin 6 selected */\r
+#define RI_PIN_7 ((uint16_t)0x0080) /*!< Pin 7 selected */\r
+#define RI_PIN_8 ((uint16_t)0x0100) /*!< Pin 8 selected */\r
+#define RI_PIN_9 ((uint16_t)0x0200) /*!< Pin 9 selected */\r
+#define RI_PIN_10 ((uint16_t)0x0400) /*!< Pin 10 selected */\r
+#define RI_PIN_11 ((uint16_t)0x0800) /*!< Pin 11 selected */\r
+#define RI_PIN_12 ((uint16_t)0x1000) /*!< Pin 12 selected */\r
+#define RI_PIN_13 ((uint16_t)0x2000) /*!< Pin 13 selected */\r
+#define RI_PIN_14 ((uint16_t)0x4000) /*!< Pin 14 selected */\r
+#define RI_PIN_15 ((uint16_t)0x8000) /*!< Pin 15 selected */\r
+#define RI_PIN_ALL ((uint16_t)0xFFFF) /*!< All pins selected */\r
+\r
+#define IS_RI_PIN(__PIN__) ((__PIN__) != (uint16_t)0x00)\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/* Exported macros -----------------------------------------------------------*/\r
+\r
+/** @defgroup HAL_Exported_Macros HAL Exported Macros\r
+ * @{\r
+ */\r
+\r
+/** @defgroup DBGMCU_Macros DBGMCU: Debug MCU\r
+ * @{\r
+ */\r
+\r
+/** @defgroup DBGMCU_Freeze_Unfreeze Freeze Unfreeze Peripherals in Debug mode\r
+ * @brief Freeze/Unfreeze Peripherals in Debug mode\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @brief TIM2 Peripherals Debug mode\r
+ */\r
+#if defined (DBGMCU_APB1_FZ_DBG_TIM2_STOP)\r
+#define __HAL_DBGMCU_FREEZE_TIM2() SET_BIT(DBGMCU->APB1FZ, DBGMCU_APB1_FZ_DBG_TIM2_STOP)\r
+#define __HAL_DBGMCU_UNFREEZE_TIM2() CLEAR_BIT(DBGMCU->APB1FZ, DBGMCU_APB1_FZ_DBG_TIM2_STOP)\r
+#endif\r
+\r
+/**\r
+ * @brief TIM3 Peripherals Debug mode\r
+ */\r
+#if defined (DBGMCU_APB1_FZ_DBG_TIM3_STOP)\r
+#define __HAL_DBGMCU_FREEZE_TIM3() SET_BIT(DBGMCU->APB1FZ, DBGMCU_APB1_FZ_DBG_TIM3_STOP)\r
+#define __HAL_DBGMCU_UNFREEZE_TIM3() CLEAR_BIT(DBGMCU->APB1FZ, DBGMCU_APB1_FZ_DBG_TIM3_STOP)\r
+#endif\r
+\r
+/**\r
+ * @brief TIM4 Peripherals Debug mode\r
+ */\r
+#if defined (DBGMCU_APB1_FZ_DBG_TIM4_STOP)\r
+#define __HAL_DBGMCU_FREEZE_TIM4() SET_BIT(DBGMCU->APB1FZ, DBGMCU_APB1_FZ_DBG_TIM4_STOP)\r
+#define __HAL_DBGMCU_UNFREEZE_TIM4() CLEAR_BIT(DBGMCU->APB1FZ, DBGMCU_APB1_FZ_DBG_TIM4_STOP)\r
+#endif\r
+\r
+/**\r
+ * @brief TIM5 Peripherals Debug mode\r
+ */\r
+#if defined (DBGMCU_APB1_FZ_DBG_TIM5_STOP)\r
+#define __HAL_DBGMCU_FREEZE_TIM5() SET_BIT(DBGMCU->APB1FZ, DBGMCU_APB1_FZ_DBG_TIM5_STOP)\r
+#define __HAL_DBGMCU_UNFREEZE_TIM5() CLEAR_BIT(DBGMCU->APB1FZ, DBGMCU_APB1_FZ_DBG_TIM5_STOP)\r
+#endif\r
+\r
+/**\r
+ * @brief TIM6 Peripherals Debug mode\r
+ */\r
+#if defined (DBGMCU_APB1_FZ_DBG_TIM6_STOP)\r
+#define __HAL_DBGMCU_FREEZE_TIM6() SET_BIT(DBGMCU->APB1FZ, DBGMCU_APB1_FZ_DBG_TIM6_STOP)\r
+#define __HAL_DBGMCU_UNFREEZE_TIM6() CLEAR_BIT(DBGMCU->APB1FZ, DBGMCU_APB1_FZ_DBG_TIM6_STOP)\r
+#endif\r
+\r
+/**\r
+ * @brief TIM7 Peripherals Debug mode\r
+ */\r
+#if defined (DBGMCU_APB1_FZ_DBG_TIM7_STOP)\r
+#define __HAL_DBGMCU_FREEZE_TIM7() SET_BIT(DBGMCU->APB1FZ, DBGMCU_APB1_FZ_DBG_TIM7_STOP)\r
+#define __HAL_DBGMCU_UNFREEZE_TIM7() CLEAR_BIT(DBGMCU->APB1FZ, DBGMCU_APB1_FZ_DBG_TIM7_STOP)\r
+#endif\r
+\r
+/**\r
+ * @brief RTC Peripherals Debug mode\r
+ */\r
+#if defined (DBGMCU_APB1_FZ_DBG_RTC_STOP)\r
+#define __HAL_DBGMCU_FREEZE_RTC() SET_BIT(DBGMCU->APB1FZ, DBGMCU_APB1_FZ_DBG_RTC_STOP)\r
+#define __HAL_DBGMCU_UNFREEZE_RTC() CLEAR_BIT(DBGMCU->APB1FZ, DBGMCU_APB1_FZ_DBG_RTC_STOP)\r
+#endif\r
+\r
+/**\r
+ * @brief WWDG Peripherals Debug mode\r
+ */\r
+#if defined (DBGMCU_APB1_FZ_DBG_WWDG_STOP)\r
+#define __HAL_DBGMCU_FREEZE_WWDG() SET_BIT(DBGMCU->APB1FZ, DBGMCU_APB1_FZ_DBG_WWDG_STOP)\r
+#define __HAL_DBGMCU_UNFREEZE_WWDG() CLEAR_BIT(DBGMCU->APB1FZ, DBGMCU_APB1_FZ_DBG_WWDG_STOP)\r
+#endif\r
+\r
+/**\r
+ * @brief IWDG Peripherals Debug mode\r
+ */\r
+#if defined (DBGMCU_APB1_FZ_DBG_IWDG_STOP)\r
+#define __HAL_DBGMCU_FREEZE_IWDG() SET_BIT(DBGMCU->APB1FZ, DBGMCU_APB1_FZ_DBG_IWDG_STOP)\r
+#define __HAL_DBGMCU_UNFREEZE_IWDG() CLEAR_BIT(DBGMCU->APB1FZ, DBGMCU_APB1_FZ_DBG_IWDG_STOP)\r
+#endif\r
+\r
+/**\r
+ * @brief I2C1 Peripherals Debug mode\r
+ */\r
+#if defined (DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT)\r
+#define __HAL_DBGMCU_FREEZE_I2C1_TIMEOUT() SET_BIT(DBGMCU->APB1FZ, DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT)\r
+#define __HAL_DBGMCU_UNFREEZE_I2C1_TIMEOUT() CLEAR_BIT(DBGMCU->APB1FZ, DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT)\r
+#endif\r
+\r
+/**\r
+ * @brief I2C2 Peripherals Debug mode\r
+ */\r
+#if defined (DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT)\r
+#define __HAL_DBGMCU_FREEZE_I2C2_TIMEOUT() SET_BIT(DBGMCU->APB1FZ, DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT)\r
+#define __HAL_DBGMCU_UNFREEZE_I2C2_TIMEOUT() CLEAR_BIT(DBGMCU->APB1FZ, DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT)\r
+#endif\r
+\r
+/**\r
+ * @brief TIM9 Peripherals Debug mode\r
+ */\r
+#if defined (DBGMCU_APB2_FZ_DBG_TIM9_STOP)\r
+#define __HAL_DBGMCU_FREEZE_TIM9() SET_BIT(DBGMCU->APB2FZ, DBGMCU_APB2_FZ_DBG_TIM9_STOP)\r
+#define __HAL_DBGMCU_UNFREEZE_TIM9() CLEAR_BIT(DBGMCU->APB2FZ, DBGMCU_APB2_FZ_DBG_TIM9_STOP)\r
+#endif\r
+\r
+/**\r
+ * @brief TIM10 Peripherals Debug mode\r
+ */\r
+#if defined (DBGMCU_APB2_FZ_DBG_TIM10_STOP)\r
+#define __HAL_DBGMCU_FREEZE_TIM10() SET_BIT(DBGMCU->APB2FZ, DBGMCU_APB2_FZ_DBG_TIM10_STOP)\r
+#define __HAL_DBGMCU_UNFREEZE_TIM10() CLEAR_BIT(DBGMCU->APB2FZ, DBGMCU_APB2_FZ_DBG_TIM10_STOP)\r
+#endif\r
+\r
+/**\r
+ * @brief TIM11 Peripherals Debug mode\r
+ */\r
+#if defined (DBGMCU_APB2_FZ_DBG_TIM11_STOP)\r
+#define __HAL_DBGMCU_FREEZE_TIM11() SET_BIT(DBGMCU->APB2FZ, DBGMCU_APB2_FZ_DBG_TIM11_STOP)\r
+#define __HAL_DBGMCU_UNFREEZE_TIM11() CLEAR_BIT(DBGMCU->APB2FZ, DBGMCU_APB2_FZ_DBG_TIM11_STOP)\r
+#endif\r
+\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup SYSCFG_Macros SYSCFG: SYStem ConFiG\r
+ * @{\r
+ */\r
+\r
+/** @defgroup SYSCFG_VrefInt VREFINT configuration\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @brief Enables or disables the output of internal reference voltage\r
+ * (VrefInt) on I/O pin.\r
+ * @note The VrefInt output can be routed to any I/O in group 3:\r
+ * - For Cat.1 and Cat.2 devices: CH8 (PB0) or CH9 (PB1).\r
+ * - For Cat.3 devices: CH8 (PB0), CH9 (PB1) or CH0b (PB2).\r
+ * - For Cat.4 and Cat.5 devices: CH8 (PB0), CH9 (PB1), CH0b (PB2),\r
+ * CH1b (PF11) or CH2b (PF12).\r
+ * Note: Comparator peripheral clock must be preliminarily enabled,\r
+ * either in COMP user function "HAL_COMP_MspInit()" (should be\r
+ * done if comparators are used) or by direct clock enable:\r
+ * Refer to macro "__HAL_RCC_COMP_CLK_ENABLE()".\r
+ * Note: In addition with this macro, VrefInt output buffer must be\r
+ * connected to the selected I/O pin. Refer to macro\r
+ * "__HAL_RI_IOSWITCH_CLOSE()".\r
+ * @note VrefInt output enable: Internal reference voltage connected to I/O group 3\r
+ * VrefInt output disable: Internal reference voltage disconnected from I/O group 3\r
+ * @retval None\r
+ */\r
+#define __HAL_SYSCFG_VREFINT_OUT_ENABLE() SET_BIT(COMP->CSR, COMP_CSR_VREFOUTEN)\r
+#define __HAL_SYSCFG_VREFINT_OUT_DISABLE() CLEAR_BIT(COMP->CSR, COMP_CSR_VREFOUTEN)\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup SYSCFG_BootModeConfig Boot Mode Configuration\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @brief Main Flash memory mapped at 0x00000000\r
+ */\r
+#define __HAL_SYSCFG_REMAPMEMORY_FLASH() CLEAR_BIT(SYSCFG->MEMRMP, SYSCFG_MEMRMP_MEM_MODE)\r
+\r
+/** @brief System Flash memory mapped at 0x00000000\r
+ */\r
+#define __HAL_SYSCFG_REMAPMEMORY_SYSTEMFLASH() MODIFY_REG(SYSCFG->MEMRMP, SYSCFG_MEMRMP_MEM_MODE, SYSCFG_MEMRMP_MEM_MODE_0)\r
+\r
+/** @brief Embedded SRAM mapped at 0x00000000\r
+ */\r
+#define __HAL_SYSCFG_REMAPMEMORY_SRAM() MODIFY_REG(SYSCFG->MEMRMP, SYSCFG_MEMRMP_MEM_MODE, SYSCFG_MEMRMP_MEM_MODE_0 | SYSCFG_MEMRMP_MEM_MODE_1)\r
+\r
+#if defined(FSMC_R_BASE)\r
+/** @brief FSMC Bank1 (NOR/PSRAM 1 and 2) mapped at 0x00000000\r
+ */\r
+#define __HAL_SYSCFG_REMAPMEMORY_FSMC() MODIFY_REG(SYSCFG->MEMRMP, SYSCFG_MEMRMP_MEM_MODE, SYSCFG_MEMRMP_MEM_MODE_1)\r
+\r
+#endif /* FSMC_R_BASE */\r
+\r
+/**\r
+ * @brief Returns the boot mode as configured by user.\r
+ * @retval The boot mode as configured by user. The returned value can be one\r
+ * of the following values:\r
+ * @arg SYSCFG_BOOT_MAINFLASH\r
+ * @arg SYSCFG_BOOT_SYSTEMFLASH\r
+ * @arg SYSCFG_BOOT_FSMC (available only for STM32L151xD, STM32L152xD & STM32L162xD)\r
+ * @arg SYSCFG_BOOT_SRAM\r
+ */\r
+#define __HAL_SYSCFG_GET_BOOT_MODE() READ_BIT(SYSCFG->MEMRMP, SYSCFG_MEMRMP_BOOT_MODE)\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup SYSCFG_USBConfig USB DP line Configuration\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @brief Control the internal pull-up on USB DP line.\r
+ */\r
+#define __HAL_SYSCFG_USBPULLUP_ENABLE() SET_BIT(SYSCFG->PMC, SYSCFG_PMC_USB_PU)\r
+\r
+#define __HAL_SYSCFG_USBPULLUP_DISABLE() CLEAR_BIT(SYSCFG->PMC, SYSCFG_PMC_USB_PU)\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup RI_Macris RI: Routing Interface\r
+ * @{\r
+ */\r
+\r
+/** @defgroup RI_InputCaputureConfig Input Capture configuration\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @brief Configures the routing interface to map Input Capture 1 of TIMx to a selected I/O pin.\r
+ * @param __TIMSELECT__ Timer select.\r
+ * This parameter can be one of the following values:\r
+ * @arg TIM_SELECT_NONE: No timer selected and default Timer mapping is enabled.\r
+ * @arg TIM_SELECT_TIM2: Timer 2 Input Captures to be routed.\r
+ * @arg TIM_SELECT_TIM3: Timer 3 Input Captures to be routed.\r
+ * @arg TIM_SELECT_TIM4: Timer 4 Input Captures to be routed.\r
+ * @param __INPUT__ selects which pin to be routed to Input Capture.\r
+ * This parameter must be a value of @ref RI_InputCaptureRouting\r
+ * e.g.\r
+ * __HAL_RI_REMAP_INPUTCAPTURE1(TIM_SELECT_TIM2, RI_INPUTCAPTUREROUTING_1)\r
+ * allows routing of Input capture IC1 of TIM2 to PA4.\r
+ * For details about correspondence between RI_INPUTCAPTUREROUTING_x\r
+ * and I/O pins refer to the parameters' description in the header file\r
+ * or refer to the product reference manual.\r
+ * @note Input capture selection bits are not reset by this function.\r
+ * To reset input capture selection bits, use SYSCFG_RIDeInit() function.\r
+ * @note The I/O should be configured in alternate function mode (AF14) using\r
+ * GPIO_PinAFConfig() function.\r
+ * @retval None.\r
+ */\r
+#define __HAL_RI_REMAP_INPUTCAPTURE1(__TIMSELECT__, __INPUT__) \\r
+ do {assert_param(IS_RI_TIM(__TIMSELECT__)); \\r
+ assert_param(IS_RI_INPUTCAPTURE_ROUTING(__INPUT__)); \\r
+ MODIFY_REG(RI->ICR, RI_ICR_TIM, (__TIMSELECT__)); \\r
+ SET_BIT(RI->ICR, RI_INPUTCAPTURE_IC1); \\r
+ MODIFY_REG(RI->ICR, RI_ICR_IC1OS, (__INPUT__) << POSITION_VAL(RI_ICR_IC1OS)); \\r
+ }while(0)\r
+\r
+/**\r
+ * @brief Configures the routing interface to map Input Capture 2 of TIMx to a selected I/O pin.\r
+ * @param __TIMSELECT__ Timer select.\r
+ * This parameter can be one of the following values:\r
+ * @arg TIM_SELECT_NONE: No timer selected and default Timer mapping is enabled.\r
+ * @arg TIM_SELECT_TIM2: Timer 2 Input Captures to be routed.\r
+ * @arg TIM_SELECT_TIM3: Timer 3 Input Captures to be routed.\r
+ * @arg TIM_SELECT_TIM4: Timer 4 Input Captures to be routed.\r
+ * @param __INPUT__ selects which pin to be routed to Input Capture.\r
+ * This parameter must be a value of @ref RI_InputCaptureRouting\r
+ * @retval None.\r
+ */\r
+#define __HAL_RI_REMAP_INPUTCAPTURE2(__TIMSELECT__, __INPUT__) \\r
+ do {assert_param(IS_RI_TIM(__TIMSELECT__)); \\r
+ assert_param(IS_RI_INPUTCAPTURE_ROUTING(__INPUT__)); \\r
+ MODIFY_REG(RI->ICR, RI_ICR_TIM, (__TIMSELECT__)); \\r
+ SET_BIT(RI->ICR, RI_INPUTCAPTURE_IC2); \\r
+ MODIFY_REG(RI->ICR, RI_ICR_IC2OS, (__INPUT__) << POSITION_VAL(RI_ICR_IC2OS)); \\r
+ }while(0)\r
+\r
+/**\r
+ * @brief Configures the routing interface to map Input Capture 3 of TIMx to a selected I/O pin.\r
+ * @param __TIMSELECT__ Timer select.\r
+ * This parameter can be one of the following values:\r
+ * @arg TIM_SELECT_NONE: No timer selected and default Timer mapping is enabled.\r
+ * @arg TIM_SELECT_TIM2: Timer 2 Input Captures to be routed.\r
+ * @arg TIM_SELECT_TIM3: Timer 3 Input Captures to be routed.\r
+ * @arg TIM_SELECT_TIM4: Timer 4 Input Captures to be routed.\r
+ * @param __INPUT__ selects which pin to be routed to Input Capture.\r
+ * This parameter must be a value of @ref RI_InputCaptureRouting\r
+ * @retval None.\r
+ */\r
+#define __HAL_RI_REMAP_INPUTCAPTURE3(__TIMSELECT__, __INPUT__) \\r
+ do {assert_param(IS_RI_TIM(__TIMSELECT__)); \\r
+ assert_param(IS_RI_INPUTCAPTURE_ROUTING(__INPUT__)); \\r
+ MODIFY_REG(RI->ICR, RI_ICR_TIM, (__TIMSELECT__)); \\r
+ SET_BIT(RI->ICR, RI_INPUTCAPTURE_IC3); \\r
+ MODIFY_REG(RI->ICR, RI_ICR_IC3OS, (__INPUT__) << POSITION_VAL(RI_ICR_IC3OS)); \\r
+ }while(0)\r
+\r
+/**\r
+ * @brief Configures the routing interface to map Input Capture 4 of TIMx to a selected I/O pin.\r
+ * @param __TIMSELECT__ Timer select.\r
+ * This parameter can be one of the following values:\r
+ * @arg TIM_SELECT_NONE: No timer selected and default Timer mapping is enabled.\r
+ * @arg TIM_SELECT_TIM2: Timer 2 Input Captures to be routed.\r
+ * @arg TIM_SELECT_TIM3: Timer 3 Input Captures to be routed.\r
+ * @arg TIM_SELECT_TIM4: Timer 4 Input Captures to be routed.\r
+ * @param __INPUT__ selects which pin to be routed to Input Capture.\r
+ * This parameter must be a value of @ref RI_InputCaptureRouting\r
+ * @retval None.\r
+ */\r
+#define __HAL_RI_REMAP_INPUTCAPTURE4(__TIMSELECT__, __INPUT__) \\r
+ do {assert_param(IS_RI_TIM(__TIMSELECT__)); \\r
+ assert_param(IS_RI_INPUTCAPTURE_ROUTING(__INPUT__)); \\r
+ MODIFY_REG(RI->ICR, RI_ICR_TIM, (__TIMSELECT__)); \\r
+ SET_BIT(RI->ICR, RI_INPUTCAPTURE_IC4); \\r
+ MODIFY_REG(RI->ICR, RI_ICR_IC4OS, (__INPUT__) << POSITION_VAL(RI_ICR_IC4OS)); \\r
+ }while(0)\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup RI_SwitchControlConfig Switch Control configuration\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @brief Enable or disable the switch control mode.\r
+ * @note ENABLE: ADC analog switches closed if the corresponding\r
+ * I/O switch is also closed.\r
+ * When using COMP1, switch control mode must be enabled.\r
+ * @note DISABLE: ADC analog switches open or controlled by the ADC interface.\r
+ * When using the ADC for acquisition, switch control mode\r
+ * must be disabled.\r
+ * @note COMP1 comparator and ADC cannot be used at the same time since\r
+ * they share the ADC switch matrix.\r
+ * @retval None\r
+ */\r
+#define __HAL_RI_SWITCHCONTROLMODE_ENABLE() SET_BIT(RI->ASCR1, RI_ASCR1_SCM)\r
+\r
+#define __HAL_RI_SWITCHCONTROLMODE_DISABLE() CLEAR_BIT(RI->ASCR1, RI_ASCR1_SCM)\r
+\r
+/*\r
+ * @brief Close or Open the routing interface Input Output switches.\r
+ * @param __IOSWITCH__ selects the I/O analog switch number.\r
+ * This parameter must be a value of @ref RI_IOSwitch\r
+ * @retval None\r
+ */\r
+#define __HAL_RI_IOSWITCH_CLOSE(__IOSWITCH__) do { assert_param(IS_RI_IOSWITCH(__IOSWITCH__)); \\r
+ if ((__IOSWITCH__) >> 31 != 0 ) \\r
+ { \\r
+ SET_BIT(RI->ASCR1, (__IOSWITCH__) & 0x7FFFFFFF); \\r
+ } \\r
+ else \\r
+ { \\r
+ SET_BIT(RI->ASCR2, (__IOSWITCH__)); \\r
+ } \\r
+ }while(0)\r
+\r
+#define __HAL_RI_IOSWITCH_OPEN(__IOSWITCH__) do { assert_param(IS_RI_IOSWITCH(__IOSWITCH__)); \\r
+ if ((__IOSWITCH__) >> 31 != 0 ) \\r
+ { \\r
+ CLEAR_BIT(RI->ASCR1, (__IOSWITCH__) & 0x7FFFFFFF); \\r
+ } \\r
+ else \\r
+ { \\r
+ CLEAR_BIT(RI->ASCR2, (__IOSWITCH__)); \\r
+ } \\r
+ }while(0)\r
+\r
+#if defined (COMP_CSR_SW1)\r
+/**\r
+ * @brief Close or open the internal switch COMP1_SW1.\r
+ * This switch connects I/O pin PC3 (can be used as ADC channel 13)\r
+ * and OPAMP3 ouput to ADC switch matrix (ADC channel VCOMP, channel\r
+ * 26) and COMP1 non-inverting input.\r
+ * Pin PC3 connection depends on another switch setting, refer to\r
+ * macro "__HAL_ADC_CHANNEL_SPEED_FAST()".\r
+ * @retval None.\r
+ */\r
+#define __HAL_RI_SWITCH_COMP1_SW1_CLOSE() SET_BIT(COMP->CSR, COMP_CSR_SW1)\r
+\r
+#define __HAL_RI_SWITCH_COMP1_SW1_OPEN() CLEAR_BIT(COMP->CSR, COMP_CSR_SW1)\r
+#endif /* COMP_CSR_SW1 */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup RI_HystConfig Hysteresis Activation and Deactivation\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @brief Enable or disable Hysteresis of the input schmitt triger of Ports A\r
+ * When the I/Os are programmed in input mode by standard I/O port\r
+ * registers, the Schmitt trigger and the hysteresis are enabled by default.\r
+ * When hysteresis is disabled, it is possible to read the\r
+ * corresponding port with a trigger level of VDDIO/2.\r
+ * @param __IOPIN__ : Selects the pin(s) on which to enable or disable hysteresis.\r
+ * This parameter must be a value of @ref RI_Pin\r
+ * @retval None\r
+ */\r
+#define __HAL_RI_HYSTERIS_PORTA_ON(__IOPIN__) do {assert_param(IS_RI_PIN(__IOPIN__)); \\r
+ CLEAR_BIT(RI->HYSCR1, (__IOPIN__)); \\r
+ } while(0)\r
+\r
+#define __HAL_RI_HYSTERIS_PORTA_OFF(__IOPIN__) do {assert_param(IS_RI_PIN(__IOPIN__)); \\r
+ SET_BIT(RI->HYSCR1, (__IOPIN__)); \\r
+ } while(0)\r
+\r
+/**\r
+ * @brief Enable or disable Hysteresis of the input schmitt triger of Ports B\r
+ * When the I/Os are programmed in input mode by standard I/O port\r
+ * registers, the Schmitt trigger and the hysteresis are enabled by default.\r
+ * When hysteresis is disabled, it is possible to read the\r
+ * corresponding port with a trigger level of VDDIO/2.\r
+ * @param __IOPIN__ : Selects the pin(s) on which to enable or disable hysteresis.\r
+ * This parameter must be a value of @ref RI_Pin\r
+ * @retval None\r
+ */\r
+#define __HAL_RI_HYSTERIS_PORTB_ON(__IOPIN__) do {assert_param(IS_RI_PIN(__IOPIN__)); \\r
+ CLEAR_BIT(RI->HYSCR1, (__IOPIN__) << 16 ); \\r
+ } while(0)\r
+\r
+#define __HAL_RI_HYSTERIS_PORTB_OFF(__IOPIN__) do {assert_param(IS_RI_PIN(__IOPIN__)); \\r
+ SET_BIT(RI->HYSCR1, (__IOPIN__) << 16 ); \\r
+ } while(0)\r
+\r
+/**\r
+ * @brief Enable or disable Hysteresis of the input schmitt triger of Ports C\r
+ * When the I/Os are programmed in input mode by standard I/O port\r
+ * registers, the Schmitt trigger and the hysteresis are enabled by default.\r
+ * When hysteresis is disabled, it is possible to read the\r
+ * corresponding port with a trigger level of VDDIO/2.\r
+ * @param __IOPIN__ : Selects the pin(s) on which to enable or disable hysteresis.\r
+ * This parameter must be a value of @ref RI_Pin\r
+ * @retval None\r
+ */\r
+#define __HAL_RI_HYSTERIS_PORTC_ON(__IOPIN__) do {assert_param(IS_RI_PIN(__IOPIN__)); \\r
+ CLEAR_BIT(RI->HYSCR2, (__IOPIN__)); \\r
+ } while(0)\r
+\r
+#define __HAL_RI_HYSTERIS_PORTC_OFF(__IOPIN__) do {assert_param(IS_RI_PIN(__IOPIN__)); \\r
+ SET_BIT(RI->HYSCR2, (__IOPIN__)); \\r
+ } while(0)\r
+\r
+/**\r
+ * @brief Enable or disable Hysteresis of the input schmitt triger of Ports D\r
+ * When the I/Os are programmed in input mode by standard I/O port\r
+ * registers, the Schmitt trigger and the hysteresis are enabled by default.\r
+ * When hysteresis is disabled, it is possible to read the\r
+ * corresponding port with a trigger level of VDDIO/2.\r
+ * @param __IOPIN__ : Selects the pin(s) on which to enable or disable hysteresis.\r
+ * This parameter must be a value of @ref RI_Pin\r
+ * @retval None\r
+ */\r
+#define __HAL_RI_HYSTERIS_PORTD_ON(__IOPIN__) do {assert_param(IS_RI_PIN(__IOPIN__)); \\r
+ CLEAR_BIT(RI->HYSCR2, (__IOPIN__) << 16 ); \\r
+ } while(0)\r
+\r
+#define __HAL_RI_HYSTERIS_PORTD_OFF(__IOPIN__) do {assert_param(IS_RI_PIN(__IOPIN__)); \\r
+ SET_BIT(RI->HYSCR2, (__IOPIN__) << 16 ); \\r
+ } while(0)\r
+\r
+#if defined (GPIOE_BASE)\r
+\r
+/**\r
+ * @brief Enable or disable Hysteresis of the input schmitt triger of Ports E\r
+ * When the I/Os are programmed in input mode by standard I/O port\r
+ * registers, the Schmitt trigger and the hysteresis are enabled by default.\r
+ * When hysteresis is disabled, it is possible to read the\r
+ * corresponding port with a trigger level of VDDIO/2.\r
+ * @param __IOPIN__ : Selects the pin(s) on which to enable or disable hysteresis.\r
+ * This parameter must be a value of @ref RI_Pin\r
+ * @retval None\r
+ */\r
+#define __HAL_RI_HYSTERIS_PORTE_ON(__IOPIN__) do {assert_param(IS_RI_PIN(__IOPIN__)); \\r
+ CLEAR_BIT(RI->HYSCR3, (__IOPIN__)); \\r
+ } while(0)\r
+\r
+#define __HAL_RI_HYSTERIS_PORTE_OFF(__IOPIN__) do {assert_param(IS_RI_PIN(__IOPIN__)); \\r
+ SET_BIT(RI->HYSCR3, (__IOPIN__)); \\r
+ } while(0)\r
+\r
+#endif /* GPIOE_BASE */\r
+\r
+#if defined(GPIOF_BASE) || defined(GPIOG_BASE)\r
+\r
+/**\r
+ * @brief Enable or disable Hysteresis of the input schmitt triger of Ports F\r
+ * When the I/Os are programmed in input mode by standard I/O port\r
+ * registers, the Schmitt trigger and the hysteresis are enabled by default.\r
+ * When hysteresis is disabled, it is possible to read the\r
+ * corresponding port with a trigger level of VDDIO/2.\r
+ * @param __IOPIN__ : Selects the pin(s) on which to enable or disable hysteresis.\r
+ * This parameter must be a value of @ref RI_Pin\r
+ * @retval None\r
+ */\r
+#define __HAL_RI_HYSTERIS_PORTF_ON(__IOPIN__) do {assert_param(IS_RI_PIN(__IOPIN__)); \\r
+ CLEAR_BIT(RI->HYSCR3, (__IOPIN__) << 16 ); \\r
+ } while(0)\r
+\r
+#define __HAL_RI_HYSTERIS_PORTF_OFF(__IOPIN__) do {assert_param(IS_RI_PIN(__IOPIN__)); \\r
+ SET_BIT(RI->HYSCR3, (__IOPIN__) << 16 ); \\r
+ } while(0)\r
+\r
+/**\r
+ * @brief Enable or disable Hysteresis of the input schmitt triger of Ports G\r
+ * When the I/Os are programmed in input mode by standard I/O port\r
+ * registers, the Schmitt trigger and the hysteresis are enabled by default.\r
+ * When hysteresis is disabled, it is possible to read the\r
+ * corresponding port with a trigger level of VDDIO/2.\r
+ * @param __IOPIN__ : Selects the pin(s) on which to enable or disable hysteresis.\r
+ * This parameter must be a value of @ref RI_Pin\r
+ * @retval None\r
+ */\r
+#define __HAL_RI_HYSTERIS_PORTG_ON(__IOPIN__) do {assert_param(IS_RI_PIN(__IOPIN__)); \\r
+ CLEAR_BIT(RI->HYSCR4, (__IOPIN__)); \\r
+ } while(0)\r
+\r
+#define __HAL_RI_HYSTERIS_PORTG_OFF(__IOPIN__) do {assert_param(IS_RI_PIN(__IOPIN__)); \\r
+ SET_BIT(RI->HYSCR4, (__IOPIN__)); \\r
+ } while(0)\r
+\r
+#endif /* GPIOF_BASE || GPIOG_BASE */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/* Exported variables --------------------------------------------------------*/\r
+/** @defgroup HAL_Exported_Variables HAL Exported Variables\r
+ * @{\r
+ */\r
+extern __IO uint32_t uwTick;\r
+extern uint32_t uwTickPrio;\r
+extern uint32_t uwTickFreq;\r
+/**\r
+ * @}\r
+ */\r
+\r
+/* Exported functions --------------------------------------------------------*/\r
+/** @addtogroup HAL_Exported_Functions\r
+ * @{\r
+ */\r
+\r
+/** @addtogroup HAL_Exported_Functions_Group1\r
+ * @{\r
+ */\r
+\r
+/* Initialization and de-initialization functions ******************************/\r
+HAL_StatusTypeDef HAL_Init(void);\r
+HAL_StatusTypeDef HAL_DeInit(void);\r
+void HAL_MspInit(void);\r
+void HAL_MspDeInit(void);\r
+HAL_StatusTypeDef HAL_InitTick(uint32_t TickPriority);\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @addtogroup HAL_Exported_Functions_Group2\r
+ * @{\r
+ */\r
+\r
+/* Peripheral Control functions ************************************************/\r
+void HAL_IncTick(void);\r
+void HAL_Delay(uint32_t Delay);\r
+uint32_t HAL_GetTick(void);\r
+uint32_t HAL_GetTickPrio(void);\r
+HAL_StatusTypeDef HAL_SetTickFreq(uint32_t Freq);\r
+uint32_t HAL_GetTickFreq(void);\r
+void HAL_SuspendTick(void);\r
+void HAL_ResumeTick(void);\r
+uint32_t HAL_GetHalVersion(void);\r
+uint32_t HAL_GetREVID(void);\r
+uint32_t HAL_GetDEVID(void);\r
+uint32_t HAL_GetUIDw0(void);\r
+uint32_t HAL_GetUIDw1(void);\r
+uint32_t HAL_GetUIDw2(void);\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @addtogroup HAL_Exported_Functions_Group3\r
+ * @{\r
+ */\r
+\r
+/* DBGMCU Peripheral Control functions *****************************************/\r
+void HAL_DBGMCU_EnableDBGSleepMode(void);\r
+void HAL_DBGMCU_DisableDBGSleepMode(void);\r
+void HAL_DBGMCU_EnableDBGStopMode(void);\r
+void HAL_DBGMCU_DisableDBGStopMode(void);\r
+void HAL_DBGMCU_EnableDBGStandbyMode(void);\r
+void HAL_DBGMCU_DisableDBGStandbyMode(void);\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+#ifdef __cplusplus\r
+}\r
+#endif\r
+\r
+#endif /* __STM32L1xx_HAL_H */\r
+\r
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\r
--- /dev/null
+/**\r
+ ******************************************************************************\r
+ * @file stm32l1xx_hal_cortex.h\r
+ * @author MCD Application Team\r
+ * @brief Header file of CORTEX HAL module.\r
+ ******************************************************************************\r
+ * @attention\r
+ *\r
+ * <h2><center>© Copyright (c) 2017 STMicroelectronics.\r
+ * All rights reserved.</center></h2>\r
+ *\r
+ * This software component is licensed by ST under BSD 3-Clause license,\r
+ * the "License"; You may not use this file except in compliance with the\r
+ * License. You may obtain a copy of the License at:\r
+ * opensource.org/licenses/BSD-3-Clause\r
+ *\r
+ ******************************************************************************\r
+ */ \r
+\r
+/* Define to prevent recursive inclusion -------------------------------------*/\r
+#ifndef __STM32L1xx_HAL_CORTEX_H\r
+#define __STM32L1xx_HAL_CORTEX_H\r
+\r
+#ifdef __cplusplus\r
+ extern "C" {\r
+#endif\r
+\r
+/* Includes ------------------------------------------------------------------*/\r
+#include "stm32l1xx_hal_def.h"\r
+\r
+/** @addtogroup STM32L1xx_HAL_Driver\r
+ * @{\r
+ */\r
+\r
+/** @addtogroup CORTEX\r
+ * @{\r
+ */\r
+ \r
+/* Exported types ------------------------------------------------------------*/\r
+/** @defgroup CORTEX_Exported_Types Cortex Exported Types\r
+ * @{\r
+ */\r
+\r
+#if (__MPU_PRESENT == 1)\r
+/** @defgroup CORTEX_MPU_Region_Initialization_Structure_definition MPU Region Initialization Structure Definition\r
+ * @brief MPU Region initialization structure \r
+ * @{\r
+ */\r
+typedef struct\r
+{\r
+ uint8_t Enable; /*!< Specifies the status of the region. \r
+ This parameter can be a value of @ref CORTEX_MPU_Region_Enable */\r
+ uint8_t Number; /*!< Specifies the number of the region to protect. \r
+ This parameter can be a value of @ref CORTEX_MPU_Region_Number */\r
+ uint32_t BaseAddress; /*!< Specifies the base address of the region to protect. */\r
+ uint8_t Size; /*!< Specifies the size of the region to protect. \r
+ This parameter can be a value of @ref CORTEX_MPU_Region_Size */\r
+ uint8_t SubRegionDisable; /*!< Specifies the number of the subregion protection to disable. \r
+ This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF */ \r
+ uint8_t TypeExtField; /*!< Specifies the TEX field level.\r
+ This parameter can be a value of @ref CORTEX_MPU_TEX_Levels */ \r
+ uint8_t AccessPermission; /*!< Specifies the region access permission type. \r
+ This parameter can be a value of @ref CORTEX_MPU_Region_Permission_Attributes */\r
+ uint8_t DisableExec; /*!< Specifies the instruction access status. \r
+ This parameter can be a value of @ref CORTEX_MPU_Instruction_Access */\r
+ uint8_t IsShareable; /*!< Specifies the shareability status of the protected region. \r
+ This parameter can be a value of @ref CORTEX_MPU_Access_Shareable */\r
+ uint8_t IsCacheable; /*!< Specifies the cacheable status of the region protected. \r
+ This parameter can be a value of @ref CORTEX_MPU_Access_Cacheable */\r
+ uint8_t IsBufferable; /*!< Specifies the bufferable status of the protected region. \r
+ This parameter can be a value of @ref CORTEX_MPU_Access_Bufferable */\r
+}MPU_Region_InitTypeDef;\r
+/**\r
+ * @}\r
+ */\r
+#endif /* __MPU_PRESENT */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/* Exported constants --------------------------------------------------------*/\r
+\r
+/** @defgroup CORTEX_Exported_Constants CORTEX Exported Constants\r
+ * @{\r
+ */\r
+\r
+\r
+/** @defgroup CORTEX_Preemption_Priority_Group CORTEX Preemption Priority Group \r
+ * @{\r
+ */\r
+\r
+#define NVIC_PRIORITYGROUP_0 (0x00000007U) /*!< 0 bits for pre-emption priority\r
+ 4 bits for subpriority */\r
+#define NVIC_PRIORITYGROUP_1 (0x00000006U) /*!< 1 bits for pre-emption priority\r
+ 3 bits for subpriority */\r
+#define NVIC_PRIORITYGROUP_2 (0x00000005U) /*!< 2 bits for pre-emption priority\r
+ 2 bits for subpriority */\r
+#define NVIC_PRIORITYGROUP_3 (0x00000004U) /*!< 3 bits for pre-emption priority\r
+ 1 bits for subpriority */\r
+#define NVIC_PRIORITYGROUP_4 (0x00000003U) /*!< 4 bits for pre-emption priority\r
+ 0 bits for subpriority */\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup CORTEX_SysTick_clock_source CORTEX SysTick clock source\r
+ * @{\r
+ */\r
+#define SYSTICK_CLKSOURCE_HCLK_DIV8 (0x00000000U)\r
+#define SYSTICK_CLKSOURCE_HCLK (0x00000004U)\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+#if (__MPU_PRESENT == 1)\r
+/** @defgroup CORTEX_MPU_HFNMI_PRIVDEF_Control MPU HFNMI and PRIVILEGED Access control\r
+ * @{\r
+ */\r
+#define MPU_HFNMI_PRIVDEF_NONE (0x00000000U) \r
+#define MPU_HARDFAULT_NMI (MPU_CTRL_HFNMIENA_Msk)\r
+#define MPU_PRIVILEGED_DEFAULT (MPU_CTRL_PRIVDEFENA_Msk)\r
+#define MPU_HFNMI_PRIVDEF (MPU_CTRL_HFNMIENA_Msk | MPU_CTRL_PRIVDEFENA_Msk)\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup CORTEX_MPU_Region_Enable CORTEX MPU Region Enable\r
+ * @{\r
+ */\r
+#define MPU_REGION_ENABLE ((uint8_t)0x01)\r
+#define MPU_REGION_DISABLE ((uint8_t)0x00)\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup CORTEX_MPU_Instruction_Access CORTEX MPU Instruction Access\r
+ * @{\r
+ */\r
+#define MPU_INSTRUCTION_ACCESS_ENABLE ((uint8_t)0x00)\r
+#define MPU_INSTRUCTION_ACCESS_DISABLE ((uint8_t)0x01)\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup CORTEX_MPU_Access_Shareable CORTEX MPU Instruction Access Shareable\r
+ * @{\r
+ */\r
+#define MPU_ACCESS_SHAREABLE ((uint8_t)0x01)\r
+#define MPU_ACCESS_NOT_SHAREABLE ((uint8_t)0x00)\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup CORTEX_MPU_Access_Cacheable CORTEX MPU Instruction Access Cacheable\r
+ * @{\r
+ */\r
+#define MPU_ACCESS_CACHEABLE ((uint8_t)0x01)\r
+#define MPU_ACCESS_NOT_CACHEABLE ((uint8_t)0x00)\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup CORTEX_MPU_Access_Bufferable CORTEX MPU Instruction Access Bufferable\r
+ * @{\r
+ */\r
+#define MPU_ACCESS_BUFFERABLE ((uint8_t)0x01)\r
+#define MPU_ACCESS_NOT_BUFFERABLE ((uint8_t)0x00)\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup CORTEX_MPU_TEX_Levels MPU TEX Levels\r
+ * @{\r
+ */\r
+#define MPU_TEX_LEVEL0 ((uint8_t)0x00)\r
+#define MPU_TEX_LEVEL1 ((uint8_t)0x01)\r
+#define MPU_TEX_LEVEL2 ((uint8_t)0x02)\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup CORTEX_MPU_Region_Size CORTEX MPU Region Size\r
+ * @{\r
+ */\r
+#define MPU_REGION_SIZE_32B ((uint8_t)0x04)\r
+#define MPU_REGION_SIZE_64B ((uint8_t)0x05)\r
+#define MPU_REGION_SIZE_128B ((uint8_t)0x06) \r
+#define MPU_REGION_SIZE_256B ((uint8_t)0x07) \r
+#define MPU_REGION_SIZE_512B ((uint8_t)0x08) \r
+#define MPU_REGION_SIZE_1KB ((uint8_t)0x09) \r
+#define MPU_REGION_SIZE_2KB ((uint8_t)0x0A)\r
+#define MPU_REGION_SIZE_4KB ((uint8_t)0x0B) \r
+#define MPU_REGION_SIZE_8KB ((uint8_t)0x0C) \r
+#define MPU_REGION_SIZE_16KB ((uint8_t)0x0D) \r
+#define MPU_REGION_SIZE_32KB ((uint8_t)0x0E) \r
+#define MPU_REGION_SIZE_64KB ((uint8_t)0x0F) \r
+#define MPU_REGION_SIZE_128KB ((uint8_t)0x10)\r
+#define MPU_REGION_SIZE_256KB ((uint8_t)0x11)\r
+#define MPU_REGION_SIZE_512KB ((uint8_t)0x12)\r
+#define MPU_REGION_SIZE_1MB ((uint8_t)0x13) \r
+#define MPU_REGION_SIZE_2MB ((uint8_t)0x14) \r
+#define MPU_REGION_SIZE_4MB ((uint8_t)0x15) \r
+#define MPU_REGION_SIZE_8MB ((uint8_t)0x16) \r
+#define MPU_REGION_SIZE_16MB ((uint8_t)0x17)\r
+#define MPU_REGION_SIZE_32MB ((uint8_t)0x18)\r
+#define MPU_REGION_SIZE_64MB ((uint8_t)0x19)\r
+#define MPU_REGION_SIZE_128MB ((uint8_t)0x1A)\r
+#define MPU_REGION_SIZE_256MB ((uint8_t)0x1B)\r
+#define MPU_REGION_SIZE_512MB ((uint8_t)0x1C)\r
+#define MPU_REGION_SIZE_1GB ((uint8_t)0x1D) \r
+#define MPU_REGION_SIZE_2GB ((uint8_t)0x1E) \r
+#define MPU_REGION_SIZE_4GB ((uint8_t)0x1F)\r
+/** \r
+ * @}\r
+ */\r
+ \r
+/** @defgroup CORTEX_MPU_Region_Permission_Attributes CORTEX MPU Region Permission Attributes \r
+ * @{\r
+ */\r
+#define MPU_REGION_NO_ACCESS ((uint8_t)0x00) \r
+#define MPU_REGION_PRIV_RW ((uint8_t)0x01) \r
+#define MPU_REGION_PRIV_RW_URO ((uint8_t)0x02) \r
+#define MPU_REGION_FULL_ACCESS ((uint8_t)0x03) \r
+#define MPU_REGION_PRIV_RO ((uint8_t)0x05) \r
+#define MPU_REGION_PRIV_RO_URO ((uint8_t)0x06)\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup CORTEX_MPU_Region_Number CORTEX MPU Region Number\r
+ * @{\r
+ */\r
+#define MPU_REGION_NUMBER0 ((uint8_t)0x00) \r
+#define MPU_REGION_NUMBER1 ((uint8_t)0x01) \r
+#define MPU_REGION_NUMBER2 ((uint8_t)0x02) \r
+#define MPU_REGION_NUMBER3 ((uint8_t)0x03) \r
+#define MPU_REGION_NUMBER4 ((uint8_t)0x04) \r
+#define MPU_REGION_NUMBER5 ((uint8_t)0x05)\r
+#define MPU_REGION_NUMBER6 ((uint8_t)0x06)\r
+#define MPU_REGION_NUMBER7 ((uint8_t)0x07)\r
+/**\r
+ * @}\r
+ */\r
+#endif /* __MPU_PRESENT */\r
+/**\r
+ * @}\r
+ */\r
+ \r
+/* Exported Macros -----------------------------------------------------------*/\r
+/** @defgroup CORTEX_Exported_Macros CORTEX Exported Macros\r
+ * @{\r
+ */\r
+\r
+/** @defgroup CORTEX_Preemption_Priority_Group_Macro CORTEX Preemption Priority Group \r
+ * @{\r
+ */\r
+#define IS_NVIC_PRIORITY_GROUP(GROUP) (((GROUP) == NVIC_PRIORITYGROUP_0) || \\r
+ ((GROUP) == NVIC_PRIORITYGROUP_1) || \\r
+ ((GROUP) == NVIC_PRIORITYGROUP_2) || \\r
+ ((GROUP) == NVIC_PRIORITYGROUP_3) || \\r
+ ((GROUP) == NVIC_PRIORITYGROUP_4))\r
+\r
+#define IS_NVIC_PREEMPTION_PRIORITY(PRIORITY) ((PRIORITY) < 0x10)\r
+\r
+#define IS_NVIC_SUB_PRIORITY(PRIORITY) ((PRIORITY) < 0x10)\r
+\r
+#define IS_NVIC_DEVICE_IRQ(IRQ) ((IRQ) >= 0x00)\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/* Private macro -------------------------------------------------------------*/\r
+/** @defgroup CORTEX_Private_Macros CORTEX Private Macros\r
+ * @{\r
+ */ \r
+ \r
+/** @defgroup CORTEX_SysTick_clock_source_Macro_Private CORTEX SysTick clock source\r
+ * @{\r
+ */ \r
+#define IS_SYSTICK_CLK_SOURCE(SOURCE) (((SOURCE) == SYSTICK_CLKSOURCE_HCLK) || \\r
+ ((SOURCE) == SYSTICK_CLKSOURCE_HCLK_DIV8))\r
+/**\r
+ * @}\r
+ */\r
+\r
+#if (__MPU_PRESENT == 1)\r
+#define IS_MPU_REGION_ENABLE(STATE) (((STATE) == MPU_REGION_ENABLE) || \\r
+ ((STATE) == MPU_REGION_DISABLE))\r
+\r
+#define IS_MPU_INSTRUCTION_ACCESS(STATE) (((STATE) == MPU_INSTRUCTION_ACCESS_ENABLE) || \\r
+ ((STATE) == MPU_INSTRUCTION_ACCESS_DISABLE))\r
+\r
+#define IS_MPU_ACCESS_SHAREABLE(STATE) (((STATE) == MPU_ACCESS_SHAREABLE) || \\r
+ ((STATE) == MPU_ACCESS_NOT_SHAREABLE))\r
+\r
+#define IS_MPU_ACCESS_CACHEABLE(STATE) (((STATE) == MPU_ACCESS_CACHEABLE) || \\r
+ ((STATE) == MPU_ACCESS_NOT_CACHEABLE))\r
+\r
+#define IS_MPU_ACCESS_BUFFERABLE(STATE) (((STATE) == MPU_ACCESS_BUFFERABLE) || \\r
+ ((STATE) == MPU_ACCESS_NOT_BUFFERABLE))\r
+\r
+#define IS_MPU_TEX_LEVEL(TYPE) (((TYPE) == MPU_TEX_LEVEL0) || \\r
+ ((TYPE) == MPU_TEX_LEVEL1) || \\r
+ ((TYPE) == MPU_TEX_LEVEL2))\r
+\r
+#define IS_MPU_REGION_PERMISSION_ATTRIBUTE(TYPE) (((TYPE) == MPU_REGION_NO_ACCESS) || \\r
+ ((TYPE) == MPU_REGION_PRIV_RW) || \\r
+ ((TYPE) == MPU_REGION_PRIV_RW_URO) || \\r
+ ((TYPE) == MPU_REGION_FULL_ACCESS) || \\r
+ ((TYPE) == MPU_REGION_PRIV_RO) || \\r
+ ((TYPE) == MPU_REGION_PRIV_RO_URO))\r
+\r
+#define IS_MPU_REGION_NUMBER(NUMBER) (((NUMBER) == MPU_REGION_NUMBER0) || \\r
+ ((NUMBER) == MPU_REGION_NUMBER1) || \\r
+ ((NUMBER) == MPU_REGION_NUMBER2) || \\r
+ ((NUMBER) == MPU_REGION_NUMBER3) || \\r
+ ((NUMBER) == MPU_REGION_NUMBER4) || \\r
+ ((NUMBER) == MPU_REGION_NUMBER5) || \\r
+ ((NUMBER) == MPU_REGION_NUMBER6) || \\r
+ ((NUMBER) == MPU_REGION_NUMBER7))\r
+\r
+#define IS_MPU_REGION_SIZE(SIZE) (((SIZE) == MPU_REGION_SIZE_32B) || \\r
+ ((SIZE) == MPU_REGION_SIZE_64B) || \\r
+ ((SIZE) == MPU_REGION_SIZE_128B) || \\r
+ ((SIZE) == MPU_REGION_SIZE_256B) || \\r
+ ((SIZE) == MPU_REGION_SIZE_512B) || \\r
+ ((SIZE) == MPU_REGION_SIZE_1KB) || \\r
+ ((SIZE) == MPU_REGION_SIZE_2KB) || \\r
+ ((SIZE) == MPU_REGION_SIZE_4KB) || \\r
+ ((SIZE) == MPU_REGION_SIZE_8KB) || \\r
+ ((SIZE) == MPU_REGION_SIZE_16KB) || \\r
+ ((SIZE) == MPU_REGION_SIZE_32KB) || \\r
+ ((SIZE) == MPU_REGION_SIZE_64KB) || \\r
+ ((SIZE) == MPU_REGION_SIZE_128KB) || \\r
+ ((SIZE) == MPU_REGION_SIZE_256KB) || \\r
+ ((SIZE) == MPU_REGION_SIZE_512KB) || \\r
+ ((SIZE) == MPU_REGION_SIZE_1MB) || \\r
+ ((SIZE) == MPU_REGION_SIZE_2MB) || \\r
+ ((SIZE) == MPU_REGION_SIZE_4MB) || \\r
+ ((SIZE) == MPU_REGION_SIZE_8MB) || \\r
+ ((SIZE) == MPU_REGION_SIZE_16MB) || \\r
+ ((SIZE) == MPU_REGION_SIZE_32MB) || \\r
+ ((SIZE) == MPU_REGION_SIZE_64MB) || \\r
+ ((SIZE) == MPU_REGION_SIZE_128MB) || \\r
+ ((SIZE) == MPU_REGION_SIZE_256MB) || \\r
+ ((SIZE) == MPU_REGION_SIZE_512MB) || \\r
+ ((SIZE) == MPU_REGION_SIZE_1GB) || \\r
+ ((SIZE) == MPU_REGION_SIZE_2GB) || \\r
+ ((SIZE) == MPU_REGION_SIZE_4GB))\r
+\r
+#define IS_MPU_SUB_REGION_DISABLE(SUBREGION) ((SUBREGION) < (uint16_t)0x00FF)\r
+#endif /* __MPU_PRESENT */\r
+\r
+/**\r
+ * @}\r
+ */\r
+ \r
+/* Private functions ---------------------------------------------------------*/ \r
+/** @defgroup CORTEX_Private_Functions CORTEX Private Functions\r
+ * @brief CORTEX private functions \r
+ * @{\r
+ */\r
+\r
+\r
+/**\r
+ * @}\r
+ */ \r
+ \r
+/* Exported functions --------------------------------------------------------*/\r
+/** @addtogroup CORTEX_Exported_Functions\r
+ * @{\r
+ */\r
+\r
+/** @addtogroup CORTEX_Exported_Functions_Group1\r
+ * @{\r
+ */ \r
+/* Initialization and de-initialization functions *****************************/\r
+void HAL_NVIC_SetPriorityGrouping(uint32_t PriorityGroup);\r
+void HAL_NVIC_SetPriority(IRQn_Type IRQn, uint32_t PreemptPriority, uint32_t SubPriority);\r
+void HAL_NVIC_EnableIRQ(IRQn_Type IRQn);\r
+void HAL_NVIC_DisableIRQ(IRQn_Type IRQn);\r
+void HAL_NVIC_SystemReset(void);\r
+uint32_t HAL_SYSTICK_Config(uint32_t TicksNumb);\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @addtogroup CORTEX_Exported_Functions_Group2\r
+ * @{\r
+ */ \r
+/* Peripheral Control functions ***********************************************/\r
+#if (__MPU_PRESENT == 1)\r
+void HAL_MPU_Enable(uint32_t MPU_Control);\r
+void HAL_MPU_Disable(void);\r
+void HAL_MPU_ConfigRegion(MPU_Region_InitTypeDef *MPU_Init);\r
+#endif /* __MPU_PRESENT */\r
+uint32_t HAL_NVIC_GetPriorityGrouping(void);\r
+void HAL_NVIC_GetPriority(IRQn_Type IRQn, uint32_t PriorityGroup, uint32_t* pPreemptPriority, uint32_t* pSubPriority);\r
+uint32_t HAL_NVIC_GetPendingIRQ(IRQn_Type IRQn);\r
+void HAL_NVIC_SetPendingIRQ(IRQn_Type IRQn);\r
+void HAL_NVIC_ClearPendingIRQ(IRQn_Type IRQn);\r
+uint32_t HAL_NVIC_GetActive(IRQn_Type IRQn);\r
+void HAL_SYSTICK_CLKSourceConfig(uint32_t CLKSource);\r
+void HAL_SYSTICK_IRQHandler(void);\r
+void HAL_SYSTICK_Callback(void);\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/**\r
+ * @}\r
+ */\r
+ \r
+#ifdef __cplusplus\r
+}\r
+#endif\r
+\r
+#endif /* __STM32L1xx_HAL_CORTEX_H */\r
+ \r
+\r
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\r
--- /dev/null
+/**\r
+ ******************************************************************************\r
+ * @file stm32l1xx_hal_def.h\r
+ * @author MCD Application Team\r
+ * @brief This file contains HAL common defines, enumeration, macros and\r
+ * structures definitions.\r
+ ******************************************************************************\r
+ * @attention\r
+ *\r
+ * <h2><center>© Copyright (c) 2017 STMicroelectronics.\r
+ * All rights reserved.</center></h2>\r
+ *\r
+ * This software component is licensed by ST under BSD 3-Clause license,\r
+ * the "License"; You may not use this file except in compliance with the\r
+ * License. You may obtain a copy of the License at:\r
+ * opensource.org/licenses/BSD-3-Clause\r
+ *\r
+ ******************************************************************************\r
+ */\r
+\r
+/* Define to prevent recursive inclusion -------------------------------------*/\r
+#ifndef __STM32L1xx_HAL_DEF\r
+#define __STM32L1xx_HAL_DEF\r
+\r
+#ifdef __cplusplus\r
+ extern "C" {\r
+#endif\r
+\r
+/* Includes ------------------------------------------------------------------*/\r
+#include "stm32l1xx.h"\r
+#include "Legacy/stm32_hal_legacy.h"\r
+#include <stddef.h>\r
+\r
+/* Exported types ------------------------------------------------------------*/\r
+\r
+/**\r
+ * @brief HAL Status structures definition\r
+ */\r
+typedef enum\r
+{\r
+ HAL_OK = 0x00U,\r
+ HAL_ERROR = 0x01U,\r
+ HAL_BUSY = 0x02U,\r
+ HAL_TIMEOUT = 0x03U\r
+} HAL_StatusTypeDef;\r
+\r
+/**\r
+ * @brief HAL Lock structures definition\r
+ */\r
+typedef enum\r
+{\r
+ HAL_UNLOCKED = 0x00U,\r
+ HAL_LOCKED = 0x01U\r
+} HAL_LockTypeDef;\r
+\r
+/* Exported macro ------------------------------------------------------------*/\r
+\r
+#define UNUSED(X) (void)X /* To avoid gcc/g++ warnings */\r
+\r
+#define HAL_MAX_DELAY 0xFFFFFFFFU\r
+\r
+#define HAL_IS_BIT_SET(REG, BIT) (((REG) & (BIT)) == (BIT))\r
+#define HAL_IS_BIT_CLR(REG, BIT) (((REG) & (BIT)) == 0U)\r
+\r
+#define __HAL_LINKDMA(__HANDLE__, __PPP_DMA_FIELD_, __DMA_HANDLE_) \\r
+ do{ \\r
+ (__HANDLE__)->__PPP_DMA_FIELD_ = &(__DMA_HANDLE_); \\r
+ (__DMA_HANDLE_).Parent = (__HANDLE__); \\r
+ } while(0)\r
+\r
+/** @brief Reset the Handle's State field.\r
+ * @param __HANDLE__: specifies the Peripheral Handle.\r
+ * @note This macro can be used for the following purpose:\r
+ * - When the Handle is declared as local variable; before passing it as parameter\r
+ * to HAL_PPP_Init() for the first time, it is mandatory to use this macro\r
+ * to set to 0 the Handle's "State" field.\r
+ * Otherwise, "State" field may have any random value and the first time the function\r
+ * HAL_PPP_Init() is called, the low level hardware initialization will be missed\r
+ * (i.e. HAL_PPP_MspInit() will not be executed).\r
+ * - When there is a need to reconfigure the low level hardware: instead of calling\r
+ * HAL_PPP_DeInit() then HAL_PPP_Init(), user can make a call to this macro then HAL_PPP_Init().\r
+ * In this later function, when the Handle's "State" field is set to 0, it will execute the function\r
+ * HAL_PPP_MspInit() which will reconfigure the low level hardware.\r
+ * @retval None\r
+ */\r
+#define __HAL_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = 0U)\r
+\r
+#if (USE_RTOS == 1)\r
+\r
+ /* Reserved for future use */\r
+ #error "USE_RTOS should be 0 in the current HAL release"\r
+\r
+#else\r
+ #define __HAL_LOCK(__HANDLE__) \\r
+ do{ \\r
+ if((__HANDLE__)->Lock == HAL_LOCKED) \\r
+ { \\r
+ return HAL_BUSY; \\r
+ } \\r
+ else \\r
+ { \\r
+ (__HANDLE__)->Lock = HAL_LOCKED; \\r
+ } \\r
+ }while (0)\r
+\r
+ #define __HAL_UNLOCK(__HANDLE__) \\r
+ do{ \\r
+ (__HANDLE__)->Lock = HAL_UNLOCKED; \\r
+ }while (0)\r
+#endif /* USE_RTOS */\r
+\r
+#if defined ( __GNUC__ ) && !defined (__CC_ARM) /* GNU Compiler */\r
+ #ifndef __weak\r
+ #define __weak __attribute__((weak))\r
+ #endif /* __weak */\r
+ #ifndef __packed\r
+ #define __packed __attribute__((__packed__))\r
+ #endif /* __packed */\r
+#endif /* __GNUC__ */\r
+\r
+\r
+/* Macro to get variable aligned on 4-bytes, for __ICCARM__ the directive "#pragma data_alignment=4" must be used instead */\r
+#if defined (__GNUC__) && !defined (__CC_ARM) /* GNU Compiler */\r
+ #ifndef __ALIGN_END\r
+ #define __ALIGN_END __attribute__ ((aligned (4)))\r
+ #endif /* __ALIGN_END */\r
+ #ifndef __ALIGN_BEGIN\r
+ #define __ALIGN_BEGIN\r
+ #endif /* __ALIGN_BEGIN */\r
+#else\r
+ #ifndef __ALIGN_END\r
+ #define __ALIGN_END\r
+ #endif /* __ALIGN_END */\r
+ #ifndef __ALIGN_BEGIN\r
+ #if defined (__CC_ARM) /* ARM Compiler */\r
+ #define __ALIGN_BEGIN __align(4)\r
+ #elif defined (__ICCARM__) /* IAR Compiler */\r
+ #define __ALIGN_BEGIN\r
+ #endif /* __CC_ARM */\r
+ #endif /* __ALIGN_BEGIN */\r
+#endif /* __GNUC__ */\r
+\r
+/**\r
+ * @brief __RAM_FUNC definition\r
+ */\r
+#if defined ( __CC_ARM )\r
+/* ARM Compiler\r
+ ------------\r
+ RAM functions are defined using the toolchain options.\r
+ Functions that are executed in RAM should reside in a separate source module.\r
+ Using the 'Options for File' dialog you can simply change the 'Code / Const'\r
+ area of a module to a memory space in physical RAM.\r
+ Available memory areas are declared in the 'Target' tab of the 'Options for Target'\r
+ dialog.\r
+*/\r
+#define __RAM_FUNC\r
+\r
+#elif defined ( __ICCARM__ )\r
+/* ICCARM Compiler\r
+ ---------------\r
+ RAM functions are defined using a specific toolchain keyword "__ramfunc".\r
+*/\r
+#define __RAM_FUNC __ramfunc\r
+\r
+#elif defined ( __GNUC__ )\r
+/* GNU Compiler\r
+ ------------\r
+ RAM functions are defined using a specific toolchain attribute\r
+ "__attribute__((section(".RamFunc")))".\r
+*/\r
+#define __RAM_FUNC __attribute__((section(".RamFunc")))\r
+\r
+#endif\r
+\r
+/**\r
+ * @brief __NOINLINE definition\r
+ */\r
+#if defined ( __CC_ARM ) || defined ( __GNUC__ )\r
+/* ARM & GNUCompiler\r
+ ----------------\r
+*/\r
+#define __NOINLINE __attribute__ ( (noinline) )\r
+\r
+#elif defined ( __ICCARM__ )\r
+/* ICCARM Compiler\r
+ ---------------\r
+*/\r
+#define __NOINLINE _Pragma("optimize = no_inline")\r
+\r
+#endif\r
+\r
+#ifdef __cplusplus\r
+}\r
+#endif\r
+\r
+#endif /* ___STM32L1xx_HAL_DEF */\r
+\r
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\r
--- /dev/null
+/**\r
+ ******************************************************************************\r
+ * @file stm32l1xx_hal_dma.h\r
+ * @author MCD Application Team\r
+ * @brief Header file of DMA HAL module.\r
+ ******************************************************************************\r
+ * @attention\r
+ *\r
+ * <h2><center>© Copyright (c) 2017 STMicroelectronics.\r
+ * All rights reserved.</center></h2>\r
+ *\r
+ * This software component is licensed by ST under BSD 3-Clause license,\r
+ * the "License"; You may not use this file except in compliance with the\r
+ * License. You may obtain a copy of the License at:\r
+ * opensource.org/licenses/BSD-3-Clause\r
+ *\r
+ ******************************************************************************\r
+ */\r
+\r
+/* Define to prevent recursive inclusion -------------------------------------*/\r
+#ifndef STM32L1xx_HAL_DMA_H\r
+#define STM32L1xx_HAL_DMA_H\r
+\r
+#ifdef __cplusplus\r
+ extern "C" {\r
+#endif\r
+\r
+/* Includes ------------------------------------------------------------------*/\r
+#include "stm32l1xx_hal_def.h"\r
+\r
+/** @addtogroup STM32L1xx_HAL_Driver\r
+ * @{\r
+ */\r
+\r
+/** @addtogroup DMA\r
+ * @{\r
+ */\r
+\r
+/* Exported types ------------------------------------------------------------*/\r
+/** @defgroup DMA_Exported_Types DMA Exported Types\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @brief DMA Configuration Structure definition\r
+ */\r
+typedef struct\r
+{\r
+ uint32_t Direction; /*!< Specifies if the data will be transferred from memory to peripheral,\r
+ from memory to memory or from peripheral to memory.\r
+ This parameter can be a value of @ref DMA_Data_transfer_direction */\r
+\r
+ uint32_t PeriphInc; /*!< Specifies whether the Peripheral address register should be incremented or not.\r
+ This parameter can be a value of @ref DMA_Peripheral_incremented_mode */\r
+\r
+ uint32_t MemInc; /*!< Specifies whether the memory address register should be incremented or not.\r
+ This parameter can be a value of @ref DMA_Memory_incremented_mode */\r
+\r
+ uint32_t PeriphDataAlignment; /*!< Specifies the Peripheral data width.\r
+ This parameter can be a value of @ref DMA_Peripheral_data_size */\r
+\r
+ uint32_t MemDataAlignment; /*!< Specifies the Memory data width.\r
+ This parameter can be a value of @ref DMA_Memory_data_size */\r
+\r
+ uint32_t Mode; /*!< Specifies the operation mode of the DMAy Channelx.\r
+ This parameter can be a value of @ref DMA_mode\r
+ @note The circular buffer mode cannot be used if the memory-to-memory\r
+ data transfer is configured on the selected Channel */\r
+\r
+ uint32_t Priority; /*!< Specifies the software priority for the DMAy Channelx.\r
+ This parameter can be a value of @ref DMA_Priority_level */\r
+} DMA_InitTypeDef;\r
+\r
+/**\r
+ * @brief HAL DMA State structures definition\r
+ */\r
+typedef enum\r
+{\r
+ HAL_DMA_STATE_RESET = 0x00U, /*!< DMA not yet initialized or disabled */\r
+ HAL_DMA_STATE_READY = 0x01U, /*!< DMA initialized and ready for use */\r
+ HAL_DMA_STATE_BUSY = 0x02U, /*!< DMA process is ongoing */\r
+ HAL_DMA_STATE_TIMEOUT = 0x03U, /*!< DMA timeout state */\r
+}HAL_DMA_StateTypeDef;\r
+\r
+/**\r
+ * @brief HAL DMA Error Code structure definition\r
+ */\r
+typedef enum\r
+{\r
+ HAL_DMA_FULL_TRANSFER = 0x00U, /*!< Full transfer */\r
+ HAL_DMA_HALF_TRANSFER = 0x01U /*!< Half Transfer */\r
+}HAL_DMA_LevelCompleteTypeDef;\r
+\r
+\r
+/**\r
+ * @brief HAL DMA Callback ID structure definition\r
+ */\r
+typedef enum\r
+{\r
+ HAL_DMA_XFER_CPLT_CB_ID = 0x00U, /*!< Full transfer */\r
+ HAL_DMA_XFER_HALFCPLT_CB_ID = 0x01U, /*!< Half transfer */\r
+ HAL_DMA_XFER_ERROR_CB_ID = 0x02U, /*!< Error */\r
+ HAL_DMA_XFER_ABORT_CB_ID = 0x03U, /*!< Abort */\r
+ HAL_DMA_XFER_ALL_CB_ID = 0x04U /*!< All */\r
+}HAL_DMA_CallbackIDTypeDef;\r
+\r
+/**\r
+ * @brief DMA handle Structure definition\r
+ */\r
+typedef struct __DMA_HandleTypeDef\r
+{\r
+ DMA_Channel_TypeDef *Instance; /*!< Register base address */\r
+\r
+ DMA_InitTypeDef Init; /*!< DMA communication parameters */\r
+\r
+ HAL_LockTypeDef Lock; /*!< DMA locking object */\r
+\r
+ __IO HAL_DMA_StateTypeDef State; /*!< DMA transfer state */\r
+\r
+ void *Parent; /*!< Parent object state */\r
+\r
+ void (* XferCpltCallback)(struct __DMA_HandleTypeDef * hdma); /*!< DMA transfer complete callback */\r
+\r
+ void (* XferHalfCpltCallback)(struct __DMA_HandleTypeDef * hdma); /*!< DMA Half transfer complete callback */\r
+\r
+ void (* XferErrorCallback)(struct __DMA_HandleTypeDef * hdma); /*!< DMA transfer error callback */\r
+\r
+ void (* XferAbortCallback)(struct __DMA_HandleTypeDef * hdma); /*!< DMA transfer abort callback */\r
+\r
+ __IO uint32_t ErrorCode; /*!< DMA Error code */\r
+\r
+ DMA_TypeDef *DmaBaseAddress; /*!< DMA Channel Base Address */\r
+\r
+ uint32_t ChannelIndex; /*!< DMA Channel Index */\r
+\r
+}DMA_HandleTypeDef;\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/* Exported constants --------------------------------------------------------*/\r
+\r
+/** @defgroup DMA_Exported_Constants DMA Exported Constants\r
+ * @{\r
+ */\r
+\r
+/** @defgroup DMA_Error_Code DMA Error Code\r
+ * @{\r
+ */\r
+#define HAL_DMA_ERROR_NONE 0x00000000U /*!< No error */\r
+#define HAL_DMA_ERROR_TE 0x00000001U /*!< Transfer error */\r
+#define HAL_DMA_ERROR_NO_XFER 0x00000004U /*!< Abort requested with no Xfer ongoing */\r
+#define HAL_DMA_ERROR_TIMEOUT 0x00000020U /*!< Timeout error */\r
+#define HAL_DMA_ERROR_NOT_SUPPORTED 0x00000100U /*!< Not supported mode */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup DMA_Data_transfer_direction DMA Data transfer direction\r
+ * @{\r
+ */\r
+#define DMA_PERIPH_TO_MEMORY 0x00000000U /*!< Peripheral to memory direction */\r
+#define DMA_MEMORY_TO_PERIPH DMA_CCR_DIR /*!< Memory to peripheral direction */\r
+#define DMA_MEMORY_TO_MEMORY DMA_CCR_MEM2MEM /*!< Memory to memory direction */\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup DMA_Peripheral_incremented_mode DMA Peripheral incremented mode\r
+ * @{\r
+ */\r
+#define DMA_PINC_ENABLE DMA_CCR_PINC /*!< Peripheral increment mode Enable */\r
+#define DMA_PINC_DISABLE 0x00000000U /*!< Peripheral increment mode Disable */\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup DMA_Memory_incremented_mode DMA Memory incremented mode\r
+ * @{\r
+ */\r
+#define DMA_MINC_ENABLE DMA_CCR_MINC /*!< Memory increment mode Enable */\r
+#define DMA_MINC_DISABLE 0x00000000U /*!< Memory increment mode Disable */\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup DMA_Peripheral_data_size DMA Peripheral data size\r
+ * @{\r
+ */\r
+#define DMA_PDATAALIGN_BYTE 0x00000000U /*!< Peripheral data alignment : Byte */\r
+#define DMA_PDATAALIGN_HALFWORD DMA_CCR_PSIZE_0 /*!< Peripheral data alignment : HalfWord */\r
+#define DMA_PDATAALIGN_WORD DMA_CCR_PSIZE_1 /*!< Peripheral data alignment : Word */\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup DMA_Memory_data_size DMA Memory data size\r
+ * @{\r
+ */\r
+#define DMA_MDATAALIGN_BYTE 0x00000000U /*!< Memory data alignment : Byte */\r
+#define DMA_MDATAALIGN_HALFWORD DMA_CCR_MSIZE_0 /*!< Memory data alignment : HalfWord */\r
+#define DMA_MDATAALIGN_WORD DMA_CCR_MSIZE_1 /*!< Memory data alignment : Word */\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup DMA_mode DMA mode\r
+ * @{\r
+ */\r
+#define DMA_NORMAL 0x00000000U /*!< Normal mode */\r
+#define DMA_CIRCULAR DMA_CCR_CIRC /*!< Circular mode */\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup DMA_Priority_level DMA Priority level\r
+ * @{\r
+ */\r
+#define DMA_PRIORITY_LOW 0x00000000U /*!< Priority level : Low */\r
+#define DMA_PRIORITY_MEDIUM DMA_CCR_PL_0 /*!< Priority level : Medium */\r
+#define DMA_PRIORITY_HIGH DMA_CCR_PL_1 /*!< Priority level : High */\r
+#define DMA_PRIORITY_VERY_HIGH DMA_CCR_PL /*!< Priority level : Very_High */\r
+/**\r
+ * @}\r
+ */\r
+\r
+\r
+/** @defgroup DMA_interrupt_enable_definitions DMA interrupt enable definitions\r
+ * @{\r
+ */\r
+#define DMA_IT_TC DMA_CCR_TCIE\r
+#define DMA_IT_HT DMA_CCR_HTIE\r
+#define DMA_IT_TE DMA_CCR_TEIE\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup DMA_flag_definitions DMA flag definitions\r
+ * @{\r
+ */\r
+#define DMA_FLAG_GL1 DMA_ISR_GIF1\r
+#define DMA_FLAG_TC1 DMA_ISR_TCIF1\r
+#define DMA_FLAG_HT1 DMA_ISR_HTIF1\r
+#define DMA_FLAG_TE1 DMA_ISR_TEIF1\r
+#define DMA_FLAG_GL2 DMA_ISR_GIF2\r
+#define DMA_FLAG_TC2 DMA_ISR_TCIF2\r
+#define DMA_FLAG_HT2 DMA_ISR_HTIF2\r
+#define DMA_FLAG_TE2 DMA_ISR_TEIF2\r
+#define DMA_FLAG_GL3 DMA_ISR_GIF3\r
+#define DMA_FLAG_TC3 DMA_ISR_TCIF3\r
+#define DMA_FLAG_HT3 DMA_ISR_HTIF3\r
+#define DMA_FLAG_TE3 DMA_ISR_TEIF3\r
+#define DMA_FLAG_GL4 DMA_ISR_GIF4\r
+#define DMA_FLAG_TC4 DMA_ISR_TCIF4\r
+#define DMA_FLAG_HT4 DMA_ISR_HTIF4\r
+#define DMA_FLAG_TE4 DMA_ISR_TEIF4\r
+#define DMA_FLAG_GL5 DMA_ISR_GIF5\r
+#define DMA_FLAG_TC5 DMA_ISR_TCIF5\r
+#define DMA_FLAG_HT5 DMA_ISR_HTIF5\r
+#define DMA_FLAG_TE5 DMA_ISR_TEIF5\r
+#define DMA_FLAG_GL6 DMA_ISR_GIF6\r
+#define DMA_FLAG_TC6 DMA_ISR_TCIF6\r
+#define DMA_FLAG_HT6 DMA_ISR_HTIF6\r
+#define DMA_FLAG_TE6 DMA_ISR_TEIF6\r
+#define DMA_FLAG_GL7 DMA_ISR_GIF7\r
+#define DMA_FLAG_TC7 DMA_ISR_TCIF7\r
+#define DMA_FLAG_HT7 DMA_ISR_HTIF7\r
+#define DMA_FLAG_TE7 DMA_ISR_TEIF7\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/* Exported macros -----------------------------------------------------------*/\r
+/** @defgroup DMA_Exported_Macros DMA Exported Macros\r
+ * @{\r
+ */\r
+\r
+/** @brief Reset DMA handle state.\r
+ * @param __HANDLE__ DMA handle\r
+ * @retval None\r
+ */\r
+#define __HAL_DMA_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_DMA_STATE_RESET)\r
+\r
+/**\r
+ * @brief Enable the specified DMA Channel.\r
+ * @param __HANDLE__ DMA handle\r
+ * @retval None\r
+ */\r
+#define __HAL_DMA_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CCR |= DMA_CCR_EN)\r
+\r
+/**\r
+ * @brief Disable the specified DMA Channel.\r
+ * @param __HANDLE__ DMA handle\r
+ * @retval None\r
+ */\r
+#define __HAL_DMA_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CCR &= ~DMA_CCR_EN)\r
+\r
+\r
+/* Interrupt & Flag management */\r
+#if defined(STM32L100xC) || defined (STM32L151xC) || defined (STM32L152xC) || defined (STM32L162xC) || \\r
+ defined(STM32L151xCA) || defined (STM32L151xD) || defined (STM32L152xCA) || defined (STM32L152xD) || defined (STM32L162xCA) || defined (STM32L162xD) || \\r
+ defined(STM32L151xE) || defined(STM32L151xDX) || defined (STM32L152xE) || defined (STM32L152xDX) || defined (STM32L162xE) || defined (STM32L162xDX)\r
+\r
+/**\r
+ * @brief Return the current DMA Channel transfer complete flag.\r
+ * @param __HANDLE__ DMA handle\r
+ * @retval The specified transfer complete flag index.\r
+ */\r
+\r
+#define __HAL_DMA_GET_TC_FLAG_INDEX(__HANDLE__) \\r
+(((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1))? DMA_FLAG_TC1 :\\r
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel1))? DMA_FLAG_TC1 :\\r
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel2))? DMA_FLAG_TC2 :\\r
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel2))? DMA_FLAG_TC2 :\\r
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel3))? DMA_FLAG_TC3 :\\r
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel3))? DMA_FLAG_TC3 :\\r
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel4))? DMA_FLAG_TC4 :\\r
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel4))? DMA_FLAG_TC4 :\\r
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel5))? DMA_FLAG_TC5 :\\r
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel5))? DMA_FLAG_TC5 :\\r
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel6))? DMA_FLAG_TC6 :\\r
+ DMA_FLAG_TC7)\r
+\r
+/**\r
+ * @brief Return the current DMA Channel half transfer complete flag.\r
+ * @param __HANDLE__ DMA handle\r
+ * @retval The specified half transfer complete flag index.\r
+ */\r
+#define __HAL_DMA_GET_HT_FLAG_INDEX(__HANDLE__)\\r
+(((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1))? DMA_FLAG_HT1 :\\r
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel1))? DMA_FLAG_HT1 :\\r
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel2))? DMA_FLAG_HT2 :\\r
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel2))? DMA_FLAG_HT2 :\\r
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel3))? DMA_FLAG_HT3 :\\r
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel3))? DMA_FLAG_HT3 :\\r
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel4))? DMA_FLAG_HT4 :\\r
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel4))? DMA_FLAG_HT4 :\\r
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel5))? DMA_FLAG_HT5 :\\r
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel5))? DMA_FLAG_HT5 :\\r
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel6))? DMA_FLAG_HT6 :\\r
+ DMA_FLAG_HT7)\r
+\r
+/**\r
+ * @brief Return the current DMA Channel transfer error flag.\r
+ * @param __HANDLE__ DMA handle\r
+ * @retval The specified transfer error flag index.\r
+ */\r
+#define __HAL_DMA_GET_TE_FLAG_INDEX(__HANDLE__)\\r
+(((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1))? DMA_FLAG_TE1 :\\r
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel1))? DMA_FLAG_TE1 :\\r
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel2))? DMA_FLAG_TE2 :\\r
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel2))? DMA_FLAG_TE2 :\\r
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel3))? DMA_FLAG_TE3 :\\r
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel3))? DMA_FLAG_TE3 :\\r
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel4))? DMA_FLAG_TE4 :\\r
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel4))? DMA_FLAG_TE4 :\\r
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel5))? DMA_FLAG_TE5 :\\r
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel5))? DMA_FLAG_TE5 :\\r
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel6))? DMA_FLAG_TE6 :\\r
+ DMA_FLAG_TE7)\r
+\r
+/**\r
+ * @brief Return the current DMA Channel Global interrupt flag.\r
+ * @param __HANDLE__ DMA handle\r
+ * @retval The specified transfer error flag index.\r
+ */\r
+#define __HAL_DMA_GET_GI_FLAG_INDEX(__HANDLE__)\\r
+(((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1))? DMA_ISR_GIF1 :\\r
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel1))? DMA_ISR_GIF1 :\\r
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel2))? DMA_ISR_GIF2 :\\r
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel2))? DMA_ISR_GIF2 :\\r
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel3))? DMA_ISR_GIF3 :\\r
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel3))? DMA_ISR_GIF3 :\\r
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel4))? DMA_ISR_GIF4 :\\r
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel4))? DMA_ISR_GIF4 :\\r
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel5))? DMA_ISR_GIF5 :\\r
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel5))? DMA_ISR_GIF5 :\\r
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel6))? DMA_ISR_GIF6 :\\r
+ DMA_ISR_GIF7)\r
+\r
+/**\r
+ * @brief Get the DMA Channel pending flags.\r
+ * @param __HANDLE__ DMA handle\r
+ * @param __FLAG__ Get the specified flag.\r
+ * This parameter can be any combination of the following values:\r
+ * @arg DMA_FLAG_TCx: Transfer complete flag\r
+ * @arg DMA_FLAG_HTx: Half transfer complete flag\r
+ * @arg DMA_FLAG_TEx: Transfer error flag\r
+ * @arg DMA_FLAG_GLx: Global interrupt flag\r
+ * Where x can be from 1 to 7 to select the DMA Channel x flag.\r
+ * @retval The state of FLAG (SET or RESET).\r
+ */\r
+#define __HAL_DMA_GET_FLAG(__HANDLE__, __FLAG__) (((uint32_t)((__HANDLE__)->Instance) > ((uint32_t)DMA1_Channel7))? \\r
+ (DMA2->ISR & (__FLAG__)) : (DMA1->ISR & (__FLAG__)))\r
+\r
+/**\r
+ * @brief Clear the DMA Channel pending flags.\r
+ * @param __HANDLE__ DMA handle\r
+ * @param __FLAG__ specifies the flag to clear.\r
+ * This parameter can be any combination of the following values:\r
+ * @arg DMA_FLAG_TCx: Transfer complete flag\r
+ * @arg DMA_FLAG_HTx: Half transfer complete flag\r
+ * @arg DMA_FLAG_TEx: Transfer error flag\r
+ * @arg DMA_FLAG_GLx: Global interrupt flag\r
+ * Where x can be from 1 to 7 to select the DMA Channel x flag.\r
+ * @retval None\r
+ */\r
+#define __HAL_DMA_CLEAR_FLAG(__HANDLE__, __FLAG__) (((uint32_t)((__HANDLE__)->Instance) > ((uint32_t)DMA1_Channel7))? \\r
+(DMA2->IFCR = (__FLAG__)) : (DMA1->IFCR = (__FLAG__)))\r
+\r
+#else\r
+/**\r
+ * @brief Return the current DMA Channel transfer complete flag.\r
+ * @param __HANDLE__ DMA handle\r
+ * @retval The specified transfer complete flag index.\r
+ */\r
+\r
+#define __HAL_DMA_GET_TC_FLAG_INDEX(__HANDLE__) \\r
+(((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1))? DMA_FLAG_TC1 :\\r
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel2))? DMA_FLAG_TC2 :\\r
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel3))? DMA_FLAG_TC3 :\\r
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel4))? DMA_FLAG_TC4 :\\r
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel5))? DMA_FLAG_TC5 :\\r
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel6))? DMA_FLAG_TC6 :\\r
+ DMA_FLAG_TC7)\r
+\r
+/**\r
+ * @brief Return the current DMA Channel half transfer complete flag.\r
+ * @param __HANDLE__ DMA handle\r
+ * @retval The specified half transfer complete flag index.\r
+ */\r
+#define __HAL_DMA_GET_HT_FLAG_INDEX(__HANDLE__)\\r
+(((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1))? DMA_FLAG_HT1 :\\r
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel2))? DMA_FLAG_HT2 :\\r
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel3))? DMA_FLAG_HT3 :\\r
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel4))? DMA_FLAG_HT4 :\\r
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel5))? DMA_FLAG_HT5 :\\r
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel6))? DMA_FLAG_HT6 :\\r
+ DMA_FLAG_HT7)\r
+\r
+/**\r
+ * @brief Return the current DMA Channel transfer error flag.\r
+ * @param __HANDLE__ DMA handle\r
+ * @retval The specified transfer error flag index.\r
+ */\r
+#define __HAL_DMA_GET_TE_FLAG_INDEX(__HANDLE__)\\r
+(((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1))? DMA_FLAG_TE1 :\\r
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel2))? DMA_FLAG_TE2 :\\r
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel3))? DMA_FLAG_TE3 :\\r
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel4))? DMA_FLAG_TE4 :\\r
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel5))? DMA_FLAG_TE5 :\\r
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel6))? DMA_FLAG_TE6 :\\r
+ DMA_FLAG_TE7)\r
+\r
+/**\r
+ * @brief Return the current DMA Channel Global interrupt flag.\r
+ * @param __HANDLE__ DMA handle\r
+ * @retval The specified transfer error flag index.\r
+ */\r
+#define __HAL_DMA_GET_GI_FLAG_INDEX(__HANDLE__)\\r
+(((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1))? DMA_ISR_GIF1 :\\r
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel2))? DMA_ISR_GIF2 :\\r
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel3))? DMA_ISR_GIF3 :\\r
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel4))? DMA_ISR_GIF4 :\\r
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel5))? DMA_ISR_GIF5 :\\r
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel6))? DMA_ISR_GIF6 :\\r
+ DMA_ISR_GIF7)\r
+\r
+/**\r
+ * @brief Get the DMA Channel pending flags.\r
+ * @param __HANDLE__ DMA handle\r
+ * @param __FLAG__ Get the specified flag.\r
+ * This parameter can be any combination of the following values:\r
+ * @arg DMA_FLAG_TCIFx: Transfer complete flag\r
+ * @arg DMA_FLAG_HTIFx: Half transfer complete flag\r
+ * @arg DMA_FLAG_TEIFx: Transfer error flag\r
+ * @arg DMA_ISR_GIFx: Global interrupt flag\r
+ * Where x can be from 1 to 7 to select the DMA Channel x flag.\r
+ * @retval The state of FLAG (SET or RESET).\r
+ */\r
+#define __HAL_DMA_GET_FLAG(__HANDLE__, __FLAG__) (DMA1->ISR & (__FLAG__))\r
+\r
+/**\r
+ * @brief Clear the DMA Channel pending flags.\r
+ * @param __HANDLE__ DMA handle\r
+ * @param __FLAG__ specifies the flag to clear.\r
+ * This parameter can be any combination of the following values:\r
+ * @arg DMA_FLAG_TCx: Transfer complete flag\r
+ * @arg DMA_FLAG_HTx: Half transfer complete flag\r
+ * @arg DMA_FLAG_TEx: Transfer error flag\r
+ * @arg DMA_FLAG_GLx: Global interrupt flag\r
+ * Where x can be from 1 to 7 to select the DMA Channel x flag.\r
+ * @retval None\r
+ */\r
+#define __HAL_DMA_CLEAR_FLAG(__HANDLE__, __FLAG__) (DMA1->IFCR = (__FLAG__))\r
+\r
+#endif /* STM32L100xC || STM32L151xC || STM32L152xC || STM32L162xC || STM32L151xCA) || defined (STM32L151xD) || defined (STM32L152xCA) || defined (STM32L152xD) || defined (STM32L162xCA) || defined (STM32L162xD) || STM32L151xE || STM32L151xDX || STM32L152xE || STM32L152xDX || STM32L162xE || STM32L162xDX */\r
+\r
+/**\r
+ * @brief Enable the specified DMA Channel interrupts.\r
+ * @param __HANDLE__ DMA handle\r
+ * @param __INTERRUPT__ specifies the DMA interrupt sources to be enabled or disabled.\r
+ * This parameter can be any combination of the following values:\r
+ * @arg DMA_IT_TC: Transfer complete interrupt mask\r
+ * @arg DMA_IT_HT: Half transfer complete interrupt mask\r
+ * @arg DMA_IT_TE: Transfer error interrupt mask\r
+ * @retval None\r
+ */\r
+#define __HAL_DMA_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CCR |= (__INTERRUPT__))\r
+\r
+/**\r
+ * @brief Disable the specified DMA Channel interrupts.\r
+ * @param __HANDLE__ DMA handle\r
+ * @param __INTERRUPT__ specifies the DMA interrupt sources to be enabled or disabled.\r
+ * This parameter can be any combination of the following values:\r
+ * @arg DMA_IT_TC: Transfer complete interrupt mask\r
+ * @arg DMA_IT_HT: Half transfer complete interrupt mask\r
+ * @arg DMA_IT_TE: Transfer error interrupt mask\r
+ * @retval None\r
+ */\r
+#define __HAL_DMA_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CCR &= ~(__INTERRUPT__))\r
+\r
+/**\r
+ * @brief Check whether the specified DMA Channel interrupt is enabled or not.\r
+ * @param __HANDLE__ DMA handle\r
+ * @param __INTERRUPT__ specifies the DMA interrupt source to check.\r
+ * This parameter can be one of the following values:\r
+ * @arg DMA_IT_TC: Transfer complete interrupt mask\r
+ * @arg DMA_IT_HT: Half transfer complete interrupt mask\r
+ * @arg DMA_IT_TE: Transfer error interrupt mask\r
+ * @retval The state of DMA_IT (SET or RESET).\r
+ */\r
+#define __HAL_DMA_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->CCR & (__INTERRUPT__)))\r
+\r
+/**\r
+ * @brief Return the number of remaining data units in the current DMA Channel transfer.\r
+ * @param __HANDLE__ DMA handle\r
+ * @retval The number of remaining data units in the current DMA Channel transfer.\r
+ */\r
+#define __HAL_DMA_GET_COUNTER(__HANDLE__) ((__HANDLE__)->Instance->CNDTR)\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/* Exported functions --------------------------------------------------------*/\r
+\r
+/** @addtogroup DMA_Exported_Functions\r
+ * @{\r
+ */\r
+\r
+/** @addtogroup DMA_Exported_Functions_Group1\r
+ * @{\r
+ */\r
+/* Initialization and de-initialization functions *****************************/\r
+HAL_StatusTypeDef HAL_DMA_Init(DMA_HandleTypeDef *hdma);\r
+HAL_StatusTypeDef HAL_DMA_DeInit (DMA_HandleTypeDef *hdma);\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @addtogroup DMA_Exported_Functions_Group2\r
+ * @{\r
+ */\r
+/* IO operation functions *****************************************************/\r
+HAL_StatusTypeDef HAL_DMA_Start (DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength);\r
+HAL_StatusTypeDef HAL_DMA_Start_IT(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength);\r
+HAL_StatusTypeDef HAL_DMA_Abort(DMA_HandleTypeDef *hdma);\r
+HAL_StatusTypeDef HAL_DMA_Abort_IT(DMA_HandleTypeDef *hdma);\r
+HAL_StatusTypeDef HAL_DMA_PollForTransfer(DMA_HandleTypeDef *hdma, HAL_DMA_LevelCompleteTypeDef CompleteLevel, uint32_t Timeout);\r
+void HAL_DMA_IRQHandler(DMA_HandleTypeDef *hdma);\r
+HAL_StatusTypeDef HAL_DMA_RegisterCallback(DMA_HandleTypeDef *hdma, HAL_DMA_CallbackIDTypeDef CallbackID, void (* pCallback)( DMA_HandleTypeDef * _hdma));\r
+HAL_StatusTypeDef HAL_DMA_UnRegisterCallback(DMA_HandleTypeDef *hdma, HAL_DMA_CallbackIDTypeDef CallbackID);\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @addtogroup DMA_Exported_Functions_Group3\r
+ * @{\r
+ */\r
+/* Peripheral State and Error functions ***************************************/\r
+HAL_DMA_StateTypeDef HAL_DMA_GetState(DMA_HandleTypeDef *hdma);\r
+uint32_t HAL_DMA_GetError(DMA_HandleTypeDef *hdma);\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/* Private macros ------------------------------------------------------------*/\r
+/** @defgroup DMA_Private_Macros DMA Private Macros\r
+ * @{\r
+ */\r
+\r
+#define IS_DMA_DIRECTION(DIRECTION) (((DIRECTION) == DMA_PERIPH_TO_MEMORY ) || \\r
+ ((DIRECTION) == DMA_MEMORY_TO_PERIPH) || \\r
+ ((DIRECTION) == DMA_MEMORY_TO_MEMORY))\r
+\r
+#define IS_DMA_BUFFER_SIZE(SIZE) (((SIZE) >= 0x1U) && ((SIZE) < 0x10000U))\r
+\r
+#define IS_DMA_PERIPHERAL_INC_STATE(STATE) (((STATE) == DMA_PINC_ENABLE) || \\r
+ ((STATE) == DMA_PINC_DISABLE))\r
+\r
+#define IS_DMA_MEMORY_INC_STATE(STATE) (((STATE) == DMA_MINC_ENABLE) || \\r
+ ((STATE) == DMA_MINC_DISABLE))\r
+\r
+#define IS_DMA_PERIPHERAL_DATA_SIZE(SIZE) (((SIZE) == DMA_PDATAALIGN_BYTE) || \\r
+ ((SIZE) == DMA_PDATAALIGN_HALFWORD) || \\r
+ ((SIZE) == DMA_PDATAALIGN_WORD))\r
+\r
+#define IS_DMA_MEMORY_DATA_SIZE(SIZE) (((SIZE) == DMA_MDATAALIGN_BYTE) || \\r
+ ((SIZE) == DMA_MDATAALIGN_HALFWORD) || \\r
+ ((SIZE) == DMA_MDATAALIGN_WORD ))\r
+\r
+#define IS_DMA_MODE(MODE) (((MODE) == DMA_NORMAL ) || \\r
+ ((MODE) == DMA_CIRCULAR))\r
+\r
+#define IS_DMA_PRIORITY(PRIORITY) (((PRIORITY) == DMA_PRIORITY_LOW ) || \\r
+ ((PRIORITY) == DMA_PRIORITY_MEDIUM) || \\r
+ ((PRIORITY) == DMA_PRIORITY_HIGH) || \\r
+ ((PRIORITY) == DMA_PRIORITY_VERY_HIGH))\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/* Private functions ---------------------------------------------------------*/\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+#ifdef __cplusplus\r
+}\r
+#endif\r
+\r
+#endif /* STM32L1xx_HAL_DMA_H */\r
+\r
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\r
--- /dev/null
+/**\r
+ ******************************************************************************\r
+ * @file stm32l1xx_hal_flash.h\r
+ * @author MCD Application Team\r
+ * @brief Header file of Flash HAL module.\r
+ ******************************************************************************\r
+ * @attention\r
+ *\r
+ * <h2><center>© Copyright (c) 2017 STMicroelectronics.\r
+ * All rights reserved.</center></h2>\r
+ *\r
+ * This software component is licensed by ST under BSD 3-Clause license,\r
+ * the "License"; You may not use this file except in compliance with the\r
+ * License. You may obtain a copy of the License at:\r
+ * opensource.org/licenses/BSD-3-Clause\r
+ *\r
+ ******************************************************************************\r
+ */\r
+\r
+/* Define to prevent recursive inclusion -------------------------------------*/\r
+#ifndef __STM32L1xx_HAL_FLASH_H\r
+#define __STM32L1xx_HAL_FLASH_H\r
+\r
+#ifdef __cplusplus\r
+ extern "C" {\r
+#endif\r
+\r
+/* Includes ------------------------------------------------------------------*/\r
+#include "stm32l1xx_hal_def.h"\r
+ \r
+/** @addtogroup STM32L1xx_HAL_Driver\r
+ * @{\r
+ */\r
+\r
+/** @addtogroup FLASH\r
+ * @{\r
+ */\r
+ \r
+/** @addtogroup FLASH_Private_Constants\r
+ * @{\r
+ */\r
+#define FLASH_TIMEOUT_VALUE (50000U) /* 50 s */\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @addtogroup FLASH_Private_Macros\r
+ * @{\r
+ */\r
+\r
+#define IS_FLASH_TYPEPROGRAM(_VALUE_) ((_VALUE_) == FLASH_TYPEPROGRAM_WORD)\r
+\r
+#define IS_FLASH_LATENCY(__LATENCY__) (((__LATENCY__) == FLASH_LATENCY_0) || \\r
+ ((__LATENCY__) == FLASH_LATENCY_1))\r
+\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/* Exported types ------------------------------------------------------------*/ \r
+/** @defgroup FLASH_Exported_Types FLASH Exported Types\r
+ * @{\r
+ */ \r
+\r
+/**\r
+ * @brief FLASH Procedure structure definition\r
+ */\r
+typedef enum \r
+{\r
+ FLASH_PROC_NONE = 0U, \r
+ FLASH_PROC_PAGEERASE = 1U,\r
+ FLASH_PROC_PROGRAM = 2U,\r
+} FLASH_ProcedureTypeDef;\r
+\r
+/** \r
+ * @brief FLASH handle Structure definition \r
+ */\r
+typedef struct\r
+{\r
+ __IO FLASH_ProcedureTypeDef ProcedureOnGoing; /*!< Internal variable to indicate which procedure is ongoing or not in IT context */\r
+ \r
+ __IO uint32_t NbPagesToErase; /*!< Internal variable to save the remaining sectors to erase in IT context*/\r
+\r
+ __IO uint32_t Address; /*!< Internal variable to save address selected for program or erase */\r
+\r
+ __IO uint32_t Page; /*!< Internal variable to define the current page which is erasing */\r
+\r
+ HAL_LockTypeDef Lock; /*!< FLASH locking object */\r
+\r
+ __IO uint32_t ErrorCode; /*!< FLASH error code \r
+ This parameter can be a value of @ref FLASH_Error_Codes */\r
+} FLASH_ProcessTypeDef;\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/* Exported constants --------------------------------------------------------*/\r
+/** @defgroup FLASH_Exported_Constants FLASH Exported Constants\r
+ * @{\r
+ */ \r
+\r
+/** @defgroup FLASH_Error_Codes FLASH Error Codes\r
+ * @{\r
+ */\r
+\r
+#define HAL_FLASH_ERROR_NONE 0x00U /*!< No error */\r
+#define HAL_FLASH_ERROR_PGA 0x01U /*!< Programming alignment error */\r
+#define HAL_FLASH_ERROR_WRP 0x02U /*!< Write protection error */\r
+#define HAL_FLASH_ERROR_OPTV 0x04U /*!< Option validity error */\r
+#define HAL_FLASH_ERROR_SIZE 0x08U /*!< */\r
+#define HAL_FLASH_ERROR_RD 0x10U /*!< Read protected error */\r
+#define HAL_FLASH_ERROR_OPTVUSR 0x20U /*!< Option UserValidity Error. */\r
+#define HAL_FLASH_ERROR_OPERATION 0x40U /*!< Not used */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup FLASH_Page_Size FLASH size information\r
+ * @{\r
+ */ \r
+\r
+#define FLASH_SIZE (uint32_t)((*((uint32_t *)FLASHSIZE_BASE)&0xFFFFU) * 1024U)\r
+#define FLASH_PAGE_SIZE (256U) /*!< FLASH Page Size in bytes */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup FLASH_Type_Program FLASH Type Program\r
+ * @{\r
+ */ \r
+#define FLASH_TYPEPROGRAM_WORD (0x02U) /*!<Program a word (32-bit) at a specified address.*/\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup FLASH_Latency FLASH Latency\r
+ * @{\r
+ */ \r
+#define FLASH_LATENCY_0 (0x00000000U) /*!< FLASH Zero Latency cycle */\r
+#define FLASH_LATENCY_1 FLASH_ACR_LATENCY /*!< FLASH One Latency cycle */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup FLASH_Interrupts FLASH Interrupts \r
+ * @{\r
+ */\r
+\r
+#define FLASH_IT_EOP FLASH_PECR_EOPIE /*!< End of programming interrupt source */\r
+#define FLASH_IT_ERR FLASH_PECR_ERRIE /*!< Error interrupt source */\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/** @defgroup FLASH_Flags FLASH Flags \r
+ * @{\r
+ */ \r
+\r
+#define FLASH_FLAG_BSY FLASH_SR_BSY /*!< FLASH Busy flag */\r
+#define FLASH_FLAG_EOP FLASH_SR_EOP /*!< FLASH End of Programming flag */\r
+#define FLASH_FLAG_ENDHV FLASH_SR_ENDHV /*!< FLASH End of High Voltage flag */\r
+#define FLASH_FLAG_READY FLASH_SR_READY /*!< FLASH Ready flag after low power mode */\r
+#define FLASH_FLAG_WRPERR FLASH_SR_WRPERR /*!< FLASH Write protected error flag */\r
+#define FLASH_FLAG_PGAERR FLASH_SR_PGAERR /*!< FLASH Programming Alignment error flag */\r
+#define FLASH_FLAG_SIZERR FLASH_SR_SIZERR /*!< FLASH Size error flag */\r
+#define FLASH_FLAG_OPTVERR FLASH_SR_OPTVERR /*!< FLASH Option Validity error flag */\r
+/* Cat2 & Cat3*/\r
+#if defined(FLASH_SR_RDERR)\r
+#define FLASH_FLAG_RDERR FLASH_SR_RDERR /*!< Read protected error flag */\r
+#endif /* FLASH_SR_RDERR */\r
+/* Cat3, Cat4 & Cat5*/\r
+#if defined(FLASH_SR_OPTVERRUSR)\r
+#define FLASH_FLAG_OPTVERRUSR FLASH_SR_OPTVERRUSR /*!< FLASH Option User Validity error flag */\r
+#endif /* FLASH_SR_OPTVERRUSR */\r
+\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/** @defgroup FLASH_Keys FLASH Keys \r
+ * @{\r
+ */ \r
+\r
+#define FLASH_PDKEY1 (0x04152637U) /*!< Flash power down key1 */\r
+#define FLASH_PDKEY2 (0xFAFBFCFDU) /*!< Flash power down key2: used with FLASH_PDKEY1 \r
+ to unlock the RUN_PD bit in FLASH_ACR */\r
+\r
+#define FLASH_PEKEY1 (0x89ABCDEFU) /*!< Flash program erase key1 */\r
+#define FLASH_PEKEY2 (0x02030405U) /*!< Flash program erase key: used with FLASH_PEKEY2\r
+ to unlock the write access to the FLASH_PECR register and\r
+ data EEPROM */\r
+\r
+#define FLASH_PRGKEY1 (0x8C9DAEBFU) /*!< Flash program memory key1 */\r
+#define FLASH_PRGKEY2 (0x13141516U) /*!< Flash program memory key2: used with FLASH_PRGKEY2\r
+ to unlock the program memory */\r
+\r
+#define FLASH_OPTKEY1 (0xFBEAD9C8U) /*!< Flash option key1 */\r
+#define FLASH_OPTKEY2 (0x24252627U) /*!< Flash option key2: used with FLASH_OPTKEY1 to\r
+ unlock the write access to the option byte block */\r
+/**\r
+ * @}\r
+ */\r
+/**\r
+ * @}\r
+ */ \r
+ \r
+/* Exported macro ------------------------------------------------------------*/\r
+\r
+/** @defgroup FLASH_Exported_Macros FLASH Exported Macros\r
+ * @brief macros to control FLASH features \r
+ * @{\r
+ */\r
+ \r
+\r
+/** @defgroup FLASH_Interrupt FLASH Interrupts\r
+ * @brief macros to handle FLASH interrupts\r
+ * @{\r
+ */ \r
+\r
+/**\r
+ * @brief Enable the specified FLASH interrupt.\r
+ * @param __INTERRUPT__ FLASH interrupt \r
+ * This parameter can be any combination of the following values:\r
+ * @arg @ref FLASH_IT_EOP End of FLASH Operation Interrupt\r
+ * @arg @ref FLASH_IT_ERR Error Interrupt \r
+ * @retval none\r
+ */ \r
+#define __HAL_FLASH_ENABLE_IT(__INTERRUPT__) SET_BIT((FLASH->PECR), (__INTERRUPT__))\r
+\r
+/**\r
+ * @brief Disable the specified FLASH interrupt.\r
+ * @param __INTERRUPT__ FLASH interrupt \r
+ * This parameter can be any combination of the following values:\r
+ * @arg @ref FLASH_IT_EOP End of FLASH Operation Interrupt\r
+ * @arg @ref FLASH_IT_ERR Error Interrupt \r
+ * @retval none\r
+ */ \r
+#define __HAL_FLASH_DISABLE_IT(__INTERRUPT__) CLEAR_BIT((FLASH->PECR), (uint32_t)(__INTERRUPT__))\r
+\r
+/**\r
+ * @brief Get the specified FLASH flag status. \r
+ * @param __FLAG__ specifies the FLASH flag to check.\r
+ * This parameter can be one of the following values:\r
+ * @arg @ref FLASH_FLAG_BSY FLASH Busy flag\r
+ * @arg @ref FLASH_FLAG_EOP FLASH End of Operation flag \r
+ * @arg @ref FLASH_FLAG_ENDHV FLASH End of High Voltage flag\r
+ * @arg @ref FLASH_FLAG_READY FLASH Ready flag after low power mode\r
+ * @arg @ref FLASH_FLAG_PGAERR FLASH Programming Alignment error flag\r
+ * @arg @ref FLASH_FLAG_SIZERR FLASH Size error flag\r
+ * @arg @ref FLASH_FLAG_OPTVERR FLASH Option validity error error flag\r
+@if STM32L100xB\r
+@elif STM32L100xBA\r
+ * @arg @ref FLASH_FLAG_RDERR FLASH Read Protection error flag (PCROP)\r
+@elif STM32L151xB\r
+@elif STM32L151xBA\r
+ * @arg @ref FLASH_FLAG_RDERR FLASH Read Protection error flag (PCROP)\r
+@elif STM32L152xB\r
+@elif STM32L152xBA\r
+ * @arg @ref FLASH_FLAG_RDERR FLASH Read Protection error flag (PCROP)\r
+@elif STM32L100xC\r
+ * @arg @ref FLASH_FLAG_RDERR FLASH Read Protection error flag (PCROP)\r
+ * @arg @ref FLASH_FLAG_OPTVERRUSR FLASH Option User validity error\r
+@elif STM32L151xC\r
+ * @arg @ref FLASH_FLAG_RDERR FLASH Read Protection error flag (PCROP)\r
+ * @arg @ref FLASH_FLAG_OPTVERRUSR FLASH Option User validity error\r
+@elif STM32L152xC\r
+ * @arg @ref FLASH_FLAG_RDERR FLASH Read Protection error flag (PCROP)\r
+ * @arg @ref FLASH_FLAG_OPTVERRUSR FLASH Option User validity error\r
+@elif STM32L162xC\r
+ * @arg @ref FLASH_FLAG_RDERR FLASH Read Protection error flag (PCROP)\r
+ * @arg @ref FLASH_FLAG_OPTVERRUSR FLASH Option User validity error\r
+@else\r
+ * @arg @ref FLASH_FLAG_OPTVERRUSR FLASH Option User validity error\r
+@endif\r
+ * @arg @ref FLASH_FLAG_WRPERR FLASH Write protected error flag \r
+ * @retval The new state of __FLAG__ (SET or RESET).\r
+ */\r
+#define __HAL_FLASH_GET_FLAG(__FLAG__) (((FLASH->SR) & (__FLAG__)) == (__FLAG__))\r
+\r
+/**\r
+ * @brief Clear the specified FLASH flag.\r
+ * @param __FLAG__ specifies the FLASH flags to clear.\r
+ * This parameter can be any combination of the following values:\r
+ * @arg @ref FLASH_FLAG_EOP FLASH End of Operation flag \r
+ * @arg @ref FLASH_FLAG_PGAERR FLASH Programming Alignment error flag\r
+ * @arg @ref FLASH_FLAG_SIZERR FLASH Size error flag\r
+ * @arg @ref FLASH_FLAG_OPTVERR FLASH Option validity error error flag\r
+@if STM32L100xB\r
+@elif STM32L100xBA\r
+ * @arg @ref FLASH_FLAG_RDERR FLASH Read Protection error flag (PCROP)\r
+@elif STM32L151xB\r
+@elif STM32L151xBA\r
+ * @arg @ref FLASH_FLAG_RDERR FLASH Read Protection error flag (PCROP)\r
+@elif STM32L152xB\r
+@elif STM32L152xBA\r
+ * @arg @ref FLASH_FLAG_RDERR FLASH Read Protection error flag (PCROP)\r
+@elif STM32L100xC\r
+ * @arg @ref FLASH_FLAG_RDERR FLASH Read Protection error flag (PCROP)\r
+ * @arg @ref FLASH_FLAG_OPTVERRUSR FLASH Option User validity error\r
+@elif STM32L151xC\r
+ * @arg @ref FLASH_FLAG_RDERR FLASH Read Protection error flag (PCROP)\r
+ * @arg @ref FLASH_FLAG_OPTVERRUSR FLASH Option User validity error\r
+@elif STM32L152xC\r
+ * @arg @ref FLASH_FLAG_RDERR FLASH Read Protection error flag (PCROP)\r
+ * @arg @ref FLASH_FLAG_OPTVERRUSR FLASH Option User validity error\r
+@elif STM32L162xC\r
+ * @arg @ref FLASH_FLAG_RDERR FLASH Read Protection error flag (PCROP)\r
+ * @arg @ref FLASH_FLAG_OPTVERRUSR FLASH Option User validity error\r
+@else\r
+ * @arg @ref FLASH_FLAG_OPTVERRUSR FLASH Option User validity error\r
+@endif\r
+ * @arg @ref FLASH_FLAG_WRPERR FLASH Write protected error flag \r
+ * @retval none\r
+ */\r
+#define __HAL_FLASH_CLEAR_FLAG(__FLAG__) ((FLASH->SR) = (__FLAG__))\r
+\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/* Include FLASH HAL Extended module */\r
+#include "stm32l1xx_hal_flash_ex.h" \r
+#include "stm32l1xx_hal_flash_ramfunc.h" \r
+\r
+/* Exported functions --------------------------------------------------------*/\r
+/** @addtogroup FLASH_Exported_Functions\r
+ * @{\r
+ */\r
+ \r
+/** @addtogroup FLASH_Exported_Functions_Group1\r
+ * @{\r
+ */\r
+/* IO operation functions *****************************************************/\r
+HAL_StatusTypeDef HAL_FLASH_Program(uint32_t TypeProgram, uint32_t Address, uint32_t Data);\r
+HAL_StatusTypeDef HAL_FLASH_Program_IT(uint32_t TypeProgram, uint32_t Address, uint32_t Data);\r
+\r
+/* FLASH IRQ handler function */\r
+void HAL_FLASH_IRQHandler(void);\r
+/* Callbacks in non blocking modes */ \r
+void HAL_FLASH_EndOfOperationCallback(uint32_t ReturnValue);\r
+void HAL_FLASH_OperationErrorCallback(uint32_t ReturnValue);\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @addtogroup FLASH_Exported_Functions_Group2\r
+ * @{\r
+ */\r
+/* Peripheral Control functions ***********************************************/\r
+HAL_StatusTypeDef HAL_FLASH_Unlock(void);\r
+HAL_StatusTypeDef HAL_FLASH_Lock(void);\r
+HAL_StatusTypeDef HAL_FLASH_OB_Unlock(void);\r
+HAL_StatusTypeDef HAL_FLASH_OB_Lock(void);\r
+HAL_StatusTypeDef HAL_FLASH_OB_Launch(void);\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @addtogroup FLASH_Exported_Functions_Group3\r
+ * @{\r
+ */\r
+/* Peripheral State and Error functions ***************************************/\r
+uint32_t HAL_FLASH_GetError(void);\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/* Private function -------------------------------------------------*/\r
+/** @addtogroup FLASH_Private_Functions\r
+ * @{\r
+ */\r
+HAL_StatusTypeDef FLASH_WaitForLastOperation(uint32_t Timeout);\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+#ifdef __cplusplus\r
+}\r
+#endif\r
+\r
+#endif /* __STM32L1xx_HAL_FLASH_H */\r
+\r
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\r
+\r
--- /dev/null
+/**\r
+ ******************************************************************************\r
+ * @file stm32l1xx_hal_flash_ex.h\r
+ * @author MCD Application Team\r
+ * @brief Header file of Flash HAL Extended module.\r
+ ******************************************************************************\r
+ * @attention\r
+ *\r
+ * <h2><center>© Copyright (c) 2017 STMicroelectronics.\r
+ * All rights reserved.</center></h2>\r
+ *\r
+ * This software component is licensed by ST under BSD 3-Clause license,\r
+ * the "License"; You may not use this file except in compliance with the\r
+ * License. You may obtain a copy of the License at:\r
+ * opensource.org/licenses/BSD-3-Clause\r
+ *\r
+ ******************************************************************************\r
+ */ \r
+\r
+/* Define to prevent recursive inclusion -------------------------------------*/\r
+#ifndef __STM32L1xx_HAL_FLASH_EX_H\r
+#define __STM32L1xx_HAL_FLASH_EX_H\r
+\r
+#ifdef __cplusplus\r
+ extern "C" {\r
+#endif\r
+\r
+/* Includes ------------------------------------------------------------------*/\r
+#include "stm32l1xx_hal_def.h"\r
+\r
+/** @addtogroup STM32L1xx_HAL_Driver\r
+ * @{\r
+ */\r
+\r
+/** @addtogroup FLASHEx\r
+ * @{\r
+ */ \r
+\r
+/** @addtogroup FLASHEx_Private_Constants\r
+ * @{\r
+ */\r
+#if defined(FLASH_SR_RDERR) && defined(FLASH_SR_OPTVERRUSR)\r
+\r
+#define FLASH_FLAG_MASK ( FLASH_FLAG_EOP | FLASH_FLAG_ENDHV | FLASH_FLAG_WRPERR | \\r
+ FLASH_FLAG_OPTVERR | FLASH_FLAG_PGAERR | FLASH_FLAG_SIZERR | \\r
+ FLASH_FLAG_OPTVERRUSR | FLASH_FLAG_RDERR)\r
+\r
+#elif defined(FLASH_SR_RDERR)\r
+\r
+#define FLASH_FLAG_MASK ( FLASH_FLAG_EOP | FLASH_FLAG_ENDHV | FLASH_FLAG_WRPERR | \\r
+ FLASH_FLAG_OPTVERR | FLASH_FLAG_PGAERR | FLASH_FLAG_SIZERR | \\r
+ FLASH_FLAG_RDERR)\r
+\r
+#elif defined(FLASH_SR_OPTVERRUSR)\r
+\r
+#define FLASH_FLAG_MASK ( FLASH_FLAG_EOP | FLASH_FLAG_ENDHV | FLASH_FLAG_WRPERR | \\r
+ FLASH_FLAG_OPTVERR | FLASH_FLAG_PGAERR | FLASH_FLAG_SIZERR | \\r
+ FLASH_FLAG_OPTVERRUSR)\r
+\r
+#else\r
+\r
+#define FLASH_FLAG_MASK ( FLASH_FLAG_EOP | FLASH_FLAG_ENDHV | FLASH_FLAG_WRPERR | \\r
+ FLASH_FLAG_OPTVERR | FLASH_FLAG_PGAERR | FLASH_FLAG_SIZERR)\r
+\r
+#endif /* FLASH_SR_RDERR & FLASH_SR_OPTVERRUSR */\r
+\r
+#if defined(STM32L100xB) || defined(STM32L151xB) || defined(STM32L152xB) || defined(STM32L100xBA) \\r
+ || defined(STM32L151xBA) || defined(STM32L152xBA)\r
+ \r
+/******* Devices with FLASH 128K *******/\r
+#define FLASH_NBPAGES_MAX 512U /* 512 pages from page 0 to page 511U */\r
+\r
+#elif defined(STM32L100xC) || defined(STM32L151xC) || defined(STM32L152xC) || defined(STM32L162xC) \\r
+ || defined(STM32L151xCA) || defined(STM32L152xCA) || defined(STM32L162xCA)\r
+\r
+/******* Devices with FLASH 256K *******/\r
+#define FLASH_NBPAGES_MAX 1025U /* 1025 pages from page 0 to page 1024U */\r
+\r
+#elif defined(STM32L151xD) || defined(STM32L151xDX) || defined(STM32L152xD) || defined(STM32L152xDX) \\r
+ || defined(STM32L162xD) || defined(STM32L162xDX)\r
+\r
+/******* Devices with FLASH 384K *******/\r
+#define FLASH_NBPAGES_MAX 1536U /* 1536 pages from page 0 to page 1535U */\r
+\r
+#elif defined(STM32L151xE) || defined(STM32L152xE) || defined(STM32L162xE)\r
+\r
+/******* Devices with FLASH 512K *******/\r
+#define FLASH_NBPAGES_MAX 2048U /* 2048 pages from page 0 to page 2047U */\r
+\r
+#endif /* STM32L100xB || STM32L151xB || STM32L152xB || STM32L100xBA || STM32L151xBA || STM32L152xBA */\r
+\r
+#define WRP_MASK_LOW (0x0000FFFFU)\r
+#define WRP_MASK_HIGH (0xFFFF0000U)\r
+\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/** @addtogroup FLASHEx_Private_Macros\r
+ * @{\r
+ */\r
+\r
+#define IS_FLASH_TYPEERASE(__VALUE__) (((__VALUE__) == FLASH_TYPEERASE_PAGES))\r
+\r
+#define IS_OPTIONBYTE(__VALUE__) (((__VALUE__) <= (OPTIONBYTE_WRP|OPTIONBYTE_RDP|OPTIONBYTE_USER|OPTIONBYTE_BOR)))\r
+\r
+#define IS_WRPSTATE(__VALUE__) (((__VALUE__) == OB_WRPSTATE_DISABLE) || \\r
+ ((__VALUE__) == OB_WRPSTATE_ENABLE))\r
+ \r
+#define IS_OB_WRP(__PAGE__) (((__PAGE__) != 0x0000000U))\r
+\r
+#define IS_OB_RDP(__LEVEL__) (((__LEVEL__) == OB_RDP_LEVEL_0) ||\\r
+ ((__LEVEL__) == OB_RDP_LEVEL_1) ||\\r
+ ((__LEVEL__) == OB_RDP_LEVEL_2))\r
+ \r
+#define IS_OB_BOR_LEVEL(__LEVEL__) (((__LEVEL__) == OB_BOR_OFF) || \\r
+ ((__LEVEL__) == OB_BOR_LEVEL1) || \\r
+ ((__LEVEL__) == OB_BOR_LEVEL2) || \\r
+ ((__LEVEL__) == OB_BOR_LEVEL3) || \\r
+ ((__LEVEL__) == OB_BOR_LEVEL4) || \\r
+ ((__LEVEL__) == OB_BOR_LEVEL5))\r
+\r
+#define IS_OB_IWDG_SOURCE(__SOURCE__) (((__SOURCE__) == OB_IWDG_SW) || ((__SOURCE__) == OB_IWDG_HW))\r
+\r
+#define IS_OB_STOP_SOURCE(__SOURCE__) (((__SOURCE__) == OB_STOP_NORST) || ((__SOURCE__) == OB_STOP_RST))\r
+\r
+#define IS_OB_STDBY_SOURCE(__SOURCE__) (((__SOURCE__) == OB_STDBY_NORST) || ((__SOURCE__) == OB_STDBY_RST))\r
+\r
+#if defined(FLASH_OBR_SPRMOD) && defined(FLASH_OBR_nRST_BFB2)\r
+ \r
+#define IS_OBEX(__VALUE__) (((__VALUE__) == OPTIONBYTE_PCROP) || ((__VALUE__) == OPTIONBYTE_BOOTCONFIG))\r
+\r
+#elif defined(FLASH_OBR_SPRMOD) && !defined(FLASH_OBR_nRST_BFB2)\r
+\r
+#define IS_OBEX(__VALUE__) ((__VALUE__) == OPTIONBYTE_PCROP)\r
+\r
+#elif !defined(FLASH_OBR_SPRMOD) && defined(FLASH_OBR_nRST_BFB2)\r
+\r
+#define IS_OBEX(__VALUE__) ((__VALUE__) == OPTIONBYTE_BOOTCONFIG)\r
+\r
+#endif /* FLASH_OBR_SPRMOD && FLASH_OBR_nRST_BFB2 */\r
+\r
+#if defined(FLASH_OBR_SPRMOD)\r
+\r
+#define IS_PCROPSTATE(__VALUE__) (((__VALUE__) == OB_PCROP_STATE_DISABLE) || \\r
+ ((__VALUE__) == OB_PCROP_STATE_ENABLE)) \r
+\r
+#define IS_OB_PCROP(__PAGE__) (((__PAGE__) != 0x0000000U))\r
+#endif /* FLASH_OBR_SPRMOD */\r
+\r
+#if defined(FLASH_OBR_nRST_BFB2)\r
+ \r
+#define IS_OB_BOOT_BANK(__BANK__) (((__BANK__) == OB_BOOT_BANK2) || ((__BANK__) == OB_BOOT_BANK1))\r
+\r
+#endif /* FLASH_OBR_nRST_BFB2 */\r
+\r
+#define IS_TYPEERASEDATA(__VALUE__) (((__VALUE__) == FLASH_TYPEERASEDATA_BYTE) || \\r
+ ((__VALUE__) == FLASH_TYPEERASEDATA_HALFWORD) || \\r
+ ((__VALUE__) == FLASH_TYPEERASEDATA_WORD))\r
+#define IS_TYPEPROGRAMDATA(__VALUE__) (((__VALUE__) == FLASH_TYPEPROGRAMDATA_BYTE) || \\r
+ ((__VALUE__) == FLASH_TYPEPROGRAMDATA_HALFWORD) || \\r
+ ((__VALUE__) == FLASH_TYPEPROGRAMDATA_WORD) || \\r
+ ((__VALUE__) == FLASH_TYPEPROGRAMDATA_FASTBYTE) || \\r
+ ((__VALUE__) == FLASH_TYPEPROGRAMDATA_FASTHALFWORD) || \\r
+ ((__VALUE__) == FLASH_TYPEPROGRAMDATA_FASTWORD))\r
+\r
+\r
+/** @defgroup FLASHEx_Address FLASHEx Address\r
+ * @{\r
+ */\r
+\r
+#define IS_FLASH_DATA_ADDRESS(__ADDRESS__) (((__ADDRESS__) >= FLASH_EEPROM_BASE) && ((__ADDRESS__) <= FLASH_EEPROM_END))\r
+\r
+#if defined(STM32L100xB) || defined(STM32L151xB) || defined(STM32L152xB) || defined(STM32L100xBA) \\r
+ || defined(STM32L151xBA) || defined(STM32L152xBA) || defined(STM32L100xC) || defined(STM32L151xC) \\r
+ || defined(STM32L152xC) || defined(STM32L162xC) || defined(STM32L151xCA) || defined(STM32L152xCA) \\r
+ || defined(STM32L162xCA)\r
+\r
+#define IS_FLASH_PROGRAM_ADDRESS(__ADDRESS__) (((__ADDRESS__) >= FLASH_BASE) && ((__ADDRESS__) <= FLASH_END)) \r
+\r
+#else /*STM32L151xD || STM32L152xD || STM32L162xD || STM32L151xE || STM32L152xE || STM32L162xE */\r
+\r
+#define IS_FLASH_PROGRAM_ADDRESS(__ADDRESS__) (((__ADDRESS__) >= FLASH_BASE) && ((__ADDRESS__) <= FLASH_BANK2_END)) \r
+#define IS_FLASH_PROGRAM_BANK1_ADDRESS(__ADDRESS__) (((__ADDRESS__) >= FLASH_BASE) && ((__ADDRESS__) <= FLASH_BANK1_END)) \r
+#define IS_FLASH_PROGRAM_BANK2_ADDRESS(__ADDRESS__) (((__ADDRESS__) >= FLASH_BANK2_BASE) && ((__ADDRESS__) <= FLASH_BANK2_END)) \r
+\r
+#endif /* STM32L100xB || STM32L151xB || STM32L152xB || (...) || STM32L151xCA || STM32L152xCA || STM32L162xCA */\r
+\r
+#define IS_NBPAGES(__PAGES__) (((__PAGES__) >= 1U) && ((__PAGES__) <= FLASH_NBPAGES_MAX)) \r
+\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/**\r
+ * @}\r
+ */ \r
+/* Exported types ------------------------------------------------------------*/ \r
+\r
+/** @defgroup FLASHEx_Exported_Types FLASHEx Exported Types\r
+ * @{\r
+ */ \r
+\r
+/**\r
+ * @brief FLASH Erase structure definition\r
+ */\r
+typedef struct\r
+{\r
+ uint32_t TypeErase; /*!< TypeErase: Page Erase only.\r
+ This parameter can be a value of @ref FLASHEx_Type_Erase */\r
+\r
+ uint32_t PageAddress; /*!< PageAddress: Initial FLASH address to be erased\r
+ This parameter must be a value belonging to FLASH Programm address (depending on the devices) */\r
+ \r
+ uint32_t NbPages; /*!< NbPages: Number of pages to be erased.\r
+ This parameter must be a value between 1 and (max number of pages - value of Initial page)*/\r
+ \r
+} FLASH_EraseInitTypeDef;\r
+\r
+/**\r
+ * @brief FLASH Option Bytes PROGRAM structure definition\r
+ */\r
+typedef struct\r
+{\r
+ uint32_t OptionType; /*!< OptionType: Option byte to be configured.\r
+ This parameter can be a value of @ref FLASHEx_Option_Type */\r
+\r
+ uint32_t WRPState; /*!< WRPState: Write protection activation or deactivation.\r
+ This parameter can be a value of @ref FLASHEx_WRP_State */\r
+\r
+ uint32_t WRPSector0To31; /*!< WRPSector0To31: specifies the sector(s) which are write protected between Sector 0 to 31\r
+ This parameter can be a combination of @ref FLASHEx_Option_Bytes_Write_Protection1 */ \r
+ \r
+#if defined(STM32L100xC) || defined(STM32L151xC) || defined(STM32L152xC) || defined(STM32L162xC) \\r
+ || defined(STM32L151xCA) || defined(STM32L151xD) || defined(STM32L151xDX) || defined(STM32L152xCA) \\r
+ || defined(STM32L152xD) || defined(STM32L152xDX) || defined(STM32L162xCA) || defined(STM32L162xD) \\r
+ || defined(STM32L162xDX) || defined(STM32L151xE) || defined(STM32L152xE) || defined(STM32L162xE)\r
+ uint32_t WRPSector32To63; /*!< WRPSector32To63: specifies the sector(s) which are write protected between Sector 32 to 63\r
+ This parameter can be a combination of @ref FLASHEx_Option_Bytes_Write_Protection2 */ \r
+#endif /* STM32L100xC || STM32L151xC || STM32L152xC || (...) || STM32L151xE || STM32L152xE || STM32L162xE */\r
+\r
+#if defined(STM32L151xD) || defined(STM32L151xDX) || defined(STM32L152xD) || defined(STM32L152xDX) \\r
+ || defined(STM32L162xD) || defined(STM32L162xDX) || defined(STM32L151xE) || defined(STM32L152xE) \\r
+ || defined(STM32L162xE)\r
+ uint32_t WRPSector64To95; /*!< WRPSector64to95: specifies the sector(s) which are write protected between Sector 64 to 95\r
+ This parameter can be a combination of @ref FLASHEx_Option_Bytes_Write_Protection3 */ \r
+#endif /* STM32L151xD || STM32L152xD || STM32L162xD || STM32L151xE || STM32L152xE || STM32L162xE */\r
+\r
+#if defined(STM32L151xE) || defined(STM32L152xE) || defined(STM32L162xE) || defined(STM32L151xDX) \\r
+ || defined(STM32L152xDX) || defined(STM32L162xDX)\r
+ uint32_t WRPSector96To127; /*!< WRPSector96To127: specifies the sector(s) which are write protected between Sector 96 to 127 or\r
+ Sectors 96 to 111 for STM32L1xxxDX devices.\r
+ This parameter can be a combination of @ref FLASHEx_Option_Bytes_Write_Protection4 */ \r
+#endif /* STM32L151xE || STM32L152xE || STM32L162xE || STM32L151xDX || ... */\r
+ \r
+ uint8_t RDPLevel; /*!< RDPLevel: Set the read protection level.\r
+ This parameter can be a value of @ref FLASHEx_Option_Bytes_Read_Protection */\r
+\r
+ uint8_t BORLevel; /*!< BORLevel: Set the BOR Level.\r
+ This parameter can be a value of @ref FLASHEx_Option_Bytes_BOR_Level */\r
+ \r
+ uint8_t USERConfig; /*!< USERConfig: Program the FLASH User Option Byte: IWDG_SW / RST_STOP / RST_STDBY.\r
+ This parameter can be a combination of @ref FLASHEx_Option_Bytes_IWatchdog, \r
+ @ref FLASHEx_Option_Bytes_nRST_STOP and @ref FLASHEx_Option_Bytes_nRST_STDBY*/\r
+} FLASH_OBProgramInitTypeDef;\r
+\r
+#if defined(FLASH_OBR_SPRMOD) || defined(FLASH_OBR_nRST_BFB2)\r
+/**\r
+ * @brief FLASH Advanced Option Bytes Program structure definition\r
+ */\r
+typedef struct\r
+{\r
+ uint32_t OptionType; /*!< OptionType: Option byte to be configured for extension .\r
+ This parameter can be a value of @ref FLASHEx_OptionAdv_Type */\r
+\r
+#if defined(FLASH_OBR_SPRMOD)\r
+ uint32_t PCROPState; /*!< PCROPState: PCROP activation or deactivation.\r
+ This parameter can be a value of @ref FLASHEx_PCROP_State */\r
+\r
+ uint32_t PCROPSector0To31; /*!< PCROPSector0To31: specifies the sector(s) set for PCROP\r
+ This parameter can be a value of @ref FLASHEx_Option_Bytes_PC_ReadWrite_Protection1 */\r
+ \r
+#if defined(STM32L151xC) || defined(STM32L152xC) || defined(STM32L162xC)\r
+ uint32_t PCROPSector32To63; /*!< PCROPSector32To63: specifies the sector(s) set for PCROP\r
+ This parameter can be a value of @ref FLASHEx_Option_Bytes_PC_ReadWrite_Protection2 */\r
+#endif /* STM32L151xC || STM32L152xC || STM32L162xC */\r
+#endif /* FLASH_OBR_SPRMOD */\r
+ \r
+#if defined(FLASH_OBR_nRST_BFB2)\r
+ uint16_t BootConfig; /*!< BootConfig: specifies Option bytes for boot config\r
+ This parameter can be a value of @ref FLASHEx_Option_Bytes_BOOT */\r
+#endif /* FLASH_OBR_nRST_BFB2*/\r
+} FLASH_AdvOBProgramInitTypeDef;\r
+\r
+/**\r
+ * @}\r
+ */\r
+#endif /* FLASH_OBR_SPRMOD || FLASH_OBR_nRST_BFB2 */\r
+\r
+/* Exported constants --------------------------------------------------------*/\r
+\r
+\r
+/** @defgroup FLASHEx_Exported_Constants FLASHEx Exported Constants\r
+ * @{\r
+ */ \r
+\r
+/** @defgroup FLASHEx_Type_Erase FLASHEx_Type_Erase\r
+ * @{\r
+ */\r
+#define FLASH_TYPEERASE_PAGES (0x00U) /*!<Page erase only*/\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup FLASHEx_Option_Type FLASHEx Option Type\r
+ * @{\r
+ */\r
+#define OPTIONBYTE_WRP (0x01U) /*!<WRP option byte configuration*/\r
+#define OPTIONBYTE_RDP (0x02U) /*!<RDP option byte configuration*/\r
+#define OPTIONBYTE_USER (0x04U) /*!<USER option byte configuration*/\r
+#define OPTIONBYTE_BOR (0x08U) /*!<BOR option byte configuration*/\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup FLASHEx_WRP_State FLASHEx WRP State\r
+ * @{\r
+ */\r
+#define OB_WRPSTATE_DISABLE (0x00U) /*!<Disable the write protection of the desired sectors*/\r
+#define OB_WRPSTATE_ENABLE (0x01U) /*!<Enable the write protection of the desired sectors*/\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup FLASHEx_Option_Bytes_Write_Protection1 FLASHEx Option Bytes Write Protection1\r
+ * @{\r
+ */\r
+ \r
+/* Common pages for Cat1, Cat2, Cat3, Cat4 & Cat5 devices */\r
+#define OB_WRP1_PAGES0TO15 (0x00000001U) /* Write protection of Sector0 */ \r
+#define OB_WRP1_PAGES16TO31 (0x00000002U) /* Write protection of Sector1 */ \r
+#define OB_WRP1_PAGES32TO47 (0x00000004U) /* Write protection of Sector2 */ \r
+#define OB_WRP1_PAGES48TO63 (0x00000008U) /* Write protection of Sector3 */ \r
+#define OB_WRP1_PAGES64TO79 (0x00000010U) /* Write protection of Sector4 */ \r
+#define OB_WRP1_PAGES80TO95 (0x00000020U) /* Write protection of Sector5 */ \r
+#define OB_WRP1_PAGES96TO111 (0x00000040U) /* Write protection of Sector6 */ \r
+#define OB_WRP1_PAGES112TO127 (0x00000080U) /* Write protection of Sector7 */ \r
+#define OB_WRP1_PAGES128TO143 (0x00000100U) /* Write protection of Sector8 */ \r
+#define OB_WRP1_PAGES144TO159 (0x00000200U) /* Write protection of Sector9 */ \r
+#define OB_WRP1_PAGES160TO175 (0x00000400U) /* Write protection of Sector10 */ \r
+#define OB_WRP1_PAGES176TO191 (0x00000800U) /* Write protection of Sector11 */ \r
+#define OB_WRP1_PAGES192TO207 (0x00001000U) /* Write protection of Sector12 */ \r
+#define OB_WRP1_PAGES208TO223 (0x00002000U) /* Write protection of Sector13 */ \r
+#define OB_WRP1_PAGES224TO239 (0x00004000U) /* Write protection of Sector14 */ \r
+#define OB_WRP1_PAGES240TO255 (0x00008000U) /* Write protection of Sector15 */ \r
+#define OB_WRP1_PAGES256TO271 (0x00010000U) /* Write protection of Sector16 */ \r
+#define OB_WRP1_PAGES272TO287 (0x00020000U) /* Write protection of Sector17 */ \r
+#define OB_WRP1_PAGES288TO303 (0x00040000U) /* Write protection of Sector18 */ \r
+#define OB_WRP1_PAGES304TO319 (0x00080000U) /* Write protection of Sector19 */ \r
+#define OB_WRP1_PAGES320TO335 (0x00100000U) /* Write protection of Sector20 */ \r
+#define OB_WRP1_PAGES336TO351 (0x00200000U) /* Write protection of Sector21 */ \r
+#define OB_WRP1_PAGES352TO367 (0x00400000U) /* Write protection of Sector22 */ \r
+#define OB_WRP1_PAGES368TO383 (0x00800000U) /* Write protection of Sector23 */ \r
+#define OB_WRP1_PAGES384TO399 (0x01000000U) /* Write protection of Sector24 */ \r
+#define OB_WRP1_PAGES400TO415 (0x02000000U) /* Write protection of Sector25 */ \r
+#define OB_WRP1_PAGES416TO431 (0x04000000U) /* Write protection of Sector26 */ \r
+#define OB_WRP1_PAGES432TO447 (0x08000000U) /* Write protection of Sector27 */ \r
+#define OB_WRP1_PAGES448TO463 (0x10000000U) /* Write protection of Sector28 */ \r
+#define OB_WRP1_PAGES464TO479 (0x20000000U) /* Write protection of Sector29 */ \r
+#define OB_WRP1_PAGES480TO495 (0x40000000U) /* Write protection of Sector30 */ \r
+#define OB_WRP1_PAGES496TO511 (0x80000000U) /* Write protection of Sector31 */ \r
+ \r
+#define OB_WRP1_ALLPAGES ((uint32_t)FLASH_WRPR1_WRP) /*!< Write protection of all Sectors */\r
+ \r
+/**\r
+ * @}\r
+ */ \r
+\r
+#if defined(STM32L100xC) || defined(STM32L151xC) || defined(STM32L152xC) || defined(STM32L162xC) \\r
+ || defined(STM32L151xCA) || defined(STM32L151xD) || defined(STM32L151xDX) || defined(STM32L152xCA) \\r
+ || defined(STM32L152xD) || defined(STM32L152xDX) || defined(STM32L162xCA) || defined(STM32L162xD) \\r
+ || defined(STM32L162xDX) || defined(STM32L151xE) || defined(STM32L152xE) || defined(STM32L162xE)\r
+\r
+/** @defgroup FLASHEx_Option_Bytes_Write_Protection2 FLASHEx Option Bytes Write Protection2\r
+ * @{\r
+ */\r
+ \r
+/* Pages for Cat3, Cat4 & Cat5 devices*/\r
+#define OB_WRP2_PAGES512TO527 (0x00000001U) /* Write protection of Sector32 */ \r
+#define OB_WRP2_PAGES528TO543 (0x00000002U) /* Write protection of Sector33 */ \r
+#define OB_WRP2_PAGES544TO559 (0x00000004U) /* Write protection of Sector34 */ \r
+#define OB_WRP2_PAGES560TO575 (0x00000008U) /* Write protection of Sector35 */ \r
+#define OB_WRP2_PAGES576TO591 (0x00000010U) /* Write protection of Sector36 */ \r
+#define OB_WRP2_PAGES592TO607 (0x00000020U) /* Write protection of Sector37 */ \r
+#define OB_WRP2_PAGES608TO623 (0x00000040U) /* Write protection of Sector38 */ \r
+#define OB_WRP2_PAGES624TO639 (0x00000080U) /* Write protection of Sector39 */ \r
+#define OB_WRP2_PAGES640TO655 (0x00000100U) /* Write protection of Sector40 */ \r
+#define OB_WRP2_PAGES656TO671 (0x00000200U) /* Write protection of Sector41 */ \r
+#define OB_WRP2_PAGES672TO687 (0x00000400U) /* Write protection of Sector42 */ \r
+#define OB_WRP2_PAGES688TO703 (0x00000800U) /* Write protection of Sector43 */ \r
+#define OB_WRP2_PAGES704TO719 (0x00001000U) /* Write protection of Sector44 */ \r
+#define OB_WRP2_PAGES720TO735 (0x00002000U) /* Write protection of Sector45 */ \r
+#define OB_WRP2_PAGES736TO751 (0x00004000U) /* Write protection of Sector46 */ \r
+#define OB_WRP2_PAGES752TO767 (0x00008000U) /* Write protection of Sector47 */ \r
+\r
+#if defined(STM32L100xC) || defined(STM32L151xC) || defined(STM32L152xC) || defined(STM32L162xC) \\r
+ || defined(STM32L151xCA) || defined(STM32L151xD) || defined(STM32L152xCA) || defined(STM32L152xD) \\r
+ || defined(STM32L162xCA) || defined(STM32L162xD) || defined(STM32L151xE) || defined(STM32L152xE) \\r
+ || defined(STM32L162xE)\r
+\r
+#define OB_WRP2_PAGES768TO783 (0x00010000U) /* Write protection of Sector48 */ \r
+#define OB_WRP2_PAGES784TO799 (0x00020000U) /* Write protection of Sector49 */ \r
+#define OB_WRP2_PAGES800TO815 (0x00040000U) /* Write protection of Sector50 */ \r
+#define OB_WRP2_PAGES816TO831 (0x00080000U) /* Write protection of Sector51 */ \r
+#define OB_WRP2_PAGES832TO847 (0x00100000U) /* Write protection of Sector52 */ \r
+#define OB_WRP2_PAGES848TO863 (0x00200000U) /* Write protection of Sector53 */ \r
+#define OB_WRP2_PAGES864TO879 (0x00400000U) /* Write protection of Sector54 */ \r
+#define OB_WRP2_PAGES880TO895 (0x00800000U) /* Write protection of Sector55 */ \r
+#define OB_WRP2_PAGES896TO911 (0x01000000U) /* Write protection of Sector56 */ \r
+#define OB_WRP2_PAGES912TO927 (0x02000000U) /* Write protection of Sector57 */ \r
+#define OB_WRP2_PAGES928TO943 (0x04000000U) /* Write protection of Sector58 */ \r
+#define OB_WRP2_PAGES944TO959 (0x08000000U) /* Write protection of Sector59 */ \r
+#define OB_WRP2_PAGES960TO975 (0x10000000U) /* Write protection of Sector60 */ \r
+#define OB_WRP2_PAGES976TO991 (0x20000000U) /* Write protection of Sector61 */ \r
+#define OB_WRP2_PAGES992TO1007 (0x40000000U) /* Write protection of Sector62 */\r
+#define OB_WRP2_PAGES1008TO1023 (0x80000000U) /* Write protection of Sector63 */\r
+\r
+#endif /* STM32L100xC || STM32L151xC || STM32L152xC || (...) || STM32L162xD || STM32L151xE || STM32L152xE || STM32L162xE */\r
+ \r
+#define OB_WRP2_ALLPAGES ((uint32_t)FLASH_WRPR2_WRP) /*!< Write protection of all Sectors */\r
+\r
+/**\r
+ * @}\r
+ */ \r
+\r
+#endif /* STM32L100xC || STM32L151xC || STM32L152xC || (...) || STM32L162xD || STM32L151xDX || STM32L152xE || STM32L162xE */\r
+\r
+#if defined(STM32L151xD) || defined(STM32L151xDX) || defined(STM32L152xD) || defined(STM32L152xDX) \\r
+ || defined(STM32L162xD) || defined(STM32L162xDX) || defined(STM32L151xE) || defined(STM32L152xE) \\r
+ || defined(STM32L162xE)\r
+\r
+/** @defgroup FLASHEx_Option_Bytes_Write_Protection3 FLASHEx Option Bytes Write Protection3\r
+ * @{\r
+ */\r
+ \r
+/* Pages for devices with FLASH >= 256KB*/\r
+#define OB_WRP3_PAGES1024TO1039 (0x00000001U) /* Write protection of Sector64 */\r
+#define OB_WRP3_PAGES1040TO1055 (0x00000002U) /* Write protection of Sector65 */\r
+#define OB_WRP3_PAGES1056TO1071 (0x00000004U) /* Write protection of Sector66 */\r
+#define OB_WRP3_PAGES1072TO1087 (0x00000008U) /* Write protection of Sector67 */\r
+#define OB_WRP3_PAGES1088TO1103 (0x00000010U) /* Write protection of Sector68 */\r
+#define OB_WRP3_PAGES1104TO1119 (0x00000020U) /* Write protection of Sector69 */\r
+#define OB_WRP3_PAGES1120TO1135 (0x00000040U) /* Write protection of Sector70 */\r
+#define OB_WRP3_PAGES1136TO1151 (0x00000080U) /* Write protection of Sector71 */\r
+#define OB_WRP3_PAGES1152TO1167 (0x00000100U) /* Write protection of Sector72 */\r
+#define OB_WRP3_PAGES1168TO1183 (0x00000200U) /* Write protection of Sector73 */\r
+#define OB_WRP3_PAGES1184TO1199 (0x00000400U) /* Write protection of Sector74 */\r
+#define OB_WRP3_PAGES1200TO1215 (0x00000800U) /* Write protection of Sector75 */\r
+#define OB_WRP3_PAGES1216TO1231 (0x00001000U) /* Write protection of Sector76 */\r
+#define OB_WRP3_PAGES1232TO1247 (0x00002000U) /* Write protection of Sector77 */\r
+#define OB_WRP3_PAGES1248TO1263 (0x00004000U) /* Write protection of Sector78 */\r
+#define OB_WRP3_PAGES1264TO1279 (0x00008000U) /* Write protection of Sector79 */\r
+#define OB_WRP3_PAGES1280TO1295 (0x00010000U) /* Write protection of Sector80 */\r
+#define OB_WRP3_PAGES1296TO1311 (0x00020000U) /* Write protection of Sector81 */\r
+#define OB_WRP3_PAGES1312TO1327 (0x00040000U) /* Write protection of Sector82 */\r
+#define OB_WRP3_PAGES1328TO1343 (0x00080000U) /* Write protection of Sector83 */\r
+#define OB_WRP3_PAGES1344TO1359 (0x00100000U) /* Write protection of Sector84 */\r
+#define OB_WRP3_PAGES1360TO1375 (0x00200000U) /* Write protection of Sector85 */\r
+#define OB_WRP3_PAGES1376TO1391 (0x00400000U) /* Write protection of Sector86 */\r
+#define OB_WRP3_PAGES1392TO1407 (0x00800000U) /* Write protection of Sector87 */\r
+#define OB_WRP3_PAGES1408TO1423 (0x01000000U) /* Write protection of Sector88 */\r
+#define OB_WRP3_PAGES1424TO1439 (0x02000000U) /* Write protection of Sector89 */\r
+#define OB_WRP3_PAGES1440TO1455 (0x04000000U) /* Write protection of Sector90 */\r
+#define OB_WRP3_PAGES1456TO1471 (0x08000000U) /* Write protection of Sector91 */\r
+#define OB_WRP3_PAGES1472TO1487 (0x10000000U) /* Write protection of Sector92 */\r
+#define OB_WRP3_PAGES1488TO1503 (0x20000000U) /* Write protection of Sector93 */\r
+#define OB_WRP3_PAGES1504TO1519 (0x40000000U) /* Write protection of Sector94 */\r
+#define OB_WRP3_PAGES1520TO1535 (0x80000000U) /* Write protection of Sector95 */\r
+\r
+#define OB_WRP3_ALLPAGES ((uint32_t)FLASH_WRPR3_WRP) /*!< Write protection of all Sectors */\r
+\r
+/**\r
+ * @}\r
+ */ \r
+\r
+#endif /* STM32L151xD || STM32L152xD || STM32L162xD || STM32L151xE || STM32L152xE || STM32L162xE*/\r
+\r
+#if defined(STM32L151xE) || defined(STM32L152xE) || defined(STM32L162xE) || defined(STM32L151xDX) \\r
+ || defined(STM32L152xDX) || defined(STM32L162xDX)\r
+\r
+/** @defgroup FLASHEx_Option_Bytes_Write_Protection4 FLASHEx Option Bytes Write Protection4\r
+ * @{\r
+ */\r
+ \r
+/* Pages for Cat5 devices*/\r
+#define OB_WRP4_PAGES1536TO1551 (0x00000001U)/* Write protection of Sector96*/ \r
+#define OB_WRP4_PAGES1552TO1567 (0x00000002U)/* Write protection of Sector97*/ \r
+#define OB_WRP4_PAGES1568TO1583 (0x00000004U)/* Write protection of Sector98*/ \r
+#define OB_WRP4_PAGES1584TO1599 (0x00000008U)/* Write protection of Sector99*/ \r
+#define OB_WRP4_PAGES1600TO1615 (0x00000010U) /* Write protection of Sector100*/ \r
+#define OB_WRP4_PAGES1616TO1631 (0x00000020U) /* Write protection of Sector101*/ \r
+#define OB_WRP4_PAGES1632TO1647 (0x00000040U) /* Write protection of Sector102*/ \r
+#define OB_WRP4_PAGES1648TO1663 (0x00000080U) /* Write protection of Sector103*/ \r
+#define OB_WRP4_PAGES1664TO1679 (0x00000100U) /* Write protection of Sector104*/ \r
+#define OB_WRP4_PAGES1680TO1695 (0x00000200U) /* Write protection of Sector105*/ \r
+#define OB_WRP4_PAGES1696TO1711 (0x00000400U) /* Write protection of Sector106*/ \r
+#define OB_WRP4_PAGES1712TO1727 (0x00000800U) /* Write protection of Sector107*/ \r
+#define OB_WRP4_PAGES1728TO1743 (0x00001000U) /* Write protection of Sector108*/ \r
+#define OB_WRP4_PAGES1744TO1759 (0x00002000U) /* Write protection of Sector109*/ \r
+#define OB_WRP4_PAGES1760TO1775 (0x00004000U) /* Write protection of Sector110*/ \r
+#define OB_WRP4_PAGES1776TO1791 (0x00008000U) /* Write protection of Sector111*/ \r
+\r
+#if defined(STM32L151xE) || defined(STM32L152xE) || defined(STM32L162xE)\r
+\r
+#define OB_WRP4_PAGES1792TO1807 (0x00010000U) /* Write protection of Sector112*/ \r
+#define OB_WRP4_PAGES1808TO1823 (0x00020000U) /* Write protection of Sector113*/ \r
+#define OB_WRP4_PAGES1824TO1839 (0x00040000U) /* Write protection of Sector114*/ \r
+#define OB_WRP4_PAGES1840TO1855 (0x00080000U) /* Write protection of Sector115*/ \r
+#define OB_WRP4_PAGES1856TO1871 (0x00100000U) /* Write protection of Sector116*/ \r
+#define OB_WRP4_PAGES1872TO1887 (0x00200000U) /* Write protection of Sector117*/ \r
+#define OB_WRP4_PAGES1888TO1903 (0x00400000U) /* Write protection of Sector118*/ \r
+#define OB_WRP4_PAGES1904TO1919 (0x00800000U) /* Write protection of Sector119*/ \r
+#define OB_WRP4_PAGES1920TO1935 (0x01000000U) /* Write protection of Sector120*/ \r
+#define OB_WRP4_PAGES1936TO1951 (0x02000000U) /* Write protection of Sector121*/ \r
+#define OB_WRP4_PAGES1952TO1967 (0x04000000U) /* Write protection of Sector122*/ \r
+#define OB_WRP4_PAGES1968TO1983 (0x08000000U) /* Write protection of Sector123*/ \r
+#define OB_WRP4_PAGES1984TO1999 (0x10000000U) /* Write protection of Sector124*/ \r
+#define OB_WRP4_PAGES2000TO2015 (0x20000000U) /* Write protection of Sector125*/ \r
+#define OB_WRP4_PAGES2016TO2031 (0x40000000U) /* Write protection of Sector126*/ \r
+#define OB_WRP4_PAGES2032TO2047 (0x80000000U) /* Write protection of Sector127*/ \r
+\r
+#endif /* STM32L151xE || STM32L152xE || STM32L162xE */\r
+\r
+#define OB_WRP4_ALLPAGES ((uint32_t)FLASH_WRPR4_WRP) /*!< Write protection of all Sectors */\r
+\r
+/**\r
+ * @}\r
+ */ \r
+\r
+#endif /* STM32L151xE || STM32L152xE || STM32L162xE || STM32L151xDX || ... */\r
+\r
+/** @defgroup FLASHEx_Option_Bytes_Read_Protection FLASHEx Option Bytes Read Protection\r
+ * @{\r
+ */ \r
+#define OB_RDP_LEVEL_0 ((uint8_t)0xAAU)\r
+#define OB_RDP_LEVEL_1 ((uint8_t)0xBBU)\r
+#define OB_RDP_LEVEL_2 ((uint8_t)0xCCU) /* Warning: When enabling read protection level 2 \r
+ it is no more possible to go back to level 1 or 0 */\r
+\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/** @defgroup FLASHEx_Option_Bytes_BOR_Level FLASHEx Option Bytes BOR Level\r
+ * @{\r
+ */\r
+\r
+#define OB_BOR_OFF ((uint8_t)0x00U) /*!< BOR is disabled at power down, the reset is asserted when the VDD \r
+ power supply reaches the PDR(Power Down Reset) threshold (1.5V) */\r
+#define OB_BOR_LEVEL1 ((uint8_t)0x08U) /*!< BOR Reset threshold levels for 1.7V - 1.8V VDD power supply */\r
+#define OB_BOR_LEVEL2 ((uint8_t)0x09U) /*!< BOR Reset threshold levels for 1.9V - 2.0V VDD power supply */\r
+#define OB_BOR_LEVEL3 ((uint8_t)0x0AU) /*!< BOR Reset threshold levels for 2.3V - 2.4V VDD power supply */\r
+#define OB_BOR_LEVEL4 ((uint8_t)0x0BU) /*!< BOR Reset threshold levels for 2.55V - 2.65V VDD power supply */\r
+#define OB_BOR_LEVEL5 ((uint8_t)0x0CU) /*!< BOR Reset threshold levels for 2.8V - 2.9V VDD power supply */\r
+\r
+/**\r
+ * @}\r
+ */\r
+ \r
+/** @defgroup FLASHEx_Option_Bytes_IWatchdog FLASHEx Option Bytes IWatchdog\r
+ * @{\r
+ */\r
+\r
+#define OB_IWDG_SW ((uint8_t)0x10U) /*!< Software WDG selected */\r
+#define OB_IWDG_HW ((uint8_t)0x00U) /*!< Hardware WDG selected */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup FLASHEx_Option_Bytes_nRST_STOP FLASHEx Option Bytes nRST_STOP\r
+ * @{\r
+ */\r
+\r
+#define OB_STOP_NORST ((uint8_t)0x20U) /*!< No reset generated when entering in STOP */\r
+#define OB_STOP_RST ((uint8_t)0x00U) /*!< Reset generated when entering in STOP */\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup FLASHEx_Option_Bytes_nRST_STDBY FLASHEx Option Bytes nRST_STDBY\r
+ * @{\r
+ */\r
+\r
+#define OB_STDBY_NORST ((uint8_t)0x40U) /*!< No reset generated when entering in STANDBY */\r
+#define OB_STDBY_RST ((uint8_t)0x00U) /*!< Reset generated when entering in STANDBY */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+#if defined(FLASH_OBR_SPRMOD)\r
+ \r
+/** @defgroup FLASHEx_OptionAdv_Type FLASHEx Option Advanced Type\r
+ * @{\r
+ */ \r
+ \r
+#define OPTIONBYTE_PCROP (0x01U) /*!<PCROP option byte configuration*/\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+#endif /* FLASH_OBR_SPRMOD */\r
+\r
+#if defined(FLASH_OBR_nRST_BFB2)\r
+\r
+/** @defgroup FLASHEx_OptionAdv_Type FLASHEx Option Advanced Type\r
+ * @{\r
+ */ \r
+ \r
+#define OPTIONBYTE_BOOTCONFIG (0x02U) /*!<BOOTConfig option byte configuration*/\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+#endif /* FLASH_OBR_nRST_BFB2 */\r
+\r
+#if defined(FLASH_OBR_SPRMOD)\r
+\r
+/** @defgroup FLASHEx_PCROP_State FLASHEx PCROP State\r
+ * @{\r
+ */\r
+#define OB_PCROP_STATE_DISABLE (0x00U) /*!<Disable PCROP for selected sectors */\r
+#define OB_PCROP_STATE_ENABLE (0x01U) /*!<Enable PCROP for selected sectors */\r
+ \r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup FLASHEx_Selection_Protection_Mode FLASHEx Selection Protection Mode\r
+ * @{\r
+ */\r
+#define OB_PCROP_DESELECTED ((uint16_t)0x0000U) /*!< Disabled PCROP, nWPRi bits used for Write Protection on sector i */\r
+#define OB_PCROP_SELECTED ((uint16_t)FLASH_OBR_SPRMOD) /*!< Enable PCROP, nWPRi bits used for PCRoP Protection on sector i */\r
+\r
+/**\r
+ * @}\r
+ */\r
+#endif /* FLASH_OBR_SPRMOD */\r
+\r
+#if defined(STM32L151xBA) || defined(STM32L152xBA) || defined(STM32L151xC) || defined(STM32L152xC) \\r
+ || defined(STM32L162xC)\r
+/** @defgroup FLASHEx_Option_Bytes_PC_ReadWrite_Protection1 FLASHEx Option Bytes PC ReadWrite Protection 1\r
+ * @{\r
+ */\r
+ \r
+/* Common pages for Cat1, Cat2, Cat3, Cat4 & Cat5 devices */\r
+#define OB_PCROP1_PAGES0TO15 (0x00000001U) /* PC Read/Write protection of Sector0 */ \r
+#define OB_PCROP1_PAGES16TO31 (0x00000002U) /* PC Read/Write protection of Sector1 */ \r
+#define OB_PCROP1_PAGES32TO47 (0x00000004U) /* PC Read/Write protection of Sector2 */ \r
+#define OB_PCROP1_PAGES48TO63 (0x00000008U) /* PC Read/Write protection of Sector3 */ \r
+#define OB_PCROP1_PAGES64TO79 (0x00000010U) /* PC Read/Write protection of Sector4 */ \r
+#define OB_PCROP1_PAGES80TO95 (0x00000020U) /* PC Read/Write protection of Sector5 */ \r
+#define OB_PCROP1_PAGES96TO111 (0x00000040U) /* PC Read/Write protection of Sector6 */ \r
+#define OB_PCROP1_PAGES112TO127 (0x00000080U) /* PC Read/Write protection of Sector7 */ \r
+#define OB_PCROP1_PAGES128TO143 (0x00000100U) /* PC Read/Write protection of Sector8 */ \r
+#define OB_PCROP1_PAGES144TO159 (0x00000200U) /* PC Read/Write protection of Sector9 */ \r
+#define OB_PCROP1_PAGES160TO175 (0x00000400U) /* PC Read/Write protection of Sector10 */ \r
+#define OB_PCROP1_PAGES176TO191 (0x00000800U) /* PC Read/Write protection of Sector11 */ \r
+#define OB_PCROP1_PAGES192TO207 (0x00001000U) /* PC Read/Write protection of Sector12 */ \r
+#define OB_PCROP1_PAGES208TO223 (0x00002000U) /* PC Read/Write protection of Sector13 */ \r
+#define OB_PCROP1_PAGES224TO239 (0x00004000U) /* PC Read/Write protection of Sector14 */ \r
+#define OB_PCROP1_PAGES240TO255 (0x00008000U) /* PC Read/Write protection of Sector15 */ \r
+#define OB_PCROP1_PAGES256TO271 (0x00010000U) /* PC Read/Write protection of Sector16 */ \r
+#define OB_PCROP1_PAGES272TO287 (0x00020000U) /* PC Read/Write protection of Sector17 */ \r
+#define OB_PCROP1_PAGES288TO303 (0x00040000U) /* PC Read/Write protection of Sector18 */ \r
+#define OB_PCROP1_PAGES304TO319 (0x00080000U) /* PC Read/Write protection of Sector19 */ \r
+#define OB_PCROP1_PAGES320TO335 (0x00100000U) /* PC Read/Write protection of Sector20 */ \r
+#define OB_PCROP1_PAGES336TO351 (0x00200000U) /* PC Read/Write protection of Sector21 */ \r
+#define OB_PCROP1_PAGES352TO367 (0x00400000U) /* PC Read/Write protection of Sector22 */ \r
+#define OB_PCROP1_PAGES368TO383 (0x00800000U) /* PC Read/Write protection of Sector23 */ \r
+#define OB_PCROP1_PAGES384TO399 (0x01000000U) /* PC Read/Write protection of Sector24 */ \r
+#define OB_PCROP1_PAGES400TO415 (0x02000000U) /* PC Read/Write protection of Sector25 */ \r
+#define OB_PCROP1_PAGES416TO431 (0x04000000U) /* PC Read/Write protection of Sector26 */ \r
+#define OB_PCROP1_PAGES432TO447 (0x08000000U) /* PC Read/Write protection of Sector27 */ \r
+#define OB_PCROP1_PAGES448TO463 (0x10000000U) /* PC Read/Write protection of Sector28 */ \r
+#define OB_PCROP1_PAGES464TO479 (0x20000000U) /* PC Read/Write protection of Sector29 */ \r
+#define OB_PCROP1_PAGES480TO495 (0x40000000U) /* PC Read/Write protection of Sector30 */ \r
+#define OB_PCROP1_PAGES496TO511 (0x80000000U) /* PC Read/Write protection of Sector31 */ \r
+ \r
+#define OB_PCROP1_ALLPAGES (0xFFFFFFFFU) /*!< PC Read/Write protection of all Sectors */\r
+ \r
+/**\r
+ * @}\r
+ */ \r
+#endif /* STM32L151xBA || STM32L152xBA || STM32L151xC || STM32L152xC || STM32L162xC */\r
+\r
+#if defined(STM32L151xC) || defined(STM32L152xC) || defined(STM32L162xC)\r
+\r
+/** @defgroup FLASHEx_Option_Bytes_PC_ReadWrite_Protection2 FLASHEx Option Bytes PC ReadWrite Protection 2\r
+ * @{\r
+ */\r
+ \r
+/* Pages for Cat3, Cat4 & Cat5 devices*/\r
+#define OB_PCROP2_PAGES512TO527 (0x00000001U) /* PC Read/Write protection of Sector32 */ \r
+#define OB_PCROP2_PAGES528TO543 (0x00000002U) /* PC Read/Write protection of Sector33 */ \r
+#define OB_PCROP2_PAGES544TO559 (0x00000004U) /* PC Read/Write protection of Sector34 */ \r
+#define OB_PCROP2_PAGES560TO575 (0x00000008U) /* PC Read/Write protection of Sector35 */ \r
+#define OB_PCROP2_PAGES576TO591 (0x00000010U) /* PC Read/Write protection of Sector36 */ \r
+#define OB_PCROP2_PAGES592TO607 (0x00000020U) /* PC Read/Write protection of Sector37 */ \r
+#define OB_PCROP2_PAGES608TO623 (0x00000040U) /* PC Read/Write protection of Sector38 */ \r
+#define OB_PCROP2_PAGES624TO639 (0x00000080U) /* PC Read/Write protection of Sector39 */ \r
+#define OB_PCROP2_PAGES640TO655 (0x00000100U) /* PC Read/Write protection of Sector40 */ \r
+#define OB_PCROP2_PAGES656TO671 (0x00000200U) /* PC Read/Write protection of Sector41 */ \r
+#define OB_PCROP2_PAGES672TO687 (0x00000400U) /* PC Read/Write protection of Sector42 */ \r
+#define OB_PCROP2_PAGES688TO703 (0x00000800U) /* PC Read/Write protection of Sector43 */ \r
+#define OB_PCROP2_PAGES704TO719 (0x00001000U) /* PC Read/Write protection of Sector44 */ \r
+#define OB_PCROP2_PAGES720TO735 (0x00002000U) /* PC Read/Write protection of Sector45 */ \r
+#define OB_PCROP2_PAGES736TO751 (0x00004000U) /* PC Read/Write protection of Sector46 */ \r
+#define OB_PCROP2_PAGES752TO767 (0x00008000U) /* PC Read/Write protection of Sector47 */ \r
+#define OB_PCROP2_PAGES768TO783 (0x00010000U) /* PC Read/Write protection of Sector48 */ \r
+#define OB_PCROP2_PAGES784TO799 (0x00020000U) /* PC Read/Write protection of Sector49 */ \r
+#define OB_PCROP2_PAGES800TO815 (0x00040000U) /* PC Read/Write protection of Sector50 */ \r
+#define OB_PCROP2_PAGES816TO831 (0x00080000U) /* PC Read/Write protection of Sector51 */ \r
+#define OB_PCROP2_PAGES832TO847 (0x00100000U) /* PC Read/Write protection of Sector52 */ \r
+#define OB_PCROP2_PAGES848TO863 (0x00200000U) /* PC Read/Write protection of Sector53 */ \r
+#define OB_PCROP2_PAGES864TO879 (0x00400000U) /* PC Read/Write protection of Sector54 */ \r
+#define OB_PCROP2_PAGES880TO895 (0x00800000U) /* PC Read/Write protection of Sector55 */ \r
+#define OB_PCROP2_PAGES896TO911 (0x01000000U) /* PC Read/Write protection of Sector56 */ \r
+#define OB_PCROP2_PAGES912TO927 (0x02000000U) /* PC Read/Write protection of Sector57 */ \r
+#define OB_PCROP2_PAGES928TO943 (0x04000000U) /* PC Read/Write protection of Sector58 */ \r
+#define OB_PCROP2_PAGES944TO959 (0x08000000U) /* PC Read/Write protection of Sector59 */ \r
+#define OB_PCROP2_PAGES960TO975 (0x10000000U) /* PC Read/Write protection of Sector60 */ \r
+#define OB_PCROP2_PAGES976TO991 (0x20000000U) /* PC Read/Write protection of Sector61 */ \r
+#define OB_PCROP2_PAGES992TO1007 (0x40000000U) /* PC Read/Write protection of Sector62 */\r
+#define OB_PCROP2_PAGES1008TO1023 (0x80000000U) /* PC Read/Write protection of Sector63 */\r
+\r
+#define OB_PCROP2_ALLPAGES (0xFFFFFFFFU) /*!< PC Read/Write protection of all Sectors */\r
+\r
+/**\r
+ * @}\r
+ */ \r
+#endif /* STM32L151xC || STM32L152xC || STM32L162xC */\r
+\r
+/** @defgroup FLASHEx_Type_Erase_Data FLASHEx Type Erase Data\r
+ * @{\r
+ */\r
+#define FLASH_TYPEERASEDATA_BYTE (0x00U) /*!<Erase byte (8-bit) at a specified address.*/\r
+#define FLASH_TYPEERASEDATA_HALFWORD (0x01U) /*!<Erase a half-word (16-bit) at a specified address.*/\r
+#define FLASH_TYPEERASEDATA_WORD (0x02U) /*!<Erase a word (32-bit) at a specified address.*/\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup FLASHEx_Type_Program_Data FLASHEx Type Program Data\r
+ * @{\r
+ */\r
+#define FLASH_TYPEPROGRAMDATA_BYTE (0x00U) /*!<Program byte (8-bit) at a specified address.*/\r
+#define FLASH_TYPEPROGRAMDATA_HALFWORD (0x01U) /*!<Program a half-word (16-bit) at a specified address.*/\r
+#define FLASH_TYPEPROGRAMDATA_WORD (0x02U) /*!<Program a word (32-bit) at a specified address.*/\r
+#define FLASH_TYPEPROGRAMDATA_FASTBYTE (0x04U) /*!<Fast Program byte (8-bit) at a specified address.*/\r
+#define FLASH_TYPEPROGRAMDATA_FASTHALFWORD (0x08U) /*!<Fast Program a half-word (16-bit) at a specified address.*/\r
+#define FLASH_TYPEPROGRAMDATA_FASTWORD (0x10U) /*!<Fast Program a word (32-bit) at a specified address.*/\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+#if defined(FLASH_OBR_nRST_BFB2)\r
+ \r
+/** @defgroup FLASHEx_Option_Bytes_BOOT FLASHEx Option Bytes BOOT\r
+ * @{\r
+ */\r
+\r
+#define OB_BOOT_BANK2 ((uint8_t)0x00U) /*!< At startup, if boot pins are set in boot from user Flash position\r
+ and this parameter is selected the device will boot from Bank 2 \r
+ or Bank 1, depending on the activation of the bank */\r
+#define OB_BOOT_BANK1 ((uint8_t)(FLASH_OBR_nRST_BFB2 >> 16U)) /*!< At startup, if boot pins are set in boot from user Flash position\r
+ and this parameter is selected the device will boot from Bank1(Default) */\r
+\r
+/**\r
+ * @}\r
+ */\r
+#endif /* FLASH_OBR_nRST_BFB2 */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/* Exported macro ------------------------------------------------------------*/\r
+\r
+/** @defgroup FLASHEx_Exported_Macros FLASHEx Exported Macros\r
+ * @{\r
+ */\r
+ \r
+/**\r
+ * @brief Set the FLASH Latency.\r
+ * @param __LATENCY__ FLASH Latency\r
+ * This parameter can be one of the following values:\r
+ * @arg @ref FLASH_LATENCY_0 FLASH Zero Latency cycle\r
+ * @arg @ref FLASH_LATENCY_1 FLASH One Latency cycle\r
+ * @retval none\r
+ */ \r
+#define __HAL_FLASH_SET_LATENCY(__LATENCY__) do { \\r
+ if ((__LATENCY__) == FLASH_LATENCY_1) {__HAL_FLASH_ACC64_ENABLE();} \\r
+ MODIFY_REG((FLASH->ACR), FLASH_ACR_LATENCY, (__LATENCY__)); \\r
+ } while(0U)\r
+\r
+/**\r
+ * @brief Get the FLASH Latency.\r
+ * @retval FLASH Latency \r
+ * This parameter can be one of the following values:\r
+ * @arg @ref FLASH_LATENCY_0 FLASH Zero Latency cycle\r
+ * @arg @ref FLASH_LATENCY_1 FLASH One Latency cycle\r
+ */ \r
+#define __HAL_FLASH_GET_LATENCY() (READ_BIT((FLASH->ACR), FLASH_ACR_LATENCY))\r
+\r
+/**\r
+ * @brief Enable the FLASH 64-bit access.\r
+ * @note Read access 64 bit is used.\r
+ * @note This bit cannot be written at the same time as the LATENCY and \r
+ * PRFTEN bits.\r
+ * @retval none\r
+ */ \r
+#define __HAL_FLASH_ACC64_ENABLE() (SET_BIT((FLASH->ACR), FLASH_ACR_ACC64))\r
+\r
+ /**\r
+ * @brief Disable the FLASH 64-bit access.\r
+ * @note Read access 32 bit is used\r
+ * @note To reset this bit, the LATENCY should be zero wait state and the \r
+ * prefetch off.\r
+ * @retval none\r
+ */ \r
+#define __HAL_FLASH_ACC64_DISABLE() (CLEAR_BIT((FLASH->ACR), FLASH_ACR_ACC64))\r
+\r
+/**\r
+ * @brief Enable the FLASH prefetch buffer.\r
+ * @retval none\r
+ */ \r
+#define __HAL_FLASH_PREFETCH_BUFFER_ENABLE() do { __HAL_FLASH_ACC64_ENABLE(); \\r
+ SET_BIT((FLASH->ACR), FLASH_ACR_PRFTEN); \\r
+ } while(0U)\r
+\r
+/**\r
+ * @brief Disable the FLASH prefetch buffer.\r
+ * @retval none\r
+ */ \r
+#define __HAL_FLASH_PREFETCH_BUFFER_DISABLE() CLEAR_BIT((FLASH->ACR), FLASH_ACR_PRFTEN)\r
+\r
+/**\r
+ * @brief Enable the FLASH power down during Sleep mode\r
+ * @retval none\r
+ */ \r
+#define __HAL_FLASH_SLEEP_POWERDOWN_ENABLE() SET_BIT(FLASH->ACR, FLASH_ACR_SLEEP_PD)\r
+\r
+/**\r
+ * @brief Disable the FLASH power down during Sleep mode\r
+ * @retval none\r
+ */ \r
+#define __HAL_FLASH_SLEEP_POWERDOWN_DISABLE() CLEAR_BIT(FLASH->ACR, FLASH_ACR_SLEEP_PD)\r
+\r
+/**\r
+ * @brief Enable the Flash Run power down mode.\r
+ * @note Writing this bit to 0 this bit, automatically the keys are\r
+ * loss and a new unlock sequence is necessary to re-write it to 1.\r
+ */\r
+#define __HAL_FLASH_POWER_DOWN_ENABLE() do { FLASH->PDKEYR = FLASH_PDKEY1; \\r
+ FLASH->PDKEYR = FLASH_PDKEY2; \\r
+ SET_BIT((FLASH->ACR), FLASH_ACR_RUN_PD); \\r
+ } while (0U)\r
+\r
+/**\r
+ * @brief Disable the Flash Run power down mode.\r
+ * @note Writing this bit to 0 this bit, automatically the keys are\r
+ * loss and a new unlock sequence is necessary to re-write it to 1.\r
+ */\r
+#define __HAL_FLASH_POWER_DOWN_DISABLE() do { FLASH->PDKEYR = FLASH_PDKEY1; \\r
+ FLASH->PDKEYR = FLASH_PDKEY2; \\r
+ CLEAR_BIT((FLASH->ACR), FLASH_ACR_RUN_PD); \\r
+ } while (0U)\r
+ \r
+/**\r
+ * @}\r
+ */\r
+\r
+/* Exported functions --------------------------------------------------------*/\r
+\r
+/** @addtogroup FLASHEx_Exported_Functions\r
+ * @{\r
+ */\r
+\r
+/** @addtogroup FLASHEx_Exported_Functions_Group1\r
+ * @{\r
+ */\r
+\r
+HAL_StatusTypeDef HAL_FLASHEx_Erase(FLASH_EraseInitTypeDef *pEraseInit, uint32_t *PageError);\r
+HAL_StatusTypeDef HAL_FLASHEx_Erase_IT(FLASH_EraseInitTypeDef *pEraseInit);\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @addtogroup FLASHEx_Exported_Functions_Group2\r
+ * @{\r
+ */\r
+\r
+HAL_StatusTypeDef HAL_FLASHEx_OBProgram(FLASH_OBProgramInitTypeDef *pOBInit);\r
+void HAL_FLASHEx_OBGetConfig(FLASH_OBProgramInitTypeDef *pOBInit);\r
+\r
+#if defined(FLASH_OBR_SPRMOD) || defined(FLASH_OBR_nRST_BFB2)\r
+ \r
+HAL_StatusTypeDef HAL_FLASHEx_AdvOBProgram (FLASH_AdvOBProgramInitTypeDef *pAdvOBInit);\r
+void HAL_FLASHEx_AdvOBGetConfig(FLASH_AdvOBProgramInitTypeDef *pAdvOBInit);\r
+\r
+#endif /* FLASH_OBR_SPRMOD || FLASH_OBR_nRST_BFB2 */\r
+\r
+#if defined(FLASH_OBR_SPRMOD)\r
+\r
+HAL_StatusTypeDef HAL_FLASHEx_OB_SelectPCROP(void);\r
+HAL_StatusTypeDef HAL_FLASHEx_OB_DeSelectPCROP(void);\r
+\r
+#endif /* FLASH_OBR_SPRMOD */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @addtogroup FLASHEx_Exported_Functions_Group3\r
+ * @{\r
+ */\r
+\r
+HAL_StatusTypeDef HAL_FLASHEx_DATAEEPROM_Unlock(void);\r
+HAL_StatusTypeDef HAL_FLASHEx_DATAEEPROM_Lock(void);\r
+\r
+HAL_StatusTypeDef HAL_FLASHEx_DATAEEPROM_Erase(uint32_t TypeErase, uint32_t Address);\r
+HAL_StatusTypeDef HAL_FLASHEx_DATAEEPROM_Program(uint32_t TypeProgram, uint32_t Address, uint32_t Data);\r
+void HAL_FLASHEx_DATAEEPROM_EnableFixedTimeProgram(void);\r
+void HAL_FLASHEx_DATAEEPROM_DisableFixedTimeProgram(void);\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/**\r
+ * @}\r
+ */ \r
+\r
+#ifdef __cplusplus\r
+}\r
+#endif\r
+\r
+#endif /* __STM32L1xx_HAL_FLASH_EX_H */\r
+\r
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\r
--- /dev/null
+/**\r
+ ******************************************************************************\r
+ * @file stm32l1xx_hal_flash_ramfunc.h\r
+ * @author MCD Application Team\r
+ * @brief Header file of FLASH RAMFUNC driver.\r
+ ******************************************************************************\r
+ * @attention\r
+ *\r
+ * <h2><center>© Copyright (c) 2017 STMicroelectronics.\r
+ * All rights reserved.</center></h2>\r
+ *\r
+ * This software component is licensed by ST under BSD 3-Clause license,\r
+ * the "License"; You may not use this file except in compliance with the\r
+ * License. You may obtain a copy of the License at:\r
+ * opensource.org/licenses/BSD-3-Clause\r
+ *\r
+ ******************************************************************************\r
+ */ \r
+\r
+/* Define to prevent recursive inclusion -------------------------------------*/\r
+#ifndef __STM32L1xx_FLASH_RAMFUNC_H\r
+#define __STM32L1xx_FLASH_RAMFUNC_H\r
+\r
+#ifdef __cplusplus\r
+ extern "C" {\r
+#endif\r
+\r
+/* Includes ------------------------------------------------------------------*/\r
+#include "stm32l1xx_hal_def.h"\r
+\r
+/** @addtogroup STM32L1xx_HAL_Driver\r
+ * @{\r
+ */\r
+\r
+/** @addtogroup FLASH_RAMFUNC\r
+ * @{\r
+ */ \r
+\r
+/* Exported types ------------------------------------------------------------*/ \r
+\r
+\r
+/* Exported functions --------------------------------------------------------*/\r
+\r
+/** @addtogroup FLASH_RAMFUNC_Exported_Functions\r
+ * @{\r
+ */\r
+\r
+/*\r
+ * @brief FLASH memory functions that should be executed from internal SRAM.\r
+ * These functions are defined inside the "stm32l1xx_hal_flash_ramfunc.c"\r
+ * file.\r
+ */\r
+ \r
+/** @addtogroup FLASH_RAMFUNC_Exported_Functions_Group1\r
+ * @{\r
+ */\r
+\r
+__RAM_FUNC HAL_StatusTypeDef HAL_FLASHEx_EnableRunPowerDown(void);\r
+__RAM_FUNC HAL_StatusTypeDef HAL_FLASHEx_DisableRunPowerDown(void);\r
+\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/** @addtogroup FLASH_RAMFUNC_Exported_Functions_Group2\r
+ * @{\r
+ */\r
+\r
+#if defined(FLASH_PECR_PARALLBANK)\r
+\r
+__RAM_FUNC HAL_StatusTypeDef HAL_FLASHEx_EraseParallelPage(uint32_t Page_Address1, uint32_t Page_Address2);\r
+__RAM_FUNC HAL_StatusTypeDef HAL_FLASHEx_ProgramParallelHalfPage(uint32_t Address1, uint32_t* pBuffer1, uint32_t Address2, uint32_t* pBuffer2);\r
+\r
+#endif /* FLASH_PECR_PARALLBANK */\r
+\r
+__RAM_FUNC HAL_StatusTypeDef HAL_FLASHEx_HalfPageProgram(uint32_t Address, uint32_t* pBuffer);\r
+\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/** @addtogroup FLASH_RAMFUNC_Exported_Functions_Group3\r
+ * @{\r
+ */\r
+__RAM_FUNC HAL_StatusTypeDef HAL_FLASHEx_GetError(uint32_t *Error);\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/** @addtogroup FLASH_RAMFUNC_Exported_Functions_Group4\r
+ * @{\r
+ */\r
+\r
+__RAM_FUNC HAL_StatusTypeDef HAL_FLASHEx_DATAEEPROM_EraseDoubleWord(uint32_t Address);\r
+__RAM_FUNC HAL_StatusTypeDef HAL_FLASHEx_DATAEEPROM_ProgramDoubleWord(uint32_t Address, uint64_t Data);\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+#ifdef __cplusplus\r
+}\r
+#endif\r
+\r
+#endif /* __STM32L1xx_FLASH_RAMFUNC_H */\r
+\r
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\r
--- /dev/null
+/**\r
+ ******************************************************************************\r
+ * @file stm32l1xx_hal_gpio.h\r
+ * @author MCD Application Team\r
+ * @brief Header file of GPIO HAL module.\r
+ ******************************************************************************\r
+ * @attention\r
+ *\r
+ * <h2><center>© Copyright (c) 2017 STMicroelectronics.\r
+ * All rights reserved.</center></h2>\r
+ *\r
+ * This software component is licensed by ST under BSD 3-Clause license,\r
+ * the "License"; You may not use this file except in compliance with the\r
+ * License. You may obtain a copy of the License at:\r
+ * opensource.org/licenses/BSD-3-Clause\r
+ *\r
+ ******************************************************************************\r
+ */ \r
+\r
+/* Define to prevent recursive inclusion -------------------------------------*/\r
+#ifndef __STM32L1xx_HAL_GPIO_H\r
+#define __STM32L1xx_HAL_GPIO_H\r
+\r
+#ifdef __cplusplus\r
+ extern "C" {\r
+#endif\r
+\r
+/* Includes ------------------------------------------------------------------*/\r
+#include "stm32l1xx_hal_def.h"\r
+\r
+/** @addtogroup STM32L1xx_HAL_Driver\r
+ * @{\r
+ */\r
+\r
+/** @defgroup GPIO GPIO\r
+ * @brief GPIO HAL module driver\r
+ * @{\r
+ */ \r
+\r
+/* Exported types ------------------------------------------------------------*/ \r
+\r
+/** @defgroup GPIO_Exported_Types GPIO Exported Types\r
+ * @{\r
+ */\r
+/** \r
+ * @brief GPIO Init structure definition \r
+ */\r
+typedef struct\r
+{\r
+ uint32_t Pin; /*!< Specifies the GPIO pins to be configured.\r
+ This parameter can be any value of @ref GPIO_pins */\r
+\r
+ uint32_t Mode; /*!< Specifies the operating mode for the selected pins.\r
+ This parameter can be a value of @ref GPIO_mode */\r
+\r
+ uint32_t Pull; /*!< Specifies the Pull-up or Pull-Down activation for the selected pins.\r
+ This parameter can be a value of @ref GPIO_pull */\r
+\r
+ uint32_t Speed; /*!< Specifies the speed for the selected pins.\r
+ This parameter can be a value of @ref GPIO_speed */\r
+\r
+ uint32_t Alternate; /*!< Peripheral to be connected to the selected pins \r
+ This parameter can be a value of @ref GPIOEx_Alternate_function_selection */\r
+}GPIO_InitTypeDef;\r
+\r
+/** \r
+ * @brief GPIO Bit SET and Bit RESET enumeration \r
+ */\r
+typedef enum\r
+{\r
+ GPIO_PIN_RESET = 0,\r
+ GPIO_PIN_SET\r
+}GPIO_PinState;\r
+/**\r
+ * @}\r
+ */\r
+ \r
+/* Exported constants --------------------------------------------------------*/\r
+\r
+/** @defgroup GPIO_Exported_Constants GPIO Exported Constants\r
+ * @{\r
+ */\r
+\r
+\r
+/** @defgroup GPIO_pins GPIO pins\r
+ * @{\r
+ */\r
+#define GPIO_PIN_0 ((uint16_t)0x0001U) /* Pin 0 selected */\r
+#define GPIO_PIN_1 ((uint16_t)0x0002U) /* Pin 1 selected */\r
+#define GPIO_PIN_2 ((uint16_t)0x0004U) /* Pin 2 selected */\r
+#define GPIO_PIN_3 ((uint16_t)0x0008U) /* Pin 3 selected */\r
+#define GPIO_PIN_4 ((uint16_t)0x0010U) /* Pin 4 selected */\r
+#define GPIO_PIN_5 ((uint16_t)0x0020U) /* Pin 5 selected */\r
+#define GPIO_PIN_6 ((uint16_t)0x0040U) /* Pin 6 selected */\r
+#define GPIO_PIN_7 ((uint16_t)0x0080U) /* Pin 7 selected */\r
+#define GPIO_PIN_8 ((uint16_t)0x0100U) /* Pin 8 selected */\r
+#define GPIO_PIN_9 ((uint16_t)0x0200U) /* Pin 9 selected */\r
+#define GPIO_PIN_10 ((uint16_t)0x0400U) /* Pin 10 selected */\r
+#define GPIO_PIN_11 ((uint16_t)0x0800U) /* Pin 11 selected */\r
+#define GPIO_PIN_12 ((uint16_t)0x1000U) /* Pin 12 selected */\r
+#define GPIO_PIN_13 ((uint16_t)0x2000U) /* Pin 13 selected */\r
+#define GPIO_PIN_14 ((uint16_t)0x4000U) /* Pin 14 selected */\r
+#define GPIO_PIN_15 ((uint16_t)0x8000U) /* Pin 15 selected */\r
+#define GPIO_PIN_All ((uint16_t)0xFFFFU) /* All pins selected */\r
+\r
+#define GPIO_PIN_MASK (0x0000FFFFU) /* PIN mask for assert test */\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup GPIO_mode GPIO mode\r
+ * @brief GPIO Configuration Mode \r
+ * Elements values convention: 0xX0yz00YZ\r
+ * - X : GPIO mode or EXTI Mode\r
+ * - y : External IT or Event trigger detection \r
+ * - z : IO configuration on External IT or Event\r
+ * - Y : Output type (Push Pull or Open Drain)\r
+ * - Z : IO Direction mode (Input, Output, Alternate or Analog)\r
+ * @{\r
+ */ \r
+#define GPIO_MODE_INPUT (0x00000000U) /*!< Input Floating Mode */\r
+#define GPIO_MODE_OUTPUT_PP (0x00000001U) /*!< Output Push Pull Mode */\r
+#define GPIO_MODE_OUTPUT_OD (0x00000011U) /*!< Output Open Drain Mode */\r
+#define GPIO_MODE_AF_PP (0x00000002U) /*!< Alternate Function Push Pull Mode */\r
+#define GPIO_MODE_AF_OD (0x00000012U) /*!< Alternate Function Open Drain Mode */\r
+\r
+#define GPIO_MODE_ANALOG (0x00000003U) /*!< Analog Mode */\r
+ \r
+#define GPIO_MODE_IT_RISING (0x10110000U) /*!< External Interrupt Mode with Rising edge trigger detection */\r
+#define GPIO_MODE_IT_FALLING (0x10210000U) /*!< External Interrupt Mode with Falling edge trigger detection */\r
+#define GPIO_MODE_IT_RISING_FALLING (0x10310000U) /*!< External Interrupt Mode with Rising/Falling edge trigger detection */\r
+\r
+#define GPIO_MODE_EVT_RISING (0x10120000U) /*!< External Event Mode with Rising edge trigger detection */\r
+#define GPIO_MODE_EVT_FALLING (0x10220000U) /*!< External Event Mode with Falling edge trigger detection */\r
+#define GPIO_MODE_EVT_RISING_FALLING (0x10320000U) /*!< External Event Mode with Rising/Falling edge trigger detection */\r
+\r
+/**\r
+ * @}\r
+ */\r
+ \r
+/** @defgroup GPIO_speed GPIO speed\r
+ * @brief GPIO Output Maximum frequency\r
+ * @{\r
+ */ \r
+#define GPIO_SPEED_FREQ_LOW (0x00000000U) /*!< max: 400 KHz, please refer to the product datasheet */\r
+#define GPIO_SPEED_FREQ_MEDIUM (0x00000001U) /*!< max: 1 MHz to 2 MHz, please refer to the product datasheet */\r
+#define GPIO_SPEED_FREQ_HIGH (0x00000002U) /*!< max: 2 MHz to 10 MHz, please refer to the product datasheet */\r
+#define GPIO_SPEED_FREQ_VERY_HIGH (0x00000003U) /*!< max: 8 MHz to 50 MHz, please refer to the product datasheet */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+ /** @defgroup GPIO_pull GPIO pull\r
+ * @brief GPIO Pull-Up or Pull-Down Activation\r
+ * @{\r
+ */ \r
+#define GPIO_NOPULL (0x00000000U) /*!< No Pull-up or Pull-down activation */\r
+#define GPIO_PULLUP (0x00000001U) /*!< Pull-up activation */\r
+#define GPIO_PULLDOWN (0x00000002U) /*!< Pull-down activation */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/* Private constants ---------------------------------------------------------*/\r
+/** @defgroup GPIO_Private_Constants GPIO Private Constants\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/* Private macros --------------------------------------------------------*/\r
+/** @defgroup GPIO_Private_Macros GPIO Private Macros\r
+ * @{\r
+ */\r
+\r
+#define IS_GPIO_PIN_ACTION(ACTION) (((ACTION) == GPIO_PIN_RESET) || ((ACTION) == GPIO_PIN_SET))\r
+\r
+#define IS_GPIO_PIN(__PIN__) ((((uint32_t)(__PIN__) & GPIO_PIN_MASK) != 0x00U) &&\\r
+ (((uint32_t)(__PIN__) & ~GPIO_PIN_MASK) == 0x00U))\r
+\r
+#define IS_GPIO_PULL(PULL) (((PULL) == GPIO_NOPULL) || ((PULL) == GPIO_PULLUP) || \\r
+ ((PULL) == GPIO_PULLDOWN))\r
+ \r
+#define IS_GPIO_SPEED(SPEED) (((SPEED) == GPIO_SPEED_FREQ_LOW) || ((SPEED) == GPIO_SPEED_FREQ_MEDIUM) || \\r
+ ((SPEED) == GPIO_SPEED_FREQ_HIGH) || ((SPEED) == GPIO_SPEED_FREQ_VERY_HIGH))\r
+\r
+#define IS_GPIO_MODE(MODE) (((MODE) == GPIO_MODE_INPUT) ||\\r
+ ((MODE) == GPIO_MODE_OUTPUT_PP) ||\\r
+ ((MODE) == GPIO_MODE_OUTPUT_OD) ||\\r
+ ((MODE) == GPIO_MODE_AF_PP) ||\\r
+ ((MODE) == GPIO_MODE_AF_OD) ||\\r
+ ((MODE) == GPIO_MODE_IT_RISING) ||\\r
+ ((MODE) == GPIO_MODE_IT_FALLING) ||\\r
+ ((MODE) == GPIO_MODE_IT_RISING_FALLING) ||\\r
+ ((MODE) == GPIO_MODE_EVT_RISING) ||\\r
+ ((MODE) == GPIO_MODE_EVT_FALLING) ||\\r
+ ((MODE) == GPIO_MODE_EVT_RISING_FALLING) ||\\r
+ ((MODE) == GPIO_MODE_ANALOG))\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/* Exported macro ------------------------------------------------------------*/\r
+\r
+/** @defgroup GPIO_Exported_Macros GPIO Exported Macros\r
+ * @{\r
+ */\r
+ \r
+/**\r
+ * @brief Checks whether the specified EXTI line flag is set or not.\r
+ * @param __EXTI_LINE__ specifies the EXTI line flag to check.\r
+ * This parameter can be GPIO_PIN_x where x can be(0..15)\r
+ * @retval The new state of __EXTI_LINE__ (SET or RESET).\r
+ */\r
+#define __HAL_GPIO_EXTI_GET_FLAG(__EXTI_LINE__) (EXTI->PR & (__EXTI_LINE__))\r
+\r
+/**\r
+ * @brief Clears the EXTI's line pending flags.\r
+ * @param __EXTI_LINE__ specifies the EXTI lines flags to clear.\r
+ * This parameter can be any combination of GPIO_PIN_x where x can be (0..15)\r
+ * @retval None\r
+ */\r
+#define __HAL_GPIO_EXTI_CLEAR_FLAG(__EXTI_LINE__) (EXTI->PR = (__EXTI_LINE__))\r
+\r
+/**\r
+ * @brief Checks whether the specified EXTI line is asserted or not.\r
+ * @param __EXTI_LINE__ specifies the EXTI line to check.\r
+ * This parameter can be GPIO_PIN_x where x can be(0..15)\r
+ * @retval The new state of __EXTI_LINE__ (SET or RESET).\r
+ */\r
+#define __HAL_GPIO_EXTI_GET_IT(__EXTI_LINE__) (EXTI->PR & (__EXTI_LINE__))\r
+\r
+/**\r
+ * @brief Clears the EXTI's line pending bits.\r
+ * @param __EXTI_LINE__ specifies the EXTI lines to clear.\r
+ * This parameter can be any combination of GPIO_PIN_x where x can be (0..15)\r
+ * @retval None\r
+ */\r
+#define __HAL_GPIO_EXTI_CLEAR_IT(__EXTI_LINE__) (EXTI->PR = (__EXTI_LINE__))\r
+\r
+/**\r
+ * @brief Generates a Software interrupt on selected EXTI line.\r
+ * @param __EXTI_LINE__ specifies the EXTI line to check.\r
+ * This parameter can be GPIO_PIN_x where x can be(0..15)\r
+ * @retval None\r
+ */\r
+#define __HAL_GPIO_EXTI_GENERATE_SWIT(__EXTI_LINE__) (EXTI->SWIER |= (__EXTI_LINE__))\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/* Include GPIO HAL Extension module */\r
+#include "stm32l1xx_hal_gpio_ex.h"\r
+\r
+/* Exported functions --------------------------------------------------------*/ \r
+/** @defgroup GPIO_Exported_Functions GPIO Exported Functions\r
+ * @brief GPIO Exported Functions\r
+ * @{\r
+ */\r
+\r
+/** @defgroup GPIO_Exported_Functions_Group1 Initialization and Configuration functions\r
+ * @brief Initialization and Configuration functions\r
+ * @{\r
+ */\r
+ \r
+/* Initialization and de-initialization functions *****************************/\r
+void HAL_GPIO_Init(GPIO_TypeDef *GPIOx, GPIO_InitTypeDef *GPIO_Init);\r
+void HAL_GPIO_DeInit(GPIO_TypeDef *GPIOx, uint32_t GPIO_Pin);\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup GPIO_Exported_Functions_Group2 IO operation functions \r
+ * @brief IO operation functions\r
+ * @{\r
+ */\r
+ \r
+/* IO operation functions *****************************************************/\r
+GPIO_PinState HAL_GPIO_ReadPin(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin);\r
+void HAL_GPIO_WritePin(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin, GPIO_PinState PinState);\r
+void HAL_GPIO_TogglePin(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin);\r
+HAL_StatusTypeDef HAL_GPIO_LockPin(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin);\r
+void HAL_GPIO_EXTI_IRQHandler(uint16_t GPIO_Pin);\r
+void HAL_GPIO_EXTI_Callback(uint16_t GPIO_Pin);\r
+\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/**\r
+ * @}\r
+ */ \r
+ \r
+#ifdef __cplusplus\r
+}\r
+#endif\r
+\r
+#endif /* __STM32L1xx_HAL_GPIO_H */\r
+\r
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\r
+\r
--- /dev/null
+/**\r
+ ******************************************************************************\r
+ * @file stm32l1xx_hal_gpio_ex.h\r
+ * @author MCD Application Team\r
+ * @brief Header file of GPIO HAL Extension module.\r
+ ******************************************************************************\r
+ * @attention\r
+ *\r
+ * <h2><center>© Copyright (c) 2017 STMicroelectronics.\r
+ * All rights reserved.</center></h2>\r
+ *\r
+ * This software component is licensed by ST under BSD 3-Clause license,\r
+ * the "License"; You may not use this file except in compliance with the\r
+ * License. You may obtain a copy of the License at:\r
+ * opensource.org/licenses/BSD-3-Clause\r
+ *\r
+ ******************************************************************************\r
+ */ \r
+\r
+/* Define to prevent recursive inclusion -------------------------------------*/\r
+#ifndef __STM32L1xx_HAL_GPIO_EX_H\r
+#define __STM32L1xx_HAL_GPIO_EX_H\r
+\r
+#ifdef __cplusplus\r
+ extern "C" {\r
+#endif\r
+\r
+/* Includes ------------------------------------------------------------------*/\r
+#include "stm32l1xx_hal_def.h"\r
+\r
+/** @addtogroup STM32L1xx_HAL_Driver\r
+ * @{\r
+ */\r
+\r
+/** @defgroup GPIOEx GPIOEx\r
+ * @{\r
+ */ \r
+\r
+/* Exported types ------------------------------------------------------------*/\r
+/* Exported constants --------------------------------------------------------*/\r
+/** @defgroup GPIOEx_Exported_Constants GPIOEx Exported Constants\r
+ * @{\r
+ */ \r
+ \r
+/** @defgroup GPIOEx_Alternate_function_selection GPIOEx Alternate function selection\r
+ * @{\r
+ */\r
+ \r
+/* AF 0 selection */ \r
+#define GPIO_AF0_MCO ((uint8_t)0x00) /*!< MCO Alternate Function mapping */\r
+#define GPIO_AF0_TAMPER ((uint8_t)0x00) /*!< TAMPER Alternate Function mapping */\r
+#define GPIO_AF0_SWJ ((uint8_t)0x00) /*!< SWJ (SWD and JTAG) Alternate Function mapping */\r
+#define GPIO_AF0_TRACE ((uint8_t)0x00) /*!< TRACE Alternate Function mapping */\r
+#define GPIO_AF0_RTC_50Hz ((uint8_t)0x00) /*!< RTC_OUT Alternate Function mapping */\r
+ \r
+/* AF 1 selection */ \r
+#define GPIO_AF1_TIM2 ((uint8_t)0x01) /*!< TIM2 Alternate Function mapping */\r
+\r
+/* AF 2 selection */ \r
+#define GPIO_AF2_TIM3 ((uint8_t)0x02) /*!< TIM3 Alternate Function mapping */\r
+#define GPIO_AF2_TIM4 ((uint8_t)0x02) /*!< TIM4 Alternate Function mapping */\r
+#if defined (STM32L151xCA) || defined (STM32L151xD) || defined (STM32L152xCA) || defined (STM32L152xD) || defined (STM32L162xCA) || defined (STM32L162xD) || defined (STM32L151xE) || defined (STM32L151xDX) || defined (STM32L152xE) || defined (STM32L152xDX) || defined (STM32L162xE) || defined (STM32L162xDX) || defined (STM32L162xC) || defined (STM32L152xC) || defined (STM32L151xC)\r
+#define GPIO_AF2_TIM5 ((uint8_t)0x02) /*!< TIM5 Alternate Function mapping */\r
+\r
+#endif /* STM32L151xCA || STM32L151xD || STM32L152xCA || STM32L152xD || STM32L162xCA || STM32L162xD ...STM32L151xC */ \r
+\r
+/* AF 3 selection */ \r
+#define GPIO_AF3_TIM9 ((uint8_t)0x03) /*!< TIM9 Alternate Function mapping */\r
+#define GPIO_AF3_TIM10 ((uint8_t)0x03) /*!< TIM10 Alternate Function mapping */\r
+#define GPIO_AF3_TIM11 ((uint8_t)0x03) /*!< TIM11 Alternate Function mapping */\r
+\r
+\r
+/* AF 4 selection */ \r
+#define GPIO_AF4_I2C1 ((uint8_t)0x04) /*!< I2C1 Alternate Function mapping */\r
+#define GPIO_AF4_I2C2 ((uint8_t)0x04) /*!< I2C2 Alternate Function mapping */\r
+\r
+/* AF 5 selection */ \r
+#define GPIO_AF5_SPI1 ((uint8_t)0x05) /*!< SPI1/I2S1 Alternate Function mapping */\r
+#define GPIO_AF5_SPI2 ((uint8_t)0x05) /*!< SPI2/I2S2 Alternate Function mapping */\r
+\r
+/* AF 6 selection */ \r
+#if defined (STM32L100xC) || defined (STM32L151xC) || defined (STM32L151xCA) || defined (STM32L151xD) || defined (STM32L151xE) || defined (STM32L151xDX) ||\\r
+ defined (STM32L152xC) || defined (STM32L152xCA) || defined (STM32L152xD) || defined (STM32L152xE) || defined (STM32L152xDX) ||\\r
+ defined (STM32L162xC) || defined (STM32L162xCA) || defined (STM32L162xD) || defined (STM32L162xE) || defined (STM32L162xDX)\r
+ \r
+#define GPIO_AF6_SPI3 ((uint8_t)0x06) /*!< SPI3/I2S3 Alternate Function mapping */\r
+\r
+#endif /* STM32L100xC || STM32L151xC || (...) || STM32L162xD || STM32L162xE || STM32L162xDX */\r
+\r
+\r
+/* AF 7 selection */ \r
+#define GPIO_AF7_USART1 ((uint8_t)0x07) /*!< USART1 Alternate Function mapping */\r
+#define GPIO_AF7_USART2 ((uint8_t)0x07) /*!< USART2 Alternate Function mapping */\r
+#define GPIO_AF7_USART3 ((uint8_t)0x07) /*!< USART3 Alternate Function mapping */\r
+\r
+/* AF 8 selection */ \r
+#if defined (STM32L151xD) || defined (STM32L151xE) || defined (STM32L151xDX) ||\\r
+ defined (STM32L152xD) || defined (STM32L152xE) || defined (STM32L152xDX) ||\\r
+ defined (STM32L162xD) || defined (STM32L162xE) || defined (STM32L162xDX)\r
+ \r
+#define GPIO_AF8_UART4 ((uint8_t)0x08) /*!< UART4 Alternate Function mapping */\r
+#define GPIO_AF8_UART5 ((uint8_t)0x08) /*!< UART5 Alternate Function mapping */\r
+\r
+#endif /* STM32L151xD || STM32L151xE || STM32L151xDX || STM32L152xD || STM32L 152xE || STM32L162xD || STM32L162xE || STM32L162xDX */\r
+\r
+\r
+/* AF 9 selection */ \r
+\r
+/* AF 10 selection */ \r
+\r
+/* AF 11 selection */ \r
+#if defined (STM32L100xB) || defined (STM32L100xBA) || defined (STM32L100xC) ||\\r
+ defined (STM32L152xB) || defined (STM32L152xBA) || defined (STM32L152xC) || defined (STM32L152xCA) || defined (STM32L152xD) || defined (STM32L152xE) || defined (STM32L152xDX) ||\\r
+ defined (STM32L162xC) || defined (STM32L162xCA) || defined (STM32L162xD) || defined (STM32L162xE) || defined (STM32L162xDX)\r
+\r
+#define GPIO_AF11_LCD ((uint8_t)0x0B) /*!< LCD Alternate Function mapping */\r
+\r
+#endif /* STM32L100xB || STM32L100xBA || STM32L100xC || (...) || STM32L162xCA || STM32L162xD || STM32L162xE || STM32L162xDX */\r
+\r
+/* AF 12 selection */ \r
+#if defined (STM32L151xD) || defined (STM32L152xD) || defined (STM32L162xD)\r
+ \r
+#define GPIO_AF12_FSMC ((uint8_t)0x0C) /*!< FSMC Alternate Function mapping */\r
+#define GPIO_AF12_SDIO ((uint8_t)0x0C) /*!< SDIO Alternate Function mapping */\r
+\r
+#endif /* STM32L151xD || STM32L152xD || STM32L162xD */\r
+/* AF 13 selection */ \r
+\r
+/* AF 14 selection */ \r
+#define GPIO_AF14_TIM_IC1 ((uint8_t)0x0E) /*!< TIMER INPUT CAPTURE Alternate Function mapping */\r
+#define GPIO_AF14_TIM_IC2 ((uint8_t)0x0E) /*!< TIMER INPUT CAPTURE Alternate Function mapping */\r
+#define GPIO_AF14_TIM_IC3 ((uint8_t)0x0E) /*!< TIMER INPUT CAPTURE Alternate Function mapping */\r
+#define GPIO_AF14_TIM_IC4 ((uint8_t)0x0E) /*!< TIMER INPUT CAPTURE Alternate Function mapping */\r
+\r
+/* AF 15 selection */ \r
+#define GPIO_AF15_EVENTOUT ((uint8_t)0x0F) /*!< EVENTOUT Alternate Function mapping */\r
+\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup GPIOEx_Private_Macros GPIOEx Private Macros\r
+ * @{\r
+ */\r
+\r
+\r
+#define IS_GPIO_AF(AF) ((AF) <= (uint8_t)0x0F)\r
+\r
+\r
+#if defined (STM32L151xCA) || defined (STM32L151xD) || defined (STM32L152xCA) || defined (STM32L152xD) || defined (STM32L162xCA) || defined (STM32L162xD) || defined (STM32L151xE) || defined (STM32L151xDX) || defined (STM32L152xE) || defined (STM32L152xDX) || defined (STM32L162xE) || defined (STM32L162xDX)\r
+#define GPIO_GET_INDEX(__GPIOx__) (((__GPIOx__) == (GPIOA))? 0U :\\r
+ ((__GPIOx__) == (GPIOB))? 1U :\\r
+ ((__GPIOx__) == (GPIOC))? 2U :\\r
+ ((__GPIOx__) == (GPIOD))? 3U :\\r
+ ((__GPIOx__) == (GPIOE))? 4U :\\r
+ ((__GPIOx__) == (GPIOH))? 5U :\\r
+ ((__GPIOx__) == (GPIOF))? 6U : 7U)\r
+#endif \r
+\r
+#if defined (STM32L151xB) || defined (STM32L151xBA) || defined (STM32L151xC) || defined (STM32L152xB) || defined (STM32L152xBA) || defined (STM32L152xC) || defined (STM32L162xC)\r
+#define GPIO_GET_INDEX(__GPIOx__) (((__GPIOx__) == (GPIOA))? 0U :\\r
+ ((__GPIOx__) == (GPIOB))? 1U :\\r
+ ((__GPIOx__) == (GPIOC))? 2U :\\r
+ ((__GPIOx__) == (GPIOD))? 3U :\\r
+ ((__GPIOx__) == (GPIOE))? 4U : 5U)\r
+#endif \r
+\r
+#if defined (STM32L100xB) || defined (STM32L100xBA) || defined (STM32L100xC)\r
+#define GPIO_GET_INDEX(__GPIOx__) (((__GPIOx__) == (GPIOA))? 0U :\\r
+ ((__GPIOx__) == (GPIOB))? 1U :\\r
+ ((__GPIOx__) == (GPIOC))? 2U :\\r
+ ((__GPIOx__) == (GPIOD))? 3U : 5U)\r
+#endif \r
+\r
+\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+\r
+\r
+/* Exported macro ------------------------------------------------------------*/\r
+/* Exported functions --------------------------------------------------------*/ \r
+\r
+\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/**\r
+ * @}\r
+ */ \r
+ \r
+#ifdef __cplusplus\r
+}\r
+#endif\r
+\r
+#endif /* __STM32L1xx_HAL_GPIO_EX_H */\r
+\r
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\r
--- /dev/null
+/**\r
+ ******************************************************************************\r
+ * @file stm32l1xx_hal_pwr.h\r
+ * @author MCD Application Team\r
+ * @brief Header file of PWR HAL module.\r
+ ******************************************************************************\r
+ * @attention\r
+ *\r
+ * <h2><center>© Copyright (c) 2017 STMicroelectronics.\r
+ * All rights reserved.</center></h2>\r
+ *\r
+ * This software component is licensed by ST under BSD 3-Clause license,\r
+ * the "License"; You may not use this file except in compliance with the\r
+ * License. You may obtain a copy of the License at:\r
+ * opensource.org/licenses/BSD-3-Clause\r
+ *\r
+ ******************************************************************************\r
+ */\r
+\r
+/* Define to prevent recursive inclusion -------------------------------------*/\r
+#ifndef __STM32L1xx_HAL_PWR_H\r
+#define __STM32L1xx_HAL_PWR_H\r
+\r
+#ifdef __cplusplus\r
+ extern "C" {\r
+#endif\r
+\r
+/* Includes ------------------------------------------------------------------*/\r
+#include "stm32l1xx_hal_def.h"\r
+\r
+/** @addtogroup STM32L1xx_HAL_Driver\r
+ * @{\r
+ */\r
+\r
+/** @addtogroup PWR\r
+ * @{\r
+ */\r
+\r
+/* Exported types ------------------------------------------------------------*/\r
+\r
+/** @defgroup PWR_Exported_Types PWR Exported Types\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @brief PWR PVD configuration structure definition\r
+ */\r
+typedef struct\r
+{\r
+ uint32_t PVDLevel; /*!< PVDLevel: Specifies the PVD detection level.\r
+ This parameter can be a value of @ref PWR_PVD_detection_level */\r
+\r
+ uint32_t Mode; /*!< Mode: Specifies the operating mode for the selected pins.\r
+ This parameter can be a value of @ref PWR_PVD_Mode */\r
+}PWR_PVDTypeDef;\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/* Internal constants --------------------------------------------------------*/\r
+\r
+/** @addtogroup PWR_Private_Constants\r
+ * @{\r
+ */\r
+#define PWR_EXTI_LINE_PVD (0x00010000U) /*!< External interrupt line 16 Connected to the PVD EXTI Line */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+\r
+\r
+/* Exported constants --------------------------------------------------------*/\r
+\r
+/** @defgroup PWR_Exported_Constants PWR Exported Constants\r
+ * @{\r
+ */\r
+\r
+/** @defgroup PWR_register_alias_address PWR Register alias address\r
+ * @{\r
+ */\r
+/* ------------- PWR registers bit address in the alias region ---------------*/\r
+#define PWR_OFFSET (PWR_BASE - PERIPH_BASE)\r
+#define PWR_CR_OFFSET 0x00\r
+#define PWR_CSR_OFFSET 0x04\r
+#define PWR_CR_OFFSET_BB (PWR_OFFSET + PWR_CR_OFFSET)\r
+#define PWR_CSR_OFFSET_BB (PWR_OFFSET + PWR_CSR_OFFSET)\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup PWR_CR_register_alias PWR CR Register alias address\r
+ * @{\r
+ */\r
+/* --- CR Register ---*/\r
+/* Alias word address of LPSDSR bit */\r
+#define LPSDSR_BIT_NUMBER POSITION_VAL(PWR_CR_LPSDSR)\r
+#define CR_LPSDSR_BB ((uint32_t)(PERIPH_BB_BASE + (PWR_CR_OFFSET_BB * 32) + (LPSDSR_BIT_NUMBER * 4)))\r
+\r
+/* Alias word address of DBP bit */\r
+#define DBP_BIT_NUMBER POSITION_VAL(PWR_CR_DBP)\r
+#define CR_DBP_BB ((uint32_t)(PERIPH_BB_BASE + (PWR_CR_OFFSET_BB * 32) + (DBP_BIT_NUMBER * 4)))\r
+\r
+/* Alias word address of LPRUN bit */\r
+#define LPRUN_BIT_NUMBER POSITION_VAL(PWR_CR_LPRUN)\r
+#define CR_LPRUN_BB ((uint32_t)(PERIPH_BB_BASE + (PWR_CR_OFFSET_BB * 32) + (LPRUN_BIT_NUMBER * 4)))\r
+\r
+/* Alias word address of PVDE bit */\r
+#define PVDE_BIT_NUMBER POSITION_VAL(PWR_CR_PVDE)\r
+#define CR_PVDE_BB ((uint32_t)(PERIPH_BB_BASE + (PWR_CR_OFFSET_BB * 32) + (PVDE_BIT_NUMBER * 4)))\r
+\r
+/* Alias word address of FWU bit */\r
+#define FWU_BIT_NUMBER POSITION_VAL(PWR_CR_FWU)\r
+#define CR_FWU_BB ((uint32_t)(PERIPH_BB_BASE + (PWR_CR_OFFSET_BB * 32) + (FWU_BIT_NUMBER * 4)))\r
+\r
+/* Alias word address of ULP bit */\r
+#define ULP_BIT_NUMBER POSITION_VAL(PWR_CR_ULP)\r
+#define CR_ULP_BB ((uint32_t)(PERIPH_BB_BASE + (PWR_CR_OFFSET_BB * 32) + (ULP_BIT_NUMBER * 4)))\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup PWR_CSR_register_alias PWR CSR Register alias address\r
+ * @{\r
+ */\r
+\r
+/* --- CSR Register ---*/\r
+/* Alias word address of EWUP1, EWUP2 and EWUP3 bits */\r
+#define CSR_EWUP_BB(VAL) ((uint32_t)(PERIPH_BB_BASE + (PWR_CSR_OFFSET_BB * 32) + (POSITION_VAL(VAL) * 4)))\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup PWR_PVD_detection_level PWR PVD detection level\r
+ * @{\r
+ */\r
+#define PWR_PVDLEVEL_0 PWR_CR_PLS_LEV0\r
+#define PWR_PVDLEVEL_1 PWR_CR_PLS_LEV1\r
+#define PWR_PVDLEVEL_2 PWR_CR_PLS_LEV2\r
+#define PWR_PVDLEVEL_3 PWR_CR_PLS_LEV3\r
+#define PWR_PVDLEVEL_4 PWR_CR_PLS_LEV4\r
+#define PWR_PVDLEVEL_5 PWR_CR_PLS_LEV5\r
+#define PWR_PVDLEVEL_6 PWR_CR_PLS_LEV6\r
+#define PWR_PVDLEVEL_7 PWR_CR_PLS_LEV7 /* External input analog voltage\r
+ (Compare internally to VREFINT) */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup PWR_PVD_Mode PWR PVD Mode\r
+ * @{\r
+ */\r
+#define PWR_PVD_MODE_NORMAL (0x00000000U) /*!< basic mode is used */\r
+#define PWR_PVD_MODE_IT_RISING (0x00010001U) /*!< External Interrupt Mode with Rising edge trigger detection */\r
+#define PWR_PVD_MODE_IT_FALLING (0x00010002U) /*!< External Interrupt Mode with Falling edge trigger detection */\r
+#define PWR_PVD_MODE_IT_RISING_FALLING (0x00010003U) /*!< External Interrupt Mode with Rising/Falling edge trigger detection */\r
+#define PWR_PVD_MODE_EVENT_RISING (0x00020001U) /*!< Event Mode with Rising edge trigger detection */\r
+#define PWR_PVD_MODE_EVENT_FALLING (0x00020002U) /*!< Event Mode with Falling edge trigger detection */\r
+#define PWR_PVD_MODE_EVENT_RISING_FALLING (0x00020003U) /*!< Event Mode with Rising/Falling edge trigger detection */\r
+\r
+ /**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup PWR_Regulator_state_in_SLEEP_STOP_mode PWR Regulator state in SLEEP/STOP mode\r
+ * @{\r
+ */\r
+#define PWR_MAINREGULATOR_ON (0x00000000U)\r
+#define PWR_LOWPOWERREGULATOR_ON PWR_CR_LPSDSR\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup PWR_SLEEP_mode_entry PWR SLEEP mode entry\r
+ * @{\r
+ */\r
+#define PWR_SLEEPENTRY_WFI ((uint8_t)0x01)\r
+#define PWR_SLEEPENTRY_WFE ((uint8_t)0x02)\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup PWR_STOP_mode_entry PWR STOP mode entry\r
+ * @{\r
+ */\r
+#define PWR_STOPENTRY_WFI ((uint8_t)0x01)\r
+#define PWR_STOPENTRY_WFE ((uint8_t)0x02)\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup PWR_Regulator_Voltage_Scale PWR Regulator Voltage Scale\r
+ * @{\r
+ */\r
+\r
+#define PWR_REGULATOR_VOLTAGE_SCALE1 PWR_CR_VOS_0\r
+#define PWR_REGULATOR_VOLTAGE_SCALE2 PWR_CR_VOS_1\r
+#define PWR_REGULATOR_VOLTAGE_SCALE3 PWR_CR_VOS\r
+\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup PWR_Flag PWR Flag\r
+ * @{\r
+ */\r
+#define PWR_FLAG_WU PWR_CSR_WUF\r
+#define PWR_FLAG_SB PWR_CSR_SBF\r
+#define PWR_FLAG_PVDO PWR_CSR_PVDO\r
+#define PWR_FLAG_VREFINTRDY PWR_CSR_VREFINTRDYF\r
+#define PWR_FLAG_VOS PWR_CSR_VOSF\r
+#define PWR_FLAG_REGLP PWR_CSR_REGLPF\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/* Exported macro ------------------------------------------------------------*/\r
+/** @defgroup PWR_Exported_Macros PWR Exported Macros\r
+ * @{\r
+ */\r
+\r
+/** @brief macros configure the main internal regulator output voltage.\r
+ * @param __REGULATOR__ specifies the regulator output voltage to achieve\r
+ * a tradeoff between performance and power consumption when the device does\r
+ * not operate at the maximum frequency (refer to the datasheets for more details).\r
+ * This parameter can be one of the following values:\r
+ * @arg PWR_REGULATOR_VOLTAGE_SCALE1: Regulator voltage output Scale 1 mode,\r
+ * System frequency up to 32 MHz.\r
+ * @arg PWR_REGULATOR_VOLTAGE_SCALE2: Regulator voltage output Scale 2 mode,\r
+ * System frequency up to 16 MHz.\r
+ * @arg PWR_REGULATOR_VOLTAGE_SCALE3: Regulator voltage output Scale 3 mode,\r
+ * System frequency up to 4.2 MHz\r
+ * @retval None\r
+ */\r
+#define __HAL_PWR_VOLTAGESCALING_CONFIG(__REGULATOR__) (MODIFY_REG(PWR->CR, PWR_CR_VOS, (__REGULATOR__)))\r
+\r
+/** @brief Check PWR flag is set or not.\r
+ * @param __FLAG__ specifies the flag to check.\r
+ * This parameter can be one of the following values:\r
+ * @arg PWR_FLAG_WU: Wake Up flag. This flag indicates that a wakeup event\r
+ * was received from the WKUP pin or from the RTC alarm (Alarm B),\r
+ * RTC Tamper event, RTC TimeStamp event or RTC Wakeup.\r
+ * An additional wakeup event is detected if the WKUP pin is enabled\r
+ * (by setting the EWUP bit) when the WKUP pin level is already high.\r
+ * @arg PWR_FLAG_SB: StandBy flag. This flag indicates that the system was\r
+ * resumed from StandBy mode.\r
+ * @arg PWR_FLAG_PVDO: PVD Output. This flag is valid only if PVD is enabled\r
+ * by the HAL_PWR_EnablePVD() function. The PVD is stopped by Standby mode\r
+ * For this reason, this bit is equal to 0 after Standby or reset\r
+ * until the PVDE bit is set.\r
+ * @arg PWR_FLAG_VREFINTRDY: Internal voltage reference (VREFINT) ready flag.\r
+ * This bit indicates the state of the internal voltage reference, VREFINT.\r
+ * @arg PWR_FLAG_VOS: Voltage Scaling select flag. A delay is required for\r
+ * the internal regulator to be ready after the voltage range is changed.\r
+ * The VOSF bit indicates that the regulator has reached the voltage level\r
+ * defined with bits VOS of PWR_CR register.\r
+ * @arg PWR_FLAG_REGLP: Regulator LP flag. When the MCU exits from Low power run\r
+ * mode, this bit stays at 1 until the regulator is ready in main mode.\r
+ * A polling on this bit is recommended to wait for the regulator main mode.\r
+ * This bit is reset by hardware when the regulator is ready.\r
+ * @retval The new state of __FLAG__ (TRUE or FALSE).\r
+ */\r
+#define __HAL_PWR_GET_FLAG(__FLAG__) ((PWR->CSR & (__FLAG__)) == (__FLAG__))\r
+\r
+/** @brief Clear the PWR's pending flags.\r
+ * @param __FLAG__ specifies the flag to clear.\r
+ * This parameter can be one of the following values:\r
+ * @arg PWR_FLAG_WU: Wake Up flag\r
+ * @arg PWR_FLAG_SB: StandBy flag\r
+ */\r
+#define __HAL_PWR_CLEAR_FLAG(__FLAG__) SET_BIT(PWR->CR, ((__FLAG__) << 2))\r
+\r
+/**\r
+ * @brief Enable interrupt on PVD Exti Line 16.\r
+ * @retval None.\r
+ */\r
+#define __HAL_PWR_PVD_EXTI_ENABLE_IT() SET_BIT(EXTI->IMR, PWR_EXTI_LINE_PVD)\r
+\r
+/**\r
+ * @brief Disable interrupt on PVD Exti Line 16.\r
+ * @retval None.\r
+ */\r
+#define __HAL_PWR_PVD_EXTI_DISABLE_IT() CLEAR_BIT(EXTI->IMR, PWR_EXTI_LINE_PVD)\r
+\r
+/**\r
+ * @brief Enable event on PVD Exti Line 16.\r
+ * @retval None.\r
+ */\r
+#define __HAL_PWR_PVD_EXTI_ENABLE_EVENT() SET_BIT(EXTI->EMR, PWR_EXTI_LINE_PVD)\r
+\r
+/**\r
+ * @brief Disable event on PVD Exti Line 16.\r
+ * @retval None.\r
+ */\r
+#define __HAL_PWR_PVD_EXTI_DISABLE_EVENT() CLEAR_BIT(EXTI->EMR, PWR_EXTI_LINE_PVD)\r
+\r
+\r
+/**\r
+ * @brief PVD EXTI line configuration: set falling edge trigger.\r
+ * @retval None.\r
+ */\r
+#define __HAL_PWR_PVD_EXTI_ENABLE_FALLING_EDGE() SET_BIT(EXTI->FTSR, PWR_EXTI_LINE_PVD)\r
+\r
+\r
+/**\r
+ * @brief Disable the PVD Extended Interrupt Falling Trigger.\r
+ * @retval None.\r
+ */\r
+#define __HAL_PWR_PVD_EXTI_DISABLE_FALLING_EDGE() CLEAR_BIT(EXTI->FTSR, PWR_EXTI_LINE_PVD)\r
+\r
+\r
+/**\r
+ * @brief PVD EXTI line configuration: set rising edge trigger.\r
+ * @retval None.\r
+ */\r
+#define __HAL_PWR_PVD_EXTI_ENABLE_RISING_EDGE() SET_BIT(EXTI->RTSR, PWR_EXTI_LINE_PVD)\r
+\r
+/**\r
+ * @brief Disable the PVD Extended Interrupt Rising Trigger.\r
+ * @retval None.\r
+ */\r
+#define __HAL_PWR_PVD_EXTI_DISABLE_RISING_EDGE() CLEAR_BIT(EXTI->RTSR, PWR_EXTI_LINE_PVD)\r
+\r
+/**\r
+ * @brief PVD EXTI line configuration: set rising & falling edge trigger.\r
+ * @retval None.\r
+ */\r
+#define __HAL_PWR_PVD_EXTI_ENABLE_RISING_FALLING_EDGE() \\r
+ do { \\r
+ __HAL_PWR_PVD_EXTI_ENABLE_RISING_EDGE(); \\r
+ __HAL_PWR_PVD_EXTI_ENABLE_FALLING_EDGE(); \\r
+ } while(0)\r
+\r
+/**\r
+ * @brief Disable the PVD Extended Interrupt Rising & Falling Trigger.\r
+ * @retval None.\r
+ */\r
+#define __HAL_PWR_PVD_EXTI_DISABLE_RISING_FALLING_EDGE() \\r
+ do { \\r
+ __HAL_PWR_PVD_EXTI_DISABLE_RISING_EDGE(); \\r
+ __HAL_PWR_PVD_EXTI_DISABLE_FALLING_EDGE(); \\r
+ } while(0)\r
+\r
+\r
+\r
+/**\r
+ * @brief Check whether the specified PVD EXTI interrupt flag is set or not.\r
+ * @retval EXTI PVD Line Status.\r
+ */\r
+#define __HAL_PWR_PVD_EXTI_GET_FLAG() (EXTI->PR & (PWR_EXTI_LINE_PVD))\r
+\r
+/**\r
+ * @brief Clear the PVD EXTI flag.\r
+ * @retval None.\r
+ */\r
+#define __HAL_PWR_PVD_EXTI_CLEAR_FLAG() (EXTI->PR = (PWR_EXTI_LINE_PVD))\r
+\r
+/**\r
+ * @brief Generate a Software interrupt on selected EXTI line.\r
+ * @retval None.\r
+ */\r
+#define __HAL_PWR_PVD_EXTI_GENERATE_SWIT() SET_BIT(EXTI->SWIER, PWR_EXTI_LINE_PVD)\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/* Private macro -------------------------------------------------------------*/\r
+/** @defgroup PWR_Private_Macros PWR Private Macros\r
+ * @{\r
+ */\r
+\r
+#define IS_PWR_PVD_LEVEL(LEVEL) (((LEVEL) == PWR_PVDLEVEL_0) || ((LEVEL) == PWR_PVDLEVEL_1)|| \\r
+ ((LEVEL) == PWR_PVDLEVEL_2) || ((LEVEL) == PWR_PVDLEVEL_3)|| \\r
+ ((LEVEL) == PWR_PVDLEVEL_4) || ((LEVEL) == PWR_PVDLEVEL_5)|| \\r
+ ((LEVEL) == PWR_PVDLEVEL_6) || ((LEVEL) == PWR_PVDLEVEL_7))\r
+\r
+\r
+#define IS_PWR_PVD_MODE(MODE) (((MODE) == PWR_PVD_MODE_IT_RISING)|| ((MODE) == PWR_PVD_MODE_IT_FALLING) || \\r
+ ((MODE) == PWR_PVD_MODE_IT_RISING_FALLING) || ((MODE) == PWR_PVD_MODE_EVENT_RISING) || \\r
+ ((MODE) == PWR_PVD_MODE_EVENT_FALLING) || ((MODE) == PWR_PVD_MODE_EVENT_RISING_FALLING) || \\r
+ ((MODE) == PWR_PVD_MODE_NORMAL))\r
+\r
+#define IS_PWR_REGULATOR(REGULATOR) (((REGULATOR) == PWR_MAINREGULATOR_ON) || \\r
+ ((REGULATOR) == PWR_LOWPOWERREGULATOR_ON))\r
+\r
+\r
+#define IS_PWR_SLEEP_ENTRY(ENTRY) (((ENTRY) == PWR_SLEEPENTRY_WFI) || ((ENTRY) == PWR_SLEEPENTRY_WFE))\r
+\r
+#define IS_PWR_STOP_ENTRY(ENTRY) (((ENTRY) == PWR_STOPENTRY_WFI) || ((ENTRY) == PWR_STOPENTRY_WFE) )\r
+\r
+#define IS_PWR_VOLTAGE_SCALING_RANGE(RANGE) (((RANGE) == PWR_REGULATOR_VOLTAGE_SCALE1) || \\r
+ ((RANGE) == PWR_REGULATOR_VOLTAGE_SCALE2) || \\r
+ ((RANGE) == PWR_REGULATOR_VOLTAGE_SCALE3))\r
+\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+\r
+\r
+/* Include PWR HAL Extension module */\r
+#include "stm32l1xx_hal_pwr_ex.h"\r
+\r
+/* Exported functions --------------------------------------------------------*/\r
+\r
+/** @addtogroup PWR_Exported_Functions PWR Exported Functions\r
+ * @{\r
+ */\r
+\r
+/** @addtogroup PWR_Exported_Functions_Group1 Initialization and de-initialization functions\r
+ * @{\r
+ */\r
+\r
+/* Initialization and de-initialization functions *******************************/\r
+void HAL_PWR_DeInit(void);\r
+void HAL_PWR_EnableBkUpAccess(void);\r
+void HAL_PWR_DisableBkUpAccess(void);\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @addtogroup PWR_Exported_Functions_Group2 Peripheral Control functions\r
+ * @{\r
+ */\r
+\r
+/* Peripheral Control functions ************************************************/\r
+void HAL_PWR_ConfigPVD(PWR_PVDTypeDef *sConfigPVD);\r
+void HAL_PWR_EnablePVD(void);\r
+void HAL_PWR_DisablePVD(void);\r
+\r
+/* WakeUp pins configuration functions ****************************************/\r
+void HAL_PWR_EnableWakeUpPin(uint32_t WakeUpPinx);\r
+void HAL_PWR_DisableWakeUpPin(uint32_t WakeUpPinx);\r
+\r
+/* Low Power modes configuration functions ************************************/\r
+void HAL_PWR_EnterSTOPMode(uint32_t Regulator, uint8_t STOPEntry);\r
+void HAL_PWR_EnterSLEEPMode(uint32_t Regulator, uint8_t SLEEPEntry);\r
+void HAL_PWR_EnterSTANDBYMode(void);\r
+\r
+void HAL_PWR_EnableSleepOnExit(void);\r
+void HAL_PWR_DisableSleepOnExit(void);\r
+void HAL_PWR_EnableSEVOnPend(void);\r
+void HAL_PWR_DisableSEVOnPend(void);\r
+\r
+\r
+\r
+void HAL_PWR_PVD_IRQHandler(void);\r
+void HAL_PWR_PVDCallback(void);\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+#ifdef __cplusplus\r
+}\r
+#endif\r
+\r
+\r
+#endif /* __STM32L1xx_HAL_PWR_H */\r
+\r
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\r
--- /dev/null
+/**\r
+ ******************************************************************************\r
+ * @file stm32l1xx_hal_pwr_ex.h\r
+ * @author MCD Application Team\r
+ * @brief Header file of PWR HAL Extension module.\r
+ ******************************************************************************\r
+ * @attention\r
+ *\r
+ * <h2><center>© Copyright (c) 2017 STMicroelectronics.\r
+ * All rights reserved.</center></h2>\r
+ *\r
+ * This software component is licensed by ST under BSD 3-Clause license,\r
+ * the "License"; You may not use this file except in compliance with the\r
+ * License. You may obtain a copy of the License at:\r
+ * opensource.org/licenses/BSD-3-Clause\r
+ *\r
+ ******************************************************************************\r
+ */\r
+\r
+/* Define to prevent recursive inclusion -------------------------------------*/\r
+#ifndef __STM32L1xx_HAL_PWR_EX_H\r
+#define __STM32L1xx_HAL_PWR_EX_H\r
+\r
+#ifdef __cplusplus\r
+ extern "C" {\r
+#endif\r
+\r
+/* Includes ------------------------------------------------------------------*/\r
+#include "stm32l1xx_hal_def.h"\r
+\r
+/** @addtogroup STM32L1xx_HAL_Driver\r
+ * @{\r
+ */\r
+\r
+/** @addtogroup PWREx\r
+ * @{\r
+ */\r
+\r
+\r
+/* Exported types ------------------------------------------------------------*/\r
+/* Exported constants --------------------------------------------------------*/\r
+\r
+/** @defgroup PWREx_Exported_Constants PWREx Exported Constants\r
+ * @{\r
+ */\r
+\r
+\r
+/** @defgroup PWREx_WakeUp_Pins PWREx Wakeup Pins\r
+ * @{\r
+ */\r
+\r
+#if defined (STM32L151xCA) || defined (STM32L151xD) || defined (STM32L152xCA) || defined (STM32L152xD) || defined (STM32L162xCA) || defined (STM32L162xD) || defined (STM32L151xE) || defined (STM32L151xDX) || defined (STM32L152xE) || defined (STM32L152xDX) || defined (STM32L162xE) || defined (STM32L162xDX) || defined (STM32L151xB) || defined (STM32L151xBA) || defined (STM32L151xC) || defined (STM32L152xB) || defined (STM32L152xBA) || defined (STM32L152xC) || defined (STM32L162xC)\r
+\r
+#define PWR_WAKEUP_PIN1 PWR_CSR_EWUP1\r
+#define PWR_WAKEUP_PIN2 PWR_CSR_EWUP2\r
+#define PWR_WAKEUP_PIN3 PWR_CSR_EWUP3\r
+#define IS_PWR_WAKEUP_PIN(PIN) (((PIN) == PWR_WAKEUP_PIN1) || \\r
+ ((PIN) == PWR_WAKEUP_PIN2) || \\r
+ ((PIN) == PWR_WAKEUP_PIN3))\r
+#else\r
+#define PWR_WAKEUP_PIN1 PWR_CSR_EWUP1\r
+#define PWR_WAKEUP_PIN2 PWR_CSR_EWUP2\r
+#define IS_PWR_WAKEUP_PIN(PIN) (((PIN) == PWR_WAKEUP_PIN1) || \\r
+ ((PIN) == PWR_WAKEUP_PIN2))\r
+#endif\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/* Exported macro ------------------------------------------------------------*/\r
+/* Exported functions --------------------------------------------------------*/\r
+\r
+/** @defgroup PWREx_Exported_Functions PWREx Exported Functions\r
+ * @{\r
+ */\r
+\r
+/** @addtogroup PWREx_Exported_Functions_Group1\r
+ * @{\r
+ */\r
+\r
+/* Peripheral Control methods ************************************************/\r
+uint32_t HAL_PWREx_GetVoltageRange(void);\r
+void HAL_PWREx_EnableFastWakeUp(void);\r
+void HAL_PWREx_DisableFastWakeUp(void);\r
+void HAL_PWREx_EnableUltraLowPower(void);\r
+void HAL_PWREx_DisableUltraLowPower(void);\r
+void HAL_PWREx_EnableLowPowerRunMode(void);\r
+HAL_StatusTypeDef HAL_PWREx_DisableLowPowerRunMode(void);\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+#ifdef __cplusplus\r
+}\r
+#endif\r
+\r
+\r
+#endif /* __STM32L1xx_HAL_PWR_EX_H */\r
+\r
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\r
--- /dev/null
+/**\r
+ ******************************************************************************\r
+ * @file stm32l1xx_hal_rcc.h\r
+ * @author MCD Application Team\r
+ * @brief Header file of RCC HAL module.\r
+ ******************************************************************************\r
+ * @attention\r
+ *\r
+ * <h2><center>© Copyright(c) 2017 STMicroelectronics.\r
+ * All rights reserved.</center></h2>\r
+ *\r
+ * This software component is licensed by ST under BSD 3-Clause license,\r
+ * the "License"; You may not use this file except in compliance with the\r
+ * License. You may obtain a copy of the License at:\r
+ * opensource.org/licenses/BSD-3-Clause\r
+ *\r
+ ******************************************************************************\r
+ */\r
+\r
+/* Define to prevent recursive inclusion -------------------------------------*/\r
+#ifndef __STM32L1xx_HAL_RCC_H\r
+#define __STM32L1xx_HAL_RCC_H\r
+\r
+#ifdef __cplusplus\r
+ extern "C" {\r
+#endif\r
+\r
+/* Includes ------------------------------------------------------------------*/\r
+#include "stm32l1xx_hal_def.h"\r
+\r
+/** @addtogroup STM32L1xx_HAL_Driver\r
+ * @{\r
+ */\r
+\r
+/** @addtogroup RCC\r
+ * @{\r
+ */\r
+\r
+/** @addtogroup RCC_Private_Constants\r
+ * @{\r
+ */\r
+\r
+/** @defgroup RCC_Timeout RCC Timeout\r
+ * @{\r
+ */\r
+\r
+/* Disable Backup domain write protection state change timeout */\r
+#define RCC_DBP_TIMEOUT_VALUE (100U) /* 100 ms */\r
+/* LSE state change timeout */\r
+#define RCC_LSE_TIMEOUT_VALUE LSE_STARTUP_TIMEOUT\r
+#define CLOCKSWITCH_TIMEOUT_VALUE (5000U) /* 5 s */\r
+#define HSE_TIMEOUT_VALUE HSE_STARTUP_TIMEOUT\r
+#define MSI_TIMEOUT_VALUE (2U) /* 2 ms (minimum Tick + 1U) */\r
+#define HSI_TIMEOUT_VALUE (2U) /* 2 ms (minimum Tick + 1U) */\r
+#define LSI_TIMEOUT_VALUE (2U) /* 2 ms (minimum Tick + 1U) */\r
+#define PLL_TIMEOUT_VALUE (2U) /* 2 ms (minimum Tick + 1U) */\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup RCC_Register_Offset Register offsets\r
+ * @{\r
+ */\r
+#define RCC_OFFSET (RCC_BASE - PERIPH_BASE)\r
+#define RCC_CR_OFFSET 0x00\r
+#define RCC_CFGR_OFFSET 0x08\r
+#define RCC_CIR_OFFSET 0x0C\r
+#define RCC_CSR_OFFSET 0x34\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup RCC_BitAddress_AliasRegion BitAddress AliasRegion\r
+ * @brief RCC registers bit address in the alias region\r
+ * @{\r
+ */\r
+#define RCC_CR_OFFSET_BB (RCC_OFFSET + RCC_CR_OFFSET)\r
+#define RCC_CFGR_OFFSET_BB (RCC_OFFSET + RCC_CFGR_OFFSET)\r
+#define RCC_CIR_OFFSET_BB (RCC_OFFSET + RCC_CIR_OFFSET)\r
+#define RCC_CSR_OFFSET_BB (RCC_OFFSET + RCC_CSR_OFFSET)\r
+\r
+/* --- CR Register ---*/\r
+/* Alias word address of HSION bit */\r
+#define RCC_HSION_BIT_NUMBER RCC_CR_HSION_Pos\r
+#define RCC_CR_HSION_BB ((uint32_t)(PERIPH_BB_BASE + (RCC_CR_OFFSET_BB * 32U) + (RCC_HSION_BIT_NUMBER * 4U)))\r
+/* Alias word address of MSION bit */\r
+#define RCC_MSION_BIT_NUMBER RCC_CR_MSION_Pos\r
+#define RCC_CR_MSION_BB ((uint32_t)(PERIPH_BB_BASE + (RCC_CR_OFFSET_BB * 32U) + (RCC_MSION_BIT_NUMBER * 4U)))\r
+/* Alias word address of HSEON bit */\r
+#define RCC_HSEON_BIT_NUMBER RCC_CR_HSEON_Pos\r
+#define RCC_CR_HSEON_BB ((uint32_t)(PERIPH_BB_BASE + (RCC_CR_OFFSET_BB * 32U) + (RCC_HSEON_BIT_NUMBER * 4U)))\r
+/* Alias word address of CSSON bit */\r
+#define RCC_CSSON_BIT_NUMBER RCC_CR_CSSON_Pos\r
+#define RCC_CR_CSSON_BB ((uint32_t)(PERIPH_BB_BASE + (RCC_CR_OFFSET_BB * 32U) + (RCC_CSSON_BIT_NUMBER * 4U)))\r
+/* Alias word address of PLLON bit */\r
+#define RCC_PLLON_BIT_NUMBER RCC_CR_PLLON_Pos\r
+#define RCC_CR_PLLON_BB ((uint32_t)(PERIPH_BB_BASE + (RCC_CR_OFFSET_BB * 32U) + (RCC_PLLON_BIT_NUMBER * 4U)))\r
+\r
+/* --- CSR Register ---*/\r
+/* Alias word address of LSION bit */\r
+#define RCC_LSION_BIT_NUMBER RCC_CSR_LSION_Pos\r
+#define RCC_CSR_LSION_BB ((uint32_t)(PERIPH_BB_BASE + (RCC_CSR_OFFSET_BB * 32U) + (RCC_LSION_BIT_NUMBER * 4U)))\r
+\r
+/* Alias word address of RMVF bit */\r
+#define RCC_RMVF_BIT_NUMBER RCC_CSR_RMVF_Pos\r
+#define RCC_CSR_RMVF_BB ((uint32_t)(PERIPH_BB_BASE + (RCC_CSR_OFFSET_BB * 32U) + (RCC_RMVF_BIT_NUMBER * 4U)))\r
+\r
+/* Alias word address of LSEON bit */\r
+#define RCC_LSEON_BIT_NUMBER RCC_CSR_LSEON_Pos\r
+#define RCC_CSR_LSEON_BB ((uint32_t)(PERIPH_BB_BASE + (RCC_CSR_OFFSET_BB * 32U) + (RCC_LSEON_BIT_NUMBER * 4U)))\r
+\r
+/* Alias word address of LSEON bit */\r
+#define RCC_LSEBYP_BIT_NUMBER RCC_CSR_LSEBYP_Pos\r
+#define RCC_CSR_LSEBYP_BB ((uint32_t)(PERIPH_BB_BASE + (RCC_CSR_OFFSET_BB * 32U) + (RCC_LSEBYP_BIT_NUMBER * 4U)))\r
+\r
+/* Alias word address of RTCEN bit */\r
+#define RCC_RTCEN_BIT_NUMBER RCC_CSR_RTCEN_Pos\r
+#define RCC_CSR_RTCEN_BB ((uint32_t)(PERIPH_BB_BASE + (RCC_CSR_OFFSET_BB * 32U) + (RCC_RTCEN_BIT_NUMBER * 4U)))\r
+\r
+/* Alias word address of RTCRST bit */\r
+#define RCC_RTCRST_BIT_NUMBER RCC_CSR_RTCRST_Pos\r
+#define RCC_CSR_RTCRST_BB ((uint32_t)(PERIPH_BB_BASE + (RCC_CSR_OFFSET_BB * 32U) + (RCC_RTCRST_BIT_NUMBER * 4U)))\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/* CR register byte 2 (Bits[23:16]) base address */\r
+#define RCC_CR_BYTE2_ADDRESS ((uint32_t)(RCC_BASE + RCC_CR_OFFSET + 0x02U))\r
+\r
+/* CIR register byte 1 (Bits[15:8]) base address */\r
+#define RCC_CIR_BYTE1_ADDRESS ((uint32_t)(RCC_BASE + RCC_CIR_OFFSET + 0x01U))\r
+\r
+/* CIR register byte 2 (Bits[23:16]) base address */\r
+#define RCC_CIR_BYTE2_ADDRESS ((uint32_t)(RCC_BASE + RCC_CIR_OFFSET + 0x02U))\r
+\r
+/* Defines used for Flags */\r
+#define CR_REG_INDEX ((uint8_t)1U)\r
+#define CSR_REG_INDEX ((uint8_t)2U)\r
+\r
+#define RCC_FLAG_MASK ((uint8_t)0x1FU)\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @addtogroup RCC_Private_Macros\r
+ * @{\r
+ */\r
+#define IS_RCC_PLLSOURCE(__SOURCE__) (((__SOURCE__) == RCC_PLLSOURCE_HSI) || \\r
+ ((__SOURCE__) == RCC_PLLSOURCE_HSE))\r
+#define IS_RCC_OSCILLATORTYPE(__OSCILLATOR__) (((__OSCILLATOR__) == RCC_OSCILLATORTYPE_NONE) || \\r
+ (((__OSCILLATOR__) & RCC_OSCILLATORTYPE_HSE) == RCC_OSCILLATORTYPE_HSE) || \\r
+ (((__OSCILLATOR__) & RCC_OSCILLATORTYPE_HSI) == RCC_OSCILLATORTYPE_HSI) || \\r
+ (((__OSCILLATOR__) & RCC_OSCILLATORTYPE_LSI) == RCC_OSCILLATORTYPE_LSI) || \\r
+ (((__OSCILLATOR__) & RCC_OSCILLATORTYPE_LSE) == RCC_OSCILLATORTYPE_LSE) || \\r
+ (((__OSCILLATOR__) & RCC_OSCILLATORTYPE_MSI) == RCC_OSCILLATORTYPE_MSI))\r
+#define IS_RCC_HSE(__HSE__) (((__HSE__) == RCC_HSE_OFF) || ((__HSE__) == RCC_HSE_ON) || \\r
+ ((__HSE__) == RCC_HSE_BYPASS))\r
+#define IS_RCC_LSE(__LSE__) (((__LSE__) == RCC_LSE_OFF) || ((__LSE__) == RCC_LSE_ON) || \\r
+ ((__LSE__) == RCC_LSE_BYPASS))\r
+#define IS_RCC_HSI(__HSI__) (((__HSI__) == RCC_HSI_OFF) || ((__HSI__) == RCC_HSI_ON))\r
+#define IS_RCC_CALIBRATION_VALUE(__VALUE__) ((__VALUE__) <= 0x1FU)\r
+#define IS_RCC_MSICALIBRATION_VALUE(__VALUE__) ((__VALUE__) <= 0xFFU)\r
+#define IS_RCC_MSI_CLOCK_RANGE(__RANGE__) (((__RANGE__) == RCC_MSIRANGE_0) || \\r
+ ((__RANGE__) == RCC_MSIRANGE_1) || \\r
+ ((__RANGE__) == RCC_MSIRANGE_2) || \\r
+ ((__RANGE__) == RCC_MSIRANGE_3) || \\r
+ ((__RANGE__) == RCC_MSIRANGE_4) || \\r
+ ((__RANGE__) == RCC_MSIRANGE_5) || \\r
+ ((__RANGE__) == RCC_MSIRANGE_6))\r
+#define IS_RCC_LSI(__LSI__) (((__LSI__) == RCC_LSI_OFF) || ((__LSI__) == RCC_LSI_ON))\r
+#define IS_RCC_MSI(__MSI__) (((__MSI__) == RCC_MSI_OFF) || ((__MSI__) == RCC_MSI_ON))\r
+\r
+#define IS_RCC_PLL(__PLL__) (((__PLL__) == RCC_PLL_NONE) || ((__PLL__) == RCC_PLL_OFF) || \\r
+ ((__PLL__) == RCC_PLL_ON))\r
+#define IS_RCC_PLL_DIV(__DIV__) (((__DIV__) == RCC_PLL_DIV2) || \\r
+ ((__DIV__) == RCC_PLL_DIV3) || ((__DIV__) == RCC_PLL_DIV4))\r
+\r
+#define IS_RCC_PLL_MUL(__MUL__) (((__MUL__) == RCC_PLL_MUL3) || ((__MUL__) == RCC_PLL_MUL4) || \\r
+ ((__MUL__) == RCC_PLL_MUL6) || ((__MUL__) == RCC_PLL_MUL8) || \\r
+ ((__MUL__) == RCC_PLL_MUL12) || ((__MUL__) == RCC_PLL_MUL16) || \\r
+ ((__MUL__) == RCC_PLL_MUL24) || ((__MUL__) == RCC_PLL_MUL32) || \\r
+ ((__MUL__) == RCC_PLL_MUL48))\r
+#define IS_RCC_CLOCKTYPE(CLK) ((((CLK) & RCC_CLOCKTYPE_SYSCLK) == RCC_CLOCKTYPE_SYSCLK) || \\r
+ (((CLK) & RCC_CLOCKTYPE_HCLK) == RCC_CLOCKTYPE_HCLK) || \\r
+ (((CLK) & RCC_CLOCKTYPE_PCLK1) == RCC_CLOCKTYPE_PCLK1) || \\r
+ (((CLK) & RCC_CLOCKTYPE_PCLK2) == RCC_CLOCKTYPE_PCLK2))\r
+#define IS_RCC_SYSCLKSOURCE(__SOURCE__) (((__SOURCE__) == RCC_SYSCLKSOURCE_MSI) || \\r
+ ((__SOURCE__) == RCC_SYSCLKSOURCE_HSI) || \\r
+ ((__SOURCE__) == RCC_SYSCLKSOURCE_HSE) || \\r
+ ((__SOURCE__) == RCC_SYSCLKSOURCE_PLLCLK))\r
+#define IS_RCC_SYSCLKSOURCE_STATUS(__SOURCE__) (((__SOURCE__) == RCC_SYSCLKSOURCE_STATUS_MSI) || \\r
+ ((__SOURCE__) == RCC_SYSCLKSOURCE_STATUS_HSI) || \\r
+ ((__SOURCE__) == RCC_SYSCLKSOURCE_STATUS_HSE) || \\r
+ ((__SOURCE__) == RCC_SYSCLKSOURCE_STATUS_PLLCLK))\r
+#define IS_RCC_HCLK(__HCLK__) (((__HCLK__) == RCC_SYSCLK_DIV1) || ((__HCLK__) == RCC_SYSCLK_DIV2) || \\r
+ ((__HCLK__) == RCC_SYSCLK_DIV4) || ((__HCLK__) == RCC_SYSCLK_DIV8) || \\r
+ ((__HCLK__) == RCC_SYSCLK_DIV16) || ((__HCLK__) == RCC_SYSCLK_DIV64) || \\r
+ ((__HCLK__) == RCC_SYSCLK_DIV128) || ((__HCLK__) == RCC_SYSCLK_DIV256) || \\r
+ ((__HCLK__) == RCC_SYSCLK_DIV512))\r
+#define IS_RCC_PCLK(__PCLK__) (((__PCLK__) == RCC_HCLK_DIV1) || ((__PCLK__) == RCC_HCLK_DIV2) || \\r
+ ((__PCLK__) == RCC_HCLK_DIV4) || ((__PCLK__) == RCC_HCLK_DIV8) || \\r
+ ((__PCLK__) == RCC_HCLK_DIV16))\r
+#define IS_RCC_MCO(__MCO__) ((__MCO__) == RCC_MCO)\r
+#define IS_RCC_MCODIV(__DIV__) (((__DIV__) == RCC_MCODIV_1) || ((__DIV__) == RCC_MCODIV_2) || \\r
+ ((__DIV__) == RCC_MCODIV_4) || ((__DIV__) == RCC_MCODIV_8) || \\r
+ ((__DIV__) == RCC_MCODIV_16))\r
+#define IS_RCC_MCO1SOURCE(__SOURCE__) (((__SOURCE__) == RCC_MCO1SOURCE_SYSCLK) || ((__SOURCE__) == RCC_MCO1SOURCE_MSI) \\r
+ || ((__SOURCE__) == RCC_MCO1SOURCE_HSI) || ((__SOURCE__) == RCC_MCO1SOURCE_LSE) \\r
+ || ((__SOURCE__) == RCC_MCO1SOURCE_LSI) || ((__SOURCE__) == RCC_MCO1SOURCE_HSE) \\r
+ || ((__SOURCE__) == RCC_MCO1SOURCE_PLLCLK) || ((__SOURCE__) == RCC_MCO1SOURCE_NOCLOCK))\r
+#define IS_RCC_RTCCLKSOURCE(__SOURCE__) (((__SOURCE__) == RCC_RTCCLKSOURCE_NO_CLK) || \\r
+ ((__SOURCE__) == RCC_RTCCLKSOURCE_LSE) || \\r
+ ((__SOURCE__) == RCC_RTCCLKSOURCE_LSI) || \\r
+ ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV2) || \\r
+ ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV4) || \\r
+ ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV8) || \\r
+ ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV16))\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/* Exported types ------------------------------------------------------------*/\r
+\r
+/** @defgroup RCC_Exported_Types RCC Exported Types\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @brief RCC PLL configuration structure definition\r
+ */\r
+typedef struct\r
+{\r
+ uint32_t PLLState; /*!< PLLState: The new state of the PLL.\r
+ This parameter can be a value of @ref RCC_PLL_Config */\r
+\r
+ uint32_t PLLSource; /*!< PLLSource: PLL entry clock source.\r
+ This parameter must be a value of @ref RCC_PLL_Clock_Source */\r
+\r
+ uint32_t PLLMUL; /*!< PLLMUL: Multiplication factor for PLL VCO input clock\r
+ This parameter must be a value of @ref RCC_PLL_Multiplication_Factor*/\r
+\r
+ uint32_t PLLDIV; /*!< PLLDIV: Division factor for PLL VCO input clock\r
+ This parameter must be a value of @ref RCC_PLL_Division_Factor*/\r
+} RCC_PLLInitTypeDef;\r
+\r
+/**\r
+ * @brief RCC Internal/External Oscillator (HSE, HSI, LSE and LSI) configuration structure definition\r
+ */\r
+typedef struct\r
+{\r
+ uint32_t OscillatorType; /*!< The oscillators to be configured.\r
+ This parameter can be a value of @ref RCC_Oscillator_Type */\r
+\r
+ uint32_t HSEState; /*!< The new state of the HSE.\r
+ This parameter can be a value of @ref RCC_HSE_Config */\r
+\r
+ uint32_t LSEState; /*!< The new state of the LSE.\r
+ This parameter can be a value of @ref RCC_LSE_Config */\r
+\r
+ uint32_t HSIState; /*!< The new state of the HSI.\r
+ This parameter can be a value of @ref RCC_HSI_Config */\r
+\r
+ uint32_t HSICalibrationValue; /*!< The HSI calibration trimming value (default is RCC_HSICALIBRATION_DEFAULT).\r
+ This parameter must be a number between Min_Data = 0x00 and Max_Data = 0x1FU */\r
+\r
+ uint32_t LSIState; /*!< The new state of the LSI.\r
+ This parameter can be a value of @ref RCC_LSI_Config */\r
+\r
+ uint32_t MSIState; /*!< The new state of the MSI.\r
+ This parameter can be a value of @ref RCC_MSI_Config */\r
+\r
+ uint32_t MSICalibrationValue; /*!< The MSI calibration trimming value. (default is RCC_MSICALIBRATION_DEFAULT).\r
+ This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFFU */\r
+\r
+ uint32_t MSIClockRange; /*!< The MSI frequency range.\r
+ This parameter can be a value of @ref RCC_MSI_Clock_Range */\r
+\r
+ RCC_PLLInitTypeDef PLL; /*!< PLL structure parameters */\r
+\r
+} RCC_OscInitTypeDef;\r
+\r
+/**\r
+ * @brief RCC System, AHB and APB busses clock configuration structure definition\r
+ */\r
+typedef struct\r
+{\r
+ uint32_t ClockType; /*!< The clock to be configured.\r
+ This parameter can be a value of @ref RCC_System_Clock_Type */\r
+\r
+ uint32_t SYSCLKSource; /*!< The clock source (SYSCLKS) used as system clock.\r
+ This parameter can be a value of @ref RCC_System_Clock_Source */\r
+\r
+ uint32_t AHBCLKDivider; /*!< The AHB clock (HCLK) divider. This clock is derived from the system clock (SYSCLK).\r
+ This parameter can be a value of @ref RCC_AHB_Clock_Source */\r
+\r
+ uint32_t APB1CLKDivider; /*!< The APB1 clock (PCLK1) divider. This clock is derived from the AHB clock (HCLK).\r
+ This parameter can be a value of @ref RCC_APB1_APB2_Clock_Source */\r
+\r
+ uint32_t APB2CLKDivider; /*!< The APB2 clock (PCLK2) divider. This clock is derived from the AHB clock (HCLK).\r
+ This parameter can be a value of @ref RCC_APB1_APB2_Clock_Source */\r
+} RCC_ClkInitTypeDef;\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/* Exported constants --------------------------------------------------------*/\r
+/** @defgroup RCC_Exported_Constants RCC Exported Constants\r
+ * @{\r
+ */\r
+\r
+/** @defgroup RCC_PLL_Clock_Source PLL Clock Source\r
+ * @{\r
+ */\r
+\r
+#define RCC_PLLSOURCE_HSI RCC_CFGR_PLLSRC_HSI /*!< HSI clock selected as PLL entry clock source */\r
+#define RCC_PLLSOURCE_HSE RCC_CFGR_PLLSRC_HSE /*!< HSE clock selected as PLL entry clock source */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup RCC_Oscillator_Type Oscillator Type\r
+ * @{\r
+ */\r
+#define RCC_OSCILLATORTYPE_NONE (0x00000000U)\r
+#define RCC_OSCILLATORTYPE_HSE (0x00000001U)\r
+#define RCC_OSCILLATORTYPE_HSI (0x00000002U)\r
+#define RCC_OSCILLATORTYPE_LSE (0x00000004U)\r
+#define RCC_OSCILLATORTYPE_LSI (0x00000008U)\r
+#define RCC_OSCILLATORTYPE_MSI (0x00000010U)\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup RCC_HSE_Config HSE Config\r
+ * @{\r
+ */\r
+#define RCC_HSE_OFF (0x00000000U) /*!< HSE clock deactivation */\r
+#define RCC_HSE_ON (0x00000001U) /*!< HSE clock activation */\r
+#define RCC_HSE_BYPASS (0x00000005U) /*!< External clock source for HSE clock */\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup RCC_LSE_Config LSE Config\r
+ * @{\r
+ */\r
+#define RCC_LSE_OFF (0x00000000U) /*!< LSE clock deactivation */\r
+#define RCC_LSE_ON (0x00000001U) /*!< LSE clock activation */\r
+#define RCC_LSE_BYPASS (0x00000005U) /*!< External clock source for LSE clock */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup RCC_HSI_Config HSI Config\r
+ * @{\r
+ */\r
+#define RCC_HSI_OFF (0x00000000U) /*!< HSI clock deactivation */\r
+#define RCC_HSI_ON RCC_CR_HSION /*!< HSI clock activation */\r
+\r
+#define RCC_HSICALIBRATION_DEFAULT (0x10U) /* Default HSI calibration trimming value */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup RCC_MSI_Clock_Range MSI Clock Range\r
+ * @{\r
+ */\r
+\r
+#define RCC_MSIRANGE_0 RCC_ICSCR_MSIRANGE_0 /*!< MSI = 65.536 KHz */\r
+#define RCC_MSIRANGE_1 RCC_ICSCR_MSIRANGE_1 /*!< MSI = 131.072 KHz */\r
+#define RCC_MSIRANGE_2 RCC_ICSCR_MSIRANGE_2 /*!< MSI = 262.144 KHz */\r
+#define RCC_MSIRANGE_3 RCC_ICSCR_MSIRANGE_3 /*!< MSI = 524.288 KHz */\r
+#define RCC_MSIRANGE_4 RCC_ICSCR_MSIRANGE_4 /*!< MSI = 1.048 MHz */\r
+#define RCC_MSIRANGE_5 RCC_ICSCR_MSIRANGE_5 /*!< MSI = 2.097 MHz */\r
+#define RCC_MSIRANGE_6 RCC_ICSCR_MSIRANGE_6 /*!< MSI = 4.194 MHz */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup RCC_LSI_Config LSI Config\r
+ * @{\r
+ */\r
+#define RCC_LSI_OFF (0x00000000U) /*!< LSI clock deactivation */\r
+#define RCC_LSI_ON RCC_CSR_LSION /*!< LSI clock activation */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup RCC_MSI_Config MSI Config\r
+ * @{\r
+ */\r
+#define RCC_MSI_OFF (0x00000000U)\r
+#define RCC_MSI_ON (0x00000001U)\r
+\r
+#define RCC_MSICALIBRATION_DEFAULT (0x00000000U) /* Default MSI calibration trimming value */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup RCC_PLL_Config PLL Config\r
+ * @{\r
+ */\r
+#define RCC_PLL_NONE (0x00000000U) /*!< PLL is not configured */\r
+#define RCC_PLL_OFF (0x00000001U) /*!< PLL deactivation */\r
+#define RCC_PLL_ON (0x00000002U) /*!< PLL activation */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup RCC_System_Clock_Type System Clock Type\r
+ * @{\r
+ */\r
+#define RCC_CLOCKTYPE_SYSCLK (0x00000001U) /*!< SYSCLK to configure */\r
+#define RCC_CLOCKTYPE_HCLK (0x00000002U) /*!< HCLK to configure */\r
+#define RCC_CLOCKTYPE_PCLK1 (0x00000004U) /*!< PCLK1 to configure */\r
+#define RCC_CLOCKTYPE_PCLK2 (0x00000008U) /*!< PCLK2 to configure */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup RCC_System_Clock_Source System Clock Source\r
+ * @{\r
+ */\r
+#define RCC_SYSCLKSOURCE_MSI RCC_CFGR_SW_MSI /*!< MSI selected as system clock */\r
+#define RCC_SYSCLKSOURCE_HSI RCC_CFGR_SW_HSI /*!< HSI selected as system clock */\r
+#define RCC_SYSCLKSOURCE_HSE RCC_CFGR_SW_HSE /*!< HSE selected as system clock */\r
+#define RCC_SYSCLKSOURCE_PLLCLK RCC_CFGR_SW_PLL /*!< PLL selected as system clock */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup RCC_System_Clock_Source_Status System Clock Source Status\r
+ * @{\r
+ */\r
+#define RCC_SYSCLKSOURCE_STATUS_MSI RCC_CFGR_SWS_MSI /*!< MSI used as system clock */\r
+#define RCC_SYSCLKSOURCE_STATUS_HSI RCC_CFGR_SWS_HSI /*!< HSI used as system clock */\r
+#define RCC_SYSCLKSOURCE_STATUS_HSE RCC_CFGR_SWS_HSE /*!< HSE used as system clock */\r
+#define RCC_SYSCLKSOURCE_STATUS_PLLCLK RCC_CFGR_SWS_PLL /*!< PLL used as system clock */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup RCC_AHB_Clock_Source AHB Clock Source\r
+ * @{\r
+ */\r
+#define RCC_SYSCLK_DIV1 RCC_CFGR_HPRE_DIV1 /*!< SYSCLK not divided */\r
+#define RCC_SYSCLK_DIV2 RCC_CFGR_HPRE_DIV2 /*!< SYSCLK divided by 2 */\r
+#define RCC_SYSCLK_DIV4 RCC_CFGR_HPRE_DIV4 /*!< SYSCLK divided by 4 */\r
+#define RCC_SYSCLK_DIV8 RCC_CFGR_HPRE_DIV8 /*!< SYSCLK divided by 8 */\r
+#define RCC_SYSCLK_DIV16 RCC_CFGR_HPRE_DIV16 /*!< SYSCLK divided by 16 */\r
+#define RCC_SYSCLK_DIV64 RCC_CFGR_HPRE_DIV64 /*!< SYSCLK divided by 64 */\r
+#define RCC_SYSCLK_DIV128 RCC_CFGR_HPRE_DIV128 /*!< SYSCLK divided by 128 */\r
+#define RCC_SYSCLK_DIV256 RCC_CFGR_HPRE_DIV256 /*!< SYSCLK divided by 256 */\r
+#define RCC_SYSCLK_DIV512 RCC_CFGR_HPRE_DIV512 /*!< SYSCLK divided by 512 */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup RCC_APB1_APB2_Clock_Source APB1 APB2 Clock Source\r
+ * @{\r
+ */\r
+#define RCC_HCLK_DIV1 RCC_CFGR_PPRE1_DIV1 /*!< HCLK not divided */\r
+#define RCC_HCLK_DIV2 RCC_CFGR_PPRE1_DIV2 /*!< HCLK divided by 2 */\r
+#define RCC_HCLK_DIV4 RCC_CFGR_PPRE1_DIV4 /*!< HCLK divided by 4 */\r
+#define RCC_HCLK_DIV8 RCC_CFGR_PPRE1_DIV8 /*!< HCLK divided by 8 */\r
+#define RCC_HCLK_DIV16 RCC_CFGR_PPRE1_DIV16 /*!< HCLK divided by 16 */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup RCC_HAL_EC_RTC_HSE_DIV RTC HSE Prescaler\r
+ * @{\r
+ */\r
+#define RCC_RTC_HSE_DIV_2 0x00000000U /*!< HSE is divided by 2 for RTC clock */\r
+#define RCC_RTC_HSE_DIV_4 RCC_CR_RTCPRE_0 /*!< HSE is divided by 4 for RTC clock */\r
+#define RCC_RTC_HSE_DIV_8 RCC_CR_RTCPRE_1 /*!< HSE is divided by 8 for RTC clock */\r
+#define RCC_RTC_HSE_DIV_16 RCC_CR_RTCPRE /*!< HSE is divided by 16 for RTC clock */\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup RCC_RTC_LCD_Clock_Source RTC LCD Clock Source\r
+ * @{\r
+ */\r
+#define RCC_RTCCLKSOURCE_NO_CLK (0x00000000U) /*!< No clock */\r
+#define RCC_RTCCLKSOURCE_LSE RCC_CSR_RTCSEL_LSE /*!< LSE oscillator clock used as RTC clock */\r
+#define RCC_RTCCLKSOURCE_LSI RCC_CSR_RTCSEL_LSI /*!< LSI oscillator clock used as RTC clock */\r
+#define RCC_RTCCLKSOURCE_HSE_DIVX RCC_CSR_RTCSEL_HSE /*!< HSE oscillator clock divided by X used as RTC clock */\r
+#define RCC_RTCCLKSOURCE_HSE_DIV2 (RCC_RTC_HSE_DIV_2 | RCC_CSR_RTCSEL_HSE) /*!< HSE oscillator clock divided by 2 used as RTC clock */\r
+#define RCC_RTCCLKSOURCE_HSE_DIV4 (RCC_RTC_HSE_DIV_4 | RCC_CSR_RTCSEL_HSE) /*!< HSE oscillator clock divided by 4 used as RTC clock */\r
+#define RCC_RTCCLKSOURCE_HSE_DIV8 (RCC_RTC_HSE_DIV_8 | RCC_CSR_RTCSEL_HSE) /*!< HSE oscillator clock divided by 8 used as RTC clock */\r
+#define RCC_RTCCLKSOURCE_HSE_DIV16 (RCC_RTC_HSE_DIV_16 | RCC_CSR_RTCSEL_HSE) /*!< HSE oscillator clock divided by 16 used as RTC clock */\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup RCC_PLL_Division_Factor PLL Division Factor\r
+ * @{\r
+ */\r
+\r
+#define RCC_PLL_DIV2 RCC_CFGR_PLLDIV2\r
+#define RCC_PLL_DIV3 RCC_CFGR_PLLDIV3\r
+#define RCC_PLL_DIV4 RCC_CFGR_PLLDIV4\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup RCC_PLL_Multiplication_Factor PLL Multiplication Factor\r
+ * @{\r
+ */\r
+\r
+#define RCC_PLL_MUL3 RCC_CFGR_PLLMUL3\r
+#define RCC_PLL_MUL4 RCC_CFGR_PLLMUL4\r
+#define RCC_PLL_MUL6 RCC_CFGR_PLLMUL6\r
+#define RCC_PLL_MUL8 RCC_CFGR_PLLMUL8\r
+#define RCC_PLL_MUL12 RCC_CFGR_PLLMUL12\r
+#define RCC_PLL_MUL16 RCC_CFGR_PLLMUL16\r
+#define RCC_PLL_MUL24 RCC_CFGR_PLLMUL24\r
+#define RCC_PLL_MUL32 RCC_CFGR_PLLMUL32\r
+#define RCC_PLL_MUL48 RCC_CFGR_PLLMUL48\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup RCC_MCO_Index MCO Index\r
+ * @{\r
+ */\r
+#define RCC_MCO1 (0x00000000U)\r
+#define RCC_MCO RCC_MCO1 /*!< MCO1 to be compliant with other families with 2 MCOs*/\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup RCC_MCOx_Clock_Prescaler MCO Clock Prescaler\r
+ * @{\r
+ */\r
+#define RCC_MCODIV_1 ((uint32_t)RCC_CFGR_MCO_DIV1)\r
+#define RCC_MCODIV_2 ((uint32_t)RCC_CFGR_MCO_DIV2)\r
+#define RCC_MCODIV_4 ((uint32_t)RCC_CFGR_MCO_DIV4)\r
+#define RCC_MCODIV_8 ((uint32_t)RCC_CFGR_MCO_DIV8)\r
+#define RCC_MCODIV_16 ((uint32_t)RCC_CFGR_MCO_DIV16)\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup RCC_MCO1_Clock_Source MCO1 Clock Source\r
+ * @{\r
+ */\r
+#define RCC_MCO1SOURCE_NOCLOCK RCC_CFGR_MCO_NOCLOCK\r
+#define RCC_MCO1SOURCE_SYSCLK RCC_CFGR_MCO_SYSCLK\r
+#define RCC_MCO1SOURCE_MSI RCC_CFGR_MCO_MSI\r
+#define RCC_MCO1SOURCE_HSI RCC_CFGR_MCO_HSI\r
+#define RCC_MCO1SOURCE_LSE RCC_CFGR_MCO_LSE\r
+#define RCC_MCO1SOURCE_LSI RCC_CFGR_MCO_LSI\r
+#define RCC_MCO1SOURCE_HSE RCC_CFGR_MCO_HSE\r
+#define RCC_MCO1SOURCE_PLLCLK RCC_CFGR_MCO_PLL\r
+\r
+/**\r
+ * @}\r
+ */\r
+/** @defgroup RCC_Interrupt Interrupts\r
+ * @{\r
+ */\r
+#define RCC_IT_LSIRDY ((uint8_t)RCC_CIR_LSIRDYF) /*!< LSI Ready Interrupt flag */\r
+#define RCC_IT_LSERDY ((uint8_t)RCC_CIR_LSERDYF) /*!< LSE Ready Interrupt flag */\r
+#define RCC_IT_HSIRDY ((uint8_t)RCC_CIR_HSIRDYF) /*!< HSI Ready Interrupt flag */\r
+#define RCC_IT_HSERDY ((uint8_t)RCC_CIR_HSERDYF) /*!< HSE Ready Interrupt flag */\r
+#define RCC_IT_PLLRDY ((uint8_t)RCC_CIR_PLLRDYF) /*!< PLL Ready Interrupt flag */\r
+#define RCC_IT_MSIRDY ((uint8_t)RCC_CIR_MSIRDYF) /*!< MSI Ready Interrupt flag */\r
+#define RCC_IT_LSECSS ((uint8_t)RCC_CIR_LSECSSF) /*!< LSE Clock Security System Interrupt flag */\r
+#define RCC_IT_CSS ((uint8_t)RCC_CIR_CSSF) /*!< Clock Security System Interrupt flag */\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup RCC_Flag Flags\r
+ * Elements values convention: XXXYYYYYb\r
+ * - YYYYY : Flag position in the register\r
+ * - XXX : Register index\r
+ * - 001: CR register\r
+ * - 010: CSR register\r
+ * @{\r
+ */\r
+/* Flags in the CR register */\r
+#define RCC_FLAG_HSIRDY ((uint8_t)((CR_REG_INDEX << 5U) | RCC_CR_HSIRDY_Pos)) /*!< Internal High Speed clock ready flag */\r
+#define RCC_FLAG_MSIRDY ((uint8_t)((CR_REG_INDEX << 5U) | RCC_CR_MSIRDY_Pos)) /*!< MSI clock ready flag */\r
+#define RCC_FLAG_HSERDY ((uint8_t)((CR_REG_INDEX << 5U) | RCC_CR_HSERDY_Pos)) /*!< External High Speed clock ready flag */\r
+#define RCC_FLAG_PLLRDY ((uint8_t)((CR_REG_INDEX << 5U) | RCC_CR_PLLRDY_Pos)) /*!< PLL clock ready flag */\r
+\r
+/* Flags in the CSR register */\r
+#define RCC_FLAG_LSIRDY ((uint8_t)((CSR_REG_INDEX << 5U) | RCC_CSR_LSIRDY_Pos)) /*!< Internal Low Speed oscillator Ready */\r
+#define RCC_FLAG_LSECSS ((uint8_t)((CSR_REG_INDEX << 5U) | RCC_CSR_LSECSSD_Pos)) /*!< CSS on LSE failure Detection */\r
+#define RCC_FLAG_OBLRST ((uint8_t)((CSR_REG_INDEX << 5U) | RCC_CSR_OBLRSTF_Pos)) /*!< Options bytes loading reset flag */\r
+#define RCC_FLAG_PINRST ((uint8_t)((CSR_REG_INDEX << 5U) | RCC_CSR_PINRSTF_Pos)) /*!< PIN reset flag */\r
+#define RCC_FLAG_PORRST ((uint8_t)((CSR_REG_INDEX << 5U) | RCC_CSR_PORRSTF_Pos)) /*!< POR/PDR reset flag */\r
+#define RCC_FLAG_SFTRST ((uint8_t)((CSR_REG_INDEX << 5U) | RCC_CSR_SFTRSTF_Pos)) /*!< Software Reset flag */\r
+#define RCC_FLAG_IWDGRST ((uint8_t)((CSR_REG_INDEX << 5U) | RCC_CSR_IWDGRSTF_Pos)) /*!< Independent Watchdog reset flag */\r
+#define RCC_FLAG_WWDGRST ((uint8_t)((CSR_REG_INDEX << 5U) | RCC_CSR_WWDGRSTF_Pos)) /*!< Window watchdog reset flag */\r
+#define RCC_FLAG_LPWRRST ((uint8_t)((CSR_REG_INDEX << 5U) | RCC_CSR_LPWRRSTF_Pos)) /*!< Low-Power reset flag */\r
+#define RCC_FLAG_LSERDY ((uint8_t)((CSR_REG_INDEX << 5U) | RCC_CSR_LSERDY_Pos)) /*!< External Low Speed oscillator Ready */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/* Exported macro ------------------------------------------------------------*/\r
+\r
+/** @defgroup RCC_Exported_Macros RCC Exported Macros\r
+ * @{\r
+ */\r
+\r
+/** @defgroup RCC_Peripheral_Clock_Enable_Disable Peripheral Clock Enable Disable\r
+ * @brief Enable or disable the AHB1 peripheral clock.\r
+ * @note After reset, the peripheral clock (used for registers read/write access)\r
+ * is disabled and the application software has to enable this clock before\r
+ * using it.\r
+ * @{\r
+ */\r
+#define __HAL_RCC_GPIOA_CLK_ENABLE() do { \\r
+ __IO uint32_t tmpreg; \\r
+ SET_BIT(RCC->AHBENR, RCC_AHBENR_GPIOAEN);\\r
+ /* Delay after an RCC peripheral clock enabling */\\r
+ tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_GPIOAEN);\\r
+ UNUSED(tmpreg); \\r
+ } while(0U)\r
+#define __HAL_RCC_GPIOB_CLK_ENABLE() do { \\r
+ __IO uint32_t tmpreg; \\r
+ SET_BIT(RCC->AHBENR, RCC_AHBENR_GPIOBEN);\\r
+ /* Delay after an RCC peripheral clock enabling */\\r
+ tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_GPIOBEN);\\r
+ UNUSED(tmpreg); \\r
+ } while(0U)\r
+#define __HAL_RCC_GPIOC_CLK_ENABLE() do { \\r
+ __IO uint32_t tmpreg; \\r
+ SET_BIT(RCC->AHBENR, RCC_AHBENR_GPIOCEN);\\r
+ /* Delay after an RCC peripheral clock enabling */\\r
+ tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_GPIOCEN);\\r
+ UNUSED(tmpreg); \\r
+ } while(0U)\r
+#define __HAL_RCC_GPIOD_CLK_ENABLE() do { \\r
+ __IO uint32_t tmpreg; \\r
+ SET_BIT(RCC->AHBENR, RCC_AHBENR_GPIODEN);\\r
+ /* Delay after an RCC peripheral clock enabling */\\r
+ tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_GPIODEN);\\r
+ UNUSED(tmpreg); \\r
+ } while(0U)\r
+#define __HAL_RCC_GPIOH_CLK_ENABLE() do { \\r
+ __IO uint32_t tmpreg; \\r
+ SET_BIT(RCC->AHBENR, RCC_AHBENR_GPIOHEN);\\r
+ /* Delay after an RCC peripheral clock enabling */\\r
+ tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_GPIOHEN);\\r
+ UNUSED(tmpreg); \\r
+ } while(0U)\r
+#define __HAL_RCC_CRC_CLK_ENABLE() do { \\r
+ __IO uint32_t tmpreg; \\r
+ SET_BIT(RCC->AHBENR, RCC_AHBENR_CRCEN);\\r
+ /* Delay after an RCC peripheral clock enabling */\\r
+ tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_CRCEN);\\r
+ UNUSED(tmpreg); \\r
+ } while(0U)\r
+#define __HAL_RCC_FLITF_CLK_ENABLE() do { \\r
+ __IO uint32_t tmpreg; \\r
+ SET_BIT(RCC->AHBENR, RCC_AHBENR_FLITFEN);\\r
+ /* Delay after an RCC peripheral clock enabling */\\r
+ tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_FLITFEN);\\r
+ UNUSED(tmpreg); \\r
+ } while(0U)\r
+#define __HAL_RCC_DMA1_CLK_ENABLE() do { \\r
+ __IO uint32_t tmpreg; \\r
+ SET_BIT(RCC->AHBENR, RCC_AHBENR_DMA1EN);\\r
+ /* Delay after an RCC peripheral clock enabling */\\r
+ tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_DMA1EN);\\r
+ UNUSED(tmpreg); \\r
+ } while(0U)\r
+\r
+#define __HAL_RCC_GPIOA_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_GPIOAEN))\r
+#define __HAL_RCC_GPIOB_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_GPIOBEN))\r
+#define __HAL_RCC_GPIOC_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_GPIOCEN))\r
+#define __HAL_RCC_GPIOD_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_GPIODEN))\r
+#define __HAL_RCC_GPIOH_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_GPIOHEN))\r
+\r
+#define __HAL_RCC_CRC_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_CRCEN))\r
+#define __HAL_RCC_FLITF_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_FLITFEN))\r
+#define __HAL_RCC_DMA1_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_DMA1EN))\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup RCC_APB1_Clock_Enable_Disable APB1 Clock Enable Disable\r
+ * @brief Enable or disable the Low Speed APB (APB1) peripheral clock.\r
+ * @note After reset, the peripheral clock (used for registers read/write access)\r
+ * is disabled and the application software has to enable this clock before\r
+ * using it.\r
+ * @{\r
+ */\r
+#define __HAL_RCC_TIM2_CLK_ENABLE() do { \\r
+ __IO uint32_t tmpreg; \\r
+ SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM2EN);\\r
+ /* Delay after an RCC peripheral clock enabling */\\r
+ tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM2EN);\\r
+ UNUSED(tmpreg); \\r
+ } while(0U)\r
+#define __HAL_RCC_TIM3_CLK_ENABLE() do { \\r
+ __IO uint32_t tmpreg; \\r
+ SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM3EN);\\r
+ /* Delay after an RCC peripheral clock enabling */\\r
+ tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM3EN);\\r
+ UNUSED(tmpreg); \\r
+ } while(0U)\r
+#define __HAL_RCC_TIM4_CLK_ENABLE() do { \\r
+ __IO uint32_t tmpreg; \\r
+ SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM4EN);\\r
+ /* Delay after an RCC peripheral clock enabling */\\r
+ tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM4EN);\\r
+ UNUSED(tmpreg); \\r
+ } while(0U)\r
+#define __HAL_RCC_TIM6_CLK_ENABLE() do { \\r
+ __IO uint32_t tmpreg; \\r
+ SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM6EN);\\r
+ /* Delay after an RCC peripheral clock enabling */\\r
+ tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM6EN);\\r
+ UNUSED(tmpreg); \\r
+ } while(0U)\r
+#define __HAL_RCC_TIM7_CLK_ENABLE() do { \\r
+ __IO uint32_t tmpreg; \\r
+ SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM7EN);\\r
+ /* Delay after an RCC peripheral clock enabling */\\r
+ tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM7EN);\\r
+ UNUSED(tmpreg); \\r
+ } while(0U)\r
+#define __HAL_RCC_WWDG_CLK_ENABLE() do { \\r
+ __IO uint32_t tmpreg; \\r
+ SET_BIT(RCC->APB1ENR, RCC_APB1ENR_WWDGEN);\\r
+ /* Delay after an RCC peripheral clock enabling */\\r
+ tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_WWDGEN);\\r
+ UNUSED(tmpreg); \\r
+ } while(0U)\r
+#define __HAL_RCC_SPI2_CLK_ENABLE() do { \\r
+ __IO uint32_t tmpreg; \\r
+ SET_BIT(RCC->APB1ENR, RCC_APB1ENR_SPI2EN);\\r
+ /* Delay after an RCC peripheral clock enabling */\\r
+ tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_SPI2EN);\\r
+ UNUSED(tmpreg); \\r
+ } while(0U)\r
+#define __HAL_RCC_USART2_CLK_ENABLE() do { \\r
+ __IO uint32_t tmpreg; \\r
+ SET_BIT(RCC->APB1ENR, RCC_APB1ENR_USART2EN);\\r
+ /* Delay after an RCC peripheral clock enabling */\\r
+ tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_USART2EN);\\r
+ UNUSED(tmpreg); \\r
+ } while(0U)\r
+#define __HAL_RCC_USART3_CLK_ENABLE() do { \\r
+ __IO uint32_t tmpreg; \\r
+ SET_BIT(RCC->APB1ENR, RCC_APB1ENR_USART3EN);\\r
+ /* Delay after an RCC peripheral clock enabling */\\r
+ tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_USART3EN);\\r
+ UNUSED(tmpreg); \\r
+ } while(0U)\r
+#define __HAL_RCC_I2C1_CLK_ENABLE() do { \\r
+ __IO uint32_t tmpreg; \\r
+ SET_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C1EN);\\r
+ /* Delay after an RCC peripheral clock enabling */\\r
+ tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C1EN);\\r
+ UNUSED(tmpreg); \\r
+ } while(0U)\r
+#define __HAL_RCC_I2C2_CLK_ENABLE() do { \\r
+ __IO uint32_t tmpreg; \\r
+ SET_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C2EN);\\r
+ /* Delay after an RCC peripheral clock enabling */\\r
+ tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C2EN);\\r
+ UNUSED(tmpreg); \\r
+ } while(0U)\r
+#define __HAL_RCC_USB_CLK_ENABLE() do { \\r
+ __IO uint32_t tmpreg; \\r
+ SET_BIT(RCC->APB1ENR, RCC_APB1ENR_USBEN);\\r
+ /* Delay after an RCC peripheral clock enabling */\\r
+ tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_USBEN);\\r
+ UNUSED(tmpreg); \\r
+ } while(0U)\r
+#define __HAL_RCC_PWR_CLK_ENABLE() do { \\r
+ __IO uint32_t tmpreg; \\r
+ SET_BIT(RCC->APB1ENR, RCC_APB1ENR_PWREN);\\r
+ /* Delay after an RCC peripheral clock enabling */\\r
+ tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_PWREN);\\r
+ UNUSED(tmpreg); \\r
+ } while(0U)\r
+#define __HAL_RCC_DAC_CLK_ENABLE() do { \\r
+ __IO uint32_t tmpreg; \\r
+ SET_BIT(RCC->APB1ENR, RCC_APB1ENR_DACEN);\\r
+ /* Delay after an RCC peripheral clock enabling */\\r
+ tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_DACEN);\\r
+ UNUSED(tmpreg); \\r
+ } while(0U)\r
+#define __HAL_RCC_COMP_CLK_ENABLE() do { \\r
+ __IO uint32_t tmpreg; \\r
+ SET_BIT(RCC->APB1ENR, RCC_APB1ENR_COMPEN);\\r
+ /* Delay after an RCC peripheral clock enabling */\\r
+ tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_COMPEN);\\r
+ UNUSED(tmpreg); \\r
+ } while(0U)\r
+\r
+\r
+#define __HAL_RCC_TIM2_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM2EN))\r
+#define __HAL_RCC_TIM3_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM3EN))\r
+#define __HAL_RCC_TIM4_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM4EN))\r
+#define __HAL_RCC_TIM6_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM6EN))\r
+#define __HAL_RCC_TIM7_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM7EN))\r
+#define __HAL_RCC_WWDG_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_WWDGEN))\r
+#define __HAL_RCC_SPI2_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_SPI2EN))\r
+#define __HAL_RCC_USART2_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_USART2EN))\r
+#define __HAL_RCC_USART3_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_USART3EN))\r
+#define __HAL_RCC_I2C1_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_I2C1EN))\r
+#define __HAL_RCC_I2C2_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_I2C2EN))\r
+#define __HAL_RCC_USB_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_USBEN))\r
+#define __HAL_RCC_PWR_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_PWREN))\r
+#define __HAL_RCC_DAC_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_DACEN))\r
+#define __HAL_RCC_COMP_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_COMPEN))\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup RCC_APB2_Clock_Enable_Disable APB2 Clock Enable Disable\r
+ * @brief Enable or disable the High Speed APB (APB2) peripheral clock.\r
+ * @note After reset, the peripheral clock (used for registers read/write access)\r
+ * is disabled and the application software has to enable this clock before\r
+ * using it.\r
+ * @{\r
+ */\r
+#define __HAL_RCC_SYSCFG_CLK_ENABLE() do { \\r
+ __IO uint32_t tmpreg; \\r
+ SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SYSCFGEN);\\r
+ /* Delay after an RCC peripheral clock enabling */\\r
+ tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SYSCFGEN);\\r
+ UNUSED(tmpreg); \\r
+ } while(0U)\r
+#define __HAL_RCC_TIM9_CLK_ENABLE() do { \\r
+ __IO uint32_t tmpreg; \\r
+ SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM9EN);\\r
+ /* Delay after an RCC peripheral clock enabling */\\r
+ tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM9EN);\\r
+ UNUSED(tmpreg); \\r
+ } while(0U)\r
+#define __HAL_RCC_TIM10_CLK_ENABLE() do { \\r
+ __IO uint32_t tmpreg; \\r
+ SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM10EN);\\r
+ /* Delay after an RCC peripheral clock enabling */\\r
+ tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM10EN);\\r
+ UNUSED(tmpreg); \\r
+ } while(0U)\r
+#define __HAL_RCC_TIM11_CLK_ENABLE() do { \\r
+ __IO uint32_t tmpreg; \\r
+ SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM11EN);\\r
+ /* Delay after an RCC peripheral clock enabling */\\r
+ tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM11EN);\\r
+ UNUSED(tmpreg); \\r
+ } while(0U)\r
+#define __HAL_RCC_ADC1_CLK_ENABLE() do { \\r
+ __IO uint32_t tmpreg; \\r
+ SET_BIT(RCC->APB2ENR, RCC_APB2ENR_ADC1EN);\\r
+ /* Delay after an RCC peripheral clock enabling */\\r
+ tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_ADC1EN);\\r
+ UNUSED(tmpreg); \\r
+ } while(0U)\r
+#define __HAL_RCC_SPI1_CLK_ENABLE() do { \\r
+ __IO uint32_t tmpreg; \\r
+ SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI1EN);\\r
+ /* Delay after an RCC peripheral clock enabling */\\r
+ tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI1EN);\\r
+ UNUSED(tmpreg); \\r
+ } while(0U)\r
+#define __HAL_RCC_USART1_CLK_ENABLE() do { \\r
+ __IO uint32_t tmpreg; \\r
+ SET_BIT(RCC->APB2ENR, RCC_APB2ENR_USART1EN);\\r
+ /* Delay after an RCC peripheral clock enabling */\\r
+ tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_USART1EN);\\r
+ UNUSED(tmpreg); \\r
+ } while(0U)\r
+\r
+#define __HAL_RCC_SYSCFG_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SYSCFGEN))\r
+#define __HAL_RCC_TIM9_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM9EN))\r
+#define __HAL_RCC_TIM10_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM10EN))\r
+#define __HAL_RCC_TIM11_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM11EN))\r
+#define __HAL_RCC_ADC1_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_ADC1EN))\r
+#define __HAL_RCC_SPI1_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SPI1EN))\r
+#define __HAL_RCC_USART1_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_USART1EN))\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup RCC_Peripheral_Clock_Force_Release RCC Peripheral Clock Force Release\r
+ * @brief Force or release AHB peripheral reset.\r
+ * @{\r
+ */\r
+#define __HAL_RCC_AHB_FORCE_RESET() (RCC->AHBRSTR = 0xFFFFFFFFU)\r
+#define __HAL_RCC_GPIOA_FORCE_RESET() (RCC->AHBRSTR |= (RCC_AHBRSTR_GPIOARST))\r
+#define __HAL_RCC_GPIOB_FORCE_RESET() (RCC->AHBRSTR |= (RCC_AHBRSTR_GPIOBRST))\r
+#define __HAL_RCC_GPIOC_FORCE_RESET() (RCC->AHBRSTR |= (RCC_AHBRSTR_GPIOCRST))\r
+#define __HAL_RCC_GPIOD_FORCE_RESET() (RCC->AHBRSTR |= (RCC_AHBRSTR_GPIODRST))\r
+#define __HAL_RCC_GPIOH_FORCE_RESET() (RCC->AHBRSTR |= (RCC_AHBRSTR_GPIOHRST))\r
+\r
+#define __HAL_RCC_CRC_FORCE_RESET() (RCC->AHBRSTR |= (RCC_AHBRSTR_CRCRST))\r
+#define __HAL_RCC_FLITF_FORCE_RESET() (RCC->AHBRSTR |= (RCC_AHBRSTR_FLITFRST))\r
+#define __HAL_RCC_DMA1_FORCE_RESET() (RCC->AHBRSTR |= (RCC_AHBRSTR_DMA1RST))\r
+\r
+#define __HAL_RCC_AHB_RELEASE_RESET() (RCC->AHBRSTR = 0x00000000U)\r
+#define __HAL_RCC_GPIOA_RELEASE_RESET() (RCC->AHBRSTR &= ~(RCC_AHBRSTR_GPIOARST))\r
+#define __HAL_RCC_GPIOB_RELEASE_RESET() (RCC->AHBRSTR &= ~(RCC_AHBRSTR_GPIOBRST))\r
+#define __HAL_RCC_GPIOC_RELEASE_RESET() (RCC->AHBRSTR &= ~(RCC_AHBRSTR_GPIOCRST))\r
+#define __HAL_RCC_GPIOD_RELEASE_RESET() (RCC->AHBRSTR &= ~(RCC_AHBRSTR_GPIODRST))\r
+#define __HAL_RCC_GPIOH_RELEASE_RESET() (RCC->AHBRSTR &= ~(RCC_AHBRSTR_GPIOHRST))\r
+\r
+#define __HAL_RCC_CRC_RELEASE_RESET() (RCC->AHBRSTR &= ~(RCC_AHBRSTR_CRCRST))\r
+#define __HAL_RCC_FLITF_RELEASE_RESET() (RCC->AHBRSTR &= ~(RCC_AHBRSTR_FLITFRST))\r
+#define __HAL_RCC_DMA1_RELEASE_RESET() (RCC->AHBRSTR &= ~(RCC_AHBRSTR_DMA1RST))\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup RCC_APB1_Force_Release_Reset APB1 Force Release Reset\r
+ * @brief Force or release APB1 peripheral reset.\r
+ * @{\r
+ */\r
+#define __HAL_RCC_APB1_FORCE_RESET() (RCC->APB1RSTR = 0xFFFFFFFFU)\r
+#define __HAL_RCC_TIM2_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM2RST))\r
+#define __HAL_RCC_TIM3_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM3RST))\r
+#define __HAL_RCC_TIM4_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM4RST))\r
+#define __HAL_RCC_TIM6_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM6RST))\r
+#define __HAL_RCC_TIM7_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM7RST))\r
+#define __HAL_RCC_WWDG_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_WWDGRST))\r
+#define __HAL_RCC_SPI2_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_SPI2RST))\r
+#define __HAL_RCC_USART2_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_USART2RST))\r
+#define __HAL_RCC_USART3_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_USART3RST))\r
+#define __HAL_RCC_I2C1_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_I2C1RST))\r
+#define __HAL_RCC_I2C2_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_I2C2RST))\r
+#define __HAL_RCC_USB_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_USBRST))\r
+#define __HAL_RCC_PWR_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_PWRRST))\r
+#define __HAL_RCC_DAC_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_DACRST))\r
+#define __HAL_RCC_COMP_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_COMPRST))\r
+\r
+#define __HAL_RCC_APB1_RELEASE_RESET() (RCC->APB1RSTR = 0x00000000U)\r
+#define __HAL_RCC_TIM2_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM2RST))\r
+#define __HAL_RCC_TIM3_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM3RST))\r
+#define __HAL_RCC_TIM4_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM4RST))\r
+#define __HAL_RCC_TIM6_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM6RST))\r
+#define __HAL_RCC_TIM7_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM7RST))\r
+#define __HAL_RCC_WWDG_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_WWDGRST))\r
+#define __HAL_RCC_SPI2_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_SPI2RST))\r
+#define __HAL_RCC_USART2_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_USART2RST))\r
+#define __HAL_RCC_USART3_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_USART3RST))\r
+#define __HAL_RCC_I2C1_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_I2C1RST))\r
+#define __HAL_RCC_I2C2_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_I2C2RST))\r
+#define __HAL_RCC_USB_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_USBRST))\r
+#define __HAL_RCC_PWR_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_PWRRST))\r
+#define __HAL_RCC_DAC_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_DACRST))\r
+#define __HAL_RCC_COMP_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_COMPRST))\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup RCC_APB2_Force_Release_Reset APB2 Force Release Reset\r
+ * @brief Force or release APB1 peripheral reset.\r
+ * @{\r
+ */\r
+#define __HAL_RCC_APB2_FORCE_RESET() (RCC->APB2RSTR = 0xFFFFFFFFU)\r
+#define __HAL_RCC_SYSCFG_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_SYSCFGRST))\r
+#define __HAL_RCC_TIM9_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_TIM9RST))\r
+#define __HAL_RCC_TIM10_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_TIM10RST))\r
+#define __HAL_RCC_TIM11_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_TIM11RST))\r
+#define __HAL_RCC_ADC1_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_ADC1RST))\r
+#define __HAL_RCC_SPI1_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_SPI1RST))\r
+#define __HAL_RCC_USART1_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_USART1RST))\r
+\r
+#define __HAL_RCC_APB2_RELEASE_RESET() (RCC->APB2RSTR = 0x00000000U)\r
+#define __HAL_RCC_SYSCFG_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SYSCFGRST))\r
+#define __HAL_RCC_TIM9_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM9RST))\r
+#define __HAL_RCC_TIM10_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM10RST))\r
+#define __HAL_RCC_TIM11_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM11RST))\r
+#define __HAL_RCC_ADC1_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_ADC1RST))\r
+#define __HAL_RCC_SPI1_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SPI1RST))\r
+#define __HAL_RCC_USART1_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_USART1RST))\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup RCC_Peripheral_Clock_Sleep_Enable_Disable RCC Peripheral Clock Sleep Enable Disable\r
+ * @note Peripheral clock gating in SLEEP mode can be used to further reduce\r
+ * power consumption.\r
+ * @note After wakeup from SLEEP mode, the peripheral clock is enabled again.\r
+ * @note By default, all peripheral clocks are enabled during SLEEP mode.\r
+ * @{\r
+ */\r
+#define __HAL_RCC_GPIOA_CLK_SLEEP_ENABLE() (RCC->AHBLPENR |= (RCC_AHBLPENR_GPIOALPEN))\r
+#define __HAL_RCC_GPIOB_CLK_SLEEP_ENABLE() (RCC->AHBLPENR |= (RCC_AHBLPENR_GPIOBLPEN))\r
+#define __HAL_RCC_GPIOC_CLK_SLEEP_ENABLE() (RCC->AHBLPENR |= (RCC_AHBLPENR_GPIOCLPEN))\r
+#define __HAL_RCC_GPIOD_CLK_SLEEP_ENABLE() (RCC->AHBLPENR |= (RCC_AHBLPENR_GPIODLPEN))\r
+#define __HAL_RCC_GPIOH_CLK_SLEEP_ENABLE() (RCC->AHBLPENR |= (RCC_AHBLPENR_GPIOHLPEN))\r
+\r
+#define __HAL_RCC_CRC_CLK_SLEEP_ENABLE() (RCC->AHBLPENR |= (RCC_AHBLPENR_CRCLPEN))\r
+#define __HAL_RCC_FLITF_CLK_SLEEP_ENABLE() (RCC->AHBLPENR |= (RCC_AHBLPENR_FLITFLPEN))\r
+#define __HAL_RCC_DMA1_CLK_SLEEP_ENABLE() (RCC->AHBLPENR |= (RCC_AHBLPENR_DMA1LPEN))\r
+\r
+#define __HAL_RCC_GPIOA_CLK_SLEEP_DISABLE() (RCC->AHBLPENR &= ~(RCC_AHBLPENR_GPIOALPEN))\r
+#define __HAL_RCC_GPIOB_CLK_SLEEP_DISABLE() (RCC->AHBLPENR &= ~(RCC_AHBLPENR_GPIOBLPEN))\r
+#define __HAL_RCC_GPIOC_CLK_SLEEP_DISABLE() (RCC->AHBLPENR &= ~(RCC_AHBLPENR_GPIOCLPEN))\r
+#define __HAL_RCC_GPIOD_CLK_SLEEP_DISABLE() (RCC->AHBLPENR &= ~(RCC_AHBLPENR_GPIODLPEN))\r
+#define __HAL_RCC_GPIOH_CLK_SLEEP_DISABLE() (RCC->AHBLPENR &= ~(RCC_AHBLPENR_GPIOHLPEN))\r
+\r
+#define __HAL_RCC_CRC_CLK_SLEEP_DISABLE() (RCC->AHBLPENR &= ~(RCC_AHBLPENR_CRCLPEN))\r
+#define __HAL_RCC_FLITF_CLK_SLEEP_DISABLE() (RCC->AHBLPENR &= ~(RCC_AHBLPENR_FLITFLPEN))\r
+#define __HAL_RCC_DMA1_CLK_SLEEP_DISABLE() (RCC->AHBLPENR &= ~(RCC_AHBLPENR_DMA1LPEN))\r
+\r
+/** @brief Enable or disable the APB1 peripheral clock during Low Power (Sleep) mode.\r
+ * @note Peripheral clock gating in SLEEP mode can be used to further reduce\r
+ * power consumption.\r
+ * @note After wakeup from SLEEP mode, the peripheral clock is enabled again.\r
+ * @note By default, all peripheral clocks are enabled during SLEEP mode.\r
+ */\r
+#define __HAL_RCC_TIM2_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM2LPEN))\r
+#define __HAL_RCC_TIM3_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM3LPEN))\r
+#define __HAL_RCC_TIM4_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM4LPEN))\r
+#define __HAL_RCC_TIM6_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM6LPEN))\r
+#define __HAL_RCC_TIM7_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM7LPEN))\r
+#define __HAL_RCC_WWDG_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_WWDGLPEN))\r
+#define __HAL_RCC_SPI2_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_SPI2LPEN))\r
+#define __HAL_RCC_USART2_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_USART2LPEN))\r
+#define __HAL_RCC_USART3_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_USART3LPEN))\r
+#define __HAL_RCC_I2C1_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_I2C1LPEN))\r
+#define __HAL_RCC_I2C2_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_I2C2LPEN))\r
+#define __HAL_RCC_USB_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_USBLPEN))\r
+#define __HAL_RCC_PWR_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_PWRLPEN))\r
+#define __HAL_RCC_DAC_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_DACLPEN))\r
+#define __HAL_RCC_COMP_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_COMPLPEN))\r
+\r
+#define __HAL_RCC_TIM2_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM2LPEN))\r
+#define __HAL_RCC_TIM3_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM3LPEN))\r
+#define __HAL_RCC_TIM4_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM4LPEN))\r
+#define __HAL_RCC_TIM6_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM6LPEN))\r
+#define __HAL_RCC_TIM7_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM7LPEN))\r
+#define __HAL_RCC_WWDG_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_WWDGLPEN))\r
+#define __HAL_RCC_SPI2_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_SPI2LPEN))\r
+#define __HAL_RCC_USART2_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_USART2LPEN))\r
+#define __HAL_RCC_USART3_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_USART3LPEN))\r
+#define __HAL_RCC_I2C1_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_I2C1LPEN))\r
+#define __HAL_RCC_I2C2_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_I2C2LPEN))\r
+#define __HAL_RCC_USB_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_USBLPEN))\r
+#define __HAL_RCC_PWR_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_PWRLPEN))\r
+#define __HAL_RCC_DAC_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_DACLPEN))\r
+#define __HAL_RCC_COMP_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_COMPLPEN))\r
+\r
+/** @brief Enable or disable the APB2 peripheral clock during Low Power (Sleep) mode.\r
+ * @note Peripheral clock gating in SLEEP mode can be used to further reduce\r
+ * power consumption.\r
+ * @note After wakeup from SLEEP mode, the peripheral clock is enabled again.\r
+ * @note By default, all peripheral clocks are enabled during SLEEP mode.\r
+ */\r
+#define __HAL_RCC_SYSCFG_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_SYSCFGLPEN))\r
+#define __HAL_RCC_TIM9_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_TIM9LPEN))\r
+#define __HAL_RCC_TIM10_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_TIM10LPEN))\r
+#define __HAL_RCC_TIM11_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_TIM11LPEN))\r
+#define __HAL_RCC_ADC1_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_ADC1LPEN))\r
+#define __HAL_RCC_SPI1_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_SPI1LPEN))\r
+#define __HAL_RCC_USART1_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_USART1LPEN))\r
+\r
+#define __HAL_RCC_SYSCFG_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_SYSCFGLPEN))\r
+#define __HAL_RCC_TIM9_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_TIM9LPEN))\r
+#define __HAL_RCC_TIM10_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_TIM10LPEN))\r
+#define __HAL_RCC_TIM11_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_TIM11LPEN))\r
+#define __HAL_RCC_ADC1_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_ADC1LPEN))\r
+#define __HAL_RCC_SPI1_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_SPI1LPEN))\r
+#define __HAL_RCC_USART1_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_USART1LPEN))\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup RCC_AHB_Peripheral_Clock_Enable_Disable_Status AHB Peripheral Clock Enable Disable Status\r
+ * @brief Get the enable or disable status of the AHB peripheral clock.\r
+ * @note After reset, the peripheral clock (used for registers read/write access)\r
+ * is disabled and the application software has to enable this clock before\r
+ * using it.\r
+ * @{\r
+ */\r
+\r
+#define __HAL_RCC_GPIOA_IS_CLK_ENABLED() ((RCC->AHBENR & (RCC_AHBENR_GPIOAEN)) != 0U)\r
+#define __HAL_RCC_GPIOB_IS_CLK_ENABLED() ((RCC->AHBENR & (RCC_AHBENR_GPIOBEN)) != 0U)\r
+#define __HAL_RCC_GPIOC_IS_CLK_ENABLED() ((RCC->AHBENR & (RCC_AHBENR_GPIOCEN)) != 0U)\r
+#define __HAL_RCC_GPIOD_IS_CLK_ENABLED() ((RCC->AHBENR & (RCC_AHBENR_GPIODEN)) != 0U)\r
+#define __HAL_RCC_GPIOH_IS_CLK_ENABLED() ((RCC->AHBENR & (RCC_AHBENR_GPIOHEN)) != 0U)\r
+#define __HAL_RCC_CRC_IS_CLK_ENABLED() ((RCC->AHBENR & (RCC_AHBENR_CRCEN)) != 0U)\r
+#define __HAL_RCC_FLITF_IS_CLK_ENABLED() ((RCC->AHBENR & (RCC_AHBENR_FLITFEN)) != 0U)\r
+#define __HAL_RCC_DMA1_IS_CLK_ENABLED() ((RCC->AHBENR & (RCC_AHBENR_DMA1EN)) != 0U)\r
+#define __HAL_RCC_GPIOA_IS_CLK_DISABLED() ((RCC->AHBENR & (RCC_AHBENR_GPIOAEN)) == 0U)\r
+#define __HAL_RCC_GPIOB_IS_CLK_DISABLED() ((RCC->AHBENR & (RCC_AHBENR_GPIOBEN)) == 0U)\r
+#define __HAL_RCC_GPIOC_IS_CLK_DISABLED() ((RCC->AHBENR & (RCC_AHBENR_GPIOCEN)) == 0U)\r
+#define __HAL_RCC_GPIOD_IS_CLK_DISABLED() ((RCC->AHBENR & (RCC_AHBENR_GPIODEN)) == 0U)\r
+#define __HAL_RCC_GPIOH_IS_CLK_DISABLED() ((RCC->AHBENR & (RCC_AHBENR_GPIOHEN)) == 0U)\r
+#define __HAL_RCC_CRC_IS_CLK_DISABLED() ((RCC->AHBENR & (RCC_AHBENR_CRCEN)) == 0U)\r
+#define __HAL_RCC_FLITF_IS_CLK_DISABLED() ((RCC->AHBENR & (RCC_AHBENR_FLITFEN)) == 0U)\r
+#define __HAL_RCC_DMA1_IS_CLK_DISABLED() ((RCC->AHBENR & (RCC_AHBENR_DMA1EN)) == 0U)\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup RCC_APB1_Peripheral_Clock_Enable_Disable_Status APB1 Peripheral Clock Enable Disable Status\r
+ * @brief Get the enable or disable status of the APB1 peripheral clock.\r
+ * @note After reset, the peripheral clock (used for registers read/write access)\r
+ * is disabled and the application software has to enable this clock before\r
+ * using it.\r
+ * @{\r
+ */\r
+\r
+#define __HAL_RCC_TIM2_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM2EN)) != 0U)\r
+#define __HAL_RCC_TIM3_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM3EN)) != 0U)\r
+#define __HAL_RCC_TIM4_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM4EN)) != 0U)\r
+#define __HAL_RCC_TIM6_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM6EN)) != 0U)\r
+#define __HAL_RCC_TIM7_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM7EN)) != 0U)\r
+#define __HAL_RCC_WWDG_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_WWDGEN)) != 0U)\r
+#define __HAL_RCC_SPI2_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_SPI2EN)) != 0U)\r
+#define __HAL_RCC_USART2_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_USART2EN)) != 0U)\r
+#define __HAL_RCC_USART3_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_USART3EN)) != 0U)\r
+#define __HAL_RCC_I2C1_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_I2C1EN)) != 0U)\r
+#define __HAL_RCC_I2C2_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_I2C2EN)) != 0U)\r
+#define __HAL_RCC_USB_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_USBEN)) != 0U)\r
+#define __HAL_RCC_PWR_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_PWREN)) != 0U)\r
+#define __HAL_RCC_DAC_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_DACEN)) != 0U)\r
+#define __HAL_RCC_COMP_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_COMPEN)) != 0U)\r
+#define __HAL_RCC_TIM2_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM2EN)) == 0U)\r
+#define __HAL_RCC_TIM3_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM3EN)) == 0U)\r
+#define __HAL_RCC_TIM4_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM4EN)) == 0U)\r
+#define __HAL_RCC_TIM6_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM6EN)) == 0U)\r
+#define __HAL_RCC_TIM7_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM7EN)) == 0U)\r
+#define __HAL_RCC_WWDG_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_WWDGEN)) == 0U)\r
+#define __HAL_RCC_SPI2_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_SPI2EN)) == 0U)\r
+#define __HAL_RCC_USART2_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_USART2EN)) == 0U)\r
+#define __HAL_RCC_USART3_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_USART3EN)) == 0U)\r
+#define __HAL_RCC_I2C1_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_I2C1EN)) == 0U)\r
+#define __HAL_RCC_I2C2_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_I2C2EN)) == 0U)\r
+#define __HAL_RCC_USB_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_USBEN)) == 0U)\r
+#define __HAL_RCC_PWR_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_PWREN)) == 0U)\r
+#define __HAL_RCC_DAC_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_DACEN)) == 0U)\r
+#define __HAL_RCC_COMP_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_COMPEN)) == 0U)\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup RCC_APB2_Peripheral_Clock_Enable_Disable_Status APB2 Peripheral Clock Enable Disable Status\r
+ * @brief Get the enable or disable status of the APB2 peripheral clock.\r
+ * @note After reset, the peripheral clock (used for registers read/write access)\r
+ * is disabled and the application software has to enable this clock before\r
+ * using it.\r
+ * @{\r
+ */\r
+\r
+#define __HAL_RCC_SYSCFG_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SYSCFGEN)) != 0U)\r
+#define __HAL_RCC_TIM9_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM9EN)) != 0U)\r
+#define __HAL_RCC_TIM10_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM10EN)) != 0U)\r
+#define __HAL_RCC_TIM11_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM11EN)) != 0U)\r
+#define __HAL_RCC_ADC1_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_ADC1EN)) != 0U)\r
+#define __HAL_RCC_SPI1_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SPI1EN)) != 0U)\r
+#define __HAL_RCC_USART1_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_USART1EN)) != 0U)\r
+#define __HAL_RCC_SYSCFG_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SYSCFGEN)) == 0U)\r
+#define __HAL_RCC_TIM9_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM9EN)) == 0U)\r
+#define __HAL_RCC_TIM10_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM10EN)) == 0U)\r
+#define __HAL_RCC_TIM11_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM11EN)) == 0U)\r
+#define __HAL_RCC_ADC1_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_ADC1EN)) == 0U)\r
+#define __HAL_RCC_SPI1_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SPI1EN)) == 0U)\r
+#define __HAL_RCC_USART1_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_USART1EN)) == 0U)\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup RCC_AHB_Clock_Sleep_Enable_Disable_Status AHB Peripheral Clock Sleep Enable Disable Status\r
+ * @brief Get the enable or disable status of the AHB peripheral clock during Low Power (Sleep) mode.\r
+ * @note Peripheral clock gating in SLEEP mode can be used to further reduce\r
+ * power consumption.\r
+ * @note After wakeup from SLEEP mode, the peripheral clock is enabled again.\r
+ * @note By default, all peripheral clocks are enabled during SLEEP mode.\r
+ * @{\r
+ */\r
+\r
+#define __HAL_RCC_GPIOA_IS_CLK_SLEEP_ENABLED() ((RCC->AHBLPENR & (RCC_AHBLPENR_GPIOALPEN)) != 0U)\r
+#define __HAL_RCC_GPIOB_IS_CLK_SLEEP_ENABLED() ((RCC->AHBLPENR & (RCC_AHBLPENR_GPIOBLPEN)) != 0U)\r
+#define __HAL_RCC_GPIOC_IS_CLK_SLEEP_ENABLED() ((RCC->AHBLPENR & (RCC_AHBLPENR_GPIOCLPEN)) != 0U)\r
+#define __HAL_RCC_GPIOD_IS_CLK_SLEEP_ENABLED() ((RCC->AHBLPENR & (RCC_AHBLPENR_GPIODLPEN)) != 0U)\r
+#define __HAL_RCC_GPIOH_IS_CLK_SLEEP_ENABLED() ((RCC->AHBLPENR & (RCC_AHBLPENR_GPIOHLPEN)) != 0U)\r
+#define __HAL_RCC_CRC_IS_CLK_SLEEP_ENABLED() ((RCC->AHBLPENR & (RCC_AHBLPENR_CRCLPEN)) != 0U)\r
+#define __HAL_RCC_FLITF_IS_CLK_SLEEP_ENABLED() ((RCC->AHBLPENR & (RCC_AHBLPENR_FLITFLPEN)) != 0U)\r
+#define __HAL_RCC_DMA1_IS_CLK_SLEEP_ENABLED() ((RCC->AHBLPENR & (RCC_AHBLPENR_DMA1LPEN)) != 0U)\r
+#define __HAL_RCC_GPIOA_IS_CLK_SLEEP_DISABLED() ((RCC->AHBLPENR & (RCC_AHBLPENR_GPIOALPEN)) == 0U)\r
+#define __HAL_RCC_GPIOB_IS_CLK_SLEEP_DISABLED() ((RCC->AHBLPENR & (RCC_AHBLPENR_GPIOBLPEN)) == 0U)\r
+#define __HAL_RCC_GPIOC_IS_CLK_SLEEP_DISABLED() ((RCC->AHBLPENR & (RCC_AHBLPENR_GPIOCLPEN)) == 0U)\r
+#define __HAL_RCC_GPIOD_IS_CLK_SLEEP_DISABLED() ((RCC->AHBLPENR & (RCC_AHBLPENR_GPIODLPEN)) == 0U)\r
+#define __HAL_RCC_GPIOH_IS_CLK_SLEEP_DISABLED() ((RCC->AHBLPENR & (RCC_AHBLPENR_GPIOHLPEN)) == 0U)\r
+#define __HAL_RCC_CRC_IS_CLK_SLEEP_DISABLED() ((RCC->AHBLPENR & (RCC_AHBLPENR_CRCLPEN)) == 0U)\r
+#define __HAL_RCC_FLITF_IS_CLK_SLEEP_DISABLED() ((RCC->AHBLPENR & (RCC_AHBLPENR_FLITFLPEN)) == 0U)\r
+#define __HAL_RCC_DMA1_IS_CLK_SLEEP_DISABLED() ((RCC->AHBLPENR & (RCC_AHBLPENR_DMA1LPEN)) == 0U)\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup RCC_APB1_Clock_Sleep_Enable_Disable_Status APB1 Peripheral Clock Sleep Enable Disable Status\r
+ * @brief Get the enable or disable status of the APB1 peripheral clock during Low Power (Sleep) mode.\r
+ * @note Peripheral clock gating in SLEEP mode can be used to further reduce\r
+ * power consumption.\r
+ * @note After wakeup from SLEEP mode, the peripheral clock is enabled again.\r
+ * @note By default, all peripheral clocks are enabled during SLEEP mode.\r
+ * @{\r
+ */\r
+\r
+#define __HAL_RCC_TIM2_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_TIM2LPEN)) != 0U)\r
+#define __HAL_RCC_TIM3_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_TIM3LPEN)) != 0U)\r
+#define __HAL_RCC_TIM4_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_TIM4LPEN)) != 0U)\r
+#define __HAL_RCC_TIM6_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_TIM6LPEN)) != 0U)\r
+#define __HAL_RCC_TIM7_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_TIM7LPEN)) != 0U)\r
+#define __HAL_RCC_WWDG_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_WWDGLPEN)) != 0U)\r
+#define __HAL_RCC_SPI2_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_SPI2LPEN)) != 0U)\r
+#define __HAL_RCC_USART2_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_USART2LPEN)) != 0U)\r
+#define __HAL_RCC_USART3_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_USART3LPEN)) != 0U)\r
+#define __HAL_RCC_I2C1_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_I2C1LPEN)) != 0U)\r
+#define __HAL_RCC_I2C2_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_I2C2LPEN)) != 0U)\r
+#define __HAL_RCC_USB_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_USBLPEN)) != 0U)\r
+#define __HAL_RCC_PWR_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_PWRLPEN)) != 0U)\r
+#define __HAL_RCC_DAC_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_DACLPEN)) != 0U)\r
+#define __HAL_RCC_COMP_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_COMPLPEN)) != 0U)\r
+#define __HAL_RCC_TIM2_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_TIM2LPEN)) == 0U)\r
+#define __HAL_RCC_TIM3_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_TIM3LPEN)) == 0U)\r
+#define __HAL_RCC_TIM4_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_TIM4LPEN)) == 0U)\r
+#define __HAL_RCC_TIM6_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_TIM6LPEN)) == 0U)\r
+#define __HAL_RCC_TIM7_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_TIM7LPEN)) == 0U)\r
+#define __HAL_RCC_WWDG_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_WWDGLPEN)) == 0U)\r
+#define __HAL_RCC_SPI2_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_SPI2LPEN)) == 0U)\r
+#define __HAL_RCC_USART2_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_USART2LPEN)) == 0U)\r
+#define __HAL_RCC_USART3_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_USART3LPEN)) == 0U)\r
+#define __HAL_RCC_I2C1_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_I2C1LPEN)) == 0U)\r
+#define __HAL_RCC_I2C2_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_I2C2LPEN)) == 0U)\r
+#define __HAL_RCC_USB_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_USBLPEN)) == 0U)\r
+#define __HAL_RCC_PWR_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_PWRLPEN)) == 0U)\r
+#define __HAL_RCC_DAC_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_DACLPEN)) == 0U)\r
+#define __HAL_RCC_COMP_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_COMPLPEN)) == 0U)\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup RCC_APB2_Clock_Sleep_Enable_Disable_Status APB2 Peripheral Clock Sleep Enable Disable Status\r
+ * @brief Get the enable or disable status of the APB2 peripheral clock during Low Power (Sleep) mode.\r
+ * @note Peripheral clock gating in SLEEP mode can be used to further reduce\r
+ * power consumption.\r
+ * @note After wakeup from SLEEP mode, the peripheral clock is enabled again.\r
+ * @note By default, all peripheral clocks are enabled during SLEEP mode.\r
+ * @{\r
+ */\r
+\r
+#define __HAL_RCC_SYSCFG_IS_CLK_SLEEP_ENABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_SYSCFGLPEN)) != 0U)\r
+#define __HAL_RCC_TIM9_IS_CLK_SLEEP_ENABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_TIM9LPEN)) != 0U)\r
+#define __HAL_RCC_TIM10_IS_CLK_SLEEP_ENABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_TIM10LPEN)) != 0U)\r
+#define __HAL_RCC_TIM11_IS_CLK_SLEEP_ENABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_TIM11LPEN)) != 0U)\r
+#define __HAL_RCC_ADC1_IS_CLK_SLEEP_ENABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_ADC1LPEN)) != 0U)\r
+#define __HAL_RCC_SPI1_IS_CLK_SLEEP_ENABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_SPI1LPEN)) != 0U)\r
+#define __HAL_RCC_USART1_IS_CLK_SLEEP_ENABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_USART1LPEN)) != 0U)\r
+#define __HAL_RCC_SYSCFG_IS_CLK_SLEEP_DISABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_SYSCFGLPEN)) == 0U)\r
+#define __HAL_RCC_TIM9_IS_CLK_SLEEP_DISABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_TIM9LPEN)) == 0U)\r
+#define __HAL_RCC_TIM10_IS_CLK_SLEEP_DISABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_TIM10LPEN)) == 0U)\r
+#define __HAL_RCC_TIM11_IS_CLK_SLEEP_DISABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_TIM11LPEN)) == 0U)\r
+#define __HAL_RCC_ADC1_IS_CLK_SLEEP_DISABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_ADC1LPEN)) == 0U)\r
+#define __HAL_RCC_SPI1_IS_CLK_SLEEP_DISABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_SPI1LPEN)) == 0U)\r
+#define __HAL_RCC_USART1_IS_CLK_SLEEP_DISABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_USART1LPEN)) == 0U)\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup RCC_HSI_Configuration HSI Configuration\r
+ * @{\r
+ */\r
+\r
+/** @brief Macros to enable or disable the Internal High Speed oscillator (HSI).\r
+ * @note The HSI is stopped by hardware when entering STOP and STANDBY modes.\r
+ * @note HSI can not be stopped if it is used as system clock source. In this case,\r
+ * you have to select another source of the system clock then stop the HSI.\r
+ * @note After enabling the HSI, the application software should wait on HSIRDY\r
+ * flag to be set indicating that HSI clock is stable and can be used as\r
+ * system clock source.\r
+ * @note When the HSI is stopped, HSIRDY flag goes low after 6 HSI oscillator\r
+ * clock cycles.\r
+ */\r
+#define __HAL_RCC_HSI_ENABLE() (*(__IO uint32_t *) RCC_CR_HSION_BB = ENABLE)\r
+#define __HAL_RCC_HSI_DISABLE() (*(__IO uint32_t *) RCC_CR_HSION_BB = DISABLE)\r
+\r
+/** @brief Macro to adjust the Internal High Speed oscillator (HSI) calibration value.\r
+ * @note The calibration is used to compensate for the variations in voltage\r
+ * and temperature that influence the frequency of the internal HSI RC.\r
+ * @param _HSICALIBRATIONVALUE_ specifies the calibration trimming value.\r
+ * (default is RCC_HSICALIBRATION_DEFAULT).\r
+ * This parameter must be a number between 0 and 0x1F.\r
+ */\r
+#define __HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(_HSICALIBRATIONVALUE_) \\r
+ (MODIFY_REG(RCC->ICSCR, RCC_ICSCR_HSITRIM, (uint32_t)(_HSICALIBRATIONVALUE_) << RCC_ICSCR_HSITRIM_Pos))\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup RCC_LSI_Configuration LSI Configuration\r
+ * @{\r
+ */\r
+\r
+/** @brief Macro to enable the Internal Low Speed oscillator (LSI).\r
+ * @note After enabling the LSI, the application software should wait on\r
+ * LSIRDY flag to be set indicating that LSI clock is stable and can\r
+ * be used to clock the IWDG and/or the RTC.\r
+ */\r
+#define __HAL_RCC_LSI_ENABLE() (*(__IO uint32_t *) RCC_CSR_LSION_BB = ENABLE)\r
+\r
+/** @brief Macro to disable the Internal Low Speed oscillator (LSI).\r
+ * @note LSI can not be disabled if the IWDG is running.\r
+ * @note When the LSI is stopped, LSIRDY flag goes low after 6 LSI oscillator\r
+ * clock cycles.\r
+ */\r
+#define __HAL_RCC_LSI_DISABLE() (*(__IO uint32_t *) RCC_CSR_LSION_BB = DISABLE)\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup RCC_HSE_Configuration HSE Configuration\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @brief Macro to configure the External High Speed oscillator (HSE).\r
+ * @note Transition HSE Bypass to HSE On and HSE On to HSE Bypass are not\r
+ * supported by this macro. User should request a transition to HSE Off\r
+ * first and then HSE On or HSE Bypass.\r
+ * @note After enabling the HSE (RCC_HSE_ON or RCC_HSE_Bypass), the application\r
+ * software should wait on HSERDY flag to be set indicating that HSE clock\r
+ * is stable and can be used to clock the PLL and/or system clock.\r
+ * @note HSE state can not be changed if it is used directly or through the\r
+ * PLL as system clock. In this case, you have to select another source\r
+ * of the system clock then change the HSE state (ex. disable it).\r
+ * @note The HSE is stopped by hardware when entering STOP and STANDBY modes.\r
+ * @note This function reset the CSSON bit, so if the clock security system(CSS)\r
+ * was previously enabled you have to enable it again after calling this\r
+ * function.\r
+ * @param __STATE__ specifies the new state of the HSE.\r
+ * This parameter can be one of the following values:\r
+ * @arg @ref RCC_HSE_OFF turn OFF the HSE oscillator, HSERDY flag goes low after\r
+ * 6 HSE oscillator clock cycles.\r
+ * @arg @ref RCC_HSE_ON turn ON the HSE oscillator\r
+ * @arg @ref RCC_HSE_BYPASS HSE oscillator bypassed with external clock\r
+ */\r
+#define __HAL_RCC_HSE_CONFIG(__STATE__) \\r
+ do{ \\r
+ if ((__STATE__) == RCC_HSE_ON) \\r
+ { \\r
+ SET_BIT(RCC->CR, RCC_CR_HSEON); \\r
+ } \\r
+ else if ((__STATE__) == RCC_HSE_OFF) \\r
+ { \\r
+ CLEAR_BIT(RCC->CR, RCC_CR_HSEON); \\r
+ CLEAR_BIT(RCC->CR, RCC_CR_HSEBYP); \\r
+ } \\r
+ else if ((__STATE__) == RCC_HSE_BYPASS) \\r
+ { \\r
+ SET_BIT(RCC->CR, RCC_CR_HSEBYP); \\r
+ SET_BIT(RCC->CR, RCC_CR_HSEON); \\r
+ } \\r
+ else \\r
+ { \\r
+ CLEAR_BIT(RCC->CR, RCC_CR_HSEON); \\r
+ CLEAR_BIT(RCC->CR, RCC_CR_HSEBYP); \\r
+ } \\r
+ }while(0U)\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup RCC_LSE_Configuration LSE Configuration\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @brief Macro to configure the External Low Speed oscillator (LSE).\r
+ * @note Transitions LSE Bypass to LSE On and LSE On to LSE Bypass are not supported by this macro.\r
+ * @note As the LSE is in the Backup domain and write access is denied to\r
+ * this domain after reset, you have to enable write access using\r
+ * @ref HAL_PWR_EnableBkUpAccess() function before to configure the LSE\r
+ * (to be done once after reset).\r
+ * @note After enabling the LSE (RCC_LSE_ON or RCC_LSE_BYPASS), the application\r
+ * software should wait on LSERDY flag to be set indicating that LSE clock\r
+ * is stable and can be used to clock the RTC.\r
+ * @param __STATE__ specifies the new state of the LSE.\r
+ * This parameter can be one of the following values:\r
+ * @arg @ref RCC_LSE_OFF turn OFF the LSE oscillator, LSERDY flag goes low after\r
+ * 6 LSE oscillator clock cycles.\r
+ * @arg @ref RCC_LSE_ON turn ON the LSE oscillator.\r
+ * @arg @ref RCC_LSE_BYPASS LSE oscillator bypassed with external clock.\r
+ */\r
+#define __HAL_RCC_LSE_CONFIG(__STATE__) \\r
+ do{ \\r
+ if ((__STATE__) == RCC_LSE_ON) \\r
+ { \\r
+ SET_BIT(RCC->CSR, RCC_CSR_LSEON); \\r
+ } \\r
+ else if ((__STATE__) == RCC_LSE_OFF) \\r
+ { \\r
+ CLEAR_BIT(RCC->CSR, RCC_CSR_LSEON); \\r
+ CLEAR_BIT(RCC->CSR, RCC_CSR_LSEBYP); \\r
+ } \\r
+ else if ((__STATE__) == RCC_LSE_BYPASS) \\r
+ { \\r
+ SET_BIT(RCC->CSR, RCC_CSR_LSEBYP); \\r
+ SET_BIT(RCC->CSR, RCC_CSR_LSEON); \\r
+ } \\r
+ else \\r
+ { \\r
+ CLEAR_BIT(RCC->CSR, RCC_CSR_LSEON); \\r
+ CLEAR_BIT(RCC->CSR, RCC_CSR_LSEBYP); \\r
+ } \\r
+ }while(0U)\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup RCC_MSI_Configuration MSI Configuration\r
+ * @{\r
+ */\r
+\r
+/** @brief Macro to enable Internal Multi Speed oscillator (MSI).\r
+ * @note After enabling the MSI, the application software should wait on MSIRDY\r
+ * flag to be set indicating that MSI clock is stable and can be used as\r
+ * system clock source.\r
+ */\r
+#define __HAL_RCC_MSI_ENABLE() (*(__IO uint32_t *) RCC_CR_MSION_BB = ENABLE)\r
+\r
+/** @brief Macro to disable the Internal Multi Speed oscillator (MSI).\r
+ * @note The MSI is stopped by hardware when entering STOP and STANDBY modes.\r
+ * It is used (enabled by hardware) as system clock source after startup\r
+ * from Reset, wakeup from STOP and STANDBY mode, or in case of failure\r
+ * of the HSE used directly or indirectly as system clock (if the Clock\r
+ * Security System CSS is enabled).\r
+ * @note MSI can not be stopped if it is used as system clock source. In this case,\r
+ * you have to select another source of the system clock then stop the MSI.\r
+ * @note When the MSI is stopped, MSIRDY flag goes low after 6 MSI oscillator\r
+ * clock cycles.\r
+ */\r
+#define __HAL_RCC_MSI_DISABLE() (*(__IO uint32_t *) RCC_CR_MSION_BB = DISABLE)\r
+\r
+/** @brief Macro adjusts Internal Multi Speed oscillator (MSI) calibration value.\r
+ * @note The calibration is used to compensate for the variations in voltage\r
+ * and temperature that influence the frequency of the internal MSI RC.\r
+ * @param _MSICALIBRATIONVALUE_ specifies the calibration trimming value.\r
+ * (default is RCC_MSICALIBRATION_DEFAULT).\r
+ * This parameter must be a number between 0 and 0xFF.\r
+ */\r
+#define __HAL_RCC_MSI_CALIBRATIONVALUE_ADJUST(_MSICALIBRATIONVALUE_) \\r
+ (MODIFY_REG(RCC->ICSCR, RCC_ICSCR_MSITRIM, (uint32_t)(_MSICALIBRATIONVALUE_) << RCC_ICSCR_MSITRIM_Pos))\r
+\r
+/* @brief Macro to configures the Internal Multi Speed oscillator (MSI) clock range.\r
+ * @note After restart from Reset or wakeup from STANDBY, the MSI clock is\r
+ * around 2.097 MHz. The MSI clock does not change after wake-up from\r
+ * STOP mode.\r
+ * @note The MSI clock range can be modified on the fly.\r
+ * @param _MSIRANGEVALUE_ specifies the MSI Clock range.\r
+ * This parameter must be one of the following values:\r
+ * @arg @ref RCC_MSIRANGE_0 MSI clock is around 65.536 KHz\r
+ * @arg @ref RCC_MSIRANGE_1 MSI clock is around 131.072 KHz\r
+ * @arg @ref RCC_MSIRANGE_2 MSI clock is around 262.144 KHz\r
+ * @arg @ref RCC_MSIRANGE_3 MSI clock is around 524.288 KHz\r
+ * @arg @ref RCC_MSIRANGE_4 MSI clock is around 1.048 MHz\r
+ * @arg @ref RCC_MSIRANGE_5 MSI clock is around 2.097 MHz (default after Reset or wake-up from STANDBY)\r
+ * @arg @ref RCC_MSIRANGE_6 MSI clock is around 4.194 MHz\r
+ */\r
+#define __HAL_RCC_MSI_RANGE_CONFIG(_MSIRANGEVALUE_) (MODIFY_REG(RCC->ICSCR, \\r
+ RCC_ICSCR_MSIRANGE, (uint32_t)(_MSIRANGEVALUE_)))\r
+\r
+/** @brief Macro to get the Internal Multi Speed oscillator (MSI) clock range in run mode\r
+ * @retval MSI clock range.\r
+ * This parameter must be one of the following values:\r
+ * @arg @ref RCC_MSIRANGE_0 MSI clock is around 65.536 KHz\r
+ * @arg @ref RCC_MSIRANGE_1 MSI clock is around 131.072 KHz\r
+ * @arg @ref RCC_MSIRANGE_2 MSI clock is around 262.144 KHz\r
+ * @arg @ref RCC_MSIRANGE_3 MSI clock is around 524.288 KHz\r
+ * @arg @ref RCC_MSIRANGE_4 MSI clock is around 1.048 MHz\r
+ * @arg @ref RCC_MSIRANGE_5 MSI clock is around 2.097 MHz (default after Reset or wake-up from STANDBY)\r
+ * @arg @ref RCC_MSIRANGE_6 MSI clock is around 4.194 MHz\r
+ */\r
+#define __HAL_RCC_GET_MSI_RANGE() (uint32_t)(READ_BIT(RCC->ICSCR, RCC_ICSCR_MSIRANGE))\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup RCC_PLL_Configuration PLL Configuration\r
+ * @{\r
+ */\r
+\r
+/** @brief Macro to enable the main PLL.\r
+ * @note After enabling the main PLL, the application software should wait on\r
+ * PLLRDY flag to be set indicating that PLL clock is stable and can\r
+ * be used as system clock source.\r
+ * @note The main PLL is disabled by hardware when entering STOP and STANDBY modes.\r
+ */\r
+#define __HAL_RCC_PLL_ENABLE() (*(__IO uint32_t *) RCC_CR_PLLON_BB = ENABLE)\r
+\r
+/** @brief Macro to disable the main PLL.\r
+ * @note The main PLL can not be disabled if it is used as system clock source\r
+ */\r
+#define __HAL_RCC_PLL_DISABLE() (*(__IO uint32_t *) RCC_CR_PLLON_BB = DISABLE)\r
+\r
+/** @brief Macro to configure the main PLL clock source, multiplication and division factors.\r
+ * @note This function must be used only when the main PLL is disabled.\r
+ *\r
+ * @param __RCC_PLLSOURCE__ specifies the PLL entry clock source.\r
+ * This parameter can be one of the following values:\r
+ * @arg @ref RCC_PLLSOURCE_HSI HSI oscillator clock selected as PLL clock entry\r
+ * @arg @ref RCC_PLLSOURCE_HSE HSE oscillator clock selected as PLL clock entry\r
+ * @param __PLLMUL__ specifies the multiplication factor for PLL VCO output clock\r
+ * This parameter can be one of the following values:\r
+ * @arg @ref RCC_PLL_MUL3 PLLVCO = PLL clock entry x 3\r
+ * @arg @ref RCC_PLL_MUL4 PLLVCO = PLL clock entry x 4\r
+ * @arg @ref RCC_PLL_MUL6 PLLVCO = PLL clock entry x 6\r
+ * @arg @ref RCC_PLL_MUL8 PLLVCO = PLL clock entry x 8\r
+ * @arg @ref RCC_PLL_MUL12 PLLVCO = PLL clock entry x 12\r
+ * @arg @ref RCC_PLL_MUL16 PLLVCO = PLL clock entry x 16\r
+ * @arg @ref RCC_PLL_MUL24 PLLVCO = PLL clock entry x 24\r
+ * @arg @ref RCC_PLL_MUL32 PLLVCO = PLL clock entry x 32\r
+ * @arg @ref RCC_PLL_MUL48 PLLVCO = PLL clock entry x 48\r
+ * @note The PLL VCO clock frequency must not exceed 96 MHz when the product is in\r
+ * Range 1, 48 MHz when the product is in Range 2 and 24 MHz when the product is\r
+ * in Range 3.\r
+ *\r
+ * @param __PLLDIV__ specifies the division factor for PLL VCO input clock\r
+ * This parameter can be one of the following values:\r
+ * @arg @ref RCC_PLL_DIV2 PLL clock output = PLLVCO / 2\r
+ * @arg @ref RCC_PLL_DIV3 PLL clock output = PLLVCO / 3\r
+ * @arg @ref RCC_PLL_DIV4 PLL clock output = PLLVCO / 4\r
+ *\r
+ */\r
+#define __HAL_RCC_PLL_CONFIG(__RCC_PLLSOURCE__, __PLLMUL__, __PLLDIV__)\\r
+ MODIFY_REG(RCC->CFGR, (RCC_CFGR_PLLSRC|RCC_CFGR_PLLMUL|RCC_CFGR_PLLDIV),((__RCC_PLLSOURCE__) | (__PLLMUL__) | (__PLLDIV__)))\r
+\r
+/** @brief Get oscillator clock selected as PLL input clock\r
+ * @retval The clock source used for PLL entry. The returned value can be one\r
+ * of the following:\r
+ * @arg @ref RCC_PLLSOURCE_HSI HSI oscillator clock selected as PLL input clock\r
+ * @arg @ref RCC_PLLSOURCE_HSE HSE oscillator clock selected as PLL input clock\r
+ */\r
+#define __HAL_RCC_GET_PLL_OSCSOURCE() ((uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_PLLSRC)))\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup RCC_Get_Clock_source Get Clock source\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @brief Macro to configure the system clock source.\r
+ * @param __SYSCLKSOURCE__ specifies the system clock source.\r
+ * This parameter can be one of the following values:\r
+ * @arg @ref RCC_SYSCLKSOURCE_MSI MSI oscillator is used as system clock source.\r
+ * @arg @ref RCC_SYSCLKSOURCE_HSI HSI oscillator is used as system clock source.\r
+ * @arg @ref RCC_SYSCLKSOURCE_HSE HSE oscillator is used as system clock source.\r
+ * @arg @ref RCC_SYSCLKSOURCE_PLLCLK PLL output is used as system clock source.\r
+ */\r
+#define __HAL_RCC_SYSCLK_CONFIG(__SYSCLKSOURCE__) \\r
+ MODIFY_REG(RCC->CFGR, RCC_CFGR_SW, (__SYSCLKSOURCE__))\r
+\r
+/** @brief Macro to get the clock source used as system clock.\r
+ * @retval The clock source used as system clock. The returned value can be one\r
+ * of the following:\r
+ * @arg @ref RCC_SYSCLKSOURCE_STATUS_MSI MSI used as system clock\r
+ * @arg @ref RCC_SYSCLKSOURCE_STATUS_HSI HSI used as system clock\r
+ * @arg @ref RCC_SYSCLKSOURCE_STATUS_HSE HSE used as system clock\r
+ * @arg @ref RCC_SYSCLKSOURCE_STATUS_PLLCLK PLL used as system clock\r
+ */\r
+#define __HAL_RCC_GET_SYSCLK_SOURCE() ((uint32_t)(READ_BIT(RCC->CFGR,RCC_CFGR_SWS)))\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup RCCEx_MCOx_Clock_Config RCC Extended MCOx Clock Config\r
+ * @{\r
+ */\r
+\r
+/** @brief Macro to configure the MCO clock.\r
+ * @param __MCOCLKSOURCE__ specifies the MCO clock source.\r
+ * This parameter can be one of the following values:\r
+ * @arg @ref RCC_MCO1SOURCE_NOCLOCK No clock selected as MCO clock\r
+ * @arg @ref RCC_MCO1SOURCE_SYSCLK System Clock selected as MCO clock\r
+ * @arg @ref RCC_MCO1SOURCE_HSI HSI oscillator clock selected as MCO clock\r
+ * @arg @ref RCC_MCO1SOURCE_MSI MSI oscillator clock selected as MCO clock\r
+ * @arg @ref RCC_MCO1SOURCE_HSE HSE oscillator clock selected as MCO clock\r
+ * @arg @ref RCC_MCO1SOURCE_PLLCLK PLL clock selected as MCO clock\r
+ * @arg @ref RCC_MCO1SOURCE_LSI LSI clock selected as MCO clock\r
+ * @arg @ref RCC_MCO1SOURCE_LSE LSE clock selected as MCO clock\r
+ * @param __MCODIV__ specifies the MCO clock prescaler.\r
+ * This parameter can be one of the following values:\r
+ * @arg @ref RCC_MCODIV_1 MCO clock source is divided by 1\r
+ * @arg @ref RCC_MCODIV_2 MCO clock source is divided by 2\r
+ * @arg @ref RCC_MCODIV_4 MCO clock source is divided by 4\r
+ * @arg @ref RCC_MCODIV_8 MCO clock source is divided by 8\r
+ * @arg @ref RCC_MCODIV_16 MCO clock source is divided by 16\r
+ */\r
+#define __HAL_RCC_MCO1_CONFIG(__MCOCLKSOURCE__, __MCODIV__) \\r
+ MODIFY_REG(RCC->CFGR, (RCC_CFGR_MCOSEL | RCC_CFGR_MCOPRE), ((__MCOCLKSOURCE__) | (__MCODIV__)))\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+ /** @defgroup RCC_RTC_Clock_Configuration RCC RTC Clock Configuration\r
+ * @{\r
+ */\r
+\r
+/** @brief Macro to configure the RTC clock (RTCCLK).\r
+ * @note As the RTC clock configuration bits are in the Backup domain and write\r
+ * access is denied to this domain after reset, you have to enable write\r
+ * access using the Power Backup Access macro before to configure\r
+ * the RTC clock source (to be done once after reset).\r
+ * @note Once the RTC clock is configured it cannot be changed unless the\r
+ * Backup domain is reset using @ref __HAL_RCC_BACKUPRESET_FORCE() macro, or by\r
+ * a Power On Reset (POR).\r
+ * @note RTC prescaler cannot be modified if HSE is enabled (HSEON = 1).\r
+ *\r
+ * @param __RTC_CLKSOURCE__ specifies the RTC clock source.\r
+ * This parameter can be one of the following values:\r
+ * @arg @ref RCC_RTCCLKSOURCE_NO_CLK No clock selected as RTC clock\r
+ * @arg @ref RCC_RTCCLKSOURCE_LSE LSE selected as RTC clock\r
+ * @arg @ref RCC_RTCCLKSOURCE_LSI LSI selected as RTC clock\r
+ * @arg @ref RCC_RTCCLKSOURCE_HSE_DIV2 HSE divided by 2 selected as RTC clock\r
+ * @arg @ref RCC_RTCCLKSOURCE_HSE_DIV4 HSE divided by 4 selected as RTC clock\r
+ * @arg @ref RCC_RTCCLKSOURCE_HSE_DIV8 HSE divided by 8 selected as RTC clock\r
+ * @arg @ref RCC_RTCCLKSOURCE_HSE_DIV16 HSE divided by 16 selected as RTC clock\r
+ * @note If the LSE or LSI is used as RTC clock source, the RTC continues to\r
+ * work in STOP and STANDBY modes, and can be used as wakeup source.\r
+ * However, when the HSE clock is used as RTC clock source, the RTC\r
+ * cannot be used in STOP and STANDBY modes.\r
+ * @note The maximum input clock frequency for RTC is 1MHz (when using HSE as\r
+ * RTC clock source).\r
+ */\r
+#define __HAL_RCC_RTC_CLKPRESCALER(__RTC_CLKSOURCE__) do { \\r
+ if(((__RTC_CLKSOURCE__) & RCC_CSR_RTCSEL_HSE) == RCC_CSR_RTCSEL_HSE) \\r
+ { \\r
+ MODIFY_REG(RCC->CR, RCC_CR_RTCPRE, ((__RTC_CLKSOURCE__) & RCC_CR_RTCPRE)); \\r
+ } \\r
+ } while (0U)\r
+\r
+#define __HAL_RCC_RTC_CONFIG(__RTC_CLKSOURCE__) do { \\r
+ __HAL_RCC_RTC_CLKPRESCALER(__RTC_CLKSOURCE__); \\r
+ RCC->CSR |= ((__RTC_CLKSOURCE__) & RCC_CSR_RTCSEL); \\r
+ } while (0U)\r
+\r
+/** @brief Macro to get the RTC clock source.\r
+ * @retval The clock source can be one of the following values:\r
+ * @arg @ref RCC_RTCCLKSOURCE_NO_CLK No clock selected as RTC clock\r
+ * @arg @ref RCC_RTCCLKSOURCE_LSE LSE selected as RTC clock\r
+ * @arg @ref RCC_RTCCLKSOURCE_LSI LSI selected as RTC clock\r
+ * @arg @ref RCC_RTCCLKSOURCE_HSE_DIVX HSE divided by X selected as RTC clock (X can be retrieved thanks to @ref __HAL_RCC_GET_RTC_HSE_PRESCALER()\r
+ */\r
+#define __HAL_RCC_GET_RTC_SOURCE() (READ_BIT(RCC->CSR, RCC_CSR_RTCSEL))\r
+\r
+/**\r
+ * @brief Get the RTC and LCD HSE clock divider (RTCCLK / LCDCLK).\r
+ *\r
+ * @retval Returned value can be one of the following values:\r
+ * @arg @ref RCC_RTC_HSE_DIV_2 HSE divided by 2 selected as RTC clock\r
+ * @arg @ref RCC_RTC_HSE_DIV_4 HSE divided by 4 selected as RTC clock\r
+ * @arg @ref RCC_RTC_HSE_DIV_8 HSE divided by 8 selected as RTC clock\r
+ * @arg @ref RCC_RTC_HSE_DIV_16 HSE divided by 16 selected as RTC clock\r
+ *\r
+ */\r
+#define __HAL_RCC_GET_RTC_HSE_PRESCALER() ((uint32_t)(READ_BIT(RCC->CR, RCC_CR_RTCPRE)))\r
+\r
+/** @brief Macro to enable the the RTC clock.\r
+ * @note These macros must be used only after the RTC clock source was selected.\r
+ */\r
+#define __HAL_RCC_RTC_ENABLE() (*(__IO uint32_t *) RCC_CSR_RTCEN_BB = ENABLE)\r
+\r
+/** @brief Macro to disable the the RTC clock.\r
+ * @note These macros must be used only after the RTC clock source was selected.\r
+ */\r
+#define __HAL_RCC_RTC_DISABLE() (*(__IO uint32_t *) RCC_CSR_RTCEN_BB = DISABLE)\r
+\r
+/** @brief Macro to force the Backup domain reset.\r
+ * @note This function resets the RTC peripheral (including the backup registers)\r
+ * and the RTC clock source selection in RCC_CSR register.\r
+ * @note The BKPSRAM is not affected by this reset.\r
+ */\r
+#define __HAL_RCC_BACKUPRESET_FORCE() (*(__IO uint32_t *) RCC_CSR_RTCRST_BB = ENABLE)\r
+\r
+/** @brief Macros to release the Backup domain reset.\r
+ */\r
+#define __HAL_RCC_BACKUPRESET_RELEASE() (*(__IO uint32_t *) RCC_CSR_RTCRST_BB = DISABLE)\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup RCC_Flags_Interrupts_Management Flags Interrupts Management\r
+ * @brief macros to manage the specified RCC Flags and interrupts.\r
+ * @{\r
+ */\r
+\r
+/** @brief Enable RCC interrupt.\r
+ * @param __INTERRUPT__ specifies the RCC interrupt sources to be enabled.\r
+ * This parameter can be any combination of the following values:\r
+ * @arg @ref RCC_IT_LSIRDY LSI ready interrupt\r
+ * @arg @ref RCC_IT_LSERDY LSE ready interrupt\r
+ * @arg @ref RCC_IT_HSIRDY HSI ready interrupt\r
+ * @arg @ref RCC_IT_HSERDY HSE ready interrupt\r
+ * @arg @ref RCC_IT_PLLRDY main PLL ready interrupt\r
+ * @arg @ref RCC_IT_MSIRDY MSI ready interrupt\r
+ * @arg @ref RCC_IT_LSECSS LSE CSS interrupt (not available for STM32L100xB || STM32L151xB || STM32L152xB devices)\r
+ */\r
+#define __HAL_RCC_ENABLE_IT(__INTERRUPT__) (*(__IO uint8_t *) RCC_CIR_BYTE1_ADDRESS |= (__INTERRUPT__))\r
+\r
+/** @brief Disable RCC interrupt.\r
+ * @param __INTERRUPT__ specifies the RCC interrupt sources to be disabled.\r
+ * This parameter can be any combination of the following values:\r
+ * @arg @ref RCC_IT_LSIRDY LSI ready interrupt\r
+ * @arg @ref RCC_IT_LSERDY LSE ready interrupt\r
+ * @arg @ref RCC_IT_HSIRDY HSI ready interrupt\r
+ * @arg @ref RCC_IT_HSERDY HSE ready interrupt\r
+ * @arg @ref RCC_IT_PLLRDY main PLL ready interrupt\r
+ * @arg @ref RCC_IT_MSIRDY MSI ready interrupt\r
+ * @arg @ref RCC_IT_LSECSS LSE CSS interrupt (not available for STM32L100xB || STM32L151xB || STM32L152xB devices)\r
+ */\r
+#define __HAL_RCC_DISABLE_IT(__INTERRUPT__) (*(__IO uint8_t *) RCC_CIR_BYTE1_ADDRESS &= (uint8_t)(~(__INTERRUPT__)))\r
+\r
+/** @brief Clear the RCC's interrupt pending bits.\r
+ * @param __INTERRUPT__ specifies the interrupt pending bit to clear.\r
+ * This parameter can be any combination of the following values:\r
+ * @arg @ref RCC_IT_LSIRDY LSI ready interrupt.\r
+ * @arg @ref RCC_IT_LSERDY LSE ready interrupt.\r
+ * @arg @ref RCC_IT_HSIRDY HSI ready interrupt.\r
+ * @arg @ref RCC_IT_HSERDY HSE ready interrupt.\r
+ * @arg @ref RCC_IT_PLLRDY Main PLL ready interrupt.\r
+ * @arg @ref RCC_IT_MSIRDY MSI ready interrupt\r
+ * @arg @ref RCC_IT_LSECSS LSE CSS interrupt (not available for STM32L100xB || STM32L151xB || STM32L152xB devices)\r
+ * @arg @ref RCC_IT_CSS Clock Security System interrupt\r
+ */\r
+#define __HAL_RCC_CLEAR_IT(__INTERRUPT__) (*(__IO uint8_t *) RCC_CIR_BYTE2_ADDRESS = (__INTERRUPT__))\r
+\r
+/** @brief Check the RCC's interrupt has occurred or not.\r
+ * @param __INTERRUPT__ specifies the RCC interrupt source to check.\r
+ * This parameter can be one of the following values:\r
+ * @arg @ref RCC_IT_LSIRDY LSI ready interrupt.\r
+ * @arg @ref RCC_IT_LSERDY LSE ready interrupt.\r
+ * @arg @ref RCC_IT_HSIRDY HSI ready interrupt.\r
+ * @arg @ref RCC_IT_HSERDY HSE ready interrupt.\r
+ * @arg @ref RCC_IT_PLLRDY Main PLL ready interrupt.\r
+ * @arg @ref RCC_IT_MSIRDY MSI ready interrupt\r
+ * @arg @ref RCC_IT_LSECSS LSE CSS interrupt (not available for STM32L100xB || STM32L151xB || STM32L152xB devices)\r
+ * @arg @ref RCC_IT_CSS Clock Security System interrupt\r
+ * @retval The new state of __INTERRUPT__ (TRUE or FALSE).\r
+ */\r
+#define __HAL_RCC_GET_IT(__INTERRUPT__) ((RCC->CIR & (__INTERRUPT__)) == (__INTERRUPT__))\r
+\r
+/** @brief Set RMVF bit to clear the reset flags.\r
+ * The reset flags are RCC_FLAG_PINRST, RCC_FLAG_PORRST, RCC_FLAG_SFTRST,\r
+ * RCC_FLAG_IWDGRST, RCC_FLAG_WWDGRST, RCC_FLAG_LPWRRST\r
+ */\r
+#define __HAL_RCC_CLEAR_RESET_FLAGS() (RCC->CSR |= RCC_CSR_RMVF)\r
+\r
+/** @brief Check RCC flag is set or not.\r
+ * @param __FLAG__ specifies the flag to check.\r
+ * This parameter can be one of the following values:\r
+ * @arg @ref RCC_FLAG_HSIRDY HSI oscillator clock ready.\r
+ * @arg @ref RCC_FLAG_MSIRDY MSI oscillator clock ready.\r
+ * @arg @ref RCC_FLAG_HSERDY HSE oscillator clock ready.\r
+ * @arg @ref RCC_FLAG_PLLRDY Main PLL clock ready.\r
+ * @arg @ref RCC_FLAG_LSERDY LSE oscillator clock ready.\r
+ * @arg @ref RCC_FLAG_LSECSS CSS on LSE failure Detection (*)\r
+ * @arg @ref RCC_FLAG_LSIRDY LSI oscillator clock ready.\r
+ * @arg @ref RCC_FLAG_OBLRST Option Byte Load reset\r
+ * @arg @ref RCC_FLAG_PINRST Pin reset.\r
+ * @arg @ref RCC_FLAG_PORRST POR/PDR reset.\r
+ * @arg @ref RCC_FLAG_SFTRST Software reset.\r
+ * @arg @ref RCC_FLAG_IWDGRST Independent Watchdog reset.\r
+ * @arg @ref RCC_FLAG_WWDGRST Window Watchdog reset.\r
+ * @arg @ref RCC_FLAG_LPWRRST Low Power reset.\r
+ * @note (*) This bit is available in high and medium+ density devices only.\r
+ * @retval The new state of __FLAG__ (TRUE or FALSE).\r
+ */\r
+#define __HAL_RCC_GET_FLAG(__FLAG__) (((((__FLAG__) >> 5U) == CR_REG_INDEX)? RCC->CR :RCC->CSR) & (1U << ((__FLAG__) & RCC_FLAG_MASK)))\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/* Include RCC HAL Extension module */\r
+#include "stm32l1xx_hal_rcc_ex.h"\r
+\r
+/* Exported functions --------------------------------------------------------*/\r
+/** @addtogroup RCC_Exported_Functions\r
+ * @{\r
+ */\r
+\r
+/** @addtogroup RCC_Exported_Functions_Group1\r
+ * @{\r
+ */\r
+\r
+/* Initialization and de-initialization functions ******************************/\r
+HAL_StatusTypeDef HAL_RCC_DeInit(void);\r
+HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct);\r
+HAL_StatusTypeDef HAL_RCC_ClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, uint32_t FLatency);\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @addtogroup RCC_Exported_Functions_Group2\r
+ * @{\r
+ */\r
+\r
+/* Peripheral Control functions ************************************************/\r
+void HAL_RCC_MCOConfig(uint32_t RCC_MCOx, uint32_t RCC_MCOSource, uint32_t RCC_MCODiv);\r
+void HAL_RCC_EnableCSS(void);\r
+/* CSS NMI IRQ handler */\r
+void HAL_RCC_NMI_IRQHandler(void);\r
+/* User Callbacks in non blocking mode (IT mode) */\r
+void HAL_RCC_CSSCallback(void);\r
+void HAL_RCC_DisableCSS(void);\r
+uint32_t HAL_RCC_GetSysClockFreq(void);\r
+uint32_t HAL_RCC_GetHCLKFreq(void);\r
+uint32_t HAL_RCC_GetPCLK1Freq(void);\r
+uint32_t HAL_RCC_GetPCLK2Freq(void);\r
+void HAL_RCC_GetOscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct);\r
+void HAL_RCC_GetClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, uint32_t *pFLatency);\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+#ifdef __cplusplus\r
+}\r
+#endif\r
+\r
+#endif /* __STM32L1xx_HAL_RCC_H */\r
+\r
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\r
+\r
--- /dev/null
+/**\r
+ ******************************************************************************\r
+ * @file stm32l1xx_hal_rcc_ex.h\r
+ * @author MCD Application Team\r
+ * @brief Header file of RCC HAL Extension module.\r
+ ******************************************************************************\r
+ * @attention\r
+ *\r
+ * <h2><center>© Copyright(c) 2017 STMicroelectronics.\r
+ * All rights reserved.</center></h2>\r
+ *\r
+ * This software component is licensed by ST under BSD 3-Clause license,\r
+ * the "License"; You may not use this file except in compliance with the\r
+ * License. You may obtain a copy of the License at:\r
+ * opensource.org/licenses/BSD-3-Clause\r
+ *\r
+ ******************************************************************************\r
+ */\r
+\r
+/* Define to prevent recursive inclusion -------------------------------------*/\r
+#ifndef __STM32L1xx_HAL_RCC_EX_H\r
+#define __STM32L1xx_HAL_RCC_EX_H\r
+\r
+#ifdef __cplusplus\r
+ extern "C" {\r
+#endif\r
+\r
+/* Includes ------------------------------------------------------------------*/\r
+#include "stm32l1xx_hal_def.h"\r
+\r
+/** @addtogroup STM32L1xx_HAL_Driver\r
+ * @{\r
+ */\r
+\r
+/** @addtogroup RCCEx\r
+ * @{\r
+ */\r
+\r
+/** @addtogroup RCCEx_Private_Constants\r
+ * @{\r
+ */\r
+\r
+#if defined(STM32L100xBA) || defined(STM32L151xBA) || defined(STM32L152xBA)\\r
+ || defined(STM32L100xC) || defined(STM32L151xC) || defined(STM32L152xC)\\r
+ || defined(STM32L162xC) || defined(STM32L151xCA) || defined(STM32L151xD)\\r
+ || defined(STM32L152xCA) || defined(STM32L152xD) || defined(STM32L162xCA)\\r
+ || defined(STM32L162xD) || defined(STM32L151xE) || defined(STM32L151xDX)\\r
+ || defined(STM32L152xE) || defined(STM32L152xDX) || defined(STM32L162xE) || defined(STM32L162xDX)\r
+\r
+/* Alias word address of LSECSSON bit */\r
+#define LSECSSON_BITNUMBER RCC_CSR_LSECSSON_Pos\r
+#define CSR_LSECSSON_BB ((uint32_t)(PERIPH_BB_BASE + (RCC_CSR_OFFSET_BB * 32U) + (LSECSSON_BITNUMBER * 4U)))\r
+\r
+#endif /* STM32L100xBA || STM32L151xBA || STM32L152xBA || STM32L100xC || STM32L151xC || STM32L152xC || STM32L162xC || STM32L151xCA || STM32L151xD || STM32L152xCA || STM32L152xD || STM32L162xCA || STM32L162xD || STM32L151xE || STM32L151xDX || STM32L152xE || STM32L152xDX || STM32L162xE || STM32L162xDX*/\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @addtogroup RCCEx_Private_Macros\r
+ * @{\r
+ */\r
+#if defined(LCD)\r
+\r
+#define IS_RCC_PERIPHCLOCK(__CLK__) ((RCC_PERIPHCLK_RTC <= (__CLK__)) && ((__CLK__) <= RCC_PERIPHCLK_LCD))\r
+\r
+#else /* Not LCD LINE */\r
+\r
+#define IS_RCC_PERIPHCLOCK(__CLK__) ((__CLK__) == RCC_PERIPHCLK_RTC)\r
+\r
+#endif /* LCD */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/* Exported types ------------------------------------------------------------*/\r
+\r
+/** @defgroup RCCEx_Exported_Types RCCEx Exported Types\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @brief RCC extended clocks structure definition\r
+ */\r
+typedef struct\r
+{\r
+ uint32_t PeriphClockSelection; /*!< The Extended Clock to be configured.\r
+ This parameter can be a value of @ref RCCEx_Periph_Clock_Selection */\r
+\r
+ uint32_t RTCClockSelection; /*!< specifies the RTC clock source.\r
+ This parameter can be a value of @ref RCC_RTC_LCD_Clock_Source */\r
+\r
+#if defined(LCD)\r
+\r
+ uint32_t LCDClockSelection; /*!< specifies the LCD clock source.\r
+ This parameter can be a value of @ref RCC_RTC_LCD_Clock_Source */\r
+\r
+#endif /* LCD */\r
+} RCC_PeriphCLKInitTypeDef;\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/* Exported constants --------------------------------------------------------*/\r
+\r
+/** @defgroup RCCEx_Exported_Constants RCCEx Exported Constants\r
+ * @{\r
+ */\r
+\r
+/** @defgroup RCCEx_Periph_Clock_Selection RCCEx Periph Clock Selection\r
+ * @{\r
+ */\r
+#define RCC_PERIPHCLK_RTC (0x00000001U)\r
+\r
+#if defined(LCD)\r
+\r
+#define RCC_PERIPHCLK_LCD (0x00000002U)\r
+\r
+#endif /* LCD */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+#if defined(RCC_LSECSS_SUPPORT)\r
+/** @defgroup RCCEx_EXTI_LINE_LSECSS RCC LSE CSS external interrupt line\r
+ * @{\r
+ */\r
+#define RCC_EXTI_LINE_LSECSS (EXTI_IMR_IM19) /*!< External interrupt line 19 connected to the LSE CSS EXTI Line */\r
+/**\r
+ * @}\r
+ */\r
+#endif /* RCC_LSECSS_SUPPORT */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/* Exported macro ------------------------------------------------------------*/\r
+/** @defgroup RCCEx_Exported_Macros RCCEx Exported Macros\r
+ * @{\r
+ */\r
+\r
+/** @defgroup RCCEx_Peripheral_Clock_Enable_Disable RCCEx_Peripheral_Clock_Enable_Disable\r
+ * @brief Enables or disables the AHB1 peripheral clock.\r
+ * @note After reset, the peripheral clock (used for registers read/write access)\r
+ * is disabled and the application software has to enable this clock before\r
+ * using it.\r
+ * @{\r
+ */\r
+#if defined(STM32L151xB) || defined(STM32L152xB) || defined(STM32L151xBA)\\r
+ || defined(STM32L152xBA) || defined(STM32L151xC) || defined(STM32L152xC)\\r
+ || defined(STM32L162xC) || defined(STM32L151xCA) || defined(STM32L151xD)\\r
+ || defined(STM32L152xCA) || defined(STM32L152xD) || defined(STM32L162xCA)\\r
+ || defined(STM32L162xD) || defined(STM32L151xE) || defined(STM32L151xDX) || defined(STM32L152xE) || defined(STM32L152xDX)\\r
+ || defined(STM32L162xE) || defined(STM32L162xDX)\r
+\r
+#define __HAL_RCC_GPIOE_CLK_ENABLE() do { \\r
+ __IO uint32_t tmpreg; \\r
+ SET_BIT(RCC->AHBENR, RCC_AHBENR_GPIOEEN);\\r
+ /* Delay after an RCC peripheral clock enabling */ \\r
+ tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_GPIOEEN);\\r
+ UNUSED(tmpreg); \\r
+ } while(0U)\r
+#define __HAL_RCC_GPIOE_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_GPIOEEN))\r
+\r
+#endif /* STM32L151xB || STM32L152xB || ... || STM32L151xCA || STM32L151xD || STM32L152xCA || STM32L152xD || STM32L162xCA || STM32L162xD || STM32L151xE || STM32L151xDX || STM32L152xE || STM32L152xDX || STM32L162xE || STM32L162xDX */\r
+\r
+#if defined(STM32L151xCA) || defined(STM32L151xD) || defined(STM32L152xCA)\\r
+ || defined(STM32L152xD) || defined(STM32L162xCA) || defined(STM32L162xD)\\r
+ || defined(STM32L151xE) || defined(STM32L151xDX) || defined(STM32L152xE) || defined(STM32L152xDX) || defined(STM32L162xE) || defined(STM32L162xDX)\r
+\r
+#define __HAL_RCC_GPIOF_CLK_ENABLE() do { \\r
+ __IO uint32_t tmpreg; \\r
+ SET_BIT(RCC->AHBENR, RCC_AHBENR_GPIOFEN);\\r
+ /* Delay after an RCC peripheral clock enabling */ \\r
+ tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_GPIOFEN);\\r
+ UNUSED(tmpreg); \\r
+ } while(0U)\r
+#define __HAL_RCC_GPIOG_CLK_ENABLE() do { \\r
+ __IO uint32_t tmpreg; \\r
+ SET_BIT(RCC->AHBENR, RCC_AHBENR_GPIOGEN);\\r
+ /* Delay after an RCC peripheral clock enabling */ \\r
+ tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_GPIOGEN);\\r
+ UNUSED(tmpreg); \\r
+ } while(0U)\r
+\r
+#define __HAL_RCC_GPIOF_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_GPIOFEN))\r
+#define __HAL_RCC_GPIOG_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_GPIOGEN))\r
+\r
+#endif /* STM32L151xCA || STM32L151xD || STM32L152xCA || STM32L152xD || STM32L162xCA || STM32L162xD || STM32L151xE || STM32L151xDX || STM32L152xE || STM32L152xDX || STM32L162xE || STM32L162xDX */\r
+\r
+#if defined(STM32L100xC) || defined(STM32L151xC) || defined(STM32L152xC)\\r
+ || defined(STM32L162xC) || defined(STM32L151xCA) || defined(STM32L151xD)\\r
+ || defined(STM32L152xCA) || defined(STM32L152xD) || defined(STM32L162xCA)\\r
+ || defined(STM32L162xD) || defined(STM32L151xE) || defined(STM32L151xDX) || defined(STM32L152xE) || defined(STM32L152xDX)\\r
+ || defined(STM32L162xE) || defined(STM32L162xDX)\r
+\r
+#define __HAL_RCC_DMA2_CLK_ENABLE() do { \\r
+ __IO uint32_t tmpreg; \\r
+ SET_BIT(RCC->AHBENR, RCC_AHBENR_DMA2EN);\\r
+ /* Delay after an RCC peripheral clock enabling */ \\r
+ tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_DMA2EN);\\r
+ UNUSED(tmpreg); \\r
+ } while(0U)\r
+\r
+#define __HAL_RCC_DMA2_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_DMA2EN))\r
+\r
+#endif /* STM32L100xC || STM32L151xC || STM32L152xC || STM32L162xC || STM32L151xCA || STM32L151xD || STM32L152xCA || STM32L152xD || STM32L162xCA || STM32L162xD || STM32L151xE || STM32L151xDX || STM32L152xE || STM32L152xDX || STM32L162xE || STM32L162xDX */\r
+\r
+#if defined(STM32L162xC) || defined(STM32L162xCA) || defined(STM32L162xD)\\r
+ || defined(STM32L162xE) || defined(STM32L162xDX)\r
+\r
+#define __HAL_RCC_AES_CLK_ENABLE() do { \\r
+ __IO uint32_t tmpreg; \\r
+ SET_BIT(RCC->AHBENR, RCC_AHBENR_AESEN);\\r
+ /* Delay after an RCC peripheral clock enabling */ \\r
+ tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_AESEN);\\r
+ UNUSED(tmpreg); \\r
+ } while(0U)\r
+#define __HAL_RCC_AES_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_AESEN))\r
+\r
+#endif /* STM32L162xC || STM32L162xCA || STM32L162xD || STM32L162xE || STM32L162xDX */\r
+\r
+#if defined(STM32L151xD) || defined(STM32L152xD) || defined(STM32L162xD)\r
+\r
+#define __HAL_RCC_FSMC_CLK_ENABLE() do { \\r
+ __IO uint32_t tmpreg; \\r
+ SET_BIT(RCC->AHBENR, RCC_AHBENR_FSMCEN);\\r
+ /* Delay after an RCC peripheral clock enabling */ \\r
+ tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_FSMCEN);\\r
+ UNUSED(tmpreg); \\r
+ } while(0U)\r
+#define __HAL_RCC_FSMC_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_FSMCEN))\r
+\r
+#endif /* STM32L151xD || STM32L152xD || STM32L162xD */\r
+\r
+#if defined(STM32L100xB) || defined(STM32L100xBA) || defined(STM32L100xC)\\r
+ || defined(STM32L152xB) || defined(STM32L152xBA) || defined(STM32L152xC)\\r
+ || defined(STM32L162xC) || defined(STM32L152xCA) || defined(STM32L152xD)\\r
+ || defined(STM32L162xCA) || defined(STM32L162xD) || defined(STM32L152xE) || defined(STM32L152xDX)\\r
+ || defined(STM32L162xE) || defined(STM32L162xDX)\r
+\r
+#define __HAL_RCC_LCD_CLK_ENABLE() do { \\r
+ __IO uint32_t tmpreg; \\r
+ SET_BIT(RCC->APB1ENR, RCC_APB1ENR_LCDEN);\\r
+ /* Delay after an RCC peripheral clock enabling */ \\r
+ tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_LCDEN);\\r
+ UNUSED(tmpreg); \\r
+ } while(0U)\r
+#define __HAL_RCC_LCD_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_LCDEN))\r
+\r
+#endif /* STM32L100xB || STM32L152xBA || ... || STM32L152xE || STM32L152xDX || STM32L162xE || STM32L162xDX */\r
+\r
+/** @brief Enables or disables the Low Speed APB (APB1) peripheral clock.\r
+ * @note After reset, the peripheral clock (used for registers read/write access)\r
+ * is disabled and the application software has to enable this clock before\r
+ * using it.\r
+ */\r
+#if defined(STM32L151xC) || defined(STM32L152xC) || defined(STM32L162xC)\\r
+ || defined(STM32L151xCA) || defined(STM32L151xD) || defined(STM32L152xCA)\\r
+ || defined(STM32L152xD) || defined(STM32L162xCA) || defined(STM32L162xD)\\r
+ || defined(STM32L151xE) || defined(STM32L151xDX) || defined(STM32L152xE) || defined(STM32L152xDX) || defined(STM32L162xE) || defined(STM32L162xDX)\r
+\r
+#define __HAL_RCC_TIM5_CLK_ENABLE() do { \\r
+ __IO uint32_t tmpreg; \\r
+ SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM5EN);\\r
+ /* Delay after an RCC peripheral clock enabling */ \\r
+ tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM5EN);\\r
+ UNUSED(tmpreg); \\r
+ } while(0U)\r
+#define __HAL_RCC_TIM5_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM5EN))\r
+\r
+#endif /* STM32L151xC || STM32L152xC || STM32L162xC || STM32L151xCA || STM32L151xD || STM32L152xCA || STM32L152xD || STM32L162xCA || STM32L162xD || STM32L151xE || STM32L151xDX || STM32L152xE || STM32L152xDX || STM32L162xE || STM32L162xDX */\r
+\r
+#if defined(STM32L100xC) || defined(STM32L151xC) || defined(STM32L152xC)\\r
+ || defined(STM32L162xC) || defined(STM32L151xCA) || defined(STM32L151xD)\\r
+ || defined(STM32L152xCA) || defined(STM32L152xD) || defined(STM32L162xCA)\\r
+ || defined(STM32L162xD) || defined(STM32L151xE) || defined(STM32L151xDX) || defined(STM32L152xE) || defined(STM32L152xDX)\\r
+ || defined(STM32L162xE) || defined(STM32L162xDX)\r
+\r
+#define __HAL_RCC_SPI3_CLK_ENABLE() do { \\r
+ __IO uint32_t tmpreg; \\r
+ SET_BIT(RCC->APB1ENR, RCC_APB1ENR_SPI3EN);\\r
+ /* Delay after an RCC peripheral clock enabling */ \\r
+ tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_SPI3EN);\\r
+ UNUSED(tmpreg); \\r
+ } while(0U)\r
+#define __HAL_RCC_SPI3_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_SPI3EN))\r
+\r
+#endif /* STM32L100xC || STM32L151xC || STM32L152xC || STM32L162xC || STM32L151xCA || STM32L151xD || STM32L152xCA || STM32L152xD || STM32L162xCA || STM32L162xD || STM32L151xE || STM32L151xDX || STM32L152xE || STM32L152xDX || STM32L162xE || STM32L162xDX */\r
+\r
+#if defined(STM32L151xD) || defined(STM32L152xD) || defined(STM32L162xD)\\r
+ || defined(STM32L151xE) || defined(STM32L151xDX) || defined(STM32L152xE) || defined(STM32L152xDX) || defined(STM32L162xE) || defined(STM32L162xDX)\r
+\r
+#define __HAL_RCC_UART4_CLK_ENABLE() do { \\r
+ __IO uint32_t tmpreg; \\r
+ SET_BIT(RCC->APB1ENR, RCC_APB1ENR_UART4EN);\\r
+ /* Delay after an RCC peripheral clock enabling */ \\r
+ tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_UART4EN);\\r
+ UNUSED(tmpreg); \\r
+ } while(0U)\r
+#define __HAL_RCC_UART5_CLK_ENABLE() do { \\r
+ __IO uint32_t tmpreg; \\r
+ SET_BIT(RCC->APB1ENR, RCC_APB1ENR_UART5EN);\\r
+ /* Delay after an RCC peripheral clock enabling */ \\r
+ tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_UART5EN);\\r
+ UNUSED(tmpreg); \\r
+ } while(0U)\r
+\r
+#define __HAL_RCC_UART4_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_UART4EN))\r
+#define __HAL_RCC_UART5_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_UART5EN))\r
+\r
+#endif /* STM32L151xD || STM32L152xD || STM32L162xD || (...) || STM32L152xDX || STM32L162xE || STM32L162xDX */\r
+\r
+#if defined(STM32L151xCA) || defined(STM32L151xD) || defined(STM32L152xCA)\\r
+ || defined(STM32L152xD) || defined(STM32L162xCA) || defined(STM32L162xD)\\r
+ || defined(STM32L151xE) || defined(STM32L151xDX) || defined(STM32L152xE)\\r
+ || defined(STM32L152xDX) || defined(STM32L162xE) || defined(STM32L162xDX)\\r
+ || defined(STM32L162xC) || defined(STM32L152xC) || defined(STM32L151xC)\r
+\r
+#define __HAL_RCC_OPAMP_CLK_ENABLE() __HAL_RCC_COMP_CLK_ENABLE() /* Peripherals COMP and OPAMP share the same clock domain */\r
+#define __HAL_RCC_OPAMP_CLK_DISABLE() __HAL_RCC_COMP_CLK_DISABLE() /* Peripherals COMP and OPAMP share the same clock domain */\r
+\r
+#endif /* STM32L151xCA || STM32L151xD || STM32L152xCA || (...) || STM32L162xC || STM32L152xC || STM32L151xC */\r
+\r
+/** @brief Enables or disables the High Speed APB (APB2) peripheral clock.\r
+ * @note After reset, the peripheral clock (used for registers read/write access)\r
+ * is disabled and the application software has to enable this clock before\r
+ * using it.\r
+ */\r
+#if defined(STM32L151xD) || defined(STM32L152xD) || defined(STM32L162xD)\r
+\r
+#define __HAL_RCC_SDIO_CLK_ENABLE() do { \\r
+ __IO uint32_t tmpreg; \\r
+ SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SDIOEN);\\r
+ /* Delay after an RCC peripheral clock enabling */ \\r
+ tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SDIOEN);\\r
+ UNUSED(tmpreg); \\r
+ } while(0U)\r
+#define __HAL_RCC_SDIO_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SDIOEN))\r
+\r
+#endif /* STM32L151xD || STM32L152xD || STM32L162xD */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+\r
+/** @defgroup RCCEx_Force_Release_Peripheral_Reset RCCEx Force Release Peripheral Reset\r
+ * @brief Forces or releases AHB peripheral reset.\r
+ * @{\r
+ */\r
+#if defined(STM32L151xB) || defined(STM32L152xB) || defined(STM32L151xBA)\\r
+ || defined(STM32L152xBA) || defined(STM32L151xC) || defined(STM32L152xC)\\r
+ || defined(STM32L162xC) || defined(STM32L151xCA) || defined(STM32L151xD)\\r
+ || defined(STM32L152xCA) || defined(STM32L152xD) || defined(STM32L162xCA)\\r
+ || defined(STM32L162xD) || defined(STM32L151xE) || defined(STM32L151xDX) || defined(STM32L152xE) || defined(STM32L152xDX)\\r
+ || defined(STM32L162xE) || defined(STM32L162xDX)\r
+\r
+#define __HAL_RCC_GPIOE_FORCE_RESET() (RCC->AHBRSTR |= (RCC_AHBRSTR_GPIOERST))\r
+#define __HAL_RCC_GPIOE_RELEASE_RESET() (RCC->AHBRSTR &= ~(RCC_AHBRSTR_GPIOERST))\r
+\r
+#endif /* STM32L151xB || STM32L152xB || ... || STM32L151xCA || STM32L151xD || STM32L152xCA || STM32L152xD || STM32L162xCA || STM32L162xD || STM32L151xE || STM32L151xDX || STM32L152xE || STM32L152xDX || STM32L162xE || STM32L162xDX */\r
+\r
+#if defined(STM32L151xCA) || defined(STM32L151xD) || defined(STM32L152xCA)\\r
+ || defined(STM32L152xD) || defined(STM32L162xCA) || defined(STM32L162xD)\\r
+ || defined(STM32L151xE) || defined(STM32L151xDX) || defined(STM32L152xE) || defined(STM32L152xDX) || defined(STM32L162xE) || defined(STM32L162xDX)\r
+\r
+#define __HAL_RCC_GPIOF_FORCE_RESET() (RCC->AHBRSTR |= (RCC_AHBRSTR_GPIOFRST))\r
+#define __HAL_RCC_GPIOG_FORCE_RESET() (RCC->AHBRSTR |= (RCC_AHBRSTR_GPIOGRST))\r
+\r
+#define __HAL_RCC_GPIOF_RELEASE_RESET() (RCC->AHBRSTR &= ~(RCC_AHBRSTR_GPIOFRST))\r
+#define __HAL_RCC_GPIOG_RELEASE_RESET() (RCC->AHBRSTR &= ~(RCC_AHBRSTR_GPIOGRST))\r
+\r
+#endif /* STM32L151xCA || STM32L151xD || STM32L152xCA || STM32L152xD || STM32L162xCA || STM32L162xD || STM32L151xE || STM32L151xDX || STM32L152xE || STM32L152xDX || STM32L162xE || STM32L162xDX */\r
+\r
+#if defined(STM32L100xC) || defined(STM32L151xC) || defined(STM32L152xC)\\r
+ || defined(STM32L162xC) || defined(STM32L151xCA) || defined(STM32L151xD)\\r
+ || defined(STM32L152xCA) || defined(STM32L152xD) || defined(STM32L162xCA)\\r
+ || defined(STM32L162xD) || defined(STM32L151xE) || defined(STM32L151xDX) || defined(STM32L152xE) || defined(STM32L152xDX)\\r
+ || defined(STM32L162xE) || defined(STM32L162xDX)\r
+\r
+#define __HAL_RCC_DMA2_FORCE_RESET() (RCC->AHBRSTR |= (RCC_AHBRSTR_DMA2RST))\r
+#define __HAL_RCC_DMA2_RELEASE_RESET() (RCC->AHBRSTR &= ~(RCC_AHBRSTR_DMA2RST))\r
+\r
+#endif /* STM32L100xC || STM32L151xC || STM32L152xC || STM32L162xC || STM32L151xCA || STM32L151xD || STM32L152xCA || STM32L152xD || STM32L162xCA || STM32L162xD || STM32L151xE || STM32L151xDX || STM32L152xE || STM32L152xDX || STM32L162xE || STM32L162xDX */\r
+\r
+#if defined(STM32L162xC) || defined(STM32L162xCA) || defined(STM32L162xD)\\r
+ || defined(STM32L162xE) || defined(STM32L162xDX)\r
+\r
+#define __HAL_RCC_AES_FORCE_RESET() (RCC->AHBRSTR |= (RCC_AHBRSTR_AESRST))\r
+#define __HAL_RCC_AES_RELEASE_RESET() (RCC->AHBRSTR &= ~(RCC_AHBRSTR_AESRST))\r
+\r
+#endif /* STM32L162xC || STM32L162xCA || STM32L162xD || STM32L162xE || STM32L162xDX */\r
+\r
+#if defined(STM32L151xD) || defined(STM32L152xD) || defined(STM32L162xD)\r
+\r
+#define __HAL_RCC_FSMC_FORCE_RESET() (RCC->AHBRSTR |= (RCC_AHBRSTR_FSMCRST))\r
+#define __HAL_RCC_FSMC_RELEASE_RESET() (RCC->AHBRSTR &= ~(RCC_AHBRSTR_FSMCRST))\r
+\r
+#endif /* STM32L151xD || STM32L152xD || STM32L162xD */\r
+\r
+#if defined(STM32L100xB) || defined(STM32L100xBA) || defined(STM32L100xC)\\r
+ || defined(STM32L152xB) || defined(STM32L152xBA) || defined(STM32L152xC)\\r
+ || defined(STM32L162xC) || defined(STM32L152xCA) || defined(STM32L152xD)\\r
+ || defined(STM32L162xCA) || defined(STM32L162xD) || defined(STM32L152xE) || defined(STM32L152xDX)\\r
+ || defined(STM32L162xE) || defined(STM32L162xDX)\r
+\r
+#define __HAL_RCC_LCD_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_LCDRST))\r
+#define __HAL_RCC_LCD_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_LCDRST))\r
+\r
+#endif /* STM32L100xB || STM32L152xBA || ... || STM32L152xE || STM32L152xDX || STM32L162xE || STM32L162xDX */\r
+\r
+/** @brief Forces or releases APB1 peripheral reset.\r
+ */\r
+#if defined(STM32L151xC) || defined(STM32L152xC) || defined(STM32L162xC)\\r
+ || defined(STM32L151xCA) || defined(STM32L151xD) || defined(STM32L152xCA)\\r
+ || defined(STM32L152xD) || defined(STM32L162xCA) || defined(STM32L162xD)\\r
+ || defined(STM32L151xE) || defined(STM32L151xDX) || defined(STM32L152xE) || defined(STM32L152xDX) || defined(STM32L162xE) || defined(STM32L162xDX)\r
+\r
+#define __HAL_RCC_TIM5_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM5RST))\r
+#define __HAL_RCC_TIM5_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM5RST))\r
+\r
+#endif /* STM32L151xC || STM32L152xC || STM32L162xC || STM32L151xCA || STM32L151xD || STM32L152xCA || STM32L152xD || STM32L162xCA || STM32L162xD || STM32L151xE || STM32L151xDX || STM32L152xE || STM32L152xDX || STM32L162xE || STM32L162xDX */\r
+\r
+#if defined(STM32L100xC) || defined(STM32L151xC) || defined(STM32L152xC)\\r
+ || defined(STM32L162xC) || defined(STM32L151xCA) || defined(STM32L151xD)\\r
+ || defined(STM32L152xCA) || defined(STM32L152xD) || defined(STM32L162xCA)\\r
+ || defined(STM32L162xD) || defined(STM32L151xE) || defined(STM32L151xDX) || defined(STM32L152xE) || defined(STM32L152xDX)\\r
+ || defined(STM32L162xE) || defined(STM32L162xDX)\r
+\r
+#define __HAL_RCC_SPI3_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_SPI3RST))\r
+#define __HAL_RCC_SPI3_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_SPI3RST))\r
+\r
+#endif /* STM32L100xC || STM32L151xC || STM32L152xC || STM32L162xC || STM32L151xCA || STM32L151xD || STM32L152xCA || STM32L152xD || STM32L162xCA || STM32L162xD || STM32L151xE || STM32L151xDX || STM32L152xE || STM32L152xDX || STM32L162xE || STM32L162xDX */\r
+\r
+#if defined(STM32L151xD) || defined(STM32L152xD) || defined(STM32L162xD)\\r
+ || defined(STM32L151xE) || defined(STM32L151xDX) || defined(STM32L152xE) || defined(STM32L152xDX) || defined(STM32L162xE) || defined(STM32L162xDX)\r
+\r
+#define __HAL_RCC_UART4_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_UART4RST))\r
+#define __HAL_RCC_UART5_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_UART5RST))\r
+\r
+#define __HAL_RCC_UART4_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_UART4RST))\r
+#define __HAL_RCC_UART5_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_UART5RST))\r
+\r
+#endif /* STM32L151xD || STM32L152xD || STM32L162xD || STM32L151xE || STM32L151xDX || STM32L152xE || STM32L152xDX || STM32L162xE || STM32L162xDX */\r
+\r
+#if defined(STM32L151xCA) || defined(STM32L151xD) || defined(STM32L152xCA)\\r
+ || defined(STM32L152xD) || defined(STM32L162xCA) || defined(STM32L162xD)\\r
+ || defined(STM32L151xE) || defined(STM32L151xDX) || defined(STM32L152xE) || defined(STM32L152xDX) || defined(STM32L162xE) || defined(STM32L162xDX)\\r
+ || defined(STM32L162xC) || defined(STM32L152xC) || defined(STM32L151xC)\r
+\r
+#define __HAL_RCC_OPAMP_FORCE_RESET() __HAL_RCC_COMP_FORCE_RESET() /* Peripherals COMP and OPAMP share the same clock domain */\r
+#define __HAL_RCC_OPAMP_RELEASE_RESET() __HAL_RCC_COMP_RELEASE_RESET() /* Peripherals COMP and OPAMP share the same clock domain */\r
+\r
+#endif /* STM32L151xCA || STM32L151xD || STM32L152xCA || STM32L152xD || STM32L162xCA || STM32L162xD || STM32L151xE || STM32L151xDX || STM32L152xE || STM32L152xDX || STM32L162xE || STM32L162xC || STM32L152xC || STM32L151xC */\r
+\r
+/** @brief Forces or releases APB2 peripheral reset.\r
+ */\r
+#if defined(STM32L151xD) || defined(STM32L152xD) || defined(STM32L162xD)\r
+\r
+#define __HAL_RCC_SDIO_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_SDIORST))\r
+#define __HAL_RCC_SDIO_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SDIORST))\r
+\r
+#endif /* STM32L151xD || STM32L152xD || STM32L162xD */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup RCCEx_Peripheral_Clock_Sleep_Enable_Disable RCCEx Peripheral Clock Sleep Enable Disable\r
+ * @brief Enables or disables the AHB1 peripheral clock during Low Power (Sleep) mode.\r
+ * @note Peripheral clock gating in SLEEP mode can be used to further reduce\r
+ * power consumption.\r
+ * @note After wakeup from SLEEP mode, the peripheral clock is enabled again.\r
+ * @note By default, all peripheral clocks are enabled during SLEEP mode.\r
+ * @{\r
+ */\r
+#if defined(STM32L151xB) || defined(STM32L152xB) || defined(STM32L151xBA)\\r
+ || defined(STM32L152xBA) || defined(STM32L151xC) || defined(STM32L152xC)\\r
+ || defined(STM32L162xC) || defined(STM32L151xCA) || defined(STM32L151xD)\\r
+ || defined(STM32L152xCA) || defined(STM32L152xD) || defined(STM32L162xCA)\\r
+ || defined(STM32L162xD) || defined(STM32L151xE) || defined(STM32L151xDX) || defined(STM32L152xE) || defined(STM32L152xDX)\\r
+ || defined(STM32L162xE) || defined(STM32L162xDX)\r
+\r
+#define __HAL_RCC_GPIOE_CLK_SLEEP_ENABLE() (RCC->AHBLPENR |= (RCC_AHBLPENR_GPIOELPEN))\r
+#define __HAL_RCC_GPIOE_CLK_SLEEP_DISABLE() (RCC->AHBLPENR &= ~(RCC_AHBLPENR_GPIOELPEN))\r
+\r
+#endif /* STM32L151xB || STM32L152xB || ... || STM32L151xCA || STM32L151xD || STM32L152xCA || STM32L152xD || STM32L162xCA || STM32L162xD || STM32L151xE || STM32L151xDX || STM32L152xE || STM32L152xDX || STM32L162xE || STM32L162xDX */\r
+\r
+#if defined(STM32L151xCA) || defined(STM32L151xD) || defined(STM32L152xCA)\\r
+ || defined(STM32L152xD) || defined(STM32L162xCA) || defined(STM32L162xD)\\r
+ || defined(STM32L151xE) || defined(STM32L151xDX) || defined(STM32L152xE) || defined(STM32L152xDX) || defined(STM32L162xE) || defined(STM32L162xDX)\r
+\r
+#define __HAL_RCC_GPIOF_CLK_SLEEP_ENABLE() (RCC->AHBLPENR |= (RCC_AHBLPENR_GPIOFLPEN))\r
+#define __HAL_RCC_GPIOG_CLK_SLEEP_ENABLE() (RCC->AHBLPENR |= (RCC_AHBLPENR_GPIOGLPEN))\r
+\r
+#define __HAL_RCC_GPIOF_CLK_SLEEP_DISABLE() (RCC->AHBLPENR &= ~(RCC_AHBLPENR_GPIOFLPEN))\r
+#define __HAL_RCC_GPIOG_CLK_SLEEP_DISABLE() (RCC->AHBLPENR &= ~(RCC_AHBLPENR_GPIOGLPEN))\r
+\r
+#endif /* STM32L151xCA || STM32L151xD || STM32L152xCA || STM32L152xD || STM32L162xCA || STM32L162xD || STM32L151xE || STM32L151xDX || STM32L152xE || STM32L152xDX || STM32L162xE || STM32L162xDX */\r
+\r
+#if defined(STM32L100xC) || defined(STM32L151xC) || defined(STM32L152xC)\\r
+ || defined(STM32L162xC) || defined(STM32L151xCA) || defined(STM32L151xD)\\r
+ || defined(STM32L152xCA) || defined(STM32L152xD) || defined(STM32L162xCA)\\r
+ || defined(STM32L162xD) || defined(STM32L151xE) || defined(STM32L151xDX) || defined(STM32L152xE) || defined(STM32L152xDX)\\r
+ || defined(STM32L162xE) || defined(STM32L162xDX)\r
+\r
+#define __HAL_RCC_DMA2_CLK_SLEEP_ENABLE() (RCC->AHBLPENR |= (RCC_AHBLPENR_DMA2LPEN))\r
+#define __HAL_RCC_DMA2_CLK_SLEEP_DISABLE() (RCC->AHBLPENR &= ~(RCC_AHBLPENR_DMA2LPEN))\r
+\r
+#endif /* STM32L100xC || STM32L151xC || STM32L152xC || STM32L162xC || STM32L151xCA || STM32L151xD || STM32L152xCA || STM32L152xD || STM32L162xCA || STM32L162xD || STM32L151xE || STM32L151xDX || STM32L152xE || STM32L152xDX || STM32L162xE || STM32L162xDX */\r
+\r
+#if defined(STM32L162xC) || defined(STM32L162xCA) || defined(STM32L162xD) || defined(STM32L162xE) || defined(STM32L162xDX)\r
+\r
+#define __HAL_RCC_AES_CLK_SLEEP_ENABLE() (RCC->AHBLPENR |= (RCC_AHBLPENR_AESLPEN))\r
+#define __HAL_RCC_AES_CLK_SLEEP_DISABLE() (RCC->AHBLPENR &= ~(RCC_AHBLPENR_AESLPEN))\r
+\r
+#endif /* STM32L162xC || STM32L162xCA || STM32L162xD || STM32L162xE || STM32L162xDX */\r
+\r
+#if defined(STM32L151xD) || defined(STM32L152xD) || defined(STM32L162xD)\r
+\r
+#define __HAL_RCC_FSMC_CLK_SLEEP_ENABLE() (RCC->AHBLPENR |= (RCC_AHBLPENR_FSMCLPEN))\r
+#define __HAL_RCC_FSMC_CLK_SLEEP_DISABLE() (RCC->AHBLPENR &= ~(RCC_AHBLPENR_FSMCLPEN))\r
+\r
+#endif /* STM32L151xD || STM32L152xD || STM32L162xD */\r
+\r
+#if defined(STM32L100xB) || defined(STM32L100xBA) || defined(STM32L100xC)\\r
+ || defined(STM32L152xB) || defined(STM32L152xBA) || defined(STM32L152xC)\\r
+ || defined(STM32L162xC) || defined(STM32L152xCA) || defined(STM32L152xD)\\r
+ || defined(STM32L162xCA) || defined(STM32L162xD) || defined(STM32L152xE) || defined(STM32L152xDX)\\r
+ || defined(STM32L162xE) || defined(STM32L162xDX)\r
+\r
+#define __HAL_RCC_LCD_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_LCDLPEN))\r
+#define __HAL_RCC_LCD_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_LCDLPEN))\r
+\r
+#endif /* STM32L100xB || STM32L152xBA || ... || STM32L152xE || STM32L152xDX || STM32L162xE || STM32L162xDX */\r
+\r
+/** @brief Enables or disables the APB1 peripheral clock during Low Power (Sleep) mode.\r
+ * @note Peripheral clock gating in SLEEP mode can be used to further reduce\r
+ * power consumption.\r
+ * @note After wakeup from SLEEP mode, the peripheral clock is enabled again.\r
+ * @note By default, all peripheral clocks are enabled during SLEEP mode.\r
+ */\r
+#if defined(STM32L151xC) || defined(STM32L152xC) || defined(STM32L162xC)\\r
+ || defined(STM32L151xCA) || defined(STM32L151xD) || defined(STM32L152xCA)\\r
+ || defined(STM32L152xD) || defined(STM32L162xCA) || defined(STM32L162xD)\\r
+ || defined(STM32L151xE) || defined(STM32L151xDX) || defined(STM32L152xE) || defined(STM32L152xDX) || defined(STM32L162xE) || defined(STM32L162xDX)\r
+\r
+#define __HAL_RCC_TIM5_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM5LPEN))\r
+#define __HAL_RCC_TIM5_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM5LPEN))\r
+\r
+#endif /* STM32L151xC || STM32L152xC || STM32L162xC || STM32L151xCA || STM32L151xD || STM32L152xCA || STM32L152xD || STM32L162xCA || STM32L162xD || STM32L151xE || STM32L151xDX || STM32L152xE || STM32L152xDX || STM32L162xE || STM32L162xDX */\r
+\r
+#if defined(STM32L100xC) || defined(STM32L151xC) || defined(STM32L152xC)\\r
+ || defined(STM32L162xC) || defined(STM32L151xCA) || defined(STM32L151xD)\\r
+ || defined(STM32L152xCA) || defined(STM32L152xD) || defined(STM32L162xCA)\\r
+ || defined(STM32L162xD) || defined(STM32L151xE) || defined(STM32L151xDX) || defined(STM32L152xE) || defined(STM32L152xDX)\\r
+ || defined(STM32L162xE) || defined(STM32L162xDX)\r
+\r
+#define __HAL_RCC_SPI3_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_SPI3LPEN))\r
+#define __HAL_RCC_SPI3_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_SPI3LPEN))\r
+\r
+#endif /* STM32L100xC || STM32L151xC || STM32L152xC || STM32L162xC || STM32L151xCA || STM32L151xD || STM32L152xCA || STM32L152xD || STM32L162xCA || STM32L162xD || STM32L151xE || STM32L151xDX || STM32L152xE || STM32L152xDX || STM32L162xE || STM32L162xDX */\r
+\r
+#if defined(STM32L151xD) || defined(STM32L152xD) || defined(STM32L162xD)\\r
+ || defined(STM32L151xE) || defined(STM32L151xDX) || defined(STM32L152xE) || defined(STM32L152xDX) || defined(STM32L162xE) || defined(STM32L162xDX)\r
+\r
+#define __HAL_RCC_UART4_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_UART4LPEN))\r
+#define __HAL_RCC_UART5_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_UART5LPEN))\r
+\r
+#define __HAL_RCC_UART4_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_UART4LPEN))\r
+#define __HAL_RCC_UART5_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_UART5LPEN))\r
+\r
+#endif /* STM32L151xD || STM32L152xD || STM32L162xD || STM32L151xE || STM32L151xDX || STM32L152xE || STM32L152xDX || STM32L162xE || STM32L162xDX */\r
+\r
+#if defined(STM32L151xCA) || defined(STM32L151xD) || defined(STM32L152xCA)\\r
+ || defined(STM32L152xD) || defined(STM32L162xCA) || defined(STM32L162xD)\\r
+ || defined(STM32L151xE) || defined(STM32L151xDX) || defined(STM32L152xE) || defined(STM32L152xDX) || defined(STM32L162xE) || defined(STM32L162xDX)\\r
+ || defined(STM32L162xC) || defined(STM32L152xC) || defined(STM32L151xC)\r
+\r
+#define __HAL_RCC_OPAMP_CLK_SLEEP_ENABLE() __HAL_RCC_COMP_CLK_SLEEP_ENABLE() /* Peripherals COMP and OPAMP share the same clock domain */\r
+#define __HAL_RCC_OPAMP_CLK_SLEEP_DISABLE() __HAL_RCC_COMP_CLK_SLEEP_DISABLE() /* Peripherals COMP and OPAMP share the same clock domain */\r
+\r
+#endif /* STM32L151xCA || STM32L151xD || STM32L152xCA || STM32L152xD || STM32L162xCA || STM32L162xD || STM32L151xE || STM32L151xDX || STM32L152xE || STM32L152xDX || STM32L162xE || STM32L162xC || STM32L152xC || STM32L151xC */\r
+\r
+/** @brief Enables or disables the APB2 peripheral clock during Low Power (Sleep) mode.\r
+ * @note Peripheral clock gating in SLEEP mode can be used to further reduce\r
+ * power consumption.\r
+ * @note After wakeup from SLEEP mode, the peripheral clock is enabled again.\r
+ * @note By default, all peripheral clocks are enabled during SLEEP mode.\r
+ */\r
+#if defined(STM32L151xD) || defined(STM32L152xD) || defined(STM32L162xD)\r
+\r
+#define __HAL_RCC_SDIO_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_SDIOLPEN))\r
+#define __HAL_RCC_SDIO_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_SDIOLPEN))\r
+\r
+#endif /* STM32L151xD || STM32L152xD || STM32L162xD */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup RCCEx_Peripheral_Clock_Enable_Disable_Status Peripheral Clock Enable Disable Status\r
+ * @brief Get the enable or disable status of peripheral clock.\r
+ * @note After reset, the peripheral clock (used for registers read/write access)\r
+ * is disabled and the application software has to enable this clock before\r
+ * using it.\r
+ * @{\r
+ */\r
+\r
+#if defined(STM32L151xB) || defined(STM32L152xB) || defined(STM32L151xBA)\\r
+ || defined(STM32L152xBA) || defined(STM32L151xC) || defined(STM32L152xC)\\r
+ || defined(STM32L162xC) || defined(STM32L151xCA) || defined(STM32L151xD)\\r
+ || defined(STM32L152xCA) || defined(STM32L152xD) || defined(STM32L162xCA)\\r
+ || defined(STM32L162xD) || defined(STM32L151xE) || defined(STM32L151xDX) || defined(STM32L152xE) || defined(STM32L152xDX)\\r
+ || defined(STM32L162xE) || defined(STM32L162xDX)\r
+\r
+#define __HAL_RCC_GPIOE_IS_CLK_ENABLED() ((RCC->AHBENR & (RCC_AHBENR_GPIOEEN)) != 0U)\r
+#define __HAL_RCC_GPIOE_IS_CLK_DISABLED() ((RCC->AHBENR & (RCC_AHBENR_GPIOEEN)) == 0U)\r
+\r
+#endif /* STM32L151xB || STM32L152xB || ... || STM32L151xCA || STM32L151xD || STM32L152xCA || STM32L152xD || STM32L162xCA || STM32L162xD || STM32L151xE || STM32L151xDX || STM32L152xE || STM32L152xDX || STM32L162xE || STM32L162xDX */\r
+\r
+#if defined(STM32L151xCA) || defined(STM32L151xD) || defined(STM32L152xCA)\\r
+ || defined(STM32L152xD) || defined(STM32L162xCA) || defined(STM32L162xD)\\r
+ || defined(STM32L151xE) || defined(STM32L151xDX) || defined(STM32L152xE) || defined(STM32L152xDX) || defined(STM32L162xE) || defined(STM32L162xDX)\r
+\r
+#define __HAL_RCC_GPIOF_IS_CLK_ENABLED() ((RCC->AHBENR & (RCC_AHBENR_GPIOFEN)) != 0U)\r
+#define __HAL_RCC_GPIOG_IS_CLK_ENABLED() ((RCC->AHBENR & (RCC_AHBENR_GPIOGEN)) != 0U)\r
+#define __HAL_RCC_GPIOF_IS_CLK_DISABLED() ((RCC->AHBENR & (RCC_AHBENR_GPIOFEN)) == 0U)\r
+#define __HAL_RCC_GPIOG_IS_CLK_DISABLED() ((RCC->AHBENR & (RCC_AHBENR_GPIOGEN)) == 0U)\r
+\r
+#endif /* STM32L151xCA || STM32L151xD || STM32L152xCA || STM32L152xD || STM32L162xCA || STM32L162xD || STM32L151xE || STM32L151xDX || STM32L152xE || STM32L152xDX || STM32L162xE || STM32L162xDX */\r
+\r
+#if defined(STM32L100xC) || defined(STM32L151xC) || defined(STM32L152xC)\\r
+ || defined(STM32L162xC) || defined(STM32L151xCA) || defined(STM32L151xD)\\r
+ || defined(STM32L152xCA) || defined(STM32L152xD) || defined(STM32L162xCA)\\r
+ || defined(STM32L162xD) || defined(STM32L151xE) || defined(STM32L151xDX) || defined(STM32L152xE) || defined(STM32L152xDX)\\r
+ || defined(STM32L162xE) || defined(STM32L162xDX)\r
+\r
+#define __HAL_RCC_DMA2_IS_CLK_ENABLED() ((RCC->AHBENR & (RCC_AHBENR_DMA2EN)) != 0U)\r
+#define __HAL_RCC_DMA2_IS_CLK_DISABLED() ((RCC->AHBENR & (RCC_AHBENR_DMA2EN)) == 0U)\r
+\r
+#endif /* STM32L100xC || STM32L151xC || STM32L152xC || STM32L162xC || STM32L151xCA || STM32L151xD || STM32L152xCA || STM32L152xD || STM32L162xCA || STM32L162xD || STM32L151xE || STM32L151xDX || STM32L152xE || STM32L152xDX || STM32L162xE || STM32L162xDX */\r
+\r
+#if defined(STM32L162xC) || defined(STM32L162xCA) || defined(STM32L162xD)\\r
+ || defined(STM32L162xE) || defined(STM32L162xDX)\r
+\r
+#define __HAL_RCC_AES_IS_CLK_ENABLED() ((RCC->AHBENR & (RCC_AHBENR_AESEN)) != 0U)\r
+#define __HAL_RCC_AES_IS_CLK_DISABLED() ((RCC->AHBENR & (RCC_AHBENR_AESEN)) == 0U)\r
+\r
+#endif /* STM32L162xC || STM32L162xCA || STM32L162xD || STM32L162xE || STM32L162xDX */\r
+\r
+#if defined(STM32L151xD) || defined(STM32L152xD) || defined(STM32L162xD)\r
+\r
+#define __HAL_RCC_FSMC_IS_CLK_ENABLED() ((RCC->AHBENR & (RCC_AHBENR_FSMCEN)) != 0U)\r
+#define __HAL_RCC_FSMC_IS_CLK_DISABLED() ((RCC->AHBENR & (RCC_AHBENR_FSMCEN)) == 0U)\r
+\r
+#endif /* STM32L151xD || STM32L152xD || STM32L162xD */\r
+\r
+#if defined(STM32L100xB) || defined(STM32L100xBA) || defined(STM32L100xC)\\r
+ || defined(STM32L152xB) || defined(STM32L152xBA) || defined(STM32L152xC)\\r
+ || defined(STM32L162xC) || defined(STM32L152xCA) || defined(STM32L152xD)\\r
+ || defined(STM32L162xCA) || defined(STM32L162xD) || defined(STM32L152xE) || defined(STM32L152xDX)\\r
+ || defined(STM32L162xE) || defined(STM32L162xDX)\r
+\r
+#define __HAL_RCC_LCD_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_LCDEN)) != 0U)\r
+#define __HAL_RCC_LCD_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_LCDEN)) == 0U)\r
+\r
+#endif /* STM32L100xB || STM32L152xBA || ... || STM32L152xE || STM32L152xDX || STM32L162xE || STM32L162xDX */\r
+\r
+#if defined(STM32L151xC) || defined(STM32L152xC) || defined(STM32L162xC)\\r
+ || defined(STM32L151xCA) || defined(STM32L151xD) || defined(STM32L152xCA)\\r
+ || defined(STM32L152xD) || defined(STM32L162xCA) || defined(STM32L162xD)\\r
+ || defined(STM32L151xE) || defined(STM32L151xDX) || defined(STM32L152xE) || defined(STM32L152xDX) || defined(STM32L162xE) || defined(STM32L162xDX)\r
+\r
+#define __HAL_RCC_TIM5_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM5EN)) != 0U)\r
+#define __HAL_RCC_TIM5_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM5EN)) == 0U)\r
+\r
+#endif /* STM32L151xC || STM32L152xC || STM32L162xC || STM32L151xCA || STM32L151xD || STM32L152xCA || STM32L152xD || STM32L162xCA || STM32L162xD || STM32L151xE || STM32L151xDX || STM32L152xE || STM32L152xDX || STM32L162xE || STM32L162xDX */\r
+\r
+#if defined(STM32L100xC) || defined(STM32L151xC) || defined(STM32L152xC)\\r
+ || defined(STM32L162xC) || defined(STM32L151xCA) || defined(STM32L151xD)\\r
+ || defined(STM32L152xCA) || defined(STM32L152xD) || defined(STM32L162xCA)\\r
+ || defined(STM32L162xD) || defined(STM32L151xE) || defined(STM32L151xDX) || defined(STM32L152xE) || defined(STM32L152xDX)\\r
+ || defined(STM32L162xE) || defined(STM32L162xDX)\r
+\r
+#define __HAL_RCC_SPI3_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_SPI3EN)) != 0U)\r
+#define __HAL_RCC_SPI3_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_SPI3EN)) == 0U)\r
+\r
+#endif /* STM32L100xC || STM32L151xC || STM32L152xC || STM32L162xC || STM32L151xCA || STM32L151xD || STM32L152xCA || STM32L152xD || STM32L162xCA || STM32L162xD || STM32L151xE || STM32L151xDX || STM32L152xE || STM32L152xDX || STM32L162xE || STM32L162xDX */\r
+\r
+#if defined(STM32L151xD) || defined(STM32L152xD) || defined(STM32L162xD)\\r
+ || defined(STM32L151xE) || defined(STM32L151xDX) || defined(STM32L152xE) || defined(STM32L152xDX) || defined(STM32L162xE) || defined(STM32L162xDX)\r
+\r
+#define __HAL_RCC_UART4_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_UART4EN)) != 0U)\r
+#define __HAL_RCC_UART5_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_UART5EN)) != 0U)\r
+#define __HAL_RCC_UART4_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_UART4EN)) == 0U)\r
+#define __HAL_RCC_UART5_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_UART5EN)) == 0U)\r
+\r
+#endif /* STM32L151xD || STM32L152xD || STM32L162xD || STM32L151xE || STM32L151xDX || STM32L152xE || STM32L152xDX || STM32L162xE || STM32L162xDX */\r
+\r
+#if defined(STM32L151xCA) || defined(STM32L151xD) || defined(STM32L152xCA)\\r
+ || defined(STM32L152xD) || defined(STM32L162xCA) || defined(STM32L162xD)\\r
+ || defined(STM32L151xE) || defined(STM32L151xDX) || defined(STM32L152xE) || defined(STM32L152xDX) || defined(STM32L162xE) || defined(STM32L162xDX)\\r
+ || defined(STM32L162xC) || defined(STM32L152xC) || defined(STM32L151xC)\r
+\r
+#define __HAL_RCC_OPAMP_IS_CLK_ENABLED() __HAL_RCC_COMP_IS_CLK_ENABLED()\r
+#define __HAL_RCC_OPAMP_IS_CLK_DISABLED() __HAL_RCC_COMP_IS_CLK_DISABLED()\r
+\r
+#endif /* STM32L151xCA || STM32L151xD || STM32L152xCA || STM32L152xD || STM32L162xCA || STM32L162xD || STM32L151xE || STM32L151xDX || STM32L152xE || STM32L152xDX || STM32L162xE || STM32L162xC || STM32L152xC || STM32L151xC */\r
+\r
+#if defined(STM32L151xD) || defined(STM32L152xD) || defined(STM32L162xD)\r
+\r
+#define __HAL_RCC_SDIO_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SDIOEN)) != 0U)\r
+#define __HAL_RCC_SDIO_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SDIOEN)) == 0U)\r
+\r
+#endif /* STM32L151xD || STM32L152xD || STM32L162xD */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup RCCEx_Peripheral_Clock_Sleep_Enable_Disable_Status Peripheral Clock Sleep Enable Disable Status\r
+ * @brief Get the enable or disable status of peripheral clock during Low Power (Sleep) mode.\r
+ * @note Peripheral clock gating in SLEEP mode can be used to further reduce\r
+ * power consumption.\r
+ * @note After wakeup from SLEEP mode, the peripheral clock is enabled again.\r
+ * @note By default, all peripheral clocks are enabled during SLEEP mode.\r
+ * @{\r
+ */\r
+\r
+#if defined(STM32L151xB) || defined(STM32L152xB) || defined(STM32L151xBA)\\r
+ || defined(STM32L152xBA) || defined(STM32L151xC) || defined(STM32L152xC)\\r
+ || defined(STM32L162xC) || defined(STM32L151xCA) || defined(STM32L151xD)\\r
+ || defined(STM32L152xCA) || defined(STM32L152xD) || defined(STM32L162xCA)\\r
+ || defined(STM32L162xD) || defined(STM32L151xE) || defined(STM32L151xDX) || defined(STM32L152xE) || defined(STM32L152xDX)\\r
+ || defined(STM32L162xE) || defined(STM32L162xDX)\r
+\r
+#define __HAL_RCC_GPIOE_IS_CLK_SLEEP_ENABLED() ((RCC->AHBLPENR & (RCC_AHBLPENR_GPIOELPEN)) != 0U)\r
+#define __HAL_RCC_GPIOE_IS_CLK_SLEEP_DISABLED() ((RCC->AHBLPENR & (RCC_AHBLPENR_GPIOELPEN)) == 0U)\r
+\r
+#endif /* STM32L151xB || STM32L152xB || ... || STM32L151xCA || STM32L151xD || STM32L152xCA || STM32L152xD || STM32L162xCA || STM32L162xD || STM32L151xE || STM32L151xDX || STM32L152xE || STM32L152xDX || STM32L162xE || STM32L162xDX */\r
+\r
+#if defined(STM32L151xCA) || defined(STM32L151xD) || defined(STM32L152xCA)\\r
+ || defined(STM32L152xD) || defined(STM32L162xCA) || defined(STM32L162xD)\\r
+ || defined(STM32L151xE) || defined(STM32L151xDX) || defined(STM32L152xE) || defined(STM32L152xDX) || defined(STM32L162xE) || defined(STM32L162xDX)\r
+\r
+#define __HAL_RCC_GPIOF_IS_CLK_SLEEP_ENABLED() ((RCC->AHBLPENR & (RCC_AHBLPENR_GPIOFLPEN)) != 0U)\r
+#define __HAL_RCC_GPIOG_IS_CLK_SLEEP_ENABLED() ((RCC->AHBLPENR & (RCC_AHBLPENR_GPIOGLPEN)) != 0U)\r
+#define __HAL_RCC_GPIOF_IS_CLK_SLEEP_DISABLED() ((RCC->AHBLPENR & (RCC_AHBLPENR_GPIOFLPEN)) == 0U)\r
+#define __HAL_RCC_GPIOG_IS_CLK_SLEEP_DISABLED() ((RCC->AHBLPENR & (RCC_AHBLPENR_GPIOGLPEN)) == 0U)\r
+\r
+#endif /* STM32L151xCA || STM32L151xD || STM32L152xCA || STM32L152xD || STM32L162xCA || STM32L162xD || STM32L151xE || STM32L151xDX || STM32L152xE || STM32L152xDX || STM32L162xE || STM32L162xDX */\r
+\r
+#if defined(STM32L100xC) || defined(STM32L151xC) || defined(STM32L152xC)\\r
+ || defined(STM32L162xC) || defined(STM32L151xCA) || defined(STM32L151xD)\\r
+ || defined(STM32L152xCA) || defined(STM32L152xD) || defined(STM32L162xCA)\\r
+ || defined(STM32L162xD) || defined(STM32L151xE) || defined(STM32L151xDX) || defined(STM32L152xE) || defined(STM32L152xDX)\\r
+ || defined(STM32L162xE) || defined(STM32L162xDX)\r
+\r
+#define __HAL_RCC_DMA2_IS_CLK_SLEEP_ENABLED() ((RCC->AHBLPENR & (RCC_AHBLPENR_DMA2LPEN)) != 0U)\r
+#define __HAL_RCC_DMA2_IS_CLK_SLEEP_DISABLED() ((RCC->AHBLPENR & (RCC_AHBLPENR_DMA2LPEN)) == 0U)\r
+\r
+#endif /* STM32L100xC || STM32L151xC || STM32L152xC || STM32L162xC || STM32L151xCA || STM32L151xD || STM32L152xCA || STM32L152xD || STM32L162xCA || STM32L162xD || STM32L151xE || STM32L151xDX || STM32L152xE || STM32L152xDX || STM32L162xE || STM32L162xDX */\r
+\r
+#if defined(STM32L162xC) || defined(STM32L162xCA) || defined(STM32L162xD)\\r
+ || defined(STM32L162xE) || defined(STM32L162xDX)\r
+\r
+#define __HAL_RCC_AES_IS_CLK_SLEEP_ENABLED() ((RCC->AHBLPENR & (RCC_AHBLPENR_AESLPEN)) != 0U)\r
+#define __HAL_RCC_AES_IS_CLK_SLEEP_DISABLED() ((RCC->AHBLPENR & (RCC_AHBLPENR_AESLPEN)) == 0U)\r
+\r
+#endif /* STM32L162xC || STM32L162xCA || STM32L162xD || STM32L162xE || STM32L162xDX */\r
+\r
+#if defined(STM32L151xD) || defined(STM32L152xD) || defined(STM32L162xD)\r
+\r
+#define __HAL_RCC_FSMC_IS_CLK_SLEEP_ENABLED() ((RCC->AHBLPENR & (RCC_AHBLPENR_FSMCLPEN)) != 0U)\r
+#define __HAL_RCC_FSMC_IS_CLK_SLEEP_DISABLED() ((RCC->AHBLPENR & (RCC_AHBLPENR_FSMCLPEN)) == 0U)\r
+\r
+#endif /* STM32L151xD || STM32L152xD || STM32L162xD */\r
+\r
+#if defined(STM32L100xB) || defined(STM32L100xBA) || defined(STM32L100xC)\\r
+ || defined(STM32L152xB) || defined(STM32L152xBA) || defined(STM32L152xC)\\r
+ || defined(STM32L162xC) || defined(STM32L152xCA) || defined(STM32L152xD)\\r
+ || defined(STM32L162xCA) || defined(STM32L162xD) || defined(STM32L152xE) || defined(STM32L152xDX)\\r
+ || defined(STM32L162xE) || defined(STM32L162xDX)\r
+\r
+#define __HAL_RCC_LCD_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_LCDLPEN)) != 0U)\r
+#define __HAL_RCC_LCD_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_LCDLPEN)) == 0U)\r
+\r
+#endif /* STM32L100xB || STM32L152xBA || ... || STM32L152xE || STM32L152xDX || STM32L162xE || STM32L162xDX */\r
+\r
+#if defined(STM32L151xC) || defined(STM32L152xC) || defined(STM32L162xC)\\r
+ || defined(STM32L151xCA) || defined(STM32L151xD) || defined(STM32L152xCA)\\r
+ || defined(STM32L152xD) || defined(STM32L162xCA) || defined(STM32L162xD)\\r
+ || defined(STM32L151xE) || defined(STM32L151xDX) || defined(STM32L152xE) || defined(STM32L152xDX) || defined(STM32L162xE) || defined(STM32L162xDX)\r
+\r
+#define __HAL_RCC_TIM5_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_TIM5LPEN)) != 0U)\r
+#define __HAL_RCC_TIM5_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_TIM5LPEN)) == 0U)\r
+\r
+#endif /* STM32L151xC || STM32L152xC || STM32L162xC || STM32L151xCA || STM32L151xD || STM32L152xCA || STM32L152xD || STM32L162xCA || STM32L162xD || STM32L151xE || STM32L151xDX || STM32L152xE || STM32L152xDX || STM32L162xE || STM32L162xDX */\r
+\r
+#if defined(STM32L100xC) || defined(STM32L151xC) || defined(STM32L152xC)\\r
+ || defined(STM32L162xC) || defined(STM32L151xCA) || defined(STM32L151xD)\\r
+ || defined(STM32L152xCA) || defined(STM32L152xD) || defined(STM32L162xCA)\\r
+ || defined(STM32L162xD) || defined(STM32L151xE) || defined(STM32L151xDX) || defined(STM32L152xE) || defined(STM32L152xDX)\\r
+ || defined(STM32L162xE) || defined(STM32L162xDX)\r
+\r
+#define __HAL_RCC_SPI3_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_SPI3LPEN)) != 0U)\r
+#define __HAL_RCC_SPI3_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_SPI3LPEN)) == 0U)\r
+\r
+#endif /* STM32L100xC || STM32L151xC || STM32L152xC || STM32L162xC || STM32L151xCA || STM32L151xD || STM32L152xCA || STM32L152xD || STM32L162xCA || STM32L162xD || STM32L151xE || STM32L151xDX || STM32L152xE || STM32L152xDX || STM32L162xE || STM32L162xDX */\r
+\r
+#if defined(STM32L151xD) || defined(STM32L152xD) || defined(STM32L162xD)\\r
+ || defined(STM32L151xE) || defined(STM32L151xDX) || defined(STM32L152xE) || defined(STM32L152xDX) || defined(STM32L162xE) || defined(STM32L162xDX)\r
+\r
+#define __HAL_RCC_UART4_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_UART4LPEN)) != 0U)\r
+#define __HAL_RCC_UART5_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_UART5LPEN)) != 0U)\r
+#define __HAL_RCC_UART4_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_UART4LPEN)) == 0U)\r
+#define __HAL_RCC_UART5_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_UART5LPEN)) == 0U)\r
+\r
+#endif /* STM32L151xD || STM32L152xD || STM32L162xD || STM32L151xE || STM32L151xDX || STM32L152xE || STM32L152xDX || STM32L162xE || STM32L162xDX */\r
+\r
+#if defined(STM32L151xCA) || defined(STM32L151xD) || defined(STM32L152xCA)\\r
+ || defined(STM32L152xD) || defined(STM32L162xCA) || defined(STM32L162xD)\\r
+ || defined(STM32L151xE) || defined(STM32L151xDX) || defined(STM32L152xE) || defined(STM32L152xDX) || defined(STM32L162xE) || defined(STM32L162xDX)\\r
+ || defined(STM32L162xC) || defined(STM32L152xC) || defined(STM32L151xC)\r
+\r
+#define __HAL_RCC_OPAMP_IS_CLK_SLEEP_ENABLED() __HAL_RCC_COMP_IS_CLK_SLEEP_ENABLED()\r
+#define __HAL_RCC_OPAMP_IS_CLK_SLEEP_DISABLED() __HAL_RCC_COMP_IS_CLK_SLEEP_DISABLED()\r
+\r
+#endif /* STM32L151xCA || STM32L151xD || STM32L152xCA || STM32L152xD || STM32L162xCA || STM32L162xD || STM32L151xE || STM32L151xDX || STM32L152xE || STM32L152xDX || STM32L162xE || STM32L162xC || STM32L152xC || STM32L151xC */\r
+\r
+#if defined(STM32L151xD) || defined(STM32L152xD) || defined(STM32L162xD)\r
+\r
+#define __HAL_RCC_SDIO_IS_CLK_SLEEP_ENABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_SDIOLPEN)) != 0U)\r
+#define __HAL_RCC_SDIO_IS_CLK_SLEEP_DISABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_SDIOLPEN)) == 0U)\r
+\r
+#endif /* STM32L151xD || STM32L152xD || STM32L162xD */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+\r
+#if defined(RCC_LSECSS_SUPPORT)\r
+\r
+/**\r
+ * @brief Enable interrupt on RCC LSE CSS EXTI Line 19.\r
+ * @retval None\r
+ */\r
+#define __HAL_RCC_LSECSS_EXTI_ENABLE_IT() SET_BIT(EXTI->IMR, RCC_EXTI_LINE_LSECSS)\r
+\r
+/**\r
+ * @brief Disable interrupt on RCC LSE CSS EXTI Line 19.\r
+ * @retval None\r
+ */\r
+#define __HAL_RCC_LSECSS_EXTI_DISABLE_IT() CLEAR_BIT(EXTI->IMR, RCC_EXTI_LINE_LSECSS)\r
+\r
+/**\r
+ * @brief Enable event on RCC LSE CSS EXTI Line 19.\r
+ * @retval None.\r
+ */\r
+#define __HAL_RCC_LSECSS_EXTI_ENABLE_EVENT() SET_BIT(EXTI->EMR, RCC_EXTI_LINE_LSECSS)\r
+\r
+/**\r
+ * @brief Disable event on RCC LSE CSS EXTI Line 19.\r
+ * @retval None.\r
+ */\r
+#define __HAL_RCC_LSECSS_EXTI_DISABLE_EVENT() CLEAR_BIT(EXTI->EMR, RCC_EXTI_LINE_LSECSS)\r
+\r
+\r
+/**\r
+ * @brief RCC LSE CSS EXTI line configuration: set falling edge trigger.\r
+ * @retval None.\r
+ */\r
+#define __HAL_RCC_LSECSS_EXTI_ENABLE_FALLING_EDGE() SET_BIT(EXTI->FTSR, RCC_EXTI_LINE_LSECSS)\r
+\r
+\r
+/**\r
+ * @brief Disable the RCC LSE CSS Extended Interrupt Falling Trigger.\r
+ * @retval None.\r
+ */\r
+#define __HAL_RCC_LSECSS_EXTI_DISABLE_FALLING_EDGE() CLEAR_BIT(EXTI->FTSR, RCC_EXTI_LINE_LSECSS)\r
+\r
+\r
+/**\r
+ * @brief RCC LSE CSS EXTI line configuration: set rising edge trigger.\r
+ * @retval None.\r
+ */\r
+#define __HAL_RCC_LSECSS_EXTI_ENABLE_RISING_EDGE() SET_BIT(EXTI->RTSR, RCC_EXTI_LINE_LSECSS)\r
+\r
+/**\r
+ * @brief Disable the RCC LSE CSS Extended Interrupt Rising Trigger.\r
+ * @retval None.\r
+ */\r
+#define __HAL_RCC_LSECSS_EXTI_DISABLE_RISING_EDGE() CLEAR_BIT(EXTI->RTSR, RCC_EXTI_LINE_LSECSS)\r
+\r
+/**\r
+ * @brief RCC LSE CSS EXTI line configuration: set rising & falling edge trigger.\r
+ * @retval None.\r
+ */\r
+#define __HAL_RCC_LSECSS_EXTI_ENABLE_RISING_FALLING_EDGE() \\r
+ do { \\r
+ __HAL_RCC_LSECSS_EXTI_ENABLE_RISING_EDGE(); \\r
+ __HAL_RCC_LSECSS_EXTI_ENABLE_FALLING_EDGE(); \\r
+ } while(0U)\r
+\r
+/**\r
+ * @brief Disable the RCC LSE CSS Extended Interrupt Rising & Falling Trigger.\r
+ * @retval None.\r
+ */\r
+#define __HAL_RCC_LSECSS_EXTI_DISABLE_RISING_FALLING_EDGE() \\r
+ do { \\r
+ __HAL_RCC_LSECSS_EXTI_DISABLE_RISING_EDGE(); \\r
+ __HAL_RCC_LSECSS_EXTI_DISABLE_FALLING_EDGE(); \\r
+ } while(0U)\r
+\r
+/**\r
+ * @brief Check whether the specified RCC LSE CSS EXTI interrupt flag is set or not.\r
+ * @retval EXTI RCC LSE CSS Line Status.\r
+ */\r
+#define __HAL_RCC_LSECSS_EXTI_GET_FLAG() (EXTI->PR & (RCC_EXTI_LINE_LSECSS))\r
+\r
+/**\r
+ * @brief Clear the RCC LSE CSS EXTI flag.\r
+ * @retval None.\r
+ */\r
+#define __HAL_RCC_LSECSS_EXTI_CLEAR_FLAG() (EXTI->PR = (RCC_EXTI_LINE_LSECSS))\r
+\r
+/**\r
+ * @brief Generate a Software interrupt on selected EXTI line.\r
+ * @retval None.\r
+ */\r
+#define __HAL_RCC_LSECSS_EXTI_GENERATE_SWIT() SET_BIT(EXTI->SWIER, RCC_EXTI_LINE_LSECSS)\r
+\r
+#endif /* RCC_LSECSS_SUPPORT */\r
+\r
+#if defined(LCD)\r
+\r
+/** @defgroup RCCEx_LCD_Configuration LCD Configuration\r
+ * @brief Macros to configure clock source of LCD peripherals.\r
+ * @{\r
+ */\r
+\r
+/** @brief Macro to configures LCD clock (LCDCLK).\r
+ * @note LCD and RTC use the same configuration\r
+ * @note LCD can however be used in the Stop low power mode if the LSE or LSI is used as the\r
+ * LCD clock source.\r
+ *\r
+ * @param __LCD_CLKSOURCE__ specifies the LCD clock source.\r
+ * This parameter can be one of the following values:\r
+ * @arg @ref RCC_RTCCLKSOURCE_LSE LSE selected as LCD clock\r
+ * @arg @ref RCC_RTCCLKSOURCE_LSI LSI selected as LCD clock\r
+ * @arg @ref RCC_RTCCLKSOURCE_HSE_DIV2 HSE divided by 2 selected as LCD clock\r
+ * @arg @ref RCC_RTCCLKSOURCE_HSE_DIV4 HSE divided by 4 selected as LCD clock\r
+ * @arg @ref RCC_RTCCLKSOURCE_HSE_DIV8 HSE divided by 8 selected as LCD clock\r
+ * @arg @ref RCC_RTCCLKSOURCE_HSE_DIV16 HSE divided by 16 selected as LCD clock\r
+ */\r
+#define __HAL_RCC_LCD_CONFIG(__LCD_CLKSOURCE__) __HAL_RCC_RTC_CONFIG(__LCD_CLKSOURCE__)\r
+\r
+/** @brief Macro to get the LCD clock source.\r
+ */\r
+#define __HAL_RCC_GET_LCD_SOURCE() __HAL_RCC_GET_RTC_SOURCE()\r
+\r
+/** @brief Macro to get the LCD clock pre-scaler.\r
+ */\r
+#define __HAL_RCC_GET_LCD_HSE_PRESCALER() __HAL_RCC_GET_RTC_HSE_PRESCALER()\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+#endif /* LCD */\r
+\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/* Exported functions --------------------------------------------------------*/\r
+/** @addtogroup RCCEx_Exported_Functions\r
+ * @{\r
+ */\r
+\r
+/** @addtogroup RCCEx_Exported_Functions_Group1\r
+ * @{\r
+ */\r
+\r
+HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit);\r
+void HAL_RCCEx_GetPeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit);\r
+uint32_t HAL_RCCEx_GetPeriphCLKFreq(uint32_t PeriphClk);\r
+\r
+#if defined(RCC_LSECSS_SUPPORT)\r
+\r
+void HAL_RCCEx_EnableLSECSS(void);\r
+void HAL_RCCEx_DisableLSECSS(void);\r
+void HAL_RCCEx_EnableLSECSS_IT(void);\r
+void HAL_RCCEx_LSECSS_IRQHandler(void);\r
+void HAL_RCCEx_LSECSS_Callback(void);\r
+\r
+#endif /* RCC_LSECSS_SUPPORT */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+#ifdef __cplusplus\r
+}\r
+#endif\r
+\r
+#endif /* __STM32L1xx_HAL_RCC_EX_H */\r
+\r
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\r
+\r
--- /dev/null
+/**\r
+ ******************************************************************************\r
+ * @file stm32l1xx_hal_tim.h\r
+ * @author MCD Application Team\r
+ * @brief Header file of TIM HAL module.\r
+ ******************************************************************************\r
+ * @attention\r
+ *\r
+ * <h2><center>© Copyright (c) 2016 STMicroelectronics.\r
+ * All rights reserved.</center></h2>\r
+ *\r
+ * This software component is licensed by ST under BSD 3-Clause license,\r
+ * the "License"; You may not use this file except in compliance with the\r
+ * License. You may obtain a copy of the License at:\r
+ * opensource.org/licenses/BSD-3-Clause\r
+ *\r
+ ******************************************************************************\r
+ */\r
+\r
+/* Define to prevent recursive inclusion -------------------------------------*/\r
+#ifndef STM32L1xx_HAL_TIM_H\r
+#define STM32L1xx_HAL_TIM_H\r
+\r
+#ifdef __cplusplus\r
+extern "C" {\r
+#endif\r
+\r
+/* Includes ------------------------------------------------------------------*/\r
+#include "stm32l1xx_hal_def.h"\r
+\r
+/** @addtogroup STM32L1xx_HAL_Driver\r
+ * @{\r
+ */\r
+\r
+/** @addtogroup TIM\r
+ * @{\r
+ */\r
+\r
+/* Exported types ------------------------------------------------------------*/\r
+/** @defgroup TIM_Exported_Types TIM Exported Types\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @brief TIM Time base Configuration Structure definition\r
+ */\r
+typedef struct\r
+{\r
+ uint32_t Prescaler; /*!< Specifies the prescaler value used to divide the TIM clock.\r
+ This parameter can be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF */\r
+\r
+ uint32_t CounterMode; /*!< Specifies the counter mode.\r
+ This parameter can be a value of @ref TIM_Counter_Mode */\r
+\r
+ uint32_t Period; /*!< Specifies the period value to be loaded into the active\r
+ Auto-Reload Register at the next update event.\r
+ This parameter can be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF. */\r
+\r
+ uint32_t ClockDivision; /*!< Specifies the clock division.\r
+ This parameter can be a value of @ref TIM_ClockDivision */\r
+\r
+ uint32_t AutoReloadPreload; /*!< Specifies the auto-reload preload.\r
+ This parameter can be a value of @ref TIM_AutoReloadPreload */\r
+} TIM_Base_InitTypeDef;\r
+\r
+/**\r
+ * @brief TIM Output Compare Configuration Structure definition\r
+ */\r
+typedef struct\r
+{\r
+ uint32_t OCMode; /*!< Specifies the TIM mode.\r
+ This parameter can be a value of @ref TIM_Output_Compare_and_PWM_modes */\r
+\r
+ uint32_t Pulse; /*!< Specifies the pulse value to be loaded into the Capture Compare Register.\r
+ This parameter can be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF */\r
+\r
+ uint32_t OCPolarity; /*!< Specifies the output polarity.\r
+ This parameter can be a value of @ref TIM_Output_Compare_Polarity */\r
+\r
+ uint32_t OCFastMode; /*!< Specifies the Fast mode state.\r
+ This parameter can be a value of @ref TIM_Output_Fast_State\r
+ @note This parameter is valid only in PWM1 and PWM2 mode. */\r
+} TIM_OC_InitTypeDef;\r
+\r
+/**\r
+ * @brief TIM One Pulse Mode Configuration Structure definition\r
+ */\r
+typedef struct\r
+{\r
+ uint32_t OCMode; /*!< Specifies the TIM mode.\r
+ This parameter can be a value of @ref TIM_Output_Compare_and_PWM_modes */\r
+\r
+ uint32_t Pulse; /*!< Specifies the pulse value to be loaded into the Capture Compare Register.\r
+ This parameter can be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF */\r
+\r
+ uint32_t OCPolarity; /*!< Specifies the output polarity.\r
+ This parameter can be a value of @ref TIM_Output_Compare_Polarity */\r
+\r
+ uint32_t ICPolarity; /*!< Specifies the active edge of the input signal.\r
+ This parameter can be a value of @ref TIM_Input_Capture_Polarity */\r
+\r
+ uint32_t ICSelection; /*!< Specifies the input.\r
+ This parameter can be a value of @ref TIM_Input_Capture_Selection */\r
+\r
+ uint32_t ICFilter; /*!< Specifies the input capture filter.\r
+ This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */\r
+} TIM_OnePulse_InitTypeDef;\r
+\r
+/**\r
+ * @brief TIM Input Capture Configuration Structure definition\r
+ */\r
+typedef struct\r
+{\r
+ uint32_t ICPolarity; /*!< Specifies the active edge of the input signal.\r
+ This parameter can be a value of @ref TIM_Input_Capture_Polarity */\r
+\r
+ uint32_t ICSelection; /*!< Specifies the input.\r
+ This parameter can be a value of @ref TIM_Input_Capture_Selection */\r
+\r
+ uint32_t ICPrescaler; /*!< Specifies the Input Capture Prescaler.\r
+ This parameter can be a value of @ref TIM_Input_Capture_Prescaler */\r
+\r
+ uint32_t ICFilter; /*!< Specifies the input capture filter.\r
+ This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */\r
+} TIM_IC_InitTypeDef;\r
+\r
+/**\r
+ * @brief TIM Encoder Configuration Structure definition\r
+ */\r
+typedef struct\r
+{\r
+ uint32_t EncoderMode; /*!< Specifies the active edge of the input signal.\r
+ This parameter can be a value of @ref TIM_Encoder_Mode */\r
+\r
+ uint32_t IC1Polarity; /*!< Specifies the active edge of the input signal.\r
+ This parameter can be a value of @ref TIM_Input_Capture_Polarity */\r
+\r
+ uint32_t IC1Selection; /*!< Specifies the input.\r
+ This parameter can be a value of @ref TIM_Input_Capture_Selection */\r
+\r
+ uint32_t IC1Prescaler; /*!< Specifies the Input Capture Prescaler.\r
+ This parameter can be a value of @ref TIM_Input_Capture_Prescaler */\r
+\r
+ uint32_t IC1Filter; /*!< Specifies the input capture filter.\r
+ This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */\r
+\r
+ uint32_t IC2Polarity; /*!< Specifies the active edge of the input signal.\r
+ This parameter can be a value of @ref TIM_Input_Capture_Polarity */\r
+\r
+ uint32_t IC2Selection; /*!< Specifies the input.\r
+ This parameter can be a value of @ref TIM_Input_Capture_Selection */\r
+\r
+ uint32_t IC2Prescaler; /*!< Specifies the Input Capture Prescaler.\r
+ This parameter can be a value of @ref TIM_Input_Capture_Prescaler */\r
+\r
+ uint32_t IC2Filter; /*!< Specifies the input capture filter.\r
+ This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */\r
+} TIM_Encoder_InitTypeDef;\r
+\r
+/**\r
+ * @brief Clock Configuration Handle Structure definition\r
+ */\r
+typedef struct\r
+{\r
+ uint32_t ClockSource; /*!< TIM clock sources\r
+ This parameter can be a value of @ref TIM_Clock_Source */\r
+ uint32_t ClockPolarity; /*!< TIM clock polarity\r
+ This parameter can be a value of @ref TIM_Clock_Polarity */\r
+ uint32_t ClockPrescaler; /*!< TIM clock prescaler\r
+ This parameter can be a value of @ref TIM_Clock_Prescaler */\r
+ uint32_t ClockFilter; /*!< TIM clock filter\r
+ This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */\r
+} TIM_ClockConfigTypeDef;\r
+\r
+/**\r
+ * @brief TIM Clear Input Configuration Handle Structure definition\r
+ */\r
+typedef struct\r
+{\r
+ uint32_t ClearInputState; /*!< TIM clear Input state\r
+ This parameter can be ENABLE or DISABLE */\r
+ uint32_t ClearInputSource; /*!< TIM clear Input sources\r
+ This parameter can be a value of @ref TIM_ClearInput_Source */\r
+ uint32_t ClearInputPolarity; /*!< TIM Clear Input polarity\r
+ This parameter can be a value of @ref TIM_ClearInput_Polarity */\r
+ uint32_t ClearInputPrescaler; /*!< TIM Clear Input prescaler\r
+ This parameter must be 0: When OCRef clear feature is used with ETR source, ETR prescaler must be off */\r
+ uint32_t ClearInputFilter; /*!< TIM Clear Input filter\r
+ This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */\r
+} TIM_ClearInputConfigTypeDef;\r
+\r
+/**\r
+ * @brief TIM Master configuration Structure definition\r
+ */\r
+typedef struct\r
+{\r
+ uint32_t MasterOutputTrigger; /*!< Trigger output (TRGO) selection\r
+ This parameter can be a value of @ref TIM_Master_Mode_Selection */\r
+ uint32_t MasterSlaveMode; /*!< Master/slave mode selection\r
+ This parameter can be a value of @ref TIM_Master_Slave_Mode */\r
+} TIM_MasterConfigTypeDef;\r
+\r
+/**\r
+ * @brief TIM Slave configuration Structure definition\r
+ */\r
+typedef struct\r
+{\r
+ uint32_t SlaveMode; /*!< Slave mode selection\r
+ This parameter can be a value of @ref TIM_Slave_Mode */\r
+ uint32_t InputTrigger; /*!< Input Trigger source\r
+ This parameter can be a value of @ref TIM_Trigger_Selection */\r
+ uint32_t TriggerPolarity; /*!< Input Trigger polarity\r
+ This parameter can be a value of @ref TIM_Trigger_Polarity */\r
+ uint32_t TriggerPrescaler; /*!< Input trigger prescaler\r
+ This parameter can be a value of @ref TIM_Trigger_Prescaler */\r
+ uint32_t TriggerFilter; /*!< Input trigger filter\r
+ This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */\r
+\r
+} TIM_SlaveConfigTypeDef;\r
+\r
+/**\r
+ * @brief HAL State structures definition\r
+ */\r
+typedef enum\r
+{\r
+ HAL_TIM_STATE_RESET = 0x00U, /*!< Peripheral not yet initialized or disabled */\r
+ HAL_TIM_STATE_READY = 0x01U, /*!< Peripheral Initialized and ready for use */\r
+ HAL_TIM_STATE_BUSY = 0x02U, /*!< An internal process is ongoing */\r
+ HAL_TIM_STATE_TIMEOUT = 0x03U, /*!< Timeout state */\r
+ HAL_TIM_STATE_ERROR = 0x04U /*!< Reception process is ongoing */\r
+} HAL_TIM_StateTypeDef;\r
+\r
+/**\r
+ * @brief HAL Active channel structures definition\r
+ */\r
+typedef enum\r
+{\r
+ HAL_TIM_ACTIVE_CHANNEL_1 = 0x01U, /*!< The active channel is 1 */\r
+ HAL_TIM_ACTIVE_CHANNEL_2 = 0x02U, /*!< The active channel is 2 */\r
+ HAL_TIM_ACTIVE_CHANNEL_3 = 0x04U, /*!< The active channel is 3 */\r
+ HAL_TIM_ACTIVE_CHANNEL_4 = 0x08U, /*!< The active channel is 4 */\r
+ HAL_TIM_ACTIVE_CHANNEL_CLEARED = 0x00U /*!< All active channels cleared */\r
+} HAL_TIM_ActiveChannel;\r
+\r
+/**\r
+ * @brief TIM Time Base Handle Structure definition\r
+ */\r
+#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)\r
+typedef struct __TIM_HandleTypeDef\r
+#else\r
+typedef struct\r
+#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */\r
+{\r
+ TIM_TypeDef *Instance; /*!< Register base address */\r
+ TIM_Base_InitTypeDef Init; /*!< TIM Time Base required parameters */\r
+ HAL_TIM_ActiveChannel Channel; /*!< Active channel */\r
+ DMA_HandleTypeDef *hdma[7]; /*!< DMA Handlers array\r
+ This array is accessed by a @ref DMA_Handle_index */\r
+ HAL_LockTypeDef Lock; /*!< Locking object */\r
+ __IO HAL_TIM_StateTypeDef State; /*!< TIM operation state */\r
+\r
+#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)\r
+ void (* Base_MspInitCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Base Msp Init Callback */\r
+ void (* Base_MspDeInitCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Base Msp DeInit Callback */\r
+ void (* IC_MspInitCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM IC Msp Init Callback */\r
+ void (* IC_MspDeInitCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM IC Msp DeInit Callback */\r
+ void (* OC_MspInitCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM OC Msp Init Callback */\r
+ void (* OC_MspDeInitCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM OC Msp DeInit Callback */\r
+ void (* PWM_MspInitCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM PWM Msp Init Callback */\r
+ void (* PWM_MspDeInitCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM PWM Msp DeInit Callback */\r
+ void (* OnePulse_MspInitCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM One Pulse Msp Init Callback */\r
+ void (* OnePulse_MspDeInitCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM One Pulse Msp DeInit Callback */\r
+ void (* Encoder_MspInitCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Encoder Msp Init Callback */\r
+ void (* Encoder_MspDeInitCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Encoder Msp DeInit Callback */\r
+ void (* PeriodElapsedCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Period Elapsed Callback */\r
+ void (* PeriodElapsedHalfCpltCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Period Elapsed half complete Callback */\r
+ void (* TriggerCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Trigger Callback */\r
+ void (* TriggerHalfCpltCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Trigger half complete Callback */\r
+ void (* IC_CaptureCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Input Capture Callback */\r
+ void (* IC_CaptureHalfCpltCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Input Capture half complete Callback */\r
+ void (* OC_DelayElapsedCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Output Compare Delay Elapsed Callback */\r
+ void (* PWM_PulseFinishedCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM PWM Pulse Finished Callback */\r
+ void (* PWM_PulseFinishedHalfCpltCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM PWM Pulse Finished half complete Callback */\r
+ void (* ErrorCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Error Callback */\r
+#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */\r
+} TIM_HandleTypeDef;\r
+\r
+#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)\r
+/**\r
+ * @brief HAL TIM Callback ID enumeration definition\r
+ */\r
+typedef enum\r
+{\r
+ HAL_TIM_BASE_MSPINIT_CB_ID = 0x00U /*!< TIM Base MspInit Callback ID */\r
+ ,HAL_TIM_BASE_MSPDEINIT_CB_ID = 0x01U /*!< TIM Base MspDeInit Callback ID */\r
+ ,HAL_TIM_IC_MSPINIT_CB_ID = 0x02U /*!< TIM IC MspInit Callback ID */\r
+ ,HAL_TIM_IC_MSPDEINIT_CB_ID = 0x03U /*!< TIM IC MspDeInit Callback ID */\r
+ ,HAL_TIM_OC_MSPINIT_CB_ID = 0x04U /*!< TIM OC MspInit Callback ID */\r
+ ,HAL_TIM_OC_MSPDEINIT_CB_ID = 0x05U /*!< TIM OC MspDeInit Callback ID */\r
+ ,HAL_TIM_PWM_MSPINIT_CB_ID = 0x06U /*!< TIM PWM MspInit Callback ID */\r
+ ,HAL_TIM_PWM_MSPDEINIT_CB_ID = 0x07U /*!< TIM PWM MspDeInit Callback ID */\r
+ ,HAL_TIM_ONE_PULSE_MSPINIT_CB_ID = 0x08U /*!< TIM One Pulse MspInit Callback ID */\r
+ ,HAL_TIM_ONE_PULSE_MSPDEINIT_CB_ID = 0x09U /*!< TIM One Pulse MspDeInit Callback ID */\r
+ ,HAL_TIM_ENCODER_MSPINIT_CB_ID = 0x0AU /*!< TIM Encoder MspInit Callback ID */\r
+ ,HAL_TIM_ENCODER_MSPDEINIT_CB_ID = 0x0BU /*!< TIM Encoder MspDeInit Callback ID */\r
+ ,HAL_TIM_PERIOD_ELAPSED_CB_ID = 0x0EU /*!< TIM Period Elapsed Callback ID */\r
+ ,HAL_TIM_PERIOD_ELAPSED_HALF_CB_ID = 0x0FU /*!< TIM Period Elapsed half complete Callback ID */\r
+ ,HAL_TIM_TRIGGER_CB_ID = 0x10U /*!< TIM Trigger Callback ID */\r
+ ,HAL_TIM_TRIGGER_HALF_CB_ID = 0x11U /*!< TIM Trigger half complete Callback ID */\r
+\r
+ ,HAL_TIM_IC_CAPTURE_CB_ID = 0x12U /*!< TIM Input Capture Callback ID */\r
+ ,HAL_TIM_IC_CAPTURE_HALF_CB_ID = 0x13U /*!< TIM Input Capture half complete Callback ID */\r
+ ,HAL_TIM_OC_DELAY_ELAPSED_CB_ID = 0x14U /*!< TIM Output Compare Delay Elapsed Callback ID */\r
+ ,HAL_TIM_PWM_PULSE_FINISHED_CB_ID = 0x15U /*!< TIM PWM Pulse Finished Callback ID */\r
+ ,HAL_TIM_PWM_PULSE_FINISHED_HALF_CB_ID = 0x16U /*!< TIM PWM Pulse Finished half complete Callback ID */\r
+ ,HAL_TIM_ERROR_CB_ID = 0x17U /*!< TIM Error Callback ID */\r
+} HAL_TIM_CallbackIDTypeDef;\r
+\r
+/**\r
+ * @brief HAL TIM Callback pointer definition\r
+ */\r
+typedef void (*pTIM_CallbackTypeDef)(TIM_HandleTypeDef *htim); /*!< pointer to the TIM callback function */\r
+\r
+#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */\r
+\r
+/**\r
+ * @}\r
+ */\r
+/* End of exported types -----------------------------------------------------*/\r
+\r
+/* Exported constants --------------------------------------------------------*/\r
+/** @defgroup TIM_Exported_Constants TIM Exported Constants\r
+ * @{\r
+ */\r
+\r
+/** @defgroup TIM_ClearInput_Source TIM Clear Input Source\r
+ * @{\r
+ */\r
+#define TIM_CLEARINPUTSOURCE_NONE 0x00000000U /*!< OCREF_CLR is disabled */\r
+#define TIM_CLEARINPUTSOURCE_ETR 0x00000001U /*!< OCREF_CLR is connected to ETRF input */\r
+#define TIM_CLEARINPUTSOURCE_OCREFCLR 0x00000002U /*!< OCREF_CLR is connected to OCREF_CLR_INT */\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup TIM_DMA_Base_address TIM DMA Base Address\r
+ * @{\r
+ */\r
+#define TIM_DMABASE_CR1 0x00000000U\r
+#define TIM_DMABASE_CR2 0x00000001U\r
+#define TIM_DMABASE_SMCR 0x00000002U\r
+#define TIM_DMABASE_DIER 0x00000003U\r
+#define TIM_DMABASE_SR 0x00000004U\r
+#define TIM_DMABASE_EGR 0x00000005U\r
+#define TIM_DMABASE_CCMR1 0x00000006U\r
+#define TIM_DMABASE_CCMR2 0x00000007U\r
+#define TIM_DMABASE_CCER 0x00000008U\r
+#define TIM_DMABASE_CNT 0x00000009U\r
+#define TIM_DMABASE_PSC 0x0000000AU\r
+#define TIM_DMABASE_ARR 0x0000000BU\r
+#define TIM_DMABASE_CCR1 0x0000000DU\r
+#define TIM_DMABASE_CCR2 0x0000000EU\r
+#define TIM_DMABASE_CCR3 0x0000000FU\r
+#define TIM_DMABASE_CCR4 0x00000010U\r
+#define TIM_DMABASE_DCR 0x00000012U\r
+#define TIM_DMABASE_DMAR 0x00000013U\r
+#define TIM_DMABASE_OR 0x00000014U\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup TIM_Event_Source TIM Event Source\r
+ * @{\r
+ */\r
+#define TIM_EVENTSOURCE_UPDATE TIM_EGR_UG /*!< Reinitialize the counter and generates an update of the registers */\r
+#define TIM_EVENTSOURCE_CC1 TIM_EGR_CC1G /*!< A capture/compare event is generated on channel 1 */\r
+#define TIM_EVENTSOURCE_CC2 TIM_EGR_CC2G /*!< A capture/compare event is generated on channel 2 */\r
+#define TIM_EVENTSOURCE_CC3 TIM_EGR_CC3G /*!< A capture/compare event is generated on channel 3 */\r
+#define TIM_EVENTSOURCE_CC4 TIM_EGR_CC4G /*!< A capture/compare event is generated on channel 4 */\r
+#define TIM_EVENTSOURCE_TRIGGER TIM_EGR_TG /*!< A trigger event is generated */\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup TIM_Input_Channel_Polarity TIM Input Channel polarity\r
+ * @{\r
+ */\r
+#define TIM_INPUTCHANNELPOLARITY_RISING 0x00000000U /*!< Polarity for TIx source */\r
+#define TIM_INPUTCHANNELPOLARITY_FALLING TIM_CCER_CC1P /*!< Polarity for TIx source */\r
+#define TIM_INPUTCHANNELPOLARITY_BOTHEDGE (TIM_CCER_CC1P | TIM_CCER_CC1NP) /*!< Polarity for TIx source */\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup TIM_ETR_Polarity TIM ETR Polarity\r
+ * @{\r
+ */\r
+#define TIM_ETRPOLARITY_INVERTED TIM_SMCR_ETP /*!< Polarity for ETR source */\r
+#define TIM_ETRPOLARITY_NONINVERTED 0x00000000U /*!< Polarity for ETR source */\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup TIM_ETR_Prescaler TIM ETR Prescaler\r
+ * @{\r
+ */\r
+#define TIM_ETRPRESCALER_DIV1 0x00000000U /*!< No prescaler is used */\r
+#define TIM_ETRPRESCALER_DIV2 TIM_SMCR_ETPS_0 /*!< ETR input source is divided by 2 */\r
+#define TIM_ETRPRESCALER_DIV4 TIM_SMCR_ETPS_1 /*!< ETR input source is divided by 4 */\r
+#define TIM_ETRPRESCALER_DIV8 TIM_SMCR_ETPS /*!< ETR input source is divided by 8 */\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup TIM_Counter_Mode TIM Counter Mode\r
+ * @{\r
+ */\r
+#define TIM_COUNTERMODE_UP 0x00000000U /*!< Counter used as up-counter */\r
+#define TIM_COUNTERMODE_DOWN TIM_CR1_DIR /*!< Counter used as down-counter */\r
+#define TIM_COUNTERMODE_CENTERALIGNED1 TIM_CR1_CMS_0 /*!< Center-aligned mode 1 */\r
+#define TIM_COUNTERMODE_CENTERALIGNED2 TIM_CR1_CMS_1 /*!< Center-aligned mode 2 */\r
+#define TIM_COUNTERMODE_CENTERALIGNED3 TIM_CR1_CMS /*!< Center-aligned mode 3 */\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup TIM_ClockDivision TIM Clock Division\r
+ * @{\r
+ */\r
+#define TIM_CLOCKDIVISION_DIV1 0x00000000U /*!< Clock division: tDTS=tCK_INT */\r
+#define TIM_CLOCKDIVISION_DIV2 TIM_CR1_CKD_0 /*!< Clock division: tDTS=2*tCK_INT */\r
+#define TIM_CLOCKDIVISION_DIV4 TIM_CR1_CKD_1 /*!< Clock division: tDTS=4*tCK_INT */\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup TIM_Output_Compare_State TIM Output Compare State\r
+ * @{\r
+ */\r
+#define TIM_OUTPUTSTATE_DISABLE 0x00000000U /*!< Capture/Compare 1 output disabled */\r
+#define TIM_OUTPUTSTATE_ENABLE TIM_CCER_CC1E /*!< Capture/Compare 1 output enabled */\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup TIM_AutoReloadPreload TIM Auto-Reload Preload\r
+ * @{\r
+ */\r
+#define TIM_AUTORELOAD_PRELOAD_DISABLE 0x00000000U /*!< TIMx_ARR register is not buffered */\r
+#define TIM_AUTORELOAD_PRELOAD_ENABLE TIM_CR1_ARPE /*!< TIMx_ARR register is buffered */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup TIM_Output_Fast_State TIM Output Fast State\r
+ * @{\r
+ */\r
+#define TIM_OCFAST_DISABLE 0x00000000U /*!< Output Compare fast disable */\r
+#define TIM_OCFAST_ENABLE TIM_CCMR1_OC1FE /*!< Output Compare fast enable */\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup TIM_Output_Compare_N_State TIM Complementary Output Compare State\r
+ * @{\r
+ */\r
+#define TIM_OUTPUTNSTATE_DISABLE 0x00000000U /*!< OCxN is disabled */\r
+#define TIM_OUTPUTNSTATE_ENABLE TIM_CCER_CC1NE /*!< OCxN is enabled */\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup TIM_Output_Compare_Polarity TIM Output Compare Polarity\r
+ * @{\r
+ */\r
+#define TIM_OCPOLARITY_HIGH 0x00000000U /*!< Capture/Compare output polarity */\r
+#define TIM_OCPOLARITY_LOW TIM_CCER_CC1P /*!< Capture/Compare output polarity */\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup TIM_Input_Capture_Polarity TIM Input Capture Polarity\r
+ * @{\r
+ */\r
+#define TIM_ICPOLARITY_RISING TIM_INPUTCHANNELPOLARITY_RISING /*!< Capture triggered by rising edge on timer input */\r
+#define TIM_ICPOLARITY_FALLING TIM_INPUTCHANNELPOLARITY_FALLING /*!< Capture triggered by falling edge on timer input */\r
+#define TIM_ICPOLARITY_BOTHEDGE TIM_INPUTCHANNELPOLARITY_BOTHEDGE /*!< Capture triggered by both rising and falling edges on timer input*/\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup TIM_Input_Capture_Selection TIM Input Capture Selection\r
+ * @{\r
+ */\r
+#define TIM_ICSELECTION_DIRECTTI TIM_CCMR1_CC1S_0 /*!< TIM Input 1, 2, 3 or 4 is selected to be\r
+ connected to IC1, IC2, IC3 or IC4, respectively */\r
+#define TIM_ICSELECTION_INDIRECTTI TIM_CCMR1_CC1S_1 /*!< TIM Input 1, 2, 3 or 4 is selected to be\r
+ connected to IC2, IC1, IC4 or IC3, respectively */\r
+#define TIM_ICSELECTION_TRC TIM_CCMR1_CC1S /*!< TIM Input 1, 2, 3 or 4 is selected to be connected to TRC */\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup TIM_Input_Capture_Prescaler TIM Input Capture Prescaler\r
+ * @{\r
+ */\r
+#define TIM_ICPSC_DIV1 0x00000000U /*!< Capture performed each time an edge is detected on the capture input */\r
+#define TIM_ICPSC_DIV2 TIM_CCMR1_IC1PSC_0 /*!< Capture performed once every 2 events */\r
+#define TIM_ICPSC_DIV4 TIM_CCMR1_IC1PSC_1 /*!< Capture performed once every 4 events */\r
+#define TIM_ICPSC_DIV8 TIM_CCMR1_IC1PSC /*!< Capture performed once every 8 events */\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup TIM_One_Pulse_Mode TIM One Pulse Mode\r
+ * @{\r
+ */\r
+#define TIM_OPMODE_SINGLE TIM_CR1_OPM /*!< Counter stops counting at the next update event */\r
+#define TIM_OPMODE_REPETITIVE 0x00000000U /*!< Counter is not stopped at update event */\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup TIM_Encoder_Mode TIM Encoder Mode\r
+ * @{\r
+ */\r
+#define TIM_ENCODERMODE_TI1 TIM_SMCR_SMS_0 /*!< Quadrature encoder mode 1, x2 mode, counts up/down on TI1FP1 edge depending on TI2FP2 level */\r
+#define TIM_ENCODERMODE_TI2 TIM_SMCR_SMS_1 /*!< Quadrature encoder mode 2, x2 mode, counts up/down on TI2FP2 edge depending on TI1FP1 level. */\r
+#define TIM_ENCODERMODE_TI12 (TIM_SMCR_SMS_1 | TIM_SMCR_SMS_0) /*!< Quadrature encoder mode 3, x4 mode, counts up/down on both TI1FP1 and TI2FP2 edges depending on the level of the other input. */\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup TIM_Interrupt_definition TIM interrupt Definition\r
+ * @{\r
+ */\r
+#define TIM_IT_UPDATE TIM_DIER_UIE /*!< Update interrupt */\r
+#define TIM_IT_CC1 TIM_DIER_CC1IE /*!< Capture/Compare 1 interrupt */\r
+#define TIM_IT_CC2 TIM_DIER_CC2IE /*!< Capture/Compare 2 interrupt */\r
+#define TIM_IT_CC3 TIM_DIER_CC3IE /*!< Capture/Compare 3 interrupt */\r
+#define TIM_IT_CC4 TIM_DIER_CC4IE /*!< Capture/Compare 4 interrupt */\r
+#define TIM_IT_TRIGGER TIM_DIER_TIE /*!< Trigger interrupt */\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup TIM_DMA_sources TIM DMA Sources\r
+ * @{\r
+ */\r
+#define TIM_DMA_UPDATE TIM_DIER_UDE /*!< DMA request is triggered by the update event */\r
+#define TIM_DMA_CC1 TIM_DIER_CC1DE /*!< DMA request is triggered by the capture/compare macth 1 event */\r
+#define TIM_DMA_CC2 TIM_DIER_CC2DE /*!< DMA request is triggered by the capture/compare macth 2 event event */\r
+#define TIM_DMA_CC3 TIM_DIER_CC3DE /*!< DMA request is triggered by the capture/compare macth 3 event event */\r
+#define TIM_DMA_CC4 TIM_DIER_CC4DE /*!< DMA request is triggered by the capture/compare macth 4 event event */\r
+#define TIM_DMA_TRIGGER TIM_DIER_TDE /*!< DMA request is triggered by the trigger event */\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup TIM_Flag_definition TIM Flag Definition\r
+ * @{\r
+ */\r
+#define TIM_FLAG_UPDATE TIM_SR_UIF /*!< Update interrupt flag */\r
+#define TIM_FLAG_CC1 TIM_SR_CC1IF /*!< Capture/Compare 1 interrupt flag */\r
+#define TIM_FLAG_CC2 TIM_SR_CC2IF /*!< Capture/Compare 2 interrupt flag */\r
+#define TIM_FLAG_CC3 TIM_SR_CC3IF /*!< Capture/Compare 3 interrupt flag */\r
+#define TIM_FLAG_CC4 TIM_SR_CC4IF /*!< Capture/Compare 4 interrupt flag */\r
+#define TIM_FLAG_TRIGGER TIM_SR_TIF /*!< Trigger interrupt flag */\r
+#define TIM_FLAG_CC1OF TIM_SR_CC1OF /*!< Capture 1 overcapture flag */\r
+#define TIM_FLAG_CC2OF TIM_SR_CC2OF /*!< Capture 2 overcapture flag */\r
+#define TIM_FLAG_CC3OF TIM_SR_CC3OF /*!< Capture 3 overcapture flag */\r
+#define TIM_FLAG_CC4OF TIM_SR_CC4OF /*!< Capture 4 overcapture flag */\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup TIM_Channel TIM Channel\r
+ * @{\r
+ */\r
+#define TIM_CHANNEL_1 0x00000000U /*!< Capture/compare channel 1 identifier */\r
+#define TIM_CHANNEL_2 0x00000004U /*!< Capture/compare channel 2 identifier */\r
+#define TIM_CHANNEL_3 0x00000008U /*!< Capture/compare channel 3 identifier */\r
+#define TIM_CHANNEL_4 0x0000000CU /*!< Capture/compare channel 4 identifier */\r
+#define TIM_CHANNEL_ALL 0x0000003CU /*!< Global Capture/compare channel identifier */\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup TIM_Clock_Source TIM Clock Source\r
+ * @{\r
+ */\r
+#define TIM_CLOCKSOURCE_ETRMODE2 TIM_SMCR_ETPS_1 /*!< External clock source mode 2 */\r
+#define TIM_CLOCKSOURCE_INTERNAL TIM_SMCR_ETPS_0 /*!< Internal clock source */\r
+#define TIM_CLOCKSOURCE_ITR0 TIM_TS_ITR0 /*!< External clock source mode 1 (ITR0) */\r
+#define TIM_CLOCKSOURCE_ITR1 TIM_TS_ITR1 /*!< External clock source mode 1 (ITR1) */\r
+#define TIM_CLOCKSOURCE_ITR2 TIM_TS_ITR2 /*!< External clock source mode 1 (ITR2) */\r
+#define TIM_CLOCKSOURCE_ITR3 TIM_TS_ITR3 /*!< External clock source mode 1 (ITR3) */\r
+#define TIM_CLOCKSOURCE_TI1ED TIM_TS_TI1F_ED /*!< External clock source mode 1 (TTI1FP1 + edge detect.) */\r
+#define TIM_CLOCKSOURCE_TI1 TIM_TS_TI1FP1 /*!< External clock source mode 1 (TTI1FP1) */\r
+#define TIM_CLOCKSOURCE_TI2 TIM_TS_TI2FP2 /*!< External clock source mode 1 (TTI2FP2) */\r
+#define TIM_CLOCKSOURCE_ETRMODE1 TIM_TS_ETRF /*!< External clock source mode 1 (ETRF) */\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup TIM_Clock_Polarity TIM Clock Polarity\r
+ * @{\r
+ */\r
+#define TIM_CLOCKPOLARITY_INVERTED TIM_ETRPOLARITY_INVERTED /*!< Polarity for ETRx clock sources */\r
+#define TIM_CLOCKPOLARITY_NONINVERTED TIM_ETRPOLARITY_NONINVERTED /*!< Polarity for ETRx clock sources */\r
+#define TIM_CLOCKPOLARITY_RISING TIM_INPUTCHANNELPOLARITY_RISING /*!< Polarity for TIx clock sources */\r
+#define TIM_CLOCKPOLARITY_FALLING TIM_INPUTCHANNELPOLARITY_FALLING /*!< Polarity for TIx clock sources */\r
+#define TIM_CLOCKPOLARITY_BOTHEDGE TIM_INPUTCHANNELPOLARITY_BOTHEDGE /*!< Polarity for TIx clock sources */\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup TIM_Clock_Prescaler TIM Clock Prescaler\r
+ * @{\r
+ */\r
+#define TIM_CLOCKPRESCALER_DIV1 TIM_ETRPRESCALER_DIV1 /*!< No prescaler is used */\r
+#define TIM_CLOCKPRESCALER_DIV2 TIM_ETRPRESCALER_DIV2 /*!< Prescaler for External ETR Clock: Capture performed once every 2 events. */\r
+#define TIM_CLOCKPRESCALER_DIV4 TIM_ETRPRESCALER_DIV4 /*!< Prescaler for External ETR Clock: Capture performed once every 4 events. */\r
+#define TIM_CLOCKPRESCALER_DIV8 TIM_ETRPRESCALER_DIV8 /*!< Prescaler for External ETR Clock: Capture performed once every 8 events. */\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup TIM_ClearInput_Polarity TIM Clear Input Polarity\r
+ * @{\r
+ */\r
+#define TIM_CLEARINPUTPOLARITY_INVERTED TIM_ETRPOLARITY_INVERTED /*!< Polarity for ETRx pin */\r
+#define TIM_CLEARINPUTPOLARITY_NONINVERTED TIM_ETRPOLARITY_NONINVERTED /*!< Polarity for ETRx pin */\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup TIM_ClearInput_Prescaler TIM Clear Input Prescaler\r
+ * @{\r
+ */\r
+#define TIM_CLEARINPUTPRESCALER_DIV1 TIM_ETRPRESCALER_DIV1 /*!< No prescaler is used */\r
+#define TIM_CLEARINPUTPRESCALER_DIV2 TIM_ETRPRESCALER_DIV2 /*!< Prescaler for External ETR pin: Capture performed once every 2 events. */\r
+#define TIM_CLEARINPUTPRESCALER_DIV4 TIM_ETRPRESCALER_DIV4 /*!< Prescaler for External ETR pin: Capture performed once every 4 events. */\r
+#define TIM_CLEARINPUTPRESCALER_DIV8 TIM_ETRPRESCALER_DIV8 /*!< Prescaler for External ETR pin: Capture performed once every 8 events. */\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup TIM_Master_Mode_Selection TIM Master Mode Selection\r
+ * @{\r
+ */\r
+#define TIM_TRGO_RESET 0x00000000U /*!< TIMx_EGR.UG bit is used as trigger output (TRGO) */\r
+#define TIM_TRGO_ENABLE TIM_CR2_MMS_0 /*!< TIMx_CR1.CEN bit is used as trigger output (TRGO) */\r
+#define TIM_TRGO_UPDATE TIM_CR2_MMS_1 /*!< Update event is used as trigger output (TRGO) */\r
+#define TIM_TRGO_OC1 (TIM_CR2_MMS_1 | TIM_CR2_MMS_0) /*!< Capture or a compare match 1 is used as trigger output (TRGO) */\r
+#define TIM_TRGO_OC1REF TIM_CR2_MMS_2 /*!< OC1REF signal is used as trigger output (TRGO) */\r
+#define TIM_TRGO_OC2REF (TIM_CR2_MMS_2 | TIM_CR2_MMS_0) /*!< OC2REF signal is used as trigger output(TRGO) */\r
+#define TIM_TRGO_OC3REF (TIM_CR2_MMS_2 | TIM_CR2_MMS_1) /*!< OC3REF signal is used as trigger output(TRGO) */\r
+#define TIM_TRGO_OC4REF (TIM_CR2_MMS_2 | TIM_CR2_MMS_1 | TIM_CR2_MMS_0) /*!< OC4REF signal is used as trigger output(TRGO) */\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup TIM_Master_Slave_Mode TIM Master/Slave Mode\r
+ * @{\r
+ */\r
+#define TIM_MASTERSLAVEMODE_ENABLE TIM_SMCR_MSM /*!< No action */\r
+#define TIM_MASTERSLAVEMODE_DISABLE 0x00000000U /*!< Master/slave mode is selected */\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup TIM_Slave_Mode TIM Slave mode\r
+ * @{\r
+ */\r
+#define TIM_SLAVEMODE_DISABLE 0x00000000U /*!< Slave mode disabled */\r
+#define TIM_SLAVEMODE_RESET TIM_SMCR_SMS_2 /*!< Reset Mode */\r
+#define TIM_SLAVEMODE_GATED (TIM_SMCR_SMS_2 | TIM_SMCR_SMS_0) /*!< Gated Mode */\r
+#define TIM_SLAVEMODE_TRIGGER (TIM_SMCR_SMS_2 | TIM_SMCR_SMS_1) /*!< Trigger Mode */\r
+#define TIM_SLAVEMODE_EXTERNAL1 (TIM_SMCR_SMS_2 | TIM_SMCR_SMS_1 | TIM_SMCR_SMS_0) /*!< External Clock Mode 1 */\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup TIM_Output_Compare_and_PWM_modes TIM Output Compare and PWM Modes\r
+ * @{\r
+ */\r
+#define TIM_OCMODE_TIMING 0x00000000U /*!< Frozen */\r
+#define TIM_OCMODE_ACTIVE TIM_CCMR1_OC1M_0 /*!< Set channel to active level on match */\r
+#define TIM_OCMODE_INACTIVE TIM_CCMR1_OC1M_1 /*!< Set channel to inactive level on match */\r
+#define TIM_OCMODE_TOGGLE (TIM_CCMR1_OC1M_1 | TIM_CCMR1_OC1M_0) /*!< Toggle */\r
+#define TIM_OCMODE_PWM1 (TIM_CCMR1_OC1M_2 | TIM_CCMR1_OC1M_1) /*!< PWM mode 1 */\r
+#define TIM_OCMODE_PWM2 (TIM_CCMR1_OC1M_2 | TIM_CCMR1_OC1M_1 | TIM_CCMR1_OC1M_0) /*!< PWM mode 2 */\r
+#define TIM_OCMODE_FORCED_ACTIVE (TIM_CCMR1_OC1M_2 | TIM_CCMR1_OC1M_0) /*!< Force active level */\r
+#define TIM_OCMODE_FORCED_INACTIVE TIM_CCMR1_OC1M_2 /*!< Force inactive level */\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup TIM_Trigger_Selection TIM Trigger Selection\r
+ * @{\r
+ */\r
+#define TIM_TS_ITR0 0x00000000U /*!< Internal Trigger 0 (ITR0) */\r
+#define TIM_TS_ITR1 TIM_SMCR_TS_0 /*!< Internal Trigger 1 (ITR1) */\r
+#define TIM_TS_ITR2 TIM_SMCR_TS_1 /*!< Internal Trigger 2 (ITR2) */\r
+#define TIM_TS_ITR3 (TIM_SMCR_TS_0 | TIM_SMCR_TS_1) /*!< Internal Trigger 3 (ITR3) */\r
+#define TIM_TS_TI1F_ED TIM_SMCR_TS_2 /*!< TI1 Edge Detector (TI1F_ED) */\r
+#define TIM_TS_TI1FP1 (TIM_SMCR_TS_0 | TIM_SMCR_TS_2) /*!< Filtered Timer Input 1 (TI1FP1) */\r
+#define TIM_TS_TI2FP2 (TIM_SMCR_TS_1 | TIM_SMCR_TS_2) /*!< Filtered Timer Input 2 (TI2FP2) */\r
+#define TIM_TS_ETRF (TIM_SMCR_TS_0 | TIM_SMCR_TS_1 | TIM_SMCR_TS_2) /*!< Filtered External Trigger input (ETRF) */\r
+#define TIM_TS_NONE 0x0000FFFFU /*!< No trigger selected */\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup TIM_Trigger_Polarity TIM Trigger Polarity\r
+ * @{\r
+ */\r
+#define TIM_TRIGGERPOLARITY_INVERTED TIM_ETRPOLARITY_INVERTED /*!< Polarity for ETRx trigger sources */\r
+#define TIM_TRIGGERPOLARITY_NONINVERTED TIM_ETRPOLARITY_NONINVERTED /*!< Polarity for ETRx trigger sources */\r
+#define TIM_TRIGGERPOLARITY_RISING TIM_INPUTCHANNELPOLARITY_RISING /*!< Polarity for TIxFPx or TI1_ED trigger sources */\r
+#define TIM_TRIGGERPOLARITY_FALLING TIM_INPUTCHANNELPOLARITY_FALLING /*!< Polarity for TIxFPx or TI1_ED trigger sources */\r
+#define TIM_TRIGGERPOLARITY_BOTHEDGE TIM_INPUTCHANNELPOLARITY_BOTHEDGE /*!< Polarity for TIxFPx or TI1_ED trigger sources */\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup TIM_Trigger_Prescaler TIM Trigger Prescaler\r
+ * @{\r
+ */\r
+#define TIM_TRIGGERPRESCALER_DIV1 TIM_ETRPRESCALER_DIV1 /*!< No prescaler is used */\r
+#define TIM_TRIGGERPRESCALER_DIV2 TIM_ETRPRESCALER_DIV2 /*!< Prescaler for External ETR Trigger: Capture performed once every 2 events. */\r
+#define TIM_TRIGGERPRESCALER_DIV4 TIM_ETRPRESCALER_DIV4 /*!< Prescaler for External ETR Trigger: Capture performed once every 4 events. */\r
+#define TIM_TRIGGERPRESCALER_DIV8 TIM_ETRPRESCALER_DIV8 /*!< Prescaler for External ETR Trigger: Capture performed once every 8 events. */\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup TIM_TI1_Selection TIM TI1 Input Selection\r
+ * @{\r
+ */\r
+#define TIM_TI1SELECTION_CH1 0x00000000U /*!< The TIMx_CH1 pin is connected to TI1 input */\r
+#define TIM_TI1SELECTION_XORCOMBINATION TIM_CR2_TI1S /*!< The TIMx_CH1, CH2 and CH3 pins are connected to the TI1 input (XOR combination) */\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup TIM_DMA_Burst_Length TIM DMA Burst Length\r
+ * @{\r
+ */\r
+#define TIM_DMABURSTLENGTH_1TRANSFER 0x00000000U /*!< The transfer is done to 1 register starting trom TIMx_CR1 + TIMx_DCR.DBA */\r
+#define TIM_DMABURSTLENGTH_2TRANSFERS 0x00000100U /*!< The transfer is done to 2 registers starting trom TIMx_CR1 + TIMx_DCR.DBA */\r
+#define TIM_DMABURSTLENGTH_3TRANSFERS 0x00000200U /*!< The transfer is done to 3 registers starting trom TIMx_CR1 + TIMx_DCR.DBA */\r
+#define TIM_DMABURSTLENGTH_4TRANSFERS 0x00000300U /*!< The transfer is done to 4 registers starting trom TIMx_CR1 + TIMx_DCR.DBA */\r
+#define TIM_DMABURSTLENGTH_5TRANSFERS 0x00000400U /*!< The transfer is done to 5 registers starting trom TIMx_CR1 + TIMx_DCR.DBA */\r
+#define TIM_DMABURSTLENGTH_6TRANSFERS 0x00000500U /*!< The transfer is done to 6 registers starting trom TIMx_CR1 + TIMx_DCR.DBA */\r
+#define TIM_DMABURSTLENGTH_7TRANSFERS 0x00000600U /*!< The transfer is done to 7 registers starting trom TIMx_CR1 + TIMx_DCR.DBA */\r
+#define TIM_DMABURSTLENGTH_8TRANSFERS 0x00000700U /*!< The transfer is done to 8 registers starting trom TIMx_CR1 + TIMx_DCR.DBA */\r
+#define TIM_DMABURSTLENGTH_9TRANSFERS 0x00000800U /*!< The transfer is done to 9 registers starting trom TIMx_CR1 + TIMx_DCR.DBA */\r
+#define TIM_DMABURSTLENGTH_10TRANSFERS 0x00000900U /*!< The transfer is done to 10 registers starting trom TIMx_CR1 + TIMx_DCR.DBA */\r
+#define TIM_DMABURSTLENGTH_11TRANSFERS 0x00000A00U /*!< The transfer is done to 11 registers starting trom TIMx_CR1 + TIMx_DCR.DBA */\r
+#define TIM_DMABURSTLENGTH_12TRANSFERS 0x00000B00U /*!< The transfer is done to 12 registers starting trom TIMx_CR1 + TIMx_DCR.DBA */\r
+#define TIM_DMABURSTLENGTH_13TRANSFERS 0x00000C00U /*!< The transfer is done to 13 registers starting trom TIMx_CR1 + TIMx_DCR.DBA */\r
+#define TIM_DMABURSTLENGTH_14TRANSFERS 0x00000D00U /*!< The transfer is done to 14 registers starting trom TIMx_CR1 + TIMx_DCR.DBA */\r
+#define TIM_DMABURSTLENGTH_15TRANSFERS 0x00000E00U /*!< The transfer is done to 15 registers starting trom TIMx_CR1 + TIMx_DCR.DBA */\r
+#define TIM_DMABURSTLENGTH_16TRANSFERS 0x00000F00U /*!< The transfer is done to 16 registers starting trom TIMx_CR1 + TIMx_DCR.DBA */\r
+#define TIM_DMABURSTLENGTH_17TRANSFERS 0x00001000U /*!< The transfer is done to 17 registers starting trom TIMx_CR1 + TIMx_DCR.DBA */\r
+#define TIM_DMABURSTLENGTH_18TRANSFERS 0x00001100U /*!< The transfer is done to 18 registers starting trom TIMx_CR1 + TIMx_DCR.DBA */\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup DMA_Handle_index TIM DMA Handle Index\r
+ * @{\r
+ */\r
+#define TIM_DMA_ID_UPDATE ((uint16_t) 0x0000) /*!< Index of the DMA handle used for Update DMA requests */\r
+#define TIM_DMA_ID_CC1 ((uint16_t) 0x0001) /*!< Index of the DMA handle used for Capture/Compare 1 DMA requests */\r
+#define TIM_DMA_ID_CC2 ((uint16_t) 0x0002) /*!< Index of the DMA handle used for Capture/Compare 2 DMA requests */\r
+#define TIM_DMA_ID_CC3 ((uint16_t) 0x0003) /*!< Index of the DMA handle used for Capture/Compare 3 DMA requests */\r
+#define TIM_DMA_ID_CC4 ((uint16_t) 0x0004) /*!< Index of the DMA handle used for Capture/Compare 4 DMA requests */\r
+#define TIM_DMA_ID_TRIGGER ((uint16_t) 0x0006) /*!< Index of the DMA handle used for Trigger DMA requests */\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup Channel_CC_State TIM Capture/Compare Channel State\r
+ * @{\r
+ */\r
+#define TIM_CCx_ENABLE 0x00000001U /*!< Input or output channel is enabled */\r
+#define TIM_CCx_DISABLE 0x00000000U /*!< Input or output channel is disabled */\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+/* End of exported constants -------------------------------------------------*/\r
+\r
+/* Exported macros -----------------------------------------------------------*/\r
+/** @defgroup TIM_Exported_Macros TIM Exported Macros\r
+ * @{\r
+ */\r
+\r
+/** @brief Reset TIM handle state.\r
+ * @param __HANDLE__ TIM handle.\r
+ * @retval None\r
+ */\r
+#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)\r
+#define __HAL_TIM_RESET_HANDLE_STATE(__HANDLE__) do { \\r
+ (__HANDLE__)->State = HAL_TIM_STATE_RESET; \\r
+ (__HANDLE__)->Base_MspInitCallback = NULL; \\r
+ (__HANDLE__)->Base_MspDeInitCallback = NULL; \\r
+ (__HANDLE__)->IC_MspInitCallback = NULL; \\r
+ (__HANDLE__)->IC_MspDeInitCallback = NULL; \\r
+ (__HANDLE__)->OC_MspInitCallback = NULL; \\r
+ (__HANDLE__)->OC_MspDeInitCallback = NULL; \\r
+ (__HANDLE__)->PWM_MspInitCallback = NULL; \\r
+ (__HANDLE__)->PWM_MspDeInitCallback = NULL; \\r
+ (__HANDLE__)->OnePulse_MspInitCallback = NULL; \\r
+ (__HANDLE__)->OnePulse_MspDeInitCallback = NULL; \\r
+ (__HANDLE__)->Encoder_MspInitCallback = NULL; \\r
+ (__HANDLE__)->Encoder_MspDeInitCallback = NULL; \\r
+ } while(0)\r
+#else\r
+#define __HAL_TIM_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_TIM_STATE_RESET)\r
+#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */\r
+\r
+/**\r
+ * @brief Enable the TIM peripheral.\r
+ * @param __HANDLE__ TIM handle\r
+ * @retval None\r
+ */\r
+#define __HAL_TIM_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1|=(TIM_CR1_CEN))\r
+\r
+/**\r
+ * @brief Disable the TIM peripheral.\r
+ * @param __HANDLE__ TIM handle\r
+ * @retval None\r
+ */\r
+#define __HAL_TIM_DISABLE(__HANDLE__) \\r
+ do { \\r
+ if (((__HANDLE__)->Instance->CCER & TIM_CCER_CCxE_MASK) == 0UL) \\r
+ { \\r
+ (__HANDLE__)->Instance->CR1 &= ~(TIM_CR1_CEN); \\r
+ } \\r
+ } while(0)\r
+\r
+/** @brief Enable the specified TIM interrupt.\r
+ * @param __HANDLE__ specifies the TIM Handle.\r
+ * @param __INTERRUPT__ specifies the TIM interrupt source to enable.\r
+ * This parameter can be one of the following values:\r
+ * @arg TIM_IT_UPDATE: Update interrupt\r
+ * @arg TIM_IT_CC1: Capture/Compare 1 interrupt\r
+ * @arg TIM_IT_CC2: Capture/Compare 2 interrupt\r
+ * @arg TIM_IT_CC3: Capture/Compare 3 interrupt\r
+ * @arg TIM_IT_CC4: Capture/Compare 4 interrupt\r
+ * @arg TIM_IT_TRIGGER: Trigger interrupt\r
+ * @retval None\r
+ */\r
+#define __HAL_TIM_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->DIER |= (__INTERRUPT__))\r
+\r
+/** @brief Disable the specified TIM interrupt.\r
+ * @param __HANDLE__ specifies the TIM Handle.\r
+ * @param __INTERRUPT__ specifies the TIM interrupt source to disable.\r
+ * This parameter can be one of the following values:\r
+ * @arg TIM_IT_UPDATE: Update interrupt\r
+ * @arg TIM_IT_CC1: Capture/Compare 1 interrupt\r
+ * @arg TIM_IT_CC2: Capture/Compare 2 interrupt\r
+ * @arg TIM_IT_CC3: Capture/Compare 3 interrupt\r
+ * @arg TIM_IT_CC4: Capture/Compare 4 interrupt\r
+ * @arg TIM_IT_TRIGGER: Trigger interrupt\r
+ * @retval None\r
+ */\r
+#define __HAL_TIM_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->DIER &= ~(__INTERRUPT__))\r
+\r
+/** @brief Enable the specified DMA request.\r
+ * @param __HANDLE__ specifies the TIM Handle.\r
+ * @param __DMA__ specifies the TIM DMA request to enable.\r
+ * This parameter can be one of the following values:\r
+ * @arg TIM_DMA_UPDATE: Update DMA request\r
+ * @arg TIM_DMA_CC1: Capture/Compare 1 DMA request\r
+ * @arg TIM_DMA_CC2: Capture/Compare 2 DMA request\r
+ * @arg TIM_DMA_CC3: Capture/Compare 3 DMA request\r
+ * @arg TIM_DMA_CC4: Capture/Compare 4 DMA request\r
+ * @arg TIM_DMA_TRIGGER: Trigger DMA request\r
+ * @retval None\r
+ */\r
+#define __HAL_TIM_ENABLE_DMA(__HANDLE__, __DMA__) ((__HANDLE__)->Instance->DIER |= (__DMA__))\r
+\r
+/** @brief Disable the specified DMA request.\r
+ * @param __HANDLE__ specifies the TIM Handle.\r
+ * @param __DMA__ specifies the TIM DMA request to disable.\r
+ * This parameter can be one of the following values:\r
+ * @arg TIM_DMA_UPDATE: Update DMA request\r
+ * @arg TIM_DMA_CC1: Capture/Compare 1 DMA request\r
+ * @arg TIM_DMA_CC2: Capture/Compare 2 DMA request\r
+ * @arg TIM_DMA_CC3: Capture/Compare 3 DMA request\r
+ * @arg TIM_DMA_CC4: Capture/Compare 4 DMA request\r
+ * @arg TIM_DMA_TRIGGER: Trigger DMA request\r
+ * @retval None\r
+ */\r
+#define __HAL_TIM_DISABLE_DMA(__HANDLE__, __DMA__) ((__HANDLE__)->Instance->DIER &= ~(__DMA__))\r
+\r
+/** @brief Check whether the specified TIM interrupt flag is set or not.\r
+ * @param __HANDLE__ specifies the TIM Handle.\r
+ * @param __FLAG__ specifies the TIM interrupt flag to check.\r
+ * This parameter can be one of the following values:\r
+ * @arg TIM_FLAG_UPDATE: Update interrupt flag\r
+ * @arg TIM_FLAG_CC1: Capture/Compare 1 interrupt flag\r
+ * @arg TIM_FLAG_CC2: Capture/Compare 2 interrupt flag\r
+ * @arg TIM_FLAG_CC3: Capture/Compare 3 interrupt flag\r
+ * @arg TIM_FLAG_CC4: Capture/Compare 4 interrupt flag\r
+ * @arg TIM_FLAG_TRIGGER: Trigger interrupt flag\r
+ * @arg TIM_FLAG_CC1OF: Capture/Compare 1 overcapture flag\r
+ * @arg TIM_FLAG_CC2OF: Capture/Compare 2 overcapture flag\r
+ * @arg TIM_FLAG_CC3OF: Capture/Compare 3 overcapture flag\r
+ * @arg TIM_FLAG_CC4OF: Capture/Compare 4 overcapture flag\r
+ * @retval The new state of __FLAG__ (TRUE or FALSE).\r
+ */\r
+#define __HAL_TIM_GET_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->SR &(__FLAG__)) == (__FLAG__))\r
+\r
+/** @brief Clear the specified TIM interrupt flag.\r
+ * @param __HANDLE__ specifies the TIM Handle.\r
+ * @param __FLAG__ specifies the TIM interrupt flag to clear.\r
+ * This parameter can be one of the following values:\r
+ * @arg TIM_FLAG_UPDATE: Update interrupt flag\r
+ * @arg TIM_FLAG_CC1: Capture/Compare 1 interrupt flag\r
+ * @arg TIM_FLAG_CC2: Capture/Compare 2 interrupt flag\r
+ * @arg TIM_FLAG_CC3: Capture/Compare 3 interrupt flag\r
+ * @arg TIM_FLAG_CC4: Capture/Compare 4 interrupt flag\r
+ * @arg TIM_FLAG_TRIGGER: Trigger interrupt flag\r
+ * @arg TIM_FLAG_CC1OF: Capture/Compare 1 overcapture flag\r
+ * @arg TIM_FLAG_CC2OF: Capture/Compare 2 overcapture flag\r
+ * @arg TIM_FLAG_CC3OF: Capture/Compare 3 overcapture flag\r
+ * @arg TIM_FLAG_CC4OF: Capture/Compare 4 overcapture flag\r
+ * @retval The new state of __FLAG__ (TRUE or FALSE).\r
+ */\r
+#define __HAL_TIM_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->SR = ~(__FLAG__))\r
+\r
+/**\r
+ * @brief Check whether the specified TIM interrupt source is enabled or not.\r
+ * @param __HANDLE__ TIM handle\r
+ * @param __INTERRUPT__ specifies the TIM interrupt source to check.\r
+ * This parameter can be one of the following values:\r
+ * @arg TIM_IT_UPDATE: Update interrupt\r
+ * @arg TIM_IT_CC1: Capture/Compare 1 interrupt\r
+ * @arg TIM_IT_CC2: Capture/Compare 2 interrupt\r
+ * @arg TIM_IT_CC3: Capture/Compare 3 interrupt\r
+ * @arg TIM_IT_CC4: Capture/Compare 4 interrupt\r
+ * @arg TIM_IT_TRIGGER: Trigger interrupt\r
+ * @retval The state of TIM_IT (SET or RESET).\r
+ */\r
+#define __HAL_TIM_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->DIER & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET)\r
+\r
+/** @brief Clear the TIM interrupt pending bits.\r
+ * @param __HANDLE__ TIM handle\r
+ * @param __INTERRUPT__ specifies the interrupt pending bit to clear.\r
+ * This parameter can be one of the following values:\r
+ * @arg TIM_IT_UPDATE: Update interrupt\r
+ * @arg TIM_IT_CC1: Capture/Compare 1 interrupt\r
+ * @arg TIM_IT_CC2: Capture/Compare 2 interrupt\r
+ * @arg TIM_IT_CC3: Capture/Compare 3 interrupt\r
+ * @arg TIM_IT_CC4: Capture/Compare 4 interrupt\r
+ * @arg TIM_IT_TRIGGER: Trigger interrupt\r
+ * @retval None\r
+ */\r
+#define __HAL_TIM_CLEAR_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->SR = ~(__INTERRUPT__))\r
+\r
+/**\r
+ * @brief Indicates whether or not the TIM Counter is used as downcounter.\r
+ * @param __HANDLE__ TIM handle.\r
+ * @retval False (Counter used as upcounter) or True (Counter used as downcounter)\r
+ * @note This macro is particularly useful to get the counting mode when the timer operates in Center-aligned mode or Encoder\r
+mode.\r
+ */\r
+#define __HAL_TIM_IS_TIM_COUNTING_DOWN(__HANDLE__) (((__HANDLE__)->Instance->CR1 &(TIM_CR1_DIR)) == (TIM_CR1_DIR))\r
+\r
+/**\r
+ * @brief Set the TIM Prescaler on runtime.\r
+ * @param __HANDLE__ TIM handle.\r
+ * @param __PRESC__ specifies the Prescaler new value.\r
+ * @retval None\r
+ */\r
+#define __HAL_TIM_SET_PRESCALER(__HANDLE__, __PRESC__) ((__HANDLE__)->Instance->PSC = (__PRESC__))\r
+\r
+/**\r
+ * @brief Set the TIM Counter Register value on runtime.\r
+ * @param __HANDLE__ TIM handle.\r
+ * @param __COUNTER__ specifies the Counter register new value.\r
+ * @retval None\r
+ */\r
+#define __HAL_TIM_SET_COUNTER(__HANDLE__, __COUNTER__) ((__HANDLE__)->Instance->CNT = (__COUNTER__))\r
+\r
+/**\r
+ * @brief Get the TIM Counter Register value on runtime.\r
+ * @param __HANDLE__ TIM handle.\r
+ * @retval 16-bit or 32-bit value of the timer counter register (TIMx_CNT)\r
+ */\r
+#define __HAL_TIM_GET_COUNTER(__HANDLE__) \\r
+ ((__HANDLE__)->Instance->CNT)\r
+\r
+/**\r
+ * @brief Set the TIM Autoreload Register value on runtime without calling another time any Init function.\r
+ * @param __HANDLE__ TIM handle.\r
+ * @param __AUTORELOAD__ specifies the Counter register new value.\r
+ * @retval None\r
+ */\r
+#define __HAL_TIM_SET_AUTORELOAD(__HANDLE__, __AUTORELOAD__) \\r
+ do{ \\r
+ (__HANDLE__)->Instance->ARR = (__AUTORELOAD__); \\r
+ (__HANDLE__)->Init.Period = (__AUTORELOAD__); \\r
+ } while(0)\r
+\r
+/**\r
+ * @brief Get the TIM Autoreload Register value on runtime.\r
+ * @param __HANDLE__ TIM handle.\r
+ * @retval 16-bit or 32-bit value of the timer auto-reload register(TIMx_ARR)\r
+ */\r
+#define __HAL_TIM_GET_AUTORELOAD(__HANDLE__) \\r
+ ((__HANDLE__)->Instance->ARR)\r
+\r
+/**\r
+ * @brief Set the TIM Clock Division value on runtime without calling another time any Init function.\r
+ * @param __HANDLE__ TIM handle.\r
+ * @param __CKD__ specifies the clock division value.\r
+ * This parameter can be one of the following value:\r
+ * @arg TIM_CLOCKDIVISION_DIV1: tDTS=tCK_INT\r
+ * @arg TIM_CLOCKDIVISION_DIV2: tDTS=2*tCK_INT\r
+ * @arg TIM_CLOCKDIVISION_DIV4: tDTS=4*tCK_INT\r
+ * @retval None\r
+ */\r
+#define __HAL_TIM_SET_CLOCKDIVISION(__HANDLE__, __CKD__) \\r
+ do{ \\r
+ (__HANDLE__)->Instance->CR1 &= (~TIM_CR1_CKD); \\r
+ (__HANDLE__)->Instance->CR1 |= (__CKD__); \\r
+ (__HANDLE__)->Init.ClockDivision = (__CKD__); \\r
+ } while(0)\r
+\r
+/**\r
+ * @brief Get the TIM Clock Division value on runtime.\r
+ * @param __HANDLE__ TIM handle.\r
+ * @retval The clock division can be one of the following values:\r
+ * @arg TIM_CLOCKDIVISION_DIV1: tDTS=tCK_INT\r
+ * @arg TIM_CLOCKDIVISION_DIV2: tDTS=2*tCK_INT\r
+ * @arg TIM_CLOCKDIVISION_DIV4: tDTS=4*tCK_INT\r
+ */\r
+#define __HAL_TIM_GET_CLOCKDIVISION(__HANDLE__) \\r
+ ((__HANDLE__)->Instance->CR1 & TIM_CR1_CKD)\r
+\r
+/**\r
+ * @brief Set the TIM Input Capture prescaler on runtime without calling another time HAL_TIM_IC_ConfigChannel() function.\r
+ * @param __HANDLE__ TIM handle.\r
+ * @param __CHANNEL__ TIM Channels to be configured.\r
+ * This parameter can be one of the following values:\r
+ * @arg TIM_CHANNEL_1: TIM Channel 1 selected\r
+ * @arg TIM_CHANNEL_2: TIM Channel 2 selected\r
+ * @arg TIM_CHANNEL_3: TIM Channel 3 selected\r
+ * @arg TIM_CHANNEL_4: TIM Channel 4 selected\r
+ * @param __ICPSC__ specifies the Input Capture4 prescaler new value.\r
+ * This parameter can be one of the following values:\r
+ * @arg TIM_ICPSC_DIV1: no prescaler\r
+ * @arg TIM_ICPSC_DIV2: capture is done once every 2 events\r
+ * @arg TIM_ICPSC_DIV4: capture is done once every 4 events\r
+ * @arg TIM_ICPSC_DIV8: capture is done once every 8 events\r
+ * @retval None\r
+ */\r
+#define __HAL_TIM_SET_ICPRESCALER(__HANDLE__, __CHANNEL__, __ICPSC__) \\r
+ do{ \\r
+ TIM_RESET_ICPRESCALERVALUE((__HANDLE__), (__CHANNEL__)); \\r
+ TIM_SET_ICPRESCALERVALUE((__HANDLE__), (__CHANNEL__), (__ICPSC__)); \\r
+ } while(0)\r
+\r
+/**\r
+ * @brief Get the TIM Input Capture prescaler on runtime.\r
+ * @param __HANDLE__ TIM handle.\r
+ * @param __CHANNEL__ TIM Channels to be configured.\r
+ * This parameter can be one of the following values:\r
+ * @arg TIM_CHANNEL_1: get input capture 1 prescaler value\r
+ * @arg TIM_CHANNEL_2: get input capture 2 prescaler value\r
+ * @arg TIM_CHANNEL_3: get input capture 3 prescaler value\r
+ * @arg TIM_CHANNEL_4: get input capture 4 prescaler value\r
+ * @retval The input capture prescaler can be one of the following values:\r
+ * @arg TIM_ICPSC_DIV1: no prescaler\r
+ * @arg TIM_ICPSC_DIV2: capture is done once every 2 events\r
+ * @arg TIM_ICPSC_DIV4: capture is done once every 4 events\r
+ * @arg TIM_ICPSC_DIV8: capture is done once every 8 events\r
+ */\r
+#define __HAL_TIM_GET_ICPRESCALER(__HANDLE__, __CHANNEL__) \\r
+ (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 & TIM_CCMR1_IC1PSC) :\\r
+ ((__CHANNEL__) == TIM_CHANNEL_2) ? (((__HANDLE__)->Instance->CCMR1 & TIM_CCMR1_IC2PSC) >> 8U) :\\r
+ ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 & TIM_CCMR2_IC3PSC) :\\r
+ (((__HANDLE__)->Instance->CCMR2 & TIM_CCMR2_IC4PSC)) >> 8U)\r
+\r
+/**\r
+ * @brief Set the TIM Capture Compare Register value on runtime without calling another time ConfigChannel function.\r
+ * @param __HANDLE__ TIM handle.\r
+ * @param __CHANNEL__ TIM Channels to be configured.\r
+ * This parameter can be one of the following values:\r
+ * @arg TIM_CHANNEL_1: TIM Channel 1 selected\r
+ * @arg TIM_CHANNEL_2: TIM Channel 2 selected\r
+ * @arg TIM_CHANNEL_3: TIM Channel 3 selected\r
+ * @arg TIM_CHANNEL_4: TIM Channel 4 selected\r
+ * @param __COMPARE__ specifies the Capture Compare register new value.\r
+ * @retval None\r
+ */\r
+#define __HAL_TIM_SET_COMPARE(__HANDLE__, __CHANNEL__, __COMPARE__) \\r
+(((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCR1 = (__COMPARE__)) :\\r
+ ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCR2 = (__COMPARE__)) :\\r
+ ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCR3 = (__COMPARE__)) :\\r
+ ((__HANDLE__)->Instance->CCR4 = (__COMPARE__)))\r
+\r
+/**\r
+ * @brief Get the TIM Capture Compare Register value on runtime.\r
+ * @param __HANDLE__ TIM handle.\r
+ * @param __CHANNEL__ TIM Channel associated with the capture compare register\r
+ * This parameter can be one of the following values:\r
+ * @arg TIM_CHANNEL_1: get capture/compare 1 register value\r
+ * @arg TIM_CHANNEL_2: get capture/compare 2 register value\r
+ * @arg TIM_CHANNEL_3: get capture/compare 3 register value\r
+ * @arg TIM_CHANNEL_4: get capture/compare 4 register value\r
+ * @retval 16-bit or 32-bit value of the capture/compare register (TIMx_CCRy)\r
+ */\r
+#define __HAL_TIM_GET_COMPARE(__HANDLE__, __CHANNEL__) \\r
+(((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCR1) :\\r
+ ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCR2) :\\r
+ ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCR3) :\\r
+ ((__HANDLE__)->Instance->CCR4))\r
+\r
+/**\r
+ * @brief Set the TIM Output compare preload.\r
+ * @param __HANDLE__ TIM handle.\r
+ * @param __CHANNEL__ TIM Channels to be configured.\r
+ * This parameter can be one of the following values:\r
+ * @arg TIM_CHANNEL_1: TIM Channel 1 selected\r
+ * @arg TIM_CHANNEL_2: TIM Channel 2 selected\r
+ * @arg TIM_CHANNEL_3: TIM Channel 3 selected\r
+ * @arg TIM_CHANNEL_4: TIM Channel 4 selected\r
+ * @retval None\r
+ */\r
+#define __HAL_TIM_ENABLE_OCxPRELOAD(__HANDLE__, __CHANNEL__) \\r
+ (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 |= TIM_CCMR1_OC1PE) :\\r
+ ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCMR1 |= TIM_CCMR1_OC2PE) :\\r
+ ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 |= TIM_CCMR2_OC3PE) :\\r
+ ((__HANDLE__)->Instance->CCMR2 |= TIM_CCMR2_OC4PE))\r
+\r
+/**\r
+ * @brief Reset the TIM Output compare preload.\r
+ * @param __HANDLE__ TIM handle.\r
+ * @param __CHANNEL__ TIM Channels to be configured.\r
+ * This parameter can be one of the following values:\r
+ * @arg TIM_CHANNEL_1: TIM Channel 1 selected\r
+ * @arg TIM_CHANNEL_2: TIM Channel 2 selected\r
+ * @arg TIM_CHANNEL_3: TIM Channel 3 selected\r
+ * @arg TIM_CHANNEL_4: TIM Channel 4 selected\r
+ * @retval None\r
+ */\r
+#define __HAL_TIM_DISABLE_OCxPRELOAD(__HANDLE__, __CHANNEL__) \\r
+ (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 &= (uint16_t)~TIM_CCMR1_OC1PE) :\\r
+ ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCMR1 &= (uint16_t)~TIM_CCMR1_OC2PE) :\\r
+ ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 &= (uint16_t)~TIM_CCMR2_OC3PE) :\\r
+ ((__HANDLE__)->Instance->CCMR2 &= (uint16_t)~TIM_CCMR2_OC4PE))\r
+\r
+/**\r
+ * @brief Set the Update Request Source (URS) bit of the TIMx_CR1 register.\r
+ * @param __HANDLE__ TIM handle.\r
+ * @note When the URS bit of the TIMx_CR1 register is set, only counter\r
+ * overflow/underflow generates an update interrupt or DMA request (if\r
+ * enabled)\r
+ * @retval None\r
+ */\r
+#define __HAL_TIM_URS_ENABLE(__HANDLE__) \\r
+ ((__HANDLE__)->Instance->CR1|= TIM_CR1_URS)\r
+\r
+/**\r
+ * @brief Reset the Update Request Source (URS) bit of the TIMx_CR1 register.\r
+ * @param __HANDLE__ TIM handle.\r
+ * @note When the URS bit of the TIMx_CR1 register is reset, any of the\r
+ * following events generate an update interrupt or DMA request (if\r
+ * enabled):\r
+ * _ Counter overflow underflow\r
+ * _ Setting the UG bit\r
+ * _ Update generation through the slave mode controller\r
+ * @retval None\r
+ */\r
+#define __HAL_TIM_URS_DISABLE(__HANDLE__) \\r
+ ((__HANDLE__)->Instance->CR1&=~TIM_CR1_URS)\r
+\r
+/**\r
+ * @brief Set the TIM Capture x input polarity on runtime.\r
+ * @param __HANDLE__ TIM handle.\r
+ * @param __CHANNEL__ TIM Channels to be configured.\r
+ * This parameter can be one of the following values:\r
+ * @arg TIM_CHANNEL_1: TIM Channel 1 selected\r
+ * @arg TIM_CHANNEL_2: TIM Channel 2 selected\r
+ * @arg TIM_CHANNEL_3: TIM Channel 3 selected\r
+ * @arg TIM_CHANNEL_4: TIM Channel 4 selected\r
+ * @param __POLARITY__ Polarity for TIx source\r
+ * @arg TIM_INPUTCHANNELPOLARITY_RISING: Rising Edge\r
+ * @arg TIM_INPUTCHANNELPOLARITY_FALLING: Falling Edge\r
+ * @arg TIM_INPUTCHANNELPOLARITY_BOTHEDGE: Rising and Falling Edge\r
+ * @retval None\r
+ */\r
+#define __HAL_TIM_SET_CAPTUREPOLARITY(__HANDLE__, __CHANNEL__, __POLARITY__) \\r
+ do{ \\r
+ TIM_RESET_CAPTUREPOLARITY((__HANDLE__), (__CHANNEL__)); \\r
+ TIM_SET_CAPTUREPOLARITY((__HANDLE__), (__CHANNEL__), (__POLARITY__)); \\r
+ }while(0)\r
+\r
+/**\r
+ * @}\r
+ */\r
+/* End of exported macros ----------------------------------------------------*/\r
+\r
+/* Private constants ---------------------------------------------------------*/\r
+/** @defgroup TIM_Private_Constants TIM Private Constants\r
+ * @{\r
+ */\r
+/* The counter of a timer instance is disabled only if all the CCx and CCxN\r
+ channels have been disabled */\r
+#define TIM_CCER_CCxE_MASK ((uint32_t)(TIM_CCER_CC1E | TIM_CCER_CC2E | TIM_CCER_CC3E | TIM_CCER_CC4E))\r
+/**\r
+ * @}\r
+ */\r
+/* End of private constants --------------------------------------------------*/\r
+\r
+/* Private macros ------------------------------------------------------------*/\r
+/** @defgroup TIM_Private_Macros TIM Private Macros\r
+ * @{\r
+ */\r
+#define IS_TIM_CLEARINPUT_SOURCE(__MODE__) (((__MODE__) == TIM_CLEARINPUTSOURCE_NONE) || \\r
+ ((__MODE__) == TIM_CLEARINPUTSOURCE_ETR) || \\r
+ ((__MODE__) == TIM_CLEARINPUTSOURCE_OCREFCLR))\r
+\r
+#define IS_TIM_DMA_BASE(__BASE__) (((__BASE__) == TIM_DMABASE_CR1) || \\r
+ ((__BASE__) == TIM_DMABASE_CR2) || \\r
+ ((__BASE__) == TIM_DMABASE_SMCR) || \\r
+ ((__BASE__) == TIM_DMABASE_DIER) || \\r
+ ((__BASE__) == TIM_DMABASE_SR) || \\r
+ ((__BASE__) == TIM_DMABASE_EGR) || \\r
+ ((__BASE__) == TIM_DMABASE_CCMR1) || \\r
+ ((__BASE__) == TIM_DMABASE_CCMR2) || \\r
+ ((__BASE__) == TIM_DMABASE_CCER) || \\r
+ ((__BASE__) == TIM_DMABASE_CNT) || \\r
+ ((__BASE__) == TIM_DMABASE_PSC) || \\r
+ ((__BASE__) == TIM_DMABASE_ARR) || \\r
+ ((__BASE__) == TIM_DMABASE_CCR1) || \\r
+ ((__BASE__) == TIM_DMABASE_CCR2) || \\r
+ ((__BASE__) == TIM_DMABASE_CCR3) || \\r
+ ((__BASE__) == TIM_DMABASE_CCR4) || \\r
+ ((__BASE__) == TIM_DMABASE_OR))\r
+\r
+#define IS_TIM_EVENT_SOURCE(__SOURCE__) ((((__SOURCE__) & 0xFFFFFFA0U) == 0x00000000U) && ((__SOURCE__) != 0x00000000U))\r
+\r
+#define IS_TIM_COUNTER_MODE(__MODE__) (((__MODE__) == TIM_COUNTERMODE_UP) || \\r
+ ((__MODE__) == TIM_COUNTERMODE_DOWN) || \\r
+ ((__MODE__) == TIM_COUNTERMODE_CENTERALIGNED1) || \\r
+ ((__MODE__) == TIM_COUNTERMODE_CENTERALIGNED2) || \\r
+ ((__MODE__) == TIM_COUNTERMODE_CENTERALIGNED3))\r
+\r
+#define IS_TIM_CLOCKDIVISION_DIV(__DIV__) (((__DIV__) == TIM_CLOCKDIVISION_DIV1) || \\r
+ ((__DIV__) == TIM_CLOCKDIVISION_DIV2) || \\r
+ ((__DIV__) == TIM_CLOCKDIVISION_DIV4))\r
+\r
+#define IS_TIM_AUTORELOAD_PRELOAD(PRELOAD) (((PRELOAD) == TIM_AUTORELOAD_PRELOAD_DISABLE) || \\r
+ ((PRELOAD) == TIM_AUTORELOAD_PRELOAD_ENABLE))\r
+\r
+#define IS_TIM_FAST_STATE(__STATE__) (((__STATE__) == TIM_OCFAST_DISABLE) || \\r
+ ((__STATE__) == TIM_OCFAST_ENABLE))\r
+\r
+#define IS_TIM_OC_POLARITY(__POLARITY__) (((__POLARITY__) == TIM_OCPOLARITY_HIGH) || \\r
+ ((__POLARITY__) == TIM_OCPOLARITY_LOW))\r
+\r
+#define IS_TIM_IC_POLARITY(__POLARITY__) (((__POLARITY__) == TIM_ICPOLARITY_RISING) || \\r
+ ((__POLARITY__) == TIM_ICPOLARITY_FALLING) || \\r
+ ((__POLARITY__) == TIM_ICPOLARITY_BOTHEDGE))\r
+\r
+#define IS_TIM_IC_SELECTION(__SELECTION__) (((__SELECTION__) == TIM_ICSELECTION_DIRECTTI) || \\r
+ ((__SELECTION__) == TIM_ICSELECTION_INDIRECTTI) || \\r
+ ((__SELECTION__) == TIM_ICSELECTION_TRC))\r
+\r
+#define IS_TIM_IC_PRESCALER(__PRESCALER__) (((__PRESCALER__) == TIM_ICPSC_DIV1) || \\r
+ ((__PRESCALER__) == TIM_ICPSC_DIV2) || \\r
+ ((__PRESCALER__) == TIM_ICPSC_DIV4) || \\r
+ ((__PRESCALER__) == TIM_ICPSC_DIV8))\r
+\r
+#define IS_TIM_OPM_MODE(__MODE__) (((__MODE__) == TIM_OPMODE_SINGLE) || \\r
+ ((__MODE__) == TIM_OPMODE_REPETITIVE))\r
+\r
+#define IS_TIM_ENCODER_MODE(__MODE__) (((__MODE__) == TIM_ENCODERMODE_TI1) || \\r
+ ((__MODE__) == TIM_ENCODERMODE_TI2) || \\r
+ ((__MODE__) == TIM_ENCODERMODE_TI12))\r
+\r
+#define IS_TIM_DMA_SOURCE(__SOURCE__) ((((__SOURCE__) & 0xFFFFA0FFU) == 0x00000000U) && ((__SOURCE__) != 0x00000000U))\r
+\r
+#define IS_TIM_CHANNELS(__CHANNEL__) (((__CHANNEL__) == TIM_CHANNEL_1) || \\r
+ ((__CHANNEL__) == TIM_CHANNEL_2) || \\r
+ ((__CHANNEL__) == TIM_CHANNEL_3) || \\r
+ ((__CHANNEL__) == TIM_CHANNEL_4) || \\r
+ ((__CHANNEL__) == TIM_CHANNEL_ALL))\r
+\r
+#define IS_TIM_OPM_CHANNELS(__CHANNEL__) (((__CHANNEL__) == TIM_CHANNEL_1) || \\r
+ ((__CHANNEL__) == TIM_CHANNEL_2))\r
+\r
+#define IS_TIM_CLOCKSOURCE(__CLOCK__) (((__CLOCK__) == TIM_CLOCKSOURCE_INTERNAL) || \\r
+ ((__CLOCK__) == TIM_CLOCKSOURCE_ETRMODE2) || \\r
+ ((__CLOCK__) == TIM_CLOCKSOURCE_ITR0) || \\r
+ ((__CLOCK__) == TIM_CLOCKSOURCE_ITR1) || \\r
+ ((__CLOCK__) == TIM_CLOCKSOURCE_ITR2) || \\r
+ ((__CLOCK__) == TIM_CLOCKSOURCE_ITR3) || \\r
+ ((__CLOCK__) == TIM_CLOCKSOURCE_TI1ED) || \\r
+ ((__CLOCK__) == TIM_CLOCKSOURCE_TI1) || \\r
+ ((__CLOCK__) == TIM_CLOCKSOURCE_TI2) || \\r
+ ((__CLOCK__) == TIM_CLOCKSOURCE_ETRMODE1))\r
+\r
+#define IS_TIM_CLOCKPOLARITY(__POLARITY__) (((__POLARITY__) == TIM_CLOCKPOLARITY_INVERTED) || \\r
+ ((__POLARITY__) == TIM_CLOCKPOLARITY_NONINVERTED) || \\r
+ ((__POLARITY__) == TIM_CLOCKPOLARITY_RISING) || \\r
+ ((__POLARITY__) == TIM_CLOCKPOLARITY_FALLING) || \\r
+ ((__POLARITY__) == TIM_CLOCKPOLARITY_BOTHEDGE))\r
+\r
+#define IS_TIM_CLOCKPRESCALER(__PRESCALER__) (((__PRESCALER__) == TIM_CLOCKPRESCALER_DIV1) || \\r
+ ((__PRESCALER__) == TIM_CLOCKPRESCALER_DIV2) || \\r
+ ((__PRESCALER__) == TIM_CLOCKPRESCALER_DIV4) || \\r
+ ((__PRESCALER__) == TIM_CLOCKPRESCALER_DIV8))\r
+\r
+#define IS_TIM_CLOCKFILTER(__ICFILTER__) ((__ICFILTER__) <= 0xFU)\r
+\r
+#define IS_TIM_CLEARINPUT_POLARITY(__POLARITY__) (((__POLARITY__) == TIM_CLEARINPUTPOLARITY_INVERTED) || \\r
+ ((__POLARITY__) == TIM_CLEARINPUTPOLARITY_NONINVERTED))\r
+\r
+#define IS_TIM_CLEARINPUT_PRESCALER(__PRESCALER__) (((__PRESCALER__) == TIM_CLEARINPUTPRESCALER_DIV1) || \\r
+ ((__PRESCALER__) == TIM_CLEARINPUTPRESCALER_DIV2) || \\r
+ ((__PRESCALER__) == TIM_CLEARINPUTPRESCALER_DIV4) || \\r
+ ((__PRESCALER__) == TIM_CLEARINPUTPRESCALER_DIV8))\r
+\r
+#define IS_TIM_CLEARINPUT_FILTER(__ICFILTER__) ((__ICFILTER__) <= 0xFU)\r
+\r
+#define IS_TIM_TRGO_SOURCE(__SOURCE__) (((__SOURCE__) == TIM_TRGO_RESET) || \\r
+ ((__SOURCE__) == TIM_TRGO_ENABLE) || \\r
+ ((__SOURCE__) == TIM_TRGO_UPDATE) || \\r
+ ((__SOURCE__) == TIM_TRGO_OC1) || \\r
+ ((__SOURCE__) == TIM_TRGO_OC1REF) || \\r
+ ((__SOURCE__) == TIM_TRGO_OC2REF) || \\r
+ ((__SOURCE__) == TIM_TRGO_OC3REF) || \\r
+ ((__SOURCE__) == TIM_TRGO_OC4REF))\r
+\r
+#define IS_TIM_MSM_STATE(__STATE__) (((__STATE__) == TIM_MASTERSLAVEMODE_ENABLE) || \\r
+ ((__STATE__) == TIM_MASTERSLAVEMODE_DISABLE))\r
+\r
+#define IS_TIM_SLAVE_MODE(__MODE__) (((__MODE__) == TIM_SLAVEMODE_DISABLE) || \\r
+ ((__MODE__) == TIM_SLAVEMODE_RESET) || \\r
+ ((__MODE__) == TIM_SLAVEMODE_GATED) || \\r
+ ((__MODE__) == TIM_SLAVEMODE_TRIGGER) || \\r
+ ((__MODE__) == TIM_SLAVEMODE_EXTERNAL1))\r
+\r
+#define IS_TIM_PWM_MODE(__MODE__) (((__MODE__) == TIM_OCMODE_PWM1) || \\r
+ ((__MODE__) == TIM_OCMODE_PWM2))\r
+\r
+#define IS_TIM_OC_MODE(__MODE__) (((__MODE__) == TIM_OCMODE_TIMING) || \\r
+ ((__MODE__) == TIM_OCMODE_ACTIVE) || \\r
+ ((__MODE__) == TIM_OCMODE_INACTIVE) || \\r
+ ((__MODE__) == TIM_OCMODE_TOGGLE) || \\r
+ ((__MODE__) == TIM_OCMODE_FORCED_ACTIVE) || \\r
+ ((__MODE__) == TIM_OCMODE_FORCED_INACTIVE))\r
+\r
+#define IS_TIM_TRIGGER_SELECTION(__SELECTION__) (((__SELECTION__) == TIM_TS_ITR0) || \\r
+ ((__SELECTION__) == TIM_TS_ITR1) || \\r
+ ((__SELECTION__) == TIM_TS_ITR2) || \\r
+ ((__SELECTION__) == TIM_TS_ITR3) || \\r
+ ((__SELECTION__) == TIM_TS_TI1F_ED) || \\r
+ ((__SELECTION__) == TIM_TS_TI1FP1) || \\r
+ ((__SELECTION__) == TIM_TS_TI2FP2) || \\r
+ ((__SELECTION__) == TIM_TS_ETRF))\r
+\r
+#define IS_TIM_INTERNAL_TRIGGEREVENT_SELECTION(__SELECTION__) (((__SELECTION__) == TIM_TS_ITR0) || \\r
+ ((__SELECTION__) == TIM_TS_ITR1) || \\r
+ ((__SELECTION__) == TIM_TS_ITR2) || \\r
+ ((__SELECTION__) == TIM_TS_ITR3) || \\r
+ ((__SELECTION__) == TIM_TS_NONE))\r
+\r
+#define IS_TIM_TRIGGERPOLARITY(__POLARITY__) (((__POLARITY__) == TIM_TRIGGERPOLARITY_INVERTED ) || \\r
+ ((__POLARITY__) == TIM_TRIGGERPOLARITY_NONINVERTED) || \\r
+ ((__POLARITY__) == TIM_TRIGGERPOLARITY_RISING ) || \\r
+ ((__POLARITY__) == TIM_TRIGGERPOLARITY_FALLING ) || \\r
+ ((__POLARITY__) == TIM_TRIGGERPOLARITY_BOTHEDGE ))\r
+\r
+#define IS_TIM_TRIGGERPRESCALER(__PRESCALER__) (((__PRESCALER__) == TIM_TRIGGERPRESCALER_DIV1) || \\r
+ ((__PRESCALER__) == TIM_TRIGGERPRESCALER_DIV2) || \\r
+ ((__PRESCALER__) == TIM_TRIGGERPRESCALER_DIV4) || \\r
+ ((__PRESCALER__) == TIM_TRIGGERPRESCALER_DIV8))\r
+\r
+#define IS_TIM_TRIGGERFILTER(__ICFILTER__) ((__ICFILTER__) <= 0xFU)\r
+\r
+#define IS_TIM_TI1SELECTION(__TI1SELECTION__) (((__TI1SELECTION__) == TIM_TI1SELECTION_CH1) || \\r
+ ((__TI1SELECTION__) == TIM_TI1SELECTION_XORCOMBINATION))\r
+\r
+#define IS_TIM_DMA_LENGTH(__LENGTH__) (((__LENGTH__) == TIM_DMABURSTLENGTH_1TRANSFER) || \\r
+ ((__LENGTH__) == TIM_DMABURSTLENGTH_2TRANSFERS) || \\r
+ ((__LENGTH__) == TIM_DMABURSTLENGTH_3TRANSFERS) || \\r
+ ((__LENGTH__) == TIM_DMABURSTLENGTH_4TRANSFERS) || \\r
+ ((__LENGTH__) == TIM_DMABURSTLENGTH_5TRANSFERS) || \\r
+ ((__LENGTH__) == TIM_DMABURSTLENGTH_6TRANSFERS) || \\r
+ ((__LENGTH__) == TIM_DMABURSTLENGTH_7TRANSFERS) || \\r
+ ((__LENGTH__) == TIM_DMABURSTLENGTH_8TRANSFERS) || \\r
+ ((__LENGTH__) == TIM_DMABURSTLENGTH_9TRANSFERS) || \\r
+ ((__LENGTH__) == TIM_DMABURSTLENGTH_10TRANSFERS) || \\r
+ ((__LENGTH__) == TIM_DMABURSTLENGTH_11TRANSFERS) || \\r
+ ((__LENGTH__) == TIM_DMABURSTLENGTH_12TRANSFERS) || \\r
+ ((__LENGTH__) == TIM_DMABURSTLENGTH_13TRANSFERS) || \\r
+ ((__LENGTH__) == TIM_DMABURSTLENGTH_14TRANSFERS) || \\r
+ ((__LENGTH__) == TIM_DMABURSTLENGTH_15TRANSFERS) || \\r
+ ((__LENGTH__) == TIM_DMABURSTLENGTH_16TRANSFERS) || \\r
+ ((__LENGTH__) == TIM_DMABURSTLENGTH_17TRANSFERS) || \\r
+ ((__LENGTH__) == TIM_DMABURSTLENGTH_18TRANSFERS))\r
+\r
+#define IS_TIM_IC_FILTER(__ICFILTER__) ((__ICFILTER__) <= 0xFU)\r
+\r
+#define IS_TIM_SLAVEMODE_TRIGGER_ENABLED(__TRIGGER__) ((__TRIGGER__) == TIM_SLAVEMODE_TRIGGER)\r
+\r
+#define TIM_SET_ICPRESCALERVALUE(__HANDLE__, __CHANNEL__, __ICPSC__) \\r
+(((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 |= (__ICPSC__)) :\\r
+ ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCMR1 |= ((__ICPSC__) << 8U)) :\\r
+ ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 |= (__ICPSC__)) :\\r
+ ((__HANDLE__)->Instance->CCMR2 |= ((__ICPSC__) << 8U)))\r
+\r
+#define TIM_RESET_ICPRESCALERVALUE(__HANDLE__, __CHANNEL__) \\r
+(((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 &= (uint16_t)~TIM_CCMR1_IC1PSC) :\\r
+ ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCMR1 &= (uint16_t)~TIM_CCMR1_IC2PSC) :\\r
+ ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 &= (uint16_t)~TIM_CCMR2_IC3PSC) :\\r
+ ((__HANDLE__)->Instance->CCMR2 &= (uint16_t)~TIM_CCMR2_IC4PSC))\r
+\r
+#define TIM_SET_CAPTUREPOLARITY(__HANDLE__, __CHANNEL__, __POLARITY__) \\r
+(((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCER |= (__POLARITY__)) :\\r
+ ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCER |= ((__POLARITY__) << 4U)) :\\r
+ ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCER |= ((__POLARITY__) << 8U)) :\\r
+ ((__HANDLE__)->Instance->CCER |= (((__POLARITY__) << 12U))))\r
+\r
+#define TIM_RESET_CAPTUREPOLARITY(__HANDLE__, __CHANNEL__) \\r
+(((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCER &= (uint16_t)~(TIM_CCER_CC1P | TIM_CCER_CC1NP)) :\\r
+ ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCER &= (uint16_t)~(TIM_CCER_CC2P | TIM_CCER_CC2NP)) :\\r
+ ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCER &= (uint16_t)~(TIM_CCER_CC3P | TIM_CCER_CC3NP)) :\\r
+ ((__HANDLE__)->Instance->CCER &= (uint16_t)~(TIM_CCER_CC4P | TIM_CCER_CC4NP)))\r
+\r
+/**\r
+ * @}\r
+ */\r
+/* End of private macros -----------------------------------------------------*/\r
+\r
+/* Include TIM HAL Extended module */\r
+#include "stm32l1xx_hal_tim_ex.h"\r
+\r
+/* Exported functions --------------------------------------------------------*/\r
+/** @addtogroup TIM_Exported_Functions TIM Exported Functions\r
+ * @{\r
+ */\r
+\r
+/** @addtogroup TIM_Exported_Functions_Group1 TIM Time Base functions\r
+ * @brief Time Base functions\r
+ * @{\r
+ */\r
+/* Time Base functions ********************************************************/\r
+HAL_StatusTypeDef HAL_TIM_Base_Init(TIM_HandleTypeDef *htim);\r
+HAL_StatusTypeDef HAL_TIM_Base_DeInit(TIM_HandleTypeDef *htim);\r
+void HAL_TIM_Base_MspInit(TIM_HandleTypeDef *htim);\r
+void HAL_TIM_Base_MspDeInit(TIM_HandleTypeDef *htim);\r
+/* Blocking mode: Polling */\r
+HAL_StatusTypeDef HAL_TIM_Base_Start(TIM_HandleTypeDef *htim);\r
+HAL_StatusTypeDef HAL_TIM_Base_Stop(TIM_HandleTypeDef *htim);\r
+/* Non-Blocking mode: Interrupt */\r
+HAL_StatusTypeDef HAL_TIM_Base_Start_IT(TIM_HandleTypeDef *htim);\r
+HAL_StatusTypeDef HAL_TIM_Base_Stop_IT(TIM_HandleTypeDef *htim);\r
+/* Non-Blocking mode: DMA */\r
+HAL_StatusTypeDef HAL_TIM_Base_Start_DMA(TIM_HandleTypeDef *htim, uint32_t *pData, uint16_t Length);\r
+HAL_StatusTypeDef HAL_TIM_Base_Stop_DMA(TIM_HandleTypeDef *htim);\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @addtogroup TIM_Exported_Functions_Group2 TIM Output Compare functions\r
+ * @brief TIM Output Compare functions\r
+ * @{\r
+ */\r
+/* Timer Output Compare functions *********************************************/\r
+HAL_StatusTypeDef HAL_TIM_OC_Init(TIM_HandleTypeDef *htim);\r
+HAL_StatusTypeDef HAL_TIM_OC_DeInit(TIM_HandleTypeDef *htim);\r
+void HAL_TIM_OC_MspInit(TIM_HandleTypeDef *htim);\r
+void HAL_TIM_OC_MspDeInit(TIM_HandleTypeDef *htim);\r
+/* Blocking mode: Polling */\r
+HAL_StatusTypeDef HAL_TIM_OC_Start(TIM_HandleTypeDef *htim, uint32_t Channel);\r
+HAL_StatusTypeDef HAL_TIM_OC_Stop(TIM_HandleTypeDef *htim, uint32_t Channel);\r
+/* Non-Blocking mode: Interrupt */\r
+HAL_StatusTypeDef HAL_TIM_OC_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel);\r
+HAL_StatusTypeDef HAL_TIM_OC_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel);\r
+/* Non-Blocking mode: DMA */\r
+HAL_StatusTypeDef HAL_TIM_OC_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length);\r
+HAL_StatusTypeDef HAL_TIM_OC_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel);\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @addtogroup TIM_Exported_Functions_Group3 TIM PWM functions\r
+ * @brief TIM PWM functions\r
+ * @{\r
+ */\r
+/* Timer PWM functions ********************************************************/\r
+HAL_StatusTypeDef HAL_TIM_PWM_Init(TIM_HandleTypeDef *htim);\r
+HAL_StatusTypeDef HAL_TIM_PWM_DeInit(TIM_HandleTypeDef *htim);\r
+void HAL_TIM_PWM_MspInit(TIM_HandleTypeDef *htim);\r
+void HAL_TIM_PWM_MspDeInit(TIM_HandleTypeDef *htim);\r
+/* Blocking mode: Polling */\r
+HAL_StatusTypeDef HAL_TIM_PWM_Start(TIM_HandleTypeDef *htim, uint32_t Channel);\r
+HAL_StatusTypeDef HAL_TIM_PWM_Stop(TIM_HandleTypeDef *htim, uint32_t Channel);\r
+/* Non-Blocking mode: Interrupt */\r
+HAL_StatusTypeDef HAL_TIM_PWM_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel);\r
+HAL_StatusTypeDef HAL_TIM_PWM_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel);\r
+/* Non-Blocking mode: DMA */\r
+HAL_StatusTypeDef HAL_TIM_PWM_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length);\r
+HAL_StatusTypeDef HAL_TIM_PWM_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel);\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @addtogroup TIM_Exported_Functions_Group4 TIM Input Capture functions\r
+ * @brief TIM Input Capture functions\r
+ * @{\r
+ */\r
+/* Timer Input Capture functions **********************************************/\r
+HAL_StatusTypeDef HAL_TIM_IC_Init(TIM_HandleTypeDef *htim);\r
+HAL_StatusTypeDef HAL_TIM_IC_DeInit(TIM_HandleTypeDef *htim);\r
+void HAL_TIM_IC_MspInit(TIM_HandleTypeDef *htim);\r
+void HAL_TIM_IC_MspDeInit(TIM_HandleTypeDef *htim);\r
+/* Blocking mode: Polling */\r
+HAL_StatusTypeDef HAL_TIM_IC_Start(TIM_HandleTypeDef *htim, uint32_t Channel);\r
+HAL_StatusTypeDef HAL_TIM_IC_Stop(TIM_HandleTypeDef *htim, uint32_t Channel);\r
+/* Non-Blocking mode: Interrupt */\r
+HAL_StatusTypeDef HAL_TIM_IC_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel);\r
+HAL_StatusTypeDef HAL_TIM_IC_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel);\r
+/* Non-Blocking mode: DMA */\r
+HAL_StatusTypeDef HAL_TIM_IC_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length);\r
+HAL_StatusTypeDef HAL_TIM_IC_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel);\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @addtogroup TIM_Exported_Functions_Group5 TIM One Pulse functions\r
+ * @brief TIM One Pulse functions\r
+ * @{\r
+ */\r
+/* Timer One Pulse functions **************************************************/\r
+HAL_StatusTypeDef HAL_TIM_OnePulse_Init(TIM_HandleTypeDef *htim, uint32_t OnePulseMode);\r
+HAL_StatusTypeDef HAL_TIM_OnePulse_DeInit(TIM_HandleTypeDef *htim);\r
+void HAL_TIM_OnePulse_MspInit(TIM_HandleTypeDef *htim);\r
+void HAL_TIM_OnePulse_MspDeInit(TIM_HandleTypeDef *htim);\r
+/* Blocking mode: Polling */\r
+HAL_StatusTypeDef HAL_TIM_OnePulse_Start(TIM_HandleTypeDef *htim, uint32_t OutputChannel);\r
+HAL_StatusTypeDef HAL_TIM_OnePulse_Stop(TIM_HandleTypeDef *htim, uint32_t OutputChannel);\r
+/* Non-Blocking mode: Interrupt */\r
+HAL_StatusTypeDef HAL_TIM_OnePulse_Start_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel);\r
+HAL_StatusTypeDef HAL_TIM_OnePulse_Stop_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel);\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @addtogroup TIM_Exported_Functions_Group6 TIM Encoder functions\r
+ * @brief TIM Encoder functions\r
+ * @{\r
+ */\r
+/* Timer Encoder functions ****************************************************/\r
+HAL_StatusTypeDef HAL_TIM_Encoder_Init(TIM_HandleTypeDef *htim, TIM_Encoder_InitTypeDef *sConfig);\r
+HAL_StatusTypeDef HAL_TIM_Encoder_DeInit(TIM_HandleTypeDef *htim);\r
+void HAL_TIM_Encoder_MspInit(TIM_HandleTypeDef *htim);\r
+void HAL_TIM_Encoder_MspDeInit(TIM_HandleTypeDef *htim);\r
+/* Blocking mode: Polling */\r
+HAL_StatusTypeDef HAL_TIM_Encoder_Start(TIM_HandleTypeDef *htim, uint32_t Channel);\r
+HAL_StatusTypeDef HAL_TIM_Encoder_Stop(TIM_HandleTypeDef *htim, uint32_t Channel);\r
+/* Non-Blocking mode: Interrupt */\r
+HAL_StatusTypeDef HAL_TIM_Encoder_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel);\r
+HAL_StatusTypeDef HAL_TIM_Encoder_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel);\r
+/* Non-Blocking mode: DMA */\r
+HAL_StatusTypeDef HAL_TIM_Encoder_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData1, uint32_t *pData2, uint16_t Length);\r
+HAL_StatusTypeDef HAL_TIM_Encoder_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel);\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @addtogroup TIM_Exported_Functions_Group7 TIM IRQ handler management\r
+ * @brief IRQ handler management\r
+ * @{\r
+ */\r
+/* Interrupt Handler functions ***********************************************/\r
+void HAL_TIM_IRQHandler(TIM_HandleTypeDef *htim);\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup TIM_Exported_Functions_Group8 TIM Peripheral Control functions\r
+ * @brief Peripheral Control functions\r
+ * @{\r
+ */\r
+/* Control functions *********************************************************/\r
+HAL_StatusTypeDef HAL_TIM_OC_ConfigChannel(TIM_HandleTypeDef *htim, TIM_OC_InitTypeDef *sConfig, uint32_t Channel);\r
+HAL_StatusTypeDef HAL_TIM_PWM_ConfigChannel(TIM_HandleTypeDef *htim, TIM_OC_InitTypeDef *sConfig, uint32_t Channel);\r
+HAL_StatusTypeDef HAL_TIM_IC_ConfigChannel(TIM_HandleTypeDef *htim, TIM_IC_InitTypeDef *sConfig, uint32_t Channel);\r
+HAL_StatusTypeDef HAL_TIM_OnePulse_ConfigChannel(TIM_HandleTypeDef *htim, TIM_OnePulse_InitTypeDef *sConfig, uint32_t OutputChannel, uint32_t InputChannel);\r
+HAL_StatusTypeDef HAL_TIM_ConfigOCrefClear(TIM_HandleTypeDef *htim, TIM_ClearInputConfigTypeDef *sClearInputConfig, uint32_t Channel);\r
+HAL_StatusTypeDef HAL_TIM_ConfigClockSource(TIM_HandleTypeDef *htim, TIM_ClockConfigTypeDef *sClockSourceConfig);\r
+HAL_StatusTypeDef HAL_TIM_ConfigTI1Input(TIM_HandleTypeDef *htim, uint32_t TI1_Selection);\r
+HAL_StatusTypeDef HAL_TIM_SlaveConfigSynchro(TIM_HandleTypeDef *htim, TIM_SlaveConfigTypeDef *sSlaveConfig);\r
+HAL_StatusTypeDef HAL_TIM_SlaveConfigSynchro_IT(TIM_HandleTypeDef *htim, TIM_SlaveConfigTypeDef *sSlaveConfig);\r
+HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress, uint32_t BurstRequestSrc, \\r
+ uint32_t *BurstBuffer, uint32_t BurstLength);\r
+HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStop(TIM_HandleTypeDef *htim, uint32_t BurstRequestSrc);\r
+HAL_StatusTypeDef HAL_TIM_DMABurst_ReadStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress, uint32_t BurstRequestSrc, \\r
+ uint32_t *BurstBuffer, uint32_t BurstLength);\r
+HAL_StatusTypeDef HAL_TIM_DMABurst_ReadStop(TIM_HandleTypeDef *htim, uint32_t BurstRequestSrc);\r
+HAL_StatusTypeDef HAL_TIM_GenerateEvent(TIM_HandleTypeDef *htim, uint32_t EventSource);\r
+uint32_t HAL_TIM_ReadCapturedValue(TIM_HandleTypeDef *htim, uint32_t Channel);\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup TIM_Exported_Functions_Group9 TIM Callbacks functions\r
+ * @brief TIM Callbacks functions\r
+ * @{\r
+ */\r
+/* Callback in non blocking modes (Interrupt and DMA) *************************/\r
+void HAL_TIM_PeriodElapsedCallback(TIM_HandleTypeDef *htim);\r
+void HAL_TIM_PeriodElapsedHalfCpltCallback(TIM_HandleTypeDef *htim);\r
+void HAL_TIM_OC_DelayElapsedCallback(TIM_HandleTypeDef *htim);\r
+void HAL_TIM_IC_CaptureCallback(TIM_HandleTypeDef *htim);\r
+void HAL_TIM_IC_CaptureHalfCpltCallback(TIM_HandleTypeDef *htim);\r
+void HAL_TIM_PWM_PulseFinishedCallback(TIM_HandleTypeDef *htim);\r
+void HAL_TIM_PWM_PulseFinishedHalfCpltCallback(TIM_HandleTypeDef *htim);\r
+void HAL_TIM_TriggerCallback(TIM_HandleTypeDef *htim);\r
+void HAL_TIM_TriggerHalfCpltCallback(TIM_HandleTypeDef *htim);\r
+void HAL_TIM_ErrorCallback(TIM_HandleTypeDef *htim);\r
+\r
+/* Callbacks Register/UnRegister functions ***********************************/\r
+#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)\r
+HAL_StatusTypeDef HAL_TIM_RegisterCallback(TIM_HandleTypeDef *htim, HAL_TIM_CallbackIDTypeDef CallbackID, pTIM_CallbackTypeDef pCallback);\r
+HAL_StatusTypeDef HAL_TIM_UnRegisterCallback(TIM_HandleTypeDef *htim, HAL_TIM_CallbackIDTypeDef CallbackID);\r
+#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup TIM_Exported_Functions_Group10 TIM Peripheral State functions\r
+ * @brief Peripheral State functions\r
+ * @{\r
+ */\r
+/* Peripheral State functions ************************************************/\r
+HAL_TIM_StateTypeDef HAL_TIM_Base_GetState(TIM_HandleTypeDef *htim);\r
+HAL_TIM_StateTypeDef HAL_TIM_OC_GetState(TIM_HandleTypeDef *htim);\r
+HAL_TIM_StateTypeDef HAL_TIM_PWM_GetState(TIM_HandleTypeDef *htim);\r
+HAL_TIM_StateTypeDef HAL_TIM_IC_GetState(TIM_HandleTypeDef *htim);\r
+HAL_TIM_StateTypeDef HAL_TIM_OnePulse_GetState(TIM_HandleTypeDef *htim);\r
+HAL_TIM_StateTypeDef HAL_TIM_Encoder_GetState(TIM_HandleTypeDef *htim);\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+/* End of exported functions -------------------------------------------------*/\r
+\r
+/* Private functions----------------------------------------------------------*/\r
+/** @defgroup TIM_Private_Functions TIM Private Functions\r
+* @{\r
+*/\r
+void TIM_DMADelayPulseCplt(DMA_HandleTypeDef *hdma);\r
+void TIM_DMADelayPulseHalfCplt(DMA_HandleTypeDef *hdma);\r
+void TIM_DMAError(DMA_HandleTypeDef *hdma);\r
+void TIM_DMACaptureCplt(DMA_HandleTypeDef *hdma);\r
+void TIM_DMACaptureHalfCplt(DMA_HandleTypeDef *hdma);\r
+\r
+#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)\r
+void TIM_ResetCallback(TIM_HandleTypeDef *htim);\r
+#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */\r
+\r
+/**\r
+* @}\r
+*/\r
+/* End of private functions --------------------------------------------------*/\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+#ifdef __cplusplus\r
+}\r
+#endif\r
+\r
+#endif /* STM32L1xx_HAL_TIM_H */\r
+\r
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\r
--- /dev/null
+/**\r
+ ******************************************************************************\r
+ * @file stm32l1xx_hal_tim_ex.h\r
+ * @author MCD Application Team\r
+ * @brief Header file of TIM HAL Extended module.\r
+ ******************************************************************************\r
+ * @attention\r
+ *\r
+ * <h2><center>© Copyright (c) 2016 STMicroelectronics.\r
+ * All rights reserved.</center></h2>\r
+ *\r
+ * This software component is licensed by ST under BSD 3-Clause license,\r
+ * the "License"; You may not use this file except in compliance with the\r
+ * License. You may obtain a copy of the License at:\r
+ * opensource.org/licenses/BSD-3-Clause\r
+ *\r
+ ******************************************************************************\r
+ */\r
+\r
+/* Define to prevent recursive inclusion -------------------------------------*/\r
+#ifndef STM32L1xx_HAL_TIM_EX_H\r
+#define STM32L1xx_HAL_TIM_EX_H\r
+\r
+#ifdef __cplusplus\r
+extern "C" {\r
+#endif\r
+\r
+/* Includes ------------------------------------------------------------------*/\r
+#include "stm32l1xx_hal_def.h"\r
+\r
+/** @addtogroup STM32L1xx_HAL_Driver\r
+ * @{\r
+ */\r
+\r
+/** @addtogroup TIMEx\r
+ * @{\r
+ */\r
+\r
+/* Exported types ------------------------------------------------------------*/\r
+/** @defgroup TIMEx_Exported_Types TIM Extended Exported Types\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+/* End of exported types -----------------------------------------------------*/\r
+\r
+/* Exported constants --------------------------------------------------------*/\r
+/** @defgroup TIMEx_Exported_Constants TIM Extended Exported Constants\r
+ * @{\r
+ */\r
+\r
+/** @defgroup TIMEx_Remap TIM Extended Remapping\r
+ * @{\r
+ */\r
+/* @note STM32L1XX devices are organized in 6 categories: Cat.1, Cat.2, Cat.3, Cat.4, Cat.5, Cat.6.\r
+ Remap capabilities depend on the device category. As the DMA2 controller is available only in\r
+ Cat.3, Cat.4,Cat.5 and Cat.6 devices it is used to discriminate Cat.1 and Cat.2 devices v.s.\r
+ Cat.3, Cat.4, Cat.5 and Cat.6 devices. */\r
+#if defined(DMA2)\r
+#define TIM_TIM2_ITR1_TIM10_OC (0x00000000) /*!< TIM2 ITR1 input is connected to TIM10 OC */\r
+#define TIM_TIM2_ITR1_TIM5_TGO TIM2_OR_ITR1_RMP /*!< TIM2 ITR1 input is connected to TIM5 TGO */\r
+#endif /* DMA2 */\r
+\r
+#if defined(DMA2)\r
+#define TIM_TIM3_ITR2_TIM11_OC (0x00000000) /*!< TIM3 ITR2 input is connected to TIM11 OC */\r
+#define TIM_TIM3_ITR2_TIM5_TGO TIM2_OR_ITR1_RMP /*!< TIM3 ITR2 input is connected to TIM5 TGO */\r
+#endif /* DMA2 */\r
+\r
+#if defined(DMA2)\r
+#define TIM_TIM9_ITR1_TIM3_TGO (0x00000000) /*!< TIM9 ITR1 input is connected to TIM3 TGO */\r
+#define TIM_TIM9_ITR1_TS TIM9_OR_ITR1_RMP /*!< TIM9 ITR1 input is connected to touch sensing I/O */\r
+#endif /* DMA2 */\r
+#define TIM_TIM9_GPIO (0x00000000) /*!< TIM9 Channel1 is connected to GPIO */\r
+#define TIM_TIM9_LSE TIM_OR_TI1RMP_0 /*!< TIM9 Channel1 is connected to LSE internal clock */\r
+#define TIM_TIM9_GPIO1 TIM_OR_TI1RMP_1 /*!< TIM9 Channel1 is connected to GPIO */\r
+#define TIM_TIM9_GPIO2 TIM_OR_TI1RMP /*!< TIM9 Channel1 is connected to GPIO */\r
+\r
+#if defined(DMA2)\r
+#define TIM_TIM10_TI1RMP (0x00000000) /*!< TIM10 Channel 1 depends on TI1_RMP */\r
+#define TIM_TIM10_RI TIM_OR_TI1_RMP_RI /*!< TIM10 Channel 1 is connected to RI */\r
+#define TIM_TIM10_ETR_LSE (0x00000000) /*!< TIM10 ETR input is connected to LSE clock */\r
+#define TIM_TIM10_ETR_TIM9_TGO TIM_OR_ETR_RMP /*!< TIM10 ETR input is connected to TIM9 TGO */\r
+#endif /* DMA2 */\r
+#define TIM_TIM10_GPIO (0x00000000) /*!< TIM10 Channel1 is connected to GPIO */\r
+#define TIM_TIM10_LSI TIM_OR_TI1RMP_0 /*!< TIM10 Channel1 is connected to LSI internal clock */\r
+#define TIM_TIM10_LSE TIM_OR_TI1RMP_1 /*!< TIM10 Channel1 is connected to LSE internal clock */\r
+#define TIM_TIM10_RTC TIM_OR_TI1RMP /*!< TIM10 Channel1 is connected to RTC wakeup interrupt */\r
+\r
+#if defined(DMA2)\r
+#define TIM_TIM11_TI1RMP (0x00000000) /*!< TIM11 Channel 1 depends on TI1_RMP */\r
+#define TIM_TIM11_RI TIM_OR_TI1_RMP_RI /*!< TIM11 Channel 1 is connected to RI */\r
+#define TIM_TIM11_ETR_LSE (0x00000000) /*!< TIM11 ETR input is connected to LSE clock */\r
+#define TIM_TIM11_ETR_TIM9_TGO TIM_OR_ETR_RMP /*!< TIM11 ETR input is connected to TIM9 TGO */\r
+#endif /* DMA2 */\r
+#define TIM_TIM11_GPIO (0x00000000) /*!< TIM11 Channel1 is connected to GPIO */\r
+#define TIM_TIM11_MSI TIM_OR_TI1RMP_0 /*!< TIM11 Channel1 is connected to MSI internal clock */\r
+#define TIM_TIM11_HSE_RTC TIM_OR_TI1RMP_1 /*!< TIM11 Channel1 is connected to HSE_RTC clock */\r
+#define TIM_TIM11_GPIO1 TIM_OR_TI1RMP /*!< TIM11 Channel1 is connected to GPIO */\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+/* End of exported constants -------------------------------------------------*/\r
+\r
+/* Exported macro ------------------------------------------------------------*/\r
+/** @defgroup TIMEx_Exported_Macros TIM Extended Exported Macros\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+/* End of exported macro -----------------------------------------------------*/\r
+\r
+/* Private macro -------------------------------------------------------------*/\r
+/** @defgroup TIMEx_Private_Macros TIM Extended Private Macros\r
+ * @{\r
+ */\r
+#if defined(DMA2)\r
+#define IS_TIM_REMAP(INSTANCE, TIM_REMAP) \\r
+ ( (((INSTANCE) == TIM2) && (((TIM_REMAP) == TIM_TIM2_ITR1_TIM10_OC) || ((TIM_REMAP) == TIM_TIM2_ITR1_TIM5_TGO))) || \\r
+ (((INSTANCE) == TIM3) && (((TIM_REMAP) == TIM_TIM3_ITR2_TIM11_OC) || ((TIM_REMAP) == TIM_TIM3_ITR2_TIM5_TGO))) || \\r
+ (((INSTANCE) == TIM9) && ((TIM_REMAP) <= (TIM_TIM9_ITR1_TS | TIM_TIM9_GPIO2))) || \\r
+ (((INSTANCE) == TIM10) && ((TIM_REMAP) <= (TIM_TIM10_RI | TIM_TIM10_ETR_TIM9_TGO | TIM_TIM10_RTC))) || \\r
+ (((INSTANCE) == TIM11) && ((TIM_REMAP) <= (TIM_TIM11_RI | TIM_TIM11_ETR_TIM9_TGO | TIM_TIM11_GPIO1))) \\r
+ )\r
+#else\r
+#define IS_TIM_REMAP(INSTANCE, TIM_REMAP) \\r
+ ( (((INSTANCE) == TIM9) && (((TIM_REMAP) == TIM_TIM9_GPIO) || ((TIM_REMAP) == TIM_TIM9_LSE) || ((TIM_REMAP) == TIM_TIM9_GPIO1) || ((TIM_REMAP) == TIM_TIM9_GPIO2))) || \\r
+ (((INSTANCE) == TIM10) && (((TIM_REMAP) == TIM_TIM10_GPIO) || ((TIM_REMAP) == TIM_TIM10_LSI) || ((TIM_REMAP) == TIM_TIM10_LSE) || ((TIM_REMAP) == TIM_TIM10_RTC))) || \\r
+ (((INSTANCE) == TIM11) && (((TIM_REMAP) == TIM_TIM11_GPIO) || ((TIM_REMAP) == TIM_TIM11_MSI) || ((TIM_REMAP) == TIM_TIM11_HSE_RTC) || ((TIM_REMAP) == TIM_TIM11_GPIO1))) \\r
+ )\r
+#endif /* DMA2 */\r
+\r
+/**\r
+ * @}\r
+ */\r
+/* End of private macro ------------------------------------------------------*/\r
+\r
+/* Exported functions --------------------------------------------------------*/\r
+/** @addtogroup TIMEx_Exported_Functions TIM Extended Exported Functions\r
+ * @{\r
+ */\r
+\r
+/** @addtogroup TIMEx_Exported_Functions_Group5 Extended Peripheral Control functions\r
+ * @brief Peripheral Control functions\r
+ * @{\r
+ */\r
+/* Extended Control functions ************************************************/\r
+HAL_StatusTypeDef HAL_TIMEx_MasterConfigSynchronization(TIM_HandleTypeDef *htim, TIM_MasterConfigTypeDef *sMasterConfig);\r
+HAL_StatusTypeDef HAL_TIMEx_RemapConfig(TIM_HandleTypeDef *htim, uint32_t Remap);\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+/* End of exported functions -------------------------------------------------*/\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+#ifdef __cplusplus\r
+}\r
+#endif\r
+\r
+\r
+#endif /* STM32L1xx_HAL_TIM_EX_H */\r
+\r
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\r
--- /dev/null
+/**\r
+ ******************************************************************************\r
+ * @file stm32l1xx_hal_uart.h\r
+ * @author MCD Application Team\r
+ * @brief Header file of UART HAL module.\r
+ ******************************************************************************\r
+ * @attention\r
+ *\r
+ * <h2><center>© Copyright (c) 2016 STMicroelectronics.\r
+ * All rights reserved.</center></h2>\r
+ *\r
+ * This software component is licensed by ST under BSD 3-Clause license,\r
+ * the "License"; You may not use this file except in compliance with the\r
+ * License. You may obtain a copy of the License at:\r
+ * opensource.org/licenses/BSD-3-Clause\r
+ *\r
+ ******************************************************************************\r
+ */\r
+\r
+/* Define to prevent recursive inclusion -------------------------------------*/\r
+#ifndef __STM32L1xx_HAL_UART_H\r
+#define __STM32L1xx_HAL_UART_H\r
+\r
+#ifdef __cplusplus\r
+extern "C" {\r
+#endif\r
+\r
+/* Includes ------------------------------------------------------------------*/\r
+#include "stm32l1xx_hal_def.h"\r
+\r
+/** @addtogroup STM32L1xx_HAL_Driver\r
+ * @{\r
+ */\r
+\r
+/** @addtogroup UART\r
+ * @{\r
+ */\r
+\r
+/* Exported types ------------------------------------------------------------*/\r
+/** @defgroup UART_Exported_Types UART Exported Types\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @brief UART Init Structure definition\r
+ */\r
+typedef struct\r
+{\r
+ uint32_t BaudRate; /*!< This member configures the UART communication baud rate.\r
+ The baud rate is computed using the following formula:\r
+ - IntegerDivider = ((PCLKx) / (8 * (OVR8+1) * (huart->Init.BaudRate)))\r
+ - FractionalDivider = ((IntegerDivider - ((uint32_t) IntegerDivider)) * 8 * (OVR8+1)) + 0.5\r
+ Where OVR8 is the "oversampling by 8 mode" configuration bit in the CR1 register. */\r
+\r
+ uint32_t WordLength; /*!< Specifies the number of data bits transmitted or received in a frame.\r
+ This parameter can be a value of @ref UART_Word_Length */\r
+\r
+ uint32_t StopBits; /*!< Specifies the number of stop bits transmitted.\r
+ This parameter can be a value of @ref UART_Stop_Bits */\r
+\r
+ uint32_t Parity; /*!< Specifies the parity mode.\r
+ This parameter can be a value of @ref UART_Parity\r
+ @note When parity is enabled, the computed parity is inserted\r
+ at the MSB position of the transmitted data (9th bit when\r
+ the word length is set to 9 data bits; 8th bit when the\r
+ word length is set to 8 data bits). */\r
+\r
+ uint32_t Mode; /*!< Specifies whether the Receive or Transmit mode is enabled or disabled.\r
+ This parameter can be a value of @ref UART_Mode */\r
+\r
+ uint32_t HwFlowCtl; /*!< Specifies whether the hardware flow control mode is enabled or disabled.\r
+ This parameter can be a value of @ref UART_Hardware_Flow_Control */\r
+\r
+ uint32_t OverSampling; /*!< Specifies whether the Over sampling 8 is enabled or disabled, to achieve higher speed (up to fPCLK/8).\r
+ This parameter can be a value of @ref UART_Over_Sampling */\r
+} UART_InitTypeDef;\r
+\r
+/**\r
+ * @brief HAL UART State structures definition\r
+ * @note HAL UART State value is a combination of 2 different substates: gState and RxState.\r
+ * - gState contains UART state information related to global Handle management\r
+ * and also information related to Tx operations.\r
+ * gState value coding follow below described bitmap :\r
+ * b7-b6 Error information\r
+ * 00 : No Error\r
+ * 01 : (Not Used)\r
+ * 10 : Timeout\r
+ * 11 : Error\r
+ * b5 Peripheral initialization status\r
+ * 0 : Reset (Peripheral not initialized)\r
+ * 1 : Init done (Peripheral not initialized. HAL UART Init function already called)\r
+ * b4-b3 (not used)\r
+ * xx : Should be set to 00\r
+ * b2 Intrinsic process state\r
+ * 0 : Ready\r
+ * 1 : Busy (Peripheral busy with some configuration or internal operations)\r
+ * b1 (not used)\r
+ * x : Should be set to 0\r
+ * b0 Tx state\r
+ * 0 : Ready (no Tx operation ongoing)\r
+ * 1 : Busy (Tx operation ongoing)\r
+ * - RxState contains information related to Rx operations.\r
+ * RxState value coding follow below described bitmap :\r
+ * b7-b6 (not used)\r
+ * xx : Should be set to 00\r
+ * b5 Peripheral initialization status\r
+ * 0 : Reset (Peripheral not initialized)\r
+ * 1 : Init done (Peripheral not initialized)\r
+ * b4-b2 (not used)\r
+ * xxx : Should be set to 000\r
+ * b1 Rx state\r
+ * 0 : Ready (no Rx operation ongoing)\r
+ * 1 : Busy (Rx operation ongoing)\r
+ * b0 (not used)\r
+ * x : Should be set to 0.\r
+ */\r
+typedef enum\r
+{\r
+ HAL_UART_STATE_RESET = 0x00U, /*!< Peripheral is not yet Initialized\r
+ Value is allowed for gState and RxState */\r
+ HAL_UART_STATE_READY = 0x20U, /*!< Peripheral Initialized and ready for use\r
+ Value is allowed for gState and RxState */\r
+ HAL_UART_STATE_BUSY = 0x24U, /*!< an internal process is ongoing\r
+ Value is allowed for gState only */\r
+ HAL_UART_STATE_BUSY_TX = 0x21U, /*!< Data Transmission process is ongoing\r
+ Value is allowed for gState only */\r
+ HAL_UART_STATE_BUSY_RX = 0x22U, /*!< Data Reception process is ongoing\r
+ Value is allowed for RxState only */\r
+ HAL_UART_STATE_BUSY_TX_RX = 0x23U, /*!< Data Transmission and Reception process is ongoing\r
+ Not to be used for neither gState nor RxState.\r
+ Value is result of combination (Or) between gState and RxState values */\r
+ HAL_UART_STATE_TIMEOUT = 0xA0U, /*!< Timeout state\r
+ Value is allowed for gState only */\r
+ HAL_UART_STATE_ERROR = 0xE0U /*!< Error\r
+ Value is allowed for gState only */\r
+} HAL_UART_StateTypeDef;\r
+\r
+/**\r
+ * @brief UART handle Structure definition\r
+ */\r
+typedef struct __UART_HandleTypeDef\r
+{\r
+ USART_TypeDef *Instance; /*!< UART registers base address */\r
+\r
+ UART_InitTypeDef Init; /*!< UART communication parameters */\r
+\r
+ uint8_t *pTxBuffPtr; /*!< Pointer to UART Tx transfer Buffer */\r
+\r
+ uint16_t TxXferSize; /*!< UART Tx Transfer size */\r
+\r
+ __IO uint16_t TxXferCount; /*!< UART Tx Transfer Counter */\r
+\r
+ uint8_t *pRxBuffPtr; /*!< Pointer to UART Rx transfer Buffer */\r
+\r
+ uint16_t RxXferSize; /*!< UART Rx Transfer size */\r
+\r
+ __IO uint16_t RxXferCount; /*!< UART Rx Transfer Counter */\r
+\r
+ DMA_HandleTypeDef *hdmatx; /*!< UART Tx DMA Handle parameters */\r
+\r
+ DMA_HandleTypeDef *hdmarx; /*!< UART Rx DMA Handle parameters */\r
+\r
+ HAL_LockTypeDef Lock; /*!< Locking object */\r
+\r
+ __IO HAL_UART_StateTypeDef gState; /*!< UART state information related to global Handle management\r
+ and also related to Tx operations.\r
+ This parameter can be a value of @ref HAL_UART_StateTypeDef */\r
+\r
+ __IO HAL_UART_StateTypeDef RxState; /*!< UART state information related to Rx operations.\r
+ This parameter can be a value of @ref HAL_UART_StateTypeDef */\r
+\r
+ __IO uint32_t ErrorCode; /*!< UART Error code */\r
+\r
+#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)\r
+ void (* TxHalfCpltCallback)(struct __UART_HandleTypeDef *huart); /*!< UART Tx Half Complete Callback */\r
+ void (* TxCpltCallback)(struct __UART_HandleTypeDef *huart); /*!< UART Tx Complete Callback */\r
+ void (* RxHalfCpltCallback)(struct __UART_HandleTypeDef *huart); /*!< UART Rx Half Complete Callback */\r
+ void (* RxCpltCallback)(struct __UART_HandleTypeDef *huart); /*!< UART Rx Complete Callback */\r
+ void (* ErrorCallback)(struct __UART_HandleTypeDef *huart); /*!< UART Error Callback */\r
+ void (* AbortCpltCallback)(struct __UART_HandleTypeDef *huart); /*!< UART Abort Complete Callback */\r
+ void (* AbortTransmitCpltCallback)(struct __UART_HandleTypeDef *huart); /*!< UART Abort Transmit Complete Callback */\r
+ void (* AbortReceiveCpltCallback)(struct __UART_HandleTypeDef *huart); /*!< UART Abort Receive Complete Callback */\r
+ void (* WakeupCallback)(struct __UART_HandleTypeDef *huart); /*!< UART Wakeup Callback */\r
+\r
+ void (* MspInitCallback)(struct __UART_HandleTypeDef *huart); /*!< UART Msp Init callback */\r
+ void (* MspDeInitCallback)(struct __UART_HandleTypeDef *huart); /*!< UART Msp DeInit callback */\r
+#endif /* USE_HAL_UART_REGISTER_CALLBACKS */\r
+\r
+} UART_HandleTypeDef;\r
+\r
+#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)\r
+/**\r
+ * @brief HAL UART Callback ID enumeration definition\r
+ */\r
+typedef enum\r
+{\r
+ HAL_UART_TX_HALFCOMPLETE_CB_ID = 0x00U, /*!< UART Tx Half Complete Callback ID */\r
+ HAL_UART_TX_COMPLETE_CB_ID = 0x01U, /*!< UART Tx Complete Callback ID */\r
+ HAL_UART_RX_HALFCOMPLETE_CB_ID = 0x02U, /*!< UART Rx Half Complete Callback ID */\r
+ HAL_UART_RX_COMPLETE_CB_ID = 0x03U, /*!< UART Rx Complete Callback ID */\r
+ HAL_UART_ERROR_CB_ID = 0x04U, /*!< UART Error Callback ID */\r
+ HAL_UART_ABORT_COMPLETE_CB_ID = 0x05U, /*!< UART Abort Complete Callback ID */\r
+ HAL_UART_ABORT_TRANSMIT_COMPLETE_CB_ID = 0x06U, /*!< UART Abort Transmit Complete Callback ID */\r
+ HAL_UART_ABORT_RECEIVE_COMPLETE_CB_ID = 0x07U, /*!< UART Abort Receive Complete Callback ID */\r
+ HAL_UART_WAKEUP_CB_ID = 0x08U, /*!< UART Wakeup Callback ID */\r
+\r
+ HAL_UART_MSPINIT_CB_ID = 0x0BU, /*!< UART MspInit callback ID */\r
+ HAL_UART_MSPDEINIT_CB_ID = 0x0CU /*!< UART MspDeInit callback ID */\r
+\r
+} HAL_UART_CallbackIDTypeDef;\r
+\r
+/**\r
+ * @brief HAL UART Callback pointer definition\r
+ */\r
+typedef void (*pUART_CallbackTypeDef)(UART_HandleTypeDef *huart); /*!< pointer to an UART callback function */\r
+\r
+#endif /* USE_HAL_UART_REGISTER_CALLBACKS */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/* Exported constants --------------------------------------------------------*/\r
+/** @defgroup UART_Exported_Constants UART Exported Constants\r
+ * @{\r
+ */\r
+\r
+/** @defgroup UART_Error_Code UART Error Code\r
+ * @{\r
+ */\r
+#define HAL_UART_ERROR_NONE 0x00000000U /*!< No error */\r
+#define HAL_UART_ERROR_PE 0x00000001U /*!< Parity error */\r
+#define HAL_UART_ERROR_NE 0x00000002U /*!< Noise error */\r
+#define HAL_UART_ERROR_FE 0x00000004U /*!< Frame error */\r
+#define HAL_UART_ERROR_ORE 0x00000008U /*!< Overrun error */\r
+#define HAL_UART_ERROR_DMA 0x00000010U /*!< DMA transfer error */\r
+#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)\r
+#define HAL_UART_ERROR_INVALID_CALLBACK 0x00000020U /*!< Invalid Callback error */\r
+#endif /* USE_HAL_UART_REGISTER_CALLBACKS */\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup UART_Word_Length UART Word Length\r
+ * @{\r
+ */\r
+#define UART_WORDLENGTH_8B 0x00000000U\r
+#define UART_WORDLENGTH_9B ((uint32_t)USART_CR1_M)\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup UART_Stop_Bits UART Number of Stop Bits\r
+ * @{\r
+ */\r
+#define UART_STOPBITS_1 0x00000000U\r
+#define UART_STOPBITS_2 ((uint32_t)USART_CR2_STOP_1)\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup UART_Parity UART Parity\r
+ * @{\r
+ */\r
+#define UART_PARITY_NONE 0x00000000U\r
+#define UART_PARITY_EVEN ((uint32_t)USART_CR1_PCE)\r
+#define UART_PARITY_ODD ((uint32_t)(USART_CR1_PCE | USART_CR1_PS))\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup UART_Hardware_Flow_Control UART Hardware Flow Control\r
+ * @{\r
+ */\r
+#define UART_HWCONTROL_NONE 0x00000000U\r
+#define UART_HWCONTROL_RTS ((uint32_t)USART_CR3_RTSE)\r
+#define UART_HWCONTROL_CTS ((uint32_t)USART_CR3_CTSE)\r
+#define UART_HWCONTROL_RTS_CTS ((uint32_t)(USART_CR3_RTSE | USART_CR3_CTSE))\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup UART_Mode UART Transfer Mode\r
+ * @{\r
+ */\r
+#define UART_MODE_RX ((uint32_t)USART_CR1_RE)\r
+#define UART_MODE_TX ((uint32_t)USART_CR1_TE)\r
+#define UART_MODE_TX_RX ((uint32_t)(USART_CR1_TE | USART_CR1_RE))\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup UART_State UART State\r
+ * @{\r
+ */\r
+#define UART_STATE_DISABLE 0x00000000U\r
+#define UART_STATE_ENABLE ((uint32_t)USART_CR1_UE)\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup UART_Over_Sampling UART Over Sampling\r
+ * @{\r
+ */\r
+#define UART_OVERSAMPLING_16 0x00000000U\r
+#define UART_OVERSAMPLING_8 ((uint32_t)USART_CR1_OVER8)\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup UART_LIN_Break_Detection_Length UART LIN Break Detection Length\r
+ * @{\r
+ */\r
+#define UART_LINBREAKDETECTLENGTH_10B 0x00000000U\r
+#define UART_LINBREAKDETECTLENGTH_11B ((uint32_t)USART_CR2_LBDL)\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup UART_WakeUp_functions UART Wakeup Functions\r
+ * @{\r
+ */\r
+#define UART_WAKEUPMETHOD_IDLELINE 0x00000000U\r
+#define UART_WAKEUPMETHOD_ADDRESSMARK ((uint32_t)USART_CR1_WAKE)\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup UART_Flags UART FLags\r
+ * Elements values convention: 0xXXXX\r
+ * - 0xXXXX : Flag mask in the SR register\r
+ * @{\r
+ */\r
+#define UART_FLAG_CTS ((uint32_t)USART_SR_CTS)\r
+#define UART_FLAG_LBD ((uint32_t)USART_SR_LBD)\r
+#define UART_FLAG_TXE ((uint32_t)USART_SR_TXE)\r
+#define UART_FLAG_TC ((uint32_t)USART_SR_TC)\r
+#define UART_FLAG_RXNE ((uint32_t)USART_SR_RXNE)\r
+#define UART_FLAG_IDLE ((uint32_t)USART_SR_IDLE)\r
+#define UART_FLAG_ORE ((uint32_t)USART_SR_ORE)\r
+#define UART_FLAG_NE ((uint32_t)USART_SR_NE)\r
+#define UART_FLAG_FE ((uint32_t)USART_SR_FE)\r
+#define UART_FLAG_PE ((uint32_t)USART_SR_PE)\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup UART_Interrupt_definition UART Interrupt Definitions\r
+ * Elements values convention: 0xY000XXXX\r
+ * - XXXX : Interrupt mask (16 bits) in the Y register\r
+ * - Y : Interrupt source register (2bits)\r
+ * - 0001: CR1 register\r
+ * - 0010: CR2 register\r
+ * - 0011: CR3 register\r
+ * @{\r
+ */\r
+\r
+#define UART_IT_PE ((uint32_t)(UART_CR1_REG_INDEX << 28U | USART_CR1_PEIE))\r
+#define UART_IT_TXE ((uint32_t)(UART_CR1_REG_INDEX << 28U | USART_CR1_TXEIE))\r
+#define UART_IT_TC ((uint32_t)(UART_CR1_REG_INDEX << 28U | USART_CR1_TCIE))\r
+#define UART_IT_RXNE ((uint32_t)(UART_CR1_REG_INDEX << 28U | USART_CR1_RXNEIE))\r
+#define UART_IT_IDLE ((uint32_t)(UART_CR1_REG_INDEX << 28U | USART_CR1_IDLEIE))\r
+\r
+#define UART_IT_LBD ((uint32_t)(UART_CR2_REG_INDEX << 28U | USART_CR2_LBDIE))\r
+\r
+#define UART_IT_CTS ((uint32_t)(UART_CR3_REG_INDEX << 28U | USART_CR3_CTSIE))\r
+#define UART_IT_ERR ((uint32_t)(UART_CR3_REG_INDEX << 28U | USART_CR3_EIE))\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/* Exported macro ------------------------------------------------------------*/\r
+/** @defgroup UART_Exported_Macros UART Exported Macros\r
+ * @{\r
+ */\r
+\r
+/** @brief Reset UART handle gstate & RxState\r
+ * @param __HANDLE__ specifies the UART Handle.\r
+ * UART Handle selects the USARTx or UARTy peripheral\r
+ * (USART,UART availability and x,y values depending on device).\r
+ * @retval None\r
+ */\r
+#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)\r
+#define __HAL_UART_RESET_HANDLE_STATE(__HANDLE__) do{ \\r
+ (__HANDLE__)->gState = HAL_UART_STATE_RESET; \\r
+ (__HANDLE__)->RxState = HAL_UART_STATE_RESET; \\r
+ (__HANDLE__)->MspInitCallback = NULL; \\r
+ (__HANDLE__)->MspDeInitCallback = NULL; \\r
+ } while(0U)\r
+#else\r
+#define __HAL_UART_RESET_HANDLE_STATE(__HANDLE__) do{ \\r
+ (__HANDLE__)->gState = HAL_UART_STATE_RESET; \\r
+ (__HANDLE__)->RxState = HAL_UART_STATE_RESET; \\r
+ } while(0U)\r
+#endif /*USE_HAL_UART_REGISTER_CALLBACKS */\r
+\r
+/** @brief Flushes the UART DR register\r
+ * @param __HANDLE__ specifies the UART Handle.\r
+ * UART Handle selects the USARTx or UARTy peripheral\r
+ * (USART,UART availability and x,y values depending on device).\r
+ */\r
+#define __HAL_UART_FLUSH_DRREGISTER(__HANDLE__) ((__HANDLE__)->Instance->DR)\r
+\r
+/** @brief Checks whether the specified UART flag is set or not.\r
+ * @param __HANDLE__ specifies the UART Handle.\r
+ * UART Handle selects the USARTx or UARTy peripheral\r
+ * (USART,UART availability and x,y values depending on device).\r
+ * @param __FLAG__ specifies the flag to check.\r
+ * This parameter can be one of the following values:\r
+ * @arg UART_FLAG_CTS: CTS Change flag (not available for UART4 and UART5)\r
+ * @arg UART_FLAG_LBD: LIN Break detection flag\r
+ * @arg UART_FLAG_TXE: Transmit data register empty flag\r
+ * @arg UART_FLAG_TC: Transmission Complete flag\r
+ * @arg UART_FLAG_RXNE: Receive data register not empty flag\r
+ * @arg UART_FLAG_IDLE: Idle Line detection flag\r
+ * @arg UART_FLAG_ORE: Overrun Error flag\r
+ * @arg UART_FLAG_NE: Noise Error flag\r
+ * @arg UART_FLAG_FE: Framing Error flag\r
+ * @arg UART_FLAG_PE: Parity Error flag\r
+ * @retval The new state of __FLAG__ (TRUE or FALSE).\r
+ */\r
+#define __HAL_UART_GET_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->SR & (__FLAG__)) == (__FLAG__))\r
+\r
+/** @brief Clears the specified UART pending flag.\r
+ * @param __HANDLE__ specifies the UART Handle.\r
+ * UART Handle selects the USARTx or UARTy peripheral\r
+ * (USART,UART availability and x,y values depending on device).\r
+ * @param __FLAG__ specifies the flag to check.\r
+ * This parameter can be any combination of the following values:\r
+ * @arg UART_FLAG_CTS: CTS Change flag (not available for UART4 and UART5).\r
+ * @arg UART_FLAG_LBD: LIN Break detection flag.\r
+ * @arg UART_FLAG_TC: Transmission Complete flag.\r
+ * @arg UART_FLAG_RXNE: Receive data register not empty flag.\r
+ *\r
+ * @note PE (Parity error), FE (Framing error), NE (Noise error), ORE (Overrun\r
+ * error) and IDLE (Idle line detected) flags are cleared by software\r
+ * sequence: a read operation to USART_SR register followed by a read\r
+ * operation to USART_DR register.\r
+ * @note RXNE flag can be also cleared by a read to the USART_DR register.\r
+ * @note TC flag can be also cleared by software sequence: a read operation to\r
+ * USART_SR register followed by a write operation to USART_DR register.\r
+ * @note TXE flag is cleared only by a write to the USART_DR register.\r
+ *\r
+ * @retval None\r
+ */\r
+#define __HAL_UART_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->SR = ~(__FLAG__))\r
+\r
+/** @brief Clears the UART PE pending flag.\r
+ * @param __HANDLE__ specifies the UART Handle.\r
+ * UART Handle selects the USARTx or UARTy peripheral\r
+ * (USART,UART availability and x,y values depending on device).\r
+ * @retval None\r
+ */\r
+#define __HAL_UART_CLEAR_PEFLAG(__HANDLE__) \\r
+ do{ \\r
+ __IO uint32_t tmpreg = 0x00U; \\r
+ tmpreg = (__HANDLE__)->Instance->SR; \\r
+ tmpreg = (__HANDLE__)->Instance->DR; \\r
+ UNUSED(tmpreg); \\r
+ } while(0U)\r
+\r
+/** @brief Clears the UART FE pending flag.\r
+ * @param __HANDLE__ specifies the UART Handle.\r
+ * UART Handle selects the USARTx or UARTy peripheral\r
+ * (USART,UART availability and x,y values depending on device).\r
+ * @retval None\r
+ */\r
+#define __HAL_UART_CLEAR_FEFLAG(__HANDLE__) __HAL_UART_CLEAR_PEFLAG(__HANDLE__)\r
+\r
+/** @brief Clears the UART NE pending flag.\r
+ * @param __HANDLE__ specifies the UART Handle.\r
+ * UART Handle selects the USARTx or UARTy peripheral\r
+ * (USART,UART availability and x,y values depending on device).\r
+ * @retval None\r
+ */\r
+#define __HAL_UART_CLEAR_NEFLAG(__HANDLE__) __HAL_UART_CLEAR_PEFLAG(__HANDLE__)\r
+\r
+/** @brief Clears the UART ORE pending flag.\r
+ * @param __HANDLE__ specifies the UART Handle.\r
+ * UART Handle selects the USARTx or UARTy peripheral\r
+ * (USART,UART availability and x,y values depending on device).\r
+ * @retval None\r
+ */\r
+#define __HAL_UART_CLEAR_OREFLAG(__HANDLE__) __HAL_UART_CLEAR_PEFLAG(__HANDLE__)\r
+\r
+/** @brief Clears the UART IDLE pending flag.\r
+ * @param __HANDLE__ specifies the UART Handle.\r
+ * UART Handle selects the USARTx or UARTy peripheral\r
+ * (USART,UART availability and x,y values depending on device).\r
+ * @retval None\r
+ */\r
+#define __HAL_UART_CLEAR_IDLEFLAG(__HANDLE__) __HAL_UART_CLEAR_PEFLAG(__HANDLE__)\r
+\r
+/** @brief Enable the specified UART interrupt.\r
+ * @param __HANDLE__ specifies the UART Handle.\r
+ * UART Handle selects the USARTx or UARTy peripheral\r
+ * (USART,UART availability and x,y values depending on device).\r
+ * @param __INTERRUPT__ specifies the UART interrupt source to enable.\r
+ * This parameter can be one of the following values:\r
+ * @arg UART_IT_CTS: CTS change interrupt\r
+ * @arg UART_IT_LBD: LIN Break detection interrupt\r
+ * @arg UART_IT_TXE: Transmit Data Register empty interrupt\r
+ * @arg UART_IT_TC: Transmission complete interrupt\r
+ * @arg UART_IT_RXNE: Receive Data register not empty interrupt\r
+ * @arg UART_IT_IDLE: Idle line detection interrupt\r
+ * @arg UART_IT_PE: Parity Error interrupt\r
+ * @arg UART_IT_ERR: Error interrupt(Frame error, noise error, overrun error)\r
+ * @retval None\r
+ */\r
+#define __HAL_UART_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((((__INTERRUPT__) >> 28U) == UART_CR1_REG_INDEX)? ((__HANDLE__)->Instance->CR1 |= ((__INTERRUPT__) & UART_IT_MASK)): \\r
+ (((__INTERRUPT__) >> 28U) == UART_CR2_REG_INDEX)? ((__HANDLE__)->Instance->CR2 |= ((__INTERRUPT__) & UART_IT_MASK)): \\r
+ ((__HANDLE__)->Instance->CR3 |= ((__INTERRUPT__) & UART_IT_MASK)))\r
+\r
+/** @brief Disable the specified UART interrupt.\r
+ * @param __HANDLE__ specifies the UART Handle.\r
+ * UART Handle selects the USARTx or UARTy peripheral\r
+ * (USART,UART availability and x,y values depending on device).\r
+ * @param __INTERRUPT__ specifies the UART interrupt source to disable.\r
+ * This parameter can be one of the following values:\r
+ * @arg UART_IT_CTS: CTS change interrupt\r
+ * @arg UART_IT_LBD: LIN Break detection interrupt\r
+ * @arg UART_IT_TXE: Transmit Data Register empty interrupt\r
+ * @arg UART_IT_TC: Transmission complete interrupt\r
+ * @arg UART_IT_RXNE: Receive Data register not empty interrupt\r
+ * @arg UART_IT_IDLE: Idle line detection interrupt\r
+ * @arg UART_IT_PE: Parity Error interrupt\r
+ * @arg UART_IT_ERR: Error interrupt(Frame error, noise error, overrun error)\r
+ * @retval None\r
+ */\r
+#define __HAL_UART_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((((__INTERRUPT__) >> 28U) == UART_CR1_REG_INDEX)? ((__HANDLE__)->Instance->CR1 &= ~((__INTERRUPT__) & UART_IT_MASK)): \\r
+ (((__INTERRUPT__) >> 28U) == UART_CR2_REG_INDEX)? ((__HANDLE__)->Instance->CR2 &= ~((__INTERRUPT__) & UART_IT_MASK)): \\r
+ ((__HANDLE__)->Instance->CR3 &= ~ ((__INTERRUPT__) & UART_IT_MASK)))\r
+\r
+/** @brief Checks whether the specified UART interrupt has occurred or not.\r
+ * @param __HANDLE__ specifies the UART Handle.\r
+ * UART Handle selects the USARTx or UARTy peripheral\r
+ * (USART,UART availability and x,y values depending on device).\r
+ * @param __IT__ specifies the UART interrupt source to check.\r
+ * This parameter can be one of the following values:\r
+ * @arg UART_IT_CTS: CTS change interrupt (not available for UART4 and UART5)\r
+ * @arg UART_IT_LBD: LIN Break detection interrupt\r
+ * @arg UART_IT_TXE: Transmit Data Register empty interrupt\r
+ * @arg UART_IT_TC: Transmission complete interrupt\r
+ * @arg UART_IT_RXNE: Receive Data register not empty interrupt\r
+ * @arg UART_IT_IDLE: Idle line detection interrupt\r
+ * @arg UART_IT_ERR: Error interrupt\r
+ * @retval The new state of __IT__ (TRUE or FALSE).\r
+ */\r
+#define __HAL_UART_GET_IT_SOURCE(__HANDLE__, __IT__) (((((__IT__) >> 28U) == UART_CR1_REG_INDEX)? (__HANDLE__)->Instance->CR1:(((((uint32_t)(__IT__)) >> 28U) == UART_CR2_REG_INDEX)? \\r
+ (__HANDLE__)->Instance->CR2 : (__HANDLE__)->Instance->CR3)) & (((uint32_t)(__IT__)) & UART_IT_MASK))\r
+\r
+/** @brief Enable CTS flow control\r
+ * @note This macro allows to enable CTS hardware flow control for a given UART instance,\r
+ * without need to call HAL_UART_Init() function.\r
+ * As involving direct access to UART registers, usage of this macro should be fully endorsed by user.\r
+ * @note As macro is expected to be used for modifying CTS Hw flow control feature activation, without need\r
+ * for USART instance Deinit/Init, following conditions for macro call should be fulfilled :\r
+ * - UART instance should have already been initialised (through call of HAL_UART_Init() )\r
+ * - macro could only be called when corresponding UART instance is disabled (i.e __HAL_UART_DISABLE(__HANDLE__))\r
+ * and should be followed by an Enable macro (i.e __HAL_UART_ENABLE(__HANDLE__)).\r
+ * @param __HANDLE__ specifies the UART Handle.\r
+ * The Handle Instance can be any USARTx (supporting the HW Flow control feature).\r
+ * It is used to select the USART peripheral (USART availability and x value depending on device).\r
+ * @retval None\r
+ */\r
+#define __HAL_UART_HWCONTROL_CTS_ENABLE(__HANDLE__) \\r
+ do{ \\r
+ SET_BIT((__HANDLE__)->Instance->CR3, USART_CR3_CTSE); \\r
+ (__HANDLE__)->Init.HwFlowCtl |= USART_CR3_CTSE; \\r
+ } while(0U)\r
+\r
+/** @brief Disable CTS flow control\r
+ * @note This macro allows to disable CTS hardware flow control for a given UART instance,\r
+ * without need to call HAL_UART_Init() function.\r
+ * As involving direct access to UART registers, usage of this macro should be fully endorsed by user.\r
+ * @note As macro is expected to be used for modifying CTS Hw flow control feature activation, without need\r
+ * for USART instance Deinit/Init, following conditions for macro call should be fulfilled :\r
+ * - UART instance should have already been initialised (through call of HAL_UART_Init() )\r
+ * - macro could only be called when corresponding UART instance is disabled (i.e __HAL_UART_DISABLE(__HANDLE__))\r
+ * and should be followed by an Enable macro (i.e __HAL_UART_ENABLE(__HANDLE__)).\r
+ * @param __HANDLE__ specifies the UART Handle.\r
+ * The Handle Instance can be any USARTx (supporting the HW Flow control feature).\r
+ * It is used to select the USART peripheral (USART availability and x value depending on device).\r
+ * @retval None\r
+ */\r
+#define __HAL_UART_HWCONTROL_CTS_DISABLE(__HANDLE__) \\r
+ do{ \\r
+ CLEAR_BIT((__HANDLE__)->Instance->CR3, USART_CR3_CTSE); \\r
+ (__HANDLE__)->Init.HwFlowCtl &= ~(USART_CR3_CTSE); \\r
+ } while(0U)\r
+\r
+/** @brief Enable RTS flow control\r
+ * This macro allows to enable RTS hardware flow control for a given UART instance,\r
+ * without need to call HAL_UART_Init() function.\r
+ * As involving direct access to UART registers, usage of this macro should be fully endorsed by user.\r
+ * @note As macro is expected to be used for modifying RTS Hw flow control feature activation, without need\r
+ * for USART instance Deinit/Init, following conditions for macro call should be fulfilled :\r
+ * - UART instance should have already been initialised (through call of HAL_UART_Init() )\r
+ * - macro could only be called when corresponding UART instance is disabled (i.e __HAL_UART_DISABLE(__HANDLE__))\r
+ * and should be followed by an Enable macro (i.e __HAL_UART_ENABLE(__HANDLE__)).\r
+ * @param __HANDLE__ specifies the UART Handle.\r
+ * The Handle Instance can be any USARTx (supporting the HW Flow control feature).\r
+ * It is used to select the USART peripheral (USART availability and x value depending on device).\r
+ * @retval None\r
+ */\r
+#define __HAL_UART_HWCONTROL_RTS_ENABLE(__HANDLE__) \\r
+ do{ \\r
+ SET_BIT((__HANDLE__)->Instance->CR3, USART_CR3_RTSE); \\r
+ (__HANDLE__)->Init.HwFlowCtl |= USART_CR3_RTSE; \\r
+ } while(0U)\r
+\r
+/** @brief Disable RTS flow control\r
+ * This macro allows to disable RTS hardware flow control for a given UART instance,\r
+ * without need to call HAL_UART_Init() function.\r
+ * As involving direct access to UART registers, usage of this macro should be fully endorsed by user.\r
+ * @note As macro is expected to be used for modifying RTS Hw flow control feature activation, without need\r
+ * for USART instance Deinit/Init, following conditions for macro call should be fulfilled :\r
+ * - UART instance should have already been initialised (through call of HAL_UART_Init() )\r
+ * - macro could only be called when corresponding UART instance is disabled (i.e __HAL_UART_DISABLE(__HANDLE__))\r
+ * and should be followed by an Enable macro (i.e __HAL_UART_ENABLE(__HANDLE__)).\r
+ * @param __HANDLE__ specifies the UART Handle.\r
+ * The Handle Instance can be any USARTx (supporting the HW Flow control feature).\r
+ * It is used to select the USART peripheral (USART availability and x value depending on device).\r
+ * @retval None\r
+ */\r
+#define __HAL_UART_HWCONTROL_RTS_DISABLE(__HANDLE__) \\r
+ do{ \\r
+ CLEAR_BIT((__HANDLE__)->Instance->CR3, USART_CR3_RTSE);\\r
+ (__HANDLE__)->Init.HwFlowCtl &= ~(USART_CR3_RTSE); \\r
+ } while(0U)\r
+\r
+/** @brief Macro to enable the UART's one bit sample method\r
+ * @param __HANDLE__ specifies the UART Handle.\r
+ * @retval None\r
+ */\r
+#define __HAL_UART_ONE_BIT_SAMPLE_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR3|= USART_CR3_ONEBIT)\r
+\r
+/** @brief Macro to disable the UART's one bit sample method\r
+ * @param __HANDLE__ specifies the UART Handle.\r
+ * @retval None\r
+ */\r
+#define __HAL_UART_ONE_BIT_SAMPLE_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR3 &= (uint16_t)~((uint16_t)USART_CR3_ONEBIT))\r
+\r
+/** @brief Enable UART\r
+ * @param __HANDLE__ specifies the UART Handle.\r
+ * @retval None\r
+ */\r
+#define __HAL_UART_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1 |= USART_CR1_UE)\r
+\r
+/** @brief Disable UART\r
+ * @param __HANDLE__ specifies the UART Handle.\r
+ * @retval None\r
+ */\r
+#define __HAL_UART_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1 &= ~USART_CR1_UE)\r
+/**\r
+ * @}\r
+ */\r
+\r
+/* Exported functions --------------------------------------------------------*/\r
+/** @addtogroup UART_Exported_Functions\r
+ * @{\r
+ */\r
+\r
+/** @addtogroup UART_Exported_Functions_Group1 Initialization and de-initialization functions\r
+ * @{\r
+ */\r
+\r
+/* Initialization/de-initialization functions **********************************/\r
+HAL_StatusTypeDef HAL_UART_Init(UART_HandleTypeDef *huart);\r
+HAL_StatusTypeDef HAL_HalfDuplex_Init(UART_HandleTypeDef *huart);\r
+HAL_StatusTypeDef HAL_LIN_Init(UART_HandleTypeDef *huart, uint32_t BreakDetectLength);\r
+HAL_StatusTypeDef HAL_MultiProcessor_Init(UART_HandleTypeDef *huart, uint8_t Address, uint32_t WakeUpMethod);\r
+HAL_StatusTypeDef HAL_UART_DeInit(UART_HandleTypeDef *huart);\r
+void HAL_UART_MspInit(UART_HandleTypeDef *huart);\r
+void HAL_UART_MspDeInit(UART_HandleTypeDef *huart);\r
+\r
+/* Callbacks Register/UnRegister functions ***********************************/\r
+#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)\r
+HAL_StatusTypeDef HAL_UART_RegisterCallback(UART_HandleTypeDef *huart, HAL_UART_CallbackIDTypeDef CallbackID, pUART_CallbackTypeDef pCallback);\r
+HAL_StatusTypeDef HAL_UART_UnRegisterCallback(UART_HandleTypeDef *huart, HAL_UART_CallbackIDTypeDef CallbackID);\r
+#endif /* USE_HAL_UART_REGISTER_CALLBACKS */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @addtogroup UART_Exported_Functions_Group2 IO operation functions\r
+ * @{\r
+ */\r
+\r
+/* IO operation functions *******************************************************/\r
+HAL_StatusTypeDef HAL_UART_Transmit(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size, uint32_t Timeout);\r
+HAL_StatusTypeDef HAL_UART_Receive(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size, uint32_t Timeout);\r
+HAL_StatusTypeDef HAL_UART_Transmit_IT(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size);\r
+HAL_StatusTypeDef HAL_UART_Receive_IT(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size);\r
+HAL_StatusTypeDef HAL_UART_Transmit_DMA(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size);\r
+HAL_StatusTypeDef HAL_UART_Receive_DMA(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size);\r
+HAL_StatusTypeDef HAL_UART_DMAPause(UART_HandleTypeDef *huart);\r
+HAL_StatusTypeDef HAL_UART_DMAResume(UART_HandleTypeDef *huart);\r
+HAL_StatusTypeDef HAL_UART_DMAStop(UART_HandleTypeDef *huart);\r
+/* Transfer Abort functions */\r
+HAL_StatusTypeDef HAL_UART_Abort(UART_HandleTypeDef *huart);\r
+HAL_StatusTypeDef HAL_UART_AbortTransmit(UART_HandleTypeDef *huart);\r
+HAL_StatusTypeDef HAL_UART_AbortReceive(UART_HandleTypeDef *huart);\r
+HAL_StatusTypeDef HAL_UART_Abort_IT(UART_HandleTypeDef *huart);\r
+HAL_StatusTypeDef HAL_UART_AbortTransmit_IT(UART_HandleTypeDef *huart);\r
+HAL_StatusTypeDef HAL_UART_AbortReceive_IT(UART_HandleTypeDef *huart);\r
+\r
+void HAL_UART_IRQHandler(UART_HandleTypeDef *huart);\r
+void HAL_UART_TxCpltCallback(UART_HandleTypeDef *huart);\r
+void HAL_UART_TxHalfCpltCallback(UART_HandleTypeDef *huart);\r
+void HAL_UART_RxCpltCallback(UART_HandleTypeDef *huart);\r
+void HAL_UART_RxHalfCpltCallback(UART_HandleTypeDef *huart);\r
+void HAL_UART_ErrorCallback(UART_HandleTypeDef *huart);\r
+void HAL_UART_AbortCpltCallback(UART_HandleTypeDef *huart);\r
+void HAL_UART_AbortTransmitCpltCallback(UART_HandleTypeDef *huart);\r
+void HAL_UART_AbortReceiveCpltCallback(UART_HandleTypeDef *huart);\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @addtogroup UART_Exported_Functions_Group3\r
+ * @{\r
+ */\r
+/* Peripheral Control functions ************************************************/\r
+HAL_StatusTypeDef HAL_LIN_SendBreak(UART_HandleTypeDef *huart);\r
+HAL_StatusTypeDef HAL_MultiProcessor_EnterMuteMode(UART_HandleTypeDef *huart);\r
+HAL_StatusTypeDef HAL_MultiProcessor_ExitMuteMode(UART_HandleTypeDef *huart);\r
+HAL_StatusTypeDef HAL_HalfDuplex_EnableTransmitter(UART_HandleTypeDef *huart);\r
+HAL_StatusTypeDef HAL_HalfDuplex_EnableReceiver(UART_HandleTypeDef *huart);\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @addtogroup UART_Exported_Functions_Group4\r
+ * @{\r
+ */\r
+/* Peripheral State functions **************************************************/\r
+HAL_UART_StateTypeDef HAL_UART_GetState(UART_HandleTypeDef *huart);\r
+uint32_t HAL_UART_GetError(UART_HandleTypeDef *huart);\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+/* Private types -------------------------------------------------------------*/\r
+/* Private variables ---------------------------------------------------------*/\r
+/* Private constants ---------------------------------------------------------*/\r
+/** @defgroup UART_Private_Constants UART Private Constants\r
+ * @{\r
+ */\r
+/** @brief UART interruptions flag mask\r
+ *\r
+ */\r
+#define UART_IT_MASK 0x0000FFFFU\r
+\r
+#define UART_CR1_REG_INDEX 1U\r
+#define UART_CR2_REG_INDEX 2U\r
+#define UART_CR3_REG_INDEX 3U\r
+/**\r
+ * @}\r
+ */\r
+\r
+/* Private macros ------------------------------------------------------------*/\r
+/** @defgroup UART_Private_Macros UART Private Macros\r
+ * @{\r
+ */\r
+#define IS_UART_WORD_LENGTH(LENGTH) (((LENGTH) == UART_WORDLENGTH_8B) || \\r
+ ((LENGTH) == UART_WORDLENGTH_9B))\r
+#define IS_UART_LIN_WORD_LENGTH(LENGTH) (((LENGTH) == UART_WORDLENGTH_8B))\r
+#define IS_UART_STOPBITS(STOPBITS) (((STOPBITS) == UART_STOPBITS_1) || \\r
+ ((STOPBITS) == UART_STOPBITS_2))\r
+#define IS_UART_PARITY(PARITY) (((PARITY) == UART_PARITY_NONE) || \\r
+ ((PARITY) == UART_PARITY_EVEN) || \\r
+ ((PARITY) == UART_PARITY_ODD))\r
+#define IS_UART_HARDWARE_FLOW_CONTROL(CONTROL)\\r
+ (((CONTROL) == UART_HWCONTROL_NONE) || \\r
+ ((CONTROL) == UART_HWCONTROL_RTS) || \\r
+ ((CONTROL) == UART_HWCONTROL_CTS) || \\r
+ ((CONTROL) == UART_HWCONTROL_RTS_CTS))\r
+#define IS_UART_MODE(MODE) ((((MODE) & 0x0000FFF3U) == 0x00U) && ((MODE) != 0x00U))\r
+#define IS_UART_STATE(STATE) (((STATE) == UART_STATE_DISABLE) || \\r
+ ((STATE) == UART_STATE_ENABLE))\r
+#define IS_UART_OVERSAMPLING(SAMPLING) (((SAMPLING) == UART_OVERSAMPLING_16) || \\r
+ ((SAMPLING) == UART_OVERSAMPLING_8))\r
+#define IS_UART_LIN_OVERSAMPLING(SAMPLING) (((SAMPLING) == UART_OVERSAMPLING_16))\r
+#define IS_UART_LIN_BREAK_DETECT_LENGTH(LENGTH) (((LENGTH) == UART_LINBREAKDETECTLENGTH_10B) || \\r
+ ((LENGTH) == UART_LINBREAKDETECTLENGTH_11B))\r
+#define IS_UART_WAKEUPMETHOD(WAKEUP) (((WAKEUP) == UART_WAKEUPMETHOD_IDLELINE) || \\r
+ ((WAKEUP) == UART_WAKEUPMETHOD_ADDRESSMARK))\r
+#define IS_UART_BAUDRATE(BAUDRATE) ((BAUDRATE) <= 4000000U)\r
+#define IS_UART_ADDRESS(ADDRESS) ((ADDRESS) <= 0x0FU)\r
+\r
+#define UART_DIV_SAMPLING16(_PCLK_, _BAUD_) (((_PCLK_)*25U)/(4U*(_BAUD_)))\r
+#define UART_DIVMANT_SAMPLING16(_PCLK_, _BAUD_) (UART_DIV_SAMPLING16((_PCLK_), (_BAUD_))/100U)\r
+#define UART_DIVFRAQ_SAMPLING16(_PCLK_, _BAUD_) (((UART_DIV_SAMPLING16((_PCLK_), (_BAUD_)) - (UART_DIVMANT_SAMPLING16((_PCLK_), (_BAUD_)) * 100U)) * 16U + 50U) / 100U)\r
+/* UART BRR = mantissa + overflow + fraction\r
+ = (UART DIVMANT << 4) + (UART DIVFRAQ & 0xF0) + (UART DIVFRAQ & 0x0FU) */\r
+#define UART_BRR_SAMPLING16(_PCLK_, _BAUD_) (((UART_DIVMANT_SAMPLING16((_PCLK_), (_BAUD_)) << 4U) + \\r
+ (UART_DIVFRAQ_SAMPLING16((_PCLK_), (_BAUD_)) & 0xF0U)) + \\r
+ (UART_DIVFRAQ_SAMPLING16((_PCLK_), (_BAUD_)) & 0x0FU))\r
+\r
+#define UART_DIV_SAMPLING8(_PCLK_, _BAUD_) (((_PCLK_)*25U)/(2U*(_BAUD_)))\r
+#define UART_DIVMANT_SAMPLING8(_PCLK_, _BAUD_) (UART_DIV_SAMPLING8((_PCLK_), (_BAUD_))/100U)\r
+#define UART_DIVFRAQ_SAMPLING8(_PCLK_, _BAUD_) (((UART_DIV_SAMPLING8((_PCLK_), (_BAUD_)) - (UART_DIVMANT_SAMPLING8((_PCLK_), (_BAUD_)) * 100U)) * 8U + 50U) / 100U)\r
+/* UART BRR = mantissa + overflow + fraction\r
+ = (UART DIVMANT << 4) + ((UART DIVFRAQ & 0xF8) << 1) + (UART DIVFRAQ & 0x07U) */\r
+#define UART_BRR_SAMPLING8(_PCLK_, _BAUD_) (((UART_DIVMANT_SAMPLING8((_PCLK_), (_BAUD_)) << 4U) + \\r
+ ((UART_DIVFRAQ_SAMPLING8((_PCLK_), (_BAUD_)) & 0xF8U) << 1U)) + \\r
+ (UART_DIVFRAQ_SAMPLING8((_PCLK_), (_BAUD_)) & 0x07U))\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/* Private functions ---------------------------------------------------------*/\r
+/** @defgroup UART_Private_Functions UART Private Functions\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+#ifdef __cplusplus\r
+}\r
+#endif\r
+\r
+#endif /* __STM32L1xx_HAL_UART_H */\r
+\r
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\r
--- /dev/null
+/**\r
+ ******************************************************************************\r
+ * @file stm32l1xx_hal.c\r
+ * @author MCD Application Team\r
+ * @brief HAL module driver.\r
+ * This is the common part of the HAL initialization\r
+ *\r
+ @verbatim\r
+ ==============================================================================\r
+ ##### How to use this driver #####\r
+ ==============================================================================\r
+ [..]\r
+ The common HAL driver contains a set of generic and common APIs that can be\r
+ used by the PPP peripheral drivers and the user to start using the HAL.\r
+ [..]\r
+ The HAL contains two APIs categories:\r
+ (+) Common HAL APIs\r
+ (+) Services HAL APIs\r
+\r
+ @endverbatim\r
+ ******************************************************************************\r
+ * @attention\r
+ *\r
+ * <h2><center>© Copyright (c) 2017 STMicroelectronics.\r
+ * All rights reserved.</center></h2>\r
+ *\r
+ * This software component is licensed by ST under BSD 3-Clause license,\r
+ * the "License"; You may not use this file except in compliance with the\r
+ * License. You may obtain a copy of the License at:\r
+ * opensource.org/licenses/BSD-3-Clause\r
+ *\r
+ ******************************************************************************\r
+ */\r
+\r
+/* Includes ------------------------------------------------------------------*/\r
+#include "stm32l1xx_hal.h"\r
+\r
+/** @addtogroup STM32L1xx_HAL_Driver\r
+ * @{\r
+ */\r
+\r
+/** @defgroup HAL HAL\r
+ * @brief HAL module driver.\r
+ * @{\r
+ */\r
+\r
+#ifdef HAL_MODULE_ENABLED\r
+\r
+/* Private typedef -----------------------------------------------------------*/\r
+/* Private define ------------------------------------------------------------*/\r
+\r
+/** @defgroup HAL_Private_Defines HAL Private Defines\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @brief STM32L1xx HAL Driver version number\r
+ */\r
+#define __STM32L1xx_HAL_VERSION_MAIN (0x01) /*!< [31:24] main version */\r
+#define __STM32L1xx_HAL_VERSION_SUB1 (0x04) /*!< [23:16] sub1 version */\r
+#define __STM32L1xx_HAL_VERSION_SUB2 (0x00) /*!< [15:8] sub2 version */\r
+#define __STM32L1xx_HAL_VERSION_RC (0x00) /*!< [7:0] release candidate */\r
+#define __STM32L1xx_HAL_VERSION ((__STM32L1xx_HAL_VERSION_MAIN << 24)\\r
+ |(__STM32L1xx_HAL_VERSION_SUB1 << 16)\\r
+ |(__STM32L1xx_HAL_VERSION_SUB2 << 8 )\\r
+ |(__STM32L1xx_HAL_VERSION_RC))\r
+\r
+#define IDCODE_DEVID_MASK (0x00000FFFU)\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/* Private macro -------------------------------------------------------------*/\r
+/* Private variables ---------------------------------------------------------*/\r
+/* Private function prototypes -----------------------------------------------*/\r
+/* Private functions ---------------------------------------------------------*/\r
+\r
+/* Exported variables --------------------------------------------------------*/\r
+/** @addtogroup HAL_Exported_Variables\r
+ * @{\r
+ */\r
+__IO uint32_t uwTick;\r
+uint32_t uwTickPrio = (1UL << __NVIC_PRIO_BITS); /* Invalid priority */\r
+uint32_t uwTickFreq = HAL_TICK_FREQ_DEFAULT; /* 1KHz */\r
+/**\r
+ * @}\r
+ */\r
+\r
+/* Exported functions --------------------------------------------------------*/\r
+/** @defgroup HAL_Exported_Functions HAL Exported Functions\r
+ * @{\r
+ */\r
+\r
+/** @defgroup HAL_Exported_Functions_Group1 Initialization and de-initialization Functions\r
+ * @brief Initialization and de-initialization functions\r
+ *\r
+@verbatim\r
+ ===============================================================================\r
+ ##### Initialization and de-initialization functions #####\r
+ ===============================================================================\r
+ [..] This section provides functions allowing to:\r
+ (+) Initialize the Flash interface, the NVIC allocation and initial clock\r
+ configuration. It initializes the source of time base also when timeout\r
+ is needed and the backup domain when enabled.\r
+ (+) De-initialize common part of the HAL.\r
+ (+) Configure the time base source to have 1ms time base with a dedicated\r
+ Tick interrupt priority.\r
+ (++) SysTick timer is used by default as source of time base, but user\r
+ can eventually implement his proper time base source (a general purpose\r
+ timer for example or other time source), keeping in mind that Time base\r
+ duration should be kept 1ms since PPP_TIMEOUT_VALUEs are defined and\r
+ handled in milliseconds basis.\r
+ (++) Time base configuration function (HAL_InitTick ()) is called automatically\r
+ at the beginning of the program after reset by HAL_Init() or at any time\r
+ when clock is configured, by HAL_RCC_ClockConfig().\r
+ (++) Source of time base is configured to generate interrupts at regular\r
+ time intervals. Care must be taken if HAL_Delay() is called from a\r
+ peripheral ISR process, the Tick interrupt line must have higher priority\r
+ (numerically lower) than the peripheral interrupt. Otherwise the caller\r
+ ISR process will be blocked.\r
+ (++) functions affecting time base configurations are declared as __weak\r
+ to make override possible in case of other implementations in user file.\r
+\r
+@endverbatim\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @brief This function configures the Flash prefetch,\r
+ * configures time base source, NVIC and Low level hardware\r
+ * @note This function is called at the beginning of program after reset and before\r
+ * the clock configuration\r
+ * @note The time base configuration is based on MSI clock when exiting from Reset.\r
+ * Once done, time base tick start incrementing.\r
+ * In the default implementation,Systick is used as source of time base.\r
+ * the tick variable is incremented each 1ms in its ISR.\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_Init(void)\r
+{\r
+ HAL_StatusTypeDef status = HAL_OK;\r
+\r
+ /* Configure Flash prefetch */\r
+#if (PREFETCH_ENABLE != 0)\r
+ __HAL_FLASH_PREFETCH_BUFFER_ENABLE();\r
+#endif /* PREFETCH_ENABLE */\r
+\r
+ /* Set Interrupt Group Priority */\r
+ HAL_NVIC_SetPriorityGrouping(NVIC_PRIORITYGROUP_4);\r
+\r
+ /* Use systick as time base source and configure 1ms tick (default clock after Reset is MSI) */\r
+ if (HAL_InitTick(TICK_INT_PRIORITY) != HAL_OK)\r
+ {\r
+ status = HAL_ERROR;\r
+ }\r
+ else\r
+ {\r
+ /* Init the low level hardware */\r
+ HAL_MspInit();\r
+ }\r
+\r
+ /* Return function status */\r
+ return status;\r
+}\r
+\r
+/**\r
+ * @brief This function de-initializes common part of the HAL and stops the source\r
+ * of time base.\r
+ * @note This function is optional.\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_DeInit(void)\r
+{\r
+ /* Reset of all peripherals */\r
+ __HAL_RCC_APB1_FORCE_RESET();\r
+ __HAL_RCC_APB1_RELEASE_RESET();\r
+\r
+ __HAL_RCC_APB2_FORCE_RESET();\r
+ __HAL_RCC_APB2_RELEASE_RESET();\r
+\r
+ __HAL_RCC_AHB_FORCE_RESET();\r
+ __HAL_RCC_AHB_RELEASE_RESET();\r
+\r
+ /* De-Init the low level hardware */\r
+ HAL_MspDeInit();\r
+\r
+ /* Return function status */\r
+ return HAL_OK;\r
+}\r
+\r
+/**\r
+ * @brief Initialize the MSP.\r
+ * @retval None\r
+ */\r
+__weak void HAL_MspInit(void)\r
+{\r
+ /* NOTE : This function should not be modified, when the callback is needed,\r
+ the HAL_MspInit could be implemented in the user file\r
+ */\r
+}\r
+\r
+/**\r
+ * @brief DeInitialize the MSP.\r
+ * @retval None\r
+ */\r
+__weak void HAL_MspDeInit(void)\r
+{\r
+ /* NOTE : This function should not be modified, when the callback is needed,\r
+ the HAL_MspDeInit could be implemented in the user file\r
+ */\r
+}\r
+\r
+/**\r
+ * @brief This function configures the source of the time base:\r
+ * The time source is configured to have 1ms time base with a dedicated\r
+ * Tick interrupt priority.\r
+ * @note This function is called automatically at the beginning of program after\r
+ * reset by HAL_Init() or at any time when clock is reconfigured by HAL_RCC_ClockConfig().\r
+ * @note In the default implementation, SysTick timer is the source of time base.\r
+ * It is used to generate interrupts at regular time intervals.\r
+ * Care must be taken if HAL_Delay() is called from a peripheral ISR process,\r
+ * The SysTick interrupt must have higher priority (numerically lower)\r
+ * than the peripheral interrupt. Otherwise the caller ISR process will be blocked.\r
+ * The function is declared as __weak to be overwritten in case of other\r
+ * implementation in user file.\r
+ * @param TickPriority Tick interrupt priority.\r
+ * @retval HAL status\r
+ */\r
+__weak HAL_StatusTypeDef HAL_InitTick(uint32_t TickPriority)\r
+{\r
+ HAL_StatusTypeDef status = HAL_OK;\r
+\r
+ if (uwTickFreq != 0U)\r
+ {\r
+ /*Configure the SysTick to have interrupt in 1ms time basis*/\r
+ if (HAL_SYSTICK_Config(SystemCoreClock / (1000U / uwTickFreq)) == 0U)\r
+ {\r
+ /* Configure the SysTick IRQ priority */\r
+ if (TickPriority < (1UL << __NVIC_PRIO_BITS))\r
+ {\r
+ HAL_NVIC_SetPriority(SysTick_IRQn, TickPriority, 0U);\r
+ uwTickPrio = TickPriority;\r
+ }\r
+ else\r
+ {\r
+ status = HAL_ERROR;\r
+ }\r
+ }\r
+ else\r
+ {\r
+ status = HAL_ERROR;\r
+ }\r
+ }\r
+ else\r
+ {\r
+ status = HAL_ERROR;\r
+ }\r
+\r
+ /* Return function status */\r
+ return status;\r
+}\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup HAL_Exported_Functions_Group2 HAL Control functions\r
+ * @brief HAL Control functions\r
+ *\r
+@verbatim\r
+ ===============================================================================\r
+ ##### HAL Control functions #####\r
+ ===============================================================================\r
+ [..] This section provides functions allowing to:\r
+ (+) Provide a tick value in millisecond\r
+ (+) Provide a blocking delay in millisecond\r
+ (+) Suspend the time base source interrupt\r
+ (+) Resume the time base source interrupt\r
+ (+) Get the HAL API driver version\r
+ (+) Get the device identifier\r
+ (+) Get the device revision identifier\r
+ (+) Get the unique device identifier\r
+\r
+@endverbatim\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @brief This function is called to increment a global variable "uwTick"\r
+ * used as application time base.\r
+ * @note In the default implementation, this variable is incremented each 1ms\r
+ * in SysTick ISR.\r
+ * @note This function is declared as __weak to be overwritten in case of other\r
+ * implementations in user file.\r
+ * @retval None\r
+ */\r
+__weak void HAL_IncTick(void)\r
+{\r
+ uwTick += uwTickFreq;\r
+}\r
+\r
+/**\r
+ * @brief Provide a tick value in millisecond.\r
+ * @note This function is declared as __weak to be overwritten in case of other\r
+ * implementations in user file.\r
+ * @retval tick value\r
+ */\r
+__weak uint32_t HAL_GetTick(void)\r
+{\r
+ return uwTick;\r
+}\r
+\r
+/**\r
+ * @brief This function returns a tick priority.\r
+ * @retval tick priority\r
+ */\r
+uint32_t HAL_GetTickPrio(void)\r
+{\r
+ return uwTickPrio;\r
+}\r
+\r
+/**\r
+ * @brief Set new tick Freq.\r
+ * @param Freq tick frequency\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_SetTickFreq(uint32_t Freq)\r
+{\r
+ HAL_StatusTypeDef status = HAL_OK;\r
+ assert_param(IS_TICKFREQ(Freq));\r
+\r
+ if (uwTickFreq != Freq)\r
+ {\r
+ /* Apply the new tick Freq */\r
+ status = HAL_InitTick(uwTickPrio);\r
+ if (status == HAL_OK)\r
+ {\r
+ uwTickFreq = Freq;\r
+ }\r
+ }\r
+\r
+ return status;\r
+}\r
+\r
+/**\r
+ * @brief Return tick frequency.\r
+ * @retval tick period in Hz\r
+ */\r
+uint32_t HAL_GetTickFreq(void)\r
+{\r
+ return uwTickFreq;\r
+}\r
+\r
+/**\r
+ * @brief This function provides minimum delay (in milliseconds) based\r
+ * on variable incremented.\r
+ * @note In the default implementation , SysTick timer is the source of time base.\r
+ * It is used to generate interrupts at regular time intervals where uwTick\r
+ * is incremented.\r
+ * @note This function is declared as __weak to be overwritten in case of other\r
+ * implementations in user file.\r
+ * @param Delay specifies the delay time length, in milliseconds.\r
+ * @retval None\r
+ */\r
+__weak void HAL_Delay(uint32_t Delay)\r
+{\r
+ uint32_t tickstart = HAL_GetTick();\r
+ uint32_t wait = Delay;\r
+\r
+ /* Add a period to guaranty minimum wait */\r
+ if (wait < HAL_MAX_DELAY)\r
+ {\r
+ wait += (uint32_t)(uwTickFreq);\r
+ }\r
+\r
+ while((HAL_GetTick() - tickstart) < wait)\r
+ {\r
+ }\r
+}\r
+\r
+/**\r
+ * @brief Suspend the Tick increment.\r
+ * @note In the default implementation , SysTick timer is the source of time base. It is\r
+ * used to generate interrupts at regular time intervals. Once HAL_SuspendTick()\r
+ * is called, the SysTick interrupt will be disabled and so Tick increment\r
+ * is suspended.\r
+ * @note This function is declared as __weak to be overwritten in case of other\r
+ * implementations in user file.\r
+ * @retval None\r
+ */\r
+__weak void HAL_SuspendTick(void)\r
+{\r
+ /* Disable SysTick Interrupt */\r
+ CLEAR_BIT(SysTick->CTRL,SysTick_CTRL_TICKINT_Msk);\r
+}\r
+\r
+/**\r
+ * @brief Resume the Tick increment.\r
+ * @note In the default implementation , SysTick timer is the source of time base. It is\r
+ * used to generate interrupts at regular time intervals. Once HAL_ResumeTick()\r
+ * is called, the SysTick interrupt will be enabled and so Tick increment\r
+ * is resumed.\r
+ * @note This function is declared as __weak to be overwritten in case of other\r
+ * implementations in user file.\r
+ * @retval None\r
+ */\r
+__weak void HAL_ResumeTick(void)\r
+{\r
+ /* Enable SysTick Interrupt */\r
+ SET_BIT(SysTick->CTRL,SysTick_CTRL_TICKINT_Msk);\r
+}\r
+\r
+/**\r
+ * @brief Return the HAL revision\r
+ * @retval version: 0xXYZR (8bits for each decimal, R for RC)\r
+ */\r
+uint32_t HAL_GetHalVersion(void)\r
+{\r
+ return __STM32L1xx_HAL_VERSION;\r
+}\r
+\r
+/**\r
+ * @brief Return the device revision identifier.\r
+ * @retval Device revision identifier\r
+ */\r
+uint32_t HAL_GetREVID(void)\r
+{\r
+ return((DBGMCU->IDCODE) >> 16U);\r
+}\r
+\r
+/**\r
+ * @brief Return the device identifier.\r
+ * @retval Device identifier\r
+ */\r
+uint32_t HAL_GetDEVID(void)\r
+{\r
+ return((DBGMCU->IDCODE) & IDCODE_DEVID_MASK);\r
+}\r
+\r
+/**\r
+ * @brief Return the first word of the unique device identifier (UID based on 96 bits)\r
+ * @retval Device identifier 31:0 bits\r
+ */\r
+uint32_t HAL_GetUIDw0(void)\r
+{\r
+ return(READ_REG(*((uint32_t *)UID_BASE)));\r
+}\r
+\r
+/**\r
+ * @brief Return the second word of the unique device identifier (UID based on 96 bits)\r
+ * @retval Device identifier 63:32 bits\r
+ */\r
+uint32_t HAL_GetUIDw1(void)\r
+{\r
+ return(READ_REG(*((uint32_t *)(UID_BASE + 0x4U))));\r
+}\r
+\r
+/**\r
+ * @brief Return the third word of the unique device identifier (UID based on 96 bits)\r
+ * @retval Device identifier 95:64 bits\r
+ */\r
+uint32_t HAL_GetUIDw2(void)\r
+{\r
+ return(READ_REG(*((uint32_t *)(UID_BASE + 0x14U))));\r
+}\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup HAL_Exported_Functions_Group3 DBGMCU Peripheral Control functions\r
+ * @brief DBGMCU Peripheral Control functions\r
+ *\r
+@verbatim\r
+ ===============================================================================\r
+ ##### DBGMCU Peripheral Control functions #####\r
+ ===============================================================================\r
+ [..] This section provides functions allowing to:\r
+ (+) Enable/Disable Debug module during SLEEP mode\r
+ (+) Enable/Disable Debug module during STOP mode\r
+ (+) Enable/Disable Debug module during STANDBY mode\r
+\r
+@endverbatim\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @brief Enable the Debug Module during SLEEP mode\r
+ * @retval None\r
+ */\r
+void HAL_DBGMCU_EnableDBGSleepMode(void)\r
+{\r
+ SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_SLEEP);\r
+}\r
+\r
+/**\r
+ * @brief Disable the Debug Module during SLEEP mode\r
+ * @retval None\r
+ */\r
+void HAL_DBGMCU_DisableDBGSleepMode(void)\r
+{\r
+ CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_SLEEP);\r
+}\r
+\r
+/**\r
+ * @brief Enable the Debug Module during STOP mode\r
+ * @retval None\r
+ */\r
+void HAL_DBGMCU_EnableDBGStopMode(void)\r
+{\r
+ SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STOP);\r
+}\r
+\r
+/**\r
+ * @brief Disable the Debug Module during STOP mode\r
+ * @retval None\r
+ */\r
+void HAL_DBGMCU_DisableDBGStopMode(void)\r
+{\r
+ CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STOP);\r
+}\r
+\r
+/**\r
+ * @brief Enable the Debug Module during STANDBY mode\r
+ * @retval None\r
+ */\r
+void HAL_DBGMCU_EnableDBGStandbyMode(void)\r
+{\r
+ SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STANDBY);\r
+}\r
+\r
+/**\r
+ * @brief Disable the Debug Module during STANDBY mode\r
+ * @retval None\r
+ */\r
+void HAL_DBGMCU_DisableDBGStandbyMode(void)\r
+{\r
+ CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STANDBY);\r
+}\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+#endif /* HAL_MODULE_ENABLED */\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\r
--- /dev/null
+/**\r
+ ******************************************************************************\r
+ * @file stm32l1xx_hal_cortex.c\r
+ * @author MCD Application Team\r
+ * @brief CORTEX HAL module driver.\r
+ *\r
+ * This file provides firmware functions to manage the following\r
+ * functionalities of the CORTEX:\r
+ * + Initialization and de-initialization functions\r
+ * + Peripheral Control functions\r
+ * \r
+ * @verbatim \r
+ ==============================================================================\r
+ ##### How to use this driver #####\r
+ ==============================================================================\r
+\r
+ [..] \r
+ *** How to configure Interrupts using Cortex HAL driver ***\r
+ ===========================================================\r
+ [..] \r
+ This section provide functions allowing to configure the NVIC interrupts (IRQ).\r
+ The Cortex-M3 exceptions are managed by CMSIS functions.\r
+ \r
+ (#) Configure the NVIC Priority Grouping using HAL_NVIC_SetPriorityGrouping() function\r
+\r
+ (#) Configure the priority of the selected IRQ Channels using HAL_NVIC_SetPriority() \r
+\r
+ (#) Enable the selected IRQ Channels using HAL_NVIC_EnableIRQ() \r
+ \r
+\r
+ -@- When the NVIC_PRIORITYGROUP_0 is selected, IRQ pre-emption is no more possible. \r
+ The pending IRQ priority will be managed only by the sub priority.\r
+ \r
+ -@- IRQ priority order (sorted by highest to lowest priority):\r
+ (+@) Lowest pre-emption priority\r
+ (+@) Lowest sub priority\r
+ (+@) Lowest hardware priority (IRQ number)\r
+ \r
+ [..] \r
+ *** How to configure Systick using Cortex HAL driver ***\r
+ ========================================================\r
+ [..]\r
+ Setup SysTick Timer for 1 msec interrupts.\r
+ \r
+ (+) The HAL_SYSTICK_Config()function calls the SysTick_Config() function which\r
+ is a CMSIS function that:\r
+ (++) Configures the SysTick Reload register with value passed as function parameter.\r
+ (++) Configures the SysTick IRQ priority to the lowest value (0x0F).\r
+ (++) Resets the SysTick Counter register.\r
+ (++) Configures the SysTick Counter clock source to be Core Clock Source (HCLK).\r
+ (++) Enables the SysTick Interrupt.\r
+ (++) Starts the SysTick Counter.\r
+ \r
+ (+) You can change the SysTick Clock source to be HCLK_Div8 by calling the macro\r
+ __HAL_CORTEX_SYSTICKCLK_CONFIG(SYSTICK_CLKSOURCE_HCLK_DIV8) just after the\r
+ HAL_SYSTICK_Config() function call. The __HAL_CORTEX_SYSTICKCLK_CONFIG() macro is defined\r
+ inside the stm32l1xx_hal_cortex.h file.\r
+\r
+ (+) You can change the SysTick IRQ priority by calling the\r
+ HAL_NVIC_SetPriority(SysTick_IRQn,...) function just after the HAL_SYSTICK_Config() function \r
+ call. The HAL_NVIC_SetPriority() call the NVIC_SetPriority() function which is a CMSIS function.\r
+\r
+ (+) To adjust the SysTick time base, use the following formula:\r
+ \r
+ Reload Value = SysTick Counter Clock (Hz) x Desired Time base (s)\r
+ (++) Reload Value is the parameter to be passed for HAL_SYSTICK_Config() function\r
+ (++) Reload Value should not exceed 0xFFFFFF\r
+ \r
+ @endverbatim\r
+ ******************************************************************************\r
+ * @attention\r
+ *\r
+ * <h2><center>© Copyright (c) 2017 STMicroelectronics.\r
+ * All rights reserved.</center></h2>\r
+ *\r
+ * This software component is licensed by ST under BSD 3-Clause license,\r
+ * the "License"; You may not use this file except in compliance with the\r
+ * License. You may obtain a copy of the License at:\r
+ * opensource.org/licenses/BSD-3-Clause\r
+ *\r
+ ******************************************************************************\r
+ */\r
+\r
+/*\r
+ Additional Tables: CORTEX_NVIC_Priority_Table\r
+ The table below gives the allowed values of the pre-emption priority and subpriority according\r
+ to the Priority Grouping configuration performed by HAL_NVIC_SetPriorityGrouping() function.\r
+ ==========================================================================================================================\r
+ NVIC_PriorityGroup | NVIC_IRQChannelPreemptionPriority | NVIC_IRQChannelSubPriority | Description\r
+ ==========================================================================================================================\r
+ NVIC_PRIORITYGROUP_0 | 0 | 0-15 | 0 bits for pre-emption priority\r
+ | | | 4 bits for subpriority\r
+ --------------------------------------------------------------------------------------------------------------------------\r
+ NVIC_PRIORITYGROUP_1 | 0-1 | 0-7 | 1 bits for pre-emption priority\r
+ | | | 3 bits for subpriority\r
+ -------------------------------------------------------------------------------------------------------------------------- \r
+ NVIC_PRIORITYGROUP_2 | 0-3 | 0-3 | 2 bits for pre-emption priority\r
+ | | | 2 bits for subpriority\r
+ -------------------------------------------------------------------------------------------------------------------------- \r
+ NVIC_PRIORITYGROUP_3 | 0-7 | 0-1 | 3 bits for pre-emption priority\r
+ | | | 1 bits for subpriority\r
+ -------------------------------------------------------------------------------------------------------------------------- \r
+ NVIC_PRIORITYGROUP_4 | 0-15 | 0 | 4 bits for pre-emption priority\r
+ | | | 0 bits for subpriority \r
+ ==========================================================================================================================\r
+*/\r
+\r
+/* Includes ------------------------------------------------------------------*/\r
+#include "stm32l1xx_hal.h"\r
+\r
+/** @addtogroup STM32L1xx_HAL_Driver\r
+ * @{\r
+ */\r
+\r
+/** @defgroup CORTEX CORTEX\r
+ * @brief CORTEX HAL module driver\r
+ * @{\r
+ */\r
+\r
+#ifdef HAL_CORTEX_MODULE_ENABLED\r
+\r
+/* Private typedef -----------------------------------------------------------*/\r
+/* Private define ------------------------------------------------------------*/\r
+/* Private macro -------------------------------------------------------------*/\r
+/* Private variables ---------------------------------------------------------*/\r
+/* Private function prototypes -----------------------------------------------*/\r
+/* Private functions ---------------------------------------------------------*/\r
+\r
+/** @defgroup CORTEX_Exported_Functions CORTEX Exported Functions\r
+ * @{\r
+ */\r
+\r
+\r
+/** @defgroup CORTEX_Exported_Functions_Group1 Initialization and de-initialization functions\r
+ * @brief Initialization and Configuration functions \r
+ *\r
+@verbatim \r
+ ==============================================================================\r
+ ##### Initialization and de-initialization functions #####\r
+ ==============================================================================\r
+ [..]\r
+ This section provide the Cortex HAL driver functions allowing to configure Interrupts\r
+ Systick functionalities \r
+\r
+@endverbatim\r
+ * @{\r
+ */\r
+\r
+\r
+/**\r
+ * @brief Sets the priority grouping field (pre-emption priority and subpriority)\r
+ * using the required unlock sequence.\r
+ * @param PriorityGroup The priority grouping bits length. \r
+ * This parameter can be one of the following values:\r
+ * @arg NVIC_PRIORITYGROUP_0: 0 bits for pre-emption priority\r
+ * 4 bits for subpriority\r
+ * @arg NVIC_PRIORITYGROUP_1: 1 bits for pre-emption priority\r
+ * 3 bits for subpriority\r
+ * @arg NVIC_PRIORITYGROUP_2: 2 bits for pre-emption priority\r
+ * 2 bits for subpriority\r
+ * @arg NVIC_PRIORITYGROUP_3: 3 bits for pre-emption priority\r
+ * 1 bits for subpriority\r
+ * @arg NVIC_PRIORITYGROUP_4: 4 bits for pre-emption priority\r
+ * 0 bits for subpriority\r
+ * @note When the NVIC_PriorityGroup_0 is selected, IRQ pre-emption is no more possible. \r
+ * The pending IRQ priority will be managed only by the subpriority. \r
+ * @retval None\r
+ */\r
+void HAL_NVIC_SetPriorityGrouping(uint32_t PriorityGroup)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_NVIC_PRIORITY_GROUP(PriorityGroup));\r
+ \r
+ /* Set the PRIGROUP[10:8] bits according to the PriorityGroup parameter value */\r
+ NVIC_SetPriorityGrouping(PriorityGroup);\r
+}\r
+\r
+/**\r
+ * @brief Sets the priority of an interrupt.\r
+ * @param IRQn External interrupt number\r
+ * This parameter can be an enumerator of IRQn_Type enumeration\r
+ * (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32l1xx.h))\r
+ * @param PreemptPriority The pre-emption priority for the IRQn channel.\r
+ * This parameter can be a value between 0 and 15\r
+ * A lower priority value indicates a higher priority \r
+ * @param SubPriority the subpriority level for the IRQ channel.\r
+ * This parameter can be a value between 0 and 15\r
+ * A lower priority value indicates a higher priority. \r
+ * @retval None\r
+ */\r
+void HAL_NVIC_SetPriority(IRQn_Type IRQn, uint32_t PreemptPriority, uint32_t SubPriority)\r
+{\r
+ uint32_t prioritygroup = 0x00;\r
+ \r
+ /* Check the parameters */\r
+ assert_param(IS_NVIC_SUB_PRIORITY(SubPriority));\r
+ assert_param(IS_NVIC_PREEMPTION_PRIORITY(PreemptPriority));\r
+ \r
+ prioritygroup = NVIC_GetPriorityGrouping();\r
+ \r
+ NVIC_SetPriority(IRQn, NVIC_EncodePriority(prioritygroup, PreemptPriority, SubPriority));\r
+}\r
+\r
+/**\r
+ * @brief Enables a device specific interrupt in the NVIC interrupt controller.\r
+ * @note To configure interrupts priority correctly, the NVIC_PriorityGroupConfig()\r
+ * function should be called before. \r
+ * @param IRQn External interrupt number\r
+ * This parameter can be an enumerator of IRQn_Type enumeration\r
+ * (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32l1xx.h))\r
+ * @retval None\r
+ */\r
+void HAL_NVIC_EnableIRQ(IRQn_Type IRQn)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_NVIC_DEVICE_IRQ(IRQn));\r
+ \r
+ /* Enable interrupt */\r
+ NVIC_EnableIRQ(IRQn);\r
+}\r
+\r
+/**\r
+ * @brief Disables a device specific interrupt in the NVIC interrupt controller.\r
+ * @param IRQn External interrupt number\r
+ * This parameter can be an enumerator of IRQn_Type enumeration\r
+ * (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32l1xxxx.h)) \r
+ * @retval None\r
+ */\r
+void HAL_NVIC_DisableIRQ(IRQn_Type IRQn)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_NVIC_DEVICE_IRQ(IRQn));\r
+ \r
+ /* Disable interrupt */\r
+ NVIC_DisableIRQ(IRQn);\r
+}\r
+\r
+/**\r
+ * @brief Initiates a system reset request to reset the MCU.\r
+ * @retval None\r
+ */\r
+void HAL_NVIC_SystemReset(void)\r
+{\r
+ /* System Reset */\r
+ NVIC_SystemReset();\r
+}\r
+\r
+/**\r
+ * @brief Initializes the System Timer and its interrupt, and starts the System Tick Timer.\r
+ * Counter is in free running mode to generate periodic interrupts.\r
+ * @param TicksNumb Specifies the ticks Number of ticks between two interrupts.\r
+ * @retval status: - 0 Function succeeded.\r
+ * - 1 Function failed.\r
+ */\r
+uint32_t HAL_SYSTICK_Config(uint32_t TicksNumb)\r
+{\r
+ return SysTick_Config(TicksNumb);\r
+}\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup CORTEX_Exported_Functions_Group2 Peripheral Control functions\r
+ * @brief Cortex control functions \r
+ *\r
+@verbatim \r
+ ==============================================================================\r
+ ##### Peripheral Control functions #####\r
+ ==============================================================================\r
+ [..]\r
+ This subsection provides a set of functions allowing to control the CORTEX\r
+ (NVIC, SYSTICK, MPU) functionalities. \r
+ \r
+ \r
+@endverbatim\r
+ * @{\r
+ */\r
+\r
+#if (__MPU_PRESENT == 1)\r
+/**\r
+ * @brief Enable the MPU.\r
+ * @param MPU_Control Specifies the control mode of the MPU during hard fault, \r
+ * NMI, FAULTMASK and privileged accessto the default memory \r
+ * This parameter can be one of the following values:\r
+ * @arg MPU_HFNMI_PRIVDEF_NONE\r
+ * @arg MPU_HARDFAULT_NMI\r
+ * @arg MPU_PRIVILEGED_DEFAULT\r
+ * @arg MPU_HFNMI_PRIVDEF\r
+ * @retval None\r
+ */\r
+void HAL_MPU_Enable(uint32_t MPU_Control)\r
+{\r
+ /* Enable the MPU */\r
+ MPU->CTRL = (MPU_Control | MPU_CTRL_ENABLE_Msk);\r
+\r
+ /* Ensure MPU setting take effects */\r
+ __DSB();\r
+ __ISB();\r
+}\r
+\r
+/**\r
+ * @brief Disable the MPU.\r
+ * @retval None\r
+ */\r
+void HAL_MPU_Disable(void)\r
+{\r
+ /* Make sure outstanding transfers are done */\r
+ __DMB();\r
+\r
+ /* Disable the MPU and clear the control register*/\r
+ MPU->CTRL = 0;\r
+}\r
+\r
+/**\r
+ * @brief Initializes and configures the Region and the memory to be protected.\r
+ * @param MPU_Init Pointer to a MPU_Region_InitTypeDef structure that contains\r
+ * the initialization and configuration information.\r
+ * @retval None\r
+ */\r
+void HAL_MPU_ConfigRegion(MPU_Region_InitTypeDef *MPU_Init)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_MPU_REGION_NUMBER(MPU_Init->Number));\r
+ assert_param(IS_MPU_REGION_ENABLE(MPU_Init->Enable));\r
+\r
+ /* Set the Region number */\r
+ MPU->RNR = MPU_Init->Number;\r
+\r
+ if ((MPU_Init->Enable) != RESET)\r
+ {\r
+ /* Check the parameters */\r
+ assert_param(IS_MPU_INSTRUCTION_ACCESS(MPU_Init->DisableExec));\r
+ assert_param(IS_MPU_REGION_PERMISSION_ATTRIBUTE(MPU_Init->AccessPermission));\r
+ assert_param(IS_MPU_TEX_LEVEL(MPU_Init->TypeExtField));\r
+ assert_param(IS_MPU_ACCESS_SHAREABLE(MPU_Init->IsShareable));\r
+ assert_param(IS_MPU_ACCESS_CACHEABLE(MPU_Init->IsCacheable));\r
+ assert_param(IS_MPU_ACCESS_BUFFERABLE(MPU_Init->IsBufferable));\r
+ assert_param(IS_MPU_SUB_REGION_DISABLE(MPU_Init->SubRegionDisable));\r
+ assert_param(IS_MPU_REGION_SIZE(MPU_Init->Size));\r
+ \r
+ MPU->RBAR = MPU_Init->BaseAddress;\r
+ MPU->RASR = ((uint32_t)MPU_Init->DisableExec << MPU_RASR_XN_Pos) |\r
+ ((uint32_t)MPU_Init->AccessPermission << MPU_RASR_AP_Pos) |\r
+ ((uint32_t)MPU_Init->TypeExtField << MPU_RASR_TEX_Pos) |\r
+ ((uint32_t)MPU_Init->IsShareable << MPU_RASR_S_Pos) |\r
+ ((uint32_t)MPU_Init->IsCacheable << MPU_RASR_C_Pos) |\r
+ ((uint32_t)MPU_Init->IsBufferable << MPU_RASR_B_Pos) |\r
+ ((uint32_t)MPU_Init->SubRegionDisable << MPU_RASR_SRD_Pos) |\r
+ ((uint32_t)MPU_Init->Size << MPU_RASR_SIZE_Pos) |\r
+ ((uint32_t)MPU_Init->Enable << MPU_RASR_ENABLE_Pos);\r
+ }\r
+ else\r
+ {\r
+ MPU->RBAR = 0x00;\r
+ MPU->RASR = 0x00;\r
+ }\r
+}\r
+#endif /* __MPU_PRESENT */\r
+\r
+/**\r
+ * @brief Gets the priority grouping field from the NVIC Interrupt Controller.\r
+ * @retval Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field)\r
+ */\r
+uint32_t HAL_NVIC_GetPriorityGrouping(void)\r
+{\r
+ /* Get the PRIGROUP[10:8] field value */\r
+ return NVIC_GetPriorityGrouping();\r
+}\r
+\r
+/**\r
+ * @brief Gets the priority of an interrupt.\r
+ * @param IRQn External interrupt number\r
+ * This parameter can be an enumerator of IRQn_Type enumeration\r
+ * (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32l1xxxx.h))\r
+ * @param PriorityGroup the priority grouping bits length.\r
+ * This parameter can be one of the following values:\r
+ * @arg NVIC_PRIORITYGROUP_0: 0 bits for pre-emption priority\r
+ * 4 bits for subpriority\r
+ * @arg NVIC_PRIORITYGROUP_1: 1 bits for pre-emption priority\r
+ * 3 bits for subpriority\r
+ * @arg NVIC_PRIORITYGROUP_2: 2 bits for pre-emption priority\r
+ * 2 bits for subpriority\r
+ * @arg NVIC_PRIORITYGROUP_3: 3 bits for pre-emption priority\r
+ * 1 bits for subpriority\r
+ * @arg NVIC_PRIORITYGROUP_4: 4 bits for pre-emption priority\r
+ * 0 bits for subpriority\r
+ * @param pPreemptPriority Pointer on the Preemptive priority value (starting from 0).\r
+ * @param pSubPriority Pointer on the Subpriority value (starting from 0).\r
+ * @retval None\r
+ */\r
+void HAL_NVIC_GetPriority(IRQn_Type IRQn, uint32_t PriorityGroup, uint32_t* pPreemptPriority, uint32_t* pSubPriority)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_NVIC_PRIORITY_GROUP(PriorityGroup));\r
+ /* Get priority for Cortex-M system or device specific interrupts */\r
+ NVIC_DecodePriority(NVIC_GetPriority(IRQn), PriorityGroup, pPreemptPriority, pSubPriority);\r
+}\r
+\r
+/**\r
+ * @brief Sets Pending bit of an external interrupt.\r
+ * @param IRQn External interrupt number\r
+ * This parameter can be an enumerator of IRQn_Type enumeration\r
+ * (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32l1xxxx.h)) \r
+ * @retval None\r
+ */\r
+void HAL_NVIC_SetPendingIRQ(IRQn_Type IRQn)\r
+{ \r
+ /* Set interrupt pending */\r
+ NVIC_SetPendingIRQ(IRQn);\r
+}\r
+\r
+/**\r
+ * @brief Gets Pending Interrupt (reads the pending register in the NVIC \r
+ * and returns the pending bit for the specified interrupt).\r
+ * @param IRQn External interrupt number\r
+ * This parameter can be an enumerator of IRQn_Type enumeration\r
+ * (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32l1xxxx.h)) \r
+ * @retval status: - 0 Interrupt status is not pending.\r
+ * - 1 Interrupt status is pending.\r
+ */\r
+uint32_t HAL_NVIC_GetPendingIRQ(IRQn_Type IRQn)\r
+{ \r
+ /* Return 1 if pending else 0 */\r
+ return NVIC_GetPendingIRQ(IRQn);\r
+}\r
+\r
+/**\r
+ * @brief Clears the pending bit of an external interrupt.\r
+ * @param IRQn External interrupt number\r
+ * This parameter can be an enumerator of IRQn_Type enumeration\r
+ * (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32l1xxxx.h)) \r
+ * @retval None\r
+ */\r
+void HAL_NVIC_ClearPendingIRQ(IRQn_Type IRQn)\r
+{ \r
+ /* Clear pending interrupt */\r
+ NVIC_ClearPendingIRQ(IRQn);\r
+}\r
+\r
+/**\r
+ * @brief Gets active interrupt ( reads the active register in NVIC and returns the active bit).\r
+ * @param IRQn External interrupt number\r
+ * This parameter can be an enumerator of IRQn_Type enumeration\r
+ * (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32l1xxxx.h)) \r
+ * @retval status: - 0 Interrupt status is not pending.\r
+ * - 1 Interrupt status is pending.\r
+ */\r
+uint32_t HAL_NVIC_GetActive(IRQn_Type IRQn)\r
+{ \r
+ /* Return 1 if active else 0 */\r
+ return NVIC_GetActive(IRQn);\r
+}\r
+\r
+/**\r
+ * @brief Configures the SysTick clock source.\r
+ * @param CLKSource specifies the SysTick clock source.\r
+ * This parameter can be one of the following values:\r
+ * @arg SYSTICK_CLKSOURCE_HCLK_DIV8: AHB clock divided by 8 selected as SysTick clock source.\r
+ * @arg SYSTICK_CLKSOURCE_HCLK: AHB clock selected as SysTick clock source.\r
+ * @retval None\r
+ */\r
+void HAL_SYSTICK_CLKSourceConfig(uint32_t CLKSource)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_SYSTICK_CLK_SOURCE(CLKSource));\r
+ if (CLKSource == SYSTICK_CLKSOURCE_HCLK)\r
+ {\r
+ SysTick->CTRL |= SYSTICK_CLKSOURCE_HCLK;\r
+ }\r
+ else\r
+ {\r
+ SysTick->CTRL &= ~SYSTICK_CLKSOURCE_HCLK;\r
+ }\r
+}\r
+\r
+/**\r
+ * @brief This function handles SYSTICK interrupt request.\r
+ * @retval None\r
+ */\r
+void HAL_SYSTICK_IRQHandler(void)\r
+{\r
+ HAL_SYSTICK_Callback();\r
+}\r
+\r
+/**\r
+ * @brief SYSTICK callback.\r
+ * @retval None\r
+ */\r
+__weak void HAL_SYSTICK_Callback(void)\r
+{\r
+ /* NOTE : This function Should not be modified, when the callback is needed,\r
+ the HAL_SYSTICK_Callback could be implemented in the user file\r
+ */\r
+}\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+#endif /* HAL_CORTEX_MODULE_ENABLED */\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\r
--- /dev/null
+/**\r
+ ******************************************************************************\r
+ * @file stm32l1xx_hal_dma.c\r
+ * @author MCD Application Team\r
+ * @brief DMA HAL module driver.\r
+ * This file provides firmware functions to manage the following\r
+ * functionalities of the Direct Memory Access (DMA) peripheral:\r
+ * + Initialization and de-initialization functions\r
+ * + IO operation functions\r
+ * + Peripheral State and errors functions\r
+ @verbatim\r
+ ==============================================================================\r
+ ##### How to use this driver #####\r
+ ==============================================================================\r
+ [..]\r
+ (#) Enable and configure the peripheral to be connected to the DMA Channel\r
+ (except for internal SRAM / FLASH memories: no initialization is\r
+ necessary). Please refer to the Reference manual for connection between peripherals\r
+ and DMA requests.\r
+\r
+ (#) For a given Channel, program the required configuration through the following parameters:\r
+ Channel request, Transfer Direction, Source and Destination data formats,\r
+ Circular or Normal mode, Channel Priority level, Source and Destination Increment mode\r
+ using HAL_DMA_Init() function.\r
+\r
+ (#) Use HAL_DMA_GetState() function to return the DMA state and HAL_DMA_GetError() in case of error\r
+ detection.\r
+\r
+ (#) Use HAL_DMA_Abort() function to abort the current transfer\r
+\r
+ -@- In Memory-to-Memory transfer mode, Circular mode is not allowed.\r
+ *** Polling mode IO operation ***\r
+ =================================\r
+ [..]\r
+ (+) Use HAL_DMA_Start() to start DMA transfer after the configuration of Source\r
+ address and destination address and the Length of data to be transferred\r
+ (+) Use HAL_DMA_PollForTransfer() to poll for the end of current transfer, in this\r
+ case a fixed Timeout can be configured by User depending from his application.\r
+\r
+ *** Interrupt mode IO operation ***\r
+ ===================================\r
+ [..]\r
+ (+) Configure the DMA interrupt priority using HAL_NVIC_SetPriority()\r
+ (+) Enable the DMA IRQ handler using HAL_NVIC_EnableIRQ()\r
+ (+) Use HAL_DMA_Start_IT() to start DMA transfer after the configuration of\r
+ Source address and destination address and the Length of data to be transferred.\r
+ In this case the DMA interrupt is configured\r
+ (+) Use HAL_DMA_IRQHandler() called under DMA_IRQHandler() Interrupt subroutine\r
+ (+) At the end of data transfer HAL_DMA_IRQHandler() function is executed and user can\r
+ add his own function to register callbacks with HAL_DMA_RegisterCallback().\r
+\r
+ *** DMA HAL driver macros list ***\r
+ =============================================\r
+ [..]\r
+ Below the list of macros in DMA HAL driver.\r
+\r
+ (+) __HAL_DMA_ENABLE: Enable the specified DMA Channel.\r
+ (+) __HAL_DMA_DISABLE: Disable the specified DMA Channel.\r
+ (+) __HAL_DMA_GET_FLAG: Get the DMA Channel pending flags.\r
+ (+) __HAL_DMA_CLEAR_FLAG: Clear the DMA Channel pending flags.\r
+ (+) __HAL_DMA_ENABLE_IT: Enable the specified DMA Channel interrupts.\r
+ (+) __HAL_DMA_DISABLE_IT: Disable the specified DMA Channel interrupts.\r
+ (+) __HAL_DMA_GET_IT_SOURCE: Check whether the specified DMA Channel interrupt is enabled or not.\r
+\r
+ [..]\r
+ (@) You can refer to the DMA HAL driver header file for more useful macros\r
+\r
+ @endverbatim\r
+ ******************************************************************************\r
+ * @attention\r
+ *\r
+ * <h2><center>© Copyright (c) 2017 STMicroelectronics.\r
+ * All rights reserved.</center></h2>\r
+ *\r
+ * This software component is licensed by ST under BSD 3-Clause license,\r
+ * the "License"; You may not use this file except in compliance with the\r
+ * License. You may obtain a copy of the License at:\r
+ * opensource.org/licenses/BSD-3-Clause\r
+ *\r
+ ******************************************************************************\r
+ */\r
+\r
+/* Includes ------------------------------------------------------------------*/\r
+#include "stm32l1xx_hal.h"\r
+\r
+/** @addtogroup STM32L1xx_HAL_Driver\r
+ * @{\r
+ */\r
+\r
+/** @defgroup DMA DMA\r
+ * @brief DMA HAL module driver\r
+ * @{\r
+ */\r
+\r
+#ifdef HAL_DMA_MODULE_ENABLED\r
+\r
+/* Private typedef -----------------------------------------------------------*/\r
+/* Private define ------------------------------------------------------------*/\r
+/* Private macro -------------------------------------------------------------*/\r
+/* Private variables ---------------------------------------------------------*/\r
+/* Private function prototypes -----------------------------------------------*/\r
+/** @defgroup DMA_Private_Functions DMA Private Functions\r
+ * @{\r
+ */\r
+\r
+static void DMA_SetConfig(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength);\r
+/**\r
+ * @}\r
+ */\r
+\r
+/* Exported functions ---------------------------------------------------------*/\r
+\r
+/** @defgroup DMA_Exported_Functions DMA Exported Functions\r
+ * @{\r
+ */\r
+\r
+/** @defgroup DMA_Exported_Functions_Group1 Initialization and de-initialization functions\r
+ * @brief Initialization and de-initialization functions\r
+ *\r
+@verbatim\r
+ ===============================================================================\r
+ ##### Initialization and de-initialization functions #####\r
+ ===============================================================================\r
+ [..]\r
+ This section provides functions allowing to initialize the DMA Channel source\r
+ and destination addresses, incrementation and data sizes, transfer direction,\r
+ circular/normal mode selection, memory-to-memory mode selection and Channel priority value.\r
+ [..]\r
+ The HAL_DMA_Init() function follows the DMA configuration procedures as described in\r
+ reference manual.\r
+\r
+@endverbatim\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @brief Initialize the DMA according to the specified\r
+ * parameters in the DMA_InitTypeDef and initialize the associated handle.\r
+ * @param hdma Pointer to a DMA_HandleTypeDef structure that contains\r
+ * the configuration information for the specified DMA Channel.\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_DMA_Init(DMA_HandleTypeDef *hdma)\r
+{\r
+ uint32_t tmp;\r
+\r
+ /* Check the DMA handle allocation */\r
+ if(hdma == NULL)\r
+ {\r
+ return HAL_ERROR;\r
+ }\r
+\r
+ /* Check the parameters */\r
+ assert_param(IS_DMA_ALL_INSTANCE(hdma->Instance));\r
+ assert_param(IS_DMA_DIRECTION(hdma->Init.Direction));\r
+ assert_param(IS_DMA_PERIPHERAL_INC_STATE(hdma->Init.PeriphInc));\r
+ assert_param(IS_DMA_MEMORY_INC_STATE(hdma->Init.MemInc));\r
+ assert_param(IS_DMA_PERIPHERAL_DATA_SIZE(hdma->Init.PeriphDataAlignment));\r
+ assert_param(IS_DMA_MEMORY_DATA_SIZE(hdma->Init.MemDataAlignment));\r
+ assert_param(IS_DMA_MODE(hdma->Init.Mode));\r
+ assert_param(IS_DMA_PRIORITY(hdma->Init.Priority));\r
+\r
+#if defined (DMA2)\r
+ /* Compute the channel index */\r
+ if ((uint32_t)(hdma->Instance) < (uint32_t)(DMA2_Channel1))\r
+ {\r
+ /* DMA1 */\r
+ hdma->ChannelIndex = (((uint32_t)hdma->Instance - (uint32_t)DMA1_Channel1) / ((uint32_t)DMA1_Channel2 - (uint32_t)DMA1_Channel1)) << 2U;\r
+ hdma->DmaBaseAddress = DMA1;\r
+ }\r
+ else\r
+ {\r
+ /* DMA2 */\r
+ hdma->ChannelIndex = (((uint32_t)hdma->Instance - (uint32_t)DMA2_Channel1) / ((uint32_t)DMA2_Channel2 - (uint32_t)DMA2_Channel1)) << 2U;\r
+ hdma->DmaBaseAddress = DMA2;\r
+ }\r
+#else\r
+ /* calculation of the channel index */\r
+ /* DMA1 */\r
+ hdma->ChannelIndex = (((uint32_t)hdma->Instance - (uint32_t)DMA1_Channel1) / ((uint32_t)DMA1_Channel2 - (uint32_t)DMA1_Channel1)) << 2U;\r
+ hdma->DmaBaseAddress = DMA1;\r
+#endif\r
+\r
+ /* Change DMA peripheral state */\r
+ hdma->State = HAL_DMA_STATE_BUSY;\r
+\r
+ /* Get the CR register value */\r
+ tmp = hdma->Instance->CCR;\r
+\r
+ /* Clear PL, MSIZE, PSIZE, MINC, PINC, CIRC, DIR and MEM2MEM bits */\r
+ tmp &= ((uint32_t)~(DMA_CCR_PL | DMA_CCR_MSIZE | DMA_CCR_PSIZE |\r
+ DMA_CCR_MINC | DMA_CCR_PINC | DMA_CCR_CIRC |\r
+ DMA_CCR_DIR | DMA_CCR_MEM2MEM));\r
+\r
+ /* Prepare the DMA Channel configuration */\r
+ tmp |= hdma->Init.Direction |\r
+ hdma->Init.PeriphInc | hdma->Init.MemInc |\r
+ hdma->Init.PeriphDataAlignment | hdma->Init.MemDataAlignment |\r
+ hdma->Init.Mode | hdma->Init.Priority;\r
+\r
+ /* Write to DMA Channel CR register */\r
+ hdma->Instance->CCR = tmp;\r
+\r
+ /* Initialise the error code */\r
+ hdma->ErrorCode = HAL_DMA_ERROR_NONE;\r
+\r
+ /* Initialize the DMA state*/\r
+ hdma->State = HAL_DMA_STATE_READY;\r
+\r
+ /* Allocate lock resource and initialize it */\r
+ hdma->Lock = HAL_UNLOCKED;\r
+\r
+ return HAL_OK;\r
+}\r
+\r
+/**\r
+ * @brief DeInitialize the DMA peripheral.\r
+ * @param hdma pointer to a DMA_HandleTypeDef structure that contains\r
+ * the configuration information for the specified DMA Channel.\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_DMA_DeInit(DMA_HandleTypeDef *hdma)\r
+{\r
+\r
+ /* Check the DMA handle allocation */\r
+ if (NULL == hdma )\r
+ {\r
+ return HAL_ERROR;\r
+ }\r
+\r
+ /* Check the parameters */\r
+ assert_param(IS_DMA_ALL_INSTANCE(hdma->Instance));\r
+\r
+ /* Disable the selected DMA Channelx */\r
+ __HAL_DMA_DISABLE(hdma);\r
+\r
+#if defined (DMA2)\r
+ /* Compute the channel index */\r
+ if ((uint32_t)(hdma->Instance) < (uint32_t)(DMA2_Channel1))\r
+ {\r
+ /* DMA1 */\r
+ hdma->ChannelIndex = (((uint32_t)hdma->Instance - (uint32_t)DMA1_Channel1) / ((uint32_t)DMA1_Channel2 - (uint32_t)DMA1_Channel1)) << 2U;\r
+ hdma->DmaBaseAddress = DMA1;\r
+ }\r
+ else\r
+ {\r
+ /* DMA2 */\r
+ hdma->ChannelIndex = (((uint32_t)hdma->Instance - (uint32_t)DMA2_Channel1) / ((uint32_t)DMA2_Channel2 - (uint32_t)DMA2_Channel1)) << 2U;\r
+ hdma->DmaBaseAddress = DMA2;\r
+ }\r
+#else\r
+ /* calculation of the channel index */\r
+ /* DMA1 */\r
+ hdma->ChannelIndex = (((uint32_t)hdma->Instance - (uint32_t)DMA1_Channel1) / ((uint32_t)DMA1_Channel2 - (uint32_t)DMA1_Channel1)) << 2U;\r
+ hdma->DmaBaseAddress = DMA1;\r
+#endif\r
+\r
+ /* Reset DMA Channel CR register */\r
+ hdma->Instance->CCR = 0U;\r
+\r
+ /* Clear all flags */\r
+ hdma->DmaBaseAddress->IFCR = (DMA_ISR_GIF1 << (hdma->ChannelIndex & 0x1CU));\r
+\r
+ /* Clean callbacks */\r
+ hdma->XferCpltCallback = NULL;\r
+ hdma->XferHalfCpltCallback = NULL;\r
+ hdma->XferErrorCallback = NULL;\r
+ hdma->XferAbortCallback = NULL;\r
+\r
+ /* Initialise the error code */\r
+ hdma->ErrorCode = HAL_DMA_ERROR_NONE;\r
+\r
+ /* Initialize the DMA state */\r
+ hdma->State = HAL_DMA_STATE_RESET;\r
+\r
+ /* Release Lock */\r
+ __HAL_UNLOCK(hdma);\r
+\r
+ return HAL_OK;\r
+}\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup DMA_Exported_Functions_Group2 Input and Output operation functions\r
+ * @brief Input and Output operation functions\r
+ *\r
+@verbatim\r
+ ===============================================================================\r
+ ##### IO operation functions #####\r
+ ===============================================================================\r
+ [..] This section provides functions allowing to:\r
+ (+) Configure the source, destination address and data length and Start DMA transfer\r
+ (+) Configure the source, destination address and data length and\r
+ Start DMA transfer with interrupt\r
+ (+) Abort DMA transfer\r
+ (+) Poll for transfer complete\r
+ (+) Handle DMA interrupt request\r
+\r
+@endverbatim\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @brief Start the DMA Transfer.\r
+ * @param hdma pointer to a DMA_HandleTypeDef structure that contains\r
+ * the configuration information for the specified DMA Channel.\r
+ * @param SrcAddress The source memory Buffer address\r
+ * @param DstAddress The destination memory Buffer address\r
+ * @param DataLength The length of data to be transferred from source to destination\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_DMA_Start(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength)\r
+{\r
+ HAL_StatusTypeDef status = HAL_OK;\r
+\r
+ /* Check the parameters */\r
+ assert_param(IS_DMA_BUFFER_SIZE(DataLength));\r
+\r
+ /* Process locked */\r
+ __HAL_LOCK(hdma);\r
+\r
+ if(HAL_DMA_STATE_READY == hdma->State)\r
+ {\r
+ /* Change DMA peripheral state */\r
+ hdma->State = HAL_DMA_STATE_BUSY;\r
+ hdma->ErrorCode = HAL_DMA_ERROR_NONE;\r
+\r
+ /* Disable the peripheral */\r
+ __HAL_DMA_DISABLE(hdma);\r
+\r
+ /* Configure the source, destination address and the data length & clear flags*/\r
+ DMA_SetConfig(hdma, SrcAddress, DstAddress, DataLength);\r
+\r
+ /* Enable the Peripheral */\r
+ __HAL_DMA_ENABLE(hdma);\r
+ }\r
+ else\r
+ {\r
+ /* Process Unlocked */\r
+ __HAL_UNLOCK(hdma);\r
+ status = HAL_BUSY;\r
+ }\r
+ return status;\r
+}\r
+\r
+/**\r
+ * @brief Start the DMA Transfer with interrupt enabled.\r
+ * @param hdma pointer to a DMA_HandleTypeDef structure that contains\r
+ * the configuration information for the specified DMA Channel.\r
+ * @param SrcAddress The source memory Buffer address\r
+ * @param DstAddress The destination memory Buffer address\r
+ * @param DataLength The length of data to be transferred from source to destination\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_DMA_Start_IT(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength)\r
+{\r
+ HAL_StatusTypeDef status = HAL_OK;\r
+\r
+ /* Check the parameters */\r
+ assert_param(IS_DMA_BUFFER_SIZE(DataLength));\r
+\r
+ /* Process locked */\r
+ __HAL_LOCK(hdma);\r
+\r
+ if(HAL_DMA_STATE_READY == hdma->State)\r
+ {\r
+ /* Change DMA peripheral state */\r
+ hdma->State = HAL_DMA_STATE_BUSY;\r
+ hdma->ErrorCode = HAL_DMA_ERROR_NONE;\r
+\r
+ /* Disable the peripheral */\r
+ __HAL_DMA_DISABLE(hdma);\r
+\r
+ /* Configure the source, destination address and the data length & clear flags*/\r
+ DMA_SetConfig(hdma, SrcAddress, DstAddress, DataLength);\r
+\r
+ /* Enable the transfer complete interrupt */\r
+ /* Enable the transfer Error interrupt */\r
+ if(NULL != hdma->XferHalfCpltCallback )\r
+ {\r
+ /* Enable the Half transfer complete interrupt as well */\r
+ __HAL_DMA_ENABLE_IT(hdma, (DMA_IT_TC | DMA_IT_HT | DMA_IT_TE));\r
+ }\r
+ else\r
+ {\r
+ __HAL_DMA_DISABLE_IT(hdma, DMA_IT_HT);\r
+ __HAL_DMA_ENABLE_IT(hdma, (DMA_IT_TC | DMA_IT_TE));\r
+ }\r
+\r
+ /* Enable the Peripheral */\r
+ __HAL_DMA_ENABLE(hdma);\r
+ }\r
+ else\r
+ {\r
+ /* Process Unlocked */\r
+ __HAL_UNLOCK(hdma);\r
+\r
+ /* Remain BUSY */\r
+ status = HAL_BUSY;\r
+ }\r
+ return status;\r
+}\r
+\r
+/**\r
+ * @brief Abort the DMA Transfer.\r
+ * @param hdma pointer to a DMA_HandleTypeDef structure that contains\r
+ * the configuration information for the specified DMA Channel.\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_DMA_Abort(DMA_HandleTypeDef *hdma)\r
+{\r
+ HAL_StatusTypeDef status = HAL_OK;\r
+\r
+ /* Check the DMA peripheral state */\r
+ if(hdma->State != HAL_DMA_STATE_BUSY)\r
+ {\r
+ hdma->ErrorCode = HAL_DMA_ERROR_NO_XFER;\r
+\r
+ /* Process Unlocked */\r
+ __HAL_UNLOCK(hdma);\r
+\r
+ return HAL_ERROR;\r
+ }\r
+ else\r
+ {\r
+ /* Disable DMA IT */\r
+ __HAL_DMA_DISABLE_IT(hdma, (DMA_IT_TC | DMA_IT_HT | DMA_IT_TE));\r
+\r
+ /* Disable the channel */\r
+ __HAL_DMA_DISABLE(hdma);\r
+\r
+ /* Clear all flags */\r
+ hdma->DmaBaseAddress->IFCR = (DMA_ISR_GIF1 << (hdma->ChannelIndex & 0x1CU));\r
+\r
+ /* Change the DMA state */\r
+ hdma->State = HAL_DMA_STATE_READY;\r
+\r
+ /* Process Unlocked */\r
+ __HAL_UNLOCK(hdma);\r
+\r
+ return status;\r
+ }\r
+}\r
+\r
+/**\r
+ * @brief Aborts the DMA Transfer in Interrupt mode.\r
+ * @param hdma pointer to a DMA_HandleTypeDef structure that contains\r
+ * the configuration information for the specified DMA Channel.\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_DMA_Abort_IT(DMA_HandleTypeDef *hdma)\r
+{\r
+ HAL_StatusTypeDef status = HAL_OK;\r
+\r
+ if(HAL_DMA_STATE_BUSY != hdma->State)\r
+ {\r
+ /* no transfer ongoing */\r
+ hdma->ErrorCode = HAL_DMA_ERROR_NO_XFER;\r
+\r
+ status = HAL_ERROR;\r
+ }\r
+ else\r
+ {\r
+ /* Disable DMA IT */\r
+ __HAL_DMA_DISABLE_IT(hdma, (DMA_IT_TC | DMA_IT_HT | DMA_IT_TE));\r
+\r
+ /* Disable the channel */\r
+ __HAL_DMA_DISABLE(hdma);\r
+\r
+ /* Clear all flags */\r
+ hdma->DmaBaseAddress->IFCR = (DMA_ISR_GIF1 << (hdma->ChannelIndex & 0x1CU));\r
+\r
+ /* Change the DMA state */\r
+ hdma->State = HAL_DMA_STATE_READY;\r
+\r
+ /* Process Unlocked */\r
+ __HAL_UNLOCK(hdma);\r
+\r
+ /* Call User Abort callback */\r
+ if(hdma->XferAbortCallback != NULL)\r
+ {\r
+ hdma->XferAbortCallback(hdma);\r
+ }\r
+ }\r
+ return status;\r
+}\r
+\r
+/**\r
+ * @brief Polling for transfer complete.\r
+ * @param hdma pointer to a DMA_HandleTypeDef structure that contains\r
+ * the configuration information for the specified DMA Channel.\r
+ * @param CompleteLevel Specifies the DMA level complete.\r
+ * @param Timeout Timeout duration.\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_DMA_PollForTransfer(DMA_HandleTypeDef *hdma, HAL_DMA_LevelCompleteTypeDef CompleteLevel, uint32_t Timeout)\r
+{\r
+ uint32_t temp;\r
+ uint32_t tickstart;\r
+\r
+ if(HAL_DMA_STATE_BUSY != hdma->State)\r
+ {\r
+ /* no transfer ongoing */\r
+ hdma->ErrorCode = HAL_DMA_ERROR_NO_XFER;\r
+ __HAL_UNLOCK(hdma);\r
+ return HAL_ERROR;\r
+ }\r
+\r
+ /* Polling mode not supported in circular mode */\r
+ if ((hdma->Instance->CCR & DMA_CCR_CIRC) != 0U)\r
+ {\r
+ hdma->ErrorCode = HAL_DMA_ERROR_NOT_SUPPORTED;\r
+ return HAL_ERROR;\r
+ }\r
+\r
+ /* Get the level transfer complete flag */\r
+ if (HAL_DMA_FULL_TRANSFER == CompleteLevel)\r
+ {\r
+ /* Transfer Complete flag */\r
+ temp = DMA_FLAG_TC1 << (hdma->ChannelIndex & 0x1CU);\r
+ }\r
+ else\r
+ {\r
+ /* Half Transfer Complete flag */\r
+ temp = DMA_FLAG_HT1 << (hdma->ChannelIndex & 0x1CU);\r
+ }\r
+\r
+ /* Get tick */\r
+ tickstart = HAL_GetTick();\r
+\r
+ while((hdma->DmaBaseAddress->ISR & temp) == 0U)\r
+ {\r
+ if((hdma->DmaBaseAddress->ISR & (DMA_FLAG_TE1 << (hdma->ChannelIndex& 0x1CU))) != 0U)\r
+ {\r
+ /* When a DMA transfer error occurs */\r
+ /* A hardware clear of its EN bits is performed */\r
+ /* Clear all flags */\r
+ hdma->DmaBaseAddress->IFCR = (DMA_ISR_GIF1 << (hdma->ChannelIndex & 0x1CU));\r
+\r
+ /* Update error code */\r
+ hdma->ErrorCode = HAL_DMA_ERROR_TE;\r
+\r
+ /* Change the DMA state */\r
+ hdma->State= HAL_DMA_STATE_READY;\r
+\r
+ /* Process Unlocked */\r
+ __HAL_UNLOCK(hdma);\r
+\r
+ return HAL_ERROR;\r
+ }\r
+ /* Check for the Timeout */\r
+ if(Timeout != HAL_MAX_DELAY)\r
+ {\r
+ if(((HAL_GetTick() - tickstart) > Timeout) || (Timeout == 0U))\r
+ {\r
+ /* Update error code */\r
+ hdma->ErrorCode = HAL_DMA_ERROR_TIMEOUT;\r
+\r
+ /* Change the DMA state */\r
+ hdma->State = HAL_DMA_STATE_READY;\r
+\r
+ /* Process Unlocked */\r
+ __HAL_UNLOCK(hdma);\r
+\r
+ return HAL_ERROR;\r
+ }\r
+ }\r
+ }\r
+\r
+ if(HAL_DMA_FULL_TRANSFER == CompleteLevel)\r
+ {\r
+ /* Clear the transfer complete flag */\r
+ hdma->DmaBaseAddress->IFCR = (DMA_FLAG_TC1 << (hdma->ChannelIndex& 0x1CU));\r
+\r
+ /* The selected Channelx EN bit is cleared (DMA is disabled and\r
+ all transfers are complete) */\r
+ hdma->State = HAL_DMA_STATE_READY;\r
+ }\r
+ else\r
+ {\r
+ /* Clear the half transfer complete flag */\r
+ hdma->DmaBaseAddress->IFCR = (DMA_FLAG_HT1 << (hdma->ChannelIndex & 0x1CU));\r
+ }\r
+\r
+ /* Process unlocked */\r
+ __HAL_UNLOCK(hdma);\r
+\r
+ return HAL_OK;\r
+}\r
+\r
+/**\r
+ * @brief Handle DMA interrupt request.\r
+ * @param hdma pointer to a DMA_HandleTypeDef structure that contains\r
+ * the configuration information for the specified DMA Channel.\r
+ * @retval None\r
+ */\r
+void HAL_DMA_IRQHandler(DMA_HandleTypeDef *hdma)\r
+{\r
+ uint32_t flag_it = hdma->DmaBaseAddress->ISR;\r
+ uint32_t source_it = hdma->Instance->CCR;\r
+\r
+ /* Half Transfer Complete Interrupt management ******************************/\r
+ if (((flag_it & (DMA_FLAG_HT1 << (hdma->ChannelIndex & 0x1CU))) != 0U) && ((source_it & DMA_IT_HT) != 0U))\r
+ {\r
+ /* Disable the half transfer interrupt if the DMA mode is not CIRCULAR */\r
+ if((hdma->Instance->CCR & DMA_CCR_CIRC) == 0U)\r
+ {\r
+ /* Disable the half transfer interrupt */\r
+ __HAL_DMA_DISABLE_IT(hdma, DMA_IT_HT);\r
+ }\r
+ /* Clear the half transfer complete flag */\r
+ hdma->DmaBaseAddress->IFCR = DMA_ISR_HTIF1 << (hdma->ChannelIndex & 0x1CU);\r
+\r
+ /* DMA peripheral state is not updated in Half Transfer */\r
+ /* but in Transfer Complete case */\r
+\r
+ if(hdma->XferHalfCpltCallback != NULL)\r
+ {\r
+ /* Half transfer callback */\r
+ hdma->XferHalfCpltCallback(hdma);\r
+ }\r
+ }\r
+\r
+ /* Transfer Complete Interrupt management ***********************************/\r
+ else if (((flag_it & (DMA_FLAG_TC1 << (hdma->ChannelIndex & 0x1CU))) != 0U) && ((source_it & DMA_IT_TC) != 0U))\r
+ {\r
+ \r
+ if((hdma->Instance->CCR & DMA_CCR_CIRC) == 0U)\r
+ {\r
+ /* Disable the transfer complete interrupt if the DMA mode is not CIRCULAR */\r
+ /* Disable the transfer complete and error interrupt */\r
+ /* if the DMA mode is not CIRCULAR */\r
+ __HAL_DMA_DISABLE_IT(hdma, DMA_IT_TE | DMA_IT_TC);\r
+\r
+ /* Change the DMA state */\r
+ hdma->State = HAL_DMA_STATE_READY;\r
+ }\r
+ /* Clear the transfer complete flag */\r
+ hdma->DmaBaseAddress->IFCR = (DMA_ISR_TCIF1 << (hdma->ChannelIndex & 0x1CU));\r
+\r
+ /* Process Unlocked */\r
+ __HAL_UNLOCK(hdma);\r
+\r
+ if(hdma->XferCpltCallback != NULL)\r
+ {\r
+ /* Transfer complete callback */\r
+ hdma->XferCpltCallback(hdma);\r
+ }\r
+ }\r
+\r
+ /* Transfer Error Interrupt management **************************************/\r
+ else if (((flag_it & (DMA_FLAG_TE1 << (hdma->ChannelIndex & 0x1CU))) != 0U) && ((source_it & DMA_IT_TE) != 0U))\r
+ {\r
+ /* When a DMA transfer error occurs */\r
+ /* A hardware clear of its EN bits is performed */\r
+ /* Disable ALL DMA IT */\r
+ __HAL_DMA_DISABLE_IT(hdma, (DMA_IT_TC | DMA_IT_HT | DMA_IT_TE));\r
+\r
+ /* Clear all flags */\r
+ hdma->DmaBaseAddress->IFCR = (DMA_ISR_GIF1 << (hdma->ChannelIndex & 0x1CU));\r
+\r
+ /* Update error code */\r
+ hdma->ErrorCode = HAL_DMA_ERROR_TE;\r
+\r
+ /* Change the DMA state */\r
+ hdma->State = HAL_DMA_STATE_READY;\r
+\r
+ /* Process Unlocked */\r
+ __HAL_UNLOCK(hdma);\r
+\r
+ if (hdma->XferErrorCallback != NULL)\r
+ {\r
+ /* Transfer error callback */\r
+ hdma->XferErrorCallback(hdma);\r
+ }\r
+ }\r
+ else\r
+ {\r
+ /* Nothing To Do */\r
+ }\r
+ return;\r
+}\r
+\r
+/**\r
+ * @brief Register callbacks\r
+ * @param hdma pointer to a DMA_HandleTypeDef structure that contains\r
+ * the configuration information for the specified DMA Channel.\r
+ * @param CallbackID User Callback identifer\r
+ * a HAL_DMA_CallbackIDTypeDef ENUM as parameter.\r
+ * @param pCallback pointer to private callbacsk function which has pointer to\r
+ * a DMA_HandleTypeDef structure as parameter.\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_DMA_RegisterCallback(DMA_HandleTypeDef *hdma, HAL_DMA_CallbackIDTypeDef CallbackID, void (* pCallback)( DMA_HandleTypeDef * _hdma))\r
+{\r
+ HAL_StatusTypeDef status = HAL_OK;\r
+\r
+ /* Process locked */\r
+ __HAL_LOCK(hdma);\r
+\r
+ if(HAL_DMA_STATE_READY == hdma->State)\r
+ {\r
+ switch (CallbackID)\r
+ {\r
+ case HAL_DMA_XFER_CPLT_CB_ID:\r
+ hdma->XferCpltCallback = pCallback;\r
+ break;\r
+\r
+ case HAL_DMA_XFER_HALFCPLT_CB_ID:\r
+ hdma->XferHalfCpltCallback = pCallback;\r
+ break;\r
+\r
+ case HAL_DMA_XFER_ERROR_CB_ID:\r
+ hdma->XferErrorCallback = pCallback;\r
+ break;\r
+\r
+ case HAL_DMA_XFER_ABORT_CB_ID:\r
+ hdma->XferAbortCallback = pCallback;\r
+ break;\r
+\r
+ default:\r
+ status = HAL_ERROR;\r
+ break;\r
+ }\r
+ }\r
+ else\r
+ {\r
+ status = HAL_ERROR;\r
+ }\r
+\r
+ /* Release Lock */\r
+ __HAL_UNLOCK(hdma);\r
+\r
+ return status;\r
+}\r
+\r
+/**\r
+ * @brief UnRegister callbacks\r
+ * @param hdma pointer to a DMA_HandleTypeDef structure that contains\r
+ * the configuration information for the specified DMA Channel.\r
+ * @param CallbackID User Callback identifer\r
+ * a HAL_DMA_CallbackIDTypeDef ENUM as parameter.\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_DMA_UnRegisterCallback(DMA_HandleTypeDef *hdma, HAL_DMA_CallbackIDTypeDef CallbackID)\r
+{\r
+ HAL_StatusTypeDef status = HAL_OK;\r
+\r
+ /* Process locked */\r
+ __HAL_LOCK(hdma);\r
+\r
+ if(HAL_DMA_STATE_READY == hdma->State)\r
+ {\r
+ switch (CallbackID)\r
+ {\r
+ case HAL_DMA_XFER_CPLT_CB_ID:\r
+ hdma->XferCpltCallback = NULL;\r
+ break;\r
+\r
+ case HAL_DMA_XFER_HALFCPLT_CB_ID:\r
+ hdma->XferHalfCpltCallback = NULL;\r
+ break;\r
+\r
+ case HAL_DMA_XFER_ERROR_CB_ID:\r
+ hdma->XferErrorCallback = NULL;\r
+ break;\r
+\r
+ case HAL_DMA_XFER_ABORT_CB_ID:\r
+ hdma->XferAbortCallback = NULL;\r
+ break;\r
+\r
+ case HAL_DMA_XFER_ALL_CB_ID:\r
+ hdma->XferCpltCallback = NULL;\r
+ hdma->XferHalfCpltCallback = NULL;\r
+ hdma->XferErrorCallback = NULL;\r
+ hdma->XferAbortCallback = NULL;\r
+ break;\r
+\r
+ default:\r
+ status = HAL_ERROR;\r
+ break;\r
+ }\r
+ }\r
+ else\r
+ {\r
+ status = HAL_ERROR;\r
+ }\r
+\r
+ /* Release Lock */\r
+ __HAL_UNLOCK(hdma);\r
+\r
+ return status;\r
+}\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+\r
+\r
+/** @defgroup DMA_Exported_Functions_Group3 Peripheral State and Errors functions\r
+ * @brief Peripheral State and Errors functions\r
+ *\r
+@verbatim\r
+ ===============================================================================\r
+ ##### Peripheral State and Errors functions #####\r
+ ===============================================================================\r
+ [..]\r
+ This subsection provides functions allowing to\r
+ (+) Check the DMA state\r
+ (+) Get error code\r
+\r
+@endverbatim\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @brief Return the DMA handle state.\r
+ * @param hdma pointer to a DMA_HandleTypeDef structure that contains\r
+ * the configuration information for the specified DMA Channel.\r
+ * @retval HAL state\r
+ */\r
+HAL_DMA_StateTypeDef HAL_DMA_GetState(DMA_HandleTypeDef *hdma)\r
+{\r
+ /* Return DMA handle state */\r
+ return hdma->State;\r
+}\r
+\r
+/**\r
+ * @brief Return the DMA error code.\r
+ * @param hdma pointer to a DMA_HandleTypeDef structure that contains\r
+ * the configuration information for the specified DMA Channel.\r
+ * @retval DMA Error Code\r
+ */\r
+uint32_t HAL_DMA_GetError(DMA_HandleTypeDef *hdma)\r
+{\r
+ return hdma->ErrorCode;\r
+}\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @addtogroup DMA_Private_Functions\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @brief Sets the DMA Transfer parameter.\r
+ * @param hdma pointer to a DMA_HandleTypeDef structure that contains\r
+ * the configuration information for the specified DMA Channel.\r
+ * @param SrcAddress The source memory Buffer address\r
+ * @param DstAddress The destination memory Buffer address\r
+ * @param DataLength The length of data to be transferred from source to destination\r
+ * @retval HAL status\r
+ */\r
+static void DMA_SetConfig(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength)\r
+{\r
+ /* Clear all flags */\r
+ hdma->DmaBaseAddress->IFCR = (DMA_ISR_GIF1 << (hdma->ChannelIndex & 0x1CU));\r
+\r
+ /* Configure DMA Channel data length */\r
+ hdma->Instance->CNDTR = DataLength;\r
+\r
+ /* Memory to Peripheral */\r
+ if((hdma->Init.Direction) == DMA_MEMORY_TO_PERIPH)\r
+ {\r
+ /* Configure DMA Channel destination address */\r
+ hdma->Instance->CPAR = DstAddress;\r
+\r
+ /* Configure DMA Channel source address */\r
+ hdma->Instance->CMAR = SrcAddress;\r
+ }\r
+ /* Peripheral to Memory */\r
+ else\r
+ {\r
+ /* Configure DMA Channel source address */\r
+ hdma->Instance->CPAR = SrcAddress;\r
+\r
+ /* Configure DMA Channel destination address */\r
+ hdma->Instance->CMAR = DstAddress;\r
+ }\r
+}\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+#endif /* HAL_DMA_MODULE_ENABLED */\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\r
--- /dev/null
+/**\r
+ ******************************************************************************\r
+ * @file stm32l1xx_hal_flash.c\r
+ * @author MCD Application Team\r
+ * @brief FLASH HAL module driver.\r
+ * This file provides firmware functions to manage the following \r
+ * functionalities of the internal FLASH memory:\r
+ * + Program operations functions\r
+ * + Memory Control functions \r
+ * + Peripheral State functions\r
+ * \r
+ @verbatim\r
+ ==============================================================================\r
+ ##### FLASH peripheral features #####\r
+ ==============================================================================\r
+ [..] The Flash memory interface manages CPU AHB I-Code and D-Code accesses \r
+ to the Flash memory. It implements the erase and program Flash memory operations \r
+ and the read and write protection mechanisms.\r
+\r
+ [..] The Flash memory interface accelerates code execution with a system of instruction\r
+ prefetch. \r
+\r
+ [..] The FLASH main features are:\r
+ (+) Flash memory read operations\r
+ (+) Flash memory program/erase operations\r
+ (+) Read / write protections\r
+ (+) Prefetch on I-Code\r
+ (+) Option Bytes programming\r
+\r
+\r
+ ##### How to use this driver #####\r
+ ==============================================================================\r
+ [..] \r
+ This driver provides functions and macros to configure and program the FLASH \r
+ memory of all STM32L1xx devices.\r
+ \r
+ (#) FLASH Memory I/O Programming functions: this group includes all needed\r
+ functions to erase and program the main memory:\r
+ (++) Lock and Unlock the FLASH interface\r
+ (++) Erase function: Erase page\r
+ (++) Program functions: Fast Word and Half Page(should be \r
+ executed from internal SRAM).\r
+ \r
+ (#) DATA EEPROM Programming functions: this group includes all \r
+ needed functions to erase and program the DATA EEPROM memory:\r
+ (++) Lock and Unlock the DATA EEPROM interface.\r
+ (++) Erase function: Erase Byte, erase HalfWord, erase Word, erase \r
+ Double Word (should be executed from internal SRAM).\r
+ (++) Program functions: Fast Program Byte, Fast Program Half-Word, \r
+ FastProgramWord, Program Byte, Program Half-Word, \r
+ Program Word and Program Double-Word (should be executed \r
+ from internal SRAM).\r
+\r
+ (#) FLASH Option Bytes Programming functions: this group includes all needed\r
+ functions to manage the Option Bytes:\r
+ (++) Lock and Unlock the Option Bytes\r
+ (++) Set/Reset the write protection\r
+ (++) Set the Read protection Level\r
+ (++) Program the user Option Bytes\r
+ (++) Launch the Option Bytes loader\r
+ (++) Set/Get the Read protection Level.\r
+ (++) Set/Get the BOR level.\r
+ (++) Get the Write protection.\r
+ (++) Get the user option bytes.\r
+ \r
+ (#) Interrupts and flags management functions : this group \r
+ includes all needed functions to:\r
+ (++) Handle FLASH interrupts\r
+ (++) Wait for last FLASH operation according to its status\r
+ (++) Get error flag status\r
+\r
+ (#) FLASH Interface configuration functions: this group includes \r
+ the management of following features:\r
+ (++) Enable/Disable the RUN PowerDown mode.\r
+ (++) Enable/Disable the SLEEP PowerDown mode. \r
+ \r
+ (#) FLASH Peripheral State methods: this group includes \r
+ the management of following features:\r
+ (++) Wait for the FLASH operation\r
+ (++) Get the specific FLASH error flag\r
+ \r
+ [..] In addition to these function, this driver includes a set of macros allowing\r
+ to handle the following operations:\r
+ \r
+ (+) Set/Get the latency\r
+ (+) Enable/Disable the prefetch buffer\r
+ (+) Enable/Disable the 64 bit Read Access.\r
+ (+) Enable/Disable the Flash power-down\r
+ (+) Enable/Disable the FLASH interrupts\r
+ (+) Monitor the FLASH flags status\r
+ \r
+ ##### Programming operation functions #####\r
+ =============================================================================== \r
+ [..]\r
+ This subsection provides a set of functions allowing to manage the FLASH \r
+ program operations.\r
+ \r
+ [..] The FLASH Memory Programming functions, includes the following functions:\r
+ (+) HAL_FLASH_Unlock(void);\r
+ (+) HAL_FLASH_Lock(void);\r
+ (+) HAL_FLASH_Program(uint32_t TypeProgram, uint32_t Address, uint32_t Data)\r
+ (+) HAL_FLASH_Program_IT(uint32_t TypeProgram, uint32_t Address, uint32_t Data)\r
+ \r
+ [..] Any operation of erase or program should follow these steps:\r
+ (#) Call the HAL_FLASH_Unlock() function to enable the flash control register and \r
+ program memory access.\r
+ (#) Call the desired function to erase page or program data.\r
+ (#) Call the HAL_FLASH_Lock() to disable the flash program memory access \r
+ (recommended to protect the FLASH memory against possible unwanted operation).\r
+ \r
+ ##### Option Bytes Programming functions ##### \r
+ ============================================================================== \r
+ \r
+ [..] The FLASH_Option Bytes Programming_functions, includes the following functions:\r
+ (+) HAL_FLASH_OB_Unlock(void);\r
+ (+) HAL_FLASH_OB_Lock(void);\r
+ (+) HAL_FLASH_OB_Launch(void);\r
+ (+) HAL_FLASHEx_OBProgram(FLASH_OBProgramInitTypeDef *pOBInit);\r
+ (+) HAL_FLASHEx_OBGetConfig(FLASH_OBProgramInitTypeDef *pOBInit);\r
+ \r
+ [..] Any operation of erase or program should follow these steps:\r
+ (#) Call the HAL_FLASH_OB_Unlock() function to enable the Flash option control \r
+ register access.\r
+ (#) Call the following functions to program the desired option bytes.\r
+ (++) HAL_FLASHEx_OBProgram(FLASH_OBProgramInitTypeDef *pOBInit); \r
+ (#) Once all needed option bytes to be programmed are correctly written, call the\r
+ HAL_FLASH_OB_Launch(void) function to launch the Option Bytes programming process.\r
+ (#) Call the HAL_FLASH_OB_Lock() to disable the Flash option control register access (recommended\r
+ to protect the option Bytes against possible unwanted operations).\r
+ \r
+ [..] Proprietary code Read Out Protection (PcROP): \r
+ (#) The PcROP sector is selected by using the same option bytes as the Write\r
+ protection. As a result, these 2 options are exclusive each other.\r
+ (#) To activate PCROP mode for Flash sectors(s), you need to follow the sequence below:\r
+ (++) Use this function HAL_FLASHEx_AdvOBProgram with PCROPState = OB_PCROP_STATE_ENABLE.\r
+\r
+ @endverbatim\r
+ ******************************************************************************\r
+ * @attention\r
+ *\r
+ * <h2><center>© Copyright (c) 2017 STMicroelectronics.\r
+ * All rights reserved.</center></h2>\r
+ *\r
+ * This software component is licensed by ST under BSD 3-Clause license,\r
+ * the "License"; You may not use this file except in compliance with the\r
+ * License. You may obtain a copy of the License at:\r
+ * opensource.org/licenses/BSD-3-Clause\r
+ *\r
+ ******************************************************************************\r
+ */\r
+\r
+/* Includes ------------------------------------------------------------------*/\r
+#include "stm32l1xx_hal.h"\r
+\r
+/** @addtogroup STM32L1xx_HAL_Driver\r
+ * @{\r
+ */\r
+\r
+#ifdef HAL_FLASH_MODULE_ENABLED\r
+\r
+/** @defgroup FLASH FLASH\r
+ * @brief FLASH HAL module driver\r
+ * @{\r
+ */\r
+\r
+/* Private typedef -----------------------------------------------------------*/\r
+/* Private define ------------------------------------------------------------*/\r
+/** @defgroup FLASH_Private_Constants FLASH Private Constants\r
+ * @{\r
+ */\r
+/**\r
+ * @}\r
+ */\r
+\r
+/* Private macro ---------------------------- ---------------------------------*/\r
+/** @defgroup FLASH_Private_Macros FLASH Private Macros\r
+ * @{\r
+ */\r
+ \r
+/**\r
+ * @}\r
+ */\r
+\r
+/* Private variables ---------------------------------------------------------*/\r
+/** @defgroup FLASH_Private_Variables FLASH Private Variables\r
+ * @{\r
+ */\r
+/* Variables used for Erase pages under interruption*/\r
+FLASH_ProcessTypeDef pFlash;\r
+/**\r
+ * @}\r
+ */\r
+\r
+/* Private function prototypes -----------------------------------------------*/\r
+/** @defgroup FLASH_Private_Functions FLASH Private Functions\r
+ * @{\r
+ */\r
+static void FLASH_SetErrorCode(void);\r
+extern void FLASH_PageErase(uint32_t PageAddress);\r
+/**\r
+ * @}\r
+ */\r
+\r
+/* Exported functions ---------------------------------------------------------*/\r
+/** @defgroup FLASH_Exported_Functions FLASH Exported Functions\r
+ * @{\r
+ */\r
+ \r
+/** @defgroup FLASH_Exported_Functions_Group1 Programming operation functions \r
+ * @brief Programming operation functions \r
+ *\r
+@verbatim \r
+@endverbatim\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @brief Program word at a specified address\r
+ * @note To correctly run this function, the HAL_FLASH_Unlock() function\r
+ * must be called before.\r
+ * Call the HAL_FLASH_Lock() to disable the flash memory access\r
+ * (recommended to protect the FLASH memory against possible unwanted operation).\r
+ *\r
+ * @param TypeProgram Indicate the way to program at a specified address.\r
+ * This parameter can be a value of @ref FLASH_Type_Program\r
+ * @param Address Specifie the address to be programmed.\r
+ * @param Data Specifie the data to be programmed\r
+ * \r
+ * @retval HAL_StatusTypeDef HAL Status\r
+ */\r
+HAL_StatusTypeDef HAL_FLASH_Program(uint32_t TypeProgram, uint32_t Address, uint32_t Data)\r
+{\r
+ HAL_StatusTypeDef status = HAL_ERROR;\r
+ \r
+ /* Process Locked */\r
+ __HAL_LOCK(&pFlash);\r
+\r
+ /* Check the parameters */\r
+ assert_param(IS_FLASH_TYPEPROGRAM(TypeProgram));\r
+ assert_param(IS_FLASH_PROGRAM_ADDRESS(Address));\r
+\r
+ /* Wait for last operation to be completed */\r
+ status = FLASH_WaitForLastOperation(FLASH_TIMEOUT_VALUE);\r
+ \r
+ if(status == HAL_OK)\r
+ {\r
+ /* Clean the error context */\r
+ pFlash.ErrorCode = HAL_FLASH_ERROR_NONE;\r
+\r
+ /*Program word (32-bit) at a specified address.*/\r
+ *(__IO uint32_t *)Address = Data;\r
+\r
+ /* Wait for last operation to be completed */\r
+ status = FLASH_WaitForLastOperation(FLASH_TIMEOUT_VALUE);\r
+ }\r
+\r
+ /* Process Unlocked */\r
+ __HAL_UNLOCK(&pFlash);\r
+\r
+ return status;\r
+}\r
+\r
+/**\r
+ * @brief Program word at a specified address with interrupt enabled.\r
+ *\r
+ * @param TypeProgram Indicate the way to program at a specified address.\r
+ * This parameter can be a value of @ref FLASH_Type_Program\r
+ * @param Address Specifie the address to be programmed.\r
+ * @param Data Specifie the data to be programmed\r
+ * \r
+ * @retval HAL_StatusTypeDef HAL Status\r
+ */\r
+HAL_StatusTypeDef HAL_FLASH_Program_IT(uint32_t TypeProgram, uint32_t Address, uint32_t Data)\r
+{\r
+ HAL_StatusTypeDef status = HAL_OK;\r
+ \r
+ /* Process Locked */\r
+ __HAL_LOCK(&pFlash);\r
+\r
+ /* Check the parameters */\r
+ assert_param(IS_FLASH_TYPEPROGRAM(TypeProgram));\r
+ assert_param(IS_FLASH_PROGRAM_ADDRESS(Address));\r
+\r
+ /* Enable End of FLASH Operation and Error source interrupts */\r
+ __HAL_FLASH_ENABLE_IT(FLASH_IT_EOP | FLASH_IT_ERR);\r
+ \r
+ pFlash.Address = Address;\r
+ pFlash.ProcedureOnGoing = FLASH_PROC_PROGRAM;\r
+ /* Clean the error context */\r
+ pFlash.ErrorCode = HAL_FLASH_ERROR_NONE;\r
+\r
+ if(TypeProgram == FLASH_TYPEPROGRAM_WORD)\r
+ {\r
+ /* Program word (32-bit) at a specified address. */\r
+ *(__IO uint32_t *)Address = Data;\r
+ }\r
+ return status;\r
+}\r
+\r
+/**\r
+ * @brief This function handles FLASH interrupt request.\r
+ * @retval None\r
+ */\r
+void HAL_FLASH_IRQHandler(void)\r
+{\r
+ uint32_t addresstmp = 0U;\r
+ \r
+ /* Check FLASH operation error flags */\r
+ if( __HAL_FLASH_GET_FLAG(FLASH_FLAG_WRPERR) || \r
+ __HAL_FLASH_GET_FLAG(FLASH_FLAG_PGAERR) || \r
+ __HAL_FLASH_GET_FLAG(FLASH_FLAG_SIZERR) || \r
+#if defined(FLASH_SR_RDERR)\r
+ __HAL_FLASH_GET_FLAG(FLASH_FLAG_RDERR) || \r
+#endif /* FLASH_SR_RDERR */\r
+#if defined(FLASH_SR_OPTVERRUSR)\r
+ __HAL_FLASH_GET_FLAG(FLASH_FLAG_OPTVERRUSR) || \r
+#endif /* FLASH_SR_OPTVERRUSR */\r
+ __HAL_FLASH_GET_FLAG(FLASH_FLAG_OPTVERR) )\r
+ {\r
+ if(pFlash.ProcedureOnGoing == FLASH_PROC_PAGEERASE)\r
+ {\r
+ /* Return the faulty sector */\r
+ addresstmp = pFlash.Page;\r
+ pFlash.Page = 0xFFFFFFFFU;\r
+ }\r
+ else\r
+ {\r
+ /* Return the faulty address */\r
+ addresstmp = pFlash.Address;\r
+ }\r
+ /* Save the Error code */\r
+ FLASH_SetErrorCode();\r
+ \r
+ /* FLASH error interrupt user callback */\r
+ HAL_FLASH_OperationErrorCallback(addresstmp);\r
+\r
+ /* Stop the procedure ongoing */\r
+ pFlash.ProcedureOnGoing = FLASH_PROC_NONE;\r
+ }\r
+\r
+ /* Check FLASH End of Operation flag */\r
+ if(__HAL_FLASH_GET_FLAG(FLASH_FLAG_EOP))\r
+ {\r
+ /* Clear FLASH End of Operation pending bit */\r
+ __HAL_FLASH_CLEAR_FLAG(FLASH_FLAG_EOP);\r
+ \r
+ /* Process can continue only if no error detected */\r
+ if(pFlash.ProcedureOnGoing != FLASH_PROC_NONE)\r
+ {\r
+ if(pFlash.ProcedureOnGoing == FLASH_PROC_PAGEERASE)\r
+ {\r
+ /* Nb of pages to erased can be decreased */\r
+ pFlash.NbPagesToErase--;\r
+\r
+ /* Check if there are still pages to erase */\r
+ if(pFlash.NbPagesToErase != 0U)\r
+ {\r
+ addresstmp = pFlash.Page;\r
+ /*Indicate user which sector has been erased */\r
+ HAL_FLASH_EndOfOperationCallback(addresstmp);\r
+\r
+ /*Increment sector number*/\r
+ addresstmp = pFlash.Page + FLASH_PAGE_SIZE;\r
+ pFlash.Page = addresstmp;\r
+\r
+ /* If the erase operation is completed, disable the ERASE Bit */\r
+ CLEAR_BIT(FLASH->PECR, FLASH_PECR_ERASE);\r
+\r
+ FLASH_PageErase(addresstmp);\r
+ }\r
+ else\r
+ {\r
+ /* No more pages to Erase, user callback can be called. */\r
+ /* Reset Sector and stop Erase pages procedure */\r
+ pFlash.Page = addresstmp = 0xFFFFFFFFU;\r
+ pFlash.ProcedureOnGoing = FLASH_PROC_NONE;\r
+ /* FLASH EOP interrupt user callback */\r
+ HAL_FLASH_EndOfOperationCallback(addresstmp);\r
+ }\r
+ }\r
+ else\r
+ {\r
+ /* If the program operation is completed, disable the PROG Bit */\r
+ CLEAR_BIT(FLASH->PECR, FLASH_PECR_PROG);\r
+\r
+ /* Program ended. Return the selected address */\r
+ /* FLASH EOP interrupt user callback */\r
+ HAL_FLASH_EndOfOperationCallback(pFlash.Address);\r
+ \r
+ /* Reset Address and stop Program procedure */\r
+ pFlash.Address = 0xFFFFFFFFU;\r
+ pFlash.ProcedureOnGoing = FLASH_PROC_NONE;\r
+ }\r
+ }\r
+ }\r
+ \r
+\r
+ if(pFlash.ProcedureOnGoing == FLASH_PROC_NONE)\r
+ {\r
+ /* Operation is completed, disable the PROG and ERASE */\r
+ CLEAR_BIT(FLASH->PECR, (FLASH_PECR_ERASE | FLASH_PECR_PROG));\r
+\r
+ /* Disable End of FLASH Operation and Error source interrupts */\r
+ __HAL_FLASH_DISABLE_IT(FLASH_IT_EOP | FLASH_IT_ERR);\r
+\r
+ /* Process Unlocked */\r
+ __HAL_UNLOCK(&pFlash);\r
+ }\r
+}\r
+\r
+/**\r
+ * @brief FLASH end of operation interrupt callback\r
+ * @param ReturnValue The value saved in this parameter depends on the ongoing procedure\r
+ * - Pages Erase: Address of the page which has been erased \r
+ * (if 0xFFFFFFFF, it means that all the selected pages have been erased)\r
+ * - Program: Address which was selected for data program\r
+ * @retval none\r
+ */\r
+__weak void HAL_FLASH_EndOfOperationCallback(uint32_t ReturnValue)\r
+{\r
+ /* Prevent unused argument(s) compilation warning */\r
+ UNUSED(ReturnValue);\r
+\r
+ /* NOTE : This function Should not be modified, when the callback is needed,\r
+ the HAL_FLASH_EndOfOperationCallback could be implemented in the user file\r
+ */ \r
+}\r
+\r
+/**\r
+ * @brief FLASH operation error interrupt callback\r
+ * @param ReturnValue The value saved in this parameter depends on the ongoing procedure\r
+ * - Pages Erase: Address of the page which returned an error\r
+ * - Program: Address which was selected for data program\r
+ * @retval none\r
+ */\r
+__weak void HAL_FLASH_OperationErrorCallback(uint32_t ReturnValue)\r
+{\r
+ /* Prevent unused argument(s) compilation warning */\r
+ UNUSED(ReturnValue);\r
+\r
+ /* NOTE : This function Should not be modified, when the callback is needed,\r
+ the HAL_FLASH_OperationErrorCallback could be implemented in the user file\r
+ */ \r
+}\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup FLASH_Exported_Functions_Group2 Peripheral Control functions \r
+ * @brief management functions \r
+ *\r
+@verbatim \r
+ ===============================================================================\r
+ ##### Peripheral Control functions #####\r
+ =============================================================================== \r
+ [..]\r
+ This subsection provides a set of functions allowing to control the FLASH \r
+ memory operations.\r
+\r
+@endverbatim\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @brief Unlock the FLASH control register access\r
+ * @retval HAL Status\r
+ */\r
+HAL_StatusTypeDef HAL_FLASH_Unlock(void)\r
+{\r
+ if (HAL_IS_BIT_SET(FLASH->PECR, FLASH_PECR_PRGLOCK))\r
+ {\r
+ /* Unlocking FLASH_PECR register access*/\r
+ if(HAL_IS_BIT_SET(FLASH->PECR, FLASH_PECR_PELOCK))\r
+ { \r
+ WRITE_REG(FLASH->PEKEYR, FLASH_PEKEY1);\r
+ WRITE_REG(FLASH->PEKEYR, FLASH_PEKEY2);\r
+ \r
+ /* Verify that PELOCK is unlocked */\r
+ if(HAL_IS_BIT_SET(FLASH->PECR, FLASH_PECR_PELOCK))\r
+ {\r
+ return HAL_ERROR;\r
+ }\r
+ }\r
+ \r
+ /* Unlocking the program memory access */\r
+ WRITE_REG(FLASH->PRGKEYR, FLASH_PRGKEY1);\r
+ WRITE_REG(FLASH->PRGKEYR, FLASH_PRGKEY2); \r
+ \r
+ /* Verify that PRGLOCK is unlocked */\r
+ if (HAL_IS_BIT_SET(FLASH->PECR, FLASH_PECR_PRGLOCK))\r
+ {\r
+ return HAL_ERROR;\r
+ }\r
+ }\r
+ \r
+ return HAL_OK; \r
+}\r
+\r
+/**\r
+ * @brief Locks the FLASH control register access\r
+ * @retval HAL Status\r
+ */\r
+HAL_StatusTypeDef HAL_FLASH_Lock(void)\r
+{\r
+ /* Set the PRGLOCK Bit to lock the FLASH Registers access */\r
+ SET_BIT(FLASH->PECR, FLASH_PECR_PRGLOCK);\r
+ \r
+ return HAL_OK; \r
+}\r
+\r
+/**\r
+ * @brief Unlock the FLASH Option Control Registers access.\r
+ * @retval HAL Status\r
+ */\r
+HAL_StatusTypeDef HAL_FLASH_OB_Unlock(void)\r
+{\r
+ if(HAL_IS_BIT_SET(FLASH->PECR, FLASH_PECR_OPTLOCK))\r
+ {\r
+ /* Unlocking FLASH_PECR register access*/\r
+ if(HAL_IS_BIT_SET(FLASH->PECR, FLASH_PECR_PELOCK))\r
+ { \r
+ /* Unlocking FLASH_PECR register access*/\r
+ WRITE_REG(FLASH->PEKEYR, FLASH_PEKEY1);\r
+ WRITE_REG(FLASH->PEKEYR, FLASH_PEKEY2);\r
+\r
+ /* Verify that PELOCK is unlocked */\r
+ if(HAL_IS_BIT_SET(FLASH->PECR, FLASH_PECR_PELOCK))\r
+ {\r
+ return HAL_ERROR;\r
+ }\r
+ }\r
+\r
+ /* Unlocking the option bytes block access */\r
+ WRITE_REG(FLASH->OPTKEYR, FLASH_OPTKEY1);\r
+ WRITE_REG(FLASH->OPTKEYR, FLASH_OPTKEY2);\r
+\r
+ /* Verify that OPTLOCK is unlocked */\r
+ if (HAL_IS_BIT_SET(FLASH->PECR, FLASH_PECR_OPTLOCK))\r
+ {\r
+ return HAL_ERROR;\r
+ }\r
+ }\r
+ \r
+ return HAL_OK; \r
+}\r
+\r
+/**\r
+ * @brief Lock the FLASH Option Control Registers access.\r
+ * @retval HAL Status \r
+ */\r
+HAL_StatusTypeDef HAL_FLASH_OB_Lock(void)\r
+{\r
+ /* Set the OPTLOCK Bit to lock the option bytes block access */\r
+ SET_BIT(FLASH->PECR, FLASH_PECR_OPTLOCK);\r
+ \r
+ return HAL_OK; \r
+}\r
+ \r
+/**\r
+ * @brief Launch the option byte loading.\r
+ * @note This function will reset automatically the MCU.\r
+ * @retval HAL Status\r
+ */\r
+HAL_StatusTypeDef HAL_FLASH_OB_Launch(void)\r
+{\r
+ /* Set the OBL_Launch bit to launch the option byte loading */\r
+ SET_BIT(FLASH->PECR, FLASH_PECR_OBL_LAUNCH);\r
+ \r
+ /* Wait for last operation to be completed */\r
+ return(FLASH_WaitForLastOperation(FLASH_TIMEOUT_VALUE));\r
+}\r
+\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/** @defgroup FLASH_Exported_Functions_Group3 Peripheral errors functions \r
+ * @brief Peripheral errors functions \r
+ *\r
+@verbatim \r
+ ===============================================================================\r
+ ##### Peripheral Errors functions #####\r
+ =============================================================================== \r
+ [..]\r
+ This subsection permit to get in run-time errors of the FLASH peripheral.\r
+\r
+@endverbatim\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @brief Get the specific FLASH error flag.\r
+ * @retval FLASH_ErrorCode The returned value can be:\r
+ * @ref FLASH_Error_Codes\r
+ */\r
+uint32_t HAL_FLASH_GetError(void)\r
+{\r
+ return pFlash.ErrorCode;\r
+}\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @addtogroup FLASH_Private_Functions\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @brief Wait for a FLASH operation to complete.\r
+ * @param Timeout maximum flash operation timeout\r
+ * @retval HAL Status\r
+ */\r
+HAL_StatusTypeDef FLASH_WaitForLastOperation(uint32_t Timeout)\r
+{\r
+ /* Wait for the FLASH operation to complete by polling on BUSY flag to be reset.\r
+ Even if the FLASH operation fails, the BUSY flag will be reset and an error\r
+ flag will be set */\r
+ \r
+ uint32_t tickstart = HAL_GetTick();\r
+ \r
+ while(__HAL_FLASH_GET_FLAG(FLASH_FLAG_BSY)) \r
+ { \r
+ if (Timeout != HAL_MAX_DELAY)\r
+ {\r
+ if((Timeout == 0U) || ((HAL_GetTick()-tickstart) > Timeout))\r
+ {\r
+ return HAL_TIMEOUT;\r
+ }\r
+ }\r
+ }\r
+ \r
+ /* Check FLASH End of Operation flag */\r
+ if (__HAL_FLASH_GET_FLAG(FLASH_FLAG_EOP))\r
+ {\r
+ /* Clear FLASH End of Operation pending bit */\r
+ __HAL_FLASH_CLEAR_FLAG(FLASH_FLAG_EOP);\r
+ }\r
+ \r
+ if(__HAL_FLASH_GET_FLAG(FLASH_FLAG_WRPERR) || \r
+ __HAL_FLASH_GET_FLAG(FLASH_FLAG_OPTVERR) || \r
+#if defined(FLASH_SR_RDERR)\r
+ __HAL_FLASH_GET_FLAG(FLASH_FLAG_RDERR) || \r
+#endif /* FLASH_SR_RDERR */\r
+#if defined(FLASH_SR_OPTVERRUSR)\r
+ __HAL_FLASH_GET_FLAG(FLASH_FLAG_OPTVERRUSR) || \r
+#endif /* FLASH_SR_OPTVERRUSR */\r
+ __HAL_FLASH_GET_FLAG(FLASH_FLAG_PGAERR))\r
+ {\r
+ /*Save the error code*/\r
+ FLASH_SetErrorCode();\r
+ return HAL_ERROR;\r
+ }\r
+\r
+ /* There is no error flag set */\r
+ return HAL_OK;\r
+}\r
+\r
+\r
+/**\r
+ * @brief Set the specific FLASH error flag.\r
+ * @retval None\r
+ */\r
+static void FLASH_SetErrorCode(void)\r
+{\r
+ uint32_t flags = 0U;\r
+ \r
+ if(__HAL_FLASH_GET_FLAG(FLASH_FLAG_WRPERR))\r
+ {\r
+ pFlash.ErrorCode |= HAL_FLASH_ERROR_WRP;\r
+ flags |= FLASH_FLAG_WRPERR;\r
+ }\r
+ if(__HAL_FLASH_GET_FLAG(FLASH_FLAG_PGAERR))\r
+ {\r
+ pFlash.ErrorCode |= HAL_FLASH_ERROR_PGA;\r
+ flags |= FLASH_FLAG_PGAERR;\r
+ }\r
+ if(__HAL_FLASH_GET_FLAG(FLASH_FLAG_OPTVERR))\r
+ {\r
+ pFlash.ErrorCode |= HAL_FLASH_ERROR_OPTV;\r
+ flags |= FLASH_FLAG_OPTVERR;\r
+ }\r
+\r
+#if defined(FLASH_SR_RDERR)\r
+ if(__HAL_FLASH_GET_FLAG(FLASH_FLAG_RDERR))\r
+ {\r
+ pFlash.ErrorCode |= HAL_FLASH_ERROR_RD;\r
+ flags |= FLASH_FLAG_RDERR;\r
+ }\r
+#endif /* FLASH_SR_RDERR */\r
+#if defined(FLASH_SR_OPTVERRUSR)\r
+ if(__HAL_FLASH_GET_FLAG(FLASH_FLAG_OPTVERRUSR))\r
+ {\r
+ pFlash.ErrorCode |= HAL_FLASH_ERROR_OPTVUSR;\r
+ flags |= FLASH_FLAG_OPTVERRUSR;\r
+ }\r
+#endif /* FLASH_SR_OPTVERRUSR */\r
+\r
+ /* Clear FLASH error pending bits */\r
+ __HAL_FLASH_CLEAR_FLAG(flags);\r
+} \r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+#endif /* HAL_FLASH_MODULE_ENABLED */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\r
--- /dev/null
+/**\r
+ ******************************************************************************\r
+ * @file stm32l1xx_hal_flash_ex.c\r
+ * @author MCD Application Team\r
+ * @brief Extended FLASH HAL module driver.\r
+ * \r
+ * This file provides firmware functions to manage the following \r
+ * functionalities of the internal FLASH memory:\r
+ * + FLASH Interface configuration\r
+ * + FLASH Memory Erasing\r
+ * + DATA EEPROM Programming/Erasing\r
+ * + Option Bytes Programming\r
+ * + Interrupts management\r
+ * \r
+ @verbatim\r
+ ==============================================================================\r
+ ##### Flash peripheral Extended features #####\r
+ ==============================================================================\r
+ \r
+ [..] Comparing to other products, the FLASH interface for STM32L1xx\r
+ devices contains the following additional features \r
+ (+) Erase functions\r
+ (+) DATA_EEPROM memory management\r
+ (+) BOOT option bit configuration \r
+ (+) PCROP protection for all sectors\r
+ \r
+ ##### How to use this driver #####\r
+ ==============================================================================\r
+ [..] This driver provides functions to configure and program the FLASH memory \r
+ of all STM32L1xx. It includes:\r
+ (+) Full DATA_EEPROM erase and program management\r
+ (+) Boot activation\r
+ (+) PCROP protection configuration and control for all pages\r
+ \r
+ @endverbatim\r
+ ******************************************************************************\r
+ * @attention\r
+ *\r
+ * <h2><center>© Copyright (c) 2017 STMicroelectronics.\r
+ * All rights reserved.</center></h2>\r
+ *\r
+ * This software component is licensed by ST under BSD 3-Clause license,\r
+ * the "License"; You may not use this file except in compliance with the\r
+ * License. You may obtain a copy of the License at:\r
+ * opensource.org/licenses/BSD-3-Clause\r
+ *\r
+ ******************************************************************************\r
+ */ \r
+\r
+/* Includes ------------------------------------------------------------------*/\r
+#include "stm32l1xx_hal.h"\r
+\r
+/** @addtogroup STM32L1xx_HAL_Driver\r
+ * @{\r
+ */\r
+#ifdef HAL_FLASH_MODULE_ENABLED\r
+\r
+/** @addtogroup FLASH\r
+ * @{\r
+ */\r
+/** @addtogroup FLASH_Private_Variables\r
+ * @{\r
+ */\r
+/* Variables used for Erase pages under interruption*/\r
+extern FLASH_ProcessTypeDef pFlash;\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+ \r
+/** @defgroup FLASHEx FLASHEx\r
+ * @brief FLASH HAL Extension module driver\r
+ * @{\r
+ */\r
+\r
+/* Private typedef -----------------------------------------------------------*/\r
+/* Private define ------------------------------------------------------------*/\r
+/** @defgroup FLASHEx_Private_Constants FLASHEx Private Constants\r
+ * @{\r
+ */\r
+/**\r
+ * @}\r
+ */\r
+\r
+/* Private macro -------------------------------------------------------------*/\r
+/** @defgroup FLASHEx_Private_Macros FLASHEx Private Macros\r
+ * @{\r
+ */\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/* Private variables ---------------------------------------------------------*/\r
+/* Private function prototypes -----------------------------------------------*/\r
+/** @defgroup FLASHEx_Private_Functions FLASHEx Private Functions\r
+ * @{\r
+ */\r
+void FLASH_PageErase(uint32_t PageAddress);\r
+static HAL_StatusTypeDef FLASH_OB_WRPConfig(FLASH_OBProgramInitTypeDef *pOBInit, FunctionalState NewState);\r
+static void FLASH_OB_WRPConfigWRP1OrPCROP1(uint32_t WRP1OrPCROP1, FunctionalState NewState);\r
+#if defined(STM32L100xC) || defined(STM32L151xC) || defined(STM32L152xC) || defined(STM32L162xC) \\r
+ || defined(STM32L151xCA) || defined(STM32L151xD) || defined(STM32L151xDX) || defined(STM32L152xCA) \\r
+ || defined(STM32L152xD) || defined(STM32L152xDX) || defined(STM32L162xCA) || defined(STM32L162xD) \\r
+ || defined(STM32L162xDX) || defined(STM32L151xE) || defined(STM32L152xE) || defined(STM32L162xE)\r
+static void FLASH_OB_WRPConfigWRP2OrPCROP2(uint32_t WRP2OrPCROP2, FunctionalState NewState);\r
+#endif /* STM32L100xC || STM32L151xC || STM32L152xC || (...) || STM32L151xE || STM32L152xE || STM32L162xE */\r
+#if defined(STM32L151xD) || defined(STM32L151xDX) || defined(STM32L152xD) || defined(STM32L152xDX) \\r
+ || defined(STM32L162xD) || defined(STM32L162xDX) || defined(STM32L151xE) || defined(STM32L152xE) \\r
+ || defined(STM32L162xE)\r
+static void FLASH_OB_WRPConfigWRP3(uint32_t WRP3, FunctionalState NewState);\r
+#endif /* STM32L151xD || STM32L152xD || STM32L162xD || STM32L151xE || STM32L152xE || STM32L162xE */\r
+#if defined(STM32L151xE) || defined(STM32L152xE) || defined(STM32L162xE) || defined(STM32L151xDX) \\r
+ || defined(STM32L152xDX) || defined(STM32L162xDX)\r
+static void FLASH_OB_WRPConfigWRP4(uint32_t WRP4, FunctionalState NewState);\r
+#endif /* STM32L151xE || STM32L152xE || STM32L151xDX || ... */\r
+#if defined(FLASH_OBR_SPRMOD)\r
+static HAL_StatusTypeDef FLASH_OB_PCROPConfig(FLASH_AdvOBProgramInitTypeDef *pAdvOBInit, FunctionalState NewState);\r
+#endif /* FLASH_OBR_SPRMOD */\r
+#if defined(FLASH_OBR_nRST_BFB2)\r
+static HAL_StatusTypeDef FLASH_OB_BootConfig(uint8_t OB_BOOT);\r
+#endif /* FLASH_OBR_nRST_BFB2 */\r
+static HAL_StatusTypeDef FLASH_OB_RDPConfig(uint8_t OB_RDP);\r
+static HAL_StatusTypeDef FLASH_OB_UserConfig(uint8_t OB_IWDG, uint8_t OB_STOP, uint8_t OB_STDBY);\r
+static HAL_StatusTypeDef FLASH_OB_BORConfig(uint8_t OB_BOR);\r
+static uint8_t FLASH_OB_GetRDP(void);\r
+static uint8_t FLASH_OB_GetUser(void);\r
+static uint8_t FLASH_OB_GetBOR(void);\r
+static HAL_StatusTypeDef FLASH_DATAEEPROM_FastProgramByte(uint32_t Address, uint8_t Data);\r
+static HAL_StatusTypeDef FLASH_DATAEEPROM_FastProgramHalfWord(uint32_t Address, uint16_t Data);\r
+static HAL_StatusTypeDef FLASH_DATAEEPROM_FastProgramWord(uint32_t Address, uint32_t Data);\r
+static HAL_StatusTypeDef FLASH_DATAEEPROM_ProgramWord(uint32_t Address, uint32_t Data);\r
+static HAL_StatusTypeDef FLASH_DATAEEPROM_ProgramHalfWord(uint32_t Address, uint16_t Data);\r
+static HAL_StatusTypeDef FLASH_DATAEEPROM_ProgramByte(uint32_t Address, uint8_t Data);\r
+/**\r
+ * @}\r
+ */\r
+\r
+/* Exported functions ---------------------------------------------------------*/\r
+/** @defgroup FLASHEx_Exported_Functions FLASHEx Exported Functions\r
+ * @{\r
+ */\r
+\r
+/** @defgroup FLASHEx_Exported_Functions_Group1 FLASHEx Memory Erasing functions\r
+ * @brief FLASH Memory Erasing functions\r
+ *\r
+@verbatim \r
+ ==============================================================================\r
+ ##### FLASH Erasing Programming functions ##### \r
+ ==============================================================================\r
+\r
+ [..] The FLASH Memory Erasing functions, includes the following functions:\r
+ (+) @ref HAL_FLASHEx_Erase: return only when erase has been done\r
+ (+) @ref HAL_FLASHEx_Erase_IT: end of erase is done when @ref HAL_FLASH_EndOfOperationCallback \r
+ is called with parameter 0xFFFFFFFF\r
+\r
+ [..] Any operation of erase should follow these steps:\r
+ (#) Call the @ref HAL_FLASH_Unlock() function to enable the flash control register and \r
+ program memory access.\r
+ (#) Call the desired function to erase page.\r
+ (#) Call the @ref HAL_FLASH_Lock() to disable the flash program memory access \r
+ (recommended to protect the FLASH memory against possible unwanted operation).\r
+\r
+@endverbatim\r
+ * @{\r
+ */\r
+ \r
+/**\r
+ * @brief Erase the specified FLASH memory Pages \r
+ * @note To correctly run this function, the @ref HAL_FLASH_Unlock() function\r
+ * must be called before.\r
+ * Call the @ref HAL_FLASH_Lock() to disable the flash memory access \r
+ * (recommended to protect the FLASH memory against possible unwanted operation)\r
+ * @note For STM32L151xDX/STM32L152xDX/STM32L162xDX, as memory is not continuous between\r
+ * 2 banks, user should perform pages erase by bank only.\r
+ * @param[in] pEraseInit pointer to an FLASH_EraseInitTypeDef structure that\r
+ * contains the configuration information for the erasing.\r
+ * \r
+ * @param[out] PageError pointer to variable that\r
+ * contains the configuration information on faulty page in case of error\r
+ * (0xFFFFFFFF means that all the pages have been correctly erased)\r
+ * \r
+ * @retval HAL_StatusTypeDef HAL Status\r
+ */\r
+HAL_StatusTypeDef HAL_FLASHEx_Erase(FLASH_EraseInitTypeDef *pEraseInit, uint32_t *PageError)\r
+{\r
+ HAL_StatusTypeDef status = HAL_ERROR;\r
+ uint32_t address = 0U;\r
+ \r
+ /* Process Locked */\r
+ __HAL_LOCK(&pFlash);\r
+\r
+ /* Wait for last operation to be completed */\r
+ status = FLASH_WaitForLastOperation(FLASH_TIMEOUT_VALUE);\r
+\r
+ if (status == HAL_OK)\r
+ {\r
+ /*Initialization of PageError variable*/\r
+ *PageError = 0xFFFFFFFFU;\r
+\r
+ /* Check the parameters */\r
+ assert_param(IS_NBPAGES(pEraseInit->NbPages));\r
+ assert_param(IS_FLASH_TYPEERASE(pEraseInit->TypeErase));\r
+ assert_param(IS_FLASH_PROGRAM_ADDRESS(pEraseInit->PageAddress));\r
+ assert_param(IS_FLASH_PROGRAM_ADDRESS((pEraseInit->PageAddress & ~(FLASH_PAGE_SIZE - 1U)) + pEraseInit->NbPages * FLASH_PAGE_SIZE - 1U));\r
+\r
+#if defined(STM32L151xDX) || defined(STM32L152xDX) || defined(STM32L162xDX)\r
+ /* Check on which bank belongs the 1st address to erase */\r
+ if (pEraseInit->PageAddress < FLASH_BANK2_BASE)\r
+ {\r
+ /* BANK1 */\r
+ /* Check that last page to erase still belongs to BANK1 */\r
+ if (((pEraseInit->PageAddress & ~(FLASH_PAGE_SIZE - 1U)) + pEraseInit->NbPages * FLASH_PAGE_SIZE - 1U) > FLASH_BANK1_END)\r
+ {\r
+ /* Last page does not belong to BANK1, erase procedure cannot be performed because memory is not\r
+ continuous */\r
+ /* Process Unlocked */\r
+ __HAL_UNLOCK(&pFlash);\r
+ return HAL_ERROR;\r
+ }\r
+ }\r
+ else\r
+ {\r
+ /* BANK2 */\r
+ /* Check that last page to erase still belongs to BANK2 */\r
+ if (((pEraseInit->PageAddress & ~(FLASH_PAGE_SIZE - 1U)) + pEraseInit->NbPages * FLASH_PAGE_SIZE - 1U) > FLASH_BANK2_END)\r
+ {\r
+ /* Last page does not belong to BANK2, erase procedure cannot be performed because memory is not\r
+ continuous */\r
+ /* Process Unlocked */\r
+ __HAL_UNLOCK(&pFlash);\r
+ return HAL_ERROR;\r
+ }\r
+ }\r
+#endif /* STM32L151xDX || STM32L152xDX || STM32L162xDX */\r
+\r
+ /* Erase page by page to be done*/\r
+ for(address = pEraseInit->PageAddress; \r
+ address < ((pEraseInit->NbPages * FLASH_PAGE_SIZE) + pEraseInit->PageAddress);\r
+ address += FLASH_PAGE_SIZE)\r
+ {\r
+ FLASH_PageErase(address);\r
+\r
+ /* Wait for last operation to be completed */\r
+ status = FLASH_WaitForLastOperation(FLASH_TIMEOUT_VALUE);\r
+\r
+ /* If the erase operation is completed, disable the ERASE Bit */\r
+ CLEAR_BIT(FLASH->PECR, FLASH_PECR_PROG);\r
+ CLEAR_BIT(FLASH->PECR, FLASH_PECR_ERASE);\r
+\r
+ if (status != HAL_OK) \r
+ {\r
+ /* In case of error, stop erase procedure and return the faulty address */\r
+ *PageError = address;\r
+ break;\r
+ }\r
+ }\r
+ }\r
+\r
+ /* Process Unlocked */\r
+ __HAL_UNLOCK(&pFlash);\r
+\r
+ return status;\r
+}\r
+\r
+/**\r
+ * @brief Perform a page erase of the specified FLASH memory pages with interrupt enabled\r
+ * @note To correctly run this function, the @ref HAL_FLASH_Unlock() function\r
+ * must be called before.\r
+ * Call the @ref HAL_FLASH_Lock() to disable the flash memory access \r
+ * (recommended to protect the FLASH memory against possible unwanted operation)\r
+ * End of erase is done when @ref HAL_FLASH_EndOfOperationCallback is called with parameter\r
+ * 0xFFFFFFFF\r
+ * @note For STM32L151xDX/STM32L152xDX/STM32L162xDX, as memory is not continuous between\r
+ * 2 banks, user should perform pages erase by bank only.\r
+ * @param pEraseInit pointer to an FLASH_EraseInitTypeDef structure that\r
+ * contains the configuration information for the erasing.\r
+ * \r
+ * @retval HAL_StatusTypeDef HAL Status\r
+ */\r
+HAL_StatusTypeDef HAL_FLASHEx_Erase_IT(FLASH_EraseInitTypeDef *pEraseInit)\r
+{\r
+ HAL_StatusTypeDef status = HAL_ERROR;\r
+\r
+ /* If procedure already ongoing, reject the next one */\r
+ if (pFlash.ProcedureOnGoing != FLASH_PROC_NONE)\r
+ {\r
+ return HAL_ERROR;\r
+ }\r
+\r
+ /* Check the parameters */\r
+ assert_param(IS_NBPAGES(pEraseInit->NbPages));\r
+ assert_param(IS_FLASH_TYPEERASE(pEraseInit->TypeErase));\r
+ assert_param(IS_FLASH_PROGRAM_ADDRESS(pEraseInit->PageAddress));\r
+ assert_param(IS_FLASH_PROGRAM_ADDRESS((pEraseInit->PageAddress & ~(FLASH_PAGE_SIZE - 1U)) + pEraseInit->NbPages * FLASH_PAGE_SIZE - 1U));\r
+\r
+ /* Process Locked */\r
+ __HAL_LOCK(&pFlash);\r
+\r
+#if defined(STM32L151xDX) || defined(STM32L152xDX) || defined(STM32L162xDX)\r
+ /* Check on which bank belongs the 1st address to erase */\r
+ if (pEraseInit->PageAddress < FLASH_BANK2_BASE)\r
+ {\r
+ /* BANK1 */\r
+ /* Check that last page to erase still belongs to BANK1 */\r
+ if (((pEraseInit->PageAddress & ~(FLASH_PAGE_SIZE - 1U)) + pEraseInit->NbPages * FLASH_PAGE_SIZE - 1U) > FLASH_BANK1_END)\r
+ {\r
+ /* Last page does not belong to BANK1, erase procedure cannot be performed because memory is not\r
+ continuous */\r
+ /* Process Unlocked */\r
+ __HAL_UNLOCK(&pFlash);\r
+ return HAL_ERROR;\r
+ }\r
+ }\r
+ else\r
+ {\r
+ /* BANK2 */\r
+ /* Check that last page to erase still belongs to BANK2 */\r
+ if (((pEraseInit->PageAddress & ~(FLASH_PAGE_SIZE - 1U)) + pEraseInit->NbPages * FLASH_PAGE_SIZE - 1U) > FLASH_BANK2_END)\r
+ {\r
+ /* Last page does not belong to BANK2, erase procedure cannot be performed because memory is not\r
+ continuous */\r
+ /* Process Unlocked */\r
+ __HAL_UNLOCK(&pFlash);\r
+ return HAL_ERROR;\r
+ }\r
+ }\r
+#endif /* STM32L151xDX || STM32L152xDX || STM32L162xDX */\r
+\r
+ /* Wait for last operation to be completed */\r
+ status = FLASH_WaitForLastOperation(FLASH_TIMEOUT_VALUE);\r
+ \r
+ if (status == HAL_OK)\r
+ {\r
+ /* Enable End of FLASH Operation and Error source interrupts */\r
+ __HAL_FLASH_ENABLE_IT(FLASH_IT_EOP | FLASH_IT_ERR);\r
+ \r
+ pFlash.ProcedureOnGoing = FLASH_PROC_PAGEERASE;\r
+ pFlash.NbPagesToErase = pEraseInit->NbPages;\r
+ pFlash.Page = pEraseInit->PageAddress;\r
+\r
+ /*Erase 1st page and wait for IT*/\r
+ FLASH_PageErase(pEraseInit->PageAddress);\r
+ }\r
+ else\r
+ {\r
+ /* Process Unlocked */\r
+ __HAL_UNLOCK(&pFlash);\r
+ }\r
+\r
+ return status;\r
+}\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup FLASHEx_Exported_Functions_Group2 Option Bytes Programming functions\r
+ * @brief Option Bytes Programming functions\r
+ *\r
+@verbatim \r
+ ==============================================================================\r
+ ##### Option Bytes Programming functions ##### \r
+ ============================================================================== \r
+\r
+ [..] Any operation of erase or program should follow these steps:\r
+ (#) Call the @ref HAL_FLASH_OB_Unlock() function to enable the Flash option control \r
+ register access.\r
+ (#) Call following function to program the desired option bytes.\r
+ (++) @ref HAL_FLASHEx_OBProgram:\r
+ - To Enable/Disable the desired sector write protection.\r
+ - To set the desired read Protection Level.\r
+ - To configure the user option Bytes: IWDG, STOP and the Standby.\r
+ - To Set the BOR level.\r
+ (#) Once all needed option bytes to be programmed are correctly written, call the\r
+ @ref HAL_FLASH_OB_Launch(void) function to launch the Option Bytes programming process.\r
+ (#) Call the @ref HAL_FLASH_OB_Lock() to disable the Flash option control register access (recommended\r
+ to protect the option Bytes against possible unwanted operations).\r
+\r
+ [..] Proprietary code Read Out Protection (PcROP):\r
+ (#) The PcROP sector is selected by using the same option bytes as the Write\r
+ protection (nWRPi bits). As a result, these 2 options are exclusive each other.\r
+ (#) In order to activate the PcROP (change the function of the nWRPi option bits), \r
+ the SPRMOD option bit must be activated.\r
+ (#) The active value of nWRPi bits is inverted when PCROP mode is active, this\r
+ means: if SPRMOD = 1 and nWRPi = 1 (default value), then the user sector "i"\r
+ is read/write protected.\r
+ (#) To activate PCROP mode for Flash sector(s), you need to call the following function:\r
+ (++) @ref HAL_FLASHEx_AdvOBProgram in selecting sectors to be read/write protected\r
+ (++) @ref HAL_FLASHEx_OB_SelectPCROP to enable the read/write protection\r
+ (#) PcROP is available only in STM32L151xBA, STM32L152xBA, STM32L151xC, STM32L152xC & STM32L162xC devices.\r
+\r
+@endverbatim\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @brief Program option bytes\r
+ * @param pOBInit pointer to an FLASH_OBInitStruct structure that\r
+ * contains the configuration information for the programming.\r
+ * \r
+ * @retval HAL_StatusTypeDef HAL Status\r
+ */\r
+HAL_StatusTypeDef HAL_FLASHEx_OBProgram(FLASH_OBProgramInitTypeDef *pOBInit)\r
+{\r
+ HAL_StatusTypeDef status = HAL_ERROR;\r
+ \r
+ /* Process Locked */\r
+ __HAL_LOCK(&pFlash);\r
+\r
+ /* Check the parameters */\r
+ assert_param(IS_OPTIONBYTE(pOBInit->OptionType));\r
+\r
+ /*Write protection configuration*/\r
+ if((pOBInit->OptionType & OPTIONBYTE_WRP) == OPTIONBYTE_WRP)\r
+ {\r
+ assert_param(IS_WRPSTATE(pOBInit->WRPState));\r
+ if (pOBInit->WRPState == OB_WRPSTATE_ENABLE)\r
+ {\r
+ /* Enable of Write protection on the selected Sector*/\r
+ status = FLASH_OB_WRPConfig(pOBInit, ENABLE);\r
+ }\r
+ else\r
+ {\r
+ /* Disable of Write protection on the selected Sector*/\r
+ status = FLASH_OB_WRPConfig(pOBInit, DISABLE);\r
+ }\r
+ if (status != HAL_OK)\r
+ {\r
+ /* Process Unlocked */\r
+ __HAL_UNLOCK(&pFlash);\r
+ return status;\r
+ }\r
+ }\r
+ \r
+ /* Read protection configuration*/\r
+ if((pOBInit->OptionType & OPTIONBYTE_RDP) == OPTIONBYTE_RDP)\r
+ {\r
+ status = FLASH_OB_RDPConfig(pOBInit->RDPLevel);\r
+ if (status != HAL_OK)\r
+ {\r
+ /* Process Unlocked */\r
+ __HAL_UNLOCK(&pFlash);\r
+ return status;\r
+ }\r
+ }\r
+ \r
+ /* USER configuration*/\r
+ if((pOBInit->OptionType & OPTIONBYTE_USER) == OPTIONBYTE_USER)\r
+ {\r
+ status = FLASH_OB_UserConfig(pOBInit->USERConfig & OB_IWDG_SW, \r
+ pOBInit->USERConfig & OB_STOP_NORST,\r
+ pOBInit->USERConfig & OB_STDBY_NORST);\r
+ if (status != HAL_OK)\r
+ {\r
+ /* Process Unlocked */\r
+ __HAL_UNLOCK(&pFlash);\r
+ return status;\r
+ }\r
+ }\r
+\r
+ /* BOR Level configuration*/\r
+ if((pOBInit->OptionType & OPTIONBYTE_BOR) == OPTIONBYTE_BOR)\r
+ {\r
+ status = FLASH_OB_BORConfig(pOBInit->BORLevel);\r
+ if (status != HAL_OK)\r
+ {\r
+ /* Process Unlocked */\r
+ __HAL_UNLOCK(&pFlash);\r
+ return status;\r
+ }\r
+ }\r
+ /* Process Unlocked */\r
+ __HAL_UNLOCK(&pFlash);\r
+\r
+ return status;\r
+}\r
+\r
+/**\r
+ * @brief Get the Option byte configuration\r
+ * @param pOBInit pointer to an FLASH_OBInitStruct structure that\r
+ * contains the configuration information for the programming.\r
+ * \r
+ * @retval None\r
+ */\r
+void HAL_FLASHEx_OBGetConfig(FLASH_OBProgramInitTypeDef *pOBInit)\r
+{\r
+ pOBInit->OptionType = OPTIONBYTE_WRP | OPTIONBYTE_RDP | OPTIONBYTE_USER | OPTIONBYTE_BOR;\r
+\r
+ /*Get WRP1*/\r
+ pOBInit->WRPSector0To31 = (uint32_t)(FLASH->WRPR1);\r
+\r
+#if defined(STM32L100xC) || defined(STM32L151xC) || defined(STM32L152xC) || defined(STM32L162xC) \\r
+ || defined(STM32L151xCA) || defined(STM32L151xD) || defined(STM32L151xDX) || defined(STM32L152xCA) \\r
+ || defined(STM32L152xD) || defined(STM32L152xDX) || defined(STM32L162xCA) || defined(STM32L162xD) \\r
+ || defined(STM32L162xDX) || defined(STM32L151xE) || defined(STM32L152xE) || defined(STM32L162xE)\r
+ \r
+ /*Get WRP2*/\r
+ pOBInit->WRPSector32To63 = (uint32_t)(FLASH->WRPR2);\r
+\r
+#endif /* STM32L100xC || STM32L151xC || STM32L152xC || (...) || STM32L151xE || STM32L152xE || STM32L162xE */\r
+ \r
+#if defined(STM32L151xD) || defined(STM32L151xDX) || defined(STM32L152xD) || defined(STM32L152xDX) \\r
+ || defined(STM32L162xD) || defined(STM32L162xDX) || defined(STM32L151xE) || defined(STM32L152xE) \\r
+ || defined(STM32L162xE)\r
+ \r
+ /*Get WRP3*/\r
+ pOBInit->WRPSector64To95 = (uint32_t)(FLASH->WRPR3);\r
+\r
+#endif /* STM32L151xD || STM32L152xD || STM32L162xD || STM32L151xE || STM32L152xE || STM32L162xE */\r
+ \r
+#if defined(STM32L151xE) || defined(STM32L152xE) || defined(STM32L162xE) || defined(STM32L151xDX) \\r
+ || defined(STM32L152xDX) || defined(STM32L162xDX)\r
+\r
+ /*Get WRP4*/\r
+ pOBInit->WRPSector96To127 = (uint32_t)(FLASH->WRPR4);\r
+\r
+#endif /* STM32L151xE || STM32L152xE || STM32L162xE || STM32L151xDX || ... */\r
+\r
+ /*Get RDP Level*/\r
+ pOBInit->RDPLevel = FLASH_OB_GetRDP();\r
+\r
+ /*Get USER*/\r
+ pOBInit->USERConfig = FLASH_OB_GetUser();\r
+\r
+ /*Get BOR Level*/\r
+ pOBInit->BORLevel = FLASH_OB_GetBOR();\r
+}\r
+\r
+#if defined(FLASH_OBR_SPRMOD) || defined(FLASH_OBR_nRST_BFB2)\r
+ \r
+/**\r
+ * @brief Program option bytes\r
+ * @note This function can be used only for Cat2 & Cat3 devices for PCROP and Cat4 & Cat5 for BFB2.\r
+ * @param pAdvOBInit pointer to an FLASH_AdvOBProgramInitTypeDef structure that\r
+ * contains the configuration information for the programming.\r
+ * \r
+ * @retval HAL_StatusTypeDef HAL Status\r
+ */\r
+HAL_StatusTypeDef HAL_FLASHEx_AdvOBProgram (FLASH_AdvOBProgramInitTypeDef *pAdvOBInit)\r
+{\r
+ HAL_StatusTypeDef status = HAL_ERROR;\r
+ \r
+ /* Check the parameters */\r
+ assert_param(IS_OBEX(pAdvOBInit->OptionType));\r
+\r
+#if defined(FLASH_OBR_SPRMOD)\r
+ \r
+ /* Program PCROP option byte*/\r
+ if ((pAdvOBInit->OptionType & OPTIONBYTE_PCROP) == OPTIONBYTE_PCROP)\r
+ {\r
+ /* Check the parameters */\r
+ assert_param(IS_PCROPSTATE(pAdvOBInit->PCROPState));\r
+ if (pAdvOBInit->PCROPState == OB_PCROP_STATE_ENABLE)\r
+ {\r
+ /*Enable of Write protection on the selected Sector*/\r
+ status = FLASH_OB_PCROPConfig(pAdvOBInit, ENABLE);\r
+ if (status != HAL_OK)\r
+ {\r
+ return status;\r
+ }\r
+ }\r
+ else\r
+ {\r
+ /* Disable of Write protection on the selected Sector*/ \r
+ status = FLASH_OB_PCROPConfig(pAdvOBInit, DISABLE);\r
+ if (status != HAL_OK)\r
+ {\r
+ return status;\r
+ }\r
+ }\r
+ }\r
+ \r
+#endif /* FLASH_OBR_SPRMOD */\r
+\r
+#if defined(FLASH_OBR_nRST_BFB2)\r
+ \r
+ /* Program BOOT config option byte */\r
+ if ((pAdvOBInit->OptionType & OPTIONBYTE_BOOTCONFIG) == OPTIONBYTE_BOOTCONFIG)\r
+ {\r
+ status = FLASH_OB_BootConfig(pAdvOBInit->BootConfig);\r
+ }\r
+ \r
+#endif /* FLASH_OBR_nRST_BFB2 */\r
+\r
+ return status;\r
+}\r
+\r
+/**\r
+ * @brief Get the OBEX byte configuration\r
+ * @note This function can be used only for Cat2 & Cat3 devices for PCROP and Cat4 & Cat5 for BFB2.\r
+ * @param pAdvOBInit pointer to an FLASH_AdvOBProgramInitTypeDef structure that\r
+ * contains the configuration information for the programming.\r
+ * \r
+ * @retval None\r
+ */\r
+void HAL_FLASHEx_AdvOBGetConfig(FLASH_AdvOBProgramInitTypeDef *pAdvOBInit)\r
+{\r
+ pAdvOBInit->OptionType = 0U;\r
+ \r
+#if defined(FLASH_OBR_SPRMOD)\r
+ \r
+ pAdvOBInit->OptionType |= OPTIONBYTE_PCROP;\r
+\r
+ /*Get PCROP state */\r
+ pAdvOBInit->PCROPState = (FLASH->OBR & FLASH_OBR_SPRMOD) >> POSITION_VAL(FLASH_OBR_SPRMOD);\r
+ \r
+ /*Get PCROP protected sector from 0 to 31 */\r
+ pAdvOBInit->PCROPSector0To31 = FLASH->WRPR1;\r
+ \r
+#if defined(STM32L100xC) || defined(STM32L151xC) || defined(STM32L152xC) || defined(STM32L162xC)\r
+\r
+ /*Get PCROP protected sector from 32 to 63 */\r
+ pAdvOBInit->PCROPSector32To63 = FLASH->WRPR2;\r
+\r
+#endif /* STM32L100xC || STM32L151xC || STM32L152xC || STM32L162xC */\r
+#endif /* FLASH_OBR_SPRMOD */\r
+\r
+#if defined(FLASH_OBR_nRST_BFB2)\r
+ \r
+ pAdvOBInit->OptionType |= OPTIONBYTE_BOOTCONFIG;\r
+\r
+ /* Get Boot config OB */\r
+ pAdvOBInit->BootConfig = (FLASH->OBR & FLASH_OBR_nRST_BFB2) >> 16U;\r
+\r
+#endif /* FLASH_OBR_nRST_BFB2 */\r
+}\r
+\r
+#endif /* FLASH_OBR_SPRMOD || FLASH_OBR_nRST_BFB2 */\r
+\r
+#if defined(FLASH_OBR_SPRMOD)\r
+\r
+/**\r
+ * @brief Select the Protection Mode (SPRMOD).\r
+ * @note This function can be used only for STM32L151xBA, STM32L152xBA, STM32L151xC, STM32L152xC & STM32L162xC devices\r
+ * @note Once SPRMOD bit is active, unprotection of a protected sector is not possible \r
+ * @note Read a protected sector will set RDERR Flag and write a protected sector will set WRPERR Flag\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_FLASHEx_OB_SelectPCROP(void)\r
+{\r
+ HAL_StatusTypeDef status = HAL_OK;\r
+ uint16_t tmp1 = 0U;\r
+ uint32_t tmp2 = 0U;\r
+ uint8_t optiontmp = 0U;\r
+ uint16_t optiontmp2 = 0U;\r
+ \r
+ status = FLASH_WaitForLastOperation(FLASH_TIMEOUT_VALUE);\r
+ \r
+ /* Mask RDP Byte */\r
+ optiontmp = (uint8_t)(*(__IO uint8_t *)(OB_BASE)); \r
+ \r
+ /* Update Option Byte */\r
+ optiontmp2 = (uint16_t)(OB_PCROP_SELECTED | optiontmp); \r
+ \r
+ /* calculate the option byte to write */\r
+ tmp1 = (uint16_t)(~(optiontmp2 ));\r
+ tmp2 = (uint32_t)(((uint32_t)((uint32_t)(tmp1) << 16U)) | ((uint32_t)optiontmp2));\r
+ \r
+ if(status == HAL_OK)\r
+ { \r
+ /* Clean the error context */\r
+ pFlash.ErrorCode = HAL_FLASH_ERROR_NONE;\r
+\r
+ /* program PCRop */\r
+ OB->RDP = tmp2;\r
+ \r
+ /* Wait for last operation to be completed */\r
+ status = FLASH_WaitForLastOperation(FLASH_TIMEOUT_VALUE);\r
+ }\r
+ \r
+ /* Return the Read protection operation Status */\r
+ return status; \r
+}\r
+\r
+/**\r
+ * @brief Deselect the Protection Mode (SPRMOD).\r
+ * @note This function can be used only for STM32L151xBA, STM32L152xBA, STM32L151xC, STM32L152xC & STM32L162xC devices\r
+ * @note Once SPRMOD bit is active, unprotection of a protected sector is not possible \r
+ * @note Read a protected sector will set RDERR Flag and write a protected sector will set WRPERR Flag\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_FLASHEx_OB_DeSelectPCROP(void)\r
+{\r
+ HAL_StatusTypeDef status = HAL_OK;\r
+ uint16_t tmp1 = 0U;\r
+ uint32_t tmp2 = 0U;\r
+ uint8_t optiontmp = 0U;\r
+ uint16_t optiontmp2 = 0U;\r
+ \r
+ status = FLASH_WaitForLastOperation(FLASH_TIMEOUT_VALUE);\r
+ \r
+ /* Mask RDP Byte */\r
+ optiontmp = (uint8_t)(*(__IO uint8_t *)(OB_BASE)); \r
+ \r
+ /* Update Option Byte */\r
+ optiontmp2 = (uint16_t)(OB_PCROP_DESELECTED | optiontmp); \r
+ \r
+ /* calculate the option byte to write */\r
+ tmp1 = (uint16_t)(~(optiontmp2 ));\r
+ tmp2 = (uint32_t)(((uint32_t)((uint32_t)(tmp1) << 16U)) | ((uint32_t)optiontmp2));\r
+ \r
+ if(status == HAL_OK)\r
+ { \r
+ /* Clean the error context */\r
+ pFlash.ErrorCode = HAL_FLASH_ERROR_NONE;\r
+\r
+ /* program PCRop */\r
+ OB->RDP = tmp2;\r
+ \r
+ /* Wait for last operation to be completed */\r
+ status = FLASH_WaitForLastOperation(FLASH_TIMEOUT_VALUE);\r
+ }\r
+ \r
+ /* Return the Read protection operation Status */\r
+ return status; \r
+}\r
+\r
+#endif /* FLASH_OBR_SPRMOD */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup FLASHEx_Exported_Functions_Group3 DATA EEPROM Programming functions\r
+ * @brief DATA EEPROM Programming functions\r
+ *\r
+@verbatim \r
+ ===============================================================================\r
+ ##### DATA EEPROM Programming functions ##### \r
+ =============================================================================== \r
+ \r
+ [..] Any operation of erase or program should follow these steps:\r
+ (#) Call the @ref HAL_FLASHEx_DATAEEPROM_Unlock() function to enable the data EEPROM access\r
+ and Flash program erase control register access.\r
+ (#) Call the desired function to erase or program data.\r
+ (#) Call the @ref HAL_FLASHEx_DATAEEPROM_Lock() to disable the data EEPROM access\r
+ and Flash program erase control register access(recommended\r
+ to protect the DATA_EEPROM against possible unwanted operation).\r
+\r
+@endverbatim\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @brief Unlocks the data memory and FLASH_PECR register access.\r
+ * @retval HAL_StatusTypeDef HAL Status\r
+ */\r
+HAL_StatusTypeDef HAL_FLASHEx_DATAEEPROM_Unlock(void)\r
+{\r
+ if((FLASH->PECR & FLASH_PECR_PELOCK) != RESET)\r
+ { \r
+ /* Unlocking the Data memory and FLASH_PECR register access*/\r
+ FLASH->PEKEYR = FLASH_PEKEY1;\r
+ FLASH->PEKEYR = FLASH_PEKEY2;\r
+ }\r
+ else\r
+ {\r
+ return HAL_ERROR;\r
+ }\r
+ return HAL_OK; \r
+}\r
+\r
+/**\r
+ * @brief Locks the Data memory and FLASH_PECR register access.\r
+ * @retval HAL_StatusTypeDef HAL Status\r
+ */\r
+HAL_StatusTypeDef HAL_FLASHEx_DATAEEPROM_Lock(void)\r
+{\r
+ /* Set the PELOCK Bit to lock the data memory and FLASH_PECR register access */\r
+ SET_BIT(FLASH->PECR, FLASH_PECR_PELOCK);\r
+ \r
+ return HAL_OK;\r
+}\r
+\r
+/**\r
+ * @brief Erase a word in data memory.\r
+ * @param Address specifies the address to be erased.\r
+ * @param TypeErase Indicate the way to erase at a specified address.\r
+ * This parameter can be a value of @ref FLASH_Type_Program\r
+ * @note To correctly run this function, the @ref HAL_FLASHEx_DATAEEPROM_Unlock() function\r
+ * must be called before.\r
+ * Call the @ref HAL_FLASHEx_DATAEEPROM_Lock() to the data EEPROM access\r
+ * and Flash program erase control register access(recommended to protect \r
+ * the DATA_EEPROM against possible unwanted operation).\r
+ * @retval HAL_StatusTypeDef HAL Status\r
+ */\r
+HAL_StatusTypeDef HAL_FLASHEx_DATAEEPROM_Erase(uint32_t TypeErase, uint32_t Address)\r
+{\r
+ HAL_StatusTypeDef status = HAL_OK;\r
+ \r
+ /* Check the parameters */\r
+ assert_param(IS_TYPEPROGRAMDATA(TypeErase));\r
+ assert_param(IS_FLASH_DATA_ADDRESS(Address));\r
+ \r
+ /* Wait for last operation to be completed */\r
+ status = FLASH_WaitForLastOperation(FLASH_TIMEOUT_VALUE);\r
+ \r
+ if(status == HAL_OK)\r
+ {\r
+ /* Clean the error context */\r
+ pFlash.ErrorCode = HAL_FLASH_ERROR_NONE;\r
+\r
+ if(TypeErase == FLASH_TYPEERASEDATA_WORD)\r
+ {\r
+ /* Write 00000000h to valid address in the data memory */\r
+ *(__IO uint32_t *) Address = 0x00000000U;\r
+ }\r
+\r
+ if(TypeErase == FLASH_TYPEERASEDATA_HALFWORD)\r
+ {\r
+ /* Write 0000h to valid address in the data memory */\r
+ *(__IO uint16_t *) Address = (uint16_t)0x0000;\r
+ }\r
+\r
+ if(TypeErase == FLASH_TYPEERASEDATA_BYTE)\r
+ {\r
+ /* Write 00h to valid address in the data memory */\r
+ *(__IO uint8_t *) Address = (uint8_t)0x00;\r
+ }\r
+\r
+ status = FLASH_WaitForLastOperation(FLASH_TIMEOUT_VALUE);\r
+ }\r
+ \r
+ /* Return the erase status */\r
+ return status;\r
+} \r
+\r
+/**\r
+ * @brief Program word at a specified address\r
+ * @note To correctly run this function, the @ref HAL_FLASHEx_DATAEEPROM_Unlock() function\r
+ * must be called before.\r
+ * Call the @ref HAL_FLASHEx_DATAEEPROM_Unlock() to he data EEPROM access\r
+ * and Flash program erase control register access(recommended to protect \r
+ * the DATA_EEPROM against possible unwanted operation).\r
+ * @note The function @ref HAL_FLASHEx_DATAEEPROM_EnableFixedTimeProgram() can be called before \r
+ * this function to configure the Fixed Time Programming.\r
+ * @param TypeProgram Indicate the way to program at a specified address.\r
+ * This parameter can be a value of @ref FLASHEx_Type_Program_Data\r
+ * @param Address specifie the address to be programmed.\r
+ * @param Data specifie the data to be programmed\r
+ * \r
+ * @retval HAL_StatusTypeDef HAL Status\r
+ */\r
+\r
+HAL_StatusTypeDef HAL_FLASHEx_DATAEEPROM_Program(uint32_t TypeProgram, uint32_t Address, uint32_t Data)\r
+{\r
+ HAL_StatusTypeDef status = HAL_ERROR;\r
+ \r
+ /* Process Locked */\r
+ __HAL_LOCK(&pFlash);\r
+\r
+ /* Check the parameters */\r
+ assert_param(IS_TYPEPROGRAMDATA(TypeProgram));\r
+\r
+ /* Wait for last operation to be completed */\r
+ status = FLASH_WaitForLastOperation(FLASH_TIMEOUT_VALUE);\r
+ \r
+ if(status == HAL_OK)\r
+ {\r
+ /* Clean the error context */\r
+ pFlash.ErrorCode = HAL_FLASH_ERROR_NONE;\r
+\r
+ if(TypeProgram == FLASH_TYPEPROGRAMDATA_WORD)\r
+ {\r
+ /* Program word (32-bit) at a specified address.*/\r
+ status = FLASH_DATAEEPROM_ProgramWord(Address, (uint32_t) Data);\r
+ }\r
+ else if(TypeProgram == FLASH_TYPEPROGRAMDATA_HALFWORD)\r
+ {\r
+ /* Program halfword (16-bit) at a specified address.*/\r
+ status = FLASH_DATAEEPROM_ProgramHalfWord(Address, (uint16_t) Data);\r
+ }\r
+ else if(TypeProgram == FLASH_TYPEPROGRAMDATA_BYTE)\r
+ {\r
+ /* Program byte (8-bit) at a specified address.*/\r
+ status = FLASH_DATAEEPROM_ProgramByte(Address, (uint8_t) Data);\r
+ }\r
+ else if(TypeProgram == FLASH_TYPEPROGRAMDATA_FASTBYTE)\r
+ {\r
+ /*Program word (8-bit) at a specified address.*/\r
+ status = FLASH_DATAEEPROM_FastProgramByte(Address, (uint8_t) Data);\r
+ }\r
+ else if(TypeProgram == FLASH_TYPEPROGRAMDATA_FASTHALFWORD)\r
+ {\r
+ /* Program halfword (16-bit) at a specified address.*/\r
+ status = FLASH_DATAEEPROM_FastProgramHalfWord(Address, (uint16_t) Data);\r
+ } \r
+ else if(TypeProgram == FLASH_TYPEPROGRAMDATA_FASTWORD)\r
+ {\r
+ /* Program word (32-bit) at a specified address.*/\r
+ status = FLASH_DATAEEPROM_FastProgramWord(Address, (uint32_t) Data);\r
+ }\r
+ else\r
+ {\r
+ status = HAL_ERROR;\r
+ }\r
+\r
+ }\r
+\r
+ /* Process Unlocked */\r
+ __HAL_UNLOCK(&pFlash);\r
+\r
+ return status;\r
+}\r
+\r
+/**\r
+ * @brief Enable DATA EEPROM fixed Time programming (2*Tprog).\r
+ * @retval None\r
+ */\r
+void HAL_FLASHEx_DATAEEPROM_EnableFixedTimeProgram(void)\r
+{\r
+ SET_BIT(FLASH->PECR, FLASH_PECR_FTDW);\r
+}\r
+\r
+/**\r
+ * @brief Disables DATA EEPROM fixed Time programming (2*Tprog).\r
+ * @retval None\r
+ */\r
+void HAL_FLASHEx_DATAEEPROM_DisableFixedTimeProgram(void)\r
+{\r
+ CLEAR_BIT(FLASH->PECR, FLASH_PECR_FTDW);\r
+}\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @addtogroup FLASHEx_Private_Functions\r
+ * @{\r
+ */\r
+\r
+/*\r
+==============================================================================\r
+ OPTIONS BYTES\r
+==============================================================================\r
+*/\r
+/**\r
+ * @brief Enables or disables the read out protection.\r
+ * @note To correctly run this function, the @ref HAL_FLASH_OB_Unlock() function\r
+ * must be called before.\r
+ * @param OB_RDP specifies the read protection level. \r
+ * This parameter can be:\r
+ * @arg @ref OB_RDP_LEVEL_0 No protection\r
+ * @arg @ref OB_RDP_LEVEL_1 Read protection of the memory\r
+ * @arg @ref OB_RDP_LEVEL_2 Chip protection\r
+ * \r
+ * !!!Warning!!! When enabling OB_RDP_LEVEL_2 it's no more possible to go back to level 1 or 0\r
+ * \r
+ * @retval HAL status\r
+ */\r
+static HAL_StatusTypeDef FLASH_OB_RDPConfig(uint8_t OB_RDP)\r
+{\r
+ HAL_StatusTypeDef status = HAL_OK;\r
+ uint32_t tmp1 = 0U, tmp2 = 0U, tmp3 = 0U;\r
+ \r
+ /* Check the parameters */\r
+ assert_param(IS_OB_RDP(OB_RDP));\r
+ \r
+ tmp1 = (uint32_t)(OB->RDP & FLASH_OBR_RDPRT);\r
+ \r
+ /* According to errata sheet, DocID022054 Rev 5, par2.1.5\r
+ Before setting Level0 in the RDP register, check that the current level is not equal to Level0.\r
+ If the current level is not equal to Level0, Level0 can be activated.\r
+ If the current level is Level0 then the RDP register must not be written again with Level0. */\r
+ \r
+ if ((tmp1 == OB_RDP_LEVEL_0) && (OB_RDP == OB_RDP_LEVEL_0))\r
+ {\r
+ /*current level is Level0 then the RDP register must not be written again with Level0. */\r
+ status = HAL_ERROR;\r
+ }\r
+ else \r
+ {\r
+#if defined(FLASH_OBR_SPRMOD)\r
+ /* Mask SPRMOD bit */\r
+ tmp3 = (uint32_t)(OB->RDP & FLASH_OBR_SPRMOD);\r
+#endif\r
+\r
+ /* calculate the option byte to write */\r
+ tmp1 = (~((uint32_t)(OB_RDP | tmp3)));\r
+ tmp2 = (uint32_t)(((uint32_t)((uint32_t)(tmp1) << 16U)) | ((uint32_t)(OB_RDP | tmp3)));\r
+\r
+ /* Wait for last operation to be completed */\r
+ status = FLASH_WaitForLastOperation(FLASH_TIMEOUT_VALUE);\r
+\r
+ if(status == HAL_OK)\r
+ {\r
+ /* Clean the error context */\r
+ pFlash.ErrorCode = HAL_FLASH_ERROR_NONE;\r
+\r
+ /* program read protection level */\r
+ OB->RDP = tmp2;\r
+\r
+ /* Wait for last operation to be completed */\r
+ status = FLASH_WaitForLastOperation(FLASH_TIMEOUT_VALUE);\r
+ }\r
+ }\r
+\r
+ /* Return the Read protection operation Status */\r
+ return status;\r
+}\r
+\r
+/**\r
+ * @brief Programs the FLASH brownout reset threshold level Option Byte.\r
+ * @param OB_BOR Selects the brownout reset threshold level.\r
+ * This parameter can be one of the following values:\r
+ * @arg @ref OB_BOR_OFF BOR is disabled at power down, the reset is asserted when the VDD \r
+ * power supply reaches the PDR(Power Down Reset) threshold (1.5V)\r
+ * @arg @ref OB_BOR_LEVEL1 BOR Reset threshold levels for 1.7V - 1.8V VDD power supply\r
+ * @arg @ref OB_BOR_LEVEL2 BOR Reset threshold levels for 1.9V - 2.0V VDD power supply\r
+ * @arg @ref OB_BOR_LEVEL3 BOR Reset threshold levels for 2.3V - 2.4V VDD power supply\r
+ * @arg @ref OB_BOR_LEVEL4 BOR Reset threshold levels for 2.55V - 2.65V VDD power supply\r
+ * @arg @ref OB_BOR_LEVEL5 BOR Reset threshold levels for 2.8V - 2.9V VDD power supply\r
+ * @retval HAL status\r
+ */\r
+static HAL_StatusTypeDef FLASH_OB_BORConfig(uint8_t OB_BOR)\r
+{\r
+ HAL_StatusTypeDef status = HAL_OK;\r
+ uint32_t tmp = 0U, tmp1 = 0U;\r
+\r
+ /* Check the parameters */\r
+ assert_param(IS_OB_BOR_LEVEL(OB_BOR));\r
+\r
+ /* Get the User Option byte register */\r
+ tmp1 = OB->USER & ((~FLASH_OBR_BOR_LEV) >> 16U);\r
+\r
+ /* Calculate the option byte to write - [0xFFU | nUSER | 0x00U | USER]*/\r
+ tmp = (uint32_t)~((OB_BOR | tmp1)) << 16U;\r
+ tmp |= (OB_BOR | tmp1);\r
+ \r
+ /* Wait for last operation to be completed */\r
+ status = FLASH_WaitForLastOperation(FLASH_TIMEOUT_VALUE);\r
+ \r
+ if(status == HAL_OK)\r
+ { \r
+ /* Clean the error context */\r
+ pFlash.ErrorCode = HAL_FLASH_ERROR_NONE;\r
+\r
+ /* Write the BOR Option Byte */ \r
+ OB->USER = tmp;\r
+\r
+ /* Wait for last operation to be completed */\r
+ status = FLASH_WaitForLastOperation(FLASH_TIMEOUT_VALUE);\r
+ }\r
+ \r
+ /* Return the Option Byte BOR Programming Status */\r
+ return status;\r
+}\r
+\r
+/**\r
+ * @brief Returns the FLASH User Option Bytes values.\r
+ * @retval The FLASH User Option Bytes.\r
+ */\r
+static uint8_t FLASH_OB_GetUser(void)\r
+{\r
+ /* Return the User Option Byte */\r
+ return (uint8_t)((FLASH->OBR & (FLASH_OBR_IWDG_SW | FLASH_OBR_nRST_STOP | FLASH_OBR_nRST_STDBY)) >> 16U);\r
+}\r
+\r
+/**\r
+ * @brief Returns the FLASH Read Protection level.\r
+ * @retval FLASH RDP level\r
+ * This parameter can be one of the following values:\r
+ * @arg @ref OB_RDP_LEVEL_0 No protection\r
+ * @arg @ref OB_RDP_LEVEL_1 Read protection of the memory\r
+ * @arg @ref OB_RDP_LEVEL_2 Full chip protection\r
+ */\r
+static uint8_t FLASH_OB_GetRDP(void)\r
+{\r
+ uint8_t rdp_level = (uint8_t)(FLASH->OBR & FLASH_OBR_RDPRT);\r
+\r
+ if ((rdp_level != OB_RDP_LEVEL_0) && (rdp_level != OB_RDP_LEVEL_2))\r
+ {\r
+ return (OB_RDP_LEVEL_1);\r
+ }\r
+ else\r
+ {\r
+ return (rdp_level);\r
+ }\r
+}\r
+\r
+/**\r
+ * @brief Returns the FLASH BOR level.\r
+ * @retval The BOR level Option Bytes.\r
+ */\r
+static uint8_t FLASH_OB_GetBOR(void)\r
+{\r
+ /* Return the BOR level */\r
+ return (uint8_t)((FLASH->OBR & (uint32_t)FLASH_OBR_BOR_LEV) >> 16U);\r
+}\r
+\r
+/**\r
+ * @brief Write protects the desired pages of the first 64KB of the Flash.\r
+ * @param pOBInit pointer to an FLASH_OBInitStruct structure that\r
+ * contains WRP parameters.\r
+ * @param NewState new state of the specified FLASH Pages Wtite protection.\r
+ * This parameter can be: ENABLE or DISABLE.\r
+ * @retval HAL_StatusTypeDef\r
+ */\r
+static HAL_StatusTypeDef FLASH_OB_WRPConfig(FLASH_OBProgramInitTypeDef *pOBInit, FunctionalState NewState)\r
+{\r
+ HAL_StatusTypeDef status = HAL_OK;\r
+ \r
+ /* Wait for last operation to be completed */\r
+ status = FLASH_WaitForLastOperation(FLASH_TIMEOUT_VALUE);\r
+ \r
+ if(status == HAL_OK)\r
+ {\r
+ /* Clean the error context */\r
+ pFlash.ErrorCode = HAL_FLASH_ERROR_NONE;\r
+\r
+ /* WRP for sector between 0 to 31 */\r
+ if (pOBInit->WRPSector0To31 != 0U)\r
+ {\r
+ FLASH_OB_WRPConfigWRP1OrPCROP1(pOBInit->WRPSector0To31, NewState);\r
+ }\r
+ \r
+#if defined(STM32L100xC) || defined(STM32L151xC) || defined(STM32L152xC) || defined(STM32L162xC) \\r
+ || defined(STM32L151xCA) || defined(STM32L151xD) || defined(STM32L151xDX) || defined(STM32L152xCA) \\r
+ || defined(STM32L152xD) || defined(STM32L152xDX) || defined(STM32L162xCA) || defined(STM32L162xD) \\r
+ || defined(STM32L162xDX) || defined(STM32L151xE) || defined(STM32L152xE) || defined(STM32L162xE)\r
+ \r
+ /* Pages for Cat3, Cat4 & Cat5 devices*/\r
+ /* WRP for sector between 32 to 63 */\r
+ if (pOBInit->WRPSector32To63 != 0U)\r
+ {\r
+ FLASH_OB_WRPConfigWRP2OrPCROP2(pOBInit->WRPSector32To63, NewState);\r
+ }\r
+ \r
+#endif /* STM32L100xC || STM32L151xC || STM32L152xC || (...) || STM32L151xE || STM32L152xE || STM32L162xE */\r
+\r
+#if defined(STM32L151xD) || defined(STM32L151xDX) || defined(STM32L152xD) || defined(STM32L152xDX) \\r
+ || defined(STM32L162xD) || defined(STM32L162xDX) || defined(STM32L151xE) || defined(STM32L152xE) \\r
+ || defined(STM32L162xE)\r
+ \r
+ /* Pages for devices with FLASH >= 256KB*/\r
+ /* WRP for sector between 64 to 95 */\r
+ if (pOBInit->WRPSector64To95 != 0U)\r
+ {\r
+ FLASH_OB_WRPConfigWRP3(pOBInit->WRPSector64To95, NewState);\r
+ }\r
+ \r
+#endif /* STM32L151xD || STM32L152xD || STM32L162xD || STM32L151xE || STM32L152xE || STM32L162xE */\r
+\r
+#if defined(STM32L151xE) || defined(STM32L152xE) || defined(STM32L162xE) || defined(STM32L151xDX) \\r
+ || defined(STM32L152xDX) || defined(STM32L162xDX)\r
+\r
+ /* Pages for Cat5 devices*/\r
+ /* WRP for sector between 96 to 127 */\r
+ if (pOBInit->WRPSector96To127 != 0U)\r
+ {\r
+ FLASH_OB_WRPConfigWRP4(pOBInit->WRPSector96To127, NewState);\r
+ }\r
+ \r
+#endif /* STM32L151xE || STM32L152xE || STM32L162xE || STM32L151xDX || ... */\r
+\r
+ /* Wait for last operation to be completed */\r
+ status = FLASH_WaitForLastOperation(FLASH_TIMEOUT_VALUE);\r
+ }\r
+\r
+ /* Return the write protection operation Status */\r
+ return status; \r
+}\r
+\r
+#if defined(STM32L151xBA) || defined(STM32L152xBA) || defined(STM32L151xC) || defined(STM32L152xC) \\r
+ || defined(STM32L162xC)\r
+/**\r
+ * @brief Enables the read/write protection (PCROP) of the desired \r
+ * sectors.\r
+ * @note This function can be used only for Cat2 & Cat3 devices\r
+ * @param pAdvOBInit pointer to an FLASH_AdvOBProgramInitTypeDef structure that\r
+ * contains PCROP parameters.\r
+ * @param NewState new state of the specified FLASH Pages read/Write protection.\r
+ * This parameter can be: ENABLE or DISABLE.\r
+ * @retval HAL status\r
+ */\r
+static HAL_StatusTypeDef FLASH_OB_PCROPConfig(FLASH_AdvOBProgramInitTypeDef *pAdvOBInit, FunctionalState NewState)\r
+{\r
+ HAL_StatusTypeDef status = HAL_OK;\r
+ FunctionalState pcropstate = DISABLE;\r
+ \r
+ /* Wait for last operation to be completed */\r
+ status = FLASH_WaitForLastOperation(FLASH_TIMEOUT_VALUE);\r
+ \r
+ /* Invert state to use same function of WRP */\r
+ if (NewState == DISABLE)\r
+ {\r
+ pcropstate = ENABLE;\r
+ }\r
+ \r
+ if(status == HAL_OK)\r
+ {\r
+ /* Clean the error context */\r
+ pFlash.ErrorCode = HAL_FLASH_ERROR_NONE;\r
+\r
+ /* Pages for Cat2 devices*/\r
+ /* PCROP for sector between 0 to 31 */\r
+ if (pAdvOBInit->PCROPSector0To31 != 0U)\r
+ {\r
+ FLASH_OB_WRPConfigWRP1OrPCROP1(pAdvOBInit->PCROPSector0To31, pcropstate);\r
+ }\r
+ \r
+#if defined(STM32L100xC) || defined(STM32L151xC) || defined(STM32L152xC) || defined(STM32L162xC)\r
+\r
+ /* Pages for Cat3 devices*/\r
+ /* WRP for sector between 32 to 63 */\r
+ if (pAdvOBInit->PCROPSector32To63 != 0U)\r
+ {\r
+ FLASH_OB_WRPConfigWRP2OrPCROP2(pAdvOBInit->PCROPSector32To63, pcropstate);\r
+ }\r
+ \r
+#endif /* STM32L100xC || STM32L151xC || STM32L152xC || STM32L162xC */\r
+ \r
+ /* Wait for last operation to be completed */\r
+ status = FLASH_WaitForLastOperation(FLASH_TIMEOUT_VALUE);\r
+ }\r
+\r
+ /* Return the write protection operation Status */\r
+ return status; \r
+}\r
+#endif /* STM32L151xBA || STM32L152xBA || STM32L151xC || STM32L152xC || STM32L162xC */\r
+\r
+/**\r
+ * @brief Write protects the desired pages of the first 128KB of the Flash.\r
+ * @param WRP1OrPCROP1 specifies the address of the pages to be write protected.\r
+ * This parameter can be a combination of @ref FLASHEx_Option_Bytes_Write_Protection1\r
+ * @param NewState new state of the specified FLASH Pages Write protection.\r
+ * This parameter can be: ENABLE or DISABLE.\r
+ * @retval None\r
+ */\r
+static void FLASH_OB_WRPConfigWRP1OrPCROP1(uint32_t WRP1OrPCROP1, FunctionalState NewState)\r
+{\r
+ uint32_t wrp01data = 0U, wrp23data = 0U;\r
+ \r
+ uint32_t tmp1 = 0U, tmp2 = 0U;\r
+ \r
+ /* Check the parameters */\r
+ assert_param(IS_OB_WRP(WRP1OrPCROP1));\r
+ assert_param(IS_FUNCTIONAL_STATE(NewState));\r
+\r
+ if (NewState != DISABLE)\r
+ {\r
+ wrp01data = (uint16_t)(((WRP1OrPCROP1 & WRP_MASK_LOW) | OB->WRP01));\r
+ wrp23data = (uint16_t)((((WRP1OrPCROP1 & WRP_MASK_HIGH)>>16U | OB->WRP23))); \r
+ tmp1 = (uint32_t)(~(wrp01data) << 16U)|(wrp01data);\r
+ OB->WRP01 = tmp1;\r
+\r
+ tmp2 = (uint32_t)(~(wrp23data) << 16U)|(wrp23data);\r
+ OB->WRP23 = tmp2; \r
+ }\r
+ else\r
+ {\r
+ wrp01data = (uint16_t)(~WRP1OrPCROP1 & (WRP_MASK_LOW & OB->WRP01));\r
+ wrp23data = (uint16_t)((((~WRP1OrPCROP1 & WRP_MASK_HIGH)>>16U & OB->WRP23))); \r
+\r
+ tmp1 = (uint32_t)((~wrp01data) << 16U)|(wrp01data);\r
+ OB->WRP01 = tmp1;\r
+ \r
+ tmp2 = (uint32_t)((~wrp23data) << 16U)|(wrp23data);\r
+ OB->WRP23 = tmp2;\r
+ }\r
+}\r
+\r
+#if defined(STM32L100xC) || defined(STM32L151xC) || defined(STM32L152xC) || defined(STM32L162xC) \\r
+ || defined(STM32L151xCA) || defined(STM32L151xD) || defined(STM32L151xDX) || defined(STM32L152xCA) \\r
+ || defined(STM32L152xD) || defined(STM32L152xDX) || defined(STM32L162xCA) || defined(STM32L162xD) \\r
+ || defined(STM32L162xDX) || defined(STM32L151xE) || defined(STM32L152xE) || defined(STM32L162xE)\r
+/**\r
+ * @brief Enable Write protects the desired pages of the second 128KB of the Flash.\r
+ * @note This function can be used only for Cat3, Cat4 & Cat5 devices.\r
+ * @param WRP2OrPCROP2 specifies the address of the pages to be write protected.\r
+ * This parameter can be a combination of @ref FLASHEx_Option_Bytes_Write_Protection2\r
+ * @param NewState new state of the specified FLASH Pages Wtite protection.\r
+ * This parameter can be: ENABLE or DISABLE.\r
+ * @retval None\r
+ */\r
+static void FLASH_OB_WRPConfigWRP2OrPCROP2(uint32_t WRP2OrPCROP2, FunctionalState NewState)\r
+{\r
+ uint32_t wrp45data = 0U, wrp67data = 0U;\r
+ \r
+ uint32_t tmp1 = 0U, tmp2 = 0U;\r
+ \r
+ /* Check the parameters */\r
+ assert_param(IS_OB_WRP(WRP2OrPCROP2));\r
+ assert_param(IS_FUNCTIONAL_STATE(NewState));\r
+\r
+ if (NewState != DISABLE)\r
+ {\r
+ wrp45data = (uint16_t)(((WRP2OrPCROP2 & WRP_MASK_LOW) | OB->WRP45));\r
+ wrp67data = (uint16_t)((((WRP2OrPCROP2 & WRP_MASK_HIGH)>>16U | OB->WRP67))); \r
+ tmp1 = (uint32_t)(~(wrp45data) << 16U)|(wrp45data);\r
+ OB->WRP45 = tmp1;\r
+ \r
+ tmp2 = (uint32_t)(~(wrp67data) << 16U)|(wrp67data);\r
+ OB->WRP67 = tmp2;\r
+ }\r
+ else\r
+ {\r
+ wrp45data = (uint16_t)(~WRP2OrPCROP2 & (WRP_MASK_LOW & OB->WRP45));\r
+ wrp67data = (uint16_t)((((~WRP2OrPCROP2 & WRP_MASK_HIGH)>>16U & OB->WRP67))); \r
+ \r
+ tmp1 = (uint32_t)((~wrp45data) << 16U)|(wrp45data);\r
+ OB->WRP45 = tmp1;\r
+ \r
+ tmp2 = (uint32_t)((~wrp67data) << 16U)|(wrp67data);\r
+ OB->WRP67 = tmp2;\r
+ }\r
+}\r
+#endif /* STM32L100xC || STM32L151xC || STM32L152xC || (...) || STM32L151xE || STM32L152xE || STM32L162xE */\r
+\r
+#if defined(STM32L151xD) || defined(STM32L151xDX) || defined(STM32L152xD) || defined(STM32L152xDX) \\r
+ || defined(STM32L162xD) || defined(STM32L162xDX) || defined(STM32L151xE) || defined(STM32L152xE) \\r
+ || defined(STM32L162xE)\r
+/**\r
+ * @brief Enable Write protects the desired pages of the third 128KB of the Flash.\r
+ * @note This function can be used only for STM32L151xD, STM32L152xD, STM32L162xD & Cat5 devices.\r
+ * @param WRP3 specifies the address of the pages to be write protected.\r
+ * This parameter can be a combination of @ref FLASHEx_Option_Bytes_Write_Protection3\r
+ * @param NewState new state of the specified FLASH Pages Wtite protection.\r
+ * This parameter can be: ENABLE or DISABLE.\r
+ * @retval None\r
+ */\r
+static void FLASH_OB_WRPConfigWRP3(uint32_t WRP3, FunctionalState NewState)\r
+{\r
+ uint32_t wrp89data = 0U, wrp1011data = 0U;\r
+ \r
+ uint32_t tmp1 = 0U, tmp2 = 0U;\r
+ \r
+ /* Check the parameters */\r
+ assert_param(IS_OB_WRP(WRP3));\r
+ assert_param(IS_FUNCTIONAL_STATE(NewState));\r
+\r
+ if (NewState != DISABLE)\r
+ {\r
+ wrp89data = (uint16_t)(((WRP3 & WRP_MASK_LOW) | OB->WRP89));\r
+ wrp1011data = (uint16_t)((((WRP3 & WRP_MASK_HIGH)>>16U | OB->WRP1011))); \r
+ tmp1 = (uint32_t)(~(wrp89data) << 16U)|(wrp89data);\r
+ OB->WRP89 = tmp1;\r
+\r
+ tmp2 = (uint32_t)(~(wrp1011data) << 16U)|(wrp1011data);\r
+ OB->WRP1011 = tmp2; \r
+ }\r
+ else\r
+ {\r
+ wrp89data = (uint16_t)(~WRP3 & (WRP_MASK_LOW & OB->WRP89));\r
+ wrp1011data = (uint16_t)((((~WRP3 & WRP_MASK_HIGH)>>16U & OB->WRP1011))); \r
+\r
+ tmp1 = (uint32_t)((~wrp89data) << 16U)|(wrp89data);\r
+ OB->WRP89 = tmp1;\r
+\r
+ tmp2 = (uint32_t)((~wrp1011data) << 16U)|(wrp1011data);\r
+ OB->WRP1011 = tmp2;\r
+ }\r
+}\r
+#endif /* STM32L151xD || STM32L152xD || STM32L162xD || STM32L151xE || STM32L152xE || STM32L162xE */\r
+\r
+#if defined(STM32L151xE) || defined(STM32L152xE) || defined(STM32L162xE) || defined(STM32L151xDX) \\r
+ || defined(STM32L152xDX) || defined(STM32L162xDX)\r
+/**\r
+ * @brief Enable Write protects the desired pages of the Fourth 128KB of the Flash.\r
+ * @note This function can be used only for Cat5 & STM32L1xxDX devices.\r
+ * @param WRP4 specifies the address of the pages to be write protected.\r
+ * This parameter can be a combination of @ref FLASHEx_Option_Bytes_Write_Protection4\r
+ * @param NewState new state of the specified FLASH Pages Wtite protection.\r
+ * This parameter can be: ENABLE or DISABLE.\r
+ * @retval None\r
+ */\r
+static void FLASH_OB_WRPConfigWRP4(uint32_t WRP4, FunctionalState NewState)\r
+{\r
+ uint32_t wrp1213data = 0U, wrp1415data = 0U;\r
+ \r
+ uint32_t tmp1 = 0U, tmp2 = 0U;\r
+ \r
+ /* Check the parameters */\r
+ assert_param(IS_OB_WRP(WRP4));\r
+ assert_param(IS_FUNCTIONAL_STATE(NewState));\r
+\r
+ if (NewState != DISABLE)\r
+ {\r
+ wrp1213data = (uint16_t)(((WRP4 & WRP_MASK_LOW) | OB->WRP1213));\r
+ wrp1415data = (uint16_t)((((WRP4 & WRP_MASK_HIGH)>>16U | OB->WRP1415))); \r
+ tmp1 = (uint32_t)(~(wrp1213data) << 16U)|(wrp1213data);\r
+ OB->WRP1213 = tmp1;\r
+\r
+ tmp2 = (uint32_t)(~(wrp1415data) << 16U)|(wrp1415data);\r
+ OB->WRP1415 = tmp2; \r
+ }\r
+ else\r
+ {\r
+ wrp1213data = (uint16_t)(~WRP4 & (WRP_MASK_LOW & OB->WRP1213));\r
+ wrp1415data = (uint16_t)((((~WRP4 & WRP_MASK_HIGH)>>16U & OB->WRP1415))); \r
+\r
+ tmp1 = (uint32_t)((~wrp1213data) << 16U)|(wrp1213data);\r
+ OB->WRP1213 = tmp1;\r
+\r
+ tmp2 = (uint32_t)((~wrp1415data) << 16U)|(wrp1415data);\r
+ OB->WRP1415 = tmp2;\r
+ }\r
+}\r
+#endif /* STM32L151xE || STM32L152xE || STM32L162xE || STM32L151xDX || ... */\r
+\r
+/**\r
+ * @brief Programs the FLASH User Option Byte: IWDG_SW / RST_STOP / RST_STDBY.\r
+ * @param OB_IWDG Selects the WDG mode.\r
+ * This parameter can be one of the following values:\r
+ * @arg @ref OB_IWDG_SW Software WDG selected\r
+ * @arg @ref OB_IWDG_HW Hardware WDG selected\r
+ * @param OB_STOP Reset event when entering STOP mode.\r
+ * This parameter can be one of the following values:\r
+ * @arg @ref OB_STOP_NORST No reset generated when entering in STOP\r
+ * @arg @ref OB_STOP_RST Reset generated when entering in STOP\r
+ * @param OB_STDBY Reset event when entering Standby mode.\r
+ * This parameter can be one of the following values:\r
+ * @arg @ref OB_STDBY_NORST No reset generated when entering in STANDBY\r
+ * @arg @ref OB_STDBY_RST Reset generated when entering in STANDBY\r
+ * @retval HAL status\r
+ */\r
+static HAL_StatusTypeDef FLASH_OB_UserConfig(uint8_t OB_IWDG, uint8_t OB_STOP, uint8_t OB_STDBY)\r
+{\r
+ HAL_StatusTypeDef status = HAL_OK; \r
+ uint32_t tmp = 0U, tmp1 = 0U;\r
+\r
+ /* Check the parameters */\r
+ assert_param(IS_OB_IWDG_SOURCE(OB_IWDG));\r
+ assert_param(IS_OB_STOP_SOURCE(OB_STOP));\r
+ assert_param(IS_OB_STDBY_SOURCE(OB_STDBY));\r
+\r
+ /* Get the User Option byte register */\r
+ tmp1 = OB->USER & ((~(FLASH_OBR_IWDG_SW | FLASH_OBR_nRST_STOP | FLASH_OBR_nRST_STDBY)) >> 16U);\r
+\r
+ /* Calculate the user option byte to write */ \r
+ tmp = (uint32_t)(((uint32_t)~((uint32_t)((uint32_t)(OB_IWDG) | (uint32_t)(OB_STOP) | (uint32_t)(OB_STDBY) | tmp1))) << 16U);\r
+ tmp |= ((uint32_t)(OB_IWDG) | ((uint32_t)OB_STOP) | (uint32_t)(OB_STDBY) | tmp1);\r
+ \r
+ /* Wait for last operation to be completed */\r
+ status = FLASH_WaitForLastOperation(FLASH_TIMEOUT_VALUE);\r
+ \r
+ if(status == HAL_OK)\r
+ { \r
+ /* Clean the error context */\r
+ pFlash.ErrorCode = HAL_FLASH_ERROR_NONE;\r
+\r
+ /* Write the User Option Byte */\r
+ OB->USER = tmp;\r
+ \r
+ /* Wait for last operation to be completed */\r
+ status = FLASH_WaitForLastOperation(FLASH_TIMEOUT_VALUE);\r
+ }\r
+\r
+ /* Return the Option Byte program Status */\r
+ return status;\r
+}\r
+\r
+#if defined(FLASH_OBR_nRST_BFB2)\r
+/**\r
+ * @brief Configures to boot from Bank1 or Bank2.\r
+ * @param OB_BOOT select the FLASH Bank to boot from.\r
+ * This parameter can be one of the following values:\r
+ * @arg @ref OB_BOOT_BANK2 At startup, if boot pins are set in boot from user Flash\r
+ * position and this parameter is selected the device will boot from Bank2 or Bank1,\r
+ * depending on the activation of the bank. The active banks are checked in\r
+ * the following order: Bank2, followed by Bank1.\r
+ * The active bank is recognized by the value programmed at the base address\r
+ * of the respective bank (corresponding to the initial stack pointer value\r
+ * in the interrupt vector table).\r
+ * @arg @ref OB_BOOT_BANK1 At startup, if boot pins are set in boot from user Flash\r
+ * position and this parameter is selected the device will boot from Bank1(Default).\r
+ * For more information, please refer to AN2606 from www.st.com. \r
+ * @retval HAL status\r
+ */\r
+static HAL_StatusTypeDef FLASH_OB_BootConfig(uint8_t OB_BOOT)\r
+{\r
+ HAL_StatusTypeDef status = HAL_OK; \r
+ uint32_t tmp = 0U, tmp1 = 0U;\r
+\r
+ /* Check the parameters */\r
+ assert_param(IS_OB_BOOT_BANK(OB_BOOT));\r
+\r
+ /* Get the User Option byte register and BOR Level*/\r
+ tmp1 = OB->USER & ((~FLASH_OBR_nRST_BFB2) >> 16U);\r
+\r
+ /* Calculate the option byte to write */\r
+ tmp = (uint32_t)~(OB_BOOT | tmp1) << 16U;\r
+ tmp |= (OB_BOOT | tmp1);\r
+\r
+ /* Wait for last operation to be completed */\r
+ status = FLASH_WaitForLastOperation(FLASH_TIMEOUT_VALUE);\r
+\r
+ if(status == HAL_OK)\r
+ { \r
+ /* Clean the error context */\r
+ pFlash.ErrorCode = HAL_FLASH_ERROR_NONE;\r
+\r
+ /* Write the BOOT Option Byte */\r
+ OB->USER = tmp;\r
+ \r
+ /* Wait for last operation to be completed */\r
+ status = FLASH_WaitForLastOperation(FLASH_TIMEOUT_VALUE);\r
+ }\r
+\r
+ /* Return the Option Byte program Status */\r
+ return status;\r
+}\r
+\r
+#endif /* FLASH_OBR_nRST_BFB2 */\r
+\r
+/*\r
+==============================================================================\r
+ DATA\r
+==============================================================================\r
+*/\r
+\r
+/**\r
+ * @brief Write a Byte at a specified address in data memory.\r
+ * @param Address specifies the address to be written.\r
+ * @param Data specifies the data to be written.\r
+ * @note This function assumes that the is data word is already erased.\r
+ * @retval HAL status\r
+ */\r
+static HAL_StatusTypeDef FLASH_DATAEEPROM_FastProgramByte(uint32_t Address, uint8_t Data)\r
+{\r
+ HAL_StatusTypeDef status = HAL_OK;\r
+#if defined(STM32L100xB) || defined(STM32L151xB) || defined(STM32L152xB)\r
+ uint32_t tmp = 0U, tmpaddr = 0U;\r
+#endif /* STM32L100xB || STM32L151xB || STM32L152xB */\r
+ \r
+ /* Check the parameters */\r
+ assert_param(IS_FLASH_DATA_ADDRESS(Address)); \r
+\r
+ /* Wait for last operation to be completed */\r
+ status = FLASH_WaitForLastOperation(FLASH_TIMEOUT_VALUE);\r
+ \r
+ if(status == HAL_OK)\r
+ {\r
+ /* Clear the FTDW bit */\r
+ CLEAR_BIT(FLASH->PECR, FLASH_PECR_FTDW);\r
+\r
+#if defined(STM32L100xB) || defined(STM32L151xB) || defined(STM32L152xB)\r
+ /* Possible only on Cat1 devices */\r
+ if(Data != (uint8_t)0x00U) \r
+ {\r
+ /* If the previous operation is completed, proceed to write the new Data */\r
+ *(__IO uint8_t *)Address = Data;\r
+ \r
+ /* Wait for last operation to be completed */\r
+ status = FLASH_WaitForLastOperation(FLASH_TIMEOUT_VALUE);\r
+ }\r
+ else\r
+ {\r
+ tmpaddr = Address & 0xFFFFFFFCU;\r
+ tmp = * (__IO uint32_t *) tmpaddr;\r
+ tmpaddr = 0xFFU << ((uint32_t) (0x8U * (Address & 0x3U)));\r
+ tmp &= ~tmpaddr;\r
+ status = HAL_FLASHEx_DATAEEPROM_Erase(FLASH_TYPEERASEDATA_WORD, Address & 0xFFFFFFFCU);\r
+ /* Process Unlocked */\r
+ __HAL_UNLOCK(&pFlash);\r
+ status = HAL_FLASHEx_DATAEEPROM_Program(FLASH_TYPEPROGRAMDATA_FASTWORD, (Address & 0xFFFFFFFCU), tmp);\r
+ /* Process Locked */\r
+ __HAL_LOCK(&pFlash);\r
+ }\r
+#else /*!Cat1*/ \r
+ /* If the previous operation is completed, proceed to write the new Data */\r
+ *(__IO uint8_t *)Address = Data;\r
+ \r
+ /* Wait for last operation to be completed */\r
+ status = FLASH_WaitForLastOperation(FLASH_TIMEOUT_VALUE);\r
+#endif /* STM32L100xB || STM32L151xB || STM32L152xB */\r
+ }\r
+ /* Return the Write Status */\r
+ return status;\r
+}\r
+\r
+/**\r
+ * @brief Writes a half word at a specified address in data memory.\r
+ * @param Address specifies the address to be written.\r
+ * @param Data specifies the data to be written.\r
+ * @note This function assumes that the is data word is already erased.\r
+ * @retval HAL status\r
+ */\r
+static HAL_StatusTypeDef FLASH_DATAEEPROM_FastProgramHalfWord(uint32_t Address, uint16_t Data)\r
+{\r
+ HAL_StatusTypeDef status = HAL_OK;\r
+#if defined(STM32L100xB) || defined(STM32L151xB) || defined(STM32L152xB)\r
+ uint32_t tmp = 0U, tmpaddr = 0U;\r
+#endif /* STM32L100xB || STM32L151xB || STM32L152xB */\r
+ \r
+ /* Check the parameters */\r
+ assert_param(IS_FLASH_DATA_ADDRESS(Address));\r
+\r
+ /* Wait for last operation to be completed */\r
+ status = FLASH_WaitForLastOperation(FLASH_TIMEOUT_VALUE);\r
+ \r
+ if(status == HAL_OK)\r
+ {\r
+ /* Clear the FTDW bit */\r
+ CLEAR_BIT(FLASH->PECR, FLASH_PECR_FTDW);\r
+\r
+#if defined(STM32L100xB) || defined(STM32L151xB) || defined(STM32L152xB)\r
+ /* Possible only on Cat1 devices */\r
+ if(Data != (uint16_t)0x0000U) \r
+ {\r
+ /* If the previous operation is completed, proceed to write the new data */\r
+ *(__IO uint16_t *)Address = Data;\r
+ \r
+ /* Wait for last operation to be completed */\r
+ status = FLASH_WaitForLastOperation(FLASH_TIMEOUT_VALUE);\r
+ }\r
+ else\r
+ {\r
+ /* Process Unlocked */\r
+ __HAL_UNLOCK(&pFlash);\r
+ if((Address & 0x3U) != 0x3U)\r
+ {\r
+ tmpaddr = Address & 0xFFFFFFFCU;\r
+ tmp = * (__IO uint32_t *) tmpaddr;\r
+ tmpaddr = 0xFFFFU << ((uint32_t) (0x8U * (Address & 0x3U)));\r
+ tmp &= ~tmpaddr; \r
+ status = HAL_FLASHEx_DATAEEPROM_Erase(FLASH_TYPEERASEDATA_WORD, Address & 0xFFFFFFFCU);\r
+ status = HAL_FLASHEx_DATAEEPROM_Program(FLASH_TYPEPROGRAMDATA_FASTWORD, (Address & 0xFFFFFFFCU), tmp);\r
+ }\r
+ else\r
+ {\r
+ HAL_FLASHEx_DATAEEPROM_Program(FLASH_TYPEPROGRAMDATA_FASTBYTE, Address, 0x00U);\r
+ HAL_FLASHEx_DATAEEPROM_Program(FLASH_TYPEPROGRAMDATA_FASTBYTE, Address + 1U, 0x00U);\r
+ }\r
+ /* Process Locked */\r
+ __HAL_LOCK(&pFlash);\r
+ }\r
+#else /* !Cat1 */\r
+ /* If the previous operation is completed, proceed to write the new data */\r
+ *(__IO uint16_t *)Address = Data;\r
+ \r
+ /* Wait for last operation to be completed */\r
+ status = FLASH_WaitForLastOperation(FLASH_TIMEOUT_VALUE);\r
+#endif /* STM32L100xB || STM32L151xB || STM32L152xB */\r
+ }\r
+ /* Return the Write Status */\r
+ return status;\r
+}\r
+\r
+/**\r
+ * @brief Programs a word at a specified address in data memory.\r
+ * @param Address specifies the address to be written.\r
+ * @param Data specifies the data to be written.\r
+ * @note This function assumes that the is data word is already erased.\r
+ * @retval HAL status\r
+ */\r
+static HAL_StatusTypeDef FLASH_DATAEEPROM_FastProgramWord(uint32_t Address, uint32_t Data)\r
+{\r
+ HAL_StatusTypeDef status = HAL_OK;\r
+\r
+ /* Check the parameters */\r
+ assert_param(IS_FLASH_DATA_ADDRESS(Address));\r
+ \r
+ /* Wait for last operation to be completed */\r
+ status = FLASH_WaitForLastOperation(FLASH_TIMEOUT_VALUE);\r
+ \r
+ if(status == HAL_OK)\r
+ {\r
+ /* Clear the FTDW bit */\r
+ CLEAR_BIT(FLASH->PECR, FLASH_PECR_FTDW);\r
+ \r
+ /* If the previous operation is completed, proceed to program the new data */ \r
+ *(__IO uint32_t *)Address = Data;\r
+ \r
+ /* Wait for last operation to be completed */\r
+ status = FLASH_WaitForLastOperation(FLASH_TIMEOUT_VALUE); \r
+ }\r
+ /* Return the Write Status */\r
+ return status;\r
+}\r
+\r
+/**\r
+ * @brief Write a Byte at a specified address in data memory without erase.\r
+ * @param Address specifies the address to be written.\r
+ * @param Data specifies the data to be written.\r
+ * @retval HAL status\r
+ */\r
+static HAL_StatusTypeDef FLASH_DATAEEPROM_ProgramByte(uint32_t Address, uint8_t Data)\r
+{\r
+ HAL_StatusTypeDef status = HAL_OK;\r
+#if defined(STM32L100xB) || defined(STM32L151xB) || defined(STM32L152xB)\r
+ uint32_t tmp = 0U, tmpaddr = 0U;\r
+#endif /* STM32L100xB || STM32L151xB || STM32L152xB */\r
+ \r
+ /* Check the parameters */\r
+ assert_param(IS_FLASH_DATA_ADDRESS(Address)); \r
+\r
+ /* Wait for last operation to be completed */\r
+ status = FLASH_WaitForLastOperation(FLASH_TIMEOUT_VALUE);\r
+ \r
+ if(status == HAL_OK)\r
+ {\r
+#if defined(STM32L100xB) || defined(STM32L151xB) || defined(STM32L152xB)\r
+ if(Data != (uint8_t) 0x00U)\r
+ { \r
+ *(__IO uint8_t *)Address = Data;\r
+ \r
+ /* Wait for last operation to be completed */\r
+ status = FLASH_WaitForLastOperation(FLASH_TIMEOUT_VALUE);\r
+\r
+ }\r
+ else\r
+ {\r
+ tmpaddr = Address & 0xFFFFFFFCU;\r
+ tmp = * (__IO uint32_t *) tmpaddr;\r
+ tmpaddr = 0xFFU << ((uint32_t) (0x8U * (Address & 0x3U)));\r
+ tmp &= ~tmpaddr; \r
+ status = HAL_FLASHEx_DATAEEPROM_Erase(FLASH_TYPEERASEDATA_WORD, Address & 0xFFFFFFFCU);\r
+ /* Process Unlocked */\r
+ __HAL_UNLOCK(&pFlash);\r
+ status = HAL_FLASHEx_DATAEEPROM_Program(FLASH_TYPEPROGRAMDATA_FASTWORD, (Address & 0xFFFFFFFCU), tmp);\r
+ /* Process Locked */\r
+ __HAL_LOCK(&pFlash);\r
+ }\r
+#else /* Not Cat1*/\r
+ *(__IO uint8_t *)Address = Data;\r
+ \r
+ /* Wait for last operation to be completed */\r
+ status = FLASH_WaitForLastOperation(FLASH_TIMEOUT_VALUE);\r
+#endif /* STM32L100xB || STM32L151xB || STM32L152xB */\r
+ }\r
+ /* Return the Write Status */\r
+ return status;\r
+}\r
+\r
+/**\r
+ * @brief Writes a half word at a specified address in data memory without erase.\r
+ * @param Address specifies the address to be written.\r
+ * @param Data specifies the data to be written.\r
+ * @retval HAL status\r
+ */\r
+static HAL_StatusTypeDef FLASH_DATAEEPROM_ProgramHalfWord(uint32_t Address, uint16_t Data)\r
+{\r
+ HAL_StatusTypeDef status = HAL_OK;\r
+#if defined(STM32L100xB) || defined(STM32L151xB) || defined(STM32L152xB)\r
+ uint32_t tmp = 0U, tmpaddr = 0U;\r
+#endif /* STM32L100xB || STM32L151xB || STM32L152xB */\r
+ \r
+ /* Check the parameters */\r
+ assert_param(IS_FLASH_DATA_ADDRESS(Address));\r
+\r
+ /* Wait for last operation to be completed */\r
+ status = FLASH_WaitForLastOperation(FLASH_TIMEOUT_VALUE);\r
+ \r
+ if(status == HAL_OK)\r
+ {\r
+#if defined(STM32L100xB) || defined(STM32L151xB) || defined(STM32L152xB)\r
+ if(Data != (uint16_t)0x0000U)\r
+ {\r
+ *(__IO uint16_t *)Address = Data;\r
+ \r
+ /* Wait for last operation to be completed */\r
+ status = FLASH_WaitForLastOperation(FLASH_TIMEOUT_VALUE);\r
+ }\r
+ else\r
+ {\r
+ /* Process Unlocked */\r
+ __HAL_UNLOCK(&pFlash);\r
+ if((Address & 0x3U) != 0x3U)\r
+ {\r
+ tmpaddr = Address & 0xFFFFFFFCU;\r
+ tmp = * (__IO uint32_t *) tmpaddr;\r
+ tmpaddr = 0xFFFFU << ((uint32_t) (0x8U * (Address & 0x3U)));\r
+ tmp &= ~tmpaddr; \r
+ status = HAL_FLASHEx_DATAEEPROM_Erase(FLASH_TYPEERASEDATA_WORD, Address & 0xFFFFFFFCU);\r
+ status = HAL_FLASHEx_DATAEEPROM_Program(FLASH_TYPEPROGRAMDATA_FASTWORD, (Address & 0xFFFFFFFCU), tmp);\r
+ }\r
+ else\r
+ {\r
+ HAL_FLASHEx_DATAEEPROM_Program(FLASH_TYPEPROGRAMDATA_FASTBYTE, Address, 0x00U);\r
+ HAL_FLASHEx_DATAEEPROM_Program(FLASH_TYPEPROGRAMDATA_FASTBYTE, Address + 1U, 0x00U);\r
+ }\r
+ /* Process Locked */\r
+ __HAL_LOCK(&pFlash);\r
+ }\r
+#else /* Not Cat1*/\r
+ *(__IO uint16_t *)Address = Data;\r
+ \r
+ /* Wait for last operation to be completed */\r
+ status = FLASH_WaitForLastOperation(FLASH_TIMEOUT_VALUE);\r
+#endif /* STM32L100xB || STM32L151xB || STM32L152xB */\r
+ }\r
+ /* Return the Write Status */\r
+ return status;\r
+}\r
+\r
+/**\r
+ * @brief Programs a word at a specified address in data memory without erase.\r
+ * @param Address specifies the address to be written.\r
+ * @param Data specifies the data to be written.\r
+ * @retval HAL status\r
+ */\r
+static HAL_StatusTypeDef FLASH_DATAEEPROM_ProgramWord(uint32_t Address, uint32_t Data)\r
+{\r
+ HAL_StatusTypeDef status = HAL_OK;\r
+ \r
+ /* Check the parameters */\r
+ assert_param(IS_FLASH_DATA_ADDRESS(Address));\r
+ \r
+ /* Wait for last operation to be completed */\r
+ status = FLASH_WaitForLastOperation(FLASH_TIMEOUT_VALUE);\r
+ \r
+ if(status == HAL_OK)\r
+ {\r
+ *(__IO uint32_t *)Address = Data;\r
+\r
+ /* Wait for last operation to be completed */\r
+ status = FLASH_WaitForLastOperation(FLASH_TIMEOUT_VALUE);\r
+ }\r
+ /* Return the Write Status */\r
+ return status;\r
+}\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @addtogroup FLASH\r
+ * @{\r
+ */\r
+\r
+\r
+/** @addtogroup FLASH_Private_Functions\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @brief Erases a specified page in program memory.\r
+ * @param PageAddress The page address in program memory to be erased.\r
+ * @note A Page is erased in the Program memory only if the address to load \r
+ * is the start address of a page (multiple of @ref FLASH_PAGE_SIZE bytes).\r
+ * @retval None\r
+ */\r
+void FLASH_PageErase(uint32_t PageAddress)\r
+{\r
+ /* Clean the error context */\r
+ pFlash.ErrorCode = HAL_FLASH_ERROR_NONE;\r
+\r
+ /* Set the ERASE bit */\r
+ SET_BIT(FLASH->PECR, FLASH_PECR_ERASE);\r
+\r
+ /* Set PROG bit */\r
+ SET_BIT(FLASH->PECR, FLASH_PECR_PROG);\r
+\r
+ /* Write 00000000h to the first word of the program page to erase */\r
+ *(__IO uint32_t *)(uint32_t)(PageAddress & ~(FLASH_PAGE_SIZE - 1)) = 0x00000000;\r
+}\r
+ \r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+#endif /* HAL_FLASH_MODULE_ENABLED */\r
+/**\r
+ * @}\r
+ */\r
+\r
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\r
--- /dev/null
+/**\r
+ ******************************************************************************\r
+ * @file stm32l1xx_hal_flash_ramfunc.c\r
+ * @author MCD Application Team\r
+ * @brief FLASH RAMFUNC driver.\r
+ * This file provides a Flash firmware functions which should be \r
+ * executed from internal SRAM\r
+ *\r
+ * @verbatim\r
+\r
+ *** ARM Compiler ***\r
+ --------------------\r
+ [..] RAM functions are defined using the toolchain options. \r
+ Functions that are be executed in RAM should reside in a separate\r
+ source module. Using the 'Options for File' dialog you can simply change\r
+ the 'Code / Const' area of a module to a memory space in physical RAM.\r
+ Available memory areas are declared in the 'Target' tab of the \r
+ Options for Target' dialog.\r
+\r
+ *** ICCARM Compiler ***\r
+ -----------------------\r
+ [..] RAM functions are defined using a specific toolchain keyword "__ramfunc".\r
+\r
+ *** GNU Compiler ***\r
+ --------------------\r
+ [..] RAM functions are defined using a specific toolchain attribute\r
+ "__attribute__((section(".RamFunc")))".\r
+\r
+@endverbatim\r
+ ******************************************************************************\r
+ * @attention\r
+ *\r
+ * <h2><center>© Copyright (c) 2017 STMicroelectronics.\r
+ * All rights reserved.</center></h2>\r
+ *\r
+ * This software component is licensed by ST under BSD 3-Clause license,\r
+ * the "License"; You may not use this file except in compliance with the\r
+ * License. You may obtain a copy of the License at:\r
+ * opensource.org/licenses/BSD-3-Clause\r
+ *\r
+ ******************************************************************************\r
+ */\r
+\r
+/* Includes ------------------------------------------------------------------*/\r
+#include "stm32l1xx_hal.h"\r
+\r
+/** @addtogroup STM32L1xx_HAL_Driver\r
+ * @{\r
+ */\r
+\r
+#ifdef HAL_FLASH_MODULE_ENABLED\r
+\r
+/** @addtogroup FLASH\r
+ * @{\r
+ */\r
+/** @addtogroup FLASH_Private_Variables\r
+ * @{\r
+ */\r
+extern FLASH_ProcessTypeDef pFlash;\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+ \r
+/** @defgroup FLASH_RAMFUNC FLASH_RAMFUNC\r
+ * @brief FLASH functions executed from RAM\r
+ * @{\r
+ */ \r
+\r
+\r
+/* Private typedef -----------------------------------------------------------*/\r
+/* Private define ------------------------------------------------------------*/\r
+/* Private macro -------------------------------------------------------------*/\r
+/* Private variables ---------------------------------------------------------*/\r
+/* Private function prototypes -----------------------------------------------*/\r
+/** @defgroup FLASH_RAMFUNC_Private_Functions FLASH RAM Private Functions\r
+ * @{\r
+ */\r
+\r
+static __RAM_FUNC HAL_StatusTypeDef FLASHRAM_WaitForLastOperation(uint32_t Timeout);\r
+static __RAM_FUNC HAL_StatusTypeDef FLASHRAM_SetErrorCode(void);\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/* Private functions ---------------------------------------------------------*/\r
+ \r
+/** @defgroup FLASH_RAMFUNC_Exported_Functions FLASH RAM Exported Functions\r
+ *\r
+@verbatim \r
+ ===============================================================================\r
+ ##### ramfunc functions #####\r
+ =============================================================================== \r
+ [..]\r
+ This subsection provides a set of functions that should be executed from RAM \r
+ transfers.\r
+\r
+@endverbatim\r
+ * @{\r
+ */ \r
+\r
+/** @defgroup FLASH_RAMFUNC_Exported_Functions_Group1 Peripheral features functions \r
+ * @{\r
+ */ \r
+\r
+/**\r
+ * @brief Enable the power down mode during RUN mode.\r
+ * @note This function can be used only when the user code is running from Internal SRAM.\r
+ * @retval HAL status\r
+ */\r
+__RAM_FUNC HAL_StatusTypeDef HAL_FLASHEx_EnableRunPowerDown(void)\r
+{\r
+ /* Enable the Power Down in Run mode*/\r
+ __HAL_FLASH_POWER_DOWN_ENABLE();\r
+\r
+ return HAL_OK;\r
+}\r
+\r
+/**\r
+ * @brief Disable the power down mode during RUN mode.\r
+ * @note This function can be used only when the user code is running from Internal SRAM.\r
+ * @retval HAL status\r
+ */\r
+__RAM_FUNC HAL_StatusTypeDef HAL_FLASHEx_DisableRunPowerDown(void)\r
+{\r
+ /* Disable the Power Down in Run mode*/\r
+ __HAL_FLASH_POWER_DOWN_DISABLE();\r
+\r
+ return HAL_OK; \r
+}\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup FLASH_RAMFUNC_Exported_Functions_Group2 Programming and erasing operation functions \r
+ *\r
+@verbatim \r
+@endverbatim\r
+ * @{\r
+ */\r
+\r
+#if defined(FLASH_PECR_PARALLBANK)\r
+/**\r
+ * @brief Erases a specified 2 pages in program memory in parallel.\r
+ * @note This function can be used only for STM32L151xD, STM32L152xD), STM32L162xD and Cat5 devices.\r
+ * To correctly run this function, the @ref HAL_FLASH_Unlock() function\r
+ * must be called before.\r
+ * Call the @ref HAL_FLASH_Lock() to disable the flash memory access \r
+ * (recommended to protect the FLASH memory against possible unwanted operation).\r
+ * @param Page_Address1: The page address in program memory to be erased in \r
+ * the first Bank (BANK1). This parameter should be between FLASH_BASE\r
+ * and FLASH_BANK1_END.\r
+ * @param Page_Address2: The page address in program memory to be erased in \r
+ * the second Bank (BANK2). This parameter should be between FLASH_BANK2_BASE\r
+ * and FLASH_BANK2_END.\r
+ * @note A Page is erased in the Program memory only if the address to load \r
+ * is the start address of a page (multiple of @ref FLASH_PAGE_SIZE bytes).\r
+ * @retval HAL status\r
+ */\r
+__RAM_FUNC HAL_StatusTypeDef HAL_FLASHEx_EraseParallelPage(uint32_t Page_Address1, uint32_t Page_Address2)\r
+{\r
+ HAL_StatusTypeDef status = HAL_OK;\r
+\r
+ /* Wait for last operation to be completed */\r
+ status = FLASHRAM_WaitForLastOperation(FLASH_TIMEOUT_VALUE);\r
+ \r
+ if(status == HAL_OK)\r
+ {\r
+ /* Proceed to erase the page */\r
+ SET_BIT(FLASH->PECR, FLASH_PECR_PARALLBANK);\r
+ SET_BIT(FLASH->PECR, FLASH_PECR_ERASE);\r
+ SET_BIT(FLASH->PECR, FLASH_PECR_PROG);\r
+ \r
+ /* Write 00000000h to the first word of the first program page to erase */\r
+ *(__IO uint32_t *)Page_Address1 = 0x00000000U;\r
+ /* Write 00000000h to the first word of the second program page to erase */ \r
+ *(__IO uint32_t *)Page_Address2 = 0x00000000U;\r
+ \r
+ /* Wait for last operation to be completed */\r
+ status = FLASHRAM_WaitForLastOperation(FLASH_TIMEOUT_VALUE);\r
+\r
+ /* If the erase operation is completed, disable the ERASE, PROG and PARALLBANK bits */\r
+ CLEAR_BIT(FLASH->PECR, FLASH_PECR_PROG);\r
+ CLEAR_BIT(FLASH->PECR, FLASH_PECR_ERASE);\r
+ CLEAR_BIT(FLASH->PECR, FLASH_PECR_PARALLBANK);\r
+ } \r
+ /* Return the Erase Status */\r
+ return status;\r
+}\r
+\r
+/**\r
+ * @brief Program 2 half pages in program memory in parallel (half page size is 32 Words).\r
+ * @note This function can be used only for STM32L151xD, STM32L152xD), STM32L162xD and Cat5 devices.\r
+ * @param Address1: specifies the first address to be written in the first bank \r
+ * (BANK1). This parameter should be between FLASH_BASE and (FLASH_BANK1_END - FLASH_PAGE_SIZE).\r
+ * @param pBuffer1: pointer to the buffer containing the data to be written \r
+ * to the first half page in the first bank.\r
+ * @param Address2: specifies the second address to be written in the second bank\r
+ * (BANK2). This parameter should be between FLASH_BANK2_BASE and (FLASH_BANK2_END - FLASH_PAGE_SIZE).\r
+ * @param pBuffer2: pointer to the buffer containing the data to be written \r
+ * to the second half page in the second bank.\r
+ * @note To correctly run this function, the @ref HAL_FLASH_Unlock() function\r
+ * must be called before.\r
+ * Call the @ref HAL_FLASH_Lock() to disable the flash memory access \r
+ * (recommended to protect the FLASH memory against possible unwanted operation).\r
+ * @note Half page write is possible only from SRAM.\r
+ * @note If there are more than 32 words to write, after 32 words another \r
+ * Half Page programming operation starts and has to be finished.\r
+ * @note A half page is written to the program memory only if the first \r
+ * address to load is the start address of a half page (multiple of 128 \r
+ * bytes) and the 31 remaining words to load are in the same half page.\r
+ * @note During the Program memory half page write all read operations are \r
+ * forbidden (this includes DMA read operations and debugger read \r
+ * operations such as breakpoints, periodic updates, etc.).\r
+ * @note If a PGAERR is set during a Program memory half page write, the \r
+ * complete write operation is aborted. Software should then reset the \r
+ * FPRG and PROG/DATA bits and restart the write operation from the \r
+ * beginning.\r
+ * @retval HAL status\r
+ */\r
+__RAM_FUNC HAL_StatusTypeDef HAL_FLASHEx_ProgramParallelHalfPage(uint32_t Address1, uint32_t* pBuffer1, uint32_t Address2, uint32_t* pBuffer2)\r
+{\r
+ uint32_t primask_bit;\r
+ uint32_t count = 0U; \r
+ HAL_StatusTypeDef status = HAL_OK;\r
+\r
+ /* Wait for last operation to be completed */\r
+ status = FLASHRAM_WaitForLastOperation(FLASH_TIMEOUT_VALUE);\r
+ \r
+ if(status == HAL_OK)\r
+ {\r
+ /* Disable all IRQs */\r
+ primask_bit = __get_PRIMASK();\r
+ __disable_irq();\r
+ \r
+ /* Proceed to program the new half page */\r
+ SET_BIT(FLASH->PECR, FLASH_PECR_PARALLBANK);\r
+ SET_BIT(FLASH->PECR, FLASH_PECR_FPRG);\r
+ SET_BIT(FLASH->PECR, FLASH_PECR_PROG);\r
+\r
+ /* Write the first half page directly with 32 different words */\r
+ while(count < 32U)\r
+ {\r
+ *(__IO uint32_t*) ((uint32_t)(Address1 + (4 * count))) = *pBuffer1;\r
+ pBuffer1++;\r
+ count ++; \r
+ }\r
+ \r
+ /* Write the second half page directly with 32 different words */\r
+ count = 0U;\r
+ while(count < 32U)\r
+ {\r
+ *(__IO uint32_t*) ((uint32_t)(Address2 + (4 * count))) = *pBuffer2;\r
+ pBuffer2++;\r
+ count ++; \r
+ }\r
+ \r
+ /* Wait for last operation to be completed */\r
+ status = FLASHRAM_WaitForLastOperation(FLASH_TIMEOUT_VALUE);\r
+ \r
+ /* if the write operation is completed, disable the PROG, FPRG and PARALLBANK bits */\r
+ CLEAR_BIT(FLASH->PECR, FLASH_PECR_PROG);\r
+ CLEAR_BIT(FLASH->PECR, FLASH_PECR_FPRG);\r
+ CLEAR_BIT(FLASH->PECR, FLASH_PECR_PARALLBANK);\r
+\r
+ /* Enable IRQs */\r
+ __set_PRIMASK(primask_bit); \r
+ }\r
+\r
+ /* Return the Write Status */\r
+ return status;\r
+}\r
+#endif /* FLASH_PECR_PARALLBANK */\r
+\r
+/**\r
+ * @brief Program a half page in program memory.\r
+ * @param Address specifies the address to be written.\r
+ * @param pBuffer pointer to the buffer containing the data to be written to \r
+ * the half page.\r
+ * @note To correctly run this function, the @ref HAL_FLASH_Unlock() function\r
+ * must be called before.\r
+ * Call the @ref HAL_FLASH_Lock() to disable the flash memory access \r
+ * (recommended to protect the FLASH memory against possible unwanted operation)\r
+ * @note Half page write is possible only from SRAM.\r
+ * @note If there are more than 32 words to write, after 32 words another \r
+ * Half Page programming operation starts and has to be finished.\r
+ * @note A half page is written to the program memory only if the first \r
+ * address to load is the start address of a half page (multiple of 128 \r
+ * bytes) and the 31 remaining words to load are in the same half page.\r
+ * @note During the Program memory half page write all read operations are \r
+ * forbidden (this includes DMA read operations and debugger read \r
+ * operations such as breakpoints, periodic updates, etc.).\r
+ * @note If a PGAERR is set during a Program memory half page write, the \r
+ * complete write operation is aborted. Software should then reset the \r
+ * FPRG and PROG/DATA bits and restart the write operation from the \r
+ * beginning.\r
+ * @retval HAL status\r
+ */\r
+__RAM_FUNC HAL_StatusTypeDef HAL_FLASHEx_HalfPageProgram(uint32_t Address, uint32_t* pBuffer)\r
+{\r
+ uint32_t primask_bit;\r
+ uint32_t count = 0U; \r
+ HAL_StatusTypeDef status = HAL_OK;\r
+\r
+ /* Wait for last operation to be completed */\r
+ status = FLASHRAM_WaitForLastOperation(FLASH_TIMEOUT_VALUE);\r
+ \r
+ if(status == HAL_OK)\r
+ {\r
+ /* Disable all IRQs */\r
+ primask_bit = __get_PRIMASK();\r
+ __disable_irq();\r
+\r
+ /* Proceed to program the new half page */\r
+ SET_BIT(FLASH->PECR, FLASH_PECR_FPRG);\r
+ SET_BIT(FLASH->PECR, FLASH_PECR_PROG);\r
+ \r
+ /* Write one half page directly with 32 different words */\r
+ while(count < 32U)\r
+ {\r
+ *(__IO uint32_t*) ((uint32_t)(Address + (4 * count))) = *pBuffer;\r
+ pBuffer++;\r
+ count ++; \r
+ }\r
+\r
+ /* Wait for last operation to be completed */\r
+ status = FLASHRAM_WaitForLastOperation(FLASH_TIMEOUT_VALUE);\r
+ \r
+ /* If the write operation is completed, disable the PROG and FPRG bits */\r
+ CLEAR_BIT(FLASH->PECR, FLASH_PECR_PROG);\r
+ CLEAR_BIT(FLASH->PECR, FLASH_PECR_FPRG);\r
+\r
+ /* Enable IRQs */\r
+ __set_PRIMASK(primask_bit);\r
+ }\r
+ \r
+ /* Return the Write Status */\r
+ return status;\r
+}\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup FLASH_RAMFUNC_Exported_Functions_Group3 Peripheral errors functions \r
+ * @brief Peripheral errors functions \r
+ *\r
+@verbatim \r
+ ===============================================================================\r
+ ##### Peripheral errors functions #####\r
+ =============================================================================== \r
+ [..]\r
+ This subsection permit to get in run-time errors of the FLASH peripheral.\r
+\r
+@endverbatim\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @brief Get the specific FLASH errors flag.\r
+ * @param Error pointer is the error value. It can be a mixed of:\r
+@if STM32L100xB\r
+@elif STM32L100xBA\r
+ * @arg @ref HAL_FLASH_ERROR_RD FLASH Read Protection error flag (PCROP)\r
+@elif STM32L151xB\r
+@elif STM32L151xBA\r
+ * @arg @ref HAL_FLASH_ERROR_RD FLASH Read Protection error flag (PCROP)\r
+@elif STM32L152xB\r
+@elif STM32L152xBA\r
+ * @arg @ref HAL_FLASH_ERROR_RD FLASH Read Protection error flag (PCROP)\r
+@elif STM32L100xC\r
+ * @arg @ref HAL_FLASH_ERROR_RD FLASH Read Protection error flag (PCROP)\r
+ * @arg @ref HAL_FLASH_ERROR_OPTVUSR FLASH Option User validity error\r
+@elif STM32L151xC\r
+ * @arg @ref HAL_FLASH_ERROR_RD FLASH Read Protection error flag (PCROP)\r
+ * @arg @ref HAL_FLASH_ERROR_OPTVUSR FLASH Option User validity error\r
+@elif STM32L152xC\r
+ * @arg @ref HAL_FLASH_ERROR_RD FLASH Read Protection error flag (PCROP)\r
+ * @arg @ref HAL_FLASH_ERROR_OPTVUSR FLASH Option User validity error\r
+@elif STM32L162xC\r
+ * @arg @ref HAL_FLASH_ERROR_RD FLASH Read Protection error flag (PCROP)\r
+ * @arg @ref HAL_FLASH_ERROR_OPTVUSR FLASH Option User validity error\r
+@else\r
+ * @arg @ref HAL_FLASH_ERROR_OPTVUSR FLASH Option User validity error\r
+@endif\r
+ * @arg @ref HAL_FLASH_ERROR_PGA FLASH Programming Alignment error flag\r
+ * @arg @ref HAL_FLASH_ERROR_WRP FLASH Write protected error flag\r
+ * @arg @ref HAL_FLASH_ERROR_OPTV FLASH Option valid error flag \r
+ * @retval HAL Status\r
+ */\r
+__RAM_FUNC HAL_StatusTypeDef HAL_FLASHEx_GetError(uint32_t * Error)\r
+{ \r
+ *Error = pFlash.ErrorCode;\r
+ return HAL_OK; \r
+}\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup FLASH_RAMFUNC_Exported_Functions_Group4 DATA EEPROM functions\r
+ *\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @brief Erase a double word in data memory.\r
+ * @param Address specifies the address to be erased.\r
+ * @note To correctly run this function, the HAL_FLASH_EEPROM_Unlock() function\r
+ * must be called before.\r
+ * Call the HAL_FLASH_EEPROM_Lock() to he data EEPROM access\r
+ * and Flash program erase control register access(recommended to protect \r
+ * the DATA_EEPROM against possible unwanted operation).\r
+ * @note Data memory double word erase is possible only from SRAM.\r
+ * @note A double word is erased to the data memory only if the first address \r
+ * to load is the start address of a double word (multiple of 8 bytes).\r
+ * @note During the Data memory double word erase, all read operations are \r
+ * forbidden (this includes DMA read operations and debugger read \r
+ * operations such as breakpoints, periodic updates, etc.).\r
+ * @retval HAL status\r
+ */\r
+\r
+__RAM_FUNC HAL_StatusTypeDef HAL_FLASHEx_DATAEEPROM_EraseDoubleWord(uint32_t Address)\r
+{\r
+ uint32_t primask_bit;\r
+ HAL_StatusTypeDef status = HAL_OK;\r
+ \r
+ /* Wait for last operation to be completed */\r
+ status = FLASHRAM_WaitForLastOperation(FLASH_TIMEOUT_VALUE);\r
+ \r
+ if(status == HAL_OK)\r
+ {\r
+ /* Disable all IRQs */\r
+ primask_bit = __get_PRIMASK();\r
+ __disable_irq();\r
+\r
+ /* If the previous operation is completed, proceed to erase the next double word */\r
+ /* Set the ERASE bit */\r
+ SET_BIT(FLASH->PECR, FLASH_PECR_ERASE);\r
+\r
+ /* Set DATA bit */\r
+ SET_BIT(FLASH->PECR, FLASH_PECR_DATA);\r
+ \r
+ /* Write 00000000h to the 2 words to erase */\r
+ *(__IO uint32_t *)Address = 0x00000000U;\r
+ Address += 4U;\r
+ *(__IO uint32_t *)Address = 0x00000000U;\r
+ \r
+ /* Wait for last operation to be completed */\r
+ status = FLASHRAM_WaitForLastOperation(FLASH_TIMEOUT_VALUE);\r
+ \r
+ /* If the erase operation is completed, disable the ERASE and DATA bits */\r
+ CLEAR_BIT(FLASH->PECR, FLASH_PECR_ERASE);\r
+ CLEAR_BIT(FLASH->PECR, FLASH_PECR_DATA);\r
+\r
+ /* Enable IRQs */\r
+ __set_PRIMASK(primask_bit);\r
+ \r
+ } \r
+ \r
+ /* Return the erase status */\r
+ return status;\r
+}\r
+\r
+/**\r
+ * @brief Write a double word in data memory without erase.\r
+ * @param Address specifies the address to be written.\r
+ * @param Data specifies the data to be written.\r
+ * @note To correctly run this function, the HAL_FLASH_EEPROM_Unlock() function\r
+ * must be called before.\r
+ * Call the HAL_FLASH_EEPROM_Lock() to he data EEPROM access\r
+ * and Flash program erase control register access(recommended to protect \r
+ * the DATA_EEPROM against possible unwanted operation).\r
+ * @note Data memory double word write is possible only from SRAM.\r
+ * @note A data memory double word is written to the data memory only if the \r
+ * first address to load is the start address of a double word (multiple \r
+ * of double word).\r
+ * @note During the Data memory double word write, all read operations are \r
+ * forbidden (this includes DMA read operations and debugger read \r
+ * operations such as breakpoints, periodic updates, etc.).\r
+ * @retval HAL status\r
+ */ \r
+__RAM_FUNC HAL_StatusTypeDef HAL_FLASHEx_DATAEEPROM_ProgramDoubleWord(uint32_t Address, uint64_t Data)\r
+{\r
+ uint32_t primask_bit;\r
+ HAL_StatusTypeDef status = HAL_OK;\r
+\r
+ /* Wait for last operation to be completed */\r
+ status = FLASHRAM_WaitForLastOperation(FLASH_TIMEOUT_VALUE);\r
+ \r
+ if(status == HAL_OK)\r
+ {\r
+ /* Disable all IRQs */\r
+ primask_bit = __get_PRIMASK();\r
+ __disable_irq();\r
+\r
+ /* If the previous operation is completed, proceed to program the new data*/\r
+ SET_BIT(FLASH->PECR, FLASH_PECR_FPRG);\r
+ SET_BIT(FLASH->PECR, FLASH_PECR_DATA);\r
+ \r
+ /* Write the 2 words */ \r
+ *(__IO uint32_t *)Address = (uint32_t) Data;\r
+ Address += 4U;\r
+ *(__IO uint32_t *)Address = (uint32_t) (Data >> 32);\r
+ \r
+ /* Wait for last operation to be completed */\r
+ status = FLASHRAM_WaitForLastOperation(FLASH_TIMEOUT_VALUE);\r
+ \r
+ /* If the write operation is completed, disable the FPRG and DATA bits */\r
+ CLEAR_BIT(FLASH->PECR, FLASH_PECR_FPRG);\r
+ CLEAR_BIT(FLASH->PECR, FLASH_PECR_DATA); \r
+\r
+ /* Enable IRQs */\r
+ __set_PRIMASK(primask_bit);\r
+ }\r
+ \r
+ /* Return the Write Status */\r
+ return status;\r
+}\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @addtogroup FLASH_RAMFUNC_Private_Functions\r
+ * @{\r
+ */ \r
+\r
+/**\r
+ * @brief Set the specific FLASH error flag.\r
+ * @retval HAL Status\r
+ */\r
+static __RAM_FUNC HAL_StatusTypeDef FLASHRAM_SetErrorCode(void)\r
+{\r
+ uint32_t flags = 0U;\r
+ \r
+ if(__HAL_FLASH_GET_FLAG(FLASH_FLAG_WRPERR))\r
+ {\r
+ pFlash.ErrorCode |= HAL_FLASH_ERROR_WRP;\r
+ flags |= FLASH_FLAG_WRPERR;\r
+ }\r
+ if(__HAL_FLASH_GET_FLAG(FLASH_FLAG_PGAERR))\r
+ {\r
+ pFlash.ErrorCode |= HAL_FLASH_ERROR_PGA;\r
+ flags |= FLASH_FLAG_PGAERR;\r
+ }\r
+ if(__HAL_FLASH_GET_FLAG(FLASH_FLAG_OPTVERR))\r
+ {\r
+ pFlash.ErrorCode |= HAL_FLASH_ERROR_OPTV;\r
+ flags |= FLASH_FLAG_OPTVERR;\r
+ }\r
+\r
+#if defined(FLASH_SR_RDERR)\r
+ if(__HAL_FLASH_GET_FLAG(FLASH_FLAG_RDERR))\r
+ {\r
+ pFlash.ErrorCode |= HAL_FLASH_ERROR_RD;\r
+ flags |= FLASH_FLAG_RDERR;\r
+ }\r
+#endif /* FLASH_SR_RDERR */\r
+#if defined(FLASH_SR_OPTVERRUSR)\r
+ if(__HAL_FLASH_GET_FLAG(FLASH_FLAG_OPTVERRUSR))\r
+ {\r
+ pFlash.ErrorCode |= HAL_FLASH_ERROR_OPTVUSR;\r
+ flags |= FLASH_FLAG_OPTVERRUSR;\r
+ }\r
+#endif /* FLASH_SR_OPTVERRUSR */\r
+\r
+ /* Clear FLASH error pending bits */\r
+ __HAL_FLASH_CLEAR_FLAG(flags);\r
+\r
+ return HAL_OK;\r
+} \r
+\r
+/**\r
+ * @brief Wait for a FLASH operation to complete.\r
+ * @param Timeout maximum flash operationtimeout\r
+ * @retval HAL status\r
+ */\r
+static __RAM_FUNC HAL_StatusTypeDef FLASHRAM_WaitForLastOperation(uint32_t Timeout)\r
+{ \r
+ /* Wait for the FLASH operation to complete by polling on BUSY flag to be reset.\r
+ Even if the FLASH operation fails, the BUSY flag will be reset and an error\r
+ flag will be set */\r
+ \r
+ while(__HAL_FLASH_GET_FLAG(FLASH_FLAG_BSY) && (Timeout != 0x00U)) \r
+ { \r
+ Timeout--;\r
+ }\r
+ \r
+ if(Timeout == 0x00U)\r
+ {\r
+ return HAL_TIMEOUT;\r
+ }\r
+ \r
+ /* Check FLASH End of Operation flag */\r
+ if (__HAL_FLASH_GET_FLAG(FLASH_FLAG_EOP))\r
+ {\r
+ /* Clear FLASH End of Operation pending bit */\r
+ __HAL_FLASH_CLEAR_FLAG(FLASH_FLAG_EOP);\r
+ }\r
+ \r
+ if(__HAL_FLASH_GET_FLAG(FLASH_FLAG_WRPERR) || \r
+ __HAL_FLASH_GET_FLAG(FLASH_FLAG_OPTVERR) || \r
+#if defined(FLASH_SR_RDERR)\r
+ __HAL_FLASH_GET_FLAG(FLASH_FLAG_RDERR) || \r
+#endif /* FLASH_SR_RDERR */\r
+#if defined(FLASH_SR_OPTVERRUSR)\r
+ __HAL_FLASH_GET_FLAG(FLASH_FLAG_OPTVERRUSR) || \r
+#endif /* FLASH_SR_OPTVERRUSR */\r
+ __HAL_FLASH_GET_FLAG(FLASH_FLAG_PGAERR))\r
+ {\r
+ /*Save the error code*/\r
+ FLASHRAM_SetErrorCode();\r
+ return HAL_ERROR;\r
+ }\r
+\r
+ /* There is no error flag set */\r
+ return HAL_OK;\r
+}\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+#endif /* HAL_FLASH_MODULE_ENABLED */\r
+/**\r
+ * @}\r
+ */\r
+\r
+ \r
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\r
--- /dev/null
+/**\r
+ ******************************************************************************\r
+ * @file stm32l1xx_hal_gpio.c\r
+ * @author MCD Application Team\r
+ * @brief GPIO HAL module driver.\r
+ * This file provides firmware functions to manage the following \r
+ * functionalities of the General Purpose Input/Output (GPIO) peripheral:\r
+ * + Initialization and de-initialization functions\r
+ * + IO operation functions\r
+ * \r
+ @verbatim\r
+ ==============================================================================\r
+ ##### GPIO Peripheral features #####\r
+ ============================================================================== \r
+ [..] \r
+ Each port bit of the general-purpose I/O (GPIO) ports can be individually \r
+ configured by software in several modes:\r
+ (+) Input mode \r
+ (+) Analog mode\r
+ (+) Output mode\r
+ (+) Alternate function mode\r
+ (+) External interrupt/event lines\r
+ \r
+ [..] \r
+ During and just after reset, the alternate functions and external interrupt \r
+ lines are not active and the I/O ports are configured in input floating mode.\r
+ \r
+ [..] \r
+ All GPIO pins have weak internal pull-up and pull-down resistors, which can be \r
+ activated or not.\r
+\r
+ [..]\r
+ In Output or Alternate mode, each IO can be configured on open-drain or push-pull\r
+ type and the IO speed can be selected depending on the VDD value.\r
+ \r
+ [..]\r
+ The microcontroller IO pins are connected to onboard peripherals/modules through a \r
+ multiplexer that allows only one peripheral s alternate function (AF) connected \r
+ to an IO pin at a time. In this way, there can be no conflict between peripherals \r
+ sharing the same IO pin. \r
+ \r
+ [..] \r
+ All ports have external interrupt/event capability. To use external interrupt \r
+ lines, the port must be configured in input mode. All available GPIO pins are \r
+ connected to the 16 external interrupt/event lines from EXTI0 to EXTI15.\r
+ \r
+ [..] \r
+ The external interrupt/event controller consists of up to 28 edge detectors \r
+ (depending on products 16 lines are connected to GPIO) for generating event/interrupt\r
+ requests (each input line can be independently configured to select the type \r
+ (interrupt or event) and the corresponding trigger event (rising or falling or both). \r
+ Each line can also be masked independently. \r
+ \r
+ ##### How to use this driver #####\r
+ ============================================================================== \r
+ [..]\r
+ (#) Enable the GPIO AHB clock using the following function : __GPIOx_CLK_ENABLE(). \r
+ \r
+ (#) Configure the GPIO pin(s) using HAL_GPIO_Init().\r
+ (++) Configure the IO mode using "Mode" member from GPIO_InitTypeDef structure\r
+ (++) Activate Pull-up, Pull-down resistor using "Pull" member from GPIO_InitTypeDef \r
+ structure.\r
+ (++) In case of Output or alternate function mode selection: the speed is \r
+ configured through "Speed" member from GPIO_InitTypeDef structure, \r
+ the speed is configurable: Low, Medium and High.\r
+ (++) If alternate mode is selected, the alternate function connected to the IO\r
+ is configured through "Alternate" member from GPIO_InitTypeDef structure\r
+ (++) Analog mode is required when a pin is to be used as ADC channel \r
+ or DAC output.\r
+ (++) In case of external interrupt/event selection the "Mode" member from \r
+ GPIO_InitTypeDef structure select the type (interrupt or event) and \r
+ the corresponding trigger event (rising or falling or both).\r
+ \r
+ (#) In case of external interrupt/event mode selection, configure NVIC IRQ priority \r
+ mapped to the EXTI line using HAL_NVIC_SetPriority() and enable it using\r
+ HAL_NVIC_EnableIRQ().\r
+ \r
+ (#) HAL_GPIO_DeInit allows to set register values to their reset value. It's also \r
+ recommended to use it to unconfigure pin which was used as an external interrupt \r
+ or in event mode. That's the only way to reset corresponding bit in EXTI & SYSCFG \r
+ registers.\r
+ \r
+ (#) To get the level of a pin configured in input mode use HAL_GPIO_ReadPin().\r
+ \r
+ (#) To set/reset the level of a pin configured in output mode use \r
+ HAL_GPIO_WritePin()/HAL_GPIO_TogglePin().\r
+ \r
+ (#) To lock pin configuration until next reset use HAL_GPIO_LockPin().\r
+ \r
+ (#) During and just after reset, the alternate functions are not \r
+ active and the GPIO pins are configured in input floating mode (except JTAG\r
+ pins).\r
+ \r
+ (#) The LSE oscillator pins OSC32_IN and OSC32_OUT can be used as general purpose \r
+ (PC14 and PC15, respectively) when the LSE oscillator is off. The LSE has \r
+ priority over the GPIO function.\r
+ \r
+ (#) The HSE oscillator pins OSC_IN/OSC_OUT can be used as \r
+ general purpose PH0 and PH1, respectively, when the HSE oscillator is off. \r
+ The HSE has priority over the GPIO function.\r
+ \r
+ @endverbatim\r
+ ******************************************************************************\r
+ * @attention\r
+ *\r
+ * <h2><center>© Copyright (c) 2017 STMicroelectronics.\r
+ * All rights reserved.</center></h2>\r
+ *\r
+ * This software component is licensed by ST under BSD 3-Clause license,\r
+ * the "License"; You may not use this file except in compliance with the\r
+ * License. You may obtain a copy of the License at:\r
+ * opensource.org/licenses/BSD-3-Clause\r
+ *\r
+ ****************************************************************************** \r
+ */\r
+\r
+/* Includes ------------------------------------------------------------------*/\r
+#include "stm32l1xx_hal.h"\r
+\r
+/** @addtogroup STM32L1xx_HAL_Driver\r
+ * @{\r
+ */\r
+\r
+/** @addtogroup GPIO\r
+ * @brief GPIO HAL module driver\r
+ * @{\r
+ */\r
+\r
+#ifdef HAL_GPIO_MODULE_ENABLED\r
+\r
+/* Private typedef -----------------------------------------------------------*/\r
+/* Private define ------------------------------------------------------------*/\r
+/** @addtogroup GPIO_Private_Constants\r
+ * @{\r
+ */\r
+#define GPIO_MODE (0x00000003U)\r
+#define EXTI_MODE (0x10000000U)\r
+#define GPIO_MODE_IT (0x00010000U)\r
+#define GPIO_MODE_EVT (0x00020000U)\r
+#define RISING_EDGE (0x00100000U)\r
+#define FALLING_EDGE (0x00200000U)\r
+#define GPIO_OUTPUT_TYPE (0x00000010U)\r
+\r
+#define GPIO_NUMBER (16U)\r
+ \r
+/**\r
+ * @}\r
+ */\r
+ \r
+/* Private macro -------------------------------------------------------------*/\r
+/* Private variables ---------------------------------------------------------*/\r
+/* Private function prototypes -----------------------------------------------*/\r
+/* Exported functions ---------------------------------------------------------*/\r
+\r
+/** @addtogroup GPIO_Exported_Functions\r
+ * @{\r
+ */\r
+\r
+/** @addtogroup GPIO_Exported_Functions_Group1\r
+ * @brief Initialization and Configuration functions \r
+ *\r
+@verbatim \r
+ ===============================================================================\r
+ ##### Initialization and Configuration functions #####\r
+ ===============================================================================\r
+ \r
+@endverbatim\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @brief Initializes the GPIOx peripheral according to the specified parameters in the GPIO_Init.\r
+ * @param GPIOx where x can be (A..G depending on device used) to select the GPIO peripheral for STM32L1XX family devices\r
+ * @param GPIO_Init pointer to a GPIO_InitTypeDef structure that contains\r
+ * the configuration information for the specified GPIO peripheral.\r
+ * @retval None\r
+ */\r
+void HAL_GPIO_Init(GPIO_TypeDef *GPIOx, GPIO_InitTypeDef *GPIO_Init)\r
+{ \r
+ uint32_t position = 0x00;\r
+ uint32_t iocurrent = 0x00;\r
+ uint32_t temp = 0x00;\r
+\r
+ /* Check the parameters */\r
+ assert_param(IS_GPIO_ALL_INSTANCE(GPIOx));\r
+ assert_param(IS_GPIO_PIN(GPIO_Init->Pin));\r
+ assert_param(IS_GPIO_MODE(GPIO_Init->Mode));\r
+ assert_param(IS_GPIO_PULL(GPIO_Init->Pull)); \r
+\r
+ /* Configure the port pins */\r
+ while (((GPIO_Init->Pin) >> position) != 0)\r
+ {\r
+ /* Get current io position */\r
+ iocurrent = (GPIO_Init->Pin) & (1U << position);\r
+ \r
+ if(iocurrent)\r
+ {\r
+ /*--------------------- GPIO Mode Configuration ------------------------*/\r
+ /* In case of Alternate function mode selection */\r
+ if((GPIO_Init->Mode == GPIO_MODE_AF_PP) || (GPIO_Init->Mode == GPIO_MODE_AF_OD)) \r
+ {\r
+ /* Check the Alternate function parameters */\r
+ assert_param(IS_GPIO_AF_INSTANCE(GPIOx));\r
+ assert_param(IS_GPIO_AF(GPIO_Init->Alternate));\r
+ \r
+ /* Configure Alternate function mapped with the current IO */ \r
+ /* Identify AFRL or AFRH register based on IO position*/\r
+ temp = GPIOx->AFR[position >> 3];\r
+ CLEAR_BIT(temp, 0xFU << ((uint32_t)(position & 0x07U) * 4)) ; \r
+ SET_BIT(temp, (uint32_t)(GPIO_Init->Alternate) << (((uint32_t)position & 0x07U) * 4)); \r
+ GPIOx->AFR[position >> 3] = temp;\r
+ }\r
+\r
+ /* Configure IO Direction mode (Input, Output, Alternate or Analog) */\r
+ temp = GPIOx->MODER;\r
+ CLEAR_BIT(temp, GPIO_MODER_MODER0 << (position * 2)); \r
+ SET_BIT(temp, (GPIO_Init->Mode & GPIO_MODE) << (position * 2));\r
+ GPIOx->MODER = temp;\r
+\r
+ /* In case of Output or Alternate function mode selection */\r
+ if ((GPIO_Init->Mode == GPIO_MODE_OUTPUT_PP) || (GPIO_Init->Mode == GPIO_MODE_AF_PP) ||\r
+ (GPIO_Init->Mode == GPIO_MODE_OUTPUT_OD) || (GPIO_Init->Mode == GPIO_MODE_AF_OD))\r
+ {\r
+ /* Check the Speed parameter */\r
+ assert_param(IS_GPIO_SPEED(GPIO_Init->Speed));\r
+ /* Configure the IO Speed */\r
+ temp = GPIOx->OSPEEDR; \r
+ CLEAR_BIT(temp, GPIO_OSPEEDER_OSPEEDR0 << (position * 2));\r
+ SET_BIT(temp, GPIO_Init->Speed << (position * 2));\r
+ GPIOx->OSPEEDR = temp;\r
+\r
+ /* Configure the IO Output Type */\r
+ temp = GPIOx->OTYPER;\r
+ CLEAR_BIT(temp, GPIO_OTYPER_OT_0 << position) ;\r
+ SET_BIT(temp, ((GPIO_Init->Mode & GPIO_OUTPUT_TYPE) >> 4) << position);\r
+ GPIOx->OTYPER = temp;\r
+ }\r
+\r
+ /* Activate the Pull-up or Pull down resistor for the current IO */\r
+ temp = GPIOx->PUPDR;\r
+ CLEAR_BIT(temp, GPIO_PUPDR_PUPDR0 << (position * 2));\r
+ SET_BIT(temp, (GPIO_Init->Pull) << (position * 2));\r
+ GPIOx->PUPDR = temp;\r
+\r
+ /*--------------------- EXTI Mode Configuration ------------------------*/\r
+ /* Configure the External Interrupt or event for the current IO */\r
+ if((GPIO_Init->Mode & EXTI_MODE) == EXTI_MODE) \r
+ {\r
+ /* Enable SYSCFG Clock */\r
+ __HAL_RCC_SYSCFG_CLK_ENABLE();\r
+ \r
+ temp = SYSCFG->EXTICR[position >> 2];\r
+ CLEAR_BIT(temp, (0x0FU) << (4 * (position & 0x03)));\r
+ SET_BIT(temp, (GPIO_GET_INDEX(GPIOx)) << (4 * (position & 0x03)));\r
+ SYSCFG->EXTICR[position >> 2] = temp;\r
+ \r
+ /* Clear EXTI line configuration */\r
+ temp = EXTI->IMR;\r
+ CLEAR_BIT(temp, (uint32_t)iocurrent);\r
+ if((GPIO_Init->Mode & GPIO_MODE_IT) == GPIO_MODE_IT)\r
+ {\r
+ SET_BIT(temp, iocurrent); \r
+ }\r
+ EXTI->IMR = temp;\r
+\r
+ temp = EXTI->EMR;\r
+ CLEAR_BIT(temp, (uint32_t)iocurrent); \r
+ if((GPIO_Init->Mode & GPIO_MODE_EVT) == GPIO_MODE_EVT)\r
+ {\r
+ SET_BIT(temp, iocurrent); \r
+ }\r
+ EXTI->EMR = temp;\r
+ \r
+ /* Clear Rising Falling edge configuration */\r
+ temp = EXTI->RTSR;\r
+ CLEAR_BIT(temp, (uint32_t)iocurrent); \r
+ if((GPIO_Init->Mode & RISING_EDGE) == RISING_EDGE)\r
+ {\r
+ SET_BIT(temp, iocurrent); \r
+ }\r
+ EXTI->RTSR = temp;\r
+\r
+ temp = EXTI->FTSR;\r
+ CLEAR_BIT(temp, (uint32_t)iocurrent); \r
+ if((GPIO_Init->Mode & FALLING_EDGE) == FALLING_EDGE)\r
+ {\r
+ SET_BIT(temp, iocurrent); \r
+ }\r
+ EXTI->FTSR = temp;\r
+ }\r
+ }\r
+ \r
+ position++;\r
+ } \r
+}\r
+\r
+/**\r
+ * @brief De-initializes the GPIOx peripheral registers to their default reset values.\r
+ * @param GPIOx where x can be (A..G depending on device used) to select the GPIO peripheral for STM32L1XX family devices\r
+ * @param GPIO_Pin specifies the port bit to be written.\r
+ * This parameter can be one of GPIO_PIN_x where x can be (0..15).\r
+ * @retval None\r
+ */\r
+void HAL_GPIO_DeInit(GPIO_TypeDef *GPIOx, uint32_t GPIO_Pin)\r
+{\r
+ uint32_t position = 0x00;\r
+ uint32_t iocurrent = 0x00;\r
+ uint32_t tmp = 0x00;\r
+\r
+ /* Check the parameters */\r
+ assert_param(IS_GPIO_ALL_INSTANCE(GPIOx));\r
+ assert_param(IS_GPIO_PIN(GPIO_Pin));\r
+\r
+ /* Configure the port pins */\r
+ while ((GPIO_Pin >> position) != 0)\r
+ {\r
+ /* Get current io position */\r
+ iocurrent = (GPIO_Pin) & (1U << position);\r
+\r
+ if (iocurrent)\r
+ {\r
+ /*------------------------- EXTI Mode Configuration --------------------*/\r
+ /* Clear the External Interrupt or Event for the current IO */\r
+ \r
+ tmp = SYSCFG->EXTICR[position >> 2];\r
+ tmp &= ((0x0FU) << (4 * (position & 0x03)));\r
+ if(tmp == (GPIO_GET_INDEX(GPIOx) << (4 * (position & 0x03))))\r
+ {\r
+ tmp = (0x0FU) << (4 * (position & 0x03));\r
+ CLEAR_BIT(SYSCFG->EXTICR[position >> 2], tmp);\r
+ \r
+ /* Clear EXTI line configuration */\r
+ CLEAR_BIT(EXTI->IMR, (uint32_t)iocurrent);\r
+ CLEAR_BIT(EXTI->EMR, (uint32_t)iocurrent);\r
+ \r
+ /* Clear Rising Falling edge configuration */\r
+ CLEAR_BIT(EXTI->RTSR, (uint32_t)iocurrent);\r
+ CLEAR_BIT(EXTI->FTSR, (uint32_t)iocurrent);\r
+ }\r
+\r
+ /*------------------------- GPIO Mode Configuration --------------------*/\r
+ /* Configure IO Direction in Input Floting Mode */\r
+ CLEAR_BIT(GPIOx->MODER, GPIO_MODER_MODER0 << (position * 2)); \r
+ \r
+ /* Configure the default Alternate Function in current IO */ \r
+ CLEAR_BIT(GPIOx->AFR[position >> 3], 0xFU << ((uint32_t)(position & 0x07U) * 4)) ;\r
+ \r
+ /* Configure the default value for IO Speed */\r
+ CLEAR_BIT(GPIOx->OSPEEDR, GPIO_OSPEEDER_OSPEEDR0 << (position * 2));\r
+ \r
+ /* Configure the default value IO Output Type */\r
+ CLEAR_BIT(GPIOx->OTYPER, GPIO_OTYPER_OT_0 << position) ;\r
+ \r
+ /* Deactivate the Pull-up oand Pull-down resistor for the current IO */\r
+ CLEAR_BIT(GPIOx->PUPDR, GPIO_PUPDR_PUPDR0 << (position * 2));\r
+ }\r
+\r
+ position++;\r
+ }\r
+}\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @addtogroup GPIO_Exported_Functions_Group2\r
+ * @brief GPIO Read, Write, Toggle, Lock and EXTI management functions.\r
+ *\r
+@verbatim \r
+ ===============================================================================\r
+ ##### IO operation functions #####\r
+ =============================================================================== \r
+\r
+@endverbatim\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @brief Reads the specified input port pin.\r
+ * @param GPIOx where x can be (A..G depending on device used) to select the GPIO peripheral for STM32L1XX family devices \r
+ * @param GPIO_Pin specifies the port bit to read.\r
+ * This parameter can be GPIO_PIN_x where x can be (0..15).\r
+ * @retval The input port pin value.\r
+ */\r
+GPIO_PinState HAL_GPIO_ReadPin(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin)\r
+{\r
+ GPIO_PinState bitstatus;\r
+\r
+ /* Check the parameters */\r
+ assert_param(IS_GPIO_PIN(GPIO_Pin));\r
+\r
+ if ((GPIOx->IDR & GPIO_Pin) != (uint32_t)GPIO_PIN_RESET)\r
+ {\r
+ bitstatus = GPIO_PIN_SET;\r
+ }\r
+ else\r
+ {\r
+ bitstatus = GPIO_PIN_RESET;\r
+ }\r
+ return bitstatus;\r
+}\r
+\r
+/**\r
+ * @brief Sets or clears the selected data port bit.\r
+ * @note This function uses GPIOx_BSRR register to allow atomic read/modify \r
+ * accesses. In this way, there is no risk of an IRQ occurring between\r
+ * the read and the modify access.\r
+ * @param GPIOx where x can be (A..G depending on device used) to select the GPIO peripheral for STM32L1XX family devices\r
+ * @param GPIO_Pin specifies the port bit to be written.\r
+ * This parameter can be one of GPIO_PIN_x where x can be (0..15).\r
+ * @param PinState specifies the value to be written to the selected bit.\r
+ * This parameter can be one of the GPIO_PinState enum values:\r
+ * @arg GPIO_PIN_RESET: to clear the port pin\r
+ * @arg GPIO_PIN_SET: to set the port pin\r
+ * @retval None\r
+ */\r
+void HAL_GPIO_WritePin(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin, GPIO_PinState PinState)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_GPIO_PIN(GPIO_Pin));\r
+ assert_param(IS_GPIO_PIN_ACTION(PinState));\r
+\r
+ if (PinState != GPIO_PIN_RESET)\r
+ {\r
+ GPIOx->BSRR = (uint32_t)GPIO_Pin;\r
+ }\r
+ else\r
+ {\r
+ GPIOx->BSRR = (uint32_t)GPIO_Pin << 16 ;\r
+ }\r
+}\r
+ \r
+/**\r
+ * @brief Toggles the specified GPIO pin\r
+ * @param GPIOx where x can be (A..G depending on device used) to select the GPIO peripheral for STM32L1XX family devices \r
+ * @param GPIO_Pin specifies the pins to be toggled.\r
+ * @retval None\r
+ */\r
+void HAL_GPIO_TogglePin(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_GPIO_PIN(GPIO_Pin));\r
+\r
+ if ((GPIOx->ODR & GPIO_Pin) != 0x00u)\r
+ {\r
+ GPIOx->BSRR = (uint32_t)GPIO_Pin << GPIO_NUMBER;\r
+ }\r
+ else\r
+ {\r
+ GPIOx->BSRR = (uint32_t)GPIO_Pin;\r
+ }\r
+}\r
+\r
+/**\r
+* @brief Locks GPIO Pins configuration registers.\r
+* @note The locked registers are GPIOx_MODER, GPIOx_OTYPER, GPIOx_OSPEEDR,\r
+* GPIOx_PUPDR, GPIOx_AFRL and GPIOx_AFRH.\r
+* @note The configuration of the locked GPIO pins can no longer be modified\r
+* until the next reset.\r
+* @note Limitation concerning GPIOx_OTYPER: Locking of GPIOx_OTYPER[i] with i = 15..8\r
+* depends from setting of GPIOx_LCKR[i-8] and not from GPIOx_LCKR[i].\r
+* GPIOx_LCKR[i-8] is locking GPIOx_OTYPER[i] together with GPIOx_OTYPER[i-8].\r
+* It is not possible to lock GPIOx_OTYPER[i] with i = 15..8, without locking also\r
+* GPIOx_OTYPER[i-8].\r
+* Workaround: When calling HAL_GPIO_LockPin with GPIO_Pin from GPIO_PIN_8 to GPIO_PIN_15,\r
+* you must call also HAL_GPIO_LockPin with GPIO_Pin - 8. \r
+* (When locking a pin from GPIO_PIN_8 to GPIO_PIN_15, you must lock also the corresponding \r
+* GPIO_PIN_0 to GPIO_PIN_7).\r
+* @param GPIOx where x can be (A..G depending on device used) to select the GPIO peripheral for STM32L1XX family devices \r
+* @param GPIO_Pin Specifies the port bit to be locked.\r
+* This parameter can be any combination of GPIO_Pin_x where x can be (0..15).\r
+* @retval None\r
+*/\r
+HAL_StatusTypeDef HAL_GPIO_LockPin(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin)\r
+{\r
+ __IO uint32_t tmp = GPIO_LCKR_LCKK;\r
+\r
+ /* Check the parameters */\r
+ assert_param(IS_GPIO_LOCK_INSTANCE(GPIOx));\r
+ assert_param(IS_GPIO_PIN(GPIO_Pin));\r
+\r
+ /* Apply lock key write sequence */\r
+ SET_BIT(tmp, GPIO_Pin);\r
+ /* Set LCKx bit(s): LCKK='1' + LCK[15-0] */\r
+ GPIOx->LCKR = tmp;\r
+ /* Reset LCKx bit(s): LCKK='0' + LCK[15-0] */\r
+ GPIOx->LCKR = GPIO_Pin;\r
+ /* Set LCKx bit(s): LCKK='1' + LCK[15-0] */\r
+ GPIOx->LCKR = tmp;\r
+ /* Read LCKK register. This read is mandatory to complete key lock sequence */\r
+ tmp = GPIOx->LCKR;\r
+\r
+ /* Read again in order to confirm lock is active */\r
+ if((GPIOx->LCKR & GPIO_LCKR_LCKK) != RESET)\r
+ {\r
+ return HAL_OK;\r
+ }\r
+ else\r
+ {\r
+ return HAL_ERROR;\r
+ }\r
+}\r
+\r
+/**\r
+ * @brief This function handles EXTI interrupt request.\r
+ * @param GPIO_Pin Specifies the port pin connected to corresponding EXTI line.\r
+ * @retval None\r
+ */\r
+void HAL_GPIO_EXTI_IRQHandler(uint16_t GPIO_Pin)\r
+{\r
+ /* EXTI line interrupt detected */\r
+ if(__HAL_GPIO_EXTI_GET_IT(GPIO_Pin) != RESET) \r
+ { \r
+ __HAL_GPIO_EXTI_CLEAR_IT(GPIO_Pin);\r
+ HAL_GPIO_EXTI_Callback(GPIO_Pin);\r
+ }\r
+}\r
+\r
+/**\r
+ * @brief EXTI line detection callbacks.\r
+ * @param GPIO_Pin Specifies the port pin connected to corresponding EXTI line.\r
+ * @retval None\r
+ */\r
+__weak void HAL_GPIO_EXTI_Callback(uint16_t GPIO_Pin)\r
+{\r
+ /* Prevent unused argument(s) compilation warning */\r
+ UNUSED(GPIO_Pin);\r
+\r
+ /* NOTE : This function Should not be modified, when the callback is needed,\r
+ the HAL_GPIO_EXTI_Callback could be implemented in the user file\r
+ */ \r
+}\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+#endif /* HAL_GPIO_MODULE_ENABLED */\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\r
--- /dev/null
+/**\r
+ ******************************************************************************\r
+ * @file stm32l1xx_hal_pwr.c\r
+ * @author MCD Application Team\r
+ * @brief PWR HAL module driver.\r
+ *\r
+ * This file provides firmware functions to manage the following\r
+ * functionalities of the Power Controller (PWR) peripheral:\r
+ * + Initialization/de-initialization functions\r
+ * + Peripheral Control functions\r
+ *\r
+ ******************************************************************************\r
+ * @attention\r
+ *\r
+ * <h2><center>© Copyright (c) 2017 STMicroelectronics.\r
+ * All rights reserved.</center></h2>\r
+ *\r
+ * This software component is licensed by ST under BSD 3-Clause license,\r
+ * the "License"; You may not use this file except in compliance with the\r
+ * License. You may obtain a copy of the License at:\r
+ * opensource.org/licenses/BSD-3-Clause\r
+ *\r
+ ******************************************************************************\r
+ */\r
+\r
+/* Includes ------------------------------------------------------------------*/\r
+#include "stm32l1xx_hal.h"\r
+\r
+/** @addtogroup STM32L1xx_HAL_Driver\r
+ * @{\r
+ */\r
+\r
+/** @defgroup PWR PWR\r
+ * @brief PWR HAL module driver\r
+ * @{\r
+ */\r
+\r
+#ifdef HAL_PWR_MODULE_ENABLED\r
+\r
+/* Private typedef -----------------------------------------------------------*/\r
+/* Private define ------------------------------------------------------------*/\r
+#define PVD_MODE_IT (0x00010000U)\r
+#define PVD_MODE_EVT (0x00020000U)\r
+#define PVD_RISING_EDGE (0x00000001U)\r
+#define PVD_FALLING_EDGE (0x00000002U)\r
+\r
+/* Private macro -------------------------------------------------------------*/\r
+/* Private variables ---------------------------------------------------------*/\r
+/* Private function prototypes -----------------------------------------------*/\r
+/* Private functions ---------------------------------------------------------*/\r
+\r
+/** @defgroup PWR_Exported_Functions PWR Exported Functions\r
+ * @{\r
+ */\r
+\r
+/** @defgroup PWR_Exported_Functions_Group1 Initialization and de-initialization functions\r
+ * @brief Initialization and de-initialization functions\r
+ *\r
+@verbatim\r
+ ===============================================================================\r
+ ##### Initialization and de-initialization functions #####\r
+ ===============================================================================\r
+ [..]\r
+ After reset, the backup domain (RTC registers, RTC backup data\r
+ registers) is protected against possible unwanted\r
+ write accesses.\r
+ To enable access to the RTC Domain and RTC registers, proceed as follows:\r
+ (+) Enable the Power Controller (PWR) APB1 interface clock using the\r
+ __HAL_RCC_PWR_CLK_ENABLE() macro.\r
+ (+) Enable access to RTC domain using the HAL_PWR_EnableBkUpAccess() function.\r
+\r
+@endverbatim\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @brief Deinitializes the PWR peripheral registers to their default reset values.\r
+ * @note Before calling this function, the VOS[1:0] bits should be configured\r
+ * to "10" and the system frequency has to be configured accordingly.\r
+ * To configure the VOS[1:0] bits, use the PWR_VoltageScalingConfig()\r
+ * function.\r
+ * @note ULP and FWU bits are not reset by this function.\r
+ * @retval None\r
+ */\r
+void HAL_PWR_DeInit(void)\r
+{\r
+ __HAL_RCC_PWR_FORCE_RESET();\r
+ __HAL_RCC_PWR_RELEASE_RESET();\r
+}\r
+\r
+/**\r
+ * @brief Enables access to the backup domain (RTC registers, RTC\r
+ * backup data registers ).\r
+ * @note If the HSE divided by 2, 4, 8 or 16 is used as the RTC clock, the\r
+ * Backup Domain Access should be kept enabled.\r
+ * @retval None\r
+ */\r
+void HAL_PWR_EnableBkUpAccess(void)\r
+{\r
+ /* Enable access to RTC and backup registers */\r
+ *(__IO uint32_t *) CR_DBP_BB = (uint32_t)ENABLE;\r
+}\r
+\r
+/**\r
+ * @brief Disables access to the backup domain (RTC registers, RTC\r
+ * backup data registers).\r
+ * @note If the HSE divided by 2, 4, 8 or 16 is used as the RTC clock, the\r
+ * Backup Domain Access should be kept enabled.\r
+ * @retval None\r
+ */\r
+void HAL_PWR_DisableBkUpAccess(void)\r
+{\r
+ /* Disable access to RTC and backup registers */\r
+ *(__IO uint32_t *) CR_DBP_BB = (uint32_t)DISABLE;\r
+}\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup PWR_Exported_Functions_Group2 Peripheral Control functions\r
+ * @brief Low Power modes configuration functions\r
+ *\r
+@verbatim\r
+\r
+ ===============================================================================\r
+ ##### Peripheral Control functions #####\r
+ ===============================================================================\r
+\r
+ *** PVD configuration ***\r
+ =========================\r
+ [..]\r
+ (+) The PVD is used to monitor the VDD power supply by comparing it to a\r
+ threshold selected by the PVD Level (PLS[2:0] bits in the PWR_CR).\r
+ (+) The PVD can use an external input analog voltage (PVD_IN) which is compared\r
+ internally to VREFINT. The PVD_IN (PB7) has to be configured in Analog mode\r
+ when PWR_PVDLevel_7 is selected (PLS[2:0] = 111).\r
+\r
+ (+) A PVDO flag is available to indicate if VDD/VDDA is higher or lower\r
+ than the PVD threshold. This event is internally connected to the EXTI\r
+ line16 and can generate an interrupt if enabled. This is done through\r
+ __HAL_PWR_PVD_EXTI_ENABLE_IT() macro.\r
+ (+) The PVD is stopped in Standby mode.\r
+\r
+ *** WakeUp pin configuration ***\r
+ ================================\r
+ [..]\r
+ (+) WakeUp pin is used to wake up the system from Standby mode. This pin is\r
+ forced in input pull-down configuration and is active on rising edges.\r
+ (+) There are two or three WakeUp pins:\r
+ WakeUp Pin 1 on PA.00.\r
+ WakeUp Pin 2 on PC.13.\r
+ WakeUp Pin 3 on PE.06. : Only on product with GPIOE available\r
+\r
+ [..]\r
+ *** Main and Backup Regulators configuration ***\r
+ ================================================\r
+\r
+ (+) The main internal regulator can be configured to have a tradeoff between\r
+ performance and power consumption when the device does not operate at\r
+ the maximum frequency. This is done through __HAL_PWR_VOLTAGESCALING_CONFIG()\r
+ macro which configure VOS bit in PWR_CR register:\r
+ (++) When this bit is set (Regulator voltage output Scale 1 mode selected)\r
+ the System frequency can go up to 32 MHz.\r
+ (++) When this bit is reset (Regulator voltage output Scale 2 mode selected)\r
+ the System frequency can go up to 16 MHz.\r
+ (++) When this bit is reset (Regulator voltage output Scale 3 mode selected)\r
+ the System frequency can go up to 4.2 MHz.\r
+\r
+ Refer to the datasheets for more details.\r
+\r
+ *** Low Power modes configuration ***\r
+ =====================================\r
+ [..]\r
+ The device features 5 low-power modes:\r
+ (+) Low power run mode: regulator in low power mode, limited clock frequency,\r
+ limited number of peripherals running.\r
+ (+) Sleep mode: Cortex-M3 core stopped, peripherals kept running.\r
+ (+) Low power sleep mode: Cortex-M3 core stopped, limited clock frequency,\r
+ limited number of peripherals running, regulator in low power mode.\r
+ (+) Stop mode: All clocks are stopped, regulator running, regulator in low power mode.\r
+ (+) Standby mode: VCORE domain powered off\r
+\r
+ *** Low power run mode ***\r
+ =========================\r
+ [..]\r
+ To further reduce the consumption when the system is in Run mode, the regulator can be\r
+ configured in low power mode. In this mode, the system frequency should not exceed\r
+ MSI frequency range1.\r
+ In Low power run mode, all I/O pins keep the same state as in Run mode.\r
+\r
+ (+) Entry:\r
+ (++) VCORE in range2\r
+ (++) Decrease the system frequency tonot exceed the frequency of MSI frequency range1.\r
+ (++) The regulator is forced in low power mode using the HAL_PWREx_EnableLowPowerRunMode()\r
+ function.\r
+ (+) Exit:\r
+ (++) The regulator is forced in Main regulator mode using the HAL_PWREx_DisableLowPowerRunMode()\r
+ function.\r
+ (++) Increase the system frequency if needed.\r
+\r
+ *** Sleep mode ***\r
+ ==================\r
+ [..]\r
+ (+) Entry:\r
+ The Sleep mode is entered by using the HAL_PWR_EnterSLEEPMode(PWR_MAINREGULATOR_ON, PWR_SLEEPENTRY_WFx)\r
+ functions with\r
+ (++) PWR_SLEEPENTRY_WFI: enter SLEEP mode with WFI instruction\r
+ (++) PWR_SLEEPENTRY_WFE: enter SLEEP mode with WFE instruction\r
+\r
+ (+) Exit:\r
+ (++) Any peripheral interrupt acknowledged by the nested vectored interrupt\r
+ controller (NVIC) can wake up the device from Sleep mode.\r
+\r
+ *** Low power sleep mode ***\r
+ ============================\r
+ [..]\r
+ (+) Entry:\r
+ The Low power sleep mode is entered by using the HAL_PWR_EnterSLEEPMode(PWR_LOWPOWERREGULATOR_ON, PWR_SLEEPENTRY_WFx)\r
+ functions with\r
+ (++) PWR_SLEEPENTRY_WFI: enter SLEEP mode with WFI instruction\r
+ (++) PWR_SLEEPENTRY_WFE: enter SLEEP mode with WFE instruction\r
+ (+) The Flash memory can be switched off by using the control bits (SLEEP_PD in the FLASH_ACR register.\r
+ This reduces power consumption but increases the wake-up time.\r
+\r
+ (+) Exit:\r
+ (++) If the WFI instruction was used to enter Low power sleep mode, any peripheral interrupt\r
+ acknowledged by the nested vectored interrupt controller (NVIC) can wake up the device\r
+ from Low power sleep mode. If the WFE instruction was used to enter Low power sleep mode,\r
+ the MCU exits Sleep mode as soon as an event occurs.\r
+\r
+ *** Stop mode ***\r
+ =================\r
+ [..]\r
+ The Stop mode is based on the Cortex-M3 deepsleep mode combined with peripheral\r
+ clock gating. The voltage regulator can be configured either in normal or low-power mode.\r
+ In Stop mode, all clocks in the VCORE domain are stopped, the PLL, the MSI, the HSI and\r
+ the HSE RC oscillators are disabled. Internal SRAM and register contents are preserved.\r
+ To get the lowest consumption in Stop mode, the internal Flash memory also enters low\r
+ power mode. When the Flash memory is in power-down mode, an additional startup delay is\r
+ incurred when waking up from Stop mode.\r
+ To minimize the consumption In Stop mode, VREFINT, the BOR, PVD, and temperature\r
+ sensor can be switched off before entering Stop mode. They can be switched on again by\r
+ software after exiting Stop mode using the ULP bit in the PWR_CR register.\r
+ In Stop mode, all I/O pins keep the same state as in Run mode.\r
+\r
+ (+) Entry:\r
+ The Stop mode is entered using the HAL_PWR_EnterSTOPMode(PWR_MAINREGULATOR_ON, PWR_SLEEPENTRY_WFI )\r
+ function with:\r
+ (++) Main regulator ON.\r
+ (++) Low Power regulator ON.\r
+ (++) PWR_SLEEPENTRY_WFI: enter SLEEP mode with WFI instruction\r
+ (++) PWR_SLEEPENTRY_WFE: enter SLEEP mode with WFE instruction\r
+ (+) Exit:\r
+ (++) By issuing an interrupt or a wakeup event, the MSI RC oscillator is selected as system clock.\r
+\r
+ *** Standby mode ***\r
+ ====================\r
+ [..]\r
+ The Standby mode allows to achieve the lowest power consumption. It is based on the\r
+ Cortex-M3 deepsleep mode, with the voltage regulator disabled. The VCORE domain is\r
+ consequently powered off. The PLL, the MSI, the HSI oscillator and the HSE oscillator are\r
+ also switched off. SRAM and register contents are lost except for the RTC registers, RTC\r
+ backup registers and Standby circuitry.\r
+\r
+ To minimize the consumption In Standby mode, VREFINT, the BOR, PVD, and temperature\r
+ sensor can be switched off before entering the Standby mode. They can be switched\r
+ on again by software after exiting the Standby mode.\r
+ function.\r
+\r
+ (+) Entry:\r
+ (++) The Standby mode is entered using the HAL_PWR_EnterSTANDBYMode() function.\r
+ (+) Exit:\r
+ (++) WKUP pin rising edge, RTC alarm (Alarm A and Alarm B), RTC wakeup,\r
+ tamper event, time-stamp event, external reset in NRST pin, IWDG reset.\r
+\r
+ *** Auto-wakeup (AWU) from low-power mode ***\r
+ =============================================\r
+ [..]\r
+ The MCU can be woken up from low-power mode by an RTC Alarm event, an RTC\r
+ Wakeup event, a tamper event, a time-stamp event, or a comparator event,\r
+ without depending on an external interrupt (Auto-wakeup mode).\r
+\r
+ (+) RTC auto-wakeup (AWU) from the Stop mode\r
+ (++) To wake up from the Stop mode with an RTC alarm event, it is necessary to:\r
+ (+++) Configure the EXTI Line 17 to be sensitive to rising edges (Interrupt\r
+ or Event modes) and Enable the RTC Alarm Interrupt using the HAL_RTC_SetAlarm_IT()\r
+ function\r
+ (+++) Configure the RTC to generate the RTC alarm using the HAL_RTC_Init()\r
+ and HAL_RTC_SetTime() functions.\r
+ (++) To wake up from the Stop mode with an RTC Tamper or time stamp event, it\r
+ is necessary to:\r
+ (+++) Configure the EXTI Line 19 to be sensitive to rising edges (Interrupt or Event modes) and\r
+ Enable the RTC Tamper or time stamp Interrupt using the HAL_RTCEx_SetTamper_IT()\r
+ or HAL_RTCEx_SetTimeStamp_IT() functions.\r
+ (++) To wake up from the Stop mode with an RTC WakeUp event, it is necessary to:\r
+ (+++) Configure the EXTI Line 20 to be sensitive to rising edges (Interrupt or Event modes) and\r
+ Enable the RTC WakeUp Interrupt using the HAL_RTCEx_SetWakeUpTimer_IT() function.\r
+ (+++) Configure the RTC to generate the RTC WakeUp event using the HAL_RTCEx_SetWakeUpTimer()\r
+ function.\r
+\r
+ (+) RTC auto-wakeup (AWU) from the Standby mode\r
+ (++) To wake up from the Standby mode with an RTC alarm event, it is necessary to:\r
+ (+++) Enable the RTC Alarm Interrupt using the HAL_RTC_SetAlarm_IT() function.\r
+ (+++) Configure the RTC to generate the RTC alarm using the HAL_RTC_Init()\r
+ and HAL_RTC_SetTime() functions.\r
+ (++) To wake up from the Standby mode with an RTC Tamper or time stamp event, it\r
+ is necessary to:\r
+ (+++) Enable the RTC Tamper or time stamp Interrupt and Configure the RTC to\r
+ detect the tamper or time stamp event using the HAL_RTCEx_SetTimeStamp_IT()\r
+ or HAL_RTCEx_SetTamper_IT()functions.\r
+ (++) To wake up from the Standby mode with an RTC WakeUp event, it is necessary to:\r
+ (+++) Enable the RTC WakeUp Interrupt and Configure the RTC to generate the RTC WakeUp event\r
+ using the HAL_RTCEx_SetWakeUpTimer_IT() and HAL_RTCEx_SetWakeUpTimer() functions.\r
+\r
+ (+) Comparator auto-wakeup (AWU) from the Stop mode\r
+ (++) To wake up from the Stop mode with an comparator 1 or comparator 2 wakeup\r
+ event, it is necessary to:\r
+ (+++) Configure the EXTI Line 21 or EXTI Line 22 for comparator to be sensitive to to the\r
+ selected edges (falling, rising or falling and rising) (Interrupt or Event modes) using\r
+ the COMP functions.\r
+ (+++) Configure the comparator to generate the event.\r
+\r
+\r
+\r
+@endverbatim\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @brief Configures the voltage threshold detected by the Power Voltage Detector(PVD).\r
+ * @param sConfigPVD pointer to an PWR_PVDTypeDef structure that contains the configuration\r
+ * information for the PVD.\r
+ * @note Refer to the electrical characteristics of your device datasheet for\r
+ * more details about the voltage threshold corresponding to each\r
+ * detection level.\r
+ * @retval None\r
+ */\r
+void HAL_PWR_ConfigPVD(PWR_PVDTypeDef *sConfigPVD)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_PWR_PVD_LEVEL(sConfigPVD->PVDLevel));\r
+ assert_param(IS_PWR_PVD_MODE(sConfigPVD->Mode));\r
+\r
+ /* Set PLS[7:5] bits according to PVDLevel value */\r
+ MODIFY_REG(PWR->CR, PWR_CR_PLS, sConfigPVD->PVDLevel);\r
+\r
+ /* Clear any previous config. Keep it clear if no event or IT mode is selected */\r
+ __HAL_PWR_PVD_EXTI_DISABLE_EVENT();\r
+ __HAL_PWR_PVD_EXTI_DISABLE_IT();\r
+ __HAL_PWR_PVD_EXTI_DISABLE_RISING_FALLING_EDGE();\r
+\r
+ /* Configure interrupt mode */\r
+ if((sConfigPVD->Mode & PVD_MODE_IT) == PVD_MODE_IT)\r
+ {\r
+ __HAL_PWR_PVD_EXTI_ENABLE_IT();\r
+ }\r
+\r
+ /* Configure event mode */\r
+ if((sConfigPVD->Mode & PVD_MODE_EVT) == PVD_MODE_EVT)\r
+ {\r
+ __HAL_PWR_PVD_EXTI_ENABLE_EVENT();\r
+ }\r
+\r
+ /* Configure the edge */\r
+ if((sConfigPVD->Mode & PVD_RISING_EDGE) == PVD_RISING_EDGE)\r
+ {\r
+ __HAL_PWR_PVD_EXTI_ENABLE_RISING_EDGE();\r
+ }\r
+\r
+ if((sConfigPVD->Mode & PVD_FALLING_EDGE) == PVD_FALLING_EDGE)\r
+ {\r
+ __HAL_PWR_PVD_EXTI_ENABLE_FALLING_EDGE();\r
+ }\r
+}\r
+\r
+/**\r
+ * @brief Enables the Power Voltage Detector(PVD).\r
+ * @retval None\r
+ */\r
+void HAL_PWR_EnablePVD(void)\r
+{\r
+ /* Enable the power voltage detector */\r
+ *(__IO uint32_t *) CR_PVDE_BB = (uint32_t)ENABLE;\r
+}\r
+\r
+/**\r
+ * @brief Disables the Power Voltage Detector(PVD).\r
+ * @retval None\r
+ */\r
+void HAL_PWR_DisablePVD(void)\r
+{\r
+ /* Disable the power voltage detector */\r
+ *(__IO uint32_t *) CR_PVDE_BB = (uint32_t)DISABLE;\r
+}\r
+\r
+/**\r
+ * @brief Enables the WakeUp PINx functionality.\r
+ * @param WakeUpPinx: Specifies the Power Wake-Up pin to enable.\r
+ * This parameter can be one of the following values:\r
+ * @arg PWR_WAKEUP_PIN1\r
+ * @arg PWR_WAKEUP_PIN2\r
+ * @arg PWR_WAKEUP_PIN3: Only on product with GPIOE available\r
+ * @retval None\r
+ */\r
+void HAL_PWR_EnableWakeUpPin(uint32_t WakeUpPinx)\r
+{\r
+ /* Check the parameter */\r
+ assert_param(IS_PWR_WAKEUP_PIN(WakeUpPinx));\r
+ /* Enable the EWUPx pin */\r
+ *(__IO uint32_t *) CSR_EWUP_BB(WakeUpPinx) = (uint32_t)ENABLE;\r
+}\r
+\r
+/**\r
+ * @brief Disables the WakeUp PINx functionality.\r
+ * @param WakeUpPinx: Specifies the Power Wake-Up pin to disable.\r
+ * This parameter can be one of the following values:\r
+ * @arg PWR_WAKEUP_PIN1\r
+ * @arg PWR_WAKEUP_PIN2\r
+ * @arg PWR_WAKEUP_PIN3: Only on product with GPIOE available\r
+ * @retval None\r
+ */\r
+void HAL_PWR_DisableWakeUpPin(uint32_t WakeUpPinx)\r
+{\r
+ /* Check the parameter */\r
+ assert_param(IS_PWR_WAKEUP_PIN(WakeUpPinx));\r
+ /* Disable the EWUPx pin */\r
+ *(__IO uint32_t *) CSR_EWUP_BB(WakeUpPinx) = (uint32_t)DISABLE;\r
+}\r
+\r
+/**\r
+ * @brief Enters Sleep mode.\r
+ * @note In Sleep mode, all I/O pins keep the same state as in Run mode.\r
+ * @param Regulator: Specifies the regulator state in SLEEP mode.\r
+ * This parameter can be one of the following values:\r
+ * @arg PWR_MAINREGULATOR_ON: SLEEP mode with regulator ON\r
+ * @arg PWR_LOWPOWERREGULATOR_ON: SLEEP mode with low power regulator ON\r
+ * @param SLEEPEntry: Specifies if SLEEP mode is entered with WFI or WFE instruction.\r
+ * When WFI entry is used, tick interrupt have to be disabled if not desired as\r
+ * the interrupt wake up source.\r
+ * This parameter can be one of the following values:\r
+ * @arg PWR_SLEEPENTRY_WFI: enter SLEEP mode with WFI instruction\r
+ * @arg PWR_SLEEPENTRY_WFE: enter SLEEP mode with WFE instruction\r
+ * @retval None\r
+ */\r
+void HAL_PWR_EnterSLEEPMode(uint32_t Regulator, uint8_t SLEEPEntry)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_PWR_REGULATOR(Regulator));\r
+ assert_param(IS_PWR_SLEEP_ENTRY(SLEEPEntry));\r
+\r
+ /* Select the regulator state in Sleep mode: Set PDDS and LPSDSR bit according to PWR_Regulator value */\r
+ MODIFY_REG(PWR->CR, (PWR_CR_PDDS | PWR_CR_LPSDSR), Regulator);\r
+\r
+ /* Clear SLEEPDEEP bit of Cortex System Control Register */\r
+ CLEAR_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPDEEP_Msk));\r
+\r
+ /* Select SLEEP mode entry -------------------------------------------------*/\r
+ if(SLEEPEntry == PWR_SLEEPENTRY_WFI)\r
+ {\r
+ /* Request Wait For Interrupt */\r
+ __WFI();\r
+ }\r
+ else\r
+ {\r
+ /* Request Wait For Event */\r
+ __SEV();\r
+ __WFE();\r
+ __WFE();\r
+ }\r
+}\r
+\r
+/**\r
+ * @brief Enters Stop mode.\r
+ * @note In Stop mode, all I/O pins keep the same state as in Run mode.\r
+ * @note When exiting Stop mode by using an interrupt or a wakeup event,\r
+ * MSI RC oscillator is selected as system clock.\r
+ * @note When the voltage regulator operates in low power mode, an additional\r
+ * startup delay is incurred when waking up from Stop mode.\r
+ * By keeping the internal regulator ON during Stop mode, the consumption\r
+ * is higher although the startup time is reduced.\r
+ * @param Regulator: Specifies the regulator state in Stop mode.\r
+ * This parameter can be one of the following values:\r
+ * @arg PWR_MAINREGULATOR_ON: Stop mode with regulator ON\r
+ * @arg PWR_LOWPOWERREGULATOR_ON: Stop mode with low power regulator ON\r
+ * @param STOPEntry: Specifies if Stop mode in entered with WFI or WFE instruction.\r
+ * This parameter can be one of the following values:\r
+ * @arg PWR_STOPENTRY_WFI: Enter Stop mode with WFI instruction\r
+ * @arg PWR_STOPENTRY_WFE: Enter Stop mode with WFE instruction\r
+ * @retval None\r
+ */\r
+void HAL_PWR_EnterSTOPMode(uint32_t Regulator, uint8_t STOPEntry)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_PWR_REGULATOR(Regulator));\r
+ assert_param(IS_PWR_STOP_ENTRY(STOPEntry));\r
+\r
+ /* Select the regulator state in Stop mode: Set PDDS and LPSDSR bit according to PWR_Regulator value */\r
+ MODIFY_REG(PWR->CR, (PWR_CR_PDDS | PWR_CR_LPSDSR), Regulator);\r
+\r
+ /* Set SLEEPDEEP bit of Cortex System Control Register */\r
+ SET_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPDEEP_Msk));\r
+\r
+ /* Select Stop mode entry --------------------------------------------------*/\r
+ if(STOPEntry == PWR_STOPENTRY_WFI)\r
+ {\r
+ /* Request Wait For Interrupt */\r
+ __WFI();\r
+ }\r
+ else\r
+ {\r
+ /* Request Wait For Event */\r
+ __SEV();\r
+ __WFE();\r
+ __WFE();\r
+ }\r
+ /* Reset SLEEPDEEP bit of Cortex System Control Register */\r
+ CLEAR_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPDEEP_Msk));\r
+}\r
+\r
+/**\r
+ * @brief Enters Standby mode.\r
+ * @note In Standby mode, all I/O pins are high impedance except for:\r
+ * - Reset pad (still available)\r
+ * - RTC_AF1 pin (PC13) if configured for tamper, time-stamp, RTC\r
+ * Alarm out, or RTC clock calibration out.\r
+ * - WKUP pin 1 (PA0) if enabled.\r
+ * - WKUP pin 2 (PC13) if enabled.\r
+ * - WKUP pin 3 (PE6) if enabled.\r
+ * @retval None\r
+ */\r
+void HAL_PWR_EnterSTANDBYMode(void)\r
+{\r
+ /* Select Standby mode */\r
+ SET_BIT(PWR->CR, PWR_CR_PDDS);\r
+\r
+ /* Set SLEEPDEEP bit of Cortex System Control Register */\r
+ SET_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPDEEP_Msk));\r
+\r
+ /* This option is used to ensure that store operations are completed */\r
+#if defined ( __CC_ARM)\r
+ __force_stores();\r
+#endif\r
+ /* Request Wait For Interrupt */\r
+ __WFI();\r
+}\r
+\r
+\r
+/**\r
+ * @brief Indicates Sleep-On-Exit when returning from Handler mode to Thread mode.\r
+ * @note Set SLEEPONEXIT bit of SCR register. When this bit is set, the processor\r
+ * re-enters SLEEP mode when an interruption handling is over.\r
+ * Setting this bit is useful when the processor is expected to run only on\r
+ * interruptions handling.\r
+ * @retval None\r
+ */\r
+void HAL_PWR_EnableSleepOnExit(void)\r
+{\r
+ /* Set SLEEPONEXIT bit of Cortex System Control Register */\r
+ SET_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPONEXIT_Msk));\r
+}\r
+\r
+\r
+/**\r
+ * @brief Disables Sleep-On-Exit feature when returning from Handler mode to Thread mode.\r
+ * @note Clears SLEEPONEXIT bit of SCR register. When this bit is set, the processor\r
+ * re-enters SLEEP mode when an interruption handling is over.\r
+ * @retval None\r
+ */\r
+void HAL_PWR_DisableSleepOnExit(void)\r
+{\r
+ /* Clear SLEEPONEXIT bit of Cortex System Control Register */\r
+ CLEAR_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPONEXIT_Msk));\r
+}\r
+\r
+\r
+/**\r
+ * @brief Enables CORTEX M3 SEVONPEND bit.\r
+ * @note Sets SEVONPEND bit of SCR register. When this bit is set, this causes\r
+ * WFE to wake up when an interrupt moves from inactive to pended.\r
+ * @retval None\r
+ */\r
+void HAL_PWR_EnableSEVOnPend(void)\r
+{\r
+ /* Set SEVONPEND bit of Cortex System Control Register */\r
+ SET_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SEVONPEND_Msk));\r
+}\r
+\r
+\r
+/**\r
+ * @brief Disables CORTEX M3 SEVONPEND bit.\r
+ * @note Clears SEVONPEND bit of SCR register. When this bit is set, this causes\r
+ * WFE to wake up when an interrupt moves from inactive to pended.\r
+ * @retval None\r
+ */\r
+void HAL_PWR_DisableSEVOnPend(void)\r
+{\r
+ /* Clear SEVONPEND bit of Cortex System Control Register */\r
+ CLEAR_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SEVONPEND_Msk));\r
+}\r
+\r
+\r
+\r
+/**\r
+ * @brief This function handles the PWR PVD interrupt request.\r
+ * @note This API should be called under the PVD_IRQHandler().\r
+ * @retval None\r
+ */\r
+void HAL_PWR_PVD_IRQHandler(void)\r
+{\r
+ /* Check PWR exti flag */\r
+ if(__HAL_PWR_PVD_EXTI_GET_FLAG() != RESET)\r
+ {\r
+ /* PWR PVD interrupt user callback */\r
+ HAL_PWR_PVDCallback();\r
+\r
+ /* Clear PWR Exti pending bit */\r
+ __HAL_PWR_PVD_EXTI_CLEAR_FLAG();\r
+ }\r
+}\r
+\r
+/**\r
+ * @brief PWR PVD interrupt callback\r
+ * @retval None\r
+ */\r
+__weak void HAL_PWR_PVDCallback(void)\r
+{\r
+ /* NOTE : This function Should not be modified, when the callback is needed,\r
+ the HAL_PWR_PVDCallback could be implemented in the user file\r
+ */\r
+}\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+#endif /* HAL_PWR_MODULE_ENABLED */\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\r
--- /dev/null
+/**\r
+ ******************************************************************************\r
+ * @file stm32l1xx_hal_pwr_ex.c\r
+ * @author MCD Application Team\r
+ * @brief Extended PWR HAL module driver.\r
+ * This file provides firmware functions to manage the following\r
+ * functionalities of the Power Controller (PWR) peripheral:\r
+ * + Extended Initialization and de-initialization functions\r
+ * + Extended Peripheral Control functions\r
+ *\r
+ ******************************************************************************\r
+ * @attention\r
+ *\r
+ * <h2><center>© Copyright (c) 2017 STMicroelectronics.\r
+ * All rights reserved.</center></h2>\r
+ *\r
+ * This software component is licensed by ST under BSD 3-Clause license,\r
+ * the "License"; You may not use this file except in compliance with the\r
+ * License. You may obtain a copy of the License at:\r
+ * opensource.org/licenses/BSD-3-Clause\r
+ *\r
+ ******************************************************************************\r
+ */\r
+\r
+/* Includes ------------------------------------------------------------------*/\r
+#include "stm32l1xx_hal.h"\r
+\r
+/** @addtogroup STM32L1xx_HAL_Driver\r
+ * @{\r
+ */\r
+\r
+/** @defgroup PWREx PWREx\r
+ * @brief PWR HAL module driver\r
+ * @{\r
+ */\r
+\r
+#ifdef HAL_PWR_MODULE_ENABLED\r
+\r
+/* Private typedef -----------------------------------------------------------*/\r
+/* Private define ------------------------------------------------------------*/\r
+/* Private macro -------------------------------------------------------------*/\r
+/* Private variables ---------------------------------------------------------*/\r
+/* Private function prototypes -----------------------------------------------*/\r
+/* Private functions ---------------------------------------------------------*/\r
+\r
+/** @defgroup PWREx_Exported_Functions PWREx Exported Functions\r
+ * @{\r
+ */\r
+\r
+/** @defgroup PWREx_Exported_Functions_Group1 Peripheral Extended Features Functions\r
+ * @brief Low Power modes configuration functions\r
+ *\r
+@verbatim\r
+\r
+ ===============================================================================\r
+ ##### Peripheral extended features functions #####\r
+ ===============================================================================\r
+@endverbatim\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @brief Return Voltage Scaling Range.\r
+ * @retval VOS bit field (PWR_REGULATOR_VOLTAGE_SCALE1, PWR_REGULATOR_VOLTAGE_SCALE2 or PWR_REGULATOR_VOLTAGE_SCALE3)\r
+ */\r
+uint32_t HAL_PWREx_GetVoltageRange(void)\r
+{\r
+ return (PWR->CR & PWR_CR_VOS);\r
+}\r
+\r
+\r
+/**\r
+ * @brief Enables the Fast WakeUp from Ultra Low Power mode.\r
+ * @note This bit works in conjunction with ULP bit.\r
+ * Means, when ULP = 1 and FWU = 1 :VREFINT startup time is ignored when\r
+ * exiting from low power mode.\r
+ * @retval None\r
+ */\r
+void HAL_PWREx_EnableFastWakeUp(void)\r
+{\r
+ /* Enable the fast wake up */\r
+ *(__IO uint32_t *) CR_FWU_BB = (uint32_t)ENABLE;\r
+}\r
+\r
+/**\r
+ * @brief Disables the Fast WakeUp from Ultra Low Power mode.\r
+ * @retval None\r
+ */\r
+void HAL_PWREx_DisableFastWakeUp(void)\r
+{\r
+ /* Disable the fast wake up */\r
+ *(__IO uint32_t *) CR_FWU_BB = (uint32_t)DISABLE;\r
+}\r
+\r
+/**\r
+ * @brief Enables the Ultra Low Power mode\r
+ * @retval None\r
+ */\r
+void HAL_PWREx_EnableUltraLowPower(void)\r
+{\r
+ /* Enable the Ultra Low Power mode */\r
+ *(__IO uint32_t *) CR_ULP_BB = (uint32_t)ENABLE;\r
+}\r
+\r
+/**\r
+ * @brief Disables the Ultra Low Power mode\r
+ * @retval None\r
+ */\r
+void HAL_PWREx_DisableUltraLowPower(void)\r
+{\r
+ /* Disable the Ultra Low Power mode */\r
+ *(__IO uint32_t *) CR_ULP_BB = (uint32_t)DISABLE;\r
+}\r
+\r
+/**\r
+ * @brief Enters the Low Power Run mode.\r
+ * @note Low power run mode can only be entered when VCORE is in range 2.\r
+ * In addition, the dynamic voltage scaling must not be used when Low\r
+ * power run mode is selected. Only Stop and Sleep modes with regulator\r
+ * configured in Low power mode is allowed when Low power run mode is\r
+ * selected.\r
+ * @note In Low power run mode, all I/O pins keep the same state as in Run mode.\r
+ * @retval None\r
+ */\r
+void HAL_PWREx_EnableLowPowerRunMode(void)\r
+{\r
+ /* Enters the Low Power Run mode */\r
+ *(__IO uint32_t *) CR_LPSDSR_BB = (uint32_t)ENABLE;\r
+ *(__IO uint32_t *) CR_LPRUN_BB = (uint32_t)ENABLE;\r
+}\r
+\r
+/**\r
+ * @brief Exits the Low Power Run mode.\r
+ * @retval None\r
+ */\r
+HAL_StatusTypeDef HAL_PWREx_DisableLowPowerRunMode(void)\r
+{\r
+ /* Exits the Low Power Run mode */\r
+ *(__IO uint32_t *) CR_LPRUN_BB = (uint32_t)DISABLE;\r
+ *(__IO uint32_t *) CR_LPSDSR_BB = (uint32_t)DISABLE;\r
+ return HAL_OK;\r
+}\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+#endif /* HAL_PWR_MODULE_ENABLED */\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\r
--- /dev/null
+/**\r
+ ******************************************************************************\r
+ * @file stm32l1xx_hal_rcc.c\r
+ * @author MCD Application Team\r
+ * @brief RCC HAL module driver.\r
+ * This file provides firmware functions to manage the following\r
+ * functionalities of the Reset and Clock Control (RCC) peripheral:\r
+ * + Initialization and de-initialization functions\r
+ * + Peripheral Control functions\r
+ *\r
+ @verbatim\r
+ ==============================================================================\r
+ ##### RCC specific features #####\r
+ ==============================================================================\r
+ [..]\r
+ After reset the device is running from multispeed internal oscillator clock\r
+ (MSI 2.097MHz) with Flash 0 wait state and Flash prefetch buffer is disabled,\r
+ and all peripherals are off except internal SRAM, Flash and JTAG.\r
+ (+) There is no prescaler on High speed (AHB) and Low speed (APB) buses;\r
+ all peripherals mapped on these buses are running at MSI speed.\r
+ (+) The clock for all peripherals is switched off, except the SRAM and FLASH.\r
+ (+) All GPIOs are in input floating state, except the JTAG pins which\r
+ are assigned to be used for debug purpose.\r
+ [..] Once the device started from reset, the user application has to:\r
+ (+) Configure the clock source to be used to drive the System clock\r
+ (if the application needs higher frequency/performance)\r
+ (+) Configure the System clock frequency and Flash settings\r
+ (+) Configure the AHB and APB buses prescalers\r
+ (+) Enable the clock for the peripheral(s) to be used\r
+ (+) Configure the clock source(s) for peripherals whose clocks are not\r
+ derived from the System clock (I2S, RTC, ADC, USB OTG FS/SDIO/RNG)\r
+ (*) SDIO only for STM32L1xxxD devices\r
+\r
+ ##### RCC Limitations #####\r
+ ==============================================================================\r
+ [..]\r
+ A delay between an RCC peripheral clock enable and the effective peripheral\r
+ enabling should be taken into account in order to manage the peripheral read/write\r
+ from/to registers.\r
+ (+) This delay depends on the peripheral mapping.\r
+ (++) AHB & APB peripherals, 1 dummy read is necessary\r
+\r
+ [..]\r
+ Workarounds:\r
+ (#) For AHB & APB peripherals, a dummy read to the peripheral register has been\r
+ inserted in each __HAL_RCC_PPP_CLK_ENABLE() macro.\r
+\r
+ @endverbatim\r
+ ******************************************************************************\r
+ * @attention\r
+ *\r
+ * <h2><center>© Copyright(c) 2017 STMicroelectronics.\r
+ * All rights reserved.</center></h2>\r
+ *\r
+ * This software component is licensed by ST under BSD 3-Clause license,\r
+ * the "License"; You may not use this file except in compliance with the\r
+ * License. You may obtain a copy of the License at:\r
+ * opensource.org/licenses/BSD-3-Clause\r
+ *\r
+ ******************************************************************************\r
+ */\r
+\r
+/* Includes ------------------------------------------------------------------*/\r
+#include "stm32l1xx_hal.h"\r
+\r
+/** @addtogroup STM32L1xx_HAL_Driver\r
+ * @{\r
+ */\r
+\r
+/** @defgroup RCC RCC\r
+* @brief RCC HAL module driver\r
+ * @{\r
+ */\r
+\r
+#ifdef HAL_RCC_MODULE_ENABLED\r
+\r
+/* Private typedef -----------------------------------------------------------*/\r
+/* Private define ------------------------------------------------------------*/\r
+/* Private macro -------------------------------------------------------------*/\r
+/** @defgroup RCC_Private_Macros RCC Private Macros\r
+ * @{\r
+ */\r
+\r
+#define MCO1_CLK_ENABLE() __HAL_RCC_GPIOA_CLK_ENABLE()\r
+#define MCO1_GPIO_PORT GPIOA\r
+#define MCO1_PIN GPIO_PIN_8\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/* Private variables ---------------------------------------------------------*/\r
+/** @defgroup RCC_Private_Variables RCC Private Variables\r
+ * @{\r
+ */\r
+extern const uint8_t PLLMulTable[]; /* Defined in CMSIS (system_stm32l0xx.c)*/\r
+/**\r
+ * @}\r
+ */\r
+\r
+/* Private function prototypes -----------------------------------------------*/\r
+/** @defgroup RCC_Private_Functions RCC Private Functions\r
+ * @{\r
+ */\r
+static HAL_StatusTypeDef RCC_SetFlashLatencyFromMSIRange(uint32_t MSIrange);\r
+/**\r
+ * @}\r
+ */\r
+\r
+/* Exported functions ---------------------------------------------------------*/\r
+\r
+/** @defgroup RCC_Exported_Functions RCC Exported Functions\r
+ * @{\r
+ */\r
+\r
+/** @defgroup RCC_Exported_Functions_Group1 Initialization and de-initialization functions\r
+ * @brief Initialization and Configuration functions\r
+ *\r
+ @verbatim\r
+ ===============================================================================\r
+ ##### Initialization and de-initialization functions #####\r
+ ===============================================================================\r
+ [..]\r
+ This section provides functions allowing to configure the internal/external oscillators\r
+ (MSI, HSE, HSI, LSE, LSI, PLL, CSS and MCO) and the System buses clocks (SYSCLK, AHB, APB1\r
+ and APB2).\r
+\r
+ [..] Internal/external clock and PLL configuration\r
+ (#) MSI (Multispeed internal), Seven frequency ranges are available: 65.536 kHz,\r
+ 131.072 kHz, 262.144 kHz, 524.288 kHz, 1.048 MHz, 2.097 MHz (default value) and 4.194 MHz.\r
+\r
+ (#) HSI (high-speed internal), 16 MHz factory-trimmed RC used directly or through\r
+ the PLL as System clock source.\r
+ (#) LSI (low-speed internal), ~37 KHz low consumption RC used as IWDG and/or RTC\r
+ clock source.\r
+\r
+ (#) HSE (high-speed external), 1 to 24 MHz crystal oscillator used directly or\r
+ through the PLL as System clock source. Can be used also as RTC clock source.\r
+\r
+ (#) LSE (low-speed external), 32 KHz oscillator used as RTC clock source.\r
+\r
+ (#) PLL (clocked by HSI or HSE), featuring different output clocks:\r
+ (++) The first output is used to generate the high speed system clock (up to 32 MHz)\r
+ (++) The second output is used to generate the clock for the USB OTG FS (48 MHz)\r
+\r
+ (#) CSS (Clock security system), once enable using the macro __HAL_RCC_CSS_ENABLE()\r
+ and if a HSE clock failure occurs(HSE used directly or through PLL as System\r
+ clock source), the System clocks automatically switched to MSI and an interrupt\r
+ is generated if enabled. The interrupt is linked to the Cortex-M3 NMI\r
+ (Non-Maskable Interrupt) exception vector.\r
+\r
+ (#) MCO1 (microcontroller clock output), used to output SYSCLK, HSI, LSI, MSI, LSE,\r
+ HSE or PLL clock (through a configurable prescaler) on PA8 pin.\r
+\r
+ [..] System, AHB and APB buses clocks configuration\r
+ (#) Several clock sources can be used to drive the System clock (SYSCLK): MSI, HSI,\r
+ HSE and PLL.\r
+ The AHB clock (HCLK) is derived from System clock through configurable\r
+ prescaler and used to clock the CPU, memory and peripherals mapped\r
+ on AHB bus (DMA, GPIO...). APB1 (PCLK1) and APB2 (PCLK2) clocks are derived\r
+ from AHB clock through configurable prescalers and used to clock\r
+ the peripherals mapped on these buses. You can use\r
+ "@ref HAL_RCC_GetSysClockFreq()" function to retrieve the frequencies of these clocks.\r
+\r
+ -@- All the peripheral clocks are derived from the System clock (SYSCLK) except:\r
+ (+@) RTC: RTC clock can be derived either from the LSI, LSE or HSE clock\r
+ divided by 2 to 16. You have to use @ref __HAL_RCC_RTC_CONFIG() and @ref __HAL_RCC_RTC_ENABLE()\r
+ macros to configure this clock.\r
+ (+@) LCD: LCD clock can be derived either from the LSI, LSE or HSE clock\r
+ divided by 2 to 16. You have to use @ref __HAL_RCC_LCD_CONFIG()\r
+ macros to configure this clock.\r
+ (+@) USB OTG FS: USB OTG FS require a frequency equal to 48 MHz\r
+ to work correctly. This clock is derived of the main PLL through PLL Multiplier.\r
+\r
+ (+@) IWDG clock which is always the LSI clock.\r
+\r
+ (#) The maximum frequency of the SYSCLK and HCLK is 32 MHz, PCLK2 32 MHz\r
+ and PCLK1 32 MHz. Depending on the device voltage range, the maximum\r
+ frequency should be adapted accordingly.\r
+ @endverbatim\r
+ * @{\r
+ */\r
+\r
+/*\r
+ Additional consideration on the HCLK based on Latency settings:\r
+ +----------------------------------------------------------------------+\r
+ | Latency | HCLK clock frequency (MHz) |\r
+ | |------------------------------------------------------|\r
+ | | voltage range 1 | voltage range 2 | voltage range 3 |\r
+ | | 1.8 V | 1.5 V | 1.2 V |\r
+ |---------------|------------------|-----------------|-----------------|\r
+ |0WS(1CPU cycle)| 0 < HCLK <= 16 | 0 < HCLK <= 8 | 0 < HCLK <= 2 |\r
+ |---------------|------------------|-----------------|-----------------|\r
+ |1WS(2CPU cycle)| 16 < HCLK <= 32 | 8 < HCLK <= 16 | 2 < HCLK <= 4 |\r
+ +----------------------------------------------------------------------+\r
+\r
+ The following table gives the different clock source frequencies depending on the product\r
+ voltage range:\r
+ +------------------------------------------------------------------------------------------+\r
+ | Product voltage | Clock frequency |\r
+ | |------------------|-----------------------------|-----------------------|\r
+ | range | MSI | HSI | HSE | PLL |\r
+ |-----------------|---------|--------|-----------------------------|-----------------------|\r
+ | Range 1 (1.8 V) | 4.2 MHz | 16 MHz | HSE 32 MHz (external clock) | 32 MHz |\r
+ | | | | or 24 MHz (crystal) | (PLLVCO max = 96 MHz) |\r
+ |-----------------|---------|--------|-----------------------------|-----------------------|\r
+ | Range 2 (1.5 V) | 4.2 MHz | 16 MHz | 16 MHz | 16 MHz |\r
+ | | | | | (PLLVCO max = 48 MHz) |\r
+ |-----------------|---------|--------|-----------------------------|-----------------------|\r
+ | Range 3 (1.2 V) | 4.2 MHz | NA | 8 MHz | 4 MHz |\r
+ | | | | | (PLLVCO max = 24 MHz) |\r
+ +------------------------------------------------------------------------------------------+\r
+ */\r
+\r
+/**\r
+ * @brief Resets the RCC clock configuration to the default reset state.\r
+ * @note The default reset state of the clock configuration is given below:\r
+ * - MSI ON and used as system clock source\r
+ * - HSI, HSE and PLL OFF\r
+ * - AHB, APB1 and APB2 prescaler set to 1.\r
+ * - CSS and MCO1 OFF\r
+ * - All interrupts disabled\r
+ * @note This function does not modify the configuration of the\r
+ * - Peripheral clocks\r
+ * - LSI, LSE and RTC clocks\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_RCC_DeInit(void)\r
+{\r
+ uint32_t tickstart;\r
+ HAL_StatusTypeDef status;\r
+\r
+ /* Set MSIClockRange, HSITRIM and MSITRIM bits to the reset values */\r
+ MODIFY_REG(RCC->ICSCR, (RCC_ICSCR_MSITRIM | RCC_ICSCR_HSITRIM | RCC_ICSCR_MSIRANGE), \\r
+ ((RCC_MSICALIBRATION_DEFAULT << RCC_ICSCR_MSITRIM_Pos) | (RCC_HSICALIBRATION_DEFAULT << RCC_ICSCR_HSITRIM_Pos) | RCC_ICSCR_MSIRANGE_5));\r
+\r
+ /* Set MSION bit */\r
+ SET_BIT(RCC->CR, RCC_CR_MSION);\r
+\r
+ /* Get Start Tick*/\r
+ tickstart = HAL_GetTick();\r
+\r
+ /* Wait till MSI is ready */\r
+ while (READ_BIT(RCC->CR, RCC_CR_MSIRDY) == 0U)\r
+ {\r
+ if ((HAL_GetTick() - tickstart) > MSI_TIMEOUT_VALUE)\r
+ {\r
+ return HAL_TIMEOUT;\r
+ }\r
+ }\r
+\r
+ /* Switch SYSCLK to MSI*/\r
+ CLEAR_BIT(RCC->CFGR, RCC_CFGR_SW);\r
+\r
+ /* Wait till MSI as SYSCLK status is ready */\r
+ while (READ_BIT(RCC->CFGR, RCC_CFGR_SWS) != 0U)\r
+ {\r
+ if ((HAL_GetTick() - tickstart) > CLOCKSWITCH_TIMEOUT_VALUE)\r
+ {\r
+ return HAL_TIMEOUT;\r
+ }\r
+ }\r
+\r
+ /* Update the SystemCoreClock global variable */\r
+ SystemCoreClock = MSI_VALUE;\r
+\r
+ /* Configure the source of time base considering new system clock settings */\r
+ status = HAL_InitTick(uwTickPrio);\r
+ if(status != HAL_OK)\r
+ {\r
+ return status;\r
+ }\r
+\r
+ /* Reset HSION, HSEON, CSSON & PLLON bits */\r
+ CLEAR_BIT(RCC->CR, RCC_CR_HSION | RCC_CR_HSEON | RCC_CR_CSSON | RCC_CR_PLLON);\r
+ /* Reset HSEBYP bit */\r
+ CLEAR_BIT(RCC->CR, RCC_CR_HSEBYP);\r
+\r
+ /* Get Start Tick*/\r
+ tickstart = HAL_GetTick();\r
+\r
+ /* Wait till PLL is not ready */\r
+ while (READ_BIT(RCC->CR, RCC_CR_PLLRDY) != 0U)\r
+ {\r
+ if ((HAL_GetTick() - tickstart) > PLL_TIMEOUT_VALUE)\r
+ {\r
+ return HAL_TIMEOUT;\r
+ }\r
+ }\r
+\r
+ /* Reset CFGR register */\r
+ CLEAR_REG(RCC->CFGR);\r
+\r
+ /* Disable all interrupts */\r
+ CLEAR_REG(RCC->CIR);\r
+\r
+ /* Clear all flags */\r
+#if defined(RCC_LSECSS_SUPPORT)\r
+ WRITE_REG(RCC->CIR, RCC_CIR_LSIRDYC | RCC_CIR_LSERDYC | RCC_CIR_HSIRDYC | RCC_CIR_HSERDYC | RCC_CIR_PLLRDYC | RCC_CIR_MSIRDYC | RCC_CIR_LSECSSC | RCC_CIR_CSSC);\r
+#else\r
+ WRITE_REG(RCC->CIR, RCC_CIR_LSIRDYC | RCC_CIR_LSERDYC | RCC_CIR_HSIRDYC | RCC_CIR_HSERDYC | RCC_CIR_PLLRDYC | RCC_CIR_MSIRDYC | RCC_CIR_CSSC);\r
+#endif\r
+\r
+ /* Clear all reset flags */\r
+ SET_BIT(RCC->CSR, RCC_CSR_RMVF);\r
+\r
+ return HAL_OK;\r
+}\r
+\r
+/**\r
+ * @brief Initializes the RCC Oscillators according to the specified parameters in the\r
+ * RCC_OscInitTypeDef.\r
+ * @param RCC_OscInitStruct pointer to an RCC_OscInitTypeDef structure that\r
+ * contains the configuration information for the RCC Oscillators.\r
+ * @note The PLL is not disabled when used as system clock.\r
+ * @note Transitions LSE Bypass to LSE On and LSE On to LSE Bypass are not\r
+ * supported by this macro. User should request a transition to LSE Off\r
+ * first and then LSE On or LSE Bypass.\r
+ * @note Transition HSE Bypass to HSE On and HSE On to HSE Bypass are not\r
+ * supported by this macro. User should request a transition to HSE Off\r
+ * first and then HSE On or HSE Bypass.\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct)\r
+{\r
+ uint32_t tickstart;\r
+ HAL_StatusTypeDef status;\r
+ uint32_t sysclk_source, pll_config;\r
+\r
+ /* Check the parameters */\r
+ if(RCC_OscInitStruct == NULL)\r
+ {\r
+ return HAL_ERROR;\r
+ }\r
+\r
+ assert_param(IS_RCC_OSCILLATORTYPE(RCC_OscInitStruct->OscillatorType));\r
+\r
+ sysclk_source = __HAL_RCC_GET_SYSCLK_SOURCE();\r
+ pll_config = __HAL_RCC_GET_PLL_OSCSOURCE();\r
+\r
+ /*------------------------------- HSE Configuration ------------------------*/\r
+ if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_HSE) == RCC_OSCILLATORTYPE_HSE)\r
+ {\r
+ /* Check the parameters */\r
+ assert_param(IS_RCC_HSE(RCC_OscInitStruct->HSEState));\r
+\r
+ /* When the HSE is used as system clock or clock source for PLL in these cases it is not allowed to be disabled */\r
+ if((sysclk_source == RCC_SYSCLKSOURCE_STATUS_HSE)\r
+ || ((sysclk_source == RCC_SYSCLKSOURCE_STATUS_PLLCLK) && (pll_config == RCC_PLLSOURCE_HSE)))\r
+ {\r
+ if((__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != 0U) && (RCC_OscInitStruct->HSEState == RCC_HSE_OFF))\r
+ {\r
+ return HAL_ERROR;\r
+ }\r
+ }\r
+ else\r
+ {\r
+ /* Set the new HSE configuration ---------------------------------------*/\r
+ __HAL_RCC_HSE_CONFIG(RCC_OscInitStruct->HSEState);\r
+\r
+ /* Check the HSE State */\r
+ if(RCC_OscInitStruct->HSEState != RCC_HSE_OFF)\r
+ {\r
+ /* Get Start Tick */\r
+ tickstart = HAL_GetTick();\r
+\r
+ /* Wait till HSE is ready */\r
+ while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) == 0U)\r
+ {\r
+ if((HAL_GetTick() - tickstart ) > HSE_TIMEOUT_VALUE)\r
+ {\r
+ return HAL_TIMEOUT;\r
+ }\r
+ }\r
+ }\r
+ else\r
+ {\r
+ /* Get Start Tick */\r
+ tickstart = HAL_GetTick();\r
+\r
+ /* Wait till HSE is disabled */\r
+ while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != 0U)\r
+ {\r
+ if((HAL_GetTick() - tickstart ) > HSE_TIMEOUT_VALUE)\r
+ {\r
+ return HAL_TIMEOUT;\r
+ }\r
+ }\r
+ }\r
+ }\r
+ }\r
+ /*----------------------------- HSI Configuration --------------------------*/\r
+ if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_HSI) == RCC_OSCILLATORTYPE_HSI)\r
+ {\r
+ /* Check the parameters */\r
+ assert_param(IS_RCC_HSI(RCC_OscInitStruct->HSIState));\r
+ assert_param(IS_RCC_CALIBRATION_VALUE(RCC_OscInitStruct->HSICalibrationValue));\r
+\r
+ /* Check if HSI is used as system clock or as PLL source when PLL is selected as system clock */\r
+ if((sysclk_source == RCC_SYSCLKSOURCE_STATUS_HSI)\r
+ || ((sysclk_source == RCC_SYSCLKSOURCE_STATUS_PLLCLK) && (pll_config == RCC_PLLSOURCE_HSI)))\r
+ {\r
+ /* When HSI is used as system clock it will not disabled */\r
+ if((__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != 0U) && (RCC_OscInitStruct->HSIState != RCC_HSI_ON))\r
+ {\r
+ return HAL_ERROR;\r
+ }\r
+ /* Otherwise, just the calibration is allowed */\r
+ else\r
+ {\r
+ /* Adjusts the Internal High Speed oscillator (HSI) calibration value.*/\r
+ __HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->HSICalibrationValue);\r
+ }\r
+ }\r
+ else\r
+ {\r
+ /* Check the HSI State */\r
+ if(RCC_OscInitStruct->HSIState != RCC_HSI_OFF)\r
+ {\r
+ /* Enable the Internal High Speed oscillator (HSI). */\r
+ __HAL_RCC_HSI_ENABLE();\r
+\r
+ /* Get Start Tick */\r
+ tickstart = HAL_GetTick();\r
+\r
+ /* Wait till HSI is ready */\r
+ while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) == 0U)\r
+ {\r
+ if((HAL_GetTick() - tickstart ) > HSI_TIMEOUT_VALUE)\r
+ {\r
+ return HAL_TIMEOUT;\r
+ }\r
+ }\r
+\r
+ /* Adjusts the Internal High Speed oscillator (HSI) calibration value.*/\r
+ __HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->HSICalibrationValue);\r
+ }\r
+ else\r
+ {\r
+ /* Disable the Internal High Speed oscillator (HSI). */\r
+ __HAL_RCC_HSI_DISABLE();\r
+\r
+ /* Get Start Tick */\r
+ tickstart = HAL_GetTick();\r
+\r
+ /* Wait till HSI is disabled */\r
+ while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != 0U)\r
+ {\r
+ if((HAL_GetTick() - tickstart ) > HSI_TIMEOUT_VALUE)\r
+ {\r
+ return HAL_TIMEOUT;\r
+ }\r
+ }\r
+ }\r
+ }\r
+ }\r
+ /*----------------------------- MSI Configuration --------------------------*/\r
+ if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_MSI) == RCC_OSCILLATORTYPE_MSI)\r
+ {\r
+ /* When the MSI is used as system clock it will not be disabled */\r
+ if((sysclk_source == RCC_CFGR_SWS_MSI) )\r
+ {\r
+ if((__HAL_RCC_GET_FLAG(RCC_FLAG_MSIRDY) != 0U) && (RCC_OscInitStruct->MSIState == RCC_MSI_OFF))\r
+ {\r
+ return HAL_ERROR;\r
+ }\r
+ /* Otherwise, just the calibration and MSI range change are allowed */\r
+ else\r
+ {\r
+ /* Check MSICalibrationValue and MSIClockRange input parameters */\r
+ assert_param(IS_RCC_MSICALIBRATION_VALUE(RCC_OscInitStruct->MSICalibrationValue));\r
+ assert_param(IS_RCC_MSI_CLOCK_RANGE(RCC_OscInitStruct->MSIClockRange));\r
+\r
+ /* To correctly read data from FLASH memory, the number of wait states (LATENCY)\r
+ must be correctly programmed according to the frequency of the CPU clock\r
+ (HCLK) and the supply voltage of the device. */\r
+ if(RCC_OscInitStruct->MSIClockRange > __HAL_RCC_GET_MSI_RANGE())\r
+ {\r
+ /* First increase number of wait states update if necessary */\r
+ if(RCC_SetFlashLatencyFromMSIRange(RCC_OscInitStruct->MSIClockRange) != HAL_OK)\r
+ {\r
+ return HAL_ERROR;\r
+ }\r
+\r
+ /* Selects the Multiple Speed oscillator (MSI) clock range .*/\r
+ __HAL_RCC_MSI_RANGE_CONFIG(RCC_OscInitStruct->MSIClockRange);\r
+ /* Adjusts the Multiple Speed oscillator (MSI) calibration value.*/\r
+ __HAL_RCC_MSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->MSICalibrationValue);\r
+ }\r
+ else\r
+ {\r
+ /* Else, keep current flash latency while decreasing applies */\r
+ /* Selects the Multiple Speed oscillator (MSI) clock range .*/\r
+ __HAL_RCC_MSI_RANGE_CONFIG(RCC_OscInitStruct->MSIClockRange);\r
+ /* Adjusts the Multiple Speed oscillator (MSI) calibration value.*/\r
+ __HAL_RCC_MSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->MSICalibrationValue);\r
+\r
+ /* Decrease number of wait states update if necessary */\r
+ if(RCC_SetFlashLatencyFromMSIRange(RCC_OscInitStruct->MSIClockRange) != HAL_OK)\r
+ {\r
+ return HAL_ERROR;\r
+ }\r
+ }\r
+\r
+ /* Update the SystemCoreClock global variable */\r
+ SystemCoreClock = (32768U * (1UL << ((RCC_OscInitStruct->MSIClockRange >> RCC_ICSCR_MSIRANGE_Pos) + 1U)))\r
+ >> AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> RCC_CFGR_HPRE_Pos)];\r
+\r
+ /* Configure the source of time base considering new system clocks settings*/\r
+ status = HAL_InitTick(uwTickPrio);\r
+ if(status != HAL_OK)\r
+ {\r
+ return status;\r
+ }\r
+ }\r
+ }\r
+ else\r
+ {\r
+ /* Check MSI State */\r
+ assert_param(IS_RCC_MSI(RCC_OscInitStruct->MSIState));\r
+\r
+ /* Check the MSI State */\r
+ if(RCC_OscInitStruct->MSIState != RCC_MSI_OFF)\r
+ {\r
+ /* Enable the Multi Speed oscillator (MSI). */\r
+ __HAL_RCC_MSI_ENABLE();\r
+\r
+ /* Get Start Tick */\r
+ tickstart = HAL_GetTick();\r
+\r
+ /* Wait till MSI is ready */\r
+ while(__HAL_RCC_GET_FLAG(RCC_FLAG_MSIRDY) == 0U)\r
+ {\r
+ if((HAL_GetTick() - tickstart) > MSI_TIMEOUT_VALUE)\r
+ {\r
+ return HAL_TIMEOUT;\r
+ }\r
+ }\r
+ /* Check MSICalibrationValue and MSIClockRange input parameters */\r
+ assert_param(IS_RCC_MSICALIBRATION_VALUE(RCC_OscInitStruct->MSICalibrationValue));\r
+ assert_param(IS_RCC_MSI_CLOCK_RANGE(RCC_OscInitStruct->MSIClockRange));\r
+\r
+ /* Selects the Multiple Speed oscillator (MSI) clock range .*/\r
+ __HAL_RCC_MSI_RANGE_CONFIG(RCC_OscInitStruct->MSIClockRange);\r
+ /* Adjusts the Multiple Speed oscillator (MSI) calibration value.*/\r
+ __HAL_RCC_MSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->MSICalibrationValue);\r
+\r
+ }\r
+ else\r
+ {\r
+ /* Disable the Multi Speed oscillator (MSI). */\r
+ __HAL_RCC_MSI_DISABLE();\r
+\r
+ /* Get Start Tick */\r
+ tickstart = HAL_GetTick();\r
+\r
+ /* Wait till MSI is ready */\r
+ while(__HAL_RCC_GET_FLAG(RCC_FLAG_MSIRDY) != 0U)\r
+ {\r
+ if((HAL_GetTick() - tickstart) > MSI_TIMEOUT_VALUE)\r
+ {\r
+ return HAL_TIMEOUT;\r
+ }\r
+ }\r
+ }\r
+ }\r
+ }\r
+ /*------------------------------ LSI Configuration -------------------------*/\r
+ if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_LSI) == RCC_OSCILLATORTYPE_LSI)\r
+ {\r
+ /* Check the parameters */\r
+ assert_param(IS_RCC_LSI(RCC_OscInitStruct->LSIState));\r
+\r
+ /* Check the LSI State */\r
+ if(RCC_OscInitStruct->LSIState != RCC_LSI_OFF)\r
+ {\r
+ /* Enable the Internal Low Speed oscillator (LSI). */\r
+ __HAL_RCC_LSI_ENABLE();\r
+\r
+ /* Get Start Tick */\r
+ tickstart = HAL_GetTick();\r
+\r
+ /* Wait till LSI is ready */\r
+ while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) == 0U)\r
+ {\r
+ if((HAL_GetTick() - tickstart ) > LSI_TIMEOUT_VALUE)\r
+ {\r
+ return HAL_TIMEOUT;\r
+ }\r
+ }\r
+ }\r
+ else\r
+ {\r
+ /* Disable the Internal Low Speed oscillator (LSI). */\r
+ __HAL_RCC_LSI_DISABLE();\r
+\r
+ /* Get Start Tick */\r
+ tickstart = HAL_GetTick();\r
+\r
+ /* Wait till LSI is disabled */\r
+ while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) != 0U)\r
+ {\r
+ if((HAL_GetTick() - tickstart ) > LSI_TIMEOUT_VALUE)\r
+ {\r
+ return HAL_TIMEOUT;\r
+ }\r
+ }\r
+ }\r
+ }\r
+ /*------------------------------ LSE Configuration -------------------------*/\r
+ if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_LSE) == RCC_OSCILLATORTYPE_LSE)\r
+ {\r
+ FlagStatus pwrclkchanged = RESET;\r
+\r
+ /* Check the parameters */\r
+ assert_param(IS_RCC_LSE(RCC_OscInitStruct->LSEState));\r
+\r
+ /* Update LSE configuration in Backup Domain control register */\r
+ /* Requires to enable write access to Backup Domain of necessary */\r
+ if(__HAL_RCC_PWR_IS_CLK_DISABLED())\r
+ {\r
+ __HAL_RCC_PWR_CLK_ENABLE();\r
+ pwrclkchanged = SET;\r
+ }\r
+\r
+ if(HAL_IS_BIT_CLR(PWR->CR, PWR_CR_DBP))\r
+ {\r
+ /* Enable write access to Backup domain */\r
+ SET_BIT(PWR->CR, PWR_CR_DBP);\r
+\r
+ /* Wait for Backup domain Write protection disable */\r
+ tickstart = HAL_GetTick();\r
+\r
+ while(HAL_IS_BIT_CLR(PWR->CR, PWR_CR_DBP))\r
+ {\r
+ if((HAL_GetTick() - tickstart) > RCC_DBP_TIMEOUT_VALUE)\r
+ {\r
+ return HAL_TIMEOUT;\r
+ }\r
+ }\r
+ }\r
+\r
+ /* Set the new LSE configuration -----------------------------------------*/\r
+ __HAL_RCC_LSE_CONFIG(RCC_OscInitStruct->LSEState);\r
+ /* Check the LSE State */\r
+ if(RCC_OscInitStruct->LSEState != RCC_LSE_OFF)\r
+ {\r
+ /* Get Start Tick */\r
+ tickstart = HAL_GetTick();\r
+\r
+ /* Wait till LSE is ready */\r
+ while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) == 0U)\r
+ {\r
+ if((HAL_GetTick() - tickstart ) > RCC_LSE_TIMEOUT_VALUE)\r
+ {\r
+ return HAL_TIMEOUT;\r
+ }\r
+ }\r
+ }\r
+ else\r
+ {\r
+ /* Get Start Tick */\r
+ tickstart = HAL_GetTick();\r
+\r
+ /* Wait till LSE is disabled */\r
+ while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) != 0U)\r
+ {\r
+ if((HAL_GetTick() - tickstart ) > RCC_LSE_TIMEOUT_VALUE)\r
+ {\r
+ return HAL_TIMEOUT;\r
+ }\r
+ }\r
+ }\r
+\r
+ /* Require to disable power clock if necessary */\r
+ if(pwrclkchanged == SET)\r
+ {\r
+ __HAL_RCC_PWR_CLK_DISABLE();\r
+ }\r
+ }\r
+\r
+ /*-------------------------------- PLL Configuration -----------------------*/\r
+ /* Check the parameters */\r
+ assert_param(IS_RCC_PLL(RCC_OscInitStruct->PLL.PLLState));\r
+ if ((RCC_OscInitStruct->PLL.PLLState) != RCC_PLL_NONE)\r
+ {\r
+ /* Check if the PLL is used as system clock or not */\r
+ if(sysclk_source != RCC_SYSCLKSOURCE_STATUS_PLLCLK)\r
+ {\r
+ if((RCC_OscInitStruct->PLL.PLLState) == RCC_PLL_ON)\r
+ {\r
+ /* Check the parameters */\r
+ assert_param(IS_RCC_PLLSOURCE(RCC_OscInitStruct->PLL.PLLSource));\r
+ assert_param(IS_RCC_PLL_MUL(RCC_OscInitStruct->PLL.PLLMUL));\r
+ assert_param(IS_RCC_PLL_DIV(RCC_OscInitStruct->PLL.PLLDIV));\r
+\r
+ /* Disable the main PLL. */\r
+ __HAL_RCC_PLL_DISABLE();\r
+\r
+ /* Get Start Tick */\r
+ tickstart = HAL_GetTick();\r
+\r
+ /* Wait till PLL is disabled */\r
+ while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) != 0U)\r
+ {\r
+ if((HAL_GetTick() - tickstart ) > PLL_TIMEOUT_VALUE)\r
+ {\r
+ return HAL_TIMEOUT;\r
+ }\r
+ }\r
+\r
+ /* Configure the main PLL clock source, multiplication and division factors. */\r
+ __HAL_RCC_PLL_CONFIG(RCC_OscInitStruct->PLL.PLLSource,\r
+ RCC_OscInitStruct->PLL.PLLMUL,\r
+ RCC_OscInitStruct->PLL.PLLDIV);\r
+ /* Enable the main PLL. */\r
+ __HAL_RCC_PLL_ENABLE();\r
+\r
+ /* Get Start Tick */\r
+ tickstart = HAL_GetTick();\r
+\r
+ /* Wait till PLL is ready */\r
+ while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) == 0U)\r
+ {\r
+ if((HAL_GetTick() - tickstart ) > PLL_TIMEOUT_VALUE)\r
+ {\r
+ return HAL_TIMEOUT;\r
+ }\r
+ }\r
+ }\r
+ else\r
+ {\r
+ /* Disable the main PLL. */\r
+ __HAL_RCC_PLL_DISABLE();\r
+\r
+ /* Get Start Tick */\r
+ tickstart = HAL_GetTick();\r
+\r
+ /* Wait till PLL is disabled */\r
+ while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) != 0U)\r
+ {\r
+ if((HAL_GetTick() - tickstart ) > PLL_TIMEOUT_VALUE)\r
+ {\r
+ return HAL_TIMEOUT;\r
+ }\r
+ }\r
+ }\r
+ }\r
+ else\r
+ {\r
+ /* Check if there is a request to disable the PLL used as System clock source */\r
+ if((RCC_OscInitStruct->PLL.PLLState) == RCC_PLL_OFF)\r
+ {\r
+ return HAL_ERROR;\r
+ }\r
+ else\r
+ {\r
+ /* Do not return HAL_ERROR if request repeats the current configuration */\r
+ pll_config = RCC->CFGR;\r
+ if((READ_BIT(pll_config, RCC_CFGR_PLLSRC) != RCC_OscInitStruct->PLL.PLLSource) ||\r
+ (READ_BIT(pll_config, RCC_CFGR_PLLMUL) != RCC_OscInitStruct->PLL.PLLMUL) ||\r
+ (READ_BIT(pll_config, RCC_CFGR_PLLDIV) != RCC_OscInitStruct->PLL.PLLDIV))\r
+ {\r
+ return HAL_ERROR;\r
+ }\r
+ }\r
+ }\r
+ }\r
+\r
+ return HAL_OK;\r
+}\r
+\r
+/**\r
+ * @brief Initializes the CPU, AHB and APB buses clocks according to the specified\r
+ * parameters in the RCC_ClkInitStruct.\r
+ * @param RCC_ClkInitStruct pointer to an RCC_OscInitTypeDef structure that\r
+ * contains the configuration information for the RCC peripheral.\r
+ * @param FLatency FLASH Latency\r
+ * The value of this parameter depend on device used within the same series\r
+ * @note The SystemCoreClock CMSIS variable is used to store System Clock Frequency\r
+ * and updated by @ref HAL_RCC_GetHCLKFreq() function called within this function\r
+ *\r
+ * @note The MSI is used (enabled by hardware) as system clock source after\r
+ * start-up from Reset, wake-up from STOP and STANDBY mode, or in case\r
+ * of failure of the HSE used directly or indirectly as system clock\r
+ * (if the Clock Security System CSS is enabled).\r
+ *\r
+ * @note A switch from one clock source to another occurs only if the target\r
+ * clock source is ready (clock stable after start-up delay or PLL locked).\r
+ * If a clock source which is not yet ready is selected, the switch will\r
+ * occur when the clock source will be ready.\r
+ * You can use @ref HAL_RCC_GetClockConfig() function to know which clock is\r
+ * currently used as system clock source.\r
+ * @note Depending on the device voltage range, the software has to set correctly\r
+ * HPRE[3:0] bits to ensure that HCLK not exceed the maximum allowed frequency\r
+ * (for more details refer to section above "Initialization/de-initialization functions")\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_RCC_ClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, uint32_t FLatency)\r
+{\r
+ uint32_t tickstart;\r
+ HAL_StatusTypeDef status;\r
+\r
+ /* Check the parameters */\r
+ if(RCC_ClkInitStruct == NULL)\r
+ {\r
+ return HAL_ERROR;\r
+ }\r
+\r
+ assert_param(IS_FLASH_LATENCY(FLatency));\r
+\r
+ /* To correctly read data from FLASH memory, the number of wait states (LATENCY)\r
+ must be correctly programmed according to the frequency of the CPU clock\r
+ (HCLK) and the supply voltage of the device. */\r
+\r
+ /* Increasing the number of wait states because of higher CPU frequency */\r
+ if(FLatency > __HAL_FLASH_GET_LATENCY())\r
+ {\r
+ /* Program the new number of wait states to the LATENCY bits in the FLASH_ACR register */\r
+ __HAL_FLASH_SET_LATENCY(FLatency);\r
+\r
+ /* Check that the new number of wait states is taken into account to access the Flash\r
+ memory by reading the FLASH_ACR register */\r
+ if(__HAL_FLASH_GET_LATENCY() != FLatency)\r
+ {\r
+ return HAL_ERROR;\r
+ }\r
+ }\r
+\r
+ /*-------------------------- HCLK Configuration --------------------------*/\r
+ if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_HCLK) == RCC_CLOCKTYPE_HCLK)\r
+ {\r
+ assert_param(IS_RCC_HCLK(RCC_ClkInitStruct->AHBCLKDivider));\r
+ MODIFY_REG(RCC->CFGR, RCC_CFGR_HPRE, RCC_ClkInitStruct->AHBCLKDivider);\r
+ }\r
+\r
+ /*------------------------- SYSCLK Configuration ---------------------------*/\r
+ if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_SYSCLK) == RCC_CLOCKTYPE_SYSCLK)\r
+ {\r
+ assert_param(IS_RCC_SYSCLKSOURCE(RCC_ClkInitStruct->SYSCLKSource));\r
+\r
+ /* HSE is selected as System Clock Source */\r
+ if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_HSE)\r
+ {\r
+ /* Check the HSE ready flag */\r
+ if(__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) == 0U)\r
+ {\r
+ return HAL_ERROR;\r
+ }\r
+ }\r
+ /* PLL is selected as System Clock Source */\r
+ else if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_PLLCLK)\r
+ {\r
+ /* Check the PLL ready flag */\r
+ if(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) == 0U)\r
+ {\r
+ return HAL_ERROR;\r
+ }\r
+ }\r
+ /* HSI is selected as System Clock Source */\r
+ else if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_HSI)\r
+ {\r
+ /* Check the HSI ready flag */\r
+ if(__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) == 0U)\r
+ {\r
+ return HAL_ERROR;\r
+ }\r
+ }\r
+ /* MSI is selected as System Clock Source */\r
+ else\r
+ {\r
+ /* Check the MSI ready flag */\r
+ if(__HAL_RCC_GET_FLAG(RCC_FLAG_MSIRDY) == 0U)\r
+ {\r
+ return HAL_ERROR;\r
+ }\r
+ }\r
+ __HAL_RCC_SYSCLK_CONFIG(RCC_ClkInitStruct->SYSCLKSource);\r
+\r
+ /* Get Start Tick */\r
+ tickstart = HAL_GetTick();\r
+\r
+ if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_HSE)\r
+ {\r
+ while (__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_SYSCLKSOURCE_STATUS_HSE)\r
+ {\r
+ if((HAL_GetTick() - tickstart ) > CLOCKSWITCH_TIMEOUT_VALUE)\r
+ {\r
+ return HAL_TIMEOUT;\r
+ }\r
+ }\r
+ }\r
+ else if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_PLLCLK)\r
+ {\r
+ while (__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_SYSCLKSOURCE_STATUS_PLLCLK)\r
+ {\r
+ if((HAL_GetTick() - tickstart ) > CLOCKSWITCH_TIMEOUT_VALUE)\r
+ {\r
+ return HAL_TIMEOUT;\r
+ }\r
+ }\r
+ }\r
+ else if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_HSI)\r
+ {\r
+ while (__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_SYSCLKSOURCE_STATUS_HSI)\r
+ {\r
+ if((HAL_GetTick() - tickstart ) > CLOCKSWITCH_TIMEOUT_VALUE)\r
+ {\r
+ return HAL_TIMEOUT;\r
+ }\r
+ }\r
+ }\r
+ else\r
+ {\r
+ while(__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_SYSCLKSOURCE_STATUS_MSI)\r
+ {\r
+ if((HAL_GetTick() - tickstart ) > CLOCKSWITCH_TIMEOUT_VALUE)\r
+ {\r
+ return HAL_TIMEOUT;\r
+ }\r
+ }\r
+ }\r
+ }\r
+ /* Decreasing the number of wait states because of lower CPU frequency */\r
+ if(FLatency < __HAL_FLASH_GET_LATENCY())\r
+ {\r
+ /* Program the new number of wait states to the LATENCY bits in the FLASH_ACR register */\r
+ __HAL_FLASH_SET_LATENCY(FLatency);\r
+\r
+ /* Check that the new number of wait states is taken into account to access the Flash\r
+ memory by reading the FLASH_ACR register */\r
+ if(__HAL_FLASH_GET_LATENCY() != FLatency)\r
+ {\r
+ return HAL_ERROR;\r
+ }\r
+ }\r
+\r
+ /*-------------------------- PCLK1 Configuration ---------------------------*/\r
+ if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK1) == RCC_CLOCKTYPE_PCLK1)\r
+ {\r
+ assert_param(IS_RCC_PCLK(RCC_ClkInitStruct->APB1CLKDivider));\r
+ MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE1, RCC_ClkInitStruct->APB1CLKDivider);\r
+ }\r
+\r
+ /*-------------------------- PCLK2 Configuration ---------------------------*/\r
+ if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK2) == RCC_CLOCKTYPE_PCLK2)\r
+ {\r
+ assert_param(IS_RCC_PCLK(RCC_ClkInitStruct->APB2CLKDivider));\r
+ MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE2, ((RCC_ClkInitStruct->APB2CLKDivider) << 3U));\r
+ }\r
+\r
+ /* Update the SystemCoreClock global variable */\r
+ SystemCoreClock = HAL_RCC_GetSysClockFreq() >> AHBPrescTable[(RCC->CFGR & RCC_CFGR_HPRE)>> RCC_CFGR_HPRE_Pos];\r
+\r
+ /* Configure the source of time base considering new system clocks settings*/\r
+ status = HAL_InitTick(uwTickPrio);\r
+\r
+ return status;\r
+}\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup RCC_Exported_Functions_Group2 Peripheral Control functions\r
+ * @brief RCC clocks control functions\r
+ *\r
+ @verbatim\r
+ ===============================================================================\r
+ ##### Peripheral Control functions #####\r
+ ===============================================================================\r
+ [..]\r
+ This subsection provides a set of functions allowing to control the RCC Clocks\r
+ frequencies.\r
+\r
+ @endverbatim\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @brief Selects the clock source to output on MCO pin.\r
+ * @note MCO pin should be configured in alternate function mode.\r
+ * @param RCC_MCOx specifies the output direction for the clock source.\r
+ * This parameter can be one of the following values:\r
+ * @arg @ref RCC_MCO1 Clock source to output on MCO1 pin(PA8).\r
+ * @param RCC_MCOSource specifies the clock source to output.\r
+ * This parameter can be one of the following values:\r
+ * @arg @ref RCC_MCO1SOURCE_NOCLOCK No clock selected as MCO clock\r
+ * @arg @ref RCC_MCO1SOURCE_SYSCLK System clock selected as MCO clock\r
+ * @arg @ref RCC_MCO1SOURCE_HSI HSI selected as MCO clock\r
+ * @arg @ref RCC_MCO1SOURCE_HSE HSE selected as MCO clock\r
+ * @arg @ref RCC_MCO1SOURCE_MSI MSI oscillator clock selected as MCO clock\r
+ * @arg @ref RCC_MCO1SOURCE_PLLCLK PLL clock selected as MCO clock\r
+ * @arg @ref RCC_MCO1SOURCE_LSI LSI clock selected as MCO clock\r
+ * @arg @ref RCC_MCO1SOURCE_LSE LSE clock selected as MCO clock\r
+ * @param RCC_MCODiv specifies the MCO DIV.\r
+ * This parameter can be one of the following values:\r
+ * @arg @ref RCC_MCODIV_1 no division applied to MCO clock\r
+ * @arg @ref RCC_MCODIV_2 division by 2 applied to MCO clock\r
+ * @arg @ref RCC_MCODIV_4 division by 4 applied to MCO clock\r
+ * @arg @ref RCC_MCODIV_8 division by 8 applied to MCO clock\r
+ * @arg @ref RCC_MCODIV_16 division by 16 applied to MCO clock\r
+ * @retval None\r
+ */\r
+void HAL_RCC_MCOConfig(uint32_t RCC_MCOx, uint32_t RCC_MCOSource, uint32_t RCC_MCODiv)\r
+{\r
+ GPIO_InitTypeDef gpio;\r
+\r
+ /* Check the parameters */\r
+ assert_param(IS_RCC_MCO(RCC_MCOx));\r
+ assert_param(IS_RCC_MCODIV(RCC_MCODiv));\r
+ assert_param(IS_RCC_MCO1SOURCE(RCC_MCOSource));\r
+\r
+ /* Configure the MCO1 pin in alternate function mode */\r
+ gpio.Mode = GPIO_MODE_AF_PP;\r
+ gpio.Speed = GPIO_SPEED_FREQ_HIGH;\r
+ gpio.Pull = GPIO_NOPULL;\r
+ gpio.Pin = MCO1_PIN;\r
+ gpio.Alternate = GPIO_AF0_MCO;\r
+\r
+ /* MCO1 Clock Enable */\r
+ MCO1_CLK_ENABLE();\r
+\r
+ HAL_GPIO_Init(MCO1_GPIO_PORT, &gpio);\r
+\r
+ /* Configure the MCO clock source */\r
+ __HAL_RCC_MCO1_CONFIG(RCC_MCOSource, RCC_MCODiv);\r
+}\r
+\r
+/**\r
+ * @brief Enables the Clock Security System.\r
+ * @note If a failure is detected on the HSE oscillator clock, this oscillator\r
+ * is automatically disabled and an interrupt is generated to inform the\r
+ * software about the failure (Clock Security System Interrupt, CSSI),\r
+ * allowing the MCU to perform rescue operations. The CSSI is linked to\r
+ * the Cortex-M3 NMI (Non-Maskable Interrupt) exception vector.\r
+ * @retval None\r
+ */\r
+void HAL_RCC_EnableCSS(void)\r
+{\r
+ *(__IO uint32_t *) RCC_CR_CSSON_BB = (uint32_t)ENABLE;\r
+}\r
+\r
+/**\r
+ * @brief Disables the Clock Security System.\r
+ * @retval None\r
+ */\r
+void HAL_RCC_DisableCSS(void)\r
+{\r
+ *(__IO uint32_t *) RCC_CR_CSSON_BB = (uint32_t)DISABLE;\r
+}\r
+\r
+/**\r
+ * @brief Returns the SYSCLK frequency\r
+ * @note The system frequency computed by this function is not the real\r
+ * frequency in the chip. It is calculated based on the predefined\r
+ * constant and the selected clock source:\r
+ * @note If SYSCLK source is MSI, function returns a value based on MSI\r
+ * Value as defined by the MSI range.\r
+ * @note If SYSCLK source is HSI, function returns values based on HSI_VALUE(*)\r
+ * @note If SYSCLK source is HSE, function returns a value based on HSE_VALUE(**)\r
+ * @note If SYSCLK source is PLL, function returns a value based on HSE_VALUE(**)\r
+ * or HSI_VALUE(*) multiplied/divided by the PLL factors.\r
+ * @note (*) HSI_VALUE is a constant defined in stm32l1xx_hal_conf.h file (default value\r
+ * 16 MHz) but the real value may vary depending on the variations\r
+ * in voltage and temperature.\r
+ * @note (**) HSE_VALUE is a constant defined in stm32l1xx_hal_conf.h file (default value\r
+ * 8 MHz), user has to ensure that HSE_VALUE is same as the real\r
+ * frequency of the crystal used. Otherwise, this function may\r
+ * have wrong result.\r
+ *\r
+ * @note The result of this function could be not correct when using fractional\r
+ * value for HSE crystal.\r
+ *\r
+ * @note This function can be used by the user application to compute the\r
+ * baud-rate for the communication peripherals or configure other parameters.\r
+ *\r
+ * @note Each time SYSCLK changes, this function must be called to update the\r
+ * right SYSCLK value. Otherwise, any configuration based on this function will be incorrect.\r
+ *\r
+ * @retval SYSCLK frequency\r
+ */\r
+uint32_t HAL_RCC_GetSysClockFreq(void)\r
+{\r
+ uint32_t tmpreg, pllm, plld, pllvco, msiclkrange, sysclockfreq;\r
+\r
+ tmpreg = RCC->CFGR;\r
+\r
+ /* Get SYSCLK source -------------------------------------------------------*/\r
+ switch (tmpreg & RCC_CFGR_SWS)\r
+ {\r
+ case RCC_SYSCLKSOURCE_STATUS_HSI: /* HSI used as system clock source */\r
+ {\r
+ sysclockfreq = HSI_VALUE;\r
+ break;\r
+ }\r
+ case RCC_SYSCLKSOURCE_STATUS_HSE: /* HSE used as system clock */\r
+ {\r
+ sysclockfreq = HSE_VALUE;\r
+ break;\r
+ }\r
+ case RCC_SYSCLKSOURCE_STATUS_PLLCLK: /* PLL used as system clock */\r
+ {\r
+ pllm = PLLMulTable[(uint32_t)(tmpreg & RCC_CFGR_PLLMUL) >> RCC_CFGR_PLLMUL_Pos];\r
+ plld = ((uint32_t)(tmpreg & RCC_CFGR_PLLDIV) >> RCC_CFGR_PLLDIV_Pos) + 1U;\r
+ if (__HAL_RCC_GET_PLL_OSCSOURCE() != RCC_PLLSOURCE_HSI)\r
+ {\r
+ /* HSE used as PLL clock source */\r
+ pllvco = (HSE_VALUE * pllm) / plld;\r
+ }\r
+ else\r
+ {\r
+ /* HSI used as PLL clock source */\r
+ pllvco = (HSI_VALUE * pllm) / plld;\r
+ }\r
+ sysclockfreq = pllvco;\r
+ break;\r
+ }\r
+ case RCC_SYSCLKSOURCE_STATUS_MSI: /* MSI used as system clock source */\r
+ default: /* MSI used as system clock */\r
+ {\r
+ msiclkrange = (RCC->ICSCR & RCC_ICSCR_MSIRANGE ) >> RCC_ICSCR_MSIRANGE_Pos;\r
+ sysclockfreq = (32768U * (1UL << (msiclkrange + 1U)));\r
+ break;\r
+ }\r
+ }\r
+ return sysclockfreq;\r
+}\r
+\r
+/**\r
+ * @brief Returns the HCLK frequency\r
+ * @note Each time HCLK changes, this function must be called to update the\r
+ * right HCLK value. Otherwise, any configuration based on this function will be incorrect.\r
+ *\r
+ * @note The SystemCoreClock CMSIS variable is used to store System Clock Frequency\r
+ * and updated within this function\r
+ * @retval HCLK frequency\r
+ */\r
+uint32_t HAL_RCC_GetHCLKFreq(void)\r
+{\r
+ return SystemCoreClock;\r
+}\r
+\r
+/**\r
+ * @brief Returns the PCLK1 frequency\r
+ * @note Each time PCLK1 changes, this function must be called to update the\r
+ * right PCLK1 value. Otherwise, any configuration based on this function will be incorrect.\r
+ * @retval PCLK1 frequency\r
+ */\r
+uint32_t HAL_RCC_GetPCLK1Freq(void)\r
+{\r
+ /* Get HCLK source and Compute PCLK1 frequency ---------------------------*/\r
+ return (HAL_RCC_GetHCLKFreq() >> APBPrescTable[(RCC->CFGR & RCC_CFGR_PPRE1) >> RCC_CFGR_PPRE1_Pos]);\r
+}\r
+\r
+/**\r
+ * @brief Returns the PCLK2 frequency\r
+ * @note Each time PCLK2 changes, this function must be called to update the\r
+ * right PCLK2 value. Otherwise, any configuration based on this function will be incorrect.\r
+ * @retval PCLK2 frequency\r
+ */\r
+uint32_t HAL_RCC_GetPCLK2Freq(void)\r
+{\r
+ /* Get HCLK source and Compute PCLK2 frequency ---------------------------*/\r
+ return (HAL_RCC_GetHCLKFreq()>> APBPrescTable[(RCC->CFGR & RCC_CFGR_PPRE2) >> RCC_CFGR_PPRE2_Pos]);\r
+}\r
+\r
+/**\r
+ * @brief Configures the RCC_OscInitStruct according to the internal\r
+ * RCC configuration registers.\r
+ * @param RCC_OscInitStruct pointer to an RCC_OscInitTypeDef structure that\r
+ * will be configured.\r
+ * @retval None\r
+ */\r
+void HAL_RCC_GetOscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(RCC_OscInitStruct != (void *)NULL);\r
+\r
+ /* Set all possible values for the Oscillator type parameter ---------------*/\r
+ RCC_OscInitStruct->OscillatorType = RCC_OSCILLATORTYPE_HSE | RCC_OSCILLATORTYPE_HSI \\r
+ | RCC_OSCILLATORTYPE_LSE | RCC_OSCILLATORTYPE_LSI | RCC_OSCILLATORTYPE_MSI;\r
+\r
+\r
+ /* Get the HSE configuration -----------------------------------------------*/\r
+ if((RCC->CR &RCC_CR_HSEBYP) == RCC_CR_HSEBYP)\r
+ {\r
+ RCC_OscInitStruct->HSEState = RCC_HSE_BYPASS;\r
+ }\r
+ else if((RCC->CR &RCC_CR_HSEON) == RCC_CR_HSEON)\r
+ {\r
+ RCC_OscInitStruct->HSEState = RCC_HSE_ON;\r
+ }\r
+ else\r
+ {\r
+ RCC_OscInitStruct->HSEState = RCC_HSE_OFF;\r
+ }\r
+\r
+ /* Get the HSI configuration -----------------------------------------------*/\r
+ if((RCC->CR &RCC_CR_HSION) == RCC_CR_HSION)\r
+ {\r
+ RCC_OscInitStruct->HSIState = RCC_HSI_ON;\r
+ }\r
+ else\r
+ {\r
+ RCC_OscInitStruct->HSIState = RCC_HSI_OFF;\r
+ }\r
+\r
+ RCC_OscInitStruct->HSICalibrationValue = (uint32_t)((RCC->ICSCR & RCC_ICSCR_HSITRIM) >> RCC_ICSCR_HSITRIM_Pos);\r
+\r
+ /* Get the MSI configuration -----------------------------------------------*/\r
+ if((RCC->CR &RCC_CR_MSION) == RCC_CR_MSION)\r
+ {\r
+ RCC_OscInitStruct->MSIState = RCC_MSI_ON;\r
+ }\r
+ else\r
+ {\r
+ RCC_OscInitStruct->MSIState = RCC_MSI_OFF;\r
+ }\r
+\r
+ RCC_OscInitStruct->MSICalibrationValue = (uint32_t)((RCC->ICSCR & RCC_ICSCR_MSITRIM) >> RCC_ICSCR_MSITRIM_Pos);\r
+ RCC_OscInitStruct->MSIClockRange = (uint32_t)((RCC->ICSCR & RCC_ICSCR_MSIRANGE));\r
+\r
+ /* Get the LSE configuration -----------------------------------------------*/\r
+ if((RCC->CSR &RCC_CSR_LSEBYP) == RCC_CSR_LSEBYP)\r
+ {\r
+ RCC_OscInitStruct->LSEState = RCC_LSE_BYPASS;\r
+ }\r
+ else if((RCC->CSR &RCC_CSR_LSEON) == RCC_CSR_LSEON)\r
+ {\r
+ RCC_OscInitStruct->LSEState = RCC_LSE_ON;\r
+ }\r
+ else\r
+ {\r
+ RCC_OscInitStruct->LSEState = RCC_LSE_OFF;\r
+ }\r
+\r
+ /* Get the LSI configuration -----------------------------------------------*/\r
+ if((RCC->CSR &RCC_CSR_LSION) == RCC_CSR_LSION)\r
+ {\r
+ RCC_OscInitStruct->LSIState = RCC_LSI_ON;\r
+ }\r
+ else\r
+ {\r
+ RCC_OscInitStruct->LSIState = RCC_LSI_OFF;\r
+ }\r
+\r
+\r
+ /* Get the PLL configuration -----------------------------------------------*/\r
+ if((RCC->CR &RCC_CR_PLLON) == RCC_CR_PLLON)\r
+ {\r
+ RCC_OscInitStruct->PLL.PLLState = RCC_PLL_ON;\r
+ }\r
+ else\r
+ {\r
+ RCC_OscInitStruct->PLL.PLLState = RCC_PLL_OFF;\r
+ }\r
+ RCC_OscInitStruct->PLL.PLLSource = (uint32_t)(RCC->CFGR & RCC_CFGR_PLLSRC);\r
+ RCC_OscInitStruct->PLL.PLLMUL = (uint32_t)(RCC->CFGR & RCC_CFGR_PLLMUL);\r
+ RCC_OscInitStruct->PLL.PLLDIV = (uint32_t)(RCC->CFGR & RCC_CFGR_PLLDIV);\r
+}\r
+\r
+/**\r
+ * @brief Get the RCC_ClkInitStruct according to the internal\r
+ * RCC configuration registers.\r
+ * @param RCC_ClkInitStruct pointer to an RCC_ClkInitTypeDef structure that\r
+ * contains the current clock configuration.\r
+ * @param pFLatency Pointer on the Flash Latency.\r
+ * @retval None\r
+ */\r
+void HAL_RCC_GetClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, uint32_t *pFLatency)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(RCC_ClkInitStruct != (void *)NULL);\r
+ assert_param(pFLatency != (void *)NULL);\r
+\r
+ /* Set all possible values for the Clock type parameter --------------------*/\r
+ RCC_ClkInitStruct->ClockType = RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2;\r
+\r
+ /* Get the SYSCLK configuration --------------------------------------------*/\r
+ RCC_ClkInitStruct->SYSCLKSource = (uint32_t)(RCC->CFGR & RCC_CFGR_SW);\r
+\r
+ /* Get the HCLK configuration ----------------------------------------------*/\r
+ RCC_ClkInitStruct->AHBCLKDivider = (uint32_t)(RCC->CFGR & RCC_CFGR_HPRE);\r
+\r
+ /* Get the APB1 configuration ----------------------------------------------*/\r
+ RCC_ClkInitStruct->APB1CLKDivider = (uint32_t)(RCC->CFGR & RCC_CFGR_PPRE1);\r
+\r
+ /* Get the APB2 configuration ----------------------------------------------*/\r
+ RCC_ClkInitStruct->APB2CLKDivider = (uint32_t)((RCC->CFGR & RCC_CFGR_PPRE2) >> 3U);\r
+\r
+ /* Get the Flash Wait State (Latency) configuration ------------------------*/\r
+ *pFLatency = __HAL_FLASH_GET_LATENCY();\r
+}\r
+\r
+/**\r
+ * @brief This function handles the RCC CSS interrupt request.\r
+ * @note This API should be called under the NMI_Handler().\r
+ * @retval None\r
+ */\r
+void HAL_RCC_NMI_IRQHandler(void)\r
+{\r
+ /* Check RCC CSSF flag */\r
+ if(__HAL_RCC_GET_IT(RCC_IT_CSS))\r
+ {\r
+ /* RCC Clock Security System interrupt user callback */\r
+ HAL_RCC_CSSCallback();\r
+\r
+ /* Clear RCC CSS pending bit */\r
+ __HAL_RCC_CLEAR_IT(RCC_IT_CSS);\r
+ }\r
+}\r
+\r
+/**\r
+ * @brief RCC Clock Security System interrupt callback\r
+ * @retval none\r
+ */\r
+__weak void HAL_RCC_CSSCallback(void)\r
+{\r
+ /* NOTE : This function Should not be modified, when the callback is needed,\r
+ the HAL_RCC_CSSCallback could be implemented in the user file\r
+ */\r
+}\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/* Private function prototypes -----------------------------------------------*/\r
+/** @addtogroup RCC_Private_Functions\r
+ * @{\r
+ */\r
+/**\r
+ * @brief Update number of Flash wait states in line with MSI range and current\r
+ voltage range\r
+ * @param MSIrange MSI range value from RCC_MSIRANGE_0 to RCC_MSIRANGE_6\r
+ * @retval HAL status\r
+ */\r
+static HAL_StatusTypeDef RCC_SetFlashLatencyFromMSIRange(uint32_t MSIrange)\r
+{\r
+ uint32_t vos;\r
+ uint32_t latency = FLASH_LATENCY_0; /* default value 0WS */\r
+\r
+ /* HCLK can reach 4 MHz only if AHB prescaler = 1 */\r
+ if (READ_BIT(RCC->CFGR, RCC_CFGR_HPRE) == RCC_SYSCLK_DIV1)\r
+ {\r
+ if(__HAL_RCC_PWR_IS_CLK_ENABLED())\r
+ {\r
+ vos = READ_BIT(PWR->CR, PWR_CR_VOS);\r
+ }\r
+ else\r
+ {\r
+ __HAL_RCC_PWR_CLK_ENABLE();\r
+ vos = READ_BIT(PWR->CR, PWR_CR_VOS);\r
+ __HAL_RCC_PWR_CLK_DISABLE();\r
+ }\r
+\r
+ /* Check if need to set latency 1 only for Range 3 & HCLK = 4MHz */\r
+ if((vos == PWR_REGULATOR_VOLTAGE_SCALE3) && (MSIrange == RCC_MSIRANGE_6))\r
+ {\r
+ latency = FLASH_LATENCY_1; /* 1WS */\r
+ }\r
+ }\r
+\r
+ __HAL_FLASH_SET_LATENCY(latency);\r
+\r
+ /* Check that the new number of wait states is taken into account to access the Flash\r
+ memory by reading the FLASH_ACR register */\r
+ if(__HAL_FLASH_GET_LATENCY() != latency)\r
+ {\r
+ return HAL_ERROR;\r
+ }\r
+\r
+ return HAL_OK;\r
+}\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+#endif /* HAL_RCC_MODULE_ENABLED */\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\r
--- /dev/null
+/**\r
+ ******************************************************************************\r
+ * @file stm32l1xx_hal_rcc_ex.c\r
+ * @author MCD Application Team\r
+ * @brief Extended RCC HAL module driver.\r
+ * This file provides firmware functions to manage the following\r
+ * functionalities RCC extension peripheral:\r
+ * + Extended Peripheral Control functions\r
+ *\r
+ ******************************************************************************\r
+ * @attention\r
+ *\r
+ * <h2><center>© Copyright(c) 2017 STMicroelectronics.\r
+ * All rights reserved.</center></h2>\r
+ *\r
+ * This software component is licensed by ST under BSD 3-Clause license,\r
+ * the "License"; You may not use this file except in compliance with the\r
+ * License. You may obtain a copy of the License at:\r
+ * opensource.org/licenses/BSD-3-Clause\r
+ *\r
+ ******************************************************************************\r
+ */\r
+\r
+/* Includes ------------------------------------------------------------------*/\r
+#include "stm32l1xx_hal.h"\r
+\r
+/** @addtogroup STM32L1xx_HAL_Driver\r
+ * @{\r
+ */\r
+\r
+#ifdef HAL_RCC_MODULE_ENABLED\r
+\r
+/** @defgroup RCCEx RCCEx\r
+ * @brief RCC Extension HAL module driver\r
+ * @{\r
+ */\r
+\r
+/* Private typedef -----------------------------------------------------------*/\r
+/* Private define ------------------------------------------------------------*/\r
+/** @defgroup RCCEx_Private_Constants RCCEx Private Constants\r
+ * @{\r
+ */\r
+/**\r
+ * @}\r
+ */\r
+\r
+/* Private macro -------------------------------------------------------------*/\r
+/** @defgroup RCCEx_Private_Macros RCCEx Private Macros\r
+ * @{\r
+ */\r
+/**\r
+ * @}\r
+ */\r
+\r
+/* Private variables ---------------------------------------------------------*/\r
+/* Private function prototypes -----------------------------------------------*/\r
+/* Private functions ---------------------------------------------------------*/\r
+\r
+/** @defgroup RCCEx_Exported_Functions RCCEx Exported Functions\r
+ * @{\r
+ */\r
+\r
+/** @defgroup RCCEx_Exported_Functions_Group1 Extended Peripheral Control functions\r
+ * @brief Extended Peripheral Control functions\r
+ *\r
+@verbatim\r
+ ===============================================================================\r
+ ##### Extended Peripheral Control functions #####\r
+ ===============================================================================\r
+ [..]\r
+ This subsection provides a set of functions allowing to control the RCC Clocks\r
+ frequencies.\r
+ [..]\r
+ (@) Important note: Care must be taken when HAL_RCCEx_PeriphCLKConfig() is used to\r
+ select the RTC clock source; in this case the Backup domain will be reset in\r
+ order to modify the RTC Clock source, as consequence RTC registers (including\r
+ the backup registers) are set to their reset values.\r
+\r
+@endverbatim\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @brief Initializes the RCC extended peripherals clocks according to the specified\r
+ * parameters in the RCC_PeriphCLKInitTypeDef.\r
+ * @param PeriphClkInit pointer to an RCC_PeriphCLKInitTypeDef structure that\r
+ * contains the configuration information for the Extended Peripherals clocks(RTC/LCD clock).\r
+ * @retval HAL status\r
+ * @note If HAL_ERROR returned, first switch-OFF HSE clock oscillator with @ref HAL_RCC_OscConfig()\r
+ * to possibly update HSE divider.\r
+ */\r
+HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit)\r
+{\r
+ uint32_t tickstart;\r
+ uint32_t temp_reg;\r
+\r
+ /* Check the parameters */\r
+ assert_param(IS_RCC_PERIPHCLOCK(PeriphClkInit->PeriphClockSelection));\r
+\r
+ /*------------------------------- RTC/LCD Configuration ------------------------*/\r
+ if ((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_RTC) == RCC_PERIPHCLK_RTC)\r
+#if defined(LCD)\r
+ || (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_LCD) == RCC_PERIPHCLK_LCD)\r
+#endif /* LCD */\r
+ )\r
+ {\r
+ /* check for RTC Parameters used to output RTCCLK */\r
+ if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_RTC) == RCC_PERIPHCLK_RTC)\r
+ {\r
+ assert_param(IS_RCC_RTCCLKSOURCE(PeriphClkInit->RTCClockSelection));\r
+ }\r
+\r
+#if defined(LCD)\r
+ if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_LCD) == RCC_PERIPHCLK_LCD)\r
+ {\r
+ assert_param(IS_RCC_RTCCLKSOURCE(PeriphClkInit->LCDClockSelection));\r
+ }\r
+#endif /* LCD */\r
+\r
+ FlagStatus pwrclkchanged = RESET;\r
+\r
+ /* As soon as function is called to change RTC clock source, activation of the\r
+ power domain is done. */\r
+ /* Requires to enable write access to Backup Domain of necessary */\r
+ if(__HAL_RCC_PWR_IS_CLK_DISABLED())\r
+ {\r
+ __HAL_RCC_PWR_CLK_ENABLE();\r
+ pwrclkchanged = SET;\r
+ }\r
+\r
+ if(HAL_IS_BIT_CLR(PWR->CR, PWR_CR_DBP))\r
+ {\r
+ /* Enable write access to Backup domain */\r
+ SET_BIT(PWR->CR, PWR_CR_DBP);\r
+\r
+ /* Wait for Backup domain Write protection disable */\r
+ tickstart = HAL_GetTick();\r
+\r
+ while(HAL_IS_BIT_CLR(PWR->CR, PWR_CR_DBP))\r
+ {\r
+ if((HAL_GetTick() - tickstart) > RCC_DBP_TIMEOUT_VALUE)\r
+ {\r
+ return HAL_TIMEOUT;\r
+ }\r
+ }\r
+ }\r
+\r
+ /* Check if user wants to change HSE RTC prescaler whereas HSE is enabled */\r
+ temp_reg = (RCC->CR & RCC_CR_RTCPRE);\r
+ if ((temp_reg != (PeriphClkInit->RTCClockSelection & RCC_CR_RTCPRE))\r
+#if defined (LCD)\r
+ || (temp_reg != (PeriphClkInit->LCDClockSelection & RCC_CR_RTCPRE))\r
+#endif /* LCD */\r
+ )\r
+ { /* Check HSE State */\r
+ if ((PeriphClkInit->RTCClockSelection & RCC_CSR_RTCSEL) == RCC_CSR_RTCSEL_HSE)\r
+ {\r
+ if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSERDY))\r
+ {\r
+ /* To update HSE divider, first switch-OFF HSE clock oscillator*/\r
+ return HAL_ERROR;\r
+ }\r
+ }\r
+ }\r
+\r
+ /* Reset the Backup domain only if the RTC Clock source selection is modified from reset value */\r
+ temp_reg = (RCC->CSR & RCC_CSR_RTCSEL);\r
+\r
+ if((temp_reg != 0x00000000U) && (((temp_reg != (PeriphClkInit->RTCClockSelection & RCC_CSR_RTCSEL)) \\r
+ && (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_RTC) == RCC_PERIPHCLK_RTC))\r
+#if defined(LCD)\r
+ || ((temp_reg != (PeriphClkInit->LCDClockSelection & RCC_CSR_RTCSEL)) \\r
+ && (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_LCD) == RCC_PERIPHCLK_LCD))\r
+#endif /* LCD */\r
+ ))\r
+ {\r
+ /* Store the content of CSR register before the reset of Backup Domain */\r
+ temp_reg = (RCC->CSR & ~(RCC_CSR_RTCSEL));\r
+\r
+ /* RTC Clock selection can be changed only if the Backup Domain is reset */\r
+ __HAL_RCC_BACKUPRESET_FORCE();\r
+ __HAL_RCC_BACKUPRESET_RELEASE();\r
+\r
+ /* Restore the Content of CSR register */\r
+ RCC->CSR = temp_reg;\r
+\r
+ /* Wait for LSERDY if LSE was enabled */\r
+ if (HAL_IS_BIT_SET(temp_reg, RCC_CSR_LSEON))\r
+ {\r
+ /* Get Start Tick */\r
+ tickstart = HAL_GetTick();\r
+\r
+ /* Wait till LSE is ready */\r
+ while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) == 0U)\r
+ {\r
+ if((HAL_GetTick() - tickstart ) > RCC_LSE_TIMEOUT_VALUE)\r
+ {\r
+ return HAL_TIMEOUT;\r
+ }\r
+ }\r
+ }\r
+ }\r
+ __HAL_RCC_RTC_CONFIG(PeriphClkInit->RTCClockSelection);\r
+\r
+ /* Require to disable power clock if necessary */\r
+ if(pwrclkchanged == SET)\r
+ {\r
+ __HAL_RCC_PWR_CLK_DISABLE();\r
+ }\r
+ }\r
+\r
+ return HAL_OK;\r
+}\r
+\r
+/**\r
+ * @brief Get the PeriphClkInit according to the internal RCC configuration registers.\r
+ * @param PeriphClkInit pointer to an RCC_PeriphCLKInitTypeDef structure that\r
+ * returns the configuration information for the Extended Peripherals clocks(RTC/LCD clocks).\r
+ * @retval None\r
+ */\r
+void HAL_RCCEx_GetPeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit)\r
+{\r
+ uint32_t srcclk;\r
+\r
+ /* Set all possible values for the extended clock type parameter------------*/\r
+ PeriphClkInit->PeriphClockSelection = RCC_PERIPHCLK_RTC;\r
+#if defined(LCD)\r
+ PeriphClkInit->PeriphClockSelection |= RCC_PERIPHCLK_LCD;\r
+#endif /* LCD */\r
+\r
+ /* Get the RTC/LCD configuration -----------------------------------------------*/\r
+ srcclk = __HAL_RCC_GET_RTC_SOURCE();\r
+ if (srcclk != RCC_RTCCLKSOURCE_HSE_DIV2)\r
+ {\r
+ /* Source clock is LSE or LSI*/\r
+ PeriphClkInit->RTCClockSelection = srcclk;\r
+ }\r
+ else\r
+ {\r
+ /* Source clock is HSE. Need to get the prescaler value*/\r
+ PeriphClkInit->RTCClockSelection = srcclk | (READ_BIT(RCC->CR, RCC_CR_RTCPRE));\r
+ }\r
+#if defined(LCD)\r
+ PeriphClkInit->LCDClockSelection = PeriphClkInit->RTCClockSelection;\r
+#endif /* LCD */\r
+}\r
+\r
+/**\r
+ * @brief Return the peripheral clock frequency\r
+ * @note Return 0 if peripheral clock is unknown\r
+ * @param PeriphClk Peripheral clock identifier\r
+ * This parameter can be one of the following values:\r
+ * @arg @ref RCC_PERIPHCLK_RTC RTC peripheral clock\r
+ * @arg @ref RCC_PERIPHCLK_LCD LCD peripheral clock (*)\r
+ * @note (*) means that this peripheral is not present on all the devices\r
+ * @retval Frequency in Hz (0: means that no available frequency for the peripheral)\r
+ */\r
+uint32_t HAL_RCCEx_GetPeriphCLKFreq(uint32_t PeriphClk)\r
+{\r
+ uint32_t frequency = 0;\r
+ uint32_t srcclk;\r
+\r
+ /* Check the parameters */\r
+ assert_param(IS_RCC_PERIPHCLOCK(PeriphClk));\r
+\r
+ switch (PeriphClk)\r
+ {\r
+ case RCC_PERIPHCLK_RTC:\r
+#if defined(LCD)\r
+ case RCC_PERIPHCLK_LCD:\r
+#endif /* LCD */\r
+ {\r
+ /* Get the current RTC source */\r
+ srcclk = __HAL_RCC_GET_RTC_SOURCE();\r
+\r
+ /* Check if LSE is ready if RTC clock selection is LSE */\r
+ if (srcclk == RCC_RTCCLKSOURCE_LSE)\r
+ {\r
+ if (HAL_IS_BIT_SET(RCC->CSR, RCC_CSR_LSERDY))\r
+ {\r
+ frequency = LSE_VALUE;\r
+ }\r
+ }\r
+ /* Check if LSI is ready if RTC clock selection is LSI */\r
+ else if (srcclk == RCC_RTCCLKSOURCE_LSI)\r
+ {\r
+ if (HAL_IS_BIT_SET(RCC->CSR, RCC_CSR_LSIRDY))\r
+ {\r
+ frequency = LSI_VALUE;\r
+ }\r
+ }\r
+ /* Check if HSE is ready and if RTC clock selection is HSE */\r
+ else if (srcclk == RCC_RTCCLKSOURCE_HSE_DIVX)\r
+ {\r
+ if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSERDY))\r
+ {\r
+ /* Get the current HSE clock divider */\r
+ switch (__HAL_RCC_GET_RTC_HSE_PRESCALER())\r
+ {\r
+ case RCC_RTC_HSE_DIV_16: /* HSE DIV16 has been selected */\r
+ {\r
+ frequency = HSE_VALUE / 16U;\r
+ break;\r
+ }\r
+ case RCC_RTC_HSE_DIV_8: /* HSE DIV8 has been selected */\r
+ {\r
+ frequency = HSE_VALUE / 8U;\r
+ break;\r
+ }\r
+ case RCC_RTC_HSE_DIV_4: /* HSE DIV4 has been selected */\r
+ {\r
+ frequency = HSE_VALUE / 4U;\r
+ break;\r
+ }\r
+ default: /* HSE DIV2 has been selected */\r
+ {\r
+ frequency = HSE_VALUE / 2U;\r
+ break;\r
+ }\r
+ }\r
+ }\r
+ }\r
+ else\r
+ {\r
+ /* No clock source, frequency default init at 0 */\r
+ }\r
+ break;\r
+ }\r
+\r
+ default:\r
+ break;\r
+ }\r
+\r
+ return(frequency);\r
+}\r
+\r
+#if defined(RCC_LSECSS_SUPPORT)\r
+/**\r
+ * @brief Enables the LSE Clock Security System.\r
+ * @note If a failure is detected on the external 32 kHz oscillator, the LSE clock is no longer supplied\r
+ * to the RTC but no hardware action is made to the registers.\r
+ * In Standby mode a wakeup is generated. In other modes an interrupt can be sent to wakeup\r
+ * the software (see Section 5.3.4: Clock interrupt register (RCC_CIR) on page 104).\r
+ * The software MUST then disable the LSECSSON bit, stop the defective 32 kHz oscillator\r
+ * (disabling LSEON), and can change the RTC clock source (no clock or LSI or HSE, with\r
+ * RTCSEL), or take any required action to secure the application.\r
+ * @note LSE CSS available only for high density and medium+ devices\r
+ * @retval None\r
+ */\r
+void HAL_RCCEx_EnableLSECSS(void)\r
+{\r
+ *(__IO uint32_t *) CSR_LSECSSON_BB = (uint32_t)ENABLE;\r
+}\r
+\r
+/**\r
+ * @brief Disables the LSE Clock Security System.\r
+ * @note Once enabled this bit cannot be disabled, except after an LSE failure detection\r
+ * (LSECSSD=1). In that case the software MUST disable the LSECSSON bit.\r
+ * Reset by power on reset and RTC software reset (RTCRST bit).\r
+ * @note LSE CSS available only for high density and medium+ devices\r
+ * @retval None\r
+ */\r
+void HAL_RCCEx_DisableLSECSS(void)\r
+{\r
+ /* Disable LSE CSS */\r
+ *(__IO uint32_t *) CSR_LSECSSON_BB = (uint32_t)DISABLE;\r
+\r
+ /* Disable LSE CSS IT */\r
+ __HAL_RCC_DISABLE_IT(RCC_IT_LSECSS);\r
+}\r
+\r
+/**\r
+ * @brief Enable the LSE Clock Security System IT & corresponding EXTI line.\r
+ * @note LSE Clock Security System IT is mapped on RTC EXTI line 19\r
+ * @retval None\r
+ */\r
+void HAL_RCCEx_EnableLSECSS_IT(void)\r
+{\r
+ /* Enable LSE CSS */\r
+ *(__IO uint32_t *) CSR_LSECSSON_BB = (uint32_t)ENABLE;\r
+\r
+ /* Enable LSE CSS IT */\r
+ __HAL_RCC_ENABLE_IT(RCC_IT_LSECSS);\r
+\r
+ /* Enable IT on EXTI Line 19 */\r
+ __HAL_RCC_LSECSS_EXTI_ENABLE_IT();\r
+ __HAL_RCC_LSECSS_EXTI_ENABLE_RISING_EDGE();\r
+}\r
+\r
+/**\r
+ * @brief Handle the RCC LSE Clock Security System interrupt request.\r
+ * @retval None\r
+ */\r
+void HAL_RCCEx_LSECSS_IRQHandler(void)\r
+{\r
+ /* Check RCC LSE CSSF flag */\r
+ if(__HAL_RCC_GET_IT(RCC_IT_LSECSS))\r
+ {\r
+ /* RCC LSE Clock Security System interrupt user callback */\r
+ HAL_RCCEx_LSECSS_Callback();\r
+\r
+ /* Clear RCC LSE CSS pending bit */\r
+ __HAL_RCC_CLEAR_IT(RCC_IT_LSECSS);\r
+ }\r
+}\r
+\r
+/**\r
+ * @brief RCCEx LSE Clock Security System interrupt callback.\r
+ * @retval none\r
+ */\r
+__weak void HAL_RCCEx_LSECSS_Callback(void)\r
+{\r
+ /* NOTE : This function should not be modified, when the callback is needed,\r
+ the @ref HAL_RCCEx_LSECSS_Callback should be implemented in the user file\r
+ */\r
+}\r
+#endif /* RCC_LSECSS_SUPPORT */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+#endif /* HAL_RCC_MODULE_ENABLED */\r
+/**\r
+ * @}\r
+ */\r
+\r
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\r
--- /dev/null
+/**\r
+ ******************************************************************************\r
+ * @file stm32l1xx_hal_tim.c\r
+ * @author MCD Application Team\r
+ * @brief TIM HAL module driver.\r
+ * This file provides firmware functions to manage the following\r
+ * functionalities of the Timer (TIM) peripheral:\r
+ * + TIM Time Base Initialization\r
+ * + TIM Time Base Start\r
+ * + TIM Time Base Start Interruption\r
+ * + TIM Time Base Start DMA\r
+ * + TIM Output Compare/PWM Initialization\r
+ * + TIM Output Compare/PWM Channel Configuration\r
+ * + TIM Output Compare/PWM Start\r
+ * + TIM Output Compare/PWM Start Interruption\r
+ * + TIM Output Compare/PWM Start DMA\r
+ * + TIM Input Capture Initialization\r
+ * + TIM Input Capture Channel Configuration\r
+ * + TIM Input Capture Start\r
+ * + TIM Input Capture Start Interruption\r
+ * + TIM Input Capture Start DMA\r
+ * + TIM One Pulse Initialization\r
+ * + TIM One Pulse Channel Configuration\r
+ * + TIM One Pulse Start\r
+ * + TIM Encoder Interface Initialization\r
+ * + TIM Encoder Interface Start\r
+ * + TIM Encoder Interface Start Interruption\r
+ * + TIM Encoder Interface Start DMA\r
+ * + Commutation Event configuration with Interruption and DMA\r
+ * + TIM OCRef clear configuration\r
+ * + TIM External Clock configuration\r
+ @verbatim\r
+ ==============================================================================\r
+ ##### TIMER Generic features #####\r
+ ==============================================================================\r
+ [..] The Timer features include:\r
+ (#) 16-bit up, down, up/down auto-reload counter.\r
+ (#) 16-bit programmable prescaler allowing dividing (also on the fly) the\r
+ counter clock frequency either by any factor between 1 and 65536.\r
+ (#) Up to 4 independent channels for:\r
+ (++) Input Capture\r
+ (++) Output Compare\r
+ (++) PWM generation (Edge and Center-aligned Mode)\r
+ (++) One-pulse mode output\r
+ (#) Synchronization circuit to control the timer with external signals and to interconnect\r
+ several timers together.\r
+ (#) Supports incremental encoder for positioning purposes\r
+\r
+ ##### How to use this driver #####\r
+ ==============================================================================\r
+ [..]\r
+ (#) Initialize the TIM low level resources by implementing the following functions\r
+ depending on the selected feature:\r
+ (++) Time Base : HAL_TIM_Base_MspInit()\r
+ (++) Input Capture : HAL_TIM_IC_MspInit()\r
+ (++) Output Compare : HAL_TIM_OC_MspInit()\r
+ (++) PWM generation : HAL_TIM_PWM_MspInit()\r
+ (++) One-pulse mode output : HAL_TIM_OnePulse_MspInit()\r
+ (++) Encoder mode output : HAL_TIM_Encoder_MspInit()\r
+\r
+ (#) Initialize the TIM low level resources :\r
+ (##) Enable the TIM interface clock using __HAL_RCC_TIMx_CLK_ENABLE();\r
+ (##) TIM pins configuration\r
+ (+++) Enable the clock for the TIM GPIOs using the following function:\r
+ __HAL_RCC_GPIOx_CLK_ENABLE();\r
+ (+++) Configure these TIM pins in Alternate function mode using HAL_GPIO_Init();\r
+\r
+ (#) The external Clock can be configured, if needed (the default clock is the\r
+ internal clock from the APBx), using the following function:\r
+ HAL_TIM_ConfigClockSource, the clock configuration should be done before\r
+ any start function.\r
+\r
+ (#) Configure the TIM in the desired functioning mode using one of the\r
+ Initialization function of this driver:\r
+ (++) HAL_TIM_Base_Init: to use the Timer to generate a simple time base\r
+ (++) HAL_TIM_OC_Init and HAL_TIM_OC_ConfigChannel: to use the Timer to generate an\r
+ Output Compare signal.\r
+ (++) HAL_TIM_PWM_Init and HAL_TIM_PWM_ConfigChannel: to use the Timer to generate a\r
+ PWM signal.\r
+ (++) HAL_TIM_IC_Init and HAL_TIM_IC_ConfigChannel: to use the Timer to measure an\r
+ external signal.\r
+ (++) HAL_TIM_OnePulse_Init and HAL_TIM_OnePulse_ConfigChannel: to use the Timer\r
+ in One Pulse Mode.\r
+ (++) HAL_TIM_Encoder_Init: to use the Timer Encoder Interface.\r
+\r
+ (#) Activate the TIM peripheral using one of the start functions depending from the feature used:\r
+ (++) Time Base : HAL_TIM_Base_Start(), HAL_TIM_Base_Start_DMA(), HAL_TIM_Base_Start_IT()\r
+ (++) Input Capture : HAL_TIM_IC_Start(), HAL_TIM_IC_Start_DMA(), HAL_TIM_IC_Start_IT()\r
+ (++) Output Compare : HAL_TIM_OC_Start(), HAL_TIM_OC_Start_DMA(), HAL_TIM_OC_Start_IT()\r
+ (++) PWM generation : HAL_TIM_PWM_Start(), HAL_TIM_PWM_Start_DMA(), HAL_TIM_PWM_Start_IT()\r
+ (++) One-pulse mode output : HAL_TIM_OnePulse_Start(), HAL_TIM_OnePulse_Start_IT()\r
+ (++) Encoder mode output : HAL_TIM_Encoder_Start(), HAL_TIM_Encoder_Start_DMA(), HAL_TIM_Encoder_Start_IT().\r
+\r
+ (#) The DMA Burst is managed with the two following functions:\r
+ HAL_TIM_DMABurst_WriteStart()\r
+ HAL_TIM_DMABurst_ReadStart()\r
+\r
+ *** Callback registration ***\r
+ =============================================\r
+\r
+ The compilation define USE_HAL_TIM_REGISTER_CALLBACKS when set to 1\r
+ allows the user to configure dynamically the driver callbacks.\r
+\r
+ Use Function @ref HAL_TIM_RegisterCallback() to register a callback.\r
+ @ref HAL_TIM_RegisterCallback() takes as parameters the HAL peripheral handle,\r
+ the Callback ID and a pointer to the user callback function.\r
+\r
+ Use function @ref HAL_TIM_UnRegisterCallback() to reset a callback to the default\r
+ weak function.\r
+ @ref HAL_TIM_UnRegisterCallback takes as parameters the HAL peripheral handle,\r
+ and the Callback ID.\r
+\r
+ These functions allow to register/unregister following callbacks:\r
+ (+) Base_MspInitCallback : TIM Base Msp Init Callback.\r
+ (+) Base_MspDeInitCallback : TIM Base Msp DeInit Callback.\r
+ (+) IC_MspInitCallback : TIM IC Msp Init Callback.\r
+ (+) IC_MspDeInitCallback : TIM IC Msp DeInit Callback.\r
+ (+) OC_MspInitCallback : TIM OC Msp Init Callback.\r
+ (+) OC_MspDeInitCallback : TIM OC Msp DeInit Callback.\r
+ (+) PWM_MspInitCallback : TIM PWM Msp Init Callback.\r
+ (+) PWM_MspDeInitCallback : TIM PWM Msp DeInit Callback.\r
+ (+) OnePulse_MspInitCallback : TIM One Pulse Msp Init Callback.\r
+ (+) OnePulse_MspDeInitCallback : TIM One Pulse Msp DeInit Callback.\r
+ (+) Encoder_MspInitCallback : TIM Encoder Msp Init Callback.\r
+ (+) Encoder_MspDeInitCallback : TIM Encoder Msp DeInit Callback.\r
+ (+) PeriodElapsedCallback : TIM Period Elapsed Callback.\r
+ (+) PeriodElapsedHalfCpltCallback : TIM Period Elapsed half complete Callback.\r
+ (+) TriggerCallback : TIM Trigger Callback.\r
+ (+) TriggerHalfCpltCallback : TIM Trigger half complete Callback.\r
+ (+) IC_CaptureCallback : TIM Input Capture Callback.\r
+ (+) IC_CaptureHalfCpltCallback : TIM Input Capture half complete Callback.\r
+ (+) OC_DelayElapsedCallback : TIM Output Compare Delay Elapsed Callback.\r
+ (+) PWM_PulseFinishedCallback : TIM PWM Pulse Finished Callback.\r
+ (+) PWM_PulseFinishedHalfCpltCallback : TIM PWM Pulse Finished half complete Callback.\r
+ (+) ErrorCallback : TIM Error Callback.\r
+\r
+By default, after the Init and when the state is HAL_TIM_STATE_RESET\r
+all interrupt callbacks are set to the corresponding weak functions:\r
+ examples @ref HAL_TIM_TriggerCallback(), @ref HAL_TIM_ErrorCallback().\r
+\r
+ Exception done for MspInit and MspDeInit functions that are reset to the legacy weak\r
+ functionalities in the Init / DeInit only when these callbacks are null\r
+ (not registered beforehand). If not, MspInit or MspDeInit are not null, the Init / DeInit\r
+ keep and use the user MspInit / MspDeInit callbacks(registered beforehand)\r
+\r
+ Callbacks can be registered / unregistered in HAL_TIM_STATE_READY state only.\r
+ Exception done MspInit / MspDeInit that can be registered / unregistered\r
+ in HAL_TIM_STATE_READY or HAL_TIM_STATE_RESET state,\r
+ thus registered(user) MspInit / DeInit callbacks can be used during the Init / DeInit.\r
+ In that case first register the MspInit/MspDeInit user callbacks\r
+ using @ref HAL_TIM_RegisterCallback() before calling DeInit or Init function.\r
+\r
+ When The compilation define USE_HAL_TIM_REGISTER_CALLBACKS is set to 0 or\r
+ not defined, the callback registration feature is not available and all callbacks\r
+ are set to the corresponding weak functions.\r
+\r
+ @endverbatim\r
+ ******************************************************************************\r
+ * @attention\r
+ *\r
+ * <h2><center>© Copyright (c) 2016 STMicroelectronics.\r
+ * All rights reserved.</center></h2>\r
+ *\r
+ * This software component is licensed by ST under BSD 3-Clause license,\r
+ * the "License"; You may not use this file except in compliance with the\r
+ * License. You may obtain a copy of the License at:\r
+ * opensource.org/licenses/BSD-3-Clause\r
+ *\r
+ ******************************************************************************\r
+ */\r
+\r
+/* Includes ------------------------------------------------------------------*/\r
+#include "stm32l1xx_hal.h"\r
+\r
+/** @addtogroup STM32L1xx_HAL_Driver\r
+ * @{\r
+ */\r
+\r
+/** @defgroup TIM TIM\r
+ * @brief TIM HAL module driver\r
+ * @{\r
+ */\r
+\r
+#ifdef HAL_TIM_MODULE_ENABLED\r
+\r
+/* Private typedef -----------------------------------------------------------*/\r
+/* Private define ------------------------------------------------------------*/\r
+/* Private macro -------------------------------------------------------------*/\r
+/* Private variables ---------------------------------------------------------*/\r
+/* Private function prototypes -----------------------------------------------*/\r
+/** @addtogroup TIM_Private_Functions\r
+ * @{\r
+ */\r
+static void TIM_Base_SetConfig(TIM_TypeDef *TIMx, TIM_Base_InitTypeDef *Structure);\r
+static void TIM_OC1_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config);\r
+static void TIM_OC2_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config);\r
+static void TIM_OC3_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config);\r
+static void TIM_OC4_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config);\r
+static void TIM_TI1_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection, uint32_t TIM_ICFilter);\r
+static void TIM_TI1_ConfigInputStage(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICFilter);\r
+static void TIM_TI2_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection,\r
+ uint32_t TIM_ICFilter);\r
+static void TIM_TI2_ConfigInputStage(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICFilter);\r
+static void TIM_TI3_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection,\r
+ uint32_t TIM_ICFilter);\r
+static void TIM_TI4_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection,\r
+ uint32_t TIM_ICFilter);\r
+static void TIM_ITRx_SetConfig(TIM_TypeDef *TIMx, uint32_t InputTriggerSource);\r
+static void TIM_ETR_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ExtTRGPrescaler,\r
+ uint32_t TIM_ExtTRGPolarity, uint32_t ExtTRGFilter);\r
+static void TIM_CCxChannelCmd(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t ChannelState);\r
+static void TIM_DMAPeriodElapsedCplt(DMA_HandleTypeDef *hdma);\r
+static void TIM_DMAPeriodElapsedHalfCplt(DMA_HandleTypeDef *hdma);\r
+static void TIM_DMATriggerCplt(DMA_HandleTypeDef *hdma);\r
+static void TIM_DMATriggerHalfCplt(DMA_HandleTypeDef *hdma);\r
+static HAL_StatusTypeDef TIM_SlaveTimer_SetConfig(TIM_HandleTypeDef *htim,\r
+ TIM_SlaveConfigTypeDef *sSlaveConfig);\r
+/**\r
+ * @}\r
+ */\r
+/* Exported functions --------------------------------------------------------*/\r
+\r
+/** @defgroup TIM_Exported_Functions TIM Exported Functions\r
+ * @{\r
+ */\r
+\r
+/** @defgroup TIM_Exported_Functions_Group1 TIM Time Base functions\r
+ * @brief Time Base functions\r
+ *\r
+@verbatim\r
+ ==============================================================================\r
+ ##### Time Base functions #####\r
+ ==============================================================================\r
+ [..]\r
+ This section provides functions allowing to:\r
+ (+) Initialize and configure the TIM base.\r
+ (+) De-initialize the TIM base.\r
+ (+) Start the Time Base.\r
+ (+) Stop the Time Base.\r
+ (+) Start the Time Base and enable interrupt.\r
+ (+) Stop the Time Base and disable interrupt.\r
+ (+) Start the Time Base and enable DMA transfer.\r
+ (+) Stop the Time Base and disable DMA transfer.\r
+\r
+@endverbatim\r
+ * @{\r
+ */\r
+/**\r
+ * @brief Initializes the TIM Time base Unit according to the specified\r
+ * parameters in the TIM_HandleTypeDef and initialize the associated handle.\r
+ * @note Switching from Center Aligned counter mode to Edge counter mode (or reverse)\r
+ * requires a timer reset to avoid unexpected direction\r
+ * due to DIR bit readonly in center aligned mode.\r
+ * Ex: call @ref HAL_TIM_Base_DeInit() before HAL_TIM_Base_Init()\r
+ * @param htim TIM Base handle\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_TIM_Base_Init(TIM_HandleTypeDef *htim)\r
+{\r
+ /* Check the TIM handle allocation */\r
+ if (htim == NULL)\r
+ {\r
+ return HAL_ERROR;\r
+ }\r
+\r
+ /* Check the parameters */\r
+ assert_param(IS_TIM_INSTANCE(htim->Instance));\r
+ assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode));\r
+ assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision));\r
+ assert_param(IS_TIM_AUTORELOAD_PRELOAD(htim->Init.AutoReloadPreload));\r
+\r
+ if (htim->State == HAL_TIM_STATE_RESET)\r
+ {\r
+ /* Allocate lock resource and initialize it */\r
+ htim->Lock = HAL_UNLOCKED;\r
+\r
+#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)\r
+ /* Reset interrupt callbacks to legacy weak callbacks */\r
+ TIM_ResetCallback(htim);\r
+\r
+ if (htim->Base_MspInitCallback == NULL)\r
+ {\r
+ htim->Base_MspInitCallback = HAL_TIM_Base_MspInit;\r
+ }\r
+ /* Init the low level hardware : GPIO, CLOCK, NVIC */\r
+ htim->Base_MspInitCallback(htim);\r
+#else\r
+ /* Init the low level hardware : GPIO, CLOCK, NVIC */\r
+ HAL_TIM_Base_MspInit(htim);\r
+#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */\r
+ }\r
+\r
+ /* Set the TIM state */\r
+ htim->State = HAL_TIM_STATE_BUSY;\r
+\r
+ /* Set the Time Base configuration */\r
+ TIM_Base_SetConfig(htim->Instance, &htim->Init);\r
+\r
+ /* Initialize the TIM state*/\r
+ htim->State = HAL_TIM_STATE_READY;\r
+\r
+ return HAL_OK;\r
+}\r
+\r
+/**\r
+ * @brief DeInitializes the TIM Base peripheral\r
+ * @param htim TIM Base handle\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_TIM_Base_DeInit(TIM_HandleTypeDef *htim)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_TIM_INSTANCE(htim->Instance));\r
+\r
+ htim->State = HAL_TIM_STATE_BUSY;\r
+\r
+ /* Disable the TIM Peripheral Clock */\r
+ __HAL_TIM_DISABLE(htim);\r
+\r
+#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)\r
+ if (htim->Base_MspDeInitCallback == NULL)\r
+ {\r
+ htim->Base_MspDeInitCallback = HAL_TIM_Base_MspDeInit;\r
+ }\r
+ /* DeInit the low level hardware */\r
+ htim->Base_MspDeInitCallback(htim);\r
+#else\r
+ /* DeInit the low level hardware: GPIO, CLOCK, NVIC */\r
+ HAL_TIM_Base_MspDeInit(htim);\r
+#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */\r
+\r
+ /* Change TIM state */\r
+ htim->State = HAL_TIM_STATE_RESET;\r
+\r
+ /* Release Lock */\r
+ __HAL_UNLOCK(htim);\r
+\r
+ return HAL_OK;\r
+}\r
+\r
+/**\r
+ * @brief Initializes the TIM Base MSP.\r
+ * @param htim TIM Base handle\r
+ * @retval None\r
+ */\r
+__weak void HAL_TIM_Base_MspInit(TIM_HandleTypeDef *htim)\r
+{\r
+ /* Prevent unused argument(s) compilation warning */\r
+ UNUSED(htim);\r
+\r
+ /* NOTE : This function should not be modified, when the callback is needed,\r
+ the HAL_TIM_Base_MspInit could be implemented in the user file\r
+ */\r
+}\r
+\r
+/**\r
+ * @brief DeInitializes TIM Base MSP.\r
+ * @param htim TIM Base handle\r
+ * @retval None\r
+ */\r
+__weak void HAL_TIM_Base_MspDeInit(TIM_HandleTypeDef *htim)\r
+{\r
+ /* Prevent unused argument(s) compilation warning */\r
+ UNUSED(htim);\r
+\r
+ /* NOTE : This function should not be modified, when the callback is needed,\r
+ the HAL_TIM_Base_MspDeInit could be implemented in the user file\r
+ */\r
+}\r
+\r
+\r
+/**\r
+ * @brief Starts the TIM Base generation.\r
+ * @param htim TIM Base handle\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_TIM_Base_Start(TIM_HandleTypeDef *htim)\r
+{\r
+ uint32_t tmpsmcr;\r
+\r
+ /* Check the parameters */\r
+ assert_param(IS_TIM_INSTANCE(htim->Instance));\r
+\r
+ /* Set the TIM state */\r
+ htim->State = HAL_TIM_STATE_BUSY;\r
+\r
+ /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */\r
+ tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;\r
+ if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))\r
+ {\r
+ __HAL_TIM_ENABLE(htim);\r
+ }\r
+\r
+ /* Change the TIM state*/\r
+ htim->State = HAL_TIM_STATE_READY;\r
+\r
+ /* Return function status */\r
+ return HAL_OK;\r
+}\r
+\r
+/**\r
+ * @brief Stops the TIM Base generation.\r
+ * @param htim TIM Base handle\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_TIM_Base_Stop(TIM_HandleTypeDef *htim)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_TIM_INSTANCE(htim->Instance));\r
+\r
+ /* Set the TIM state */\r
+ htim->State = HAL_TIM_STATE_BUSY;\r
+\r
+ /* Disable the Peripheral */\r
+ __HAL_TIM_DISABLE(htim);\r
+\r
+ /* Change the TIM state*/\r
+ htim->State = HAL_TIM_STATE_READY;\r
+\r
+ /* Return function status */\r
+ return HAL_OK;\r
+}\r
+\r
+/**\r
+ * @brief Starts the TIM Base generation in interrupt mode.\r
+ * @param htim TIM Base handle\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_TIM_Base_Start_IT(TIM_HandleTypeDef *htim)\r
+{\r
+ uint32_t tmpsmcr;\r
+\r
+ /* Check the parameters */\r
+ assert_param(IS_TIM_INSTANCE(htim->Instance));\r
+\r
+ /* Enable the TIM Update interrupt */\r
+ __HAL_TIM_ENABLE_IT(htim, TIM_IT_UPDATE);\r
+\r
+ /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */\r
+ tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;\r
+ if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))\r
+ {\r
+ __HAL_TIM_ENABLE(htim);\r
+ }\r
+\r
+ /* Return function status */\r
+ return HAL_OK;\r
+}\r
+\r
+/**\r
+ * @brief Stops the TIM Base generation in interrupt mode.\r
+ * @param htim TIM Base handle\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_TIM_Base_Stop_IT(TIM_HandleTypeDef *htim)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_TIM_INSTANCE(htim->Instance));\r
+ /* Disable the TIM Update interrupt */\r
+ __HAL_TIM_DISABLE_IT(htim, TIM_IT_UPDATE);\r
+\r
+ /* Disable the Peripheral */\r
+ __HAL_TIM_DISABLE(htim);\r
+\r
+ /* Return function status */\r
+ return HAL_OK;\r
+}\r
+\r
+/**\r
+ * @brief Starts the TIM Base generation in DMA mode.\r
+ * @param htim TIM Base handle\r
+ * @param pData The source Buffer address.\r
+ * @param Length The length of data to be transferred from memory to peripheral.\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_TIM_Base_Start_DMA(TIM_HandleTypeDef *htim, uint32_t *pData, uint16_t Length)\r
+{\r
+ uint32_t tmpsmcr;\r
+\r
+ /* Check the parameters */\r
+ assert_param(IS_TIM_DMA_INSTANCE(htim->Instance));\r
+\r
+ if ((htim->State == HAL_TIM_STATE_BUSY))\r
+ {\r
+ return HAL_BUSY;\r
+ }\r
+ else if ((htim->State == HAL_TIM_STATE_READY))\r
+ {\r
+ if ((pData == NULL) && (Length > 0U))\r
+ {\r
+ return HAL_ERROR;\r
+ }\r
+ else\r
+ {\r
+ htim->State = HAL_TIM_STATE_BUSY;\r
+ }\r
+ }\r
+ else\r
+ {\r
+ /* nothing to do */\r
+ }\r
+\r
+ /* Set the DMA Period elapsed callbacks */\r
+ htim->hdma[TIM_DMA_ID_UPDATE]->XferCpltCallback = TIM_DMAPeriodElapsedCplt;\r
+ htim->hdma[TIM_DMA_ID_UPDATE]->XferHalfCpltCallback = TIM_DMAPeriodElapsedHalfCplt;\r
+\r
+ /* Set the DMA error callback */\r
+ htim->hdma[TIM_DMA_ID_UPDATE]->XferErrorCallback = TIM_DMAError ;\r
+\r
+ /* Enable the DMA channel */\r
+ if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_UPDATE], (uint32_t)pData, (uint32_t)&htim->Instance->ARR, Length) != HAL_OK)\r
+ {\r
+ return HAL_ERROR;\r
+ }\r
+\r
+ /* Enable the TIM Update DMA request */\r
+ __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_UPDATE);\r
+\r
+ /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */\r
+ tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;\r
+ if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))\r
+ {\r
+ __HAL_TIM_ENABLE(htim);\r
+ }\r
+\r
+ /* Return function status */\r
+ return HAL_OK;\r
+}\r
+\r
+/**\r
+ * @brief Stops the TIM Base generation in DMA mode.\r
+ * @param htim TIM Base handle\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_TIM_Base_Stop_DMA(TIM_HandleTypeDef *htim)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_TIM_DMA_INSTANCE(htim->Instance));\r
+\r
+ /* Disable the TIM Update DMA request */\r
+ __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_UPDATE);\r
+\r
+ (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_UPDATE]);\r
+\r
+ /* Disable the Peripheral */\r
+ __HAL_TIM_DISABLE(htim);\r
+\r
+ /* Change the htim state */\r
+ htim->State = HAL_TIM_STATE_READY;\r
+\r
+ /* Return function status */\r
+ return HAL_OK;\r
+}\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup TIM_Exported_Functions_Group2 TIM Output Compare functions\r
+ * @brief TIM Output Compare functions\r
+ *\r
+@verbatim\r
+ ==============================================================================\r
+ ##### TIM Output Compare functions #####\r
+ ==============================================================================\r
+ [..]\r
+ This section provides functions allowing to:\r
+ (+) Initialize and configure the TIM Output Compare.\r
+ (+) De-initialize the TIM Output Compare.\r
+ (+) Start the TIM Output Compare.\r
+ (+) Stop the TIM Output Compare.\r
+ (+) Start the TIM Output Compare and enable interrupt.\r
+ (+) Stop the TIM Output Compare and disable interrupt.\r
+ (+) Start the TIM Output Compare and enable DMA transfer.\r
+ (+) Stop the TIM Output Compare and disable DMA transfer.\r
+\r
+@endverbatim\r
+ * @{\r
+ */\r
+/**\r
+ * @brief Initializes the TIM Output Compare according to the specified\r
+ * parameters in the TIM_HandleTypeDef and initializes the associated handle.\r
+ * @note Switching from Center Aligned counter mode to Edge counter mode (or reverse)\r
+ * requires a timer reset to avoid unexpected direction\r
+ * due to DIR bit readonly in center aligned mode.\r
+ * Ex: call @ref HAL_TIM_OC_DeInit() before HAL_TIM_OC_Init()\r
+ * @param htim TIM Output Compare handle\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_TIM_OC_Init(TIM_HandleTypeDef *htim)\r
+{\r
+ /* Check the TIM handle allocation */\r
+ if (htim == NULL)\r
+ {\r
+ return HAL_ERROR;\r
+ }\r
+\r
+ /* Check the parameters */\r
+ assert_param(IS_TIM_INSTANCE(htim->Instance));\r
+ assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode));\r
+ assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision));\r
+ assert_param(IS_TIM_AUTORELOAD_PRELOAD(htim->Init.AutoReloadPreload));\r
+\r
+ if (htim->State == HAL_TIM_STATE_RESET)\r
+ {\r
+ /* Allocate lock resource and initialize it */\r
+ htim->Lock = HAL_UNLOCKED;\r
+\r
+#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)\r
+ /* Reset interrupt callbacks to legacy weak callbacks */\r
+ TIM_ResetCallback(htim);\r
+\r
+ if (htim->OC_MspInitCallback == NULL)\r
+ {\r
+ htim->OC_MspInitCallback = HAL_TIM_OC_MspInit;\r
+ }\r
+ /* Init the low level hardware : GPIO, CLOCK, NVIC */\r
+ htim->OC_MspInitCallback(htim);\r
+#else\r
+ /* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */\r
+ HAL_TIM_OC_MspInit(htim);\r
+#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */\r
+ }\r
+\r
+ /* Set the TIM state */\r
+ htim->State = HAL_TIM_STATE_BUSY;\r
+\r
+ /* Init the base time for the Output Compare */\r
+ TIM_Base_SetConfig(htim->Instance, &htim->Init);\r
+\r
+ /* Initialize the TIM state*/\r
+ htim->State = HAL_TIM_STATE_READY;\r
+\r
+ return HAL_OK;\r
+}\r
+\r
+/**\r
+ * @brief DeInitializes the TIM peripheral\r
+ * @param htim TIM Output Compare handle\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_TIM_OC_DeInit(TIM_HandleTypeDef *htim)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_TIM_INSTANCE(htim->Instance));\r
+\r
+ htim->State = HAL_TIM_STATE_BUSY;\r
+\r
+ /* Disable the TIM Peripheral Clock */\r
+ __HAL_TIM_DISABLE(htim);\r
+\r
+#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)\r
+ if (htim->OC_MspDeInitCallback == NULL)\r
+ {\r
+ htim->OC_MspDeInitCallback = HAL_TIM_OC_MspDeInit;\r
+ }\r
+ /* DeInit the low level hardware */\r
+ htim->OC_MspDeInitCallback(htim);\r
+#else\r
+ /* DeInit the low level hardware: GPIO, CLOCK, NVIC and DMA */\r
+ HAL_TIM_OC_MspDeInit(htim);\r
+#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */\r
+\r
+ /* Change TIM state */\r
+ htim->State = HAL_TIM_STATE_RESET;\r
+\r
+ /* Release Lock */\r
+ __HAL_UNLOCK(htim);\r
+\r
+ return HAL_OK;\r
+}\r
+\r
+/**\r
+ * @brief Initializes the TIM Output Compare MSP.\r
+ * @param htim TIM Output Compare handle\r
+ * @retval None\r
+ */\r
+__weak void HAL_TIM_OC_MspInit(TIM_HandleTypeDef *htim)\r
+{\r
+ /* Prevent unused argument(s) compilation warning */\r
+ UNUSED(htim);\r
+\r
+ /* NOTE : This function should not be modified, when the callback is needed,\r
+ the HAL_TIM_OC_MspInit could be implemented in the user file\r
+ */\r
+}\r
+\r
+/**\r
+ * @brief DeInitializes TIM Output Compare MSP.\r
+ * @param htim TIM Output Compare handle\r
+ * @retval None\r
+ */\r
+__weak void HAL_TIM_OC_MspDeInit(TIM_HandleTypeDef *htim)\r
+{\r
+ /* Prevent unused argument(s) compilation warning */\r
+ UNUSED(htim);\r
+\r
+ /* NOTE : This function should not be modified, when the callback is needed,\r
+ the HAL_TIM_OC_MspDeInit could be implemented in the user file\r
+ */\r
+}\r
+\r
+/**\r
+ * @brief Starts the TIM Output Compare signal generation.\r
+ * @param htim TIM Output Compare handle\r
+ * @param Channel TIM Channel to be enabled\r
+ * This parameter can be one of the following values:\r
+ * @arg TIM_CHANNEL_1: TIM Channel 1 selected\r
+ * @arg TIM_CHANNEL_2: TIM Channel 2 selected\r
+ * @arg TIM_CHANNEL_3: TIM Channel 3 selected\r
+ * @arg TIM_CHANNEL_4: TIM Channel 4 selected\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_TIM_OC_Start(TIM_HandleTypeDef *htim, uint32_t Channel)\r
+{\r
+ uint32_t tmpsmcr;\r
+\r
+ /* Check the parameters */\r
+ assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));\r
+\r
+ /* Enable the Output compare channel */\r
+ TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);\r
+\r
+ /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */\r
+ tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;\r
+ if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))\r
+ {\r
+ __HAL_TIM_ENABLE(htim);\r
+ }\r
+\r
+ /* Return function status */\r
+ return HAL_OK;\r
+}\r
+\r
+/**\r
+ * @brief Stops the TIM Output Compare signal generation.\r
+ * @param htim TIM Output Compare handle\r
+ * @param Channel TIM Channel to be disabled\r
+ * This parameter can be one of the following values:\r
+ * @arg TIM_CHANNEL_1: TIM Channel 1 selected\r
+ * @arg TIM_CHANNEL_2: TIM Channel 2 selected\r
+ * @arg TIM_CHANNEL_3: TIM Channel 3 selected\r
+ * @arg TIM_CHANNEL_4: TIM Channel 4 selected\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_TIM_OC_Stop(TIM_HandleTypeDef *htim, uint32_t Channel)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));\r
+\r
+ /* Disable the Output compare channel */\r
+ TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);\r
+\r
+ /* Disable the Peripheral */\r
+ __HAL_TIM_DISABLE(htim);\r
+\r
+ /* Return function status */\r
+ return HAL_OK;\r
+}\r
+\r
+/**\r
+ * @brief Starts the TIM Output Compare signal generation in interrupt mode.\r
+ * @param htim TIM Output Compare handle\r
+ * @param Channel TIM Channel to be enabled\r
+ * This parameter can be one of the following values:\r
+ * @arg TIM_CHANNEL_1: TIM Channel 1 selected\r
+ * @arg TIM_CHANNEL_2: TIM Channel 2 selected\r
+ * @arg TIM_CHANNEL_3: TIM Channel 3 selected\r
+ * @arg TIM_CHANNEL_4: TIM Channel 4 selected\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_TIM_OC_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel)\r
+{\r
+ uint32_t tmpsmcr;\r
+\r
+ /* Check the parameters */\r
+ assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));\r
+\r
+ switch (Channel)\r
+ {\r
+ case TIM_CHANNEL_1:\r
+ {\r
+ /* Enable the TIM Capture/Compare 1 interrupt */\r
+ __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1);\r
+ break;\r
+ }\r
+\r
+ case TIM_CHANNEL_2:\r
+ {\r
+ /* Enable the TIM Capture/Compare 2 interrupt */\r
+ __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2);\r
+ break;\r
+ }\r
+\r
+ case TIM_CHANNEL_3:\r
+ {\r
+ /* Enable the TIM Capture/Compare 3 interrupt */\r
+ __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC3);\r
+ break;\r
+ }\r
+\r
+ case TIM_CHANNEL_4:\r
+ {\r
+ /* Enable the TIM Capture/Compare 4 interrupt */\r
+ __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC4);\r
+ break;\r
+ }\r
+\r
+ default:\r
+ break;\r
+ }\r
+\r
+ /* Enable the Output compare channel */\r
+ TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);\r
+\r
+ /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */\r
+ tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;\r
+ if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))\r
+ {\r
+ __HAL_TIM_ENABLE(htim);\r
+ }\r
+\r
+ /* Return function status */\r
+ return HAL_OK;\r
+}\r
+\r
+/**\r
+ * @brief Stops the TIM Output Compare signal generation in interrupt mode.\r
+ * @param htim TIM Output Compare handle\r
+ * @param Channel TIM Channel to be disabled\r
+ * This parameter can be one of the following values:\r
+ * @arg TIM_CHANNEL_1: TIM Channel 1 selected\r
+ * @arg TIM_CHANNEL_2: TIM Channel 2 selected\r
+ * @arg TIM_CHANNEL_3: TIM Channel 3 selected\r
+ * @arg TIM_CHANNEL_4: TIM Channel 4 selected\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_TIM_OC_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));\r
+\r
+ switch (Channel)\r
+ {\r
+ case TIM_CHANNEL_1:\r
+ {\r
+ /* Disable the TIM Capture/Compare 1 interrupt */\r
+ __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1);\r
+ break;\r
+ }\r
+\r
+ case TIM_CHANNEL_2:\r
+ {\r
+ /* Disable the TIM Capture/Compare 2 interrupt */\r
+ __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2);\r
+ break;\r
+ }\r
+\r
+ case TIM_CHANNEL_3:\r
+ {\r
+ /* Disable the TIM Capture/Compare 3 interrupt */\r
+ __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC3);\r
+ break;\r
+ }\r
+\r
+ case TIM_CHANNEL_4:\r
+ {\r
+ /* Disable the TIM Capture/Compare 4 interrupt */\r
+ __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC4);\r
+ break;\r
+ }\r
+\r
+ default:\r
+ break;\r
+ }\r
+\r
+ /* Disable the Output compare channel */\r
+ TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);\r
+\r
+ /* Disable the Peripheral */\r
+ __HAL_TIM_DISABLE(htim);\r
+\r
+ /* Return function status */\r
+ return HAL_OK;\r
+}\r
+\r
+/**\r
+ * @brief Starts the TIM Output Compare signal generation in DMA mode.\r
+ * @param htim TIM Output Compare handle\r
+ * @param Channel TIM Channel to be enabled\r
+ * This parameter can be one of the following values:\r
+ * @arg TIM_CHANNEL_1: TIM Channel 1 selected\r
+ * @arg TIM_CHANNEL_2: TIM Channel 2 selected\r
+ * @arg TIM_CHANNEL_3: TIM Channel 3 selected\r
+ * @arg TIM_CHANNEL_4: TIM Channel 4 selected\r
+ * @param pData The source Buffer address.\r
+ * @param Length The length of data to be transferred from memory to TIM peripheral\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_TIM_OC_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length)\r
+{\r
+ uint32_t tmpsmcr;\r
+\r
+ /* Check the parameters */\r
+ assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));\r
+\r
+ if ((htim->State == HAL_TIM_STATE_BUSY))\r
+ {\r
+ return HAL_BUSY;\r
+ }\r
+ else if ((htim->State == HAL_TIM_STATE_READY))\r
+ {\r
+ if ((pData == NULL) && (Length > 0U))\r
+ {\r
+ return HAL_ERROR;\r
+ }\r
+ else\r
+ {\r
+ htim->State = HAL_TIM_STATE_BUSY;\r
+ }\r
+ }\r
+ else\r
+ {\r
+ /* nothing to do */\r
+ }\r
+\r
+ switch (Channel)\r
+ {\r
+ case TIM_CHANNEL_1:\r
+ {\r
+ /* Set the DMA compare callbacks */\r
+ htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMADelayPulseCplt;\r
+ htim->hdma[TIM_DMA_ID_CC1]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt;\r
+\r
+ /* Set the DMA error callback */\r
+ htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ;\r
+\r
+ /* Enable the DMA channel */\r
+ if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)pData, (uint32_t)&htim->Instance->CCR1, Length) != HAL_OK)\r
+ {\r
+ return HAL_ERROR;\r
+ }\r
+\r
+ /* Enable the TIM Capture/Compare 1 DMA request */\r
+ __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1);\r
+ break;\r
+ }\r
+\r
+ case TIM_CHANNEL_2:\r
+ {\r
+ /* Set the DMA compare callbacks */\r
+ htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMADelayPulseCplt;\r
+ htim->hdma[TIM_DMA_ID_CC2]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt;\r
+\r
+ /* Set the DMA error callback */\r
+ htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError ;\r
+\r
+ /* Enable the DMA channel */\r
+ if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)pData, (uint32_t)&htim->Instance->CCR2, Length) != HAL_OK)\r
+ {\r
+ return HAL_ERROR;\r
+ }\r
+\r
+ /* Enable the TIM Capture/Compare 2 DMA request */\r
+ __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC2);\r
+ break;\r
+ }\r
+\r
+ case TIM_CHANNEL_3:\r
+ {\r
+ /* Set the DMA compare callbacks */\r
+ htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = TIM_DMADelayPulseCplt;\r
+ htim->hdma[TIM_DMA_ID_CC3]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt;\r
+\r
+ /* Set the DMA error callback */\r
+ htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = TIM_DMAError ;\r
+\r
+ /* Enable the DMA channel */\r
+ if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)pData, (uint32_t)&htim->Instance->CCR3, Length) != HAL_OK)\r
+ {\r
+ return HAL_ERROR;\r
+ }\r
+ /* Enable the TIM Capture/Compare 3 DMA request */\r
+ __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC3);\r
+ break;\r
+ }\r
+\r
+ case TIM_CHANNEL_4:\r
+ {\r
+ /* Set the DMA compare callbacks */\r
+ htim->hdma[TIM_DMA_ID_CC4]->XferCpltCallback = TIM_DMADelayPulseCplt;\r
+ htim->hdma[TIM_DMA_ID_CC4]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt;\r
+\r
+ /* Set the DMA error callback */\r
+ htim->hdma[TIM_DMA_ID_CC4]->XferErrorCallback = TIM_DMAError ;\r
+\r
+ /* Enable the DMA channel */\r
+ if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)pData, (uint32_t)&htim->Instance->CCR4, Length) != HAL_OK)\r
+ {\r
+ return HAL_ERROR;\r
+ }\r
+ /* Enable the TIM Capture/Compare 4 DMA request */\r
+ __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC4);\r
+ break;\r
+ }\r
+\r
+ default:\r
+ break;\r
+ }\r
+\r
+ /* Enable the Output compare channel */\r
+ TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);\r
+\r
+ /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */\r
+ tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;\r
+ if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))\r
+ {\r
+ __HAL_TIM_ENABLE(htim);\r
+ }\r
+\r
+ /* Return function status */\r
+ return HAL_OK;\r
+}\r
+\r
+/**\r
+ * @brief Stops the TIM Output Compare signal generation in DMA mode.\r
+ * @param htim TIM Output Compare handle\r
+ * @param Channel TIM Channel to be disabled\r
+ * This parameter can be one of the following values:\r
+ * @arg TIM_CHANNEL_1: TIM Channel 1 selected\r
+ * @arg TIM_CHANNEL_2: TIM Channel 2 selected\r
+ * @arg TIM_CHANNEL_3: TIM Channel 3 selected\r
+ * @arg TIM_CHANNEL_4: TIM Channel 4 selected\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_TIM_OC_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));\r
+\r
+ switch (Channel)\r
+ {\r
+ case TIM_CHANNEL_1:\r
+ {\r
+ /* Disable the TIM Capture/Compare 1 DMA request */\r
+ __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1);\r
+ (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC1]);\r
+ break;\r
+ }\r
+\r
+ case TIM_CHANNEL_2:\r
+ {\r
+ /* Disable the TIM Capture/Compare 2 DMA request */\r
+ __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC2);\r
+ (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC2]);\r
+ break;\r
+ }\r
+\r
+ case TIM_CHANNEL_3:\r
+ {\r
+ /* Disable the TIM Capture/Compare 3 DMA request */\r
+ __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC3);\r
+ (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC3]);\r
+ break;\r
+ }\r
+\r
+ case TIM_CHANNEL_4:\r
+ {\r
+ /* Disable the TIM Capture/Compare 4 interrupt */\r
+ __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC4);\r
+ (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC4]);\r
+ break;\r
+ }\r
+\r
+ default:\r
+ break;\r
+ }\r
+\r
+ /* Disable the Output compare channel */\r
+ TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);\r
+\r
+ /* Disable the Peripheral */\r
+ __HAL_TIM_DISABLE(htim);\r
+\r
+ /* Change the htim state */\r
+ htim->State = HAL_TIM_STATE_READY;\r
+\r
+ /* Return function status */\r
+ return HAL_OK;\r
+}\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup TIM_Exported_Functions_Group3 TIM PWM functions\r
+ * @brief TIM PWM functions\r
+ *\r
+@verbatim\r
+ ==============================================================================\r
+ ##### TIM PWM functions #####\r
+ ==============================================================================\r
+ [..]\r
+ This section provides functions allowing to:\r
+ (+) Initialize and configure the TIM PWM.\r
+ (+) De-initialize the TIM PWM.\r
+ (+) Start the TIM PWM.\r
+ (+) Stop the TIM PWM.\r
+ (+) Start the TIM PWM and enable interrupt.\r
+ (+) Stop the TIM PWM and disable interrupt.\r
+ (+) Start the TIM PWM and enable DMA transfer.\r
+ (+) Stop the TIM PWM and disable DMA transfer.\r
+\r
+@endverbatim\r
+ * @{\r
+ */\r
+/**\r
+ * @brief Initializes the TIM PWM Time Base according to the specified\r
+ * parameters in the TIM_HandleTypeDef and initializes the associated handle.\r
+ * @note Switching from Center Aligned counter mode to Edge counter mode (or reverse)\r
+ * requires a timer reset to avoid unexpected direction\r
+ * due to DIR bit readonly in center aligned mode.\r
+ * Ex: call @ref HAL_TIM_PWM_DeInit() before HAL_TIM_PWM_Init()\r
+ * @param htim TIM PWM handle\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_TIM_PWM_Init(TIM_HandleTypeDef *htim)\r
+{\r
+ /* Check the TIM handle allocation */\r
+ if (htim == NULL)\r
+ {\r
+ return HAL_ERROR;\r
+ }\r
+\r
+ /* Check the parameters */\r
+ assert_param(IS_TIM_INSTANCE(htim->Instance));\r
+ assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode));\r
+ assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision));\r
+ assert_param(IS_TIM_AUTORELOAD_PRELOAD(htim->Init.AutoReloadPreload));\r
+\r
+ if (htim->State == HAL_TIM_STATE_RESET)\r
+ {\r
+ /* Allocate lock resource and initialize it */\r
+ htim->Lock = HAL_UNLOCKED;\r
+\r
+#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)\r
+ /* Reset interrupt callbacks to legacy weak callbacks */\r
+ TIM_ResetCallback(htim);\r
+\r
+ if (htim->PWM_MspInitCallback == NULL)\r
+ {\r
+ htim->PWM_MspInitCallback = HAL_TIM_PWM_MspInit;\r
+ }\r
+ /* Init the low level hardware : GPIO, CLOCK, NVIC */\r
+ htim->PWM_MspInitCallback(htim);\r
+#else\r
+ /* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */\r
+ HAL_TIM_PWM_MspInit(htim);\r
+#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */\r
+ }\r
+\r
+ /* Set the TIM state */\r
+ htim->State = HAL_TIM_STATE_BUSY;\r
+\r
+ /* Init the base time for the PWM */\r
+ TIM_Base_SetConfig(htim->Instance, &htim->Init);\r
+\r
+ /* Initialize the TIM state*/\r
+ htim->State = HAL_TIM_STATE_READY;\r
+\r
+ return HAL_OK;\r
+}\r
+\r
+/**\r
+ * @brief DeInitializes the TIM peripheral\r
+ * @param htim TIM PWM handle\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_TIM_PWM_DeInit(TIM_HandleTypeDef *htim)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_TIM_INSTANCE(htim->Instance));\r
+\r
+ htim->State = HAL_TIM_STATE_BUSY;\r
+\r
+ /* Disable the TIM Peripheral Clock */\r
+ __HAL_TIM_DISABLE(htim);\r
+\r
+#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)\r
+ if (htim->PWM_MspDeInitCallback == NULL)\r
+ {\r
+ htim->PWM_MspDeInitCallback = HAL_TIM_PWM_MspDeInit;\r
+ }\r
+ /* DeInit the low level hardware */\r
+ htim->PWM_MspDeInitCallback(htim);\r
+#else\r
+ /* DeInit the low level hardware: GPIO, CLOCK, NVIC and DMA */\r
+ HAL_TIM_PWM_MspDeInit(htim);\r
+#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */\r
+\r
+ /* Change TIM state */\r
+ htim->State = HAL_TIM_STATE_RESET;\r
+\r
+ /* Release Lock */\r
+ __HAL_UNLOCK(htim);\r
+\r
+ return HAL_OK;\r
+}\r
+\r
+/**\r
+ * @brief Initializes the TIM PWM MSP.\r
+ * @param htim TIM PWM handle\r
+ * @retval None\r
+ */\r
+__weak void HAL_TIM_PWM_MspInit(TIM_HandleTypeDef *htim)\r
+{\r
+ /* Prevent unused argument(s) compilation warning */\r
+ UNUSED(htim);\r
+\r
+ /* NOTE : This function should not be modified, when the callback is needed,\r
+ the HAL_TIM_PWM_MspInit could be implemented in the user file\r
+ */\r
+}\r
+\r
+/**\r
+ * @brief DeInitializes TIM PWM MSP.\r
+ * @param htim TIM PWM handle\r
+ * @retval None\r
+ */\r
+__weak void HAL_TIM_PWM_MspDeInit(TIM_HandleTypeDef *htim)\r
+{\r
+ /* Prevent unused argument(s) compilation warning */\r
+ UNUSED(htim);\r
+\r
+ /* NOTE : This function should not be modified, when the callback is needed,\r
+ the HAL_TIM_PWM_MspDeInit could be implemented in the user file\r
+ */\r
+}\r
+\r
+/**\r
+ * @brief Starts the PWM signal generation.\r
+ * @param htim TIM handle\r
+ * @param Channel TIM Channels to be enabled\r
+ * This parameter can be one of the following values:\r
+ * @arg TIM_CHANNEL_1: TIM Channel 1 selected\r
+ * @arg TIM_CHANNEL_2: TIM Channel 2 selected\r
+ * @arg TIM_CHANNEL_3: TIM Channel 3 selected\r
+ * @arg TIM_CHANNEL_4: TIM Channel 4 selected\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_TIM_PWM_Start(TIM_HandleTypeDef *htim, uint32_t Channel)\r
+{\r
+ uint32_t tmpsmcr;\r
+\r
+ /* Check the parameters */\r
+ assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));\r
+\r
+ /* Enable the Capture compare channel */\r
+ TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);\r
+\r
+ /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */\r
+ tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;\r
+ if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))\r
+ {\r
+ __HAL_TIM_ENABLE(htim);\r
+ }\r
+\r
+ /* Return function status */\r
+ return HAL_OK;\r
+}\r
+\r
+/**\r
+ * @brief Stops the PWM signal generation.\r
+ * @param htim TIM PWM handle\r
+ * @param Channel TIM Channels to be disabled\r
+ * This parameter can be one of the following values:\r
+ * @arg TIM_CHANNEL_1: TIM Channel 1 selected\r
+ * @arg TIM_CHANNEL_2: TIM Channel 2 selected\r
+ * @arg TIM_CHANNEL_3: TIM Channel 3 selected\r
+ * @arg TIM_CHANNEL_4: TIM Channel 4 selected\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_TIM_PWM_Stop(TIM_HandleTypeDef *htim, uint32_t Channel)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));\r
+\r
+ /* Disable the Capture compare channel */\r
+ TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);\r
+\r
+ /* Disable the Peripheral */\r
+ __HAL_TIM_DISABLE(htim);\r
+\r
+ /* Change the htim state */\r
+ htim->State = HAL_TIM_STATE_READY;\r
+\r
+ /* Return function status */\r
+ return HAL_OK;\r
+}\r
+\r
+/**\r
+ * @brief Starts the PWM signal generation in interrupt mode.\r
+ * @param htim TIM PWM handle\r
+ * @param Channel TIM Channel to be enabled\r
+ * This parameter can be one of the following values:\r
+ * @arg TIM_CHANNEL_1: TIM Channel 1 selected\r
+ * @arg TIM_CHANNEL_2: TIM Channel 2 selected\r
+ * @arg TIM_CHANNEL_3: TIM Channel 3 selected\r
+ * @arg TIM_CHANNEL_4: TIM Channel 4 selected\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_TIM_PWM_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel)\r
+{\r
+ uint32_t tmpsmcr;\r
+ /* Check the parameters */\r
+ assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));\r
+\r
+ switch (Channel)\r
+ {\r
+ case TIM_CHANNEL_1:\r
+ {\r
+ /* Enable the TIM Capture/Compare 1 interrupt */\r
+ __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1);\r
+ break;\r
+ }\r
+\r
+ case TIM_CHANNEL_2:\r
+ {\r
+ /* Enable the TIM Capture/Compare 2 interrupt */\r
+ __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2);\r
+ break;\r
+ }\r
+\r
+ case TIM_CHANNEL_3:\r
+ {\r
+ /* Enable the TIM Capture/Compare 3 interrupt */\r
+ __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC3);\r
+ break;\r
+ }\r
+\r
+ case TIM_CHANNEL_4:\r
+ {\r
+ /* Enable the TIM Capture/Compare 4 interrupt */\r
+ __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC4);\r
+ break;\r
+ }\r
+\r
+ default:\r
+ break;\r
+ }\r
+\r
+ /* Enable the Capture compare channel */\r
+ TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);\r
+\r
+ /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */\r
+ tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;\r
+ if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))\r
+ {\r
+ __HAL_TIM_ENABLE(htim);\r
+ }\r
+\r
+ /* Return function status */\r
+ return HAL_OK;\r
+}\r
+\r
+/**\r
+ * @brief Stops the PWM signal generation in interrupt mode.\r
+ * @param htim TIM PWM handle\r
+ * @param Channel TIM Channels to be disabled\r
+ * This parameter can be one of the following values:\r
+ * @arg TIM_CHANNEL_1: TIM Channel 1 selected\r
+ * @arg TIM_CHANNEL_2: TIM Channel 2 selected\r
+ * @arg TIM_CHANNEL_3: TIM Channel 3 selected\r
+ * @arg TIM_CHANNEL_4: TIM Channel 4 selected\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_TIM_PWM_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));\r
+\r
+ switch (Channel)\r
+ {\r
+ case TIM_CHANNEL_1:\r
+ {\r
+ /* Disable the TIM Capture/Compare 1 interrupt */\r
+ __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1);\r
+ break;\r
+ }\r
+\r
+ case TIM_CHANNEL_2:\r
+ {\r
+ /* Disable the TIM Capture/Compare 2 interrupt */\r
+ __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2);\r
+ break;\r
+ }\r
+\r
+ case TIM_CHANNEL_3:\r
+ {\r
+ /* Disable the TIM Capture/Compare 3 interrupt */\r
+ __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC3);\r
+ break;\r
+ }\r
+\r
+ case TIM_CHANNEL_4:\r
+ {\r
+ /* Disable the TIM Capture/Compare 4 interrupt */\r
+ __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC4);\r
+ break;\r
+ }\r
+\r
+ default:\r
+ break;\r
+ }\r
+\r
+ /* Disable the Capture compare channel */\r
+ TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);\r
+\r
+ /* Disable the Peripheral */\r
+ __HAL_TIM_DISABLE(htim);\r
+\r
+ /* Return function status */\r
+ return HAL_OK;\r
+}\r
+\r
+/**\r
+ * @brief Starts the TIM PWM signal generation in DMA mode.\r
+ * @param htim TIM PWM handle\r
+ * @param Channel TIM Channels to be enabled\r
+ * This parameter can be one of the following values:\r
+ * @arg TIM_CHANNEL_1: TIM Channel 1 selected\r
+ * @arg TIM_CHANNEL_2: TIM Channel 2 selected\r
+ * @arg TIM_CHANNEL_3: TIM Channel 3 selected\r
+ * @arg TIM_CHANNEL_4: TIM Channel 4 selected\r
+ * @param pData The source Buffer address.\r
+ * @param Length The length of data to be transferred from memory to TIM peripheral\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_TIM_PWM_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length)\r
+{\r
+ uint32_t tmpsmcr;\r
+\r
+ /* Check the parameters */\r
+ assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));\r
+\r
+ if ((htim->State == HAL_TIM_STATE_BUSY))\r
+ {\r
+ return HAL_BUSY;\r
+ }\r
+ else if ((htim->State == HAL_TIM_STATE_READY))\r
+ {\r
+ if ((pData == NULL) && (Length > 0U))\r
+ {\r
+ return HAL_ERROR;\r
+ }\r
+ else\r
+ {\r
+ htim->State = HAL_TIM_STATE_BUSY;\r
+ }\r
+ }\r
+ else\r
+ {\r
+ /* nothing to do */\r
+ }\r
+\r
+ switch (Channel)\r
+ {\r
+ case TIM_CHANNEL_1:\r
+ {\r
+ /* Set the DMA compare callbacks */\r
+ htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMADelayPulseCplt;\r
+ htim->hdma[TIM_DMA_ID_CC1]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt;\r
+\r
+ /* Set the DMA error callback */\r
+ htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ;\r
+\r
+ /* Enable the DMA channel */\r
+ if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)pData, (uint32_t)&htim->Instance->CCR1, Length) != HAL_OK)\r
+ {\r
+ return HAL_ERROR;\r
+ }\r
+\r
+ /* Enable the TIM Capture/Compare 1 DMA request */\r
+ __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1);\r
+ break;\r
+ }\r
+\r
+ case TIM_CHANNEL_2:\r
+ {\r
+ /* Set the DMA compare callbacks */\r
+ htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMADelayPulseCplt;\r
+ htim->hdma[TIM_DMA_ID_CC2]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt;\r
+\r
+ /* Set the DMA error callback */\r
+ htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError ;\r
+\r
+ /* Enable the DMA channel */\r
+ if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)pData, (uint32_t)&htim->Instance->CCR2, Length) != HAL_OK)\r
+ {\r
+ return HAL_ERROR;\r
+ }\r
+ /* Enable the TIM Capture/Compare 2 DMA request */\r
+ __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC2);\r
+ break;\r
+ }\r
+\r
+ case TIM_CHANNEL_3:\r
+ {\r
+ /* Set the DMA compare callbacks */\r
+ htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = TIM_DMADelayPulseCplt;\r
+ htim->hdma[TIM_DMA_ID_CC3]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt;\r
+\r
+ /* Set the DMA error callback */\r
+ htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = TIM_DMAError ;\r
+\r
+ /* Enable the DMA channel */\r
+ if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)pData, (uint32_t)&htim->Instance->CCR3, Length) != HAL_OK)\r
+ {\r
+ return HAL_ERROR;\r
+ }\r
+ /* Enable the TIM Output Capture/Compare 3 request */\r
+ __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC3);\r
+ break;\r
+ }\r
+\r
+ case TIM_CHANNEL_4:\r
+ {\r
+ /* Set the DMA compare callbacks */\r
+ htim->hdma[TIM_DMA_ID_CC4]->XferCpltCallback = TIM_DMADelayPulseCplt;\r
+ htim->hdma[TIM_DMA_ID_CC4]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt;\r
+\r
+ /* Set the DMA error callback */\r
+ htim->hdma[TIM_DMA_ID_CC4]->XferErrorCallback = TIM_DMAError ;\r
+\r
+ /* Enable the DMA channel */\r
+ if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)pData, (uint32_t)&htim->Instance->CCR4, Length) != HAL_OK)\r
+ {\r
+ return HAL_ERROR;\r
+ }\r
+ /* Enable the TIM Capture/Compare 4 DMA request */\r
+ __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC4);\r
+ break;\r
+ }\r
+\r
+ default:\r
+ break;\r
+ }\r
+\r
+ /* Enable the Capture compare channel */\r
+ TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);\r
+\r
+ /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */\r
+ tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;\r
+ if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))\r
+ {\r
+ __HAL_TIM_ENABLE(htim);\r
+ }\r
+\r
+ /* Return function status */\r
+ return HAL_OK;\r
+}\r
+\r
+/**\r
+ * @brief Stops the TIM PWM signal generation in DMA mode.\r
+ * @param htim TIM PWM handle\r
+ * @param Channel TIM Channels to be disabled\r
+ * This parameter can be one of the following values:\r
+ * @arg TIM_CHANNEL_1: TIM Channel 1 selected\r
+ * @arg TIM_CHANNEL_2: TIM Channel 2 selected\r
+ * @arg TIM_CHANNEL_3: TIM Channel 3 selected\r
+ * @arg TIM_CHANNEL_4: TIM Channel 4 selected\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_TIM_PWM_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));\r
+\r
+ switch (Channel)\r
+ {\r
+ case TIM_CHANNEL_1:\r
+ {\r
+ /* Disable the TIM Capture/Compare 1 DMA request */\r
+ __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1);\r
+ (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC1]);\r
+ break;\r
+ }\r
+\r
+ case TIM_CHANNEL_2:\r
+ {\r
+ /* Disable the TIM Capture/Compare 2 DMA request */\r
+ __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC2);\r
+ (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC2]);\r
+ break;\r
+ }\r
+\r
+ case TIM_CHANNEL_3:\r
+ {\r
+ /* Disable the TIM Capture/Compare 3 DMA request */\r
+ __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC3);\r
+ (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC3]);\r
+ break;\r
+ }\r
+\r
+ case TIM_CHANNEL_4:\r
+ {\r
+ /* Disable the TIM Capture/Compare 4 interrupt */\r
+ __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC4);\r
+ (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC4]);\r
+ break;\r
+ }\r
+\r
+ default:\r
+ break;\r
+ }\r
+\r
+ /* Disable the Capture compare channel */\r
+ TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);\r
+\r
+ /* Disable the Peripheral */\r
+ __HAL_TIM_DISABLE(htim);\r
+\r
+ /* Change the htim state */\r
+ htim->State = HAL_TIM_STATE_READY;\r
+\r
+ /* Return function status */\r
+ return HAL_OK;\r
+}\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup TIM_Exported_Functions_Group4 TIM Input Capture functions\r
+ * @brief TIM Input Capture functions\r
+ *\r
+@verbatim\r
+ ==============================================================================\r
+ ##### TIM Input Capture functions #####\r
+ ==============================================================================\r
+ [..]\r
+ This section provides functions allowing to:\r
+ (+) Initialize and configure the TIM Input Capture.\r
+ (+) De-initialize the TIM Input Capture.\r
+ (+) Start the TIM Input Capture.\r
+ (+) Stop the TIM Input Capture.\r
+ (+) Start the TIM Input Capture and enable interrupt.\r
+ (+) Stop the TIM Input Capture and disable interrupt.\r
+ (+) Start the TIM Input Capture and enable DMA transfer.\r
+ (+) Stop the TIM Input Capture and disable DMA transfer.\r
+\r
+@endverbatim\r
+ * @{\r
+ */\r
+/**\r
+ * @brief Initializes the TIM Input Capture Time base according to the specified\r
+ * parameters in the TIM_HandleTypeDef and initializes the associated handle.\r
+ * @note Switching from Center Aligned counter mode to Edge counter mode (or reverse)\r
+ * requires a timer reset to avoid unexpected direction\r
+ * due to DIR bit readonly in center aligned mode.\r
+ * Ex: call @ref HAL_TIM_IC_DeInit() before HAL_TIM_IC_Init()\r
+ * @param htim TIM Input Capture handle\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_TIM_IC_Init(TIM_HandleTypeDef *htim)\r
+{\r
+ /* Check the TIM handle allocation */\r
+ if (htim == NULL)\r
+ {\r
+ return HAL_ERROR;\r
+ }\r
+\r
+ /* Check the parameters */\r
+ assert_param(IS_TIM_INSTANCE(htim->Instance));\r
+ assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode));\r
+ assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision));\r
+ assert_param(IS_TIM_AUTORELOAD_PRELOAD(htim->Init.AutoReloadPreload));\r
+\r
+ if (htim->State == HAL_TIM_STATE_RESET)\r
+ {\r
+ /* Allocate lock resource and initialize it */\r
+ htim->Lock = HAL_UNLOCKED;\r
+\r
+#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)\r
+ /* Reset interrupt callbacks to legacy weak callbacks */\r
+ TIM_ResetCallback(htim);\r
+\r
+ if (htim->IC_MspInitCallback == NULL)\r
+ {\r
+ htim->IC_MspInitCallback = HAL_TIM_IC_MspInit;\r
+ }\r
+ /* Init the low level hardware : GPIO, CLOCK, NVIC */\r
+ htim->IC_MspInitCallback(htim);\r
+#else\r
+ /* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */\r
+ HAL_TIM_IC_MspInit(htim);\r
+#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */\r
+ }\r
+\r
+ /* Set the TIM state */\r
+ htim->State = HAL_TIM_STATE_BUSY;\r
+\r
+ /* Init the base time for the input capture */\r
+ TIM_Base_SetConfig(htim->Instance, &htim->Init);\r
+\r
+ /* Initialize the TIM state*/\r
+ htim->State = HAL_TIM_STATE_READY;\r
+\r
+ return HAL_OK;\r
+}\r
+\r
+/**\r
+ * @brief DeInitializes the TIM peripheral\r
+ * @param htim TIM Input Capture handle\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_TIM_IC_DeInit(TIM_HandleTypeDef *htim)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_TIM_INSTANCE(htim->Instance));\r
+\r
+ htim->State = HAL_TIM_STATE_BUSY;\r
+\r
+ /* Disable the TIM Peripheral Clock */\r
+ __HAL_TIM_DISABLE(htim);\r
+\r
+#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)\r
+ if (htim->IC_MspDeInitCallback == NULL)\r
+ {\r
+ htim->IC_MspDeInitCallback = HAL_TIM_IC_MspDeInit;\r
+ }\r
+ /* DeInit the low level hardware */\r
+ htim->IC_MspDeInitCallback(htim);\r
+#else\r
+ /* DeInit the low level hardware: GPIO, CLOCK, NVIC and DMA */\r
+ HAL_TIM_IC_MspDeInit(htim);\r
+#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */\r
+\r
+ /* Change TIM state */\r
+ htim->State = HAL_TIM_STATE_RESET;\r
+\r
+ /* Release Lock */\r
+ __HAL_UNLOCK(htim);\r
+\r
+ return HAL_OK;\r
+}\r
+\r
+/**\r
+ * @brief Initializes the TIM Input Capture MSP.\r
+ * @param htim TIM Input Capture handle\r
+ * @retval None\r
+ */\r
+__weak void HAL_TIM_IC_MspInit(TIM_HandleTypeDef *htim)\r
+{\r
+ /* Prevent unused argument(s) compilation warning */\r
+ UNUSED(htim);\r
+\r
+ /* NOTE : This function should not be modified, when the callback is needed,\r
+ the HAL_TIM_IC_MspInit could be implemented in the user file\r
+ */\r
+}\r
+\r
+/**\r
+ * @brief DeInitializes TIM Input Capture MSP.\r
+ * @param htim TIM handle\r
+ * @retval None\r
+ */\r
+__weak void HAL_TIM_IC_MspDeInit(TIM_HandleTypeDef *htim)\r
+{\r
+ /* Prevent unused argument(s) compilation warning */\r
+ UNUSED(htim);\r
+\r
+ /* NOTE : This function should not be modified, when the callback is needed,\r
+ the HAL_TIM_IC_MspDeInit could be implemented in the user file\r
+ */\r
+}\r
+\r
+/**\r
+ * @brief Starts the TIM Input Capture measurement.\r
+ * @param htim TIM Input Capture handle\r
+ * @param Channel TIM Channels to be enabled\r
+ * This parameter can be one of the following values:\r
+ * @arg TIM_CHANNEL_1: TIM Channel 1 selected\r
+ * @arg TIM_CHANNEL_2: TIM Channel 2 selected\r
+ * @arg TIM_CHANNEL_3: TIM Channel 3 selected\r
+ * @arg TIM_CHANNEL_4: TIM Channel 4 selected\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_TIM_IC_Start(TIM_HandleTypeDef *htim, uint32_t Channel)\r
+{\r
+ uint32_t tmpsmcr;\r
+\r
+ /* Check the parameters */\r
+ assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));\r
+\r
+ /* Enable the Input Capture channel */\r
+ TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);\r
+\r
+ /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */\r
+ tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;\r
+ if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))\r
+ {\r
+ __HAL_TIM_ENABLE(htim);\r
+ }\r
+\r
+ /* Return function status */\r
+ return HAL_OK;\r
+}\r
+\r
+/**\r
+ * @brief Stops the TIM Input Capture measurement.\r
+ * @param htim TIM Input Capture handle\r
+ * @param Channel TIM Channels to be disabled\r
+ * This parameter can be one of the following values:\r
+ * @arg TIM_CHANNEL_1: TIM Channel 1 selected\r
+ * @arg TIM_CHANNEL_2: TIM Channel 2 selected\r
+ * @arg TIM_CHANNEL_3: TIM Channel 3 selected\r
+ * @arg TIM_CHANNEL_4: TIM Channel 4 selected\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_TIM_IC_Stop(TIM_HandleTypeDef *htim, uint32_t Channel)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));\r
+\r
+ /* Disable the Input Capture channel */\r
+ TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);\r
+\r
+ /* Disable the Peripheral */\r
+ __HAL_TIM_DISABLE(htim);\r
+\r
+ /* Return function status */\r
+ return HAL_OK;\r
+}\r
+\r
+/**\r
+ * @brief Starts the TIM Input Capture measurement in interrupt mode.\r
+ * @param htim TIM Input Capture handle\r
+ * @param Channel TIM Channels to be enabled\r
+ * This parameter can be one of the following values:\r
+ * @arg TIM_CHANNEL_1: TIM Channel 1 selected\r
+ * @arg TIM_CHANNEL_2: TIM Channel 2 selected\r
+ * @arg TIM_CHANNEL_3: TIM Channel 3 selected\r
+ * @arg TIM_CHANNEL_4: TIM Channel 4 selected\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_TIM_IC_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel)\r
+{\r
+ uint32_t tmpsmcr;\r
+\r
+ /* Check the parameters */\r
+ assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));\r
+\r
+ switch (Channel)\r
+ {\r
+ case TIM_CHANNEL_1:\r
+ {\r
+ /* Enable the TIM Capture/Compare 1 interrupt */\r
+ __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1);\r
+ break;\r
+ }\r
+\r
+ case TIM_CHANNEL_2:\r
+ {\r
+ /* Enable the TIM Capture/Compare 2 interrupt */\r
+ __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2);\r
+ break;\r
+ }\r
+\r
+ case TIM_CHANNEL_3:\r
+ {\r
+ /* Enable the TIM Capture/Compare 3 interrupt */\r
+ __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC3);\r
+ break;\r
+ }\r
+\r
+ case TIM_CHANNEL_4:\r
+ {\r
+ /* Enable the TIM Capture/Compare 4 interrupt */\r
+ __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC4);\r
+ break;\r
+ }\r
+\r
+ default:\r
+ break;\r
+ }\r
+ /* Enable the Input Capture channel */\r
+ TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);\r
+\r
+ /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */\r
+ tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;\r
+ if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))\r
+ {\r
+ __HAL_TIM_ENABLE(htim);\r
+ }\r
+\r
+ /* Return function status */\r
+ return HAL_OK;\r
+}\r
+\r
+/**\r
+ * @brief Stops the TIM Input Capture measurement in interrupt mode.\r
+ * @param htim TIM Input Capture handle\r
+ * @param Channel TIM Channels to be disabled\r
+ * This parameter can be one of the following values:\r
+ * @arg TIM_CHANNEL_1: TIM Channel 1 selected\r
+ * @arg TIM_CHANNEL_2: TIM Channel 2 selected\r
+ * @arg TIM_CHANNEL_3: TIM Channel 3 selected\r
+ * @arg TIM_CHANNEL_4: TIM Channel 4 selected\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_TIM_IC_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));\r
+\r
+ switch (Channel)\r
+ {\r
+ case TIM_CHANNEL_1:\r
+ {\r
+ /* Disable the TIM Capture/Compare 1 interrupt */\r
+ __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1);\r
+ break;\r
+ }\r
+\r
+ case TIM_CHANNEL_2:\r
+ {\r
+ /* Disable the TIM Capture/Compare 2 interrupt */\r
+ __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2);\r
+ break;\r
+ }\r
+\r
+ case TIM_CHANNEL_3:\r
+ {\r
+ /* Disable the TIM Capture/Compare 3 interrupt */\r
+ __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC3);\r
+ break;\r
+ }\r
+\r
+ case TIM_CHANNEL_4:\r
+ {\r
+ /* Disable the TIM Capture/Compare 4 interrupt */\r
+ __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC4);\r
+ break;\r
+ }\r
+\r
+ default:\r
+ break;\r
+ }\r
+\r
+ /* Disable the Input Capture channel */\r
+ TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);\r
+\r
+ /* Disable the Peripheral */\r
+ __HAL_TIM_DISABLE(htim);\r
+\r
+ /* Return function status */\r
+ return HAL_OK;\r
+}\r
+\r
+/**\r
+ * @brief Starts the TIM Input Capture measurement in DMA mode.\r
+ * @param htim TIM Input Capture handle\r
+ * @param Channel TIM Channels to be enabled\r
+ * This parameter can be one of the following values:\r
+ * @arg TIM_CHANNEL_1: TIM Channel 1 selected\r
+ * @arg TIM_CHANNEL_2: TIM Channel 2 selected\r
+ * @arg TIM_CHANNEL_3: TIM Channel 3 selected\r
+ * @arg TIM_CHANNEL_4: TIM Channel 4 selected\r
+ * @param pData The destination Buffer address.\r
+ * @param Length The length of data to be transferred from TIM peripheral to memory.\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_TIM_IC_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length)\r
+{\r
+ uint32_t tmpsmcr;\r
+\r
+ /* Check the parameters */\r
+ assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));\r
+ assert_param(IS_TIM_DMA_CC_INSTANCE(htim->Instance));\r
+\r
+ if ((htim->State == HAL_TIM_STATE_BUSY))\r
+ {\r
+ return HAL_BUSY;\r
+ }\r
+ else if ((htim->State == HAL_TIM_STATE_READY))\r
+ {\r
+ if ((pData == NULL) && (Length > 0U))\r
+ {\r
+ return HAL_ERROR;\r
+ }\r
+ else\r
+ {\r
+ htim->State = HAL_TIM_STATE_BUSY;\r
+ }\r
+ }\r
+ else\r
+ {\r
+ /* nothing to do */\r
+ }\r
+\r
+ switch (Channel)\r
+ {\r
+ case TIM_CHANNEL_1:\r
+ {\r
+ /* Set the DMA capture callbacks */\r
+ htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMACaptureCplt;\r
+ htim->hdma[TIM_DMA_ID_CC1]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt;\r
+\r
+ /* Set the DMA error callback */\r
+ htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ;\r
+\r
+ /* Enable the DMA channel */\r
+ if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)&htim->Instance->CCR1, (uint32_t)pData, Length) != HAL_OK)\r
+ {\r
+ return HAL_ERROR;\r
+ }\r
+ /* Enable the TIM Capture/Compare 1 DMA request */\r
+ __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1);\r
+ break;\r
+ }\r
+\r
+ case TIM_CHANNEL_2:\r
+ {\r
+ /* Set the DMA capture callbacks */\r
+ htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMACaptureCplt;\r
+ htim->hdma[TIM_DMA_ID_CC2]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt;\r
+\r
+ /* Set the DMA error callback */\r
+ htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError ;\r
+\r
+ /* Enable the DMA channel */\r
+ if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)&htim->Instance->CCR2, (uint32_t)pData, Length) != HAL_OK)\r
+ {\r
+ return HAL_ERROR;\r
+ }\r
+ /* Enable the TIM Capture/Compare 2 DMA request */\r
+ __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC2);\r
+ break;\r
+ }\r
+\r
+ case TIM_CHANNEL_3:\r
+ {\r
+ /* Set the DMA capture callbacks */\r
+ htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = TIM_DMACaptureCplt;\r
+ htim->hdma[TIM_DMA_ID_CC3]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt;\r
+\r
+ /* Set the DMA error callback */\r
+ htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = TIM_DMAError ;\r
+\r
+ /* Enable the DMA channel */\r
+ if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)&htim->Instance->CCR3, (uint32_t)pData, Length) != HAL_OK)\r
+ {\r
+ return HAL_ERROR;\r
+ }\r
+ /* Enable the TIM Capture/Compare 3 DMA request */\r
+ __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC3);\r
+ break;\r
+ }\r
+\r
+ case TIM_CHANNEL_4:\r
+ {\r
+ /* Set the DMA capture callbacks */\r
+ htim->hdma[TIM_DMA_ID_CC4]->XferCpltCallback = TIM_DMACaptureCplt;\r
+ htim->hdma[TIM_DMA_ID_CC4]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt;\r
+\r
+ /* Set the DMA error callback */\r
+ htim->hdma[TIM_DMA_ID_CC4]->XferErrorCallback = TIM_DMAError ;\r
+\r
+ /* Enable the DMA channel */\r
+ if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)&htim->Instance->CCR4, (uint32_t)pData, Length) != HAL_OK)\r
+ {\r
+ return HAL_ERROR;\r
+ }\r
+ /* Enable the TIM Capture/Compare 4 DMA request */\r
+ __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC4);\r
+ break;\r
+ }\r
+\r
+ default:\r
+ break;\r
+ }\r
+\r
+ /* Enable the Input Capture channel */\r
+ TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);\r
+\r
+ /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */\r
+ tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;\r
+ if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))\r
+ {\r
+ __HAL_TIM_ENABLE(htim);\r
+ }\r
+\r
+ /* Return function status */\r
+ return HAL_OK;\r
+}\r
+\r
+/**\r
+ * @brief Stops the TIM Input Capture measurement in DMA mode.\r
+ * @param htim TIM Input Capture handle\r
+ * @param Channel TIM Channels to be disabled\r
+ * This parameter can be one of the following values:\r
+ * @arg TIM_CHANNEL_1: TIM Channel 1 selected\r
+ * @arg TIM_CHANNEL_2: TIM Channel 2 selected\r
+ * @arg TIM_CHANNEL_3: TIM Channel 3 selected\r
+ * @arg TIM_CHANNEL_4: TIM Channel 4 selected\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_TIM_IC_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));\r
+ assert_param(IS_TIM_DMA_CC_INSTANCE(htim->Instance));\r
+\r
+ switch (Channel)\r
+ {\r
+ case TIM_CHANNEL_1:\r
+ {\r
+ /* Disable the TIM Capture/Compare 1 DMA request */\r
+ __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1);\r
+ (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC1]);\r
+ break;\r
+ }\r
+\r
+ case TIM_CHANNEL_2:\r
+ {\r
+ /* Disable the TIM Capture/Compare 2 DMA request */\r
+ __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC2);\r
+ (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC2]);\r
+ break;\r
+ }\r
+\r
+ case TIM_CHANNEL_3:\r
+ {\r
+ /* Disable the TIM Capture/Compare 3 DMA request */\r
+ __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC3);\r
+ (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC3]);\r
+ break;\r
+ }\r
+\r
+ case TIM_CHANNEL_4:\r
+ {\r
+ /* Disable the TIM Capture/Compare 4 DMA request */\r
+ __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC4);\r
+ (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC4]);\r
+ break;\r
+ }\r
+\r
+ default:\r
+ break;\r
+ }\r
+\r
+ /* Disable the Input Capture channel */\r
+ TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);\r
+\r
+ /* Disable the Peripheral */\r
+ __HAL_TIM_DISABLE(htim);\r
+\r
+ /* Change the htim state */\r
+ htim->State = HAL_TIM_STATE_READY;\r
+\r
+ /* Return function status */\r
+ return HAL_OK;\r
+}\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup TIM_Exported_Functions_Group5 TIM One Pulse functions\r
+ * @brief TIM One Pulse functions\r
+ *\r
+@verbatim\r
+ ==============================================================================\r
+ ##### TIM One Pulse functions #####\r
+ ==============================================================================\r
+ [..]\r
+ This section provides functions allowing to:\r
+ (+) Initialize and configure the TIM One Pulse.\r
+ (+) De-initialize the TIM One Pulse.\r
+ (+) Start the TIM One Pulse.\r
+ (+) Stop the TIM One Pulse.\r
+ (+) Start the TIM One Pulse and enable interrupt.\r
+ (+) Stop the TIM One Pulse and disable interrupt.\r
+ (+) Start the TIM One Pulse and enable DMA transfer.\r
+ (+) Stop the TIM One Pulse and disable DMA transfer.\r
+\r
+@endverbatim\r
+ * @{\r
+ */\r
+/**\r
+ * @brief Initializes the TIM One Pulse Time Base according to the specified\r
+ * parameters in the TIM_HandleTypeDef and initializes the associated handle.\r
+ * @note Switching from Center Aligned counter mode to Edge counter mode (or reverse)\r
+ * requires a timer reset to avoid unexpected direction\r
+ * due to DIR bit readonly in center aligned mode.\r
+ * Ex: call @ref HAL_TIM_OnePulse_DeInit() before HAL_TIM_OnePulse_Init()\r
+ * @param htim TIM One Pulse handle\r
+ * @param OnePulseMode Select the One pulse mode.\r
+ * This parameter can be one of the following values:\r
+ * @arg TIM_OPMODE_SINGLE: Only one pulse will be generated.\r
+ * @arg TIM_OPMODE_REPETITIVE: Repetitive pulses will be generated.\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_TIM_OnePulse_Init(TIM_HandleTypeDef *htim, uint32_t OnePulseMode)\r
+{\r
+ /* Check the TIM handle allocation */\r
+ if (htim == NULL)\r
+ {\r
+ return HAL_ERROR;\r
+ }\r
+\r
+ /* Check the parameters */\r
+ assert_param(IS_TIM_INSTANCE(htim->Instance));\r
+ assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode));\r
+ assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision));\r
+ assert_param(IS_TIM_OPM_MODE(OnePulseMode));\r
+ assert_param(IS_TIM_AUTORELOAD_PRELOAD(htim->Init.AutoReloadPreload));\r
+\r
+ if (htim->State == HAL_TIM_STATE_RESET)\r
+ {\r
+ /* Allocate lock resource and initialize it */\r
+ htim->Lock = HAL_UNLOCKED;\r
+\r
+#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)\r
+ /* Reset interrupt callbacks to legacy weak callbacks */\r
+ TIM_ResetCallback(htim);\r
+\r
+ if (htim->OnePulse_MspInitCallback == NULL)\r
+ {\r
+ htim->OnePulse_MspInitCallback = HAL_TIM_OnePulse_MspInit;\r
+ }\r
+ /* Init the low level hardware : GPIO, CLOCK, NVIC */\r
+ htim->OnePulse_MspInitCallback(htim);\r
+#else\r
+ /* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */\r
+ HAL_TIM_OnePulse_MspInit(htim);\r
+#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */\r
+ }\r
+\r
+ /* Set the TIM state */\r
+ htim->State = HAL_TIM_STATE_BUSY;\r
+\r
+ /* Configure the Time base in the One Pulse Mode */\r
+ TIM_Base_SetConfig(htim->Instance, &htim->Init);\r
+\r
+ /* Reset the OPM Bit */\r
+ htim->Instance->CR1 &= ~TIM_CR1_OPM;\r
+\r
+ /* Configure the OPM Mode */\r
+ htim->Instance->CR1 |= OnePulseMode;\r
+\r
+ /* Initialize the TIM state*/\r
+ htim->State = HAL_TIM_STATE_READY;\r
+\r
+ return HAL_OK;\r
+}\r
+\r
+/**\r
+ * @brief DeInitializes the TIM One Pulse\r
+ * @param htim TIM One Pulse handle\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_TIM_OnePulse_DeInit(TIM_HandleTypeDef *htim)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_TIM_INSTANCE(htim->Instance));\r
+\r
+ htim->State = HAL_TIM_STATE_BUSY;\r
+\r
+ /* Disable the TIM Peripheral Clock */\r
+ __HAL_TIM_DISABLE(htim);\r
+\r
+#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)\r
+ if (htim->OnePulse_MspDeInitCallback == NULL)\r
+ {\r
+ htim->OnePulse_MspDeInitCallback = HAL_TIM_OnePulse_MspDeInit;\r
+ }\r
+ /* DeInit the low level hardware */\r
+ htim->OnePulse_MspDeInitCallback(htim);\r
+#else\r
+ /* DeInit the low level hardware: GPIO, CLOCK, NVIC */\r
+ HAL_TIM_OnePulse_MspDeInit(htim);\r
+#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */\r
+\r
+ /* Change TIM state */\r
+ htim->State = HAL_TIM_STATE_RESET;\r
+\r
+ /* Release Lock */\r
+ __HAL_UNLOCK(htim);\r
+\r
+ return HAL_OK;\r
+}\r
+\r
+/**\r
+ * @brief Initializes the TIM One Pulse MSP.\r
+ * @param htim TIM One Pulse handle\r
+ * @retval None\r
+ */\r
+__weak void HAL_TIM_OnePulse_MspInit(TIM_HandleTypeDef *htim)\r
+{\r
+ /* Prevent unused argument(s) compilation warning */\r
+ UNUSED(htim);\r
+\r
+ /* NOTE : This function should not be modified, when the callback is needed,\r
+ the HAL_TIM_OnePulse_MspInit could be implemented in the user file\r
+ */\r
+}\r
+\r
+/**\r
+ * @brief DeInitializes TIM One Pulse MSP.\r
+ * @param htim TIM One Pulse handle\r
+ * @retval None\r
+ */\r
+__weak void HAL_TIM_OnePulse_MspDeInit(TIM_HandleTypeDef *htim)\r
+{\r
+ /* Prevent unused argument(s) compilation warning */\r
+ UNUSED(htim);\r
+\r
+ /* NOTE : This function should not be modified, when the callback is needed,\r
+ the HAL_TIM_OnePulse_MspDeInit could be implemented in the user file\r
+ */\r
+}\r
+\r
+/**\r
+ * @brief Starts the TIM One Pulse signal generation.\r
+ * @param htim TIM One Pulse handle\r
+ * @param OutputChannel TIM Channels to be enabled\r
+ * This parameter can be one of the following values:\r
+ * @arg TIM_CHANNEL_1: TIM Channel 1 selected\r
+ * @arg TIM_CHANNEL_2: TIM Channel 2 selected\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_TIM_OnePulse_Start(TIM_HandleTypeDef *htim, uint32_t OutputChannel)\r
+{\r
+ /* Prevent unused argument(s) compilation warning */\r
+ UNUSED(OutputChannel);\r
+\r
+ /* Enable the Capture compare and the Input Capture channels\r
+ (in the OPM Mode the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2)\r
+ if TIM_CHANNEL_1 is used as output, the TIM_CHANNEL_2 will be used as input and\r
+ if TIM_CHANNEL_1 is used as input, the TIM_CHANNEL_2 will be used as output\r
+ in all combinations, the TIM_CHANNEL_1 and TIM_CHANNEL_2 should be enabled together\r
+\r
+ No need to enable the counter, it's enabled automatically by hardware\r
+ (the counter starts in response to a stimulus and generate a pulse */\r
+\r
+ TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);\r
+ TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE);\r
+\r
+ /* Return function status */\r
+ return HAL_OK;\r
+}\r
+\r
+/**\r
+ * @brief Stops the TIM One Pulse signal generation.\r
+ * @param htim TIM One Pulse handle\r
+ * @param OutputChannel TIM Channels to be disable\r
+ * This parameter can be one of the following values:\r
+ * @arg TIM_CHANNEL_1: TIM Channel 1 selected\r
+ * @arg TIM_CHANNEL_2: TIM Channel 2 selected\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_TIM_OnePulse_Stop(TIM_HandleTypeDef *htim, uint32_t OutputChannel)\r
+{\r
+ /* Prevent unused argument(s) compilation warning */\r
+ UNUSED(OutputChannel);\r
+\r
+ /* Disable the Capture compare and the Input Capture channels\r
+ (in the OPM Mode the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2)\r
+ if TIM_CHANNEL_1 is used as output, the TIM_CHANNEL_2 will be used as input and\r
+ if TIM_CHANNEL_1 is used as input, the TIM_CHANNEL_2 will be used as output\r
+ in all combinations, the TIM_CHANNEL_1 and TIM_CHANNEL_2 should be disabled together */\r
+\r
+ TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);\r
+ TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE);\r
+\r
+ /* Disable the Peripheral */\r
+ __HAL_TIM_DISABLE(htim);\r
+\r
+ /* Return function status */\r
+ return HAL_OK;\r
+}\r
+\r
+/**\r
+ * @brief Starts the TIM One Pulse signal generation in interrupt mode.\r
+ * @param htim TIM One Pulse handle\r
+ * @param OutputChannel TIM Channels to be enabled\r
+ * This parameter can be one of the following values:\r
+ * @arg TIM_CHANNEL_1: TIM Channel 1 selected\r
+ * @arg TIM_CHANNEL_2: TIM Channel 2 selected\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_TIM_OnePulse_Start_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel)\r
+{\r
+ /* Prevent unused argument(s) compilation warning */\r
+ UNUSED(OutputChannel);\r
+\r
+ /* Enable the Capture compare and the Input Capture channels\r
+ (in the OPM Mode the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2)\r
+ if TIM_CHANNEL_1 is used as output, the TIM_CHANNEL_2 will be used as input and\r
+ if TIM_CHANNEL_1 is used as input, the TIM_CHANNEL_2 will be used as output\r
+ in all combinations, the TIM_CHANNEL_1 and TIM_CHANNEL_2 should be enabled together\r
+\r
+ No need to enable the counter, it's enabled automatically by hardware\r
+ (the counter starts in response to a stimulus and generate a pulse */\r
+\r
+ /* Enable the TIM Capture/Compare 1 interrupt */\r
+ __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1);\r
+\r
+ /* Enable the TIM Capture/Compare 2 interrupt */\r
+ __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2);\r
+\r
+ TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);\r
+ TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE);\r
+\r
+ /* Return function status */\r
+ return HAL_OK;\r
+}\r
+\r
+/**\r
+ * @brief Stops the TIM One Pulse signal generation in interrupt mode.\r
+ * @param htim TIM One Pulse handle\r
+ * @param OutputChannel TIM Channels to be enabled\r
+ * This parameter can be one of the following values:\r
+ * @arg TIM_CHANNEL_1: TIM Channel 1 selected\r
+ * @arg TIM_CHANNEL_2: TIM Channel 2 selected\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_TIM_OnePulse_Stop_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel)\r
+{\r
+ /* Prevent unused argument(s) compilation warning */\r
+ UNUSED(OutputChannel);\r
+\r
+ /* Disable the TIM Capture/Compare 1 interrupt */\r
+ __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1);\r
+\r
+ /* Disable the TIM Capture/Compare 2 interrupt */\r
+ __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2);\r
+\r
+ /* Disable the Capture compare and the Input Capture channels\r
+ (in the OPM Mode the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2)\r
+ if TIM_CHANNEL_1 is used as output, the TIM_CHANNEL_2 will be used as input and\r
+ if TIM_CHANNEL_1 is used as input, the TIM_CHANNEL_2 will be used as output\r
+ in all combinations, the TIM_CHANNEL_1 and TIM_CHANNEL_2 should be disabled together */\r
+ TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);\r
+ TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE);\r
+\r
+ /* Disable the Peripheral */\r
+ __HAL_TIM_DISABLE(htim);\r
+\r
+ /* Return function status */\r
+ return HAL_OK;\r
+}\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup TIM_Exported_Functions_Group6 TIM Encoder functions\r
+ * @brief TIM Encoder functions\r
+ *\r
+@verbatim\r
+ ==============================================================================\r
+ ##### TIM Encoder functions #####\r
+ ==============================================================================\r
+ [..]\r
+ This section provides functions allowing to:\r
+ (+) Initialize and configure the TIM Encoder.\r
+ (+) De-initialize the TIM Encoder.\r
+ (+) Start the TIM Encoder.\r
+ (+) Stop the TIM Encoder.\r
+ (+) Start the TIM Encoder and enable interrupt.\r
+ (+) Stop the TIM Encoder and disable interrupt.\r
+ (+) Start the TIM Encoder and enable DMA transfer.\r
+ (+) Stop the TIM Encoder and disable DMA transfer.\r
+\r
+@endverbatim\r
+ * @{\r
+ */\r
+/**\r
+ * @brief Initializes the TIM Encoder Interface and initialize the associated handle.\r
+ * @note Switching from Center Aligned counter mode to Edge counter mode (or reverse)\r
+ * requires a timer reset to avoid unexpected direction\r
+ * due to DIR bit readonly in center aligned mode.\r
+ * Ex: call @ref HAL_TIM_Encoder_DeInit() before HAL_TIM_Encoder_Init()\r
+ * @note Encoder mode and External clock mode 2 are not compatible and must not be selected together\r
+ * Ex: A call for @ref HAL_TIM_Encoder_Init will erase the settings of @ref HAL_TIM_ConfigClockSource\r
+ * using TIM_CLOCKSOURCE_ETRMODE2 and vice versa\r
+ * @param htim TIM Encoder Interface handle\r
+ * @param sConfig TIM Encoder Interface configuration structure\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_TIM_Encoder_Init(TIM_HandleTypeDef *htim, TIM_Encoder_InitTypeDef *sConfig)\r
+{\r
+ uint32_t tmpsmcr;\r
+ uint32_t tmpccmr1;\r
+ uint32_t tmpccer;\r
+\r
+ /* Check the TIM handle allocation */\r
+ if (htim == NULL)\r
+ {\r
+ return HAL_ERROR;\r
+ }\r
+\r
+ /* Check the parameters */\r
+ assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode));\r
+ assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision));\r
+ assert_param(IS_TIM_AUTORELOAD_PRELOAD(htim->Init.AutoReloadPreload));\r
+ assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));\r
+ assert_param(IS_TIM_ENCODER_MODE(sConfig->EncoderMode));\r
+ assert_param(IS_TIM_IC_SELECTION(sConfig->IC1Selection));\r
+ assert_param(IS_TIM_IC_SELECTION(sConfig->IC2Selection));\r
+ assert_param(IS_TIM_IC_POLARITY(sConfig->IC1Polarity));\r
+ assert_param(IS_TIM_IC_POLARITY(sConfig->IC2Polarity));\r
+ assert_param(IS_TIM_IC_PRESCALER(sConfig->IC1Prescaler));\r
+ assert_param(IS_TIM_IC_PRESCALER(sConfig->IC2Prescaler));\r
+ assert_param(IS_TIM_IC_FILTER(sConfig->IC1Filter));\r
+ assert_param(IS_TIM_IC_FILTER(sConfig->IC2Filter));\r
+\r
+ if (htim->State == HAL_TIM_STATE_RESET)\r
+ {\r
+ /* Allocate lock resource and initialize it */\r
+ htim->Lock = HAL_UNLOCKED;\r
+\r
+#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)\r
+ /* Reset interrupt callbacks to legacy weak callbacks */\r
+ TIM_ResetCallback(htim);\r
+\r
+ if (htim->Encoder_MspInitCallback == NULL)\r
+ {\r
+ htim->Encoder_MspInitCallback = HAL_TIM_Encoder_MspInit;\r
+ }\r
+ /* Init the low level hardware : GPIO, CLOCK, NVIC */\r
+ htim->Encoder_MspInitCallback(htim);\r
+#else\r
+ /* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */\r
+ HAL_TIM_Encoder_MspInit(htim);\r
+#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */\r
+ }\r
+\r
+ /* Set the TIM state */\r
+ htim->State = HAL_TIM_STATE_BUSY;\r
+\r
+ /* Reset the SMS and ECE bits */\r
+ htim->Instance->SMCR &= ~(TIM_SMCR_SMS | TIM_SMCR_ECE);\r
+\r
+ /* Configure the Time base in the Encoder Mode */\r
+ TIM_Base_SetConfig(htim->Instance, &htim->Init);\r
+\r
+ /* Get the TIMx SMCR register value */\r
+ tmpsmcr = htim->Instance->SMCR;\r
+\r
+ /* Get the TIMx CCMR1 register value */\r
+ tmpccmr1 = htim->Instance->CCMR1;\r
+\r
+ /* Get the TIMx CCER register value */\r
+ tmpccer = htim->Instance->CCER;\r
+\r
+ /* Set the encoder Mode */\r
+ tmpsmcr |= sConfig->EncoderMode;\r
+\r
+ /* Select the Capture Compare 1 and the Capture Compare 2 as input */\r
+ tmpccmr1 &= ~(TIM_CCMR1_CC1S | TIM_CCMR1_CC2S);\r
+ tmpccmr1 |= (sConfig->IC1Selection | (sConfig->IC2Selection << 8U));\r
+\r
+ /* Set the Capture Compare 1 and the Capture Compare 2 prescalers and filters */\r
+ tmpccmr1 &= ~(TIM_CCMR1_IC1PSC | TIM_CCMR1_IC2PSC);\r
+ tmpccmr1 &= ~(TIM_CCMR1_IC1F | TIM_CCMR1_IC2F);\r
+ tmpccmr1 |= sConfig->IC1Prescaler | (sConfig->IC2Prescaler << 8U);\r
+ tmpccmr1 |= (sConfig->IC1Filter << 4U) | (sConfig->IC2Filter << 12U);\r
+\r
+ /* Set the TI1 and the TI2 Polarities */\r
+ tmpccer &= ~(TIM_CCER_CC1P | TIM_CCER_CC2P);\r
+ tmpccer &= ~(TIM_CCER_CC1NP | TIM_CCER_CC2NP);\r
+ tmpccer |= sConfig->IC1Polarity | (sConfig->IC2Polarity << 4U);\r
+\r
+ /* Write to TIMx SMCR */\r
+ htim->Instance->SMCR = tmpsmcr;\r
+\r
+ /* Write to TIMx CCMR1 */\r
+ htim->Instance->CCMR1 = tmpccmr1;\r
+\r
+ /* Write to TIMx CCER */\r
+ htim->Instance->CCER = tmpccer;\r
+\r
+ /* Initialize the TIM state*/\r
+ htim->State = HAL_TIM_STATE_READY;\r
+\r
+ return HAL_OK;\r
+}\r
+\r
+\r
+/**\r
+ * @brief DeInitializes the TIM Encoder interface\r
+ * @param htim TIM Encoder Interface handle\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_TIM_Encoder_DeInit(TIM_HandleTypeDef *htim)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_TIM_INSTANCE(htim->Instance));\r
+\r
+ htim->State = HAL_TIM_STATE_BUSY;\r
+\r
+ /* Disable the TIM Peripheral Clock */\r
+ __HAL_TIM_DISABLE(htim);\r
+\r
+#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)\r
+ if (htim->Encoder_MspDeInitCallback == NULL)\r
+ {\r
+ htim->Encoder_MspDeInitCallback = HAL_TIM_Encoder_MspDeInit;\r
+ }\r
+ /* DeInit the low level hardware */\r
+ htim->Encoder_MspDeInitCallback(htim);\r
+#else\r
+ /* DeInit the low level hardware: GPIO, CLOCK, NVIC */\r
+ HAL_TIM_Encoder_MspDeInit(htim);\r
+#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */\r
+\r
+ /* Change TIM state */\r
+ htim->State = HAL_TIM_STATE_RESET;\r
+\r
+ /* Release Lock */\r
+ __HAL_UNLOCK(htim);\r
+\r
+ return HAL_OK;\r
+}\r
+\r
+/**\r
+ * @brief Initializes the TIM Encoder Interface MSP.\r
+ * @param htim TIM Encoder Interface handle\r
+ * @retval None\r
+ */\r
+__weak void HAL_TIM_Encoder_MspInit(TIM_HandleTypeDef *htim)\r
+{\r
+ /* Prevent unused argument(s) compilation warning */\r
+ UNUSED(htim);\r
+\r
+ /* NOTE : This function should not be modified, when the callback is needed,\r
+ the HAL_TIM_Encoder_MspInit could be implemented in the user file\r
+ */\r
+}\r
+\r
+/**\r
+ * @brief DeInitializes TIM Encoder Interface MSP.\r
+ * @param htim TIM Encoder Interface handle\r
+ * @retval None\r
+ */\r
+__weak void HAL_TIM_Encoder_MspDeInit(TIM_HandleTypeDef *htim)\r
+{\r
+ /* Prevent unused argument(s) compilation warning */\r
+ UNUSED(htim);\r
+\r
+ /* NOTE : This function should not be modified, when the callback is needed,\r
+ the HAL_TIM_Encoder_MspDeInit could be implemented in the user file\r
+ */\r
+}\r
+\r
+/**\r
+ * @brief Starts the TIM Encoder Interface.\r
+ * @param htim TIM Encoder Interface handle\r
+ * @param Channel TIM Channels to be enabled\r
+ * This parameter can be one of the following values:\r
+ * @arg TIM_CHANNEL_1: TIM Channel 1 selected\r
+ * @arg TIM_CHANNEL_2: TIM Channel 2 selected\r
+ * @arg TIM_CHANNEL_ALL: TIM Channel 1 and TIM Channel 2 are selected\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_TIM_Encoder_Start(TIM_HandleTypeDef *htim, uint32_t Channel)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));\r
+\r
+ /* Enable the encoder interface channels */\r
+ switch (Channel)\r
+ {\r
+ case TIM_CHANNEL_1:\r
+ {\r
+ TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);\r
+ break;\r
+ }\r
+\r
+ case TIM_CHANNEL_2:\r
+ {\r
+ TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE);\r
+ break;\r
+ }\r
+\r
+ default :\r
+ {\r
+ TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);\r
+ TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE);\r
+ break;\r
+ }\r
+ }\r
+ /* Enable the Peripheral */\r
+ __HAL_TIM_ENABLE(htim);\r
+\r
+ /* Return function status */\r
+ return HAL_OK;\r
+}\r
+\r
+/**\r
+ * @brief Stops the TIM Encoder Interface.\r
+ * @param htim TIM Encoder Interface handle\r
+ * @param Channel TIM Channels to be disabled\r
+ * This parameter can be one of the following values:\r
+ * @arg TIM_CHANNEL_1: TIM Channel 1 selected\r
+ * @arg TIM_CHANNEL_2: TIM Channel 2 selected\r
+ * @arg TIM_CHANNEL_ALL: TIM Channel 1 and TIM Channel 2 are selected\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_TIM_Encoder_Stop(TIM_HandleTypeDef *htim, uint32_t Channel)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));\r
+\r
+ /* Disable the Input Capture channels 1 and 2\r
+ (in the EncoderInterface the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2) */\r
+ switch (Channel)\r
+ {\r
+ case TIM_CHANNEL_1:\r
+ {\r
+ TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);\r
+ break;\r
+ }\r
+\r
+ case TIM_CHANNEL_2:\r
+ {\r
+ TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE);\r
+ break;\r
+ }\r
+\r
+ default :\r
+ {\r
+ TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);\r
+ TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE);\r
+ break;\r
+ }\r
+ }\r
+\r
+ /* Disable the Peripheral */\r
+ __HAL_TIM_DISABLE(htim);\r
+\r
+ /* Return function status */\r
+ return HAL_OK;\r
+}\r
+\r
+/**\r
+ * @brief Starts the TIM Encoder Interface in interrupt mode.\r
+ * @param htim TIM Encoder Interface handle\r
+ * @param Channel TIM Channels to be enabled\r
+ * This parameter can be one of the following values:\r
+ * @arg TIM_CHANNEL_1: TIM Channel 1 selected\r
+ * @arg TIM_CHANNEL_2: TIM Channel 2 selected\r
+ * @arg TIM_CHANNEL_ALL: TIM Channel 1 and TIM Channel 2 are selected\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_TIM_Encoder_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));\r
+\r
+ /* Enable the encoder interface channels */\r
+ /* Enable the capture compare Interrupts 1 and/or 2 */\r
+ switch (Channel)\r
+ {\r
+ case TIM_CHANNEL_1:\r
+ {\r
+ TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);\r
+ __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1);\r
+ break;\r
+ }\r
+\r
+ case TIM_CHANNEL_2:\r
+ {\r
+ TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE);\r
+ __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2);\r
+ break;\r
+ }\r
+\r
+ default :\r
+ {\r
+ TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);\r
+ TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE);\r
+ __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1);\r
+ __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2);\r
+ break;\r
+ }\r
+ }\r
+\r
+ /* Enable the Peripheral */\r
+ __HAL_TIM_ENABLE(htim);\r
+\r
+ /* Return function status */\r
+ return HAL_OK;\r
+}\r
+\r
+/**\r
+ * @brief Stops the TIM Encoder Interface in interrupt mode.\r
+ * @param htim TIM Encoder Interface handle\r
+ * @param Channel TIM Channels to be disabled\r
+ * This parameter can be one of the following values:\r
+ * @arg TIM_CHANNEL_1: TIM Channel 1 selected\r
+ * @arg TIM_CHANNEL_2: TIM Channel 2 selected\r
+ * @arg TIM_CHANNEL_ALL: TIM Channel 1 and TIM Channel 2 are selected\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_TIM_Encoder_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));\r
+\r
+ /* Disable the Input Capture channels 1 and 2\r
+ (in the EncoderInterface the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2) */\r
+ if (Channel == TIM_CHANNEL_1)\r
+ {\r
+ TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);\r
+\r
+ /* Disable the capture compare Interrupts 1 */\r
+ __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1);\r
+ }\r
+ else if (Channel == TIM_CHANNEL_2)\r
+ {\r
+ TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE);\r
+\r
+ /* Disable the capture compare Interrupts 2 */\r
+ __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2);\r
+ }\r
+ else\r
+ {\r
+ TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);\r
+ TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE);\r
+\r
+ /* Disable the capture compare Interrupts 1 and 2 */\r
+ __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1);\r
+ __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2);\r
+ }\r
+\r
+ /* Disable the Peripheral */\r
+ __HAL_TIM_DISABLE(htim);\r
+\r
+ /* Change the htim state */\r
+ htim->State = HAL_TIM_STATE_READY;\r
+\r
+ /* Return function status */\r
+ return HAL_OK;\r
+}\r
+\r
+/**\r
+ * @brief Starts the TIM Encoder Interface in DMA mode.\r
+ * @param htim TIM Encoder Interface handle\r
+ * @param Channel TIM Channels to be enabled\r
+ * This parameter can be one of the following values:\r
+ * @arg TIM_CHANNEL_1: TIM Channel 1 selected\r
+ * @arg TIM_CHANNEL_2: TIM Channel 2 selected\r
+ * @arg TIM_CHANNEL_ALL: TIM Channel 1 and TIM Channel 2 are selected\r
+ * @param pData1 The destination Buffer address for IC1.\r
+ * @param pData2 The destination Buffer address for IC2.\r
+ * @param Length The length of data to be transferred from TIM peripheral to memory.\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_TIM_Encoder_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData1, uint32_t *pData2, uint16_t Length)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_TIM_DMA_CC_INSTANCE(htim->Instance));\r
+\r
+ if ((htim->State == HAL_TIM_STATE_BUSY))\r
+ {\r
+ return HAL_BUSY;\r
+ }\r
+ else if ((htim->State == HAL_TIM_STATE_READY))\r
+ {\r
+ if ((((pData1 == NULL) || (pData2 == NULL))) && (Length > 0U))\r
+ {\r
+ return HAL_ERROR;\r
+ }\r
+ else\r
+ {\r
+ htim->State = HAL_TIM_STATE_BUSY;\r
+ }\r
+ }\r
+ else\r
+ {\r
+ /* nothing to do */\r
+ }\r
+\r
+ switch (Channel)\r
+ {\r
+ case TIM_CHANNEL_1:\r
+ {\r
+ /* Set the DMA capture callbacks */\r
+ htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMACaptureCplt;\r
+ htim->hdma[TIM_DMA_ID_CC1]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt;\r
+\r
+ /* Set the DMA error callback */\r
+ htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ;\r
+\r
+ /* Enable the DMA channel */\r
+ if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)&htim->Instance->CCR1, (uint32_t)pData1, Length) != HAL_OK)\r
+ {\r
+ return HAL_ERROR;\r
+ }\r
+ /* Enable the TIM Input Capture DMA request */\r
+ __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1);\r
+\r
+ /* Enable the Peripheral */\r
+ __HAL_TIM_ENABLE(htim);\r
+\r
+ /* Enable the Capture compare channel */\r
+ TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);\r
+ break;\r
+ }\r
+\r
+ case TIM_CHANNEL_2:\r
+ {\r
+ /* Set the DMA capture callbacks */\r
+ htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMACaptureCplt;\r
+ htim->hdma[TIM_DMA_ID_CC2]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt;\r
+\r
+ /* Set the DMA error callback */\r
+ htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError;\r
+ /* Enable the DMA channel */\r
+ if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)&htim->Instance->CCR2, (uint32_t)pData2, Length) != HAL_OK)\r
+ {\r
+ return HAL_ERROR;\r
+ }\r
+ /* Enable the TIM Input Capture DMA request */\r
+ __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC2);\r
+\r
+ /* Enable the Peripheral */\r
+ __HAL_TIM_ENABLE(htim);\r
+\r
+ /* Enable the Capture compare channel */\r
+ TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE);\r
+ break;\r
+ }\r
+\r
+ case TIM_CHANNEL_ALL:\r
+ {\r
+ /* Set the DMA capture callbacks */\r
+ htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMACaptureCplt;\r
+ htim->hdma[TIM_DMA_ID_CC1]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt;\r
+\r
+ /* Set the DMA error callback */\r
+ htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ;\r
+\r
+ /* Enable the DMA channel */\r
+ if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)&htim->Instance->CCR1, (uint32_t)pData1, Length) != HAL_OK)\r
+ {\r
+ return HAL_ERROR;\r
+ }\r
+\r
+ /* Set the DMA capture callbacks */\r
+ htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMACaptureCplt;\r
+ htim->hdma[TIM_DMA_ID_CC2]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt;\r
+\r
+ /* Set the DMA error callback */\r
+ htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError ;\r
+\r
+ /* Enable the DMA channel */\r
+ if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)&htim->Instance->CCR2, (uint32_t)pData2, Length) != HAL_OK)\r
+ {\r
+ return HAL_ERROR;\r
+ }\r
+ /* Enable the Peripheral */\r
+ __HAL_TIM_ENABLE(htim);\r
+\r
+ /* Enable the Capture compare channel */\r
+ TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);\r
+ TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE);\r
+\r
+ /* Enable the TIM Input Capture DMA request */\r
+ __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1);\r
+ /* Enable the TIM Input Capture DMA request */\r
+ __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC2);\r
+ break;\r
+ }\r
+\r
+ default:\r
+ break;\r
+ }\r
+ /* Return function status */\r
+ return HAL_OK;\r
+}\r
+\r
+/**\r
+ * @brief Stops the TIM Encoder Interface in DMA mode.\r
+ * @param htim TIM Encoder Interface handle\r
+ * @param Channel TIM Channels to be enabled\r
+ * This parameter can be one of the following values:\r
+ * @arg TIM_CHANNEL_1: TIM Channel 1 selected\r
+ * @arg TIM_CHANNEL_2: TIM Channel 2 selected\r
+ * @arg TIM_CHANNEL_ALL: TIM Channel 1 and TIM Channel 2 are selected\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_TIM_Encoder_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_TIM_DMA_CC_INSTANCE(htim->Instance));\r
+\r
+ /* Disable the Input Capture channels 1 and 2\r
+ (in the EncoderInterface the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2) */\r
+ if (Channel == TIM_CHANNEL_1)\r
+ {\r
+ TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);\r
+\r
+ /* Disable the capture compare DMA Request 1 */\r
+ __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1);\r
+ (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC1]);\r
+ }\r
+ else if (Channel == TIM_CHANNEL_2)\r
+ {\r
+ TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE);\r
+\r
+ /* Disable the capture compare DMA Request 2 */\r
+ __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC2);\r
+ (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC2]);\r
+ }\r
+ else\r
+ {\r
+ TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);\r
+ TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE);\r
+\r
+ /* Disable the capture compare DMA Request 1 and 2 */\r
+ __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1);\r
+ __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC2);\r
+ (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC1]);\r
+ (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC2]);\r
+ }\r
+\r
+ /* Disable the Peripheral */\r
+ __HAL_TIM_DISABLE(htim);\r
+\r
+ /* Change the htim state */\r
+ htim->State = HAL_TIM_STATE_READY;\r
+\r
+ /* Return function status */\r
+ return HAL_OK;\r
+}\r
+\r
+/**\r
+ * @}\r
+ */\r
+/** @defgroup TIM_Exported_Functions_Group7 TIM IRQ handler management\r
+ * @brief TIM IRQ handler management\r
+ *\r
+@verbatim\r
+ ==============================================================================\r
+ ##### IRQ handler management #####\r
+ ==============================================================================\r
+ [..]\r
+ This section provides Timer IRQ handler function.\r
+\r
+@endverbatim\r
+ * @{\r
+ */\r
+/**\r
+ * @brief This function handles TIM interrupts requests.\r
+ * @param htim TIM handle\r
+ * @retval None\r
+ */\r
+void HAL_TIM_IRQHandler(TIM_HandleTypeDef *htim)\r
+{\r
+ /* Capture compare 1 event */\r
+ if (__HAL_TIM_GET_FLAG(htim, TIM_FLAG_CC1) != RESET)\r
+ {\r
+ if (__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_CC1) != RESET)\r
+ {\r
+ {\r
+ __HAL_TIM_CLEAR_IT(htim, TIM_IT_CC1);\r
+ htim->Channel = HAL_TIM_ACTIVE_CHANNEL_1;\r
+\r
+ /* Input capture event */\r
+ if ((htim->Instance->CCMR1 & TIM_CCMR1_CC1S) != 0x00U)\r
+ {\r
+#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)\r
+ htim->IC_CaptureCallback(htim);\r
+#else\r
+ HAL_TIM_IC_CaptureCallback(htim);\r
+#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */\r
+ }\r
+ /* Output compare event */\r
+ else\r
+ {\r
+#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)\r
+ htim->OC_DelayElapsedCallback(htim);\r
+ htim->PWM_PulseFinishedCallback(htim);\r
+#else\r
+ HAL_TIM_OC_DelayElapsedCallback(htim);\r
+ HAL_TIM_PWM_PulseFinishedCallback(htim);\r
+#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */\r
+ }\r
+ htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;\r
+ }\r
+ }\r
+ }\r
+ /* Capture compare 2 event */\r
+ if (__HAL_TIM_GET_FLAG(htim, TIM_FLAG_CC2) != RESET)\r
+ {\r
+ if (__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_CC2) != RESET)\r
+ {\r
+ __HAL_TIM_CLEAR_IT(htim, TIM_IT_CC2);\r
+ htim->Channel = HAL_TIM_ACTIVE_CHANNEL_2;\r
+ /* Input capture event */\r
+ if ((htim->Instance->CCMR1 & TIM_CCMR1_CC2S) != 0x00U)\r
+ {\r
+#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)\r
+ htim->IC_CaptureCallback(htim);\r
+#else\r
+ HAL_TIM_IC_CaptureCallback(htim);\r
+#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */\r
+ }\r
+ /* Output compare event */\r
+ else\r
+ {\r
+#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)\r
+ htim->OC_DelayElapsedCallback(htim);\r
+ htim->PWM_PulseFinishedCallback(htim);\r
+#else\r
+ HAL_TIM_OC_DelayElapsedCallback(htim);\r
+ HAL_TIM_PWM_PulseFinishedCallback(htim);\r
+#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */\r
+ }\r
+ htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;\r
+ }\r
+ }\r
+ /* Capture compare 3 event */\r
+ if (__HAL_TIM_GET_FLAG(htim, TIM_FLAG_CC3) != RESET)\r
+ {\r
+ if (__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_CC3) != RESET)\r
+ {\r
+ __HAL_TIM_CLEAR_IT(htim, TIM_IT_CC3);\r
+ htim->Channel = HAL_TIM_ACTIVE_CHANNEL_3;\r
+ /* Input capture event */\r
+ if ((htim->Instance->CCMR2 & TIM_CCMR2_CC3S) != 0x00U)\r
+ {\r
+#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)\r
+ htim->IC_CaptureCallback(htim);\r
+#else\r
+ HAL_TIM_IC_CaptureCallback(htim);\r
+#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */\r
+ }\r
+ /* Output compare event */\r
+ else\r
+ {\r
+#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)\r
+ htim->OC_DelayElapsedCallback(htim);\r
+ htim->PWM_PulseFinishedCallback(htim);\r
+#else\r
+ HAL_TIM_OC_DelayElapsedCallback(htim);\r
+ HAL_TIM_PWM_PulseFinishedCallback(htim);\r
+#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */\r
+ }\r
+ htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;\r
+ }\r
+ }\r
+ /* Capture compare 4 event */\r
+ if (__HAL_TIM_GET_FLAG(htim, TIM_FLAG_CC4) != RESET)\r
+ {\r
+ if (__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_CC4) != RESET)\r
+ {\r
+ __HAL_TIM_CLEAR_IT(htim, TIM_IT_CC4);\r
+ htim->Channel = HAL_TIM_ACTIVE_CHANNEL_4;\r
+ /* Input capture event */\r
+ if ((htim->Instance->CCMR2 & TIM_CCMR2_CC4S) != 0x00U)\r
+ {\r
+#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)\r
+ htim->IC_CaptureCallback(htim);\r
+#else\r
+ HAL_TIM_IC_CaptureCallback(htim);\r
+#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */\r
+ }\r
+ /* Output compare event */\r
+ else\r
+ {\r
+#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)\r
+ htim->OC_DelayElapsedCallback(htim);\r
+ htim->PWM_PulseFinishedCallback(htim);\r
+#else\r
+ HAL_TIM_OC_DelayElapsedCallback(htim);\r
+ HAL_TIM_PWM_PulseFinishedCallback(htim);\r
+#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */\r
+ }\r
+ htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;\r
+ }\r
+ }\r
+ /* TIM Update event */\r
+ if (__HAL_TIM_GET_FLAG(htim, TIM_FLAG_UPDATE) != RESET)\r
+ {\r
+ if (__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_UPDATE) != RESET)\r
+ {\r
+ __HAL_TIM_CLEAR_IT(htim, TIM_IT_UPDATE);\r
+#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)\r
+ htim->PeriodElapsedCallback(htim);\r
+#else\r
+ HAL_TIM_PeriodElapsedCallback(htim);\r
+#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */\r
+ }\r
+ }\r
+ /* TIM Trigger detection event */\r
+ if (__HAL_TIM_GET_FLAG(htim, TIM_FLAG_TRIGGER) != RESET)\r
+ {\r
+ if (__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_TRIGGER) != RESET)\r
+ {\r
+ __HAL_TIM_CLEAR_IT(htim, TIM_IT_TRIGGER);\r
+#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)\r
+ htim->TriggerCallback(htim);\r
+#else\r
+ HAL_TIM_TriggerCallback(htim);\r
+#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */\r
+ }\r
+ }\r
+}\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup TIM_Exported_Functions_Group8 TIM Peripheral Control functions\r
+ * @brief TIM Peripheral Control functions\r
+ *\r
+@verbatim\r
+ ==============================================================================\r
+ ##### Peripheral Control functions #####\r
+ ==============================================================================\r
+ [..]\r
+ This section provides functions allowing to:\r
+ (+) Configure The Input Output channels for OC, PWM, IC or One Pulse mode.\r
+ (+) Configure External Clock source.\r
+ (+) Configure Master and the Slave synchronization.\r
+ (+) Configure the DMA Burst Mode.\r
+\r
+@endverbatim\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @brief Initializes the TIM Output Compare Channels according to the specified\r
+ * parameters in the TIM_OC_InitTypeDef.\r
+ * @param htim TIM Output Compare handle\r
+ * @param sConfig TIM Output Compare configuration structure\r
+ * @param Channel TIM Channels to configure\r
+ * This parameter can be one of the following values:\r
+ * @arg TIM_CHANNEL_1: TIM Channel 1 selected\r
+ * @arg TIM_CHANNEL_2: TIM Channel 2 selected\r
+ * @arg TIM_CHANNEL_3: TIM Channel 3 selected\r
+ * @arg TIM_CHANNEL_4: TIM Channel 4 selected\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_TIM_OC_ConfigChannel(TIM_HandleTypeDef *htim,\r
+ TIM_OC_InitTypeDef *sConfig,\r
+ uint32_t Channel)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_TIM_CHANNELS(Channel));\r
+ assert_param(IS_TIM_OC_MODE(sConfig->OCMode));\r
+ assert_param(IS_TIM_OC_POLARITY(sConfig->OCPolarity));\r
+\r
+ /* Process Locked */\r
+ __HAL_LOCK(htim);\r
+\r
+ htim->State = HAL_TIM_STATE_BUSY;\r
+\r
+ switch (Channel)\r
+ {\r
+ case TIM_CHANNEL_1:\r
+ {\r
+ /* Check the parameters */\r
+ assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));\r
+\r
+ /* Configure the TIM Channel 1 in Output Compare */\r
+ TIM_OC1_SetConfig(htim->Instance, sConfig);\r
+ break;\r
+ }\r
+\r
+ case TIM_CHANNEL_2:\r
+ {\r
+ /* Check the parameters */\r
+ assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));\r
+\r
+ /* Configure the TIM Channel 2 in Output Compare */\r
+ TIM_OC2_SetConfig(htim->Instance, sConfig);\r
+ break;\r
+ }\r
+\r
+ case TIM_CHANNEL_3:\r
+ {\r
+ /* Check the parameters */\r
+ assert_param(IS_TIM_CC3_INSTANCE(htim->Instance));\r
+\r
+ /* Configure the TIM Channel 3 in Output Compare */\r
+ TIM_OC3_SetConfig(htim->Instance, sConfig);\r
+ break;\r
+ }\r
+\r
+ case TIM_CHANNEL_4:\r
+ {\r
+ /* Check the parameters */\r
+ assert_param(IS_TIM_CC4_INSTANCE(htim->Instance));\r
+\r
+ /* Configure the TIM Channel 4 in Output Compare */\r
+ TIM_OC4_SetConfig(htim->Instance, sConfig);\r
+ break;\r
+ }\r
+\r
+ default:\r
+ break;\r
+ }\r
+\r
+ htim->State = HAL_TIM_STATE_READY;\r
+\r
+ __HAL_UNLOCK(htim);\r
+\r
+ return HAL_OK;\r
+}\r
+\r
+/**\r
+ * @brief Initializes the TIM Input Capture Channels according to the specified\r
+ * parameters in the TIM_IC_InitTypeDef.\r
+ * @param htim TIM IC handle\r
+ * @param sConfig TIM Input Capture configuration structure\r
+ * @param Channel TIM Channel to configure\r
+ * This parameter can be one of the following values:\r
+ * @arg TIM_CHANNEL_1: TIM Channel 1 selected\r
+ * @arg TIM_CHANNEL_2: TIM Channel 2 selected\r
+ * @arg TIM_CHANNEL_3: TIM Channel 3 selected\r
+ * @arg TIM_CHANNEL_4: TIM Channel 4 selected\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_TIM_IC_ConfigChannel(TIM_HandleTypeDef *htim, TIM_IC_InitTypeDef *sConfig, uint32_t Channel)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));\r
+ assert_param(IS_TIM_IC_POLARITY(sConfig->ICPolarity));\r
+ assert_param(IS_TIM_IC_SELECTION(sConfig->ICSelection));\r
+ assert_param(IS_TIM_IC_PRESCALER(sConfig->ICPrescaler));\r
+ assert_param(IS_TIM_IC_FILTER(sConfig->ICFilter));\r
+\r
+ /* Process Locked */\r
+ __HAL_LOCK(htim);\r
+\r
+ htim->State = HAL_TIM_STATE_BUSY;\r
+\r
+ if (Channel == TIM_CHANNEL_1)\r
+ {\r
+ /* TI1 Configuration */\r
+ TIM_TI1_SetConfig(htim->Instance,\r
+ sConfig->ICPolarity,\r
+ sConfig->ICSelection,\r
+ sConfig->ICFilter);\r
+\r
+ /* Reset the IC1PSC Bits */\r
+ htim->Instance->CCMR1 &= ~TIM_CCMR1_IC1PSC;\r
+\r
+ /* Set the IC1PSC value */\r
+ htim->Instance->CCMR1 |= sConfig->ICPrescaler;\r
+ }\r
+ else if (Channel == TIM_CHANNEL_2)\r
+ {\r
+ /* TI2 Configuration */\r
+ assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));\r
+\r
+ TIM_TI2_SetConfig(htim->Instance,\r
+ sConfig->ICPolarity,\r
+ sConfig->ICSelection,\r
+ sConfig->ICFilter);\r
+\r
+ /* Reset the IC2PSC Bits */\r
+ htim->Instance->CCMR1 &= ~TIM_CCMR1_IC2PSC;\r
+\r
+ /* Set the IC2PSC value */\r
+ htim->Instance->CCMR1 |= (sConfig->ICPrescaler << 8U);\r
+ }\r
+ else if (Channel == TIM_CHANNEL_3)\r
+ {\r
+ /* TI3 Configuration */\r
+ assert_param(IS_TIM_CC3_INSTANCE(htim->Instance));\r
+\r
+ TIM_TI3_SetConfig(htim->Instance,\r
+ sConfig->ICPolarity,\r
+ sConfig->ICSelection,\r
+ sConfig->ICFilter);\r
+\r
+ /* Reset the IC3PSC Bits */\r
+ htim->Instance->CCMR2 &= ~TIM_CCMR2_IC3PSC;\r
+\r
+ /* Set the IC3PSC value */\r
+ htim->Instance->CCMR2 |= sConfig->ICPrescaler;\r
+ }\r
+ else\r
+ {\r
+ /* TI4 Configuration */\r
+ assert_param(IS_TIM_CC4_INSTANCE(htim->Instance));\r
+\r
+ TIM_TI4_SetConfig(htim->Instance,\r
+ sConfig->ICPolarity,\r
+ sConfig->ICSelection,\r
+ sConfig->ICFilter);\r
+\r
+ /* Reset the IC4PSC Bits */\r
+ htim->Instance->CCMR2 &= ~TIM_CCMR2_IC4PSC;\r
+\r
+ /* Set the IC4PSC value */\r
+ htim->Instance->CCMR2 |= (sConfig->ICPrescaler << 8U);\r
+ }\r
+\r
+ htim->State = HAL_TIM_STATE_READY;\r
+\r
+ __HAL_UNLOCK(htim);\r
+\r
+ return HAL_OK;\r
+}\r
+\r
+/**\r
+ * @brief Initializes the TIM PWM channels according to the specified\r
+ * parameters in the TIM_OC_InitTypeDef.\r
+ * @param htim TIM PWM handle\r
+ * @param sConfig TIM PWM configuration structure\r
+ * @param Channel TIM Channels to be configured\r
+ * This parameter can be one of the following values:\r
+ * @arg TIM_CHANNEL_1: TIM Channel 1 selected\r
+ * @arg TIM_CHANNEL_2: TIM Channel 2 selected\r
+ * @arg TIM_CHANNEL_3: TIM Channel 3 selected\r
+ * @arg TIM_CHANNEL_4: TIM Channel 4 selected\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_TIM_PWM_ConfigChannel(TIM_HandleTypeDef *htim,\r
+ TIM_OC_InitTypeDef *sConfig,\r
+ uint32_t Channel)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_TIM_CHANNELS(Channel));\r
+ assert_param(IS_TIM_PWM_MODE(sConfig->OCMode));\r
+ assert_param(IS_TIM_OC_POLARITY(sConfig->OCPolarity));\r
+ assert_param(IS_TIM_FAST_STATE(sConfig->OCFastMode));\r
+\r
+ /* Process Locked */\r
+ __HAL_LOCK(htim);\r
+\r
+ htim->State = HAL_TIM_STATE_BUSY;\r
+\r
+ switch (Channel)\r
+ {\r
+ case TIM_CHANNEL_1:\r
+ {\r
+ /* Check the parameters */\r
+ assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));\r
+\r
+ /* Configure the Channel 1 in PWM mode */\r
+ TIM_OC1_SetConfig(htim->Instance, sConfig);\r
+\r
+ /* Set the Preload enable bit for channel1 */\r
+ htim->Instance->CCMR1 |= TIM_CCMR1_OC1PE;\r
+\r
+ /* Configure the Output Fast mode */\r
+ htim->Instance->CCMR1 &= ~TIM_CCMR1_OC1FE;\r
+ htim->Instance->CCMR1 |= sConfig->OCFastMode;\r
+ break;\r
+ }\r
+\r
+ case TIM_CHANNEL_2:\r
+ {\r
+ /* Check the parameters */\r
+ assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));\r
+\r
+ /* Configure the Channel 2 in PWM mode */\r
+ TIM_OC2_SetConfig(htim->Instance, sConfig);\r
+\r
+ /* Set the Preload enable bit for channel2 */\r
+ htim->Instance->CCMR1 |= TIM_CCMR1_OC2PE;\r
+\r
+ /* Configure the Output Fast mode */\r
+ htim->Instance->CCMR1 &= ~TIM_CCMR1_OC2FE;\r
+ htim->Instance->CCMR1 |= sConfig->OCFastMode << 8U;\r
+ break;\r
+ }\r
+\r
+ case TIM_CHANNEL_3:\r
+ {\r
+ /* Check the parameters */\r
+ assert_param(IS_TIM_CC3_INSTANCE(htim->Instance));\r
+\r
+ /* Configure the Channel 3 in PWM mode */\r
+ TIM_OC3_SetConfig(htim->Instance, sConfig);\r
+\r
+ /* Set the Preload enable bit for channel3 */\r
+ htim->Instance->CCMR2 |= TIM_CCMR2_OC3PE;\r
+\r
+ /* Configure the Output Fast mode */\r
+ htim->Instance->CCMR2 &= ~TIM_CCMR2_OC3FE;\r
+ htim->Instance->CCMR2 |= sConfig->OCFastMode;\r
+ break;\r
+ }\r
+\r
+ case TIM_CHANNEL_4:\r
+ {\r
+ /* Check the parameters */\r
+ assert_param(IS_TIM_CC4_INSTANCE(htim->Instance));\r
+\r
+ /* Configure the Channel 4 in PWM mode */\r
+ TIM_OC4_SetConfig(htim->Instance, sConfig);\r
+\r
+ /* Set the Preload enable bit for channel4 */\r
+ htim->Instance->CCMR2 |= TIM_CCMR2_OC4PE;\r
+\r
+ /* Configure the Output Fast mode */\r
+ htim->Instance->CCMR2 &= ~TIM_CCMR2_OC4FE;\r
+ htim->Instance->CCMR2 |= sConfig->OCFastMode << 8U;\r
+ break;\r
+ }\r
+\r
+ default:\r
+ break;\r
+ }\r
+\r
+ htim->State = HAL_TIM_STATE_READY;\r
+\r
+ __HAL_UNLOCK(htim);\r
+\r
+ return HAL_OK;\r
+}\r
+\r
+/**\r
+ * @brief Initializes the TIM One Pulse Channels according to the specified\r
+ * parameters in the TIM_OnePulse_InitTypeDef.\r
+ * @param htim TIM One Pulse handle\r
+ * @param sConfig TIM One Pulse configuration structure\r
+ * @param OutputChannel TIM output channel to configure\r
+ * This parameter can be one of the following values:\r
+ * @arg TIM_CHANNEL_1: TIM Channel 1 selected\r
+ * @arg TIM_CHANNEL_2: TIM Channel 2 selected\r
+ * @param InputChannel TIM input Channel to configure\r
+ * This parameter can be one of the following values:\r
+ * @arg TIM_CHANNEL_1: TIM Channel 1 selected\r
+ * @arg TIM_CHANNEL_2: TIM Channel 2 selected\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_TIM_OnePulse_ConfigChannel(TIM_HandleTypeDef *htim, TIM_OnePulse_InitTypeDef *sConfig, uint32_t OutputChannel, uint32_t InputChannel)\r
+{\r
+ TIM_OC_InitTypeDef temp1;\r
+\r
+ /* Check the parameters */\r
+ assert_param(IS_TIM_OPM_CHANNELS(OutputChannel));\r
+ assert_param(IS_TIM_OPM_CHANNELS(InputChannel));\r
+\r
+ if (OutputChannel != InputChannel)\r
+ {\r
+ /* Process Locked */\r
+ __HAL_LOCK(htim);\r
+\r
+ htim->State = HAL_TIM_STATE_BUSY;\r
+\r
+ /* Extract the Output compare configuration from sConfig structure */\r
+ temp1.OCMode = sConfig->OCMode;\r
+ temp1.Pulse = sConfig->Pulse;\r
+ temp1.OCPolarity = sConfig->OCPolarity;\r
+\r
+ switch (OutputChannel)\r
+ {\r
+ case TIM_CHANNEL_1:\r
+ {\r
+ assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));\r
+\r
+ TIM_OC1_SetConfig(htim->Instance, &temp1);\r
+ break;\r
+ }\r
+ case TIM_CHANNEL_2:\r
+ {\r
+ assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));\r
+\r
+ TIM_OC2_SetConfig(htim->Instance, &temp1);\r
+ break;\r
+ }\r
+ default:\r
+ break;\r
+ }\r
+\r
+ switch (InputChannel)\r
+ {\r
+ case TIM_CHANNEL_1:\r
+ {\r
+ assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));\r
+\r
+ TIM_TI1_SetConfig(htim->Instance, sConfig->ICPolarity,\r
+ sConfig->ICSelection, sConfig->ICFilter);\r
+\r
+ /* Reset the IC1PSC Bits */\r
+ htim->Instance->CCMR1 &= ~TIM_CCMR1_IC1PSC;\r
+\r
+ /* Select the Trigger source */\r
+ htim->Instance->SMCR &= ~TIM_SMCR_TS;\r
+ htim->Instance->SMCR |= TIM_TS_TI1FP1;\r
+\r
+ /* Select the Slave Mode */\r
+ htim->Instance->SMCR &= ~TIM_SMCR_SMS;\r
+ htim->Instance->SMCR |= TIM_SLAVEMODE_TRIGGER;\r
+ break;\r
+ }\r
+ case TIM_CHANNEL_2:\r
+ {\r
+ assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));\r
+\r
+ TIM_TI2_SetConfig(htim->Instance, sConfig->ICPolarity,\r
+ sConfig->ICSelection, sConfig->ICFilter);\r
+\r
+ /* Reset the IC2PSC Bits */\r
+ htim->Instance->CCMR1 &= ~TIM_CCMR1_IC2PSC;\r
+\r
+ /* Select the Trigger source */\r
+ htim->Instance->SMCR &= ~TIM_SMCR_TS;\r
+ htim->Instance->SMCR |= TIM_TS_TI2FP2;\r
+\r
+ /* Select the Slave Mode */\r
+ htim->Instance->SMCR &= ~TIM_SMCR_SMS;\r
+ htim->Instance->SMCR |= TIM_SLAVEMODE_TRIGGER;\r
+ break;\r
+ }\r
+\r
+ default:\r
+ break;\r
+ }\r
+\r
+ htim->State = HAL_TIM_STATE_READY;\r
+\r
+ __HAL_UNLOCK(htim);\r
+\r
+ return HAL_OK;\r
+ }\r
+ else\r
+ {\r
+ return HAL_ERROR;\r
+ }\r
+}\r
+\r
+/**\r
+ * @brief Configure the DMA Burst to transfer Data from the memory to the TIM peripheral\r
+ * @param htim TIM handle\r
+ * @param BurstBaseAddress TIM Base address from where the DMA will start the Data write\r
+ * This parameter can be one of the following values:\r
+ * @arg TIM_DMABASE_CR1\r
+ * @arg TIM_DMABASE_CR2\r
+ * @arg TIM_DMABASE_SMCR\r
+ * @arg TIM_DMABASE_DIER\r
+ * @arg TIM_DMABASE_SR\r
+ * @arg TIM_DMABASE_EGR\r
+ * @arg TIM_DMABASE_CCMR1\r
+ * @arg TIM_DMABASE_CCMR2\r
+ * @arg TIM_DMABASE_CCER\r
+ * @arg TIM_DMABASE_CNT\r
+ * @arg TIM_DMABASE_PSC\r
+ * @arg TIM_DMABASE_ARR\r
+ * @arg TIM_DMABASE_CCR1\r
+ * @arg TIM_DMABASE_CCR2\r
+ * @arg TIM_DMABASE_CCR3\r
+ * @arg TIM_DMABASE_CCR4\r
+ * @arg TIM_DMABASE_OR\r
+ * @param BurstRequestSrc TIM DMA Request sources\r
+ * This parameter can be one of the following values:\r
+ * @arg TIM_DMA_UPDATE: TIM update Interrupt source\r
+ * @arg TIM_DMA_CC1: TIM Capture Compare 1 DMA source\r
+ * @arg TIM_DMA_CC2: TIM Capture Compare 2 DMA source\r
+ * @arg TIM_DMA_CC3: TIM Capture Compare 3 DMA source\r
+ * @arg TIM_DMA_CC4: TIM Capture Compare 4 DMA source\r
+ * @arg TIM_DMA_TRIGGER: TIM Trigger DMA source\r
+ * @param BurstBuffer The Buffer address.\r
+ * @param BurstLength DMA Burst length. This parameter can be one value\r
+ * between: TIM_DMABURSTLENGTH_1TRANSFER and TIM_DMABURSTLENGTH_18TRANSFERS.\r
+ * @note This function should be used only when BurstLength is equal to DMA data transfer length.\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress, uint32_t BurstRequestSrc,\r
+ uint32_t *BurstBuffer, uint32_t BurstLength)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_TIM_DMABURST_INSTANCE(htim->Instance));\r
+ assert_param(IS_TIM_DMA_BASE(BurstBaseAddress));\r
+ assert_param(IS_TIM_DMA_SOURCE(BurstRequestSrc));\r
+ assert_param(IS_TIM_DMA_LENGTH(BurstLength));\r
+\r
+ if ((htim->State == HAL_TIM_STATE_BUSY))\r
+ {\r
+ return HAL_BUSY;\r
+ }\r
+ else if ((htim->State == HAL_TIM_STATE_READY))\r
+ {\r
+ if ((BurstBuffer == NULL) && (BurstLength > 0U))\r
+ {\r
+ return HAL_ERROR;\r
+ }\r
+ else\r
+ {\r
+ htim->State = HAL_TIM_STATE_BUSY;\r
+ }\r
+ }\r
+ else\r
+ {\r
+ /* nothing to do */\r
+ }\r
+ switch (BurstRequestSrc)\r
+ {\r
+ case TIM_DMA_UPDATE:\r
+ {\r
+ /* Set the DMA Period elapsed callbacks */\r
+ htim->hdma[TIM_DMA_ID_UPDATE]->XferCpltCallback = TIM_DMAPeriodElapsedCplt;\r
+ htim->hdma[TIM_DMA_ID_UPDATE]->XferHalfCpltCallback = TIM_DMAPeriodElapsedHalfCplt;\r
+\r
+ /* Set the DMA error callback */\r
+ htim->hdma[TIM_DMA_ID_UPDATE]->XferErrorCallback = TIM_DMAError ;\r
+\r
+ /* Enable the DMA channel */\r
+ if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_UPDATE], (uint32_t)BurstBuffer, (uint32_t)&htim->Instance->DMAR, ((BurstLength) >> 8U) + 1U) != HAL_OK)\r
+ {\r
+ return HAL_ERROR;\r
+ }\r
+ break;\r
+ }\r
+ case TIM_DMA_CC1:\r
+ {\r
+ /* Set the DMA compare callbacks */\r
+ htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMADelayPulseCplt;\r
+ htim->hdma[TIM_DMA_ID_CC1]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt;\r
+\r
+ /* Set the DMA error callback */\r
+ htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ;\r
+\r
+ /* Enable the DMA channel */\r
+ if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)BurstBuffer, (uint32_t)&htim->Instance->DMAR, ((BurstLength) >> 8U) + 1U) != HAL_OK)\r
+ {\r
+ return HAL_ERROR;\r
+ }\r
+ break;\r
+ }\r
+ case TIM_DMA_CC2:\r
+ {\r
+ /* Set the DMA compare callbacks */\r
+ htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMADelayPulseCplt;\r
+ htim->hdma[TIM_DMA_ID_CC2]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt;\r
+\r
+ /* Set the DMA error callback */\r
+ htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError ;\r
+\r
+ /* Enable the DMA channel */\r
+ if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)BurstBuffer, (uint32_t)&htim->Instance->DMAR, ((BurstLength) >> 8U) + 1U) != HAL_OK)\r
+ {\r
+ return HAL_ERROR;\r
+ }\r
+ break;\r
+ }\r
+ case TIM_DMA_CC3:\r
+ {\r
+ /* Set the DMA compare callbacks */\r
+ htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = TIM_DMADelayPulseCplt;\r
+ htim->hdma[TIM_DMA_ID_CC3]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt;\r
+\r
+ /* Set the DMA error callback */\r
+ htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = TIM_DMAError ;\r
+\r
+ /* Enable the DMA channel */\r
+ if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)BurstBuffer, (uint32_t)&htim->Instance->DMAR, ((BurstLength) >> 8U) + 1U) != HAL_OK)\r
+ {\r
+ return HAL_ERROR;\r
+ }\r
+ break;\r
+ }\r
+ case TIM_DMA_CC4:\r
+ {\r
+ /* Set the DMA compare callbacks */\r
+ htim->hdma[TIM_DMA_ID_CC4]->XferCpltCallback = TIM_DMADelayPulseCplt;\r
+ htim->hdma[TIM_DMA_ID_CC4]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt;\r
+\r
+ /* Set the DMA error callback */\r
+ htim->hdma[TIM_DMA_ID_CC4]->XferErrorCallback = TIM_DMAError ;\r
+\r
+ /* Enable the DMA channel */\r
+ if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)BurstBuffer, (uint32_t)&htim->Instance->DMAR, ((BurstLength) >> 8U) + 1U) != HAL_OK)\r
+ {\r
+ return HAL_ERROR;\r
+ }\r
+ break;\r
+ }\r
+ case TIM_DMA_TRIGGER:\r
+ {\r
+ /* Set the DMA trigger callbacks */\r
+ htim->hdma[TIM_DMA_ID_TRIGGER]->XferCpltCallback = TIM_DMATriggerCplt;\r
+ htim->hdma[TIM_DMA_ID_TRIGGER]->XferHalfCpltCallback = TIM_DMATriggerHalfCplt;\r
+\r
+ /* Set the DMA error callback */\r
+ htim->hdma[TIM_DMA_ID_TRIGGER]->XferErrorCallback = TIM_DMAError ;\r
+\r
+ /* Enable the DMA channel */\r
+ if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_TRIGGER], (uint32_t)BurstBuffer, (uint32_t)&htim->Instance->DMAR, ((BurstLength) >> 8U) + 1U) != HAL_OK)\r
+ {\r
+ return HAL_ERROR;\r
+ }\r
+ break;\r
+ }\r
+ default:\r
+ break;\r
+ }\r
+ /* configure the DMA Burst Mode */\r
+ htim->Instance->DCR = (BurstBaseAddress | BurstLength);\r
+\r
+ /* Enable the TIM DMA Request */\r
+ __HAL_TIM_ENABLE_DMA(htim, BurstRequestSrc);\r
+\r
+ htim->State = HAL_TIM_STATE_READY;\r
+\r
+ /* Return function status */\r
+ return HAL_OK;\r
+}\r
+\r
+/**\r
+ * @brief Stops the TIM DMA Burst mode\r
+ * @param htim TIM handle\r
+ * @param BurstRequestSrc TIM DMA Request sources to disable\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStop(TIM_HandleTypeDef *htim, uint32_t BurstRequestSrc)\r
+{\r
+ HAL_StatusTypeDef status = HAL_OK;\r
+ /* Check the parameters */\r
+ assert_param(IS_TIM_DMA_SOURCE(BurstRequestSrc));\r
+\r
+ /* Abort the DMA transfer (at least disable the DMA channel) */\r
+ switch (BurstRequestSrc)\r
+ {\r
+ case TIM_DMA_UPDATE:\r
+ {\r
+ status = HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_UPDATE]);\r
+ break;\r
+ }\r
+ case TIM_DMA_CC1:\r
+ {\r
+ status = HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC1]);\r
+ break;\r
+ }\r
+ case TIM_DMA_CC2:\r
+ {\r
+ status = HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC2]);\r
+ break;\r
+ }\r
+ case TIM_DMA_CC3:\r
+ {\r
+ status = HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC3]);\r
+ break;\r
+ }\r
+ case TIM_DMA_CC4:\r
+ {\r
+ status = HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC4]);\r
+ break;\r
+ }\r
+ case TIM_DMA_TRIGGER:\r
+ {\r
+ status = HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_TRIGGER]);\r
+ break;\r
+ }\r
+ default:\r
+ break;\r
+ }\r
+\r
+ if (HAL_OK == status)\r
+ {\r
+ /* Disable the TIM Update DMA request */\r
+ __HAL_TIM_DISABLE_DMA(htim, BurstRequestSrc);\r
+ }\r
+\r
+ /* Return function status */\r
+ return status;\r
+}\r
+\r
+/**\r
+ * @brief Configure the DMA Burst to transfer Data from the TIM peripheral to the memory\r
+ * @param htim TIM handle\r
+ * @param BurstBaseAddress TIM Base address from where the DMA will start the Data read\r
+ * This parameter can be one of the following values:\r
+ * @arg TIM_DMABASE_CR1\r
+ * @arg TIM_DMABASE_CR2\r
+ * @arg TIM_DMABASE_SMCR\r
+ * @arg TIM_DMABASE_DIER\r
+ * @arg TIM_DMABASE_SR\r
+ * @arg TIM_DMABASE_EGR\r
+ * @arg TIM_DMABASE_CCMR1\r
+ * @arg TIM_DMABASE_CCMR2\r
+ * @arg TIM_DMABASE_CCER\r
+ * @arg TIM_DMABASE_CNT\r
+ * @arg TIM_DMABASE_PSC\r
+ * @arg TIM_DMABASE_ARR\r
+ * @arg TIM_DMABASE_CCR1\r
+ * @arg TIM_DMABASE_CCR2\r
+ * @arg TIM_DMABASE_CCR3\r
+ * @arg TIM_DMABASE_CCR4\r
+ * @arg TIM_DMABASE_OR\r
+ * @param BurstRequestSrc TIM DMA Request sources\r
+ * This parameter can be one of the following values:\r
+ * @arg TIM_DMA_UPDATE: TIM update Interrupt source\r
+ * @arg TIM_DMA_CC1: TIM Capture Compare 1 DMA source\r
+ * @arg TIM_DMA_CC2: TIM Capture Compare 2 DMA source\r
+ * @arg TIM_DMA_CC3: TIM Capture Compare 3 DMA source\r
+ * @arg TIM_DMA_CC4: TIM Capture Compare 4 DMA source\r
+ * @arg TIM_DMA_TRIGGER: TIM Trigger DMA source\r
+ * @param BurstBuffer The Buffer address.\r
+ * @param BurstLength DMA Burst length. This parameter can be one value\r
+ * between: TIM_DMABURSTLENGTH_1TRANSFER and TIM_DMABURSTLENGTH_18TRANSFERS.\r
+ * @note This function should be used only when BurstLength is equal to DMA data transfer length.\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_TIM_DMABurst_ReadStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress, uint32_t BurstRequestSrc,\r
+ uint32_t *BurstBuffer, uint32_t BurstLength)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_TIM_DMABURST_INSTANCE(htim->Instance));\r
+ assert_param(IS_TIM_DMA_BASE(BurstBaseAddress));\r
+ assert_param(IS_TIM_DMA_SOURCE(BurstRequestSrc));\r
+ assert_param(IS_TIM_DMA_LENGTH(BurstLength));\r
+\r
+ if ((htim->State == HAL_TIM_STATE_BUSY))\r
+ {\r
+ return HAL_BUSY;\r
+ }\r
+ else if ((htim->State == HAL_TIM_STATE_READY))\r
+ {\r
+ if ((BurstBuffer == NULL) && (BurstLength > 0U))\r
+ {\r
+ return HAL_ERROR;\r
+ }\r
+ else\r
+ {\r
+ htim->State = HAL_TIM_STATE_BUSY;\r
+ }\r
+ }\r
+ else\r
+ {\r
+ /* nothing to do */\r
+ }\r
+ switch (BurstRequestSrc)\r
+ {\r
+ case TIM_DMA_UPDATE:\r
+ {\r
+ /* Set the DMA Period elapsed callbacks */\r
+ htim->hdma[TIM_DMA_ID_UPDATE]->XferCpltCallback = TIM_DMAPeriodElapsedCplt;\r
+ htim->hdma[TIM_DMA_ID_UPDATE]->XferHalfCpltCallback = TIM_DMAPeriodElapsedHalfCplt;\r
+\r
+ /* Set the DMA error callback */\r
+ htim->hdma[TIM_DMA_ID_UPDATE]->XferErrorCallback = TIM_DMAError ;\r
+\r
+ /* Enable the DMA channel */\r
+ if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_UPDATE], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer, ((BurstLength) >> 8U) + 1U) != HAL_OK)\r
+ {\r
+ return HAL_ERROR;\r
+ }\r
+ break;\r
+ }\r
+ case TIM_DMA_CC1:\r
+ {\r
+ /* Set the DMA capture callbacks */\r
+ htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMACaptureCplt;\r
+ htim->hdma[TIM_DMA_ID_CC1]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt;\r
+\r
+ /* Set the DMA error callback */\r
+ htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ;\r
+\r
+ /* Enable the DMA channel */\r
+ if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer, ((BurstLength) >> 8U) + 1U) != HAL_OK)\r
+ {\r
+ return HAL_ERROR;\r
+ }\r
+ break;\r
+ }\r
+ case TIM_DMA_CC2:\r
+ {\r
+ /* Set the DMA capture/compare callbacks */\r
+ htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMACaptureCplt;\r
+ htim->hdma[TIM_DMA_ID_CC2]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt;\r
+\r
+ /* Set the DMA error callback */\r
+ htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError ;\r
+\r
+ /* Enable the DMA channel */\r
+ if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer, ((BurstLength) >> 8U) + 1U) != HAL_OK)\r
+ {\r
+ return HAL_ERROR;\r
+ }\r
+ break;\r
+ }\r
+ case TIM_DMA_CC3:\r
+ {\r
+ /* Set the DMA capture callbacks */\r
+ htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = TIM_DMACaptureCplt;\r
+ htim->hdma[TIM_DMA_ID_CC3]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt;\r
+\r
+ /* Set the DMA error callback */\r
+ htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = TIM_DMAError ;\r
+\r
+ /* Enable the DMA channel */\r
+ if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer, ((BurstLength) >> 8U) + 1U) != HAL_OK)\r
+ {\r
+ return HAL_ERROR;\r
+ }\r
+ break;\r
+ }\r
+ case TIM_DMA_CC4:\r
+ {\r
+ /* Set the DMA capture callbacks */\r
+ htim->hdma[TIM_DMA_ID_CC4]->XferCpltCallback = TIM_DMACaptureCplt;\r
+ htim->hdma[TIM_DMA_ID_CC4]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt;\r
+\r
+ /* Set the DMA error callback */\r
+ htim->hdma[TIM_DMA_ID_CC4]->XferErrorCallback = TIM_DMAError ;\r
+\r
+ /* Enable the DMA channel */\r
+ if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer, ((BurstLength) >> 8U) + 1U) != HAL_OK)\r
+ {\r
+ return HAL_ERROR;\r
+ }\r
+ break;\r
+ }\r
+ case TIM_DMA_TRIGGER:\r
+ {\r
+ /* Set the DMA trigger callbacks */\r
+ htim->hdma[TIM_DMA_ID_TRIGGER]->XferCpltCallback = TIM_DMATriggerCplt;\r
+ htim->hdma[TIM_DMA_ID_TRIGGER]->XferHalfCpltCallback = TIM_DMATriggerHalfCplt;\r
+\r
+ /* Set the DMA error callback */\r
+ htim->hdma[TIM_DMA_ID_TRIGGER]->XferErrorCallback = TIM_DMAError ;\r
+\r
+ /* Enable the DMA channel */\r
+ if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_TRIGGER], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer, ((BurstLength) >> 8U) + 1U) != HAL_OK)\r
+ {\r
+ return HAL_ERROR;\r
+ }\r
+ break;\r
+ }\r
+ default:\r
+ break;\r
+ }\r
+\r
+ /* configure the DMA Burst Mode */\r
+ htim->Instance->DCR = (BurstBaseAddress | BurstLength);\r
+\r
+ /* Enable the TIM DMA Request */\r
+ __HAL_TIM_ENABLE_DMA(htim, BurstRequestSrc);\r
+\r
+ htim->State = HAL_TIM_STATE_READY;\r
+\r
+ /* Return function status */\r
+ return HAL_OK;\r
+}\r
+\r
+/**\r
+ * @brief Stop the DMA burst reading\r
+ * @param htim TIM handle\r
+ * @param BurstRequestSrc TIM DMA Request sources to disable.\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_TIM_DMABurst_ReadStop(TIM_HandleTypeDef *htim, uint32_t BurstRequestSrc)\r
+{\r
+ HAL_StatusTypeDef status = HAL_OK;\r
+ /* Check the parameters */\r
+ assert_param(IS_TIM_DMA_SOURCE(BurstRequestSrc));\r
+\r
+ /* Abort the DMA transfer (at least disable the DMA channel) */\r
+ switch (BurstRequestSrc)\r
+ {\r
+ case TIM_DMA_UPDATE:\r
+ {\r
+ status = HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_UPDATE]);\r
+ break;\r
+ }\r
+ case TIM_DMA_CC1:\r
+ {\r
+ status = HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC1]);\r
+ break;\r
+ }\r
+ case TIM_DMA_CC2:\r
+ {\r
+ status = HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC2]);\r
+ break;\r
+ }\r
+ case TIM_DMA_CC3:\r
+ {\r
+ status = HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC3]);\r
+ break;\r
+ }\r
+ case TIM_DMA_CC4:\r
+ {\r
+ status = HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC4]);\r
+ break;\r
+ }\r
+ case TIM_DMA_TRIGGER:\r
+ {\r
+ status = HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_TRIGGER]);\r
+ break;\r
+ }\r
+ default:\r
+ break;\r
+ }\r
+\r
+ if (HAL_OK == status)\r
+ {\r
+ /* Disable the TIM Update DMA request */\r
+ __HAL_TIM_DISABLE_DMA(htim, BurstRequestSrc);\r
+ }\r
+\r
+ /* Return function status */\r
+ return status;\r
+}\r
+\r
+/**\r
+ * @brief Generate a software event\r
+ * @param htim TIM handle\r
+ * @param EventSource specifies the event source.\r
+ * This parameter can be one of the following values:\r
+ * @arg TIM_EVENTSOURCE_UPDATE: Timer update Event source\r
+ * @arg TIM_EVENTSOURCE_CC1: Timer Capture Compare 1 Event source\r
+ * @arg TIM_EVENTSOURCE_CC2: Timer Capture Compare 2 Event source\r
+ * @arg TIM_EVENTSOURCE_CC3: Timer Capture Compare 3 Event source\r
+ * @arg TIM_EVENTSOURCE_CC4: Timer Capture Compare 4 Event source\r
+ * @arg TIM_EVENTSOURCE_TRIGGER: Timer Trigger Event source\r
+ * @note Basic timers can only generate an update event.\r
+ * @retval HAL status\r
+ */\r
+\r
+HAL_StatusTypeDef HAL_TIM_GenerateEvent(TIM_HandleTypeDef *htim, uint32_t EventSource)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_TIM_INSTANCE(htim->Instance));\r
+ assert_param(IS_TIM_EVENT_SOURCE(EventSource));\r
+\r
+ /* Process Locked */\r
+ __HAL_LOCK(htim);\r
+\r
+ /* Change the TIM state */\r
+ htim->State = HAL_TIM_STATE_BUSY;\r
+\r
+ /* Set the event sources */\r
+ htim->Instance->EGR = EventSource;\r
+\r
+ /* Change the TIM state */\r
+ htim->State = HAL_TIM_STATE_READY;\r
+\r
+ __HAL_UNLOCK(htim);\r
+\r
+ /* Return function status */\r
+ return HAL_OK;\r
+}\r
+\r
+/**\r
+ * @brief Configures the OCRef clear feature\r
+ * @param htim TIM handle\r
+ * @param sClearInputConfig pointer to a TIM_ClearInputConfigTypeDef structure that\r
+ * contains the OCREF clear feature and parameters for the TIM peripheral.\r
+ * @param Channel specifies the TIM Channel\r
+ * This parameter can be one of the following values:\r
+ * @arg TIM_CHANNEL_1: TIM Channel 1\r
+ * @arg TIM_CHANNEL_2: TIM Channel 2\r
+ * @arg TIM_CHANNEL_3: TIM Channel 3\r
+ * @arg TIM_CHANNEL_4: TIM Channel 4\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_TIM_ConfigOCrefClear(TIM_HandleTypeDef *htim,\r
+ TIM_ClearInputConfigTypeDef *sClearInputConfig,\r
+ uint32_t Channel)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_TIM_OCXREF_CLEAR_INSTANCE(htim->Instance));\r
+ assert_param(IS_TIM_CLEARINPUT_SOURCE(sClearInputConfig->ClearInputSource));\r
+\r
+ /* Process Locked */\r
+ __HAL_LOCK(htim);\r
+\r
+ htim->State = HAL_TIM_STATE_BUSY;\r
+\r
+ switch (sClearInputConfig->ClearInputSource)\r
+ {\r
+ case TIM_CLEARINPUTSOURCE_NONE:\r
+ {\r
+ /* Clear the OCREF clear selection bit and the the ETR Bits */\r
+ CLEAR_BIT(htim->Instance->SMCR, (TIM_SMCR_OCCS | TIM_SMCR_ETF | TIM_SMCR_ETPS | TIM_SMCR_ECE | TIM_SMCR_ETP));\r
+ break;\r
+ }\r
+ case TIM_CLEARINPUTSOURCE_OCREFCLR:\r
+ {\r
+ /* Clear the OCREF clear selection bit */\r
+ CLEAR_BIT(htim->Instance->SMCR, TIM_SMCR_OCCS);\r
+ }\r
+ break;\r
+\r
+ case TIM_CLEARINPUTSOURCE_ETR:\r
+ {\r
+ /* Check the parameters */\r
+ assert_param(IS_TIM_CLEARINPUT_POLARITY(sClearInputConfig->ClearInputPolarity));\r
+ assert_param(IS_TIM_CLEARINPUT_PRESCALER(sClearInputConfig->ClearInputPrescaler));\r
+ assert_param(IS_TIM_CLEARINPUT_FILTER(sClearInputConfig->ClearInputFilter));\r
+\r
+ /* When OCRef clear feature is used with ETR source, ETR prescaler must be off */\r
+ if (sClearInputConfig->ClearInputPrescaler != TIM_CLEARINPUTPRESCALER_DIV1)\r
+ {\r
+ htim->State = HAL_TIM_STATE_READY;\r
+ __HAL_UNLOCK(htim);\r
+ return HAL_ERROR;\r
+ }\r
+\r
+ TIM_ETR_SetConfig(htim->Instance,\r
+ sClearInputConfig->ClearInputPrescaler,\r
+ sClearInputConfig->ClearInputPolarity,\r
+ sClearInputConfig->ClearInputFilter);\r
+\r
+ /* Set the OCREF clear selection bit */\r
+ SET_BIT(htim->Instance->SMCR, TIM_SMCR_OCCS);\r
+ break;\r
+ }\r
+\r
+ default:\r
+ break;\r
+ }\r
+\r
+ switch (Channel)\r
+ {\r
+ case TIM_CHANNEL_1:\r
+ {\r
+ if (sClearInputConfig->ClearInputState != (uint32_t)DISABLE)\r
+ {\r
+ /* Enable the OCREF clear feature for Channel 1 */\r
+ SET_BIT(htim->Instance->CCMR1, TIM_CCMR1_OC1CE);\r
+ }\r
+ else\r
+ {\r
+ /* Disable the OCREF clear feature for Channel 1 */\r
+ CLEAR_BIT(htim->Instance->CCMR1, TIM_CCMR1_OC1CE);\r
+ }\r
+ break;\r
+ }\r
+ case TIM_CHANNEL_2:\r
+ {\r
+ if (sClearInputConfig->ClearInputState != (uint32_t)DISABLE)\r
+ {\r
+ /* Enable the OCREF clear feature for Channel 2 */\r
+ SET_BIT(htim->Instance->CCMR1, TIM_CCMR1_OC2CE);\r
+ }\r
+ else\r
+ {\r
+ /* Disable the OCREF clear feature for Channel 2 */\r
+ CLEAR_BIT(htim->Instance->CCMR1, TIM_CCMR1_OC2CE);\r
+ }\r
+ break;\r
+ }\r
+ case TIM_CHANNEL_3:\r
+ {\r
+ if (sClearInputConfig->ClearInputState != (uint32_t)DISABLE)\r
+ {\r
+ /* Enable the OCREF clear feature for Channel 3 */\r
+ SET_BIT(htim->Instance->CCMR2, TIM_CCMR2_OC3CE);\r
+ }\r
+ else\r
+ {\r
+ /* Disable the OCREF clear feature for Channel 3 */\r
+ CLEAR_BIT(htim->Instance->CCMR2, TIM_CCMR2_OC3CE);\r
+ }\r
+ break;\r
+ }\r
+ case TIM_CHANNEL_4:\r
+ {\r
+ if (sClearInputConfig->ClearInputState != (uint32_t)DISABLE)\r
+ {\r
+ /* Enable the OCREF clear feature for Channel 4 */\r
+ SET_BIT(htim->Instance->CCMR2, TIM_CCMR2_OC4CE);\r
+ }\r
+ else\r
+ {\r
+ /* Disable the OCREF clear feature for Channel 4 */\r
+ CLEAR_BIT(htim->Instance->CCMR2, TIM_CCMR2_OC4CE);\r
+ }\r
+ break;\r
+ }\r
+ default:\r
+ break;\r
+ }\r
+\r
+ htim->State = HAL_TIM_STATE_READY;\r
+\r
+ __HAL_UNLOCK(htim);\r
+\r
+ return HAL_OK;\r
+}\r
+\r
+/**\r
+ * @brief Configures the clock source to be used\r
+ * @param htim TIM handle\r
+ * @param sClockSourceConfig pointer to a TIM_ClockConfigTypeDef structure that\r
+ * contains the clock source information for the TIM peripheral.\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_TIM_ConfigClockSource(TIM_HandleTypeDef *htim, TIM_ClockConfigTypeDef *sClockSourceConfig)\r
+{\r
+ uint32_t tmpsmcr;\r
+\r
+ /* Process Locked */\r
+ __HAL_LOCK(htim);\r
+\r
+ htim->State = HAL_TIM_STATE_BUSY;\r
+\r
+ /* Check the parameters */\r
+ assert_param(IS_TIM_CLOCKSOURCE(sClockSourceConfig->ClockSource));\r
+\r
+ /* Reset the SMS, TS, ECE, ETPS and ETRF bits */\r
+ tmpsmcr = htim->Instance->SMCR;\r
+ tmpsmcr &= ~(TIM_SMCR_SMS | TIM_SMCR_TS);\r
+ tmpsmcr &= ~(TIM_SMCR_ETF | TIM_SMCR_ETPS | TIM_SMCR_ECE | TIM_SMCR_ETP);\r
+ htim->Instance->SMCR = tmpsmcr;\r
+\r
+ switch (sClockSourceConfig->ClockSource)\r
+ {\r
+ case TIM_CLOCKSOURCE_INTERNAL:\r
+ {\r
+ assert_param(IS_TIM_INSTANCE(htim->Instance));\r
+ break;\r
+ }\r
+\r
+ case TIM_CLOCKSOURCE_ETRMODE1:\r
+ {\r
+ /* Check whether or not the timer instance supports external trigger input mode 1 (ETRF)*/\r
+ assert_param(IS_TIM_CLOCKSOURCE_ETRMODE1_INSTANCE(htim->Instance));\r
+\r
+ /* Check ETR input conditioning related parameters */\r
+ assert_param(IS_TIM_CLOCKPRESCALER(sClockSourceConfig->ClockPrescaler));\r
+ assert_param(IS_TIM_CLOCKPOLARITY(sClockSourceConfig->ClockPolarity));\r
+ assert_param(IS_TIM_CLOCKFILTER(sClockSourceConfig->ClockFilter));\r
+\r
+ /* Configure the ETR Clock source */\r
+ TIM_ETR_SetConfig(htim->Instance,\r
+ sClockSourceConfig->ClockPrescaler,\r
+ sClockSourceConfig->ClockPolarity,\r
+ sClockSourceConfig->ClockFilter);\r
+\r
+ /* Select the External clock mode1 and the ETRF trigger */\r
+ tmpsmcr = htim->Instance->SMCR;\r
+ tmpsmcr |= (TIM_SLAVEMODE_EXTERNAL1 | TIM_CLOCKSOURCE_ETRMODE1);\r
+ /* Write to TIMx SMCR */\r
+ htim->Instance->SMCR = tmpsmcr;\r
+ break;\r
+ }\r
+\r
+ case TIM_CLOCKSOURCE_ETRMODE2:\r
+ {\r
+ /* Check whether or not the timer instance supports external trigger input mode 2 (ETRF)*/\r
+ assert_param(IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(htim->Instance));\r
+\r
+ /* Check ETR input conditioning related parameters */\r
+ assert_param(IS_TIM_CLOCKPRESCALER(sClockSourceConfig->ClockPrescaler));\r
+ assert_param(IS_TIM_CLOCKPOLARITY(sClockSourceConfig->ClockPolarity));\r
+ assert_param(IS_TIM_CLOCKFILTER(sClockSourceConfig->ClockFilter));\r
+\r
+ /* Configure the ETR Clock source */\r
+ TIM_ETR_SetConfig(htim->Instance,\r
+ sClockSourceConfig->ClockPrescaler,\r
+ sClockSourceConfig->ClockPolarity,\r
+ sClockSourceConfig->ClockFilter);\r
+ /* Enable the External clock mode2 */\r
+ htim->Instance->SMCR |= TIM_SMCR_ECE;\r
+ break;\r
+ }\r
+\r
+ case TIM_CLOCKSOURCE_TI1:\r
+ {\r
+ /* Check whether or not the timer instance supports external clock mode 1 */\r
+ assert_param(IS_TIM_CLOCKSOURCE_TIX_INSTANCE(htim->Instance));\r
+\r
+ /* Check TI1 input conditioning related parameters */\r
+ assert_param(IS_TIM_CLOCKPOLARITY(sClockSourceConfig->ClockPolarity));\r
+ assert_param(IS_TIM_CLOCKFILTER(sClockSourceConfig->ClockFilter));\r
+\r
+ TIM_TI1_ConfigInputStage(htim->Instance,\r
+ sClockSourceConfig->ClockPolarity,\r
+ sClockSourceConfig->ClockFilter);\r
+ TIM_ITRx_SetConfig(htim->Instance, TIM_CLOCKSOURCE_TI1);\r
+ break;\r
+ }\r
+\r
+ case TIM_CLOCKSOURCE_TI2:\r
+ {\r
+ /* Check whether or not the timer instance supports external clock mode 1 (ETRF)*/\r
+ assert_param(IS_TIM_CLOCKSOURCE_TIX_INSTANCE(htim->Instance));\r
+\r
+ /* Check TI2 input conditioning related parameters */\r
+ assert_param(IS_TIM_CLOCKPOLARITY(sClockSourceConfig->ClockPolarity));\r
+ assert_param(IS_TIM_CLOCKFILTER(sClockSourceConfig->ClockFilter));\r
+\r
+ TIM_TI2_ConfigInputStage(htim->Instance,\r
+ sClockSourceConfig->ClockPolarity,\r
+ sClockSourceConfig->ClockFilter);\r
+ TIM_ITRx_SetConfig(htim->Instance, TIM_CLOCKSOURCE_TI2);\r
+ break;\r
+ }\r
+\r
+ case TIM_CLOCKSOURCE_TI1ED:\r
+ {\r
+ /* Check whether or not the timer instance supports external clock mode 1 */\r
+ assert_param(IS_TIM_CLOCKSOURCE_TIX_INSTANCE(htim->Instance));\r
+\r
+ /* Check TI1 input conditioning related parameters */\r
+ assert_param(IS_TIM_CLOCKPOLARITY(sClockSourceConfig->ClockPolarity));\r
+ assert_param(IS_TIM_CLOCKFILTER(sClockSourceConfig->ClockFilter));\r
+\r
+ TIM_TI1_ConfigInputStage(htim->Instance,\r
+ sClockSourceConfig->ClockPolarity,\r
+ sClockSourceConfig->ClockFilter);\r
+ TIM_ITRx_SetConfig(htim->Instance, TIM_CLOCKSOURCE_TI1ED);\r
+ break;\r
+ }\r
+\r
+ case TIM_CLOCKSOURCE_ITR0:\r
+ case TIM_CLOCKSOURCE_ITR1:\r
+ case TIM_CLOCKSOURCE_ITR2:\r
+ case TIM_CLOCKSOURCE_ITR3:\r
+ {\r
+ /* Check whether or not the timer instance supports internal trigger input */\r
+ assert_param(IS_TIM_CLOCKSOURCE_ITRX_INSTANCE(htim->Instance));\r
+\r
+ TIM_ITRx_SetConfig(htim->Instance, sClockSourceConfig->ClockSource);\r
+ break;\r
+ }\r
+\r
+ default:\r
+ break;\r
+ }\r
+ htim->State = HAL_TIM_STATE_READY;\r
+\r
+ __HAL_UNLOCK(htim);\r
+\r
+ return HAL_OK;\r
+}\r
+\r
+/**\r
+ * @brief Selects the signal connected to the TI1 input: direct from CH1_input\r
+ * or a XOR combination between CH1_input, CH2_input & CH3_input\r
+ * @param htim TIM handle.\r
+ * @param TI1_Selection Indicate whether or not channel 1 is connected to the\r
+ * output of a XOR gate.\r
+ * This parameter can be one of the following values:\r
+ * @arg TIM_TI1SELECTION_CH1: The TIMx_CH1 pin is connected to TI1 input\r
+ * @arg TIM_TI1SELECTION_XORCOMBINATION: The TIMx_CH1, CH2 and CH3\r
+ * pins are connected to the TI1 input (XOR combination)\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_TIM_ConfigTI1Input(TIM_HandleTypeDef *htim, uint32_t TI1_Selection)\r
+{\r
+ uint32_t tmpcr2;\r
+\r
+ /* Check the parameters */\r
+ assert_param(IS_TIM_XOR_INSTANCE(htim->Instance));\r
+ assert_param(IS_TIM_TI1SELECTION(TI1_Selection));\r
+\r
+ /* Get the TIMx CR2 register value */\r
+ tmpcr2 = htim->Instance->CR2;\r
+\r
+ /* Reset the TI1 selection */\r
+ tmpcr2 &= ~TIM_CR2_TI1S;\r
+\r
+ /* Set the TI1 selection */\r
+ tmpcr2 |= TI1_Selection;\r
+\r
+ /* Write to TIMxCR2 */\r
+ htim->Instance->CR2 = tmpcr2;\r
+\r
+ return HAL_OK;\r
+}\r
+\r
+/**\r
+ * @brief Configures the TIM in Slave mode\r
+ * @param htim TIM handle.\r
+ * @param sSlaveConfig pointer to a TIM_SlaveConfigTypeDef structure that\r
+ * contains the selected trigger (internal trigger input, filtered\r
+ * timer input or external trigger input) and the Slave mode\r
+ * (Disable, Reset, Gated, Trigger, External clock mode 1).\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_TIM_SlaveConfigSynchro(TIM_HandleTypeDef *htim, TIM_SlaveConfigTypeDef *sSlaveConfig)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_TIM_SLAVE_INSTANCE(htim->Instance));\r
+ assert_param(IS_TIM_SLAVE_MODE(sSlaveConfig->SlaveMode));\r
+ assert_param(IS_TIM_TRIGGER_SELECTION(sSlaveConfig->InputTrigger));\r
+\r
+ __HAL_LOCK(htim);\r
+\r
+ htim->State = HAL_TIM_STATE_BUSY;\r
+\r
+ if(TIM_SlaveTimer_SetConfig(htim, sSlaveConfig) != HAL_OK)\r
+ {\r
+ htim->State = HAL_TIM_STATE_READY;\r
+ __HAL_UNLOCK(htim);\r
+ return HAL_ERROR;\r
+ }\r
+\r
+ /* Disable Trigger Interrupt */\r
+ __HAL_TIM_DISABLE_IT(htim, TIM_IT_TRIGGER);\r
+\r
+ /* Disable Trigger DMA request */\r
+ __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_TRIGGER);\r
+\r
+ htim->State = HAL_TIM_STATE_READY;\r
+\r
+ __HAL_UNLOCK(htim);\r
+\r
+ return HAL_OK;\r
+}\r
+\r
+/**\r
+ * @brief Configures the TIM in Slave mode in interrupt mode\r
+ * @param htim TIM handle.\r
+ * @param sSlaveConfig pointer to a TIM_SlaveConfigTypeDef structure that\r
+ * contains the selected trigger (internal trigger input, filtered\r
+ * timer input or external trigger input) and the Slave mode\r
+ * (Disable, Reset, Gated, Trigger, External clock mode 1).\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_TIM_SlaveConfigSynchro_IT(TIM_HandleTypeDef *htim,\r
+ TIM_SlaveConfigTypeDef *sSlaveConfig)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_TIM_SLAVE_INSTANCE(htim->Instance));\r
+ assert_param(IS_TIM_SLAVE_MODE(sSlaveConfig->SlaveMode));\r
+ assert_param(IS_TIM_TRIGGER_SELECTION(sSlaveConfig->InputTrigger));\r
+\r
+ __HAL_LOCK(htim);\r
+\r
+ htim->State = HAL_TIM_STATE_BUSY;\r
+\r
+ if(TIM_SlaveTimer_SetConfig(htim, sSlaveConfig) != HAL_OK)\r
+ {\r
+ htim->State = HAL_TIM_STATE_READY;\r
+ __HAL_UNLOCK(htim);\r
+ return HAL_ERROR;\r
+ }\r
+\r
+ /* Enable Trigger Interrupt */\r
+ __HAL_TIM_ENABLE_IT(htim, TIM_IT_TRIGGER);\r
+\r
+ /* Disable Trigger DMA request */\r
+ __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_TRIGGER);\r
+\r
+ htim->State = HAL_TIM_STATE_READY;\r
+\r
+ __HAL_UNLOCK(htim);\r
+\r
+ return HAL_OK;\r
+}\r
+\r
+/**\r
+ * @brief Read the captured value from Capture Compare unit\r
+ * @param htim TIM handle.\r
+ * @param Channel TIM Channels to be enabled\r
+ * This parameter can be one of the following values:\r
+ * @arg TIM_CHANNEL_1: TIM Channel 1 selected\r
+ * @arg TIM_CHANNEL_2: TIM Channel 2 selected\r
+ * @arg TIM_CHANNEL_3: TIM Channel 3 selected\r
+ * @arg TIM_CHANNEL_4: TIM Channel 4 selected\r
+ * @retval Captured value\r
+ */\r
+uint32_t HAL_TIM_ReadCapturedValue(TIM_HandleTypeDef *htim, uint32_t Channel)\r
+{\r
+ uint32_t tmpreg = 0U;\r
+\r
+ switch (Channel)\r
+ {\r
+ case TIM_CHANNEL_1:\r
+ {\r
+ /* Check the parameters */\r
+ assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));\r
+\r
+ /* Return the capture 1 value */\r
+ tmpreg = htim->Instance->CCR1;\r
+\r
+ break;\r
+ }\r
+ case TIM_CHANNEL_2:\r
+ {\r
+ /* Check the parameters */\r
+ assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));\r
+\r
+ /* Return the capture 2 value */\r
+ tmpreg = htim->Instance->CCR2;\r
+\r
+ break;\r
+ }\r
+\r
+ case TIM_CHANNEL_3:\r
+ {\r
+ /* Check the parameters */\r
+ assert_param(IS_TIM_CC3_INSTANCE(htim->Instance));\r
+\r
+ /* Return the capture 3 value */\r
+ tmpreg = htim->Instance->CCR3;\r
+\r
+ break;\r
+ }\r
+\r
+ case TIM_CHANNEL_4:\r
+ {\r
+ /* Check the parameters */\r
+ assert_param(IS_TIM_CC4_INSTANCE(htim->Instance));\r
+\r
+ /* Return the capture 4 value */\r
+ tmpreg = htim->Instance->CCR4;\r
+\r
+ break;\r
+ }\r
+\r
+ default:\r
+ break;\r
+ }\r
+\r
+ return tmpreg;\r
+}\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup TIM_Exported_Functions_Group9 TIM Callbacks functions\r
+ * @brief TIM Callbacks functions\r
+ *\r
+@verbatim\r
+ ==============================================================================\r
+ ##### TIM Callbacks functions #####\r
+ ==============================================================================\r
+ [..]\r
+ This section provides TIM callback functions:\r
+ (+) TIM Period elapsed callback\r
+ (+) TIM Output Compare callback\r
+ (+) TIM Input capture callback\r
+ (+) TIM Trigger callback\r
+ (+) TIM Error callback\r
+\r
+@endverbatim\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @brief Period elapsed callback in non-blocking mode\r
+ * @param htim TIM handle\r
+ * @retval None\r
+ */\r
+__weak void HAL_TIM_PeriodElapsedCallback(TIM_HandleTypeDef *htim)\r
+{\r
+ /* Prevent unused argument(s) compilation warning */\r
+ UNUSED(htim);\r
+\r
+ /* NOTE : This function should not be modified, when the callback is needed,\r
+ the HAL_TIM_PeriodElapsedCallback could be implemented in the user file\r
+ */\r
+}\r
+\r
+/**\r
+ * @brief Period elapsed half complete callback in non-blocking mode\r
+ * @param htim TIM handle\r
+ * @retval None\r
+ */\r
+__weak void HAL_TIM_PeriodElapsedHalfCpltCallback(TIM_HandleTypeDef *htim)\r
+{\r
+ /* Prevent unused argument(s) compilation warning */\r
+ UNUSED(htim);\r
+\r
+ /* NOTE : This function should not be modified, when the callback is needed,\r
+ the HAL_TIM_PeriodElapsedHalfCpltCallback could be implemented in the user file\r
+ */\r
+}\r
+\r
+/**\r
+ * @brief Output Compare callback in non-blocking mode\r
+ * @param htim TIM OC handle\r
+ * @retval None\r
+ */\r
+__weak void HAL_TIM_OC_DelayElapsedCallback(TIM_HandleTypeDef *htim)\r
+{\r
+ /* Prevent unused argument(s) compilation warning */\r
+ UNUSED(htim);\r
+\r
+ /* NOTE : This function should not be modified, when the callback is needed,\r
+ the HAL_TIM_OC_DelayElapsedCallback could be implemented in the user file\r
+ */\r
+}\r
+\r
+/**\r
+ * @brief Input Capture callback in non-blocking mode\r
+ * @param htim TIM IC handle\r
+ * @retval None\r
+ */\r
+__weak void HAL_TIM_IC_CaptureCallback(TIM_HandleTypeDef *htim)\r
+{\r
+ /* Prevent unused argument(s) compilation warning */\r
+ UNUSED(htim);\r
+\r
+ /* NOTE : This function should not be modified, when the callback is needed,\r
+ the HAL_TIM_IC_CaptureCallback could be implemented in the user file\r
+ */\r
+}\r
+\r
+/**\r
+ * @brief Input Capture half complete callback in non-blocking mode\r
+ * @param htim TIM IC handle\r
+ * @retval None\r
+ */\r
+__weak void HAL_TIM_IC_CaptureHalfCpltCallback(TIM_HandleTypeDef *htim)\r
+{\r
+ /* Prevent unused argument(s) compilation warning */\r
+ UNUSED(htim);\r
+\r
+ /* NOTE : This function should not be modified, when the callback is needed,\r
+ the HAL_TIM_IC_CaptureHalfCpltCallback could be implemented in the user file\r
+ */\r
+}\r
+\r
+/**\r
+ * @brief PWM Pulse finished callback in non-blocking mode\r
+ * @param htim TIM handle\r
+ * @retval None\r
+ */\r
+__weak void HAL_TIM_PWM_PulseFinishedCallback(TIM_HandleTypeDef *htim)\r
+{\r
+ /* Prevent unused argument(s) compilation warning */\r
+ UNUSED(htim);\r
+\r
+ /* NOTE : This function should not be modified, when the callback is needed,\r
+ the HAL_TIM_PWM_PulseFinishedCallback could be implemented in the user file\r
+ */\r
+}\r
+\r
+/**\r
+ * @brief PWM Pulse finished half complete callback in non-blocking mode\r
+ * @param htim TIM handle\r
+ * @retval None\r
+ */\r
+__weak void HAL_TIM_PWM_PulseFinishedHalfCpltCallback(TIM_HandleTypeDef *htim)\r
+{\r
+ /* Prevent unused argument(s) compilation warning */\r
+ UNUSED(htim);\r
+\r
+ /* NOTE : This function should not be modified, when the callback is needed,\r
+ the HAL_TIM_PWM_PulseFinishedHalfCpltCallback could be implemented in the user file\r
+ */\r
+}\r
+\r
+/**\r
+ * @brief Hall Trigger detection callback in non-blocking mode\r
+ * @param htim TIM handle\r
+ * @retval None\r
+ */\r
+__weak void HAL_TIM_TriggerCallback(TIM_HandleTypeDef *htim)\r
+{\r
+ /* Prevent unused argument(s) compilation warning */\r
+ UNUSED(htim);\r
+\r
+ /* NOTE : This function should not be modified, when the callback is needed,\r
+ the HAL_TIM_TriggerCallback could be implemented in the user file\r
+ */\r
+}\r
+\r
+/**\r
+ * @brief Hall Trigger detection half complete callback in non-blocking mode\r
+ * @param htim TIM handle\r
+ * @retval None\r
+ */\r
+__weak void HAL_TIM_TriggerHalfCpltCallback(TIM_HandleTypeDef *htim)\r
+{\r
+ /* Prevent unused argument(s) compilation warning */\r
+ UNUSED(htim);\r
+\r
+ /* NOTE : This function should not be modified, when the callback is needed,\r
+ the HAL_TIM_TriggerHalfCpltCallback could be implemented in the user file\r
+ */\r
+}\r
+\r
+/**\r
+ * @brief Timer error callback in non-blocking mode\r
+ * @param htim TIM handle\r
+ * @retval None\r
+ */\r
+__weak void HAL_TIM_ErrorCallback(TIM_HandleTypeDef *htim)\r
+{\r
+ /* Prevent unused argument(s) compilation warning */\r
+ UNUSED(htim);\r
+\r
+ /* NOTE : This function should not be modified, when the callback is needed,\r
+ the HAL_TIM_ErrorCallback could be implemented in the user file\r
+ */\r
+}\r
+\r
+#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)\r
+/**\r
+ * @brief Register a User TIM callback to be used instead of the weak predefined callback\r
+ * @param htim tim handle\r
+ * @param CallbackID ID of the callback to be registered\r
+ * This parameter can be one of the following values:\r
+ * @arg @ref HAL_TIM_BASE_MSPINIT_CB_ID Base MspInit Callback ID\r
+ * @arg @ref HAL_TIM_BASE_MSPDEINIT_CB_ID Base MspDeInit Callback ID\r
+ * @arg @ref HAL_TIM_IC_MSPINIT_CB_ID IC MspInit Callback ID\r
+ * @arg @ref HAL_TIM_IC_MSPDEINIT_CB_ID IC MspDeInit Callback ID\r
+ * @arg @ref HAL_TIM_OC_MSPINIT_CB_ID OC MspInit Callback ID\r
+ * @arg @ref HAL_TIM_OC_MSPDEINIT_CB_ID OC MspDeInit Callback ID\r
+ * @arg @ref HAL_TIM_PWM_MSPINIT_CB_ID PWM MspInit Callback ID\r
+ * @arg @ref HAL_TIM_PWM_MSPDEINIT_CB_ID PWM MspDeInit Callback ID\r
+ * @arg @ref HAL_TIM_ONE_PULSE_MSPINIT_CB_ID One Pulse MspInit Callback ID\r
+ * @arg @ref HAL_TIM_ONE_PULSE_MSPDEINIT_CB_ID One Pulse MspDeInit Callback ID\r
+ * @arg @ref HAL_TIM_ENCODER_MSPINIT_CB_ID Encoder MspInit Callback ID\r
+ * @arg @ref HAL_TIM_ENCODER_MSPDEINIT_CB_ID Encoder MspDeInit Callback ID\r
+ * @arg @ref HAL_TIM_PERIOD_ELAPSED_CB_ID Period Elapsed Callback ID\r
+ * @arg @ref HAL_TIM_PERIOD_ELAPSED_HALF_CB_ID Period Elapsed half complete Callback ID\r
+ * @arg @ref HAL_TIM_TRIGGER_CB_ID Trigger Callback ID\r
+ * @arg @ref HAL_TIM_TRIGGER_HALF_CB_ID Trigger half complete Callback ID\r
+ * @arg @ref HAL_TIM_IC_CAPTURE_CB_ID Input Capture Callback ID\r
+ * @arg @ref HAL_TIM_IC_CAPTURE_HALF_CB_ID Input Capture half complete Callback ID\r
+ * @arg @ref HAL_TIM_OC_DELAY_ELAPSED_CB_ID Output Compare Delay Elapsed Callback ID\r
+ * @arg @ref HAL_TIM_PWM_PULSE_FINISHED_CB_ID PWM Pulse Finished Callback ID\r
+ * @arg @ref HAL_TIM_PWM_PULSE_FINISHED_HALF_CB_ID PWM Pulse Finished half complete Callback ID\r
+ * @arg @ref HAL_TIM_ERROR_CB_ID Error Callback ID\r
+ * @param pCallback pointer to the callback function\r
+ * @retval status\r
+ */\r
+HAL_StatusTypeDef HAL_TIM_RegisterCallback(TIM_HandleTypeDef *htim, HAL_TIM_CallbackIDTypeDef CallbackID, pTIM_CallbackTypeDef pCallback)\r
+{\r
+ HAL_StatusTypeDef status = HAL_OK;\r
+\r
+ if (pCallback == NULL)\r
+ {\r
+ return HAL_ERROR;\r
+ }\r
+ /* Process locked */\r
+ __HAL_LOCK(htim);\r
+\r
+ if (htim->State == HAL_TIM_STATE_READY)\r
+ {\r
+ switch (CallbackID)\r
+ {\r
+ case HAL_TIM_BASE_MSPINIT_CB_ID :\r
+ htim->Base_MspInitCallback = pCallback;\r
+ break;\r
+\r
+ case HAL_TIM_BASE_MSPDEINIT_CB_ID :\r
+ htim->Base_MspDeInitCallback = pCallback;\r
+ break;\r
+\r
+ case HAL_TIM_IC_MSPINIT_CB_ID :\r
+ htim->IC_MspInitCallback = pCallback;\r
+ break;\r
+\r
+ case HAL_TIM_IC_MSPDEINIT_CB_ID :\r
+ htim->IC_MspDeInitCallback = pCallback;\r
+ break;\r
+\r
+ case HAL_TIM_OC_MSPINIT_CB_ID :\r
+ htim->OC_MspInitCallback = pCallback;\r
+ break;\r
+\r
+ case HAL_TIM_OC_MSPDEINIT_CB_ID :\r
+ htim->OC_MspDeInitCallback = pCallback;\r
+ break;\r
+\r
+ case HAL_TIM_PWM_MSPINIT_CB_ID :\r
+ htim->PWM_MspInitCallback = pCallback;\r
+ break;\r
+\r
+ case HAL_TIM_PWM_MSPDEINIT_CB_ID :\r
+ htim->PWM_MspDeInitCallback = pCallback;\r
+ break;\r
+\r
+ case HAL_TIM_ONE_PULSE_MSPINIT_CB_ID :\r
+ htim->OnePulse_MspInitCallback = pCallback;\r
+ break;\r
+\r
+ case HAL_TIM_ONE_PULSE_MSPDEINIT_CB_ID :\r
+ htim->OnePulse_MspDeInitCallback = pCallback;\r
+ break;\r
+\r
+ case HAL_TIM_ENCODER_MSPINIT_CB_ID :\r
+ htim->Encoder_MspInitCallback = pCallback;\r
+ break;\r
+\r
+ case HAL_TIM_ENCODER_MSPDEINIT_CB_ID :\r
+ htim->Encoder_MspDeInitCallback = pCallback;\r
+ break;\r
+\r
+ case HAL_TIM_PERIOD_ELAPSED_CB_ID :\r
+ htim->PeriodElapsedCallback = pCallback;\r
+ break;\r
+\r
+ case HAL_TIM_PERIOD_ELAPSED_HALF_CB_ID :\r
+ htim->PeriodElapsedHalfCpltCallback = pCallback;\r
+ break;\r
+\r
+ case HAL_TIM_TRIGGER_CB_ID :\r
+ htim->TriggerCallback = pCallback;\r
+ break;\r
+\r
+ case HAL_TIM_TRIGGER_HALF_CB_ID :\r
+ htim->TriggerHalfCpltCallback = pCallback;\r
+ break;\r
+\r
+ case HAL_TIM_IC_CAPTURE_CB_ID :\r
+ htim->IC_CaptureCallback = pCallback;\r
+ break;\r
+\r
+ case HAL_TIM_IC_CAPTURE_HALF_CB_ID :\r
+ htim->IC_CaptureHalfCpltCallback = pCallback;\r
+ break;\r
+\r
+ case HAL_TIM_OC_DELAY_ELAPSED_CB_ID :\r
+ htim->OC_DelayElapsedCallback = pCallback;\r
+ break;\r
+\r
+ case HAL_TIM_PWM_PULSE_FINISHED_CB_ID :\r
+ htim->PWM_PulseFinishedCallback = pCallback;\r
+ break;\r
+\r
+ case HAL_TIM_PWM_PULSE_FINISHED_HALF_CB_ID :\r
+ htim->PWM_PulseFinishedHalfCpltCallback = pCallback;\r
+ break;\r
+\r
+ case HAL_TIM_ERROR_CB_ID :\r
+ htim->ErrorCallback = pCallback;\r
+ break;\r
+\r
+ default :\r
+ /* Return error status */\r
+ status = HAL_ERROR;\r
+ break;\r
+ }\r
+ }\r
+ else if (htim->State == HAL_TIM_STATE_RESET)\r
+ {\r
+ switch (CallbackID)\r
+ {\r
+ case HAL_TIM_BASE_MSPINIT_CB_ID :\r
+ htim->Base_MspInitCallback = pCallback;\r
+ break;\r
+\r
+ case HAL_TIM_BASE_MSPDEINIT_CB_ID :\r
+ htim->Base_MspDeInitCallback = pCallback;\r
+ break;\r
+\r
+ case HAL_TIM_IC_MSPINIT_CB_ID :\r
+ htim->IC_MspInitCallback = pCallback;\r
+ break;\r
+\r
+ case HAL_TIM_IC_MSPDEINIT_CB_ID :\r
+ htim->IC_MspDeInitCallback = pCallback;\r
+ break;\r
+\r
+ case HAL_TIM_OC_MSPINIT_CB_ID :\r
+ htim->OC_MspInitCallback = pCallback;\r
+ break;\r
+\r
+ case HAL_TIM_OC_MSPDEINIT_CB_ID :\r
+ htim->OC_MspDeInitCallback = pCallback;\r
+ break;\r
+\r
+ case HAL_TIM_PWM_MSPINIT_CB_ID :\r
+ htim->PWM_MspInitCallback = pCallback;\r
+ break;\r
+\r
+ case HAL_TIM_PWM_MSPDEINIT_CB_ID :\r
+ htim->PWM_MspDeInitCallback = pCallback;\r
+ break;\r
+\r
+ case HAL_TIM_ONE_PULSE_MSPINIT_CB_ID :\r
+ htim->OnePulse_MspInitCallback = pCallback;\r
+ break;\r
+\r
+ case HAL_TIM_ONE_PULSE_MSPDEINIT_CB_ID :\r
+ htim->OnePulse_MspDeInitCallback = pCallback;\r
+ break;\r
+\r
+ case HAL_TIM_ENCODER_MSPINIT_CB_ID :\r
+ htim->Encoder_MspInitCallback = pCallback;\r
+ break;\r
+\r
+ case HAL_TIM_ENCODER_MSPDEINIT_CB_ID :\r
+ htim->Encoder_MspDeInitCallback = pCallback;\r
+ break;\r
+\r
+ default :\r
+ /* Return error status */\r
+ status = HAL_ERROR;\r
+ break;\r
+ }\r
+ }\r
+ else\r
+ {\r
+ /* Return error status */\r
+ status = HAL_ERROR;\r
+ }\r
+\r
+ /* Release Lock */\r
+ __HAL_UNLOCK(htim);\r
+\r
+ return status;\r
+}\r
+\r
+/**\r
+ * @brief Unregister a TIM callback\r
+ * TIM callback is redirected to the weak predefined callback\r
+ * @param htim tim handle\r
+ * @param CallbackID ID of the callback to be unregistered\r
+ * This parameter can be one of the following values:\r
+ * @arg @ref HAL_TIM_BASE_MSPINIT_CB_ID Base MspInit Callback ID\r
+ * @arg @ref HAL_TIM_BASE_MSPDEINIT_CB_ID Base MspDeInit Callback ID\r
+ * @arg @ref HAL_TIM_IC_MSPINIT_CB_ID IC MspInit Callback ID\r
+ * @arg @ref HAL_TIM_IC_MSPDEINIT_CB_ID IC MspDeInit Callback ID\r
+ * @arg @ref HAL_TIM_OC_MSPINIT_CB_ID OC MspInit Callback ID\r
+ * @arg @ref HAL_TIM_OC_MSPDEINIT_CB_ID OC MspDeInit Callback ID\r
+ * @arg @ref HAL_TIM_PWM_MSPINIT_CB_ID PWM MspInit Callback ID\r
+ * @arg @ref HAL_TIM_PWM_MSPDEINIT_CB_ID PWM MspDeInit Callback ID\r
+ * @arg @ref HAL_TIM_ONE_PULSE_MSPINIT_CB_ID One Pulse MspInit Callback ID\r
+ * @arg @ref HAL_TIM_ONE_PULSE_MSPDEINIT_CB_ID One Pulse MspDeInit Callback ID\r
+ * @arg @ref HAL_TIM_ENCODER_MSPINIT_CB_ID Encoder MspInit Callback ID\r
+ * @arg @ref HAL_TIM_ENCODER_MSPDEINIT_CB_ID Encoder MspDeInit Callback ID\r
+ * @arg @ref HAL_TIM_PERIOD_ELAPSED_CB_ID Period Elapsed Callback ID\r
+ * @arg @ref HAL_TIM_PERIOD_ELAPSED_HALF_CB_ID Period Elapsed half complete Callback ID\r
+ * @arg @ref HAL_TIM_TRIGGER_CB_ID Trigger Callback ID\r
+ * @arg @ref HAL_TIM_TRIGGER_HALF_CB_ID Trigger half complete Callback ID\r
+ * @arg @ref HAL_TIM_IC_CAPTURE_CB_ID Input Capture Callback ID\r
+ * @arg @ref HAL_TIM_IC_CAPTURE_HALF_CB_ID Input Capture half complete Callback ID\r
+ * @arg @ref HAL_TIM_OC_DELAY_ELAPSED_CB_ID Output Compare Delay Elapsed Callback ID\r
+ * @arg @ref HAL_TIM_PWM_PULSE_FINISHED_CB_ID PWM Pulse Finished Callback ID\r
+ * @arg @ref HAL_TIM_PWM_PULSE_FINISHED_HALF_CB_ID PWM Pulse Finished half complete Callback ID\r
+ * @arg @ref HAL_TIM_ERROR_CB_ID Error Callback ID\r
+ * @retval status\r
+ */\r
+HAL_StatusTypeDef HAL_TIM_UnRegisterCallback(TIM_HandleTypeDef *htim, HAL_TIM_CallbackIDTypeDef CallbackID)\r
+{\r
+ HAL_StatusTypeDef status = HAL_OK;\r
+\r
+ /* Process locked */\r
+ __HAL_LOCK(htim);\r
+\r
+ if (htim->State == HAL_TIM_STATE_READY)\r
+ {\r
+ switch (CallbackID)\r
+ {\r
+ case HAL_TIM_BASE_MSPINIT_CB_ID :\r
+ htim->Base_MspInitCallback = HAL_TIM_Base_MspInit; /* Legacy weak Base MspInit Callback */\r
+ break;\r
+\r
+ case HAL_TIM_BASE_MSPDEINIT_CB_ID :\r
+ htim->Base_MspDeInitCallback = HAL_TIM_Base_MspDeInit; /* Legacy weak Base Msp DeInit Callback */\r
+ break;\r
+\r
+ case HAL_TIM_IC_MSPINIT_CB_ID :\r
+ htim->IC_MspInitCallback = HAL_TIM_IC_MspInit; /* Legacy weak IC Msp Init Callback */\r
+ break;\r
+\r
+ case HAL_TIM_IC_MSPDEINIT_CB_ID :\r
+ htim->IC_MspDeInitCallback = HAL_TIM_IC_MspDeInit; /* Legacy weak IC Msp DeInit Callback */\r
+ break;\r
+\r
+ case HAL_TIM_OC_MSPINIT_CB_ID :\r
+ htim->OC_MspInitCallback = HAL_TIM_OC_MspInit; /* Legacy weak OC Msp Init Callback */\r
+ break;\r
+\r
+ case HAL_TIM_OC_MSPDEINIT_CB_ID :\r
+ htim->OC_MspDeInitCallback = HAL_TIM_OC_MspDeInit; /* Legacy weak OC Msp DeInit Callback */\r
+ break;\r
+\r
+ case HAL_TIM_PWM_MSPINIT_CB_ID :\r
+ htim->PWM_MspInitCallback = HAL_TIM_PWM_MspInit; /* Legacy weak PWM Msp Init Callback */\r
+ break;\r
+\r
+ case HAL_TIM_PWM_MSPDEINIT_CB_ID :\r
+ htim->PWM_MspDeInitCallback = HAL_TIM_PWM_MspDeInit; /* Legacy weak PWM Msp DeInit Callback */\r
+ break;\r
+\r
+ case HAL_TIM_ONE_PULSE_MSPINIT_CB_ID :\r
+ htim->OnePulse_MspInitCallback = HAL_TIM_OnePulse_MspInit; /* Legacy weak One Pulse Msp Init Callback */\r
+ break;\r
+\r
+ case HAL_TIM_ONE_PULSE_MSPDEINIT_CB_ID :\r
+ htim->OnePulse_MspDeInitCallback = HAL_TIM_OnePulse_MspDeInit; /* Legacy weak One Pulse Msp DeInit Callback */\r
+ break;\r
+\r
+ case HAL_TIM_ENCODER_MSPINIT_CB_ID :\r
+ htim->Encoder_MspInitCallback = HAL_TIM_Encoder_MspInit; /* Legacy weak Encoder Msp Init Callback */\r
+ break;\r
+\r
+ case HAL_TIM_ENCODER_MSPDEINIT_CB_ID :\r
+ htim->Encoder_MspDeInitCallback = HAL_TIM_Encoder_MspDeInit; /* Legacy weak Encoder Msp DeInit Callback */\r
+ break;\r
+\r
+ case HAL_TIM_PERIOD_ELAPSED_CB_ID :\r
+ htim->PeriodElapsedCallback = HAL_TIM_PeriodElapsedCallback; /* Legacy weak Period Elapsed Callback */\r
+ break;\r
+\r
+ case HAL_TIM_PERIOD_ELAPSED_HALF_CB_ID :\r
+ htim->PeriodElapsedHalfCpltCallback = HAL_TIM_PeriodElapsedHalfCpltCallback; /* Legacy weak Period Elapsed half complete Callback */\r
+ break;\r
+\r
+ case HAL_TIM_TRIGGER_CB_ID :\r
+ htim->TriggerCallback = HAL_TIM_TriggerCallback; /* Legacy weak Trigger Callback */\r
+ break;\r
+\r
+ case HAL_TIM_TRIGGER_HALF_CB_ID :\r
+ htim->TriggerHalfCpltCallback = HAL_TIM_TriggerHalfCpltCallback; /* Legacy weak Trigger half complete Callback */\r
+ break;\r
+\r
+ case HAL_TIM_IC_CAPTURE_CB_ID :\r
+ htim->IC_CaptureCallback = HAL_TIM_IC_CaptureCallback; /* Legacy weak IC Capture Callback */\r
+ break;\r
+\r
+ case HAL_TIM_IC_CAPTURE_HALF_CB_ID :\r
+ htim->IC_CaptureHalfCpltCallback = HAL_TIM_IC_CaptureHalfCpltCallback; /* Legacy weak IC Capture half complete Callback */\r
+ break;\r
+\r
+ case HAL_TIM_OC_DELAY_ELAPSED_CB_ID :\r
+ htim->OC_DelayElapsedCallback = HAL_TIM_OC_DelayElapsedCallback; /* Legacy weak OC Delay Elapsed Callback */\r
+ break;\r
+\r
+ case HAL_TIM_PWM_PULSE_FINISHED_CB_ID :\r
+ htim->PWM_PulseFinishedCallback = HAL_TIM_PWM_PulseFinishedCallback; /* Legacy weak PWM Pulse Finished Callback */\r
+ break;\r
+\r
+ case HAL_TIM_PWM_PULSE_FINISHED_HALF_CB_ID :\r
+ htim->PWM_PulseFinishedHalfCpltCallback = HAL_TIM_PWM_PulseFinishedHalfCpltCallback; /* Legacy weak PWM Pulse Finished half complete Callback */\r
+ break;\r
+\r
+ case HAL_TIM_ERROR_CB_ID :\r
+ htim->ErrorCallback = HAL_TIM_ErrorCallback; /* Legacy weak Error Callback */\r
+ break;\r
+\r
+ default :\r
+ /* Return error status */\r
+ status = HAL_ERROR;\r
+ break;\r
+ }\r
+ }\r
+ else if (htim->State == HAL_TIM_STATE_RESET)\r
+ {\r
+ switch (CallbackID)\r
+ {\r
+ case HAL_TIM_BASE_MSPINIT_CB_ID :\r
+ htim->Base_MspInitCallback = HAL_TIM_Base_MspInit; /* Legacy weak Base MspInit Callback */\r
+ break;\r
+\r
+ case HAL_TIM_BASE_MSPDEINIT_CB_ID :\r
+ htim->Base_MspDeInitCallback = HAL_TIM_Base_MspDeInit; /* Legacy weak Base Msp DeInit Callback */\r
+ break;\r
+\r
+ case HAL_TIM_IC_MSPINIT_CB_ID :\r
+ htim->IC_MspInitCallback = HAL_TIM_IC_MspInit; /* Legacy weak IC Msp Init Callback */\r
+ break;\r
+\r
+ case HAL_TIM_IC_MSPDEINIT_CB_ID :\r
+ htim->IC_MspDeInitCallback = HAL_TIM_IC_MspDeInit; /* Legacy weak IC Msp DeInit Callback */\r
+ break;\r
+\r
+ case HAL_TIM_OC_MSPINIT_CB_ID :\r
+ htim->OC_MspInitCallback = HAL_TIM_OC_MspInit; /* Legacy weak OC Msp Init Callback */\r
+ break;\r
+\r
+ case HAL_TIM_OC_MSPDEINIT_CB_ID :\r
+ htim->OC_MspDeInitCallback = HAL_TIM_OC_MspDeInit; /* Legacy weak OC Msp DeInit Callback */\r
+ break;\r
+\r
+ case HAL_TIM_PWM_MSPINIT_CB_ID :\r
+ htim->PWM_MspInitCallback = HAL_TIM_PWM_MspInit; /* Legacy weak PWM Msp Init Callback */\r
+ break;\r
+\r
+ case HAL_TIM_PWM_MSPDEINIT_CB_ID :\r
+ htim->PWM_MspDeInitCallback = HAL_TIM_PWM_MspDeInit; /* Legacy weak PWM Msp DeInit Callback */\r
+ break;\r
+\r
+ case HAL_TIM_ONE_PULSE_MSPINIT_CB_ID :\r
+ htim->OnePulse_MspInitCallback = HAL_TIM_OnePulse_MspInit; /* Legacy weak One Pulse Msp Init Callback */\r
+ break;\r
+\r
+ case HAL_TIM_ONE_PULSE_MSPDEINIT_CB_ID :\r
+ htim->OnePulse_MspDeInitCallback = HAL_TIM_OnePulse_MspDeInit; /* Legacy weak One Pulse Msp DeInit Callback */\r
+ break;\r
+\r
+ case HAL_TIM_ENCODER_MSPINIT_CB_ID :\r
+ htim->Encoder_MspInitCallback = HAL_TIM_Encoder_MspInit; /* Legacy weak Encoder Msp Init Callback */\r
+ break;\r
+\r
+ case HAL_TIM_ENCODER_MSPDEINIT_CB_ID :\r
+ htim->Encoder_MspDeInitCallback = HAL_TIM_Encoder_MspDeInit; /* Legacy weak Encoder Msp DeInit Callback */\r
+ break;\r
+\r
+ default :\r
+ /* Return error status */\r
+ status = HAL_ERROR;\r
+ break;\r
+ }\r
+ }\r
+ else\r
+ {\r
+ /* Return error status */\r
+ status = HAL_ERROR;\r
+ }\r
+\r
+ /* Release Lock */\r
+ __HAL_UNLOCK(htim);\r
+\r
+ return status;\r
+}\r
+#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup TIM_Exported_Functions_Group10 TIM Peripheral State functions\r
+ * @brief TIM Peripheral State functions\r
+ *\r
+@verbatim\r
+ ==============================================================================\r
+ ##### Peripheral State functions #####\r
+ ==============================================================================\r
+ [..]\r
+ This subsection permits to get in run-time the status of the peripheral\r
+ and the data flow.\r
+\r
+@endverbatim\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @brief Return the TIM Base handle state.\r
+ * @param htim TIM Base handle\r
+ * @retval HAL state\r
+ */\r
+HAL_TIM_StateTypeDef HAL_TIM_Base_GetState(TIM_HandleTypeDef *htim)\r
+{\r
+ return htim->State;\r
+}\r
+\r
+/**\r
+ * @brief Return the TIM OC handle state.\r
+ * @param htim TIM Output Compare handle\r
+ * @retval HAL state\r
+ */\r
+HAL_TIM_StateTypeDef HAL_TIM_OC_GetState(TIM_HandleTypeDef *htim)\r
+{\r
+ return htim->State;\r
+}\r
+\r
+/**\r
+ * @brief Return the TIM PWM handle state.\r
+ * @param htim TIM handle\r
+ * @retval HAL state\r
+ */\r
+HAL_TIM_StateTypeDef HAL_TIM_PWM_GetState(TIM_HandleTypeDef *htim)\r
+{\r
+ return htim->State;\r
+}\r
+\r
+/**\r
+ * @brief Return the TIM Input Capture handle state.\r
+ * @param htim TIM IC handle\r
+ * @retval HAL state\r
+ */\r
+HAL_TIM_StateTypeDef HAL_TIM_IC_GetState(TIM_HandleTypeDef *htim)\r
+{\r
+ return htim->State;\r
+}\r
+\r
+/**\r
+ * @brief Return the TIM One Pulse Mode handle state.\r
+ * @param htim TIM OPM handle\r
+ * @retval HAL state\r
+ */\r
+HAL_TIM_StateTypeDef HAL_TIM_OnePulse_GetState(TIM_HandleTypeDef *htim)\r
+{\r
+ return htim->State;\r
+}\r
+\r
+/**\r
+ * @brief Return the TIM Encoder Mode handle state.\r
+ * @param htim TIM Encoder Interface handle\r
+ * @retval HAL state\r
+ */\r
+HAL_TIM_StateTypeDef HAL_TIM_Encoder_GetState(TIM_HandleTypeDef *htim)\r
+{\r
+ return htim->State;\r
+}\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup TIM_Private_Functions TIM Private Functions\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @brief TIM DMA error callback\r
+ * @param hdma pointer to DMA handle.\r
+ * @retval None\r
+ */\r
+void TIM_DMAError(DMA_HandleTypeDef *hdma)\r
+{\r
+ TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;\r
+\r
+ htim->State = HAL_TIM_STATE_READY;\r
+\r
+#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)\r
+ htim->ErrorCallback(htim);\r
+#else\r
+ HAL_TIM_ErrorCallback(htim);\r
+#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */\r
+}\r
+\r
+/**\r
+ * @brief TIM DMA Delay Pulse complete callback.\r
+ * @param hdma pointer to DMA handle.\r
+ * @retval None\r
+ */\r
+void TIM_DMADelayPulseCplt(DMA_HandleTypeDef *hdma)\r
+{\r
+ TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;\r
+\r
+ htim->State = HAL_TIM_STATE_READY;\r
+\r
+ if (hdma == htim->hdma[TIM_DMA_ID_CC1])\r
+ {\r
+ htim->Channel = HAL_TIM_ACTIVE_CHANNEL_1;\r
+ }\r
+ else if (hdma == htim->hdma[TIM_DMA_ID_CC2])\r
+ {\r
+ htim->Channel = HAL_TIM_ACTIVE_CHANNEL_2;\r
+ }\r
+ else if (hdma == htim->hdma[TIM_DMA_ID_CC3])\r
+ {\r
+ htim->Channel = HAL_TIM_ACTIVE_CHANNEL_3;\r
+ }\r
+ else if (hdma == htim->hdma[TIM_DMA_ID_CC4])\r
+ {\r
+ htim->Channel = HAL_TIM_ACTIVE_CHANNEL_4;\r
+ }\r
+ else\r
+ {\r
+ /* nothing to do */\r
+ }\r
+\r
+#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)\r
+ htim->PWM_PulseFinishedCallback(htim);\r
+#else\r
+ HAL_TIM_PWM_PulseFinishedCallback(htim);\r
+#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */\r
+\r
+ htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;\r
+}\r
+\r
+/**\r
+ * @brief TIM DMA Delay Pulse half complete callback.\r
+ * @param hdma pointer to DMA handle.\r
+ * @retval None\r
+ */\r
+void TIM_DMADelayPulseHalfCplt(DMA_HandleTypeDef *hdma)\r
+{\r
+ TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;\r
+\r
+ htim->State = HAL_TIM_STATE_READY;\r
+\r
+ if (hdma == htim->hdma[TIM_DMA_ID_CC1])\r
+ {\r
+ htim->Channel = HAL_TIM_ACTIVE_CHANNEL_1;\r
+ }\r
+ else if (hdma == htim->hdma[TIM_DMA_ID_CC2])\r
+ {\r
+ htim->Channel = HAL_TIM_ACTIVE_CHANNEL_2;\r
+ }\r
+ else if (hdma == htim->hdma[TIM_DMA_ID_CC3])\r
+ {\r
+ htim->Channel = HAL_TIM_ACTIVE_CHANNEL_3;\r
+ }\r
+ else if (hdma == htim->hdma[TIM_DMA_ID_CC4])\r
+ {\r
+ htim->Channel = HAL_TIM_ACTIVE_CHANNEL_4;\r
+ }\r
+ else\r
+ {\r
+ /* nothing to do */\r
+ }\r
+\r
+#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)\r
+ htim->PWM_PulseFinishedHalfCpltCallback(htim);\r
+#else\r
+ HAL_TIM_PWM_PulseFinishedHalfCpltCallback(htim);\r
+#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */\r
+\r
+ htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;\r
+}\r
+\r
+/**\r
+ * @brief TIM DMA Capture complete callback.\r
+ * @param hdma pointer to DMA handle.\r
+ * @retval None\r
+ */\r
+void TIM_DMACaptureCplt(DMA_HandleTypeDef *hdma)\r
+{\r
+ TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;\r
+\r
+ htim->State = HAL_TIM_STATE_READY;\r
+\r
+ if (hdma == htim->hdma[TIM_DMA_ID_CC1])\r
+ {\r
+ htim->Channel = HAL_TIM_ACTIVE_CHANNEL_1;\r
+ }\r
+ else if (hdma == htim->hdma[TIM_DMA_ID_CC2])\r
+ {\r
+ htim->Channel = HAL_TIM_ACTIVE_CHANNEL_2;\r
+ }\r
+ else if (hdma == htim->hdma[TIM_DMA_ID_CC3])\r
+ {\r
+ htim->Channel = HAL_TIM_ACTIVE_CHANNEL_3;\r
+ }\r
+ else if (hdma == htim->hdma[TIM_DMA_ID_CC4])\r
+ {\r
+ htim->Channel = HAL_TIM_ACTIVE_CHANNEL_4;\r
+ }\r
+ else\r
+ {\r
+ /* nothing to do */\r
+ }\r
+\r
+#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)\r
+ htim->IC_CaptureCallback(htim);\r
+#else\r
+ HAL_TIM_IC_CaptureCallback(htim);\r
+#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */\r
+\r
+ htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;\r
+}\r
+\r
+/**\r
+ * @brief TIM DMA Capture half complete callback.\r
+ * @param hdma pointer to DMA handle.\r
+ * @retval None\r
+ */\r
+void TIM_DMACaptureHalfCplt(DMA_HandleTypeDef *hdma)\r
+{\r
+ TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;\r
+\r
+ htim->State = HAL_TIM_STATE_READY;\r
+\r
+ if (hdma == htim->hdma[TIM_DMA_ID_CC1])\r
+ {\r
+ htim->Channel = HAL_TIM_ACTIVE_CHANNEL_1;\r
+ }\r
+ else if (hdma == htim->hdma[TIM_DMA_ID_CC2])\r
+ {\r
+ htim->Channel = HAL_TIM_ACTIVE_CHANNEL_2;\r
+ }\r
+ else if (hdma == htim->hdma[TIM_DMA_ID_CC3])\r
+ {\r
+ htim->Channel = HAL_TIM_ACTIVE_CHANNEL_3;\r
+ }\r
+ else if (hdma == htim->hdma[TIM_DMA_ID_CC4])\r
+ {\r
+ htim->Channel = HAL_TIM_ACTIVE_CHANNEL_4;\r
+ }\r
+ else\r
+ {\r
+ /* nothing to do */\r
+ }\r
+\r
+#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)\r
+ htim->IC_CaptureHalfCpltCallback(htim);\r
+#else\r
+ HAL_TIM_IC_CaptureHalfCpltCallback(htim);\r
+#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */\r
+\r
+ htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;\r
+}\r
+\r
+/**\r
+ * @brief TIM DMA Period Elapse complete callback.\r
+ * @param hdma pointer to DMA handle.\r
+ * @retval None\r
+ */\r
+static void TIM_DMAPeriodElapsedCplt(DMA_HandleTypeDef *hdma)\r
+{\r
+ TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;\r
+\r
+ htim->State = HAL_TIM_STATE_READY;\r
+\r
+#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)\r
+ htim->PeriodElapsedCallback(htim);\r
+#else\r
+ HAL_TIM_PeriodElapsedCallback(htim);\r
+#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */\r
+}\r
+\r
+/**\r
+ * @brief TIM DMA Period Elapse half complete callback.\r
+ * @param hdma pointer to DMA handle.\r
+ * @retval None\r
+ */\r
+static void TIM_DMAPeriodElapsedHalfCplt(DMA_HandleTypeDef *hdma)\r
+{\r
+ TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;\r
+\r
+ htim->State = HAL_TIM_STATE_READY;\r
+\r
+#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)\r
+ htim->PeriodElapsedHalfCpltCallback(htim);\r
+#else\r
+ HAL_TIM_PeriodElapsedHalfCpltCallback(htim);\r
+#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */\r
+}\r
+\r
+/**\r
+ * @brief TIM DMA Trigger callback.\r
+ * @param hdma pointer to DMA handle.\r
+ * @retval None\r
+ */\r
+static void TIM_DMATriggerCplt(DMA_HandleTypeDef *hdma)\r
+{\r
+ TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;\r
+\r
+ htim->State = HAL_TIM_STATE_READY;\r
+\r
+#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)\r
+ htim->TriggerCallback(htim);\r
+#else\r
+ HAL_TIM_TriggerCallback(htim);\r
+#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */\r
+}\r
+\r
+/**\r
+ * @brief TIM DMA Trigger half complete callback.\r
+ * @param hdma pointer to DMA handle.\r
+ * @retval None\r
+ */\r
+static void TIM_DMATriggerHalfCplt(DMA_HandleTypeDef *hdma)\r
+{\r
+ TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;\r
+\r
+ htim->State = HAL_TIM_STATE_READY;\r
+\r
+#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)\r
+ htim->TriggerHalfCpltCallback(htim);\r
+#else\r
+ HAL_TIM_TriggerHalfCpltCallback(htim);\r
+#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */\r
+}\r
+\r
+/**\r
+ * @brief Time Base configuration\r
+ * @param TIMx TIM peripheral\r
+ * @param Structure TIM Base configuration structure\r
+ * @retval None\r
+ */\r
+void TIM_Base_SetConfig(TIM_TypeDef *TIMx, TIM_Base_InitTypeDef *Structure)\r
+{\r
+ uint32_t tmpcr1;\r
+ tmpcr1 = TIMx->CR1;\r
+\r
+ /* Set TIM Time Base Unit parameters ---------------------------------------*/\r
+ if (IS_TIM_COUNTER_MODE_SELECT_INSTANCE(TIMx))\r
+ {\r
+ /* Select the Counter Mode */\r
+ tmpcr1 &= ~(TIM_CR1_DIR | TIM_CR1_CMS);\r
+ tmpcr1 |= Structure->CounterMode;\r
+ }\r
+\r
+ if (IS_TIM_CLOCK_DIVISION_INSTANCE(TIMx))\r
+ {\r
+ /* Set the clock division */\r
+ tmpcr1 &= ~TIM_CR1_CKD;\r
+ tmpcr1 |= (uint32_t)Structure->ClockDivision;\r
+ }\r
+\r
+ /* Set the auto-reload preload */\r
+ MODIFY_REG(tmpcr1, TIM_CR1_ARPE, Structure->AutoReloadPreload);\r
+\r
+ TIMx->CR1 = tmpcr1;\r
+\r
+ /* Set the Autoreload value */\r
+ TIMx->ARR = (uint32_t)Structure->Period ;\r
+\r
+ /* Set the Prescaler value */\r
+ TIMx->PSC = Structure->Prescaler;\r
+\r
+ /* Generate an update event to reload the Prescaler\r
+ and the repetition counter (only for advanced timer) value immediately */\r
+ TIMx->EGR = TIM_EGR_UG;\r
+}\r
+\r
+/**\r
+ * @brief Timer Output Compare 1 configuration\r
+ * @param TIMx to select the TIM peripheral\r
+ * @param OC_Config The ouput configuration structure\r
+ * @retval None\r
+ */\r
+static void TIM_OC1_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config)\r
+{\r
+ uint32_t tmpccmrx;\r
+ uint32_t tmpccer;\r
+ uint32_t tmpcr2;\r
+\r
+ /* Disable the Channel 1: Reset the CC1E Bit */\r
+ TIMx->CCER &= ~TIM_CCER_CC1E;\r
+\r
+ /* Get the TIMx CCER register value */\r
+ tmpccer = TIMx->CCER;\r
+ /* Get the TIMx CR2 register value */\r
+ tmpcr2 = TIMx->CR2;\r
+\r
+ /* Get the TIMx CCMR1 register value */\r
+ tmpccmrx = TIMx->CCMR1;\r
+\r
+ /* Reset the Output Compare Mode Bits */\r
+ tmpccmrx &= ~TIM_CCMR1_OC1M;\r
+ tmpccmrx &= ~TIM_CCMR1_CC1S;\r
+ /* Select the Output Compare Mode */\r
+ tmpccmrx |= OC_Config->OCMode;\r
+\r
+ /* Reset the Output Polarity level */\r
+ tmpccer &= ~TIM_CCER_CC1P;\r
+ /* Set the Output Compare Polarity */\r
+ tmpccer |= OC_Config->OCPolarity;\r
+\r
+ /* Write to TIMx CR2 */\r
+ TIMx->CR2 = tmpcr2;\r
+\r
+ /* Write to TIMx CCMR1 */\r
+ TIMx->CCMR1 = tmpccmrx;\r
+\r
+ /* Set the Capture Compare Register value */\r
+ TIMx->CCR1 = OC_Config->Pulse;\r
+\r
+ /* Write to TIMx CCER */\r
+ TIMx->CCER = tmpccer;\r
+}\r
+\r
+/**\r
+ * @brief Timer Output Compare 2 configuration\r
+ * @param TIMx to select the TIM peripheral\r
+ * @param OC_Config The ouput configuration structure\r
+ * @retval None\r
+ */\r
+static void TIM_OC2_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config)\r
+{\r
+ uint32_t tmpccmrx;\r
+ uint32_t tmpccer;\r
+ uint32_t tmpcr2;\r
+\r
+ /* Disable the Channel 2: Reset the CC2E Bit */\r
+ TIMx->CCER &= ~TIM_CCER_CC2E;\r
+\r
+ /* Get the TIMx CCER register value */\r
+ tmpccer = TIMx->CCER;\r
+ /* Get the TIMx CR2 register value */\r
+ tmpcr2 = TIMx->CR2;\r
+\r
+ /* Get the TIMx CCMR1 register value */\r
+ tmpccmrx = TIMx->CCMR1;\r
+\r
+ /* Reset the Output Compare mode and Capture/Compare selection Bits */\r
+ tmpccmrx &= ~TIM_CCMR1_OC2M;\r
+ tmpccmrx &= ~TIM_CCMR1_CC2S;\r
+\r
+ /* Select the Output Compare Mode */\r
+ tmpccmrx |= (OC_Config->OCMode << 8U);\r
+\r
+ /* Reset the Output Polarity level */\r
+ tmpccer &= ~TIM_CCER_CC2P;\r
+ /* Set the Output Compare Polarity */\r
+ tmpccer |= (OC_Config->OCPolarity << 4U);\r
+\r
+ /* Write to TIMx CR2 */\r
+ TIMx->CR2 = tmpcr2;\r
+\r
+ /* Write to TIMx CCMR1 */\r
+ TIMx->CCMR1 = tmpccmrx;\r
+\r
+ /* Set the Capture Compare Register value */\r
+ TIMx->CCR2 = OC_Config->Pulse;\r
+\r
+ /* Write to TIMx CCER */\r
+ TIMx->CCER = tmpccer;\r
+}\r
+\r
+/**\r
+ * @brief Timer Output Compare 3 configuration\r
+ * @param TIMx to select the TIM peripheral\r
+ * @param OC_Config The ouput configuration structure\r
+ * @retval None\r
+ */\r
+static void TIM_OC3_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config)\r
+{\r
+ uint32_t tmpccmrx;\r
+ uint32_t tmpccer;\r
+ uint32_t tmpcr2;\r
+\r
+ /* Disable the Channel 3: Reset the CC2E Bit */\r
+ TIMx->CCER &= ~TIM_CCER_CC3E;\r
+\r
+ /* Get the TIMx CCER register value */\r
+ tmpccer = TIMx->CCER;\r
+ /* Get the TIMx CR2 register value */\r
+ tmpcr2 = TIMx->CR2;\r
+\r
+ /* Get the TIMx CCMR2 register value */\r
+ tmpccmrx = TIMx->CCMR2;\r
+\r
+ /* Reset the Output Compare mode and Capture/Compare selection Bits */\r
+ tmpccmrx &= ~TIM_CCMR2_OC3M;\r
+ tmpccmrx &= ~TIM_CCMR2_CC3S;\r
+ /* Select the Output Compare Mode */\r
+ tmpccmrx |= OC_Config->OCMode;\r
+\r
+ /* Reset the Output Polarity level */\r
+ tmpccer &= ~TIM_CCER_CC3P;\r
+ /* Set the Output Compare Polarity */\r
+ tmpccer |= (OC_Config->OCPolarity << 8U);\r
+\r
+ /* Write to TIMx CR2 */\r
+ TIMx->CR2 = tmpcr2;\r
+\r
+ /* Write to TIMx CCMR2 */\r
+ TIMx->CCMR2 = tmpccmrx;\r
+\r
+ /* Set the Capture Compare Register value */\r
+ TIMx->CCR3 = OC_Config->Pulse;\r
+\r
+ /* Write to TIMx CCER */\r
+ TIMx->CCER = tmpccer;\r
+}\r
+\r
+/**\r
+ * @brief Timer Output Compare 4 configuration\r
+ * @param TIMx to select the TIM peripheral\r
+ * @param OC_Config The ouput configuration structure\r
+ * @retval None\r
+ */\r
+static void TIM_OC4_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config)\r
+{\r
+ uint32_t tmpccmrx;\r
+ uint32_t tmpccer;\r
+ uint32_t tmpcr2;\r
+\r
+ /* Disable the Channel 4: Reset the CC4E Bit */\r
+ TIMx->CCER &= ~TIM_CCER_CC4E;\r
+\r
+ /* Get the TIMx CCER register value */\r
+ tmpccer = TIMx->CCER;\r
+ /* Get the TIMx CR2 register value */\r
+ tmpcr2 = TIMx->CR2;\r
+\r
+ /* Get the TIMx CCMR2 register value */\r
+ tmpccmrx = TIMx->CCMR2;\r
+\r
+ /* Reset the Output Compare mode and Capture/Compare selection Bits */\r
+ tmpccmrx &= ~TIM_CCMR2_OC4M;\r
+ tmpccmrx &= ~TIM_CCMR2_CC4S;\r
+\r
+ /* Select the Output Compare Mode */\r
+ tmpccmrx |= (OC_Config->OCMode << 8U);\r
+\r
+ /* Reset the Output Polarity level */\r
+ tmpccer &= ~TIM_CCER_CC4P;\r
+ /* Set the Output Compare Polarity */\r
+ tmpccer |= (OC_Config->OCPolarity << 12U);\r
+\r
+ /* Write to TIMx CR2 */\r
+ TIMx->CR2 = tmpcr2;\r
+\r
+ /* Write to TIMx CCMR2 */\r
+ TIMx->CCMR2 = tmpccmrx;\r
+\r
+ /* Set the Capture Compare Register value */\r
+ TIMx->CCR4 = OC_Config->Pulse;\r
+\r
+ /* Write to TIMx CCER */\r
+ TIMx->CCER = tmpccer;\r
+}\r
+\r
+/**\r
+ * @brief Slave Timer configuration function\r
+ * @param htim TIM handle\r
+ * @param sSlaveConfig Slave timer configuration\r
+ * @retval None\r
+ */\r
+static HAL_StatusTypeDef TIM_SlaveTimer_SetConfig(TIM_HandleTypeDef *htim,\r
+ TIM_SlaveConfigTypeDef *sSlaveConfig)\r
+{\r
+ uint32_t tmpsmcr;\r
+ uint32_t tmpccmr1;\r
+ uint32_t tmpccer;\r
+\r
+ /* Get the TIMx SMCR register value */\r
+ tmpsmcr = htim->Instance->SMCR;\r
+\r
+ /* Reset the Trigger Selection Bits */\r
+ tmpsmcr &= ~TIM_SMCR_TS;\r
+ /* Set the Input Trigger source */\r
+ tmpsmcr |= sSlaveConfig->InputTrigger;\r
+\r
+ /* Reset the slave mode Bits */\r
+ tmpsmcr &= ~TIM_SMCR_SMS;\r
+ /* Set the slave mode */\r
+ tmpsmcr |= sSlaveConfig->SlaveMode;\r
+\r
+ /* Write to TIMx SMCR */\r
+ htim->Instance->SMCR = tmpsmcr;\r
+\r
+ /* Configure the trigger prescaler, filter, and polarity */\r
+ switch (sSlaveConfig->InputTrigger)\r
+ {\r
+ case TIM_TS_ETRF:\r
+ {\r
+ /* Check the parameters */\r
+ assert_param(IS_TIM_CLOCKSOURCE_ETRMODE1_INSTANCE(htim->Instance));\r
+ assert_param(IS_TIM_TRIGGERPRESCALER(sSlaveConfig->TriggerPrescaler));\r
+ assert_param(IS_TIM_TRIGGERPOLARITY(sSlaveConfig->TriggerPolarity));\r
+ assert_param(IS_TIM_TRIGGERFILTER(sSlaveConfig->TriggerFilter));\r
+ /* Configure the ETR Trigger source */\r
+ TIM_ETR_SetConfig(htim->Instance,\r
+ sSlaveConfig->TriggerPrescaler,\r
+ sSlaveConfig->TriggerPolarity,\r
+ sSlaveConfig->TriggerFilter);\r
+ break;\r
+ }\r
+\r
+ case TIM_TS_TI1F_ED:\r
+ {\r
+ /* Check the parameters */\r
+ assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));\r
+ assert_param(IS_TIM_TRIGGERFILTER(sSlaveConfig->TriggerFilter));\r
+\r
+ if(sSlaveConfig->SlaveMode == TIM_SLAVEMODE_GATED)\r
+ {\r
+ return HAL_ERROR;\r
+ }\r
+\r
+ /* Disable the Channel 1: Reset the CC1E Bit */\r
+ tmpccer = htim->Instance->CCER;\r
+ htim->Instance->CCER &= ~TIM_CCER_CC1E;\r
+ tmpccmr1 = htim->Instance->CCMR1;\r
+\r
+ /* Set the filter */\r
+ tmpccmr1 &= ~TIM_CCMR1_IC1F;\r
+ tmpccmr1 |= ((sSlaveConfig->TriggerFilter) << 4U);\r
+\r
+ /* Write to TIMx CCMR1 and CCER registers */\r
+ htim->Instance->CCMR1 = tmpccmr1;\r
+ htim->Instance->CCER = tmpccer;\r
+ break;\r
+ }\r
+\r
+ case TIM_TS_TI1FP1:\r
+ {\r
+ /* Check the parameters */\r
+ assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));\r
+ assert_param(IS_TIM_TRIGGERPOLARITY(sSlaveConfig->TriggerPolarity));\r
+ assert_param(IS_TIM_TRIGGERFILTER(sSlaveConfig->TriggerFilter));\r
+\r
+ /* Configure TI1 Filter and Polarity */\r
+ TIM_TI1_ConfigInputStage(htim->Instance,\r
+ sSlaveConfig->TriggerPolarity,\r
+ sSlaveConfig->TriggerFilter);\r
+ break;\r
+ }\r
+\r
+ case TIM_TS_TI2FP2:\r
+ {\r
+ /* Check the parameters */\r
+ assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));\r
+ assert_param(IS_TIM_TRIGGERPOLARITY(sSlaveConfig->TriggerPolarity));\r
+ assert_param(IS_TIM_TRIGGERFILTER(sSlaveConfig->TriggerFilter));\r
+\r
+ /* Configure TI2 Filter and Polarity */\r
+ TIM_TI2_ConfigInputStage(htim->Instance,\r
+ sSlaveConfig->TriggerPolarity,\r
+ sSlaveConfig->TriggerFilter);\r
+ break;\r
+ }\r
+\r
+ case TIM_TS_ITR0:\r
+ case TIM_TS_ITR1:\r
+ case TIM_TS_ITR2:\r
+ case TIM_TS_ITR3:\r
+ {\r
+ /* Check the parameter */\r
+ assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));\r
+ break;\r
+ }\r
+\r
+ default:\r
+ break;\r
+ }\r
+ return HAL_OK;\r
+}\r
+\r
+/**\r
+ * @brief Configure the TI1 as Input.\r
+ * @param TIMx to select the TIM peripheral.\r
+ * @param TIM_ICPolarity The Input Polarity.\r
+ * This parameter can be one of the following values:\r
+ * @arg TIM_ICPOLARITY_RISING\r
+ * @arg TIM_ICPOLARITY_FALLING\r
+ * @arg TIM_ICPOLARITY_BOTHEDGE\r
+ * @param TIM_ICSelection specifies the input to be used.\r
+ * This parameter can be one of the following values:\r
+ * @arg TIM_ICSELECTION_DIRECTTI: TIM Input 1 is selected to be connected to IC1.\r
+ * @arg TIM_ICSELECTION_INDIRECTTI: TIM Input 1 is selected to be connected to IC2.\r
+ * @arg TIM_ICSELECTION_TRC: TIM Input 1 is selected to be connected to TRC.\r
+ * @param TIM_ICFilter Specifies the Input Capture Filter.\r
+ * This parameter must be a value between 0x00 and 0x0F.\r
+ * @retval None\r
+ * @note TIM_ICFilter and TIM_ICPolarity are not used in INDIRECT mode as TI2FP1\r
+ * (on channel2 path) is used as the input signal. Therefore CCMR1 must be\r
+ * protected against un-initialized filter and polarity values.\r
+ */\r
+static void TIM_TI1_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection,\r
+ uint32_t TIM_ICFilter)\r
+{\r
+ uint32_t tmpccmr1;\r
+ uint32_t tmpccer;\r
+\r
+ /* Disable the Channel 1: Reset the CC1E Bit */\r
+ TIMx->CCER &= ~TIM_CCER_CC1E;\r
+ tmpccmr1 = TIMx->CCMR1;\r
+ tmpccer = TIMx->CCER;\r
+\r
+ /* Select the Input */\r
+ if (IS_TIM_CC2_INSTANCE(TIMx) != RESET)\r
+ {\r
+ tmpccmr1 &= ~TIM_CCMR1_CC1S;\r
+ tmpccmr1 |= TIM_ICSelection;\r
+ }\r
+ else\r
+ {\r
+ tmpccmr1 |= TIM_CCMR1_CC1S_0;\r
+ }\r
+\r
+ /* Set the filter */\r
+ tmpccmr1 &= ~TIM_CCMR1_IC1F;\r
+ tmpccmr1 |= ((TIM_ICFilter << 4U) & TIM_CCMR1_IC1F);\r
+\r
+ /* Select the Polarity and set the CC1E Bit */\r
+ tmpccer &= ~(TIM_CCER_CC1P | TIM_CCER_CC1NP);\r
+ tmpccer |= (TIM_ICPolarity & (TIM_CCER_CC1P | TIM_CCER_CC1NP));\r
+\r
+ /* Write to TIMx CCMR1 and CCER registers */\r
+ TIMx->CCMR1 = tmpccmr1;\r
+ TIMx->CCER = tmpccer;\r
+}\r
+\r
+/**\r
+ * @brief Configure the Polarity and Filter for TI1.\r
+ * @param TIMx to select the TIM peripheral.\r
+ * @param TIM_ICPolarity The Input Polarity.\r
+ * This parameter can be one of the following values:\r
+ * @arg TIM_ICPOLARITY_RISING\r
+ * @arg TIM_ICPOLARITY_FALLING\r
+ * @arg TIM_ICPOLARITY_BOTHEDGE\r
+ * @param TIM_ICFilter Specifies the Input Capture Filter.\r
+ * This parameter must be a value between 0x00 and 0x0F.\r
+ * @retval None\r
+ */\r
+static void TIM_TI1_ConfigInputStage(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICFilter)\r
+{\r
+ uint32_t tmpccmr1;\r
+ uint32_t tmpccer;\r
+\r
+ /* Disable the Channel 1: Reset the CC1E Bit */\r
+ tmpccer = TIMx->CCER;\r
+ TIMx->CCER &= ~TIM_CCER_CC1E;\r
+ tmpccmr1 = TIMx->CCMR1;\r
+\r
+ /* Set the filter */\r
+ tmpccmr1 &= ~TIM_CCMR1_IC1F;\r
+ tmpccmr1 |= (TIM_ICFilter << 4U);\r
+\r
+ /* Select the Polarity and set the CC1E Bit */\r
+ tmpccer &= ~(TIM_CCER_CC1P | TIM_CCER_CC1NP);\r
+ tmpccer |= TIM_ICPolarity;\r
+\r
+ /* Write to TIMx CCMR1 and CCER registers */\r
+ TIMx->CCMR1 = tmpccmr1;\r
+ TIMx->CCER = tmpccer;\r
+}\r
+\r
+/**\r
+ * @brief Configure the TI2 as Input.\r
+ * @param TIMx to select the TIM peripheral\r
+ * @param TIM_ICPolarity The Input Polarity.\r
+ * This parameter can be one of the following values:\r
+ * @arg TIM_ICPOLARITY_RISING\r
+ * @arg TIM_ICPOLARITY_FALLING\r
+ * @arg TIM_ICPOLARITY_BOTHEDGE\r
+ * @param TIM_ICSelection specifies the input to be used.\r
+ * This parameter can be one of the following values:\r
+ * @arg TIM_ICSELECTION_DIRECTTI: TIM Input 2 is selected to be connected to IC2.\r
+ * @arg TIM_ICSELECTION_INDIRECTTI: TIM Input 2 is selected to be connected to IC1.\r
+ * @arg TIM_ICSELECTION_TRC: TIM Input 2 is selected to be connected to TRC.\r
+ * @param TIM_ICFilter Specifies the Input Capture Filter.\r
+ * This parameter must be a value between 0x00 and 0x0F.\r
+ * @retval None\r
+ * @note TIM_ICFilter and TIM_ICPolarity are not used in INDIRECT mode as TI1FP2\r
+ * (on channel1 path) is used as the input signal. Therefore CCMR1 must be\r
+ * protected against un-initialized filter and polarity values.\r
+ */\r
+static void TIM_TI2_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection,\r
+ uint32_t TIM_ICFilter)\r
+{\r
+ uint32_t tmpccmr1;\r
+ uint32_t tmpccer;\r
+\r
+ /* Disable the Channel 2: Reset the CC2E Bit */\r
+ TIMx->CCER &= ~TIM_CCER_CC2E;\r
+ tmpccmr1 = TIMx->CCMR1;\r
+ tmpccer = TIMx->CCER;\r
+\r
+ /* Select the Input */\r
+ tmpccmr1 &= ~TIM_CCMR1_CC2S;\r
+ tmpccmr1 |= (TIM_ICSelection << 8U);\r
+\r
+ /* Set the filter */\r
+ tmpccmr1 &= ~TIM_CCMR1_IC2F;\r
+ tmpccmr1 |= ((TIM_ICFilter << 12U) & TIM_CCMR1_IC2F);\r
+\r
+ /* Select the Polarity and set the CC2E Bit */\r
+ tmpccer &= ~(TIM_CCER_CC2P | TIM_CCER_CC2NP);\r
+ tmpccer |= ((TIM_ICPolarity << 4U) & (TIM_CCER_CC2P | TIM_CCER_CC2NP));\r
+\r
+ /* Write to TIMx CCMR1 and CCER registers */\r
+ TIMx->CCMR1 = tmpccmr1 ;\r
+ TIMx->CCER = tmpccer;\r
+}\r
+\r
+/**\r
+ * @brief Configure the Polarity and Filter for TI2.\r
+ * @param TIMx to select the TIM peripheral.\r
+ * @param TIM_ICPolarity The Input Polarity.\r
+ * This parameter can be one of the following values:\r
+ * @arg TIM_ICPOLARITY_RISING\r
+ * @arg TIM_ICPOLARITY_FALLING\r
+ * @arg TIM_ICPOLARITY_BOTHEDGE\r
+ * @param TIM_ICFilter Specifies the Input Capture Filter.\r
+ * This parameter must be a value between 0x00 and 0x0F.\r
+ * @retval None\r
+ */\r
+static void TIM_TI2_ConfigInputStage(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICFilter)\r
+{\r
+ uint32_t tmpccmr1;\r
+ uint32_t tmpccer;\r
+\r
+ /* Disable the Channel 2: Reset the CC2E Bit */\r
+ TIMx->CCER &= ~TIM_CCER_CC2E;\r
+ tmpccmr1 = TIMx->CCMR1;\r
+ tmpccer = TIMx->CCER;\r
+\r
+ /* Set the filter */\r
+ tmpccmr1 &= ~TIM_CCMR1_IC2F;\r
+ tmpccmr1 |= (TIM_ICFilter << 12U);\r
+\r
+ /* Select the Polarity and set the CC2E Bit */\r
+ tmpccer &= ~(TIM_CCER_CC2P | TIM_CCER_CC2NP);\r
+ tmpccer |= (TIM_ICPolarity << 4U);\r
+\r
+ /* Write to TIMx CCMR1 and CCER registers */\r
+ TIMx->CCMR1 = tmpccmr1 ;\r
+ TIMx->CCER = tmpccer;\r
+}\r
+\r
+/**\r
+ * @brief Configure the TI3 as Input.\r
+ * @param TIMx to select the TIM peripheral\r
+ * @param TIM_ICPolarity The Input Polarity.\r
+ * This parameter can be one of the following values:\r
+ * @arg TIM_ICPOLARITY_RISING\r
+ * @arg TIM_ICPOLARITY_FALLING\r
+ * @arg TIM_ICPOLARITY_BOTHEDGE\r
+ * @param TIM_ICSelection specifies the input to be used.\r
+ * This parameter can be one of the following values:\r
+ * @arg TIM_ICSELECTION_DIRECTTI: TIM Input 3 is selected to be connected to IC3.\r
+ * @arg TIM_ICSELECTION_INDIRECTTI: TIM Input 3 is selected to be connected to IC4.\r
+ * @arg TIM_ICSELECTION_TRC: TIM Input 3 is selected to be connected to TRC.\r
+ * @param TIM_ICFilter Specifies the Input Capture Filter.\r
+ * This parameter must be a value between 0x00 and 0x0F.\r
+ * @retval None\r
+ * @note TIM_ICFilter and TIM_ICPolarity are not used in INDIRECT mode as TI3FP4\r
+ * (on channel1 path) is used as the input signal. Therefore CCMR2 must be\r
+ * protected against un-initialized filter and polarity values.\r
+ */\r
+static void TIM_TI3_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection,\r
+ uint32_t TIM_ICFilter)\r
+{\r
+ uint32_t tmpccmr2;\r
+ uint32_t tmpccer;\r
+\r
+ /* Disable the Channel 3: Reset the CC3E Bit */\r
+ TIMx->CCER &= ~TIM_CCER_CC3E;\r
+ tmpccmr2 = TIMx->CCMR2;\r
+ tmpccer = TIMx->CCER;\r
+\r
+ /* Select the Input */\r
+ tmpccmr2 &= ~TIM_CCMR2_CC3S;\r
+ tmpccmr2 |= TIM_ICSelection;\r
+\r
+ /* Set the filter */\r
+ tmpccmr2 &= ~TIM_CCMR2_IC3F;\r
+ tmpccmr2 |= ((TIM_ICFilter << 4U) & TIM_CCMR2_IC3F);\r
+\r
+ /* Select the Polarity and set the CC3E Bit */\r
+ tmpccer &= ~(TIM_CCER_CC3P | TIM_CCER_CC3NP);\r
+ tmpccer |= ((TIM_ICPolarity << 8U) & (TIM_CCER_CC3P | TIM_CCER_CC3NP));\r
+\r
+ /* Write to TIMx CCMR2 and CCER registers */\r
+ TIMx->CCMR2 = tmpccmr2;\r
+ TIMx->CCER = tmpccer;\r
+}\r
+\r
+/**\r
+ * @brief Configure the TI4 as Input.\r
+ * @param TIMx to select the TIM peripheral\r
+ * @param TIM_ICPolarity The Input Polarity.\r
+ * This parameter can be one of the following values:\r
+ * @arg TIM_ICPOLARITY_RISING\r
+ * @arg TIM_ICPOLARITY_FALLING\r
+ * @arg TIM_ICPOLARITY_BOTHEDGE\r
+ * @param TIM_ICSelection specifies the input to be used.\r
+ * This parameter can be one of the following values:\r
+ * @arg TIM_ICSELECTION_DIRECTTI: TIM Input 4 is selected to be connected to IC4.\r
+ * @arg TIM_ICSELECTION_INDIRECTTI: TIM Input 4 is selected to be connected to IC3.\r
+ * @arg TIM_ICSELECTION_TRC: TIM Input 4 is selected to be connected to TRC.\r
+ * @param TIM_ICFilter Specifies the Input Capture Filter.\r
+ * This parameter must be a value between 0x00 and 0x0F.\r
+ * @note TIM_ICFilter and TIM_ICPolarity are not used in INDIRECT mode as TI4FP3\r
+ * (on channel1 path) is used as the input signal. Therefore CCMR2 must be\r
+ * protected against un-initialized filter and polarity values.\r
+ * @retval None\r
+ */\r
+static void TIM_TI4_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection,\r
+ uint32_t TIM_ICFilter)\r
+{\r
+ uint32_t tmpccmr2;\r
+ uint32_t tmpccer;\r
+\r
+ /* Disable the Channel 4: Reset the CC4E Bit */\r
+ TIMx->CCER &= ~TIM_CCER_CC4E;\r
+ tmpccmr2 = TIMx->CCMR2;\r
+ tmpccer = TIMx->CCER;\r
+\r
+ /* Select the Input */\r
+ tmpccmr2 &= ~TIM_CCMR2_CC4S;\r
+ tmpccmr2 |= (TIM_ICSelection << 8U);\r
+\r
+ /* Set the filter */\r
+ tmpccmr2 &= ~TIM_CCMR2_IC4F;\r
+ tmpccmr2 |= ((TIM_ICFilter << 12U) & TIM_CCMR2_IC4F);\r
+\r
+ /* Select the Polarity and set the CC4E Bit */\r
+ tmpccer &= ~(TIM_CCER_CC4P | TIM_CCER_CC4NP);\r
+ tmpccer |= ((TIM_ICPolarity << 12U) & (TIM_CCER_CC4P | TIM_CCER_CC4NP));\r
+\r
+ /* Write to TIMx CCMR2 and CCER registers */\r
+ TIMx->CCMR2 = tmpccmr2;\r
+ TIMx->CCER = tmpccer ;\r
+}\r
+\r
+/**\r
+ * @brief Selects the Input Trigger source\r
+ * @param TIMx to select the TIM peripheral\r
+ * @param InputTriggerSource The Input Trigger source.\r
+ * This parameter can be one of the following values:\r
+ * @arg TIM_TS_ITR0: Internal Trigger 0\r
+ * @arg TIM_TS_ITR1: Internal Trigger 1\r
+ * @arg TIM_TS_ITR2: Internal Trigger 2\r
+ * @arg TIM_TS_ITR3: Internal Trigger 3\r
+ * @arg TIM_TS_TI1F_ED: TI1 Edge Detector\r
+ * @arg TIM_TS_TI1FP1: Filtered Timer Input 1\r
+ * @arg TIM_TS_TI2FP2: Filtered Timer Input 2\r
+ * @arg TIM_TS_ETRF: External Trigger input\r
+ * @retval None\r
+ */\r
+static void TIM_ITRx_SetConfig(TIM_TypeDef *TIMx, uint32_t InputTriggerSource)\r
+{\r
+ uint32_t tmpsmcr;\r
+\r
+ /* Get the TIMx SMCR register value */\r
+ tmpsmcr = TIMx->SMCR;\r
+ /* Reset the TS Bits */\r
+ tmpsmcr &= ~TIM_SMCR_TS;\r
+ /* Set the Input Trigger source and the slave mode*/\r
+ tmpsmcr |= (InputTriggerSource | TIM_SLAVEMODE_EXTERNAL1);\r
+ /* Write to TIMx SMCR */\r
+ TIMx->SMCR = tmpsmcr;\r
+}\r
+/**\r
+ * @brief Configures the TIMx External Trigger (ETR).\r
+ * @param TIMx to select the TIM peripheral\r
+ * @param TIM_ExtTRGPrescaler The external Trigger Prescaler.\r
+ * This parameter can be one of the following values:\r
+ * @arg TIM_ETRPRESCALER_DIV1: ETRP Prescaler OFF.\r
+ * @arg TIM_ETRPRESCALER_DIV2: ETRP frequency divided by 2.\r
+ * @arg TIM_ETRPRESCALER_DIV4: ETRP frequency divided by 4.\r
+ * @arg TIM_ETRPRESCALER_DIV8: ETRP frequency divided by 8.\r
+ * @param TIM_ExtTRGPolarity The external Trigger Polarity.\r
+ * This parameter can be one of the following values:\r
+ * @arg TIM_ETRPOLARITY_INVERTED: active low or falling edge active.\r
+ * @arg TIM_ETRPOLARITY_NONINVERTED: active high or rising edge active.\r
+ * @param ExtTRGFilter External Trigger Filter.\r
+ * This parameter must be a value between 0x00 and 0x0F\r
+ * @retval None\r
+ */\r
+static void TIM_ETR_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ExtTRGPrescaler,\r
+ uint32_t TIM_ExtTRGPolarity, uint32_t ExtTRGFilter)\r
+{\r
+ uint32_t tmpsmcr;\r
+\r
+ tmpsmcr = TIMx->SMCR;\r
+\r
+ /* Reset the ETR Bits */\r
+ tmpsmcr &= ~(TIM_SMCR_ETF | TIM_SMCR_ETPS | TIM_SMCR_ECE | TIM_SMCR_ETP);\r
+\r
+ /* Set the Prescaler, the Filter value and the Polarity */\r
+ tmpsmcr |= (uint32_t)(TIM_ExtTRGPrescaler | (TIM_ExtTRGPolarity | (ExtTRGFilter << 8U)));\r
+\r
+ /* Write to TIMx SMCR */\r
+ TIMx->SMCR = tmpsmcr;\r
+}\r
+\r
+/**\r
+ * @brief Enables or disables the TIM Capture Compare Channel x.\r
+ * @param TIMx to select the TIM peripheral\r
+ * @param Channel specifies the TIM Channel\r
+ * This parameter can be one of the following values:\r
+ * @arg TIM_CHANNEL_1: TIM Channel 1\r
+ * @arg TIM_CHANNEL_2: TIM Channel 2\r
+ * @arg TIM_CHANNEL_3: TIM Channel 3\r
+ * @arg TIM_CHANNEL_4: TIM Channel 4\r
+ * @param ChannelState specifies the TIM Channel CCxE bit new state.\r
+ * This parameter can be: TIM_CCx_ENABLE or TIM_CCx_DISABLE.\r
+ * @retval None\r
+ */\r
+static void TIM_CCxChannelCmd(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t ChannelState)\r
+{\r
+ uint32_t tmp;\r
+\r
+ /* Check the parameters */\r
+ assert_param(IS_TIM_CC1_INSTANCE(TIMx));\r
+ assert_param(IS_TIM_CHANNELS(Channel));\r
+\r
+ tmp = TIM_CCER_CC1E << (Channel & 0x1FU); /* 0x1FU = 31 bits max shift */\r
+\r
+ /* Reset the CCxE Bit */\r
+ TIMx->CCER &= ~tmp;\r
+\r
+ /* Set or reset the CCxE Bit */\r
+ TIMx->CCER |= (uint32_t)(ChannelState << (Channel & 0x1FU)); /* 0x1FU = 31 bits max shift */\r
+}\r
+\r
+#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)\r
+/**\r
+ * @brief Reset interrupt callbacks to the legacy weak callbacks.\r
+ * @param htim pointer to a TIM_HandleTypeDef structure that contains\r
+ * the configuration information for TIM module.\r
+ * @retval None\r
+ */\r
+void TIM_ResetCallback(TIM_HandleTypeDef *htim)\r
+{\r
+ /* Reset the TIM callback to the legacy weak callbacks */\r
+ htim->PeriodElapsedCallback = HAL_TIM_PeriodElapsedCallback; /* Legacy weak PeriodElapsedCallback */\r
+ htim->PeriodElapsedHalfCpltCallback = HAL_TIM_PeriodElapsedHalfCpltCallback; /* Legacy weak PeriodElapsedHalfCpltCallback */\r
+ htim->TriggerCallback = HAL_TIM_TriggerCallback; /* Legacy weak TriggerCallback */\r
+ htim->TriggerHalfCpltCallback = HAL_TIM_TriggerHalfCpltCallback; /* Legacy weak TriggerHalfCpltCallback */\r
+ htim->IC_CaptureCallback = HAL_TIM_IC_CaptureCallback; /* Legacy weak IC_CaptureCallback */\r
+ htim->IC_CaptureHalfCpltCallback = HAL_TIM_IC_CaptureHalfCpltCallback; /* Legacy weak IC_CaptureHalfCpltCallback */\r
+ htim->OC_DelayElapsedCallback = HAL_TIM_OC_DelayElapsedCallback; /* Legacy weak OC_DelayElapsedCallback */\r
+ htim->PWM_PulseFinishedCallback = HAL_TIM_PWM_PulseFinishedCallback; /* Legacy weak PWM_PulseFinishedCallback */\r
+ htim->PWM_PulseFinishedHalfCpltCallback = HAL_TIM_PWM_PulseFinishedHalfCpltCallback; /* Legacy weak PWM_PulseFinishedHalfCpltCallback */\r
+ htim->ErrorCallback = HAL_TIM_ErrorCallback; /* Legacy weak ErrorCallback */\r
+}\r
+#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+#endif /* HAL_TIM_MODULE_ENABLED */\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\r
--- /dev/null
+/**\r
+ ******************************************************************************\r
+ * @file stm32l1xx_hal_tim_ex.c\r
+ * @author MCD Application Team\r
+ * @brief TIM HAL module driver.\r
+ * This file provides firmware functions to manage the following\r
+ * functionalities of the Timer Extended peripheral:\r
+ * + Time Master and Slave synchronization configuration\r
+ * + Time OCRef clear configuration\r
+ * + Timer remapping capabilities configuration\r
+ @verbatim\r
+ ==============================================================================\r
+ ##### TIMER Extended features #####\r
+ ==============================================================================\r
+ [..]\r
+ The Timer Extended features include:\r
+ (#) Synchronization circuit to control the timer with external signals and to\r
+ interconnect several timers together.\r
+\r
+ @endverbatim\r
+ ******************************************************************************\r
+ * @attention\r
+ *\r
+ * <h2><center>© Copyright (c) 2016 STMicroelectronics.\r
+ * All rights reserved.</center></h2>\r
+ *\r
+ * This software component is licensed by ST under BSD 3-Clause license,\r
+ * the "License"; You may not use this file except in compliance with the\r
+ * License. You may obtain a copy of the License at:\r
+ * opensource.org/licenses/BSD-3-Clause\r
+ *\r
+ ******************************************************************************\r
+*/\r
+\r
+/* Includes ------------------------------------------------------------------*/\r
+#include "stm32l1xx_hal.h"\r
+\r
+/** @addtogroup STM32L1xx_HAL_Driver\r
+ * @{\r
+ */\r
+\r
+/** @defgroup TIMEx TIMEx\r
+ * @brief TIM Extended HAL module driver\r
+ * @{\r
+ */\r
+\r
+#ifdef HAL_TIM_MODULE_ENABLED\r
+\r
+/* Private typedef -----------------------------------------------------------*/\r
+/* Private define ------------------------------------------------------------*/\r
+/* Private macro -------------------------------------------------------------*/\r
+/* Private variables ---------------------------------------------------------*/\r
+/* Private function prototypes -----------------------------------------------*/\r
+\r
+/* Exported functions --------------------------------------------------------*/\r
+/** @defgroup TIMEx_Exported_Functions TIM Extended Exported Functions\r
+ * @{\r
+ */\r
+/** @defgroup TIMEx_Exported_Functions_Group5 Extended Peripheral Control functions\r
+ * @brief Peripheral Control functions\r
+ *\r
+@verbatim\r
+ ==============================================================================\r
+ ##### Peripheral Control functions #####\r
+ ==============================================================================\r
+ [..]\r
+ This section provides functions allowing to:\r
+ (+) Configure Master synchronization.\r
+ (+) Configure timer remapping capabilities.\r
+\r
+@endverbatim\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @brief Configures the TIM in master mode.\r
+ * @param htim TIM handle.\r
+ * @param sMasterConfig pointer to a TIM_MasterConfigTypeDef structure that\r
+ * contains the selected trigger output (TRGO) and the Master/Slave\r
+ * mode.\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_TIMEx_MasterConfigSynchronization(TIM_HandleTypeDef *htim,\r
+ TIM_MasterConfigTypeDef *sMasterConfig)\r
+{\r
+ uint32_t tmpcr2;\r
+ uint32_t tmpsmcr;\r
+\r
+ /* Check the parameters */\r
+ assert_param(IS_TIM_SYNCHRO_INSTANCE(htim->Instance));\r
+ assert_param(IS_TIM_TRGO_SOURCE(sMasterConfig->MasterOutputTrigger));\r
+ assert_param(IS_TIM_MSM_STATE(sMasterConfig->MasterSlaveMode));\r
+\r
+ /* Check input state */\r
+ __HAL_LOCK(htim);\r
+\r
+ /* Change the handler state */\r
+ htim->State = HAL_TIM_STATE_BUSY;\r
+\r
+ /* Get the TIMx CR2 register value */\r
+ tmpcr2 = htim->Instance->CR2;\r
+\r
+ /* Get the TIMx SMCR register value */\r
+ tmpsmcr = htim->Instance->SMCR;\r
+\r
+ /* Reset the MMS Bits */\r
+ tmpcr2 &= ~TIM_CR2_MMS;\r
+ /* Select the TRGO source */\r
+ tmpcr2 |= sMasterConfig->MasterOutputTrigger;\r
+\r
+ /* Reset the MSM Bit */\r
+ tmpsmcr &= ~TIM_SMCR_MSM;\r
+ /* Set master mode */\r
+ tmpsmcr |= sMasterConfig->MasterSlaveMode;\r
+\r
+ /* Update TIMx CR2 */\r
+ htim->Instance->CR2 = tmpcr2;\r
+\r
+ /* Update TIMx SMCR */\r
+ htim->Instance->SMCR = tmpsmcr;\r
+\r
+ /* Change the htim state */\r
+ htim->State = HAL_TIM_STATE_READY;\r
+\r
+ __HAL_UNLOCK(htim);\r
+\r
+ return HAL_OK;\r
+}\r
+\r
+/**\r
+ * @brief Configures the TIMx Remapping input capabilities.\r
+ * @param htim TIM handle.\r
+ * @param Remap specifies the TIM remapping source.\r
+ *\r
+ * For TIM2, the parameter can have the following values:(see note)\r
+ * @arg TIM_TIM2_ITR1_TIM10_OC: TIM2 ITR1 input is connected to TIM10 OC\r
+ * @arg TIM_TIM2_ITR1_TIM5_TGO: TIM2 ITR1 input is connected to TIM5 TGO\r
+ *\r
+ * For TIM3, the parameter can have the following values:(see note)\r
+ * @arg TIM_TIM3_ITR2_TIM11_OC: TIM3 ITR2 input is connected to TIM11 OC\r
+ * @arg TIM_TIM3_ITR2_TIM5_TGO: TIM3 ITR2 input is connected to TIM5 TGO\r
+ *\r
+ * For TIM9, the parameter is a combination of 2 fields (field1 | field2):\r
+ *\r
+ * field1 can have the following values:(see note)\r
+ * @arg TIM_TIM9_ITR1_TIM3_TGO: TIM9 ITR1 input is connected to TIM3 TGO\r
+ * @arg TIM_TIM9_ITR1_TS: TIM9 ITR1 input is connected to touch sensing I/O\r
+ *\r
+ * field2 can have the following values:\r
+ * @arg TIM_TIM9_GPIO: TIM9 Channel1 is connected to GPIO\r
+ * @arg TIM_TIM9_LSE: TIM9 Channel1 is connected to LSE internal clock\r
+ * @arg TIM_TIM9_GPIO1: TIM9 Channel1 is connected to GPIO\r
+ * @arg TIM_TIM9_GPIO2: TIM9 Channel1 is connected to GPIO\r
+ *\r
+ * For TIM10, the parameter is a combination of 3 fields (field1 | field2 | field3):\r
+ *\r
+ * field1 can have the following values:(see note)\r
+ * @arg TIM_TIM10_TI1RMP: TIM10 Channel 1 depends on TI1_RMP\r
+ * @arg TIM_TIM10_RI: TIM10 Channel 1 is connected to RI\r
+ *\r
+ * field2 can have the following values:(see note)\r
+ * @arg TIM_TIM10_ETR_LSE: TIM10 ETR input is connected to LSE clock\r
+ * @arg TIM_TIM10_ETR_TIM9_TGO: TIM10 ETR input is connected to TIM9 TGO\r
+ *\r
+ * field3 can have the following values:\r
+ * @arg TIM_TIM10_GPIO: TIM10 Channel1 is connected to GPIO\r
+ * @arg TIM_TIM10_LSI: TIM10 Channel1 is connected to LSI internal clock\r
+ * @arg TIM_TIM10_LSE: TIM10 Channel1 is connected to LSE internal clock\r
+ * @arg TIM_TIM10_RTC: TIM10 Channel1 is connected to RTC wakeup interrupt\r
+ *\r
+ * For TIM11, the parameter is a combination of 3 fields (field1 | field2 | field3):\r
+ *\r
+ * field1 can have the following values:(see note)\r
+ * @arg TIM_TIM11_TI1RMP: TIM11 Channel 1 depends on TI1_RMP\r
+ * @arg TIM_TIM11_RI: TIM11 Channel 1 is connected to RI\r
+ *\r
+ * field2 can have the following values:(see note)\r
+ * @arg TIM_TIM11_ETR_LSE: TIM11 ETR input is connected to LSE clock\r
+ * @arg TIM_TIM11_ETR_TIM9_TGO: TIM11 ETR input is connected to TIM9 TGO\r
+ *\r
+ * field3 can have the following values:\r
+ * @arg TIM_TIM11_GPIO: TIM11 Channel1 is connected to GPIO\r
+ * @arg TIM_TIM11_MSI: TIM11 Channel1 is connected to MSI internal clock\r
+ * @arg TIM_TIM11_HSE_RTC: TIM11 Channel1 is connected to HSE_RTC clock\r
+ * @arg TIM_TIM11_GPIO1: TIM11 Channel1 is connected to GPIO\r
+ *\r
+ * @note Available only in Cat.3, Cat.4,Cat.5 and Cat.6 devices.\r
+ *\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_TIMEx_RemapConfig(TIM_HandleTypeDef *htim, uint32_t Remap)\r
+{\r
+ __HAL_LOCK(htim);\r
+\r
+ /* Check parameters */\r
+ assert_param(IS_TIM_REMAP(htim->Instance, Remap));\r
+\r
+ /* Set the Timer remapping configuration */\r
+ WRITE_REG(htim->Instance->OR, Remap);\r
+\r
+ __HAL_UNLOCK(htim);\r
+\r
+ return HAL_OK;\r
+}\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+\r
+#endif /* HAL_TIM_MODULE_ENABLED */\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\r
--- /dev/null
+/**\r
+ ******************************************************************************\r
+ * @file stm32l1xx_hal_uart.c\r
+ * @author MCD Application Team\r
+ * @brief UART HAL module driver.\r
+ * This file provides firmware functions to manage the following\r
+ * functionalities of the Universal Asynchronous Receiver Transmitter Peripheral (UART).\r
+ * + Initialization and de-initialization functions\r
+ * + IO operation functions\r
+ * + Peripheral Control functions\r
+ * + Peripheral State and Errors functions\r
+ @verbatim\r
+ ==============================================================================\r
+ ##### How to use this driver #####\r
+ ==============================================================================\r
+ [..]\r
+ The UART HAL driver can be used as follows:\r
+\r
+ (#) Declare a UART_HandleTypeDef handle structure (eg. UART_HandleTypeDef huart).\r
+ (#) Initialize the UART low level resources by implementing the HAL_UART_MspInit() API:\r
+ (##) Enable the USARTx interface clock.\r
+ (##) UART pins configuration:\r
+ (+++) Enable the clock for the UART GPIOs.\r
+ (+++) Configure these UART pins (TX as alternate function pull-up, RX as alternate function Input).\r
+ (##) NVIC configuration if you need to use interrupt process (HAL_UART_Transmit_IT()\r
+ and HAL_UART_Receive_IT() APIs):\r
+ (+++) Configure the USARTx interrupt priority.\r
+ (+++) Enable the NVIC USART IRQ handle.\r
+ (##) DMA Configuration if you need to use DMA process (HAL_UART_Transmit_DMA()\r
+ and HAL_UART_Receive_DMA() APIs):\r
+ (+++) Declare a DMA handle structure for the Tx/Rx channel.\r
+ (+++) Enable the DMAx interface clock.\r
+ (+++) Configure the declared DMA handle structure with the required\r
+ Tx/Rx parameters.\r
+ (+++) Configure the DMA Tx/Rx channel.\r
+ (+++) Associate the initialized DMA handle to the UART DMA Tx/Rx handle.\r
+ (+++) Configure the priority and enable the NVIC for the transfer complete\r
+ interrupt on the DMA Tx/Rx channel.\r
+ (+++) Configure the USARTx interrupt priority and enable the NVIC USART IRQ handle\r
+ (used for last byte sending completion detection in DMA non circular mode)\r
+\r
+ (#) Program the Baud Rate, Word Length, Stop Bit, Parity, Hardware\r
+ flow control and Mode(Receiver/Transmitter) in the huart Init structure.\r
+\r
+ (#) For the UART asynchronous mode, initialize the UART registers by calling\r
+ the HAL_UART_Init() API.\r
+\r
+ (#) For the UART Half duplex mode, initialize the UART registers by calling\r
+ the HAL_HalfDuplex_Init() API.\r
+\r
+ (#) For the LIN mode, initialize the UART registers by calling the HAL_LIN_Init() API.\r
+\r
+ (#) For the Multi-Processor mode, initialize the UART registers by calling\r
+ the HAL_MultiProcessor_Init() API.\r
+\r
+ [..]\r
+ (@) The specific UART interrupts (Transmission complete interrupt,\r
+ RXNE interrupt and Error Interrupts) will be managed using the macros\r
+ __HAL_UART_ENABLE_IT() and __HAL_UART_DISABLE_IT() inside the transmit\r
+ and receive process.\r
+\r
+ [..]\r
+ (@) These APIs (HAL_UART_Init() and HAL_HalfDuplex_Init()) configure also the\r
+ low level Hardware GPIO, CLOCK, CORTEX...etc) by calling the customized\r
+ HAL_UART_MspInit() API.\r
+\r
+ ##### Callback registration #####\r
+ ==================================\r
+\r
+ [..]\r
+ The compilation define USE_HAL_UART_REGISTER_CALLBACKS when set to 1\r
+ allows the user to configure dynamically the driver callbacks.\r
+\r
+ [..]\r
+ Use Function @ref HAL_UART_RegisterCallback() to register a user callback.\r
+ Function @ref HAL_UART_RegisterCallback() allows to register following callbacks:\r
+ (+) TxHalfCpltCallback : Tx Half Complete Callback.\r
+ (+) TxCpltCallback : Tx Complete Callback.\r
+ (+) RxHalfCpltCallback : Rx Half Complete Callback.\r
+ (+) RxCpltCallback : Rx Complete Callback.\r
+ (+) ErrorCallback : Error Callback.\r
+ (+) AbortCpltCallback : Abort Complete Callback.\r
+ (+) AbortTransmitCpltCallback : Abort Transmit Complete Callback.\r
+ (+) AbortReceiveCpltCallback : Abort Receive Complete Callback.\r
+ (+) MspInitCallback : UART MspInit.\r
+ (+) MspDeInitCallback : UART MspDeInit.\r
+ This function takes as parameters the HAL peripheral handle, the Callback ID\r
+ and a pointer to the user callback function.\r
+\r
+ [..]\r
+ Use function @ref HAL_UART_UnRegisterCallback() to reset a callback to the default\r
+ weak (surcharged) function.\r
+ @ref HAL_UART_UnRegisterCallback() takes as parameters the HAL peripheral handle,\r
+ and the Callback ID.\r
+ This function allows to reset following callbacks:\r
+ (+) TxHalfCpltCallback : Tx Half Complete Callback.\r
+ (+) TxCpltCallback : Tx Complete Callback.\r
+ (+) RxHalfCpltCallback : Rx Half Complete Callback.\r
+ (+) RxCpltCallback : Rx Complete Callback.\r
+ (+) ErrorCallback : Error Callback.\r
+ (+) AbortCpltCallback : Abort Complete Callback.\r
+ (+) AbortTransmitCpltCallback : Abort Transmit Complete Callback.\r
+ (+) AbortReceiveCpltCallback : Abort Receive Complete Callback.\r
+ (+) MspInitCallback : UART MspInit.\r
+ (+) MspDeInitCallback : UART MspDeInit.\r
+\r
+ [..]\r
+ By default, after the @ref HAL_UART_Init() and when the state is HAL_UART_STATE_RESET\r
+ all callbacks are set to the corresponding weak (surcharged) functions:\r
+ examples @ref HAL_UART_TxCpltCallback(), @ref HAL_UART_RxHalfCpltCallback().\r
+ Exception done for MspInit and MspDeInit functions that are respectively\r
+ reset to the legacy weak (surcharged) functions in the @ref HAL_UART_Init()\r
+ and @ref HAL_UART_DeInit() only when these callbacks are null (not registered beforehand).\r
+ If not, MspInit or MspDeInit are not null, the @ref HAL_UART_Init() and @ref HAL_UART_DeInit()\r
+ keep and use the user MspInit/MspDeInit callbacks (registered beforehand).\r
+\r
+ [..]\r
+ Callbacks can be registered/unregistered in HAL_UART_STATE_READY state only.\r
+ Exception done MspInit/MspDeInit that can be registered/unregistered\r
+ in HAL_UART_STATE_READY or HAL_UART_STATE_RESET state, thus registered (user)\r
+ MspInit/DeInit callbacks can be used during the Init/DeInit.\r
+ In that case first register the MspInit/MspDeInit user callbacks\r
+ using @ref HAL_UART_RegisterCallback() before calling @ref HAL_UART_DeInit()\r
+ or @ref HAL_UART_Init() function.\r
+\r
+ [..]\r
+ When The compilation define USE_HAL_UART_REGISTER_CALLBACKS is set to 0 or\r
+ not defined, the callback registration feature is not available\r
+ and weak (surcharged) callbacks are used.\r
+\r
+ [..]\r
+ Three operation modes are available within this driver :\r
+\r
+ *** Polling mode IO operation ***\r
+ =================================\r
+ [..]\r
+ (+) Send an amount of data in blocking mode using HAL_UART_Transmit()\r
+ (+) Receive an amount of data in blocking mode using HAL_UART_Receive()\r
+\r
+ *** Interrupt mode IO operation ***\r
+ ===================================\r
+ [..]\r
+ (+) Send an amount of data in non blocking mode using HAL_UART_Transmit_IT()\r
+ (+) At transmission end of transfer HAL_UART_TxCpltCallback is executed and user can\r
+ add his own code by customization of function pointer HAL_UART_TxCpltCallback\r
+ (+) Receive an amount of data in non blocking mode using HAL_UART_Receive_IT()\r
+ (+) At reception end of transfer HAL_UART_RxCpltCallback is executed and user can\r
+ add his own code by customization of function pointer HAL_UART_RxCpltCallback\r
+ (+) In case of transfer Error, HAL_UART_ErrorCallback() function is executed and user can\r
+ add his own code by customization of function pointer HAL_UART_ErrorCallback\r
+\r
+ *** DMA mode IO operation ***\r
+ ==============================\r
+ [..]\r
+ (+) Send an amount of data in non blocking mode (DMA) using HAL_UART_Transmit_DMA()\r
+ (+) At transmission end of half transfer HAL_UART_TxHalfCpltCallback is executed and user can\r
+ add his own code by customization of function pointer HAL_UART_TxHalfCpltCallback\r
+ (+) At transmission end of transfer HAL_UART_TxCpltCallback is executed and user can\r
+ add his own code by customization of function pointer HAL_UART_TxCpltCallback\r
+ (+) Receive an amount of data in non blocking mode (DMA) using HAL_UART_Receive_DMA()\r
+ (+) At reception end of half transfer HAL_UART_RxHalfCpltCallback is executed and user can\r
+ add his own code by customization of function pointer HAL_UART_RxHalfCpltCallback\r
+ (+) At reception end of transfer HAL_UART_RxCpltCallback is executed and user can\r
+ add his own code by customization of function pointer HAL_UART_RxCpltCallback\r
+ (+) In case of transfer Error, HAL_UART_ErrorCallback() function is executed and user can\r
+ add his own code by customization of function pointer HAL_UART_ErrorCallback\r
+ (+) Pause the DMA Transfer using HAL_UART_DMAPause()\r
+ (+) Resume the DMA Transfer using HAL_UART_DMAResume()\r
+ (+) Stop the DMA Transfer using HAL_UART_DMAStop()\r
+\r
+ *** UART HAL driver macros list ***\r
+ =============================================\r
+ [..]\r
+ Below the list of most used macros in UART HAL driver.\r
+\r
+ (+) __HAL_UART_ENABLE: Enable the UART peripheral\r
+ (+) __HAL_UART_DISABLE: Disable the UART peripheral\r
+ (+) __HAL_UART_GET_FLAG : Check whether the specified UART flag is set or not\r
+ (+) __HAL_UART_CLEAR_FLAG : Clear the specified UART pending flag\r
+ (+) __HAL_UART_ENABLE_IT: Enable the specified UART interrupt\r
+ (+) __HAL_UART_DISABLE_IT: Disable the specified UART interrupt\r
+ (+) __HAL_UART_GET_IT_SOURCE: Check whether the specified UART interrupt has occurred or not\r
+\r
+ [..]\r
+ (@) You can refer to the UART HAL driver header file for more useful macros\r
+\r
+ @endverbatim\r
+ [..]\r
+ (@) Additionnal remark: If the parity is enabled, then the MSB bit of the data written\r
+ in the data register is transmitted but is changed by the parity bit.\r
+ Depending on the frame length defined by the M bit (8-bits or 9-bits),\r
+ the possible UART frame formats are as listed in the following table:\r
+ +-------------------------------------------------------------+\r
+ | M bit | PCE bit | UART frame |\r
+ |---------------------|---------------------------------------|\r
+ | 0 | 0 | | SB | 8 bit data | STB | |\r
+ |---------|-----------|---------------------------------------|\r
+ | 0 | 1 | | SB | 7 bit data | PB | STB | |\r
+ |---------|-----------|---------------------------------------|\r
+ | 1 | 0 | | SB | 9 bit data | STB | |\r
+ |---------|-----------|---------------------------------------|\r
+ | 1 | 1 | | SB | 8 bit data | PB | STB | |\r
+ +-------------------------------------------------------------+\r
+ ******************************************************************************\r
+ * @attention\r
+ *\r
+ * <h2><center>© Copyright (c) 2016 STMicroelectronics.\r
+ * All rights reserved.</center></h2>\r
+ *\r
+ * This software component is licensed by ST under BSD 3-Clause license,\r
+ * the "License"; You may not use this file except in compliance with the\r
+ * License. You may obtain a copy of the License at:\r
+ * opensource.org/licenses/BSD-3-Clause\r
+ *\r
+ ******************************************************************************\r
+ */\r
+\r
+/* Includes ------------------------------------------------------------------*/\r
+#include "stm32l1xx_hal.h"\r
+\r
+/** @addtogroup STM32L1xx_HAL_Driver\r
+ * @{\r
+ */\r
+\r
+/** @defgroup UART UART\r
+ * @brief HAL UART module driver\r
+ * @{\r
+ */\r
+#ifdef HAL_UART_MODULE_ENABLED\r
+\r
+/* Private typedef -----------------------------------------------------------*/\r
+/* Private define ------------------------------------------------------------*/\r
+/** @addtogroup UART_Private_Constants\r
+ * @{\r
+ */\r
+/**\r
+ * @}\r
+ */\r
+/* Private macro -------------------------------------------------------------*/\r
+/* Private variables ---------------------------------------------------------*/\r
+/* Private function prototypes -----------------------------------------------*/\r
+/** @addtogroup UART_Private_Functions UART Private Functions\r
+ * @{\r
+ */\r
+\r
+#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)\r
+void UART_InitCallbacksToDefault(UART_HandleTypeDef *huart);\r
+#endif /* USE_HAL_UART_REGISTER_CALLBACKS */\r
+static void UART_EndTxTransfer(UART_HandleTypeDef *huart);\r
+static void UART_EndRxTransfer(UART_HandleTypeDef *huart);\r
+static void UART_DMATransmitCplt(DMA_HandleTypeDef *hdma);\r
+static void UART_DMAReceiveCplt(DMA_HandleTypeDef *hdma);\r
+static void UART_DMATxHalfCplt(DMA_HandleTypeDef *hdma);\r
+static void UART_DMARxHalfCplt(DMA_HandleTypeDef *hdma);\r
+static void UART_DMAError(DMA_HandleTypeDef *hdma);\r
+static void UART_DMAAbortOnError(DMA_HandleTypeDef *hdma);\r
+static void UART_DMATxAbortCallback(DMA_HandleTypeDef *hdma);\r
+static void UART_DMARxAbortCallback(DMA_HandleTypeDef *hdma);\r
+static void UART_DMATxOnlyAbortCallback(DMA_HandleTypeDef *hdma);\r
+static void UART_DMARxOnlyAbortCallback(DMA_HandleTypeDef *hdma);\r
+static HAL_StatusTypeDef UART_Transmit_IT(UART_HandleTypeDef *huart);\r
+static HAL_StatusTypeDef UART_EndTransmit_IT(UART_HandleTypeDef *huart);\r
+static HAL_StatusTypeDef UART_Receive_IT(UART_HandleTypeDef *huart);\r
+static HAL_StatusTypeDef UART_WaitOnFlagUntilTimeout(UART_HandleTypeDef *huart, uint32_t Flag, FlagStatus Status, uint32_t Tickstart, uint32_t Timeout);\r
+static void UART_SetConfig(UART_HandleTypeDef *huart);\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/* Exported functions ---------------------------------------------------------*/\r
+/** @defgroup UART_Exported_Functions UART Exported Functions\r
+ * @{\r
+ */\r
+\r
+/** @defgroup UART_Exported_Functions_Group1 Initialization and de-initialization functions\r
+ * @brief Initialization and Configuration functions\r
+ *\r
+@verbatim\r
+ ===============================================================================\r
+ ##### Initialization and Configuration functions #####\r
+ ===============================================================================\r
+ [..]\r
+ This subsection provides a set of functions allowing to initialize the USARTx or the UARTy\r
+ in asynchronous mode.\r
+ (+) For the asynchronous mode only these parameters can be configured:\r
+ (++) Baud Rate\r
+ (++) Word Length\r
+ (++) Stop Bit\r
+ (++) Parity: If the parity is enabled, then the MSB bit of the data written\r
+ in the data register is transmitted but is changed by the parity bit.\r
+ Depending on the frame length defined by the M bit (8-bits or 9-bits),\r
+ please refer to Reference manual for possible UART frame formats.\r
+ (++) Hardware flow control\r
+ (++) Receiver/transmitter modes\r
+ (++) Over Sampling Method\r
+ [..]\r
+ The HAL_UART_Init(), HAL_HalfDuplex_Init(), HAL_LIN_Init() and HAL_MultiProcessor_Init() APIs\r
+ follow respectively the UART asynchronous, UART Half duplex, LIN and Multi-Processor configuration\r
+ procedures (details for the procedures are available in reference manual (RM0038)).\r
+\r
+@endverbatim\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @brief Initializes the UART mode according to the specified parameters in\r
+ * the UART_InitTypeDef and create the associated handle.\r
+ * @param huart Pointer to a UART_HandleTypeDef structure that contains\r
+ * the configuration information for the specified UART module.\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_UART_Init(UART_HandleTypeDef *huart)\r
+{\r
+ /* Check the UART handle allocation */\r
+ if (huart == NULL)\r
+ {\r
+ return HAL_ERROR;\r
+ }\r
+\r
+ /* Check the parameters */\r
+ if (huart->Init.HwFlowCtl != UART_HWCONTROL_NONE)\r
+ {\r
+ /* The hardware flow control is available only for USART1, USART2 and USART3 */\r
+ assert_param(IS_UART_HWFLOW_INSTANCE(huart->Instance));\r
+ assert_param(IS_UART_HARDWARE_FLOW_CONTROL(huart->Init.HwFlowCtl));\r
+ }\r
+ else\r
+ {\r
+ assert_param(IS_UART_INSTANCE(huart->Instance));\r
+ }\r
+ assert_param(IS_UART_WORD_LENGTH(huart->Init.WordLength));\r
+ assert_param(IS_UART_OVERSAMPLING(huart->Init.OverSampling));\r
+\r
+ if (huart->gState == HAL_UART_STATE_RESET)\r
+ {\r
+ /* Allocate lock resource and initialize it */\r
+ huart->Lock = HAL_UNLOCKED;\r
+\r
+#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)\r
+ UART_InitCallbacksToDefault(huart);\r
+\r
+ if (huart->MspInitCallback == NULL)\r
+ {\r
+ huart->MspInitCallback = HAL_UART_MspInit;\r
+ }\r
+\r
+ /* Init the low level hardware */\r
+ huart->MspInitCallback(huart);\r
+#else\r
+ /* Init the low level hardware : GPIO, CLOCK */\r
+ HAL_UART_MspInit(huart);\r
+#endif /* (USE_HAL_UART_REGISTER_CALLBACKS) */\r
+ }\r
+\r
+ huart->gState = HAL_UART_STATE_BUSY;\r
+\r
+ /* Disable the peripheral */\r
+ __HAL_UART_DISABLE(huart);\r
+\r
+ /* Set the UART Communication parameters */\r
+ UART_SetConfig(huart);\r
+\r
+ /* In asynchronous mode, the following bits must be kept cleared:\r
+ - LINEN and CLKEN bits in the USART_CR2 register,\r
+ - SCEN, HDSEL and IREN bits in the USART_CR3 register.*/\r
+ CLEAR_BIT(huart->Instance->CR2, (USART_CR2_LINEN | USART_CR2_CLKEN));\r
+ CLEAR_BIT(huart->Instance->CR3, (USART_CR3_SCEN | USART_CR3_HDSEL | USART_CR3_IREN));\r
+\r
+ /* Enable the peripheral */\r
+ __HAL_UART_ENABLE(huart);\r
+\r
+ /* Initialize the UART state */\r
+ huart->ErrorCode = HAL_UART_ERROR_NONE;\r
+ huart->gState = HAL_UART_STATE_READY;\r
+ huart->RxState = HAL_UART_STATE_READY;\r
+\r
+ return HAL_OK;\r
+}\r
+\r
+/**\r
+ * @brief Initializes the half-duplex mode according to the specified\r
+ * parameters in the UART_InitTypeDef and create the associated handle.\r
+ * @param huart Pointer to a UART_HandleTypeDef structure that contains\r
+ * the configuration information for the specified UART module.\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_HalfDuplex_Init(UART_HandleTypeDef *huart)\r
+{\r
+ /* Check the UART handle allocation */\r
+ if (huart == NULL)\r
+ {\r
+ return HAL_ERROR;\r
+ }\r
+\r
+ /* Check the parameters */\r
+ assert_param(IS_UART_HALFDUPLEX_INSTANCE(huart->Instance));\r
+ assert_param(IS_UART_WORD_LENGTH(huart->Init.WordLength));\r
+ assert_param(IS_UART_OVERSAMPLING(huart->Init.OverSampling));\r
+\r
+ if (huart->gState == HAL_UART_STATE_RESET)\r
+ {\r
+ /* Allocate lock resource and initialize it */\r
+ huart->Lock = HAL_UNLOCKED;\r
+\r
+#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)\r
+ UART_InitCallbacksToDefault(huart);\r
+\r
+ if (huart->MspInitCallback == NULL)\r
+ {\r
+ huart->MspInitCallback = HAL_UART_MspInit;\r
+ }\r
+\r
+ /* Init the low level hardware */\r
+ huart->MspInitCallback(huart);\r
+#else\r
+ /* Init the low level hardware : GPIO, CLOCK */\r
+ HAL_UART_MspInit(huart);\r
+#endif /* (USE_HAL_UART_REGISTER_CALLBACKS) */\r
+ }\r
+\r
+ huart->gState = HAL_UART_STATE_BUSY;\r
+\r
+ /* Disable the peripheral */\r
+ __HAL_UART_DISABLE(huart);\r
+\r
+ /* Set the UART Communication parameters */\r
+ UART_SetConfig(huart);\r
+\r
+ /* In half-duplex mode, the following bits must be kept cleared:\r
+ - LINEN and CLKEN bits in the USART_CR2 register,\r
+ - SCEN and IREN bits in the USART_CR3 register.*/\r
+ CLEAR_BIT(huart->Instance->CR2, (USART_CR2_LINEN | USART_CR2_CLKEN));\r
+ CLEAR_BIT(huart->Instance->CR3, (USART_CR3_IREN | USART_CR3_SCEN));\r
+\r
+ /* Enable the Half-Duplex mode by setting the HDSEL bit in the CR3 register */\r
+ SET_BIT(huart->Instance->CR3, USART_CR3_HDSEL);\r
+\r
+ /* Enable the peripheral */\r
+ __HAL_UART_ENABLE(huart);\r
+\r
+ /* Initialize the UART state*/\r
+ huart->ErrorCode = HAL_UART_ERROR_NONE;\r
+ huart->gState = HAL_UART_STATE_READY;\r
+ huart->RxState = HAL_UART_STATE_READY;\r
+\r
+ return HAL_OK;\r
+}\r
+\r
+/**\r
+ * @brief Initializes the LIN mode according to the specified\r
+ * parameters in the UART_InitTypeDef and create the associated handle.\r
+ * @param huart Pointer to a UART_HandleTypeDef structure that contains\r
+ * the configuration information for the specified UART module.\r
+ * @param BreakDetectLength Specifies the LIN break detection length.\r
+ * This parameter can be one of the following values:\r
+ * @arg UART_LINBREAKDETECTLENGTH_10B: 10-bit break detection\r
+ * @arg UART_LINBREAKDETECTLENGTH_11B: 11-bit break detection\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_LIN_Init(UART_HandleTypeDef *huart, uint32_t BreakDetectLength)\r
+{\r
+ /* Check the UART handle allocation */\r
+ if (huart == NULL)\r
+ {\r
+ return HAL_ERROR;\r
+ }\r
+\r
+ /* Check the LIN UART instance */\r
+ assert_param(IS_UART_LIN_INSTANCE(huart->Instance));\r
+\r
+ /* Check the Break detection length parameter */\r
+ assert_param(IS_UART_LIN_BREAK_DETECT_LENGTH(BreakDetectLength));\r
+ assert_param(IS_UART_LIN_WORD_LENGTH(huart->Init.WordLength));\r
+ assert_param(IS_UART_LIN_OVERSAMPLING(huart->Init.OverSampling));\r
+\r
+ if (huart->gState == HAL_UART_STATE_RESET)\r
+ {\r
+ /* Allocate lock resource and initialize it */\r
+ huart->Lock = HAL_UNLOCKED;\r
+\r
+#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)\r
+ UART_InitCallbacksToDefault(huart);\r
+\r
+ if (huart->MspInitCallback == NULL)\r
+ {\r
+ huart->MspInitCallback = HAL_UART_MspInit;\r
+ }\r
+\r
+ /* Init the low level hardware */\r
+ huart->MspInitCallback(huart);\r
+#else\r
+ /* Init the low level hardware : GPIO, CLOCK */\r
+ HAL_UART_MspInit(huart);\r
+#endif /* (USE_HAL_UART_REGISTER_CALLBACKS) */\r
+ }\r
+\r
+ huart->gState = HAL_UART_STATE_BUSY;\r
+\r
+ /* Disable the peripheral */\r
+ __HAL_UART_DISABLE(huart);\r
+\r
+ /* Set the UART Communication parameters */\r
+ UART_SetConfig(huart);\r
+\r
+ /* In LIN mode, the following bits must be kept cleared:\r
+ - CLKEN bits in the USART_CR2 register,\r
+ - SCEN, HDSEL and IREN bits in the USART_CR3 register.*/\r
+ CLEAR_BIT(huart->Instance->CR2, (USART_CR2_CLKEN));\r
+ CLEAR_BIT(huart->Instance->CR3, (USART_CR3_HDSEL | USART_CR3_IREN | USART_CR3_SCEN));\r
+\r
+ /* Enable the LIN mode by setting the LINEN bit in the CR2 register */\r
+ SET_BIT(huart->Instance->CR2, USART_CR2_LINEN);\r
+\r
+ /* Set the USART LIN Break detection length. */\r
+ CLEAR_BIT(huart->Instance->CR2, USART_CR2_LBDL);\r
+ SET_BIT(huart->Instance->CR2, BreakDetectLength);\r
+\r
+ /* Enable the peripheral */\r
+ __HAL_UART_ENABLE(huart);\r
+\r
+ /* Initialize the UART state*/\r
+ huart->ErrorCode = HAL_UART_ERROR_NONE;\r
+ huart->gState = HAL_UART_STATE_READY;\r
+ huart->RxState = HAL_UART_STATE_READY;\r
+\r
+ return HAL_OK;\r
+}\r
+\r
+/**\r
+ * @brief Initializes the Multi-Processor mode according to the specified\r
+ * parameters in the UART_InitTypeDef and create the associated handle.\r
+ * @param huart Pointer to a UART_HandleTypeDef structure that contains\r
+ * the configuration information for the specified UART module.\r
+ * @param Address USART address\r
+ * @param WakeUpMethod specifies the USART wake-up method.\r
+ * This parameter can be one of the following values:\r
+ * @arg UART_WAKEUPMETHOD_IDLELINE: Wake-up by an idle line detection\r
+ * @arg UART_WAKEUPMETHOD_ADDRESSMARK: Wake-up by an address mark\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_MultiProcessor_Init(UART_HandleTypeDef *huart, uint8_t Address, uint32_t WakeUpMethod)\r
+{\r
+ /* Check the UART handle allocation */\r
+ if (huart == NULL)\r
+ {\r
+ return HAL_ERROR;\r
+ }\r
+\r
+ /* Check the parameters */\r
+ assert_param(IS_UART_MULTIPROCESSOR_INSTANCE(huart->Instance));\r
+\r
+ /* Check the Address & wake up method parameters */\r
+ assert_param(IS_UART_WAKEUPMETHOD(WakeUpMethod));\r
+ assert_param(IS_UART_ADDRESS(Address));\r
+ assert_param(IS_UART_WORD_LENGTH(huart->Init.WordLength));\r
+ assert_param(IS_UART_OVERSAMPLING(huart->Init.OverSampling));\r
+\r
+ if (huart->gState == HAL_UART_STATE_RESET)\r
+ {\r
+ /* Allocate lock resource and initialize it */\r
+ huart->Lock = HAL_UNLOCKED;\r
+\r
+#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)\r
+ UART_InitCallbacksToDefault(huart);\r
+\r
+ if (huart->MspInitCallback == NULL)\r
+ {\r
+ huart->MspInitCallback = HAL_UART_MspInit;\r
+ }\r
+\r
+ /* Init the low level hardware */\r
+ huart->MspInitCallback(huart);\r
+#else\r
+ /* Init the low level hardware : GPIO, CLOCK */\r
+ HAL_UART_MspInit(huart);\r
+#endif /* (USE_HAL_UART_REGISTER_CALLBACKS) */\r
+ }\r
+\r
+ huart->gState = HAL_UART_STATE_BUSY;\r
+\r
+ /* Disable the peripheral */\r
+ __HAL_UART_DISABLE(huart);\r
+\r
+ /* Set the UART Communication parameters */\r
+ UART_SetConfig(huart);\r
+\r
+ /* In Multi-Processor mode, the following bits must be kept cleared:\r
+ - LINEN and CLKEN bits in the USART_CR2 register,\r
+ - SCEN, HDSEL and IREN bits in the USART_CR3 register */\r
+ CLEAR_BIT(huart->Instance->CR2, (USART_CR2_LINEN | USART_CR2_CLKEN));\r
+ CLEAR_BIT(huart->Instance->CR3, (USART_CR3_SCEN | USART_CR3_HDSEL | USART_CR3_IREN));\r
+\r
+ /* Set the USART address node */\r
+ CLEAR_BIT(huart->Instance->CR2, USART_CR2_ADD);\r
+ SET_BIT(huart->Instance->CR2, Address);\r
+\r
+ /* Set the wake up method by setting the WAKE bit in the CR1 register */\r
+ CLEAR_BIT(huart->Instance->CR1, USART_CR1_WAKE);\r
+ SET_BIT(huart->Instance->CR1, WakeUpMethod);\r
+\r
+ /* Enable the peripheral */\r
+ __HAL_UART_ENABLE(huart);\r
+\r
+ /* Initialize the UART state */\r
+ huart->ErrorCode = HAL_UART_ERROR_NONE;\r
+ huart->gState = HAL_UART_STATE_READY;\r
+ huart->RxState = HAL_UART_STATE_READY;\r
+\r
+ return HAL_OK;\r
+}\r
+\r
+/**\r
+ * @brief DeInitializes the UART peripheral.\r
+ * @param huart Pointer to a UART_HandleTypeDef structure that contains\r
+ * the configuration information for the specified UART module.\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_UART_DeInit(UART_HandleTypeDef *huart)\r
+{\r
+ /* Check the UART handle allocation */\r
+ if (huart == NULL)\r
+ {\r
+ return HAL_ERROR;\r
+ }\r
+\r
+ /* Check the parameters */\r
+ assert_param(IS_UART_INSTANCE(huart->Instance));\r
+\r
+ huart->gState = HAL_UART_STATE_BUSY;\r
+\r
+ /* Disable the Peripheral */\r
+ __HAL_UART_DISABLE(huart);\r
+\r
+#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)\r
+ if (huart->MspDeInitCallback == NULL)\r
+ {\r
+ huart->MspDeInitCallback = HAL_UART_MspDeInit;\r
+ }\r
+ /* DeInit the low level hardware */\r
+ huart->MspDeInitCallback(huart);\r
+#else\r
+ /* DeInit the low level hardware */\r
+ HAL_UART_MspDeInit(huart);\r
+#endif /* (USE_HAL_UART_REGISTER_CALLBACKS) */\r
+\r
+ huart->ErrorCode = HAL_UART_ERROR_NONE;\r
+ huart->gState = HAL_UART_STATE_RESET;\r
+ huart->RxState = HAL_UART_STATE_RESET;\r
+\r
+ /* Process Unlock */\r
+ __HAL_UNLOCK(huart);\r
+\r
+ return HAL_OK;\r
+}\r
+\r
+/**\r
+ * @brief UART MSP Init.\r
+ * @param huart Pointer to a UART_HandleTypeDef structure that contains\r
+ * the configuration information for the specified UART module.\r
+ * @retval None\r
+ */\r
+__weak void HAL_UART_MspInit(UART_HandleTypeDef *huart)\r
+{\r
+ /* Prevent unused argument(s) compilation warning */\r
+ UNUSED(huart);\r
+ /* NOTE: This function should not be modified, when the callback is needed,\r
+ the HAL_UART_MspInit could be implemented in the user file\r
+ */\r
+}\r
+\r
+/**\r
+ * @brief UART MSP DeInit.\r
+ * @param huart Pointer to a UART_HandleTypeDef structure that contains\r
+ * the configuration information for the specified UART module.\r
+ * @retval None\r
+ */\r
+__weak void HAL_UART_MspDeInit(UART_HandleTypeDef *huart)\r
+{\r
+ /* Prevent unused argument(s) compilation warning */\r
+ UNUSED(huart);\r
+ /* NOTE: This function should not be modified, when the callback is needed,\r
+ the HAL_UART_MspDeInit could be implemented in the user file\r
+ */\r
+}\r
+\r
+#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)\r
+/**\r
+ * @brief Register a User UART Callback\r
+ * To be used instead of the weak predefined callback\r
+ * @param huart uart handle\r
+ * @param CallbackID ID of the callback to be registered\r
+ * This parameter can be one of the following values:\r
+ * @arg @ref HAL_UART_TX_HALFCOMPLETE_CB_ID Tx Half Complete Callback ID\r
+ * @arg @ref HAL_UART_TX_COMPLETE_CB_ID Tx Complete Callback ID\r
+ * @arg @ref HAL_UART_RX_HALFCOMPLETE_CB_ID Rx Half Complete Callback ID\r
+ * @arg @ref HAL_UART_RX_COMPLETE_CB_ID Rx Complete Callback ID\r
+ * @arg @ref HAL_UART_ERROR_CB_ID Error Callback ID\r
+ * @arg @ref HAL_UART_ABORT_COMPLETE_CB_ID Abort Complete Callback ID\r
+ * @arg @ref HAL_UART_ABORT_TRANSMIT_COMPLETE_CB_ID Abort Transmit Complete Callback ID\r
+ * @arg @ref HAL_UART_ABORT_RECEIVE_COMPLETE_CB_ID Abort Receive Complete Callback ID\r
+ * @arg @ref HAL_UART_MSPINIT_CB_ID MspInit Callback ID\r
+ * @arg @ref HAL_UART_MSPDEINIT_CB_ID MspDeInit Callback ID\r
+ * @param pCallback pointer to the Callback function\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_UART_RegisterCallback(UART_HandleTypeDef *huart, HAL_UART_CallbackIDTypeDef CallbackID, pUART_CallbackTypeDef pCallback)\r
+{\r
+ HAL_StatusTypeDef status = HAL_OK;\r
+\r
+ if (pCallback == NULL)\r
+ {\r
+ /* Update the error code */\r
+ huart->ErrorCode |= HAL_UART_ERROR_INVALID_CALLBACK;\r
+\r
+ return HAL_ERROR;\r
+ }\r
+ /* Process locked */\r
+ __HAL_LOCK(huart);\r
+\r
+ if (huart->gState == HAL_UART_STATE_READY)\r
+ {\r
+ switch (CallbackID)\r
+ {\r
+ case HAL_UART_TX_HALFCOMPLETE_CB_ID :\r
+ huart->TxHalfCpltCallback = pCallback;\r
+ break;\r
+\r
+ case HAL_UART_TX_COMPLETE_CB_ID :\r
+ huart->TxCpltCallback = pCallback;\r
+ break;\r
+\r
+ case HAL_UART_RX_HALFCOMPLETE_CB_ID :\r
+ huart->RxHalfCpltCallback = pCallback;\r
+ break;\r
+\r
+ case HAL_UART_RX_COMPLETE_CB_ID :\r
+ huart->RxCpltCallback = pCallback;\r
+ break;\r
+\r
+ case HAL_UART_ERROR_CB_ID :\r
+ huart->ErrorCallback = pCallback;\r
+ break;\r
+\r
+ case HAL_UART_ABORT_COMPLETE_CB_ID :\r
+ huart->AbortCpltCallback = pCallback;\r
+ break;\r
+\r
+ case HAL_UART_ABORT_TRANSMIT_COMPLETE_CB_ID :\r
+ huart->AbortTransmitCpltCallback = pCallback;\r
+ break;\r
+\r
+ case HAL_UART_ABORT_RECEIVE_COMPLETE_CB_ID :\r
+ huart->AbortReceiveCpltCallback = pCallback;\r
+ break;\r
+\r
+ case HAL_UART_MSPINIT_CB_ID :\r
+ huart->MspInitCallback = pCallback;\r
+ break;\r
+\r
+ case HAL_UART_MSPDEINIT_CB_ID :\r
+ huart->MspDeInitCallback = pCallback;\r
+ break;\r
+\r
+ default :\r
+ /* Update the error code */\r
+ huart->ErrorCode |= HAL_UART_ERROR_INVALID_CALLBACK;\r
+\r
+ /* Return error status */\r
+ status = HAL_ERROR;\r
+ break;\r
+ }\r
+ }\r
+ else if (huart->gState == HAL_UART_STATE_RESET)\r
+ {\r
+ switch (CallbackID)\r
+ {\r
+ case HAL_UART_MSPINIT_CB_ID :\r
+ huart->MspInitCallback = pCallback;\r
+ break;\r
+\r
+ case HAL_UART_MSPDEINIT_CB_ID :\r
+ huart->MspDeInitCallback = pCallback;\r
+ break;\r
+\r
+ default :\r
+ /* Update the error code */\r
+ huart->ErrorCode |= HAL_UART_ERROR_INVALID_CALLBACK;\r
+\r
+ /* Return error status */\r
+ status = HAL_ERROR;\r
+ break;\r
+ }\r
+ }\r
+ else\r
+ {\r
+ /* Update the error code */\r
+ huart->ErrorCode |= HAL_UART_ERROR_INVALID_CALLBACK;\r
+\r
+ /* Return error status */\r
+ status = HAL_ERROR;\r
+ }\r
+\r
+ /* Release Lock */\r
+ __HAL_UNLOCK(huart);\r
+\r
+ return status;\r
+}\r
+\r
+/**\r
+ * @brief Unregister an UART Callback\r
+ * UART callaback is redirected to the weak predefined callback\r
+ * @param huart uart handle\r
+ * @param CallbackID ID of the callback to be unregistered\r
+ * This parameter can be one of the following values:\r
+ * @arg @ref HAL_UART_TX_HALFCOMPLETE_CB_ID Tx Half Complete Callback ID\r
+ * @arg @ref HAL_UART_TX_COMPLETE_CB_ID Tx Complete Callback ID\r
+ * @arg @ref HAL_UART_RX_HALFCOMPLETE_CB_ID Rx Half Complete Callback ID\r
+ * @arg @ref HAL_UART_RX_COMPLETE_CB_ID Rx Complete Callback ID\r
+ * @arg @ref HAL_UART_ERROR_CB_ID Error Callback ID\r
+ * @arg @ref HAL_UART_ABORT_COMPLETE_CB_ID Abort Complete Callback ID\r
+ * @arg @ref HAL_UART_ABORT_TRANSMIT_COMPLETE_CB_ID Abort Transmit Complete Callback ID\r
+ * @arg @ref HAL_UART_ABORT_RECEIVE_COMPLETE_CB_ID Abort Receive Complete Callback ID\r
+ * @arg @ref HAL_UART_MSPINIT_CB_ID MspInit Callback ID\r
+ * @arg @ref HAL_UART_MSPDEINIT_CB_ID MspDeInit Callback ID\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_UART_UnRegisterCallback(UART_HandleTypeDef *huart, HAL_UART_CallbackIDTypeDef CallbackID)\r
+{\r
+ HAL_StatusTypeDef status = HAL_OK;\r
+\r
+ /* Process locked */\r
+ __HAL_LOCK(huart);\r
+\r
+ if (HAL_UART_STATE_READY == huart->gState)\r
+ {\r
+ switch (CallbackID)\r
+ {\r
+ case HAL_UART_TX_HALFCOMPLETE_CB_ID :\r
+ huart->TxHalfCpltCallback = HAL_UART_TxHalfCpltCallback; /* Legacy weak TxHalfCpltCallback */\r
+ break;\r
+\r
+ case HAL_UART_TX_COMPLETE_CB_ID :\r
+ huart->TxCpltCallback = HAL_UART_TxCpltCallback; /* Legacy weak TxCpltCallback */\r
+ break;\r
+\r
+ case HAL_UART_RX_HALFCOMPLETE_CB_ID :\r
+ huart->RxHalfCpltCallback = HAL_UART_RxHalfCpltCallback; /* Legacy weak RxHalfCpltCallback */\r
+ break;\r
+\r
+ case HAL_UART_RX_COMPLETE_CB_ID :\r
+ huart->RxCpltCallback = HAL_UART_RxCpltCallback; /* Legacy weak RxCpltCallback */\r
+ break;\r
+\r
+ case HAL_UART_ERROR_CB_ID :\r
+ huart->ErrorCallback = HAL_UART_ErrorCallback; /* Legacy weak ErrorCallback */\r
+ break;\r
+\r
+ case HAL_UART_ABORT_COMPLETE_CB_ID :\r
+ huart->AbortCpltCallback = HAL_UART_AbortCpltCallback; /* Legacy weak AbortCpltCallback */\r
+ break;\r
+\r
+ case HAL_UART_ABORT_TRANSMIT_COMPLETE_CB_ID :\r
+ huart->AbortTransmitCpltCallback = HAL_UART_AbortTransmitCpltCallback; /* Legacy weak AbortTransmitCpltCallback */\r
+ break;\r
+\r
+ case HAL_UART_ABORT_RECEIVE_COMPLETE_CB_ID :\r
+ huart->AbortReceiveCpltCallback = HAL_UART_AbortReceiveCpltCallback; /* Legacy weak AbortReceiveCpltCallback */\r
+ break;\r
+\r
+ case HAL_UART_MSPINIT_CB_ID :\r
+ huart->MspInitCallback = HAL_UART_MspInit; /* Legacy weak MspInitCallback */\r
+ break;\r
+\r
+ case HAL_UART_MSPDEINIT_CB_ID :\r
+ huart->MspDeInitCallback = HAL_UART_MspDeInit; /* Legacy weak MspDeInitCallback */\r
+ break;\r
+\r
+ default :\r
+ /* Update the error code */\r
+ huart->ErrorCode |= HAL_UART_ERROR_INVALID_CALLBACK;\r
+\r
+ /* Return error status */\r
+ status = HAL_ERROR;\r
+ break;\r
+ }\r
+ }\r
+ else if (HAL_UART_STATE_RESET == huart->gState)\r
+ {\r
+ switch (CallbackID)\r
+ {\r
+ case HAL_UART_MSPINIT_CB_ID :\r
+ huart->MspInitCallback = HAL_UART_MspInit;\r
+ break;\r
+\r
+ case HAL_UART_MSPDEINIT_CB_ID :\r
+ huart->MspDeInitCallback = HAL_UART_MspDeInit;\r
+ break;\r
+\r
+ default :\r
+ /* Update the error code */\r
+ huart->ErrorCode |= HAL_UART_ERROR_INVALID_CALLBACK;\r
+\r
+ /* Return error status */\r
+ status = HAL_ERROR;\r
+ break;\r
+ }\r
+ }\r
+ else\r
+ {\r
+ /* Update the error code */\r
+ huart->ErrorCode |= HAL_UART_ERROR_INVALID_CALLBACK;\r
+\r
+ /* Return error status */\r
+ status = HAL_ERROR;\r
+ }\r
+\r
+ /* Release Lock */\r
+ __HAL_UNLOCK(huart);\r
+\r
+ return status;\r
+}\r
+#endif /* USE_HAL_UART_REGISTER_CALLBACKS */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup UART_Exported_Functions_Group2 IO operation functions\r
+ * @brief UART Transmit and Receive functions\r
+ *\r
+@verbatim\r
+ ===============================================================================\r
+ ##### IO operation functions #####\r
+ ===============================================================================\r
+ This subsection provides a set of functions allowing to manage the UART asynchronous\r
+ and Half duplex data transfers.\r
+\r
+ (#) There are two modes of transfer:\r
+ (+) Blocking mode: The communication is performed in polling mode.\r
+ The HAL status of all data processing is returned by the same function\r
+ after finishing transfer.\r
+ (+) Non-Blocking mode: The communication is performed using Interrupts\r
+ or DMA, these API's return the HAL status.\r
+ The end of the data processing will be indicated through the\r
+ dedicated UART IRQ when using Interrupt mode or the DMA IRQ when\r
+ using DMA mode.\r
+ The HAL_UART_TxCpltCallback(), HAL_UART_RxCpltCallback() user callbacks\r
+ will be executed respectively at the end of the transmit or receive process\r
+ The HAL_UART_ErrorCallback()user callback will be executed when a communication error is detected.\r
+\r
+ (#) Blocking mode API's are :\r
+ (+) HAL_UART_Transmit()\r
+ (+) HAL_UART_Receive()\r
+\r
+ (#) Non-Blocking mode API's with Interrupt are :\r
+ (+) HAL_UART_Transmit_IT()\r
+ (+) HAL_UART_Receive_IT()\r
+ (+) HAL_UART_IRQHandler()\r
+\r
+ (#) Non-Blocking mode API's with DMA are :\r
+ (+) HAL_UART_Transmit_DMA()\r
+ (+) HAL_UART_Receive_DMA()\r
+ (+) HAL_UART_DMAPause()\r
+ (+) HAL_UART_DMAResume()\r
+ (+) HAL_UART_DMAStop()\r
+\r
+ (#) A set of Transfer Complete Callbacks are provided in Non_Blocking mode:\r
+ (+) HAL_UART_TxHalfCpltCallback()\r
+ (+) HAL_UART_TxCpltCallback()\r
+ (+) HAL_UART_RxHalfCpltCallback()\r
+ (+) HAL_UART_RxCpltCallback()\r
+ (+) HAL_UART_ErrorCallback()\r
+\r
+ (#) Non-Blocking mode transfers could be aborted using Abort API's :\r
+ (+) HAL_UART_Abort()\r
+ (+) HAL_UART_AbortTransmit()\r
+ (+) HAL_UART_AbortReceive()\r
+ (+) HAL_UART_Abort_IT()\r
+ (+) HAL_UART_AbortTransmit_IT()\r
+ (+) HAL_UART_AbortReceive_IT()\r
+\r
+ (#) For Abort services based on interrupts (HAL_UART_Abortxxx_IT), a set of Abort Complete Callbacks are provided:\r
+ (+) HAL_UART_AbortCpltCallback()\r
+ (+) HAL_UART_AbortTransmitCpltCallback()\r
+ (+) HAL_UART_AbortReceiveCpltCallback()\r
+\r
+ (#) In Non-Blocking mode transfers, possible errors are split into 2 categories.\r
+ Errors are handled as follows :\r
+ (+) Error is considered as Recoverable and non blocking : Transfer could go till end, but error severity is\r
+ to be evaluated by user : this concerns Frame Error, Parity Error or Noise Error in Interrupt mode reception .\r
+ Received character is then retrieved and stored in Rx buffer, Error code is set to allow user to identify error type,\r
+ and HAL_UART_ErrorCallback() user callback is executed. Transfer is kept ongoing on UART side.\r
+ If user wants to abort it, Abort services should be called by user.\r
+ (+) Error is considered as Blocking : Transfer could not be completed properly and is aborted.\r
+ This concerns Overrun Error In Interrupt mode reception and all errors in DMA mode.\r
+ Error code is set to allow user to identify error type, and HAL_UART_ErrorCallback() user callback is executed.\r
+\r
+ -@- In the Half duplex communication, it is forbidden to run the transmit\r
+ and receive process in parallel, the UART state HAL_UART_STATE_BUSY_TX_RX can't be useful.\r
+\r
+@endverbatim\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @brief Sends an amount of data in blocking mode.\r
+ * @param huart Pointer to a UART_HandleTypeDef structure that contains\r
+ * the configuration information for the specified UART module.\r
+ * @param pData Pointer to data buffer\r
+ * @param Size Amount of data to be sent\r
+ * @param Timeout Timeout duration\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_UART_Transmit(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size, uint32_t Timeout)\r
+{\r
+ uint16_t *tmp;\r
+ uint32_t tickstart = 0U;\r
+\r
+ /* Check that a Tx process is not already ongoing */\r
+ if (huart->gState == HAL_UART_STATE_READY)\r
+ {\r
+ if ((pData == NULL) || (Size == 0U))\r
+ {\r
+ return HAL_ERROR;\r
+ }\r
+\r
+ /* Process Locked */\r
+ __HAL_LOCK(huart);\r
+\r
+ huart->ErrorCode = HAL_UART_ERROR_NONE;\r
+ huart->gState = HAL_UART_STATE_BUSY_TX;\r
+\r
+ /* Init tickstart for timeout managment */\r
+ tickstart = HAL_GetTick();\r
+\r
+ huart->TxXferSize = Size;\r
+ huart->TxXferCount = Size;\r
+ while (huart->TxXferCount > 0U)\r
+ {\r
+ huart->TxXferCount--;\r
+ if (huart->Init.WordLength == UART_WORDLENGTH_9B)\r
+ {\r
+ if (UART_WaitOnFlagUntilTimeout(huart, UART_FLAG_TXE, RESET, tickstart, Timeout) != HAL_OK)\r
+ {\r
+ return HAL_TIMEOUT;\r
+ }\r
+ tmp = (uint16_t *) pData;\r
+ huart->Instance->DR = (*tmp & (uint16_t)0x01FF);\r
+ if (huart->Init.Parity == UART_PARITY_NONE)\r
+ {\r
+ pData += 2U;\r
+ }\r
+ else\r
+ {\r
+ pData += 1U;\r
+ }\r
+ }\r
+ else\r
+ {\r
+ if (UART_WaitOnFlagUntilTimeout(huart, UART_FLAG_TXE, RESET, tickstart, Timeout) != HAL_OK)\r
+ {\r
+ return HAL_TIMEOUT;\r
+ }\r
+ huart->Instance->DR = (*pData++ & (uint8_t)0xFF);\r
+ }\r
+ }\r
+\r
+ if (UART_WaitOnFlagUntilTimeout(huart, UART_FLAG_TC, RESET, tickstart, Timeout) != HAL_OK)\r
+ {\r
+ return HAL_TIMEOUT;\r
+ }\r
+\r
+ /* At end of Tx process, restore huart->gState to Ready */\r
+ huart->gState = HAL_UART_STATE_READY;\r
+\r
+ /* Process Unlocked */\r
+ __HAL_UNLOCK(huart);\r
+\r
+ return HAL_OK;\r
+ }\r
+ else\r
+ {\r
+ return HAL_BUSY;\r
+ }\r
+}\r
+\r
+/**\r
+ * @brief Receives an amount of data in blocking mode.\r
+ * @param huart Pointer to a UART_HandleTypeDef structure that contains\r
+ * the configuration information for the specified UART module.\r
+ * @param pData Pointer to data buffer\r
+ * @param Size Amount of data to be received\r
+ * @param Timeout Timeout duration\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_UART_Receive(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size, uint32_t Timeout)\r
+{\r
+ uint16_t *tmp;\r
+ uint32_t tickstart = 0U;\r
+\r
+ /* Check that a Rx process is not already ongoing */\r
+ if (huart->RxState == HAL_UART_STATE_READY)\r
+ {\r
+ if ((pData == NULL) || (Size == 0U))\r
+ {\r
+ return HAL_ERROR;\r
+ }\r
+\r
+ /* Process Locked */\r
+ __HAL_LOCK(huart);\r
+\r
+ huart->ErrorCode = HAL_UART_ERROR_NONE;\r
+ huart->RxState = HAL_UART_STATE_BUSY_RX;\r
+\r
+ /* Init tickstart for timeout managment */\r
+ tickstart = HAL_GetTick();\r
+\r
+ huart->RxXferSize = Size;\r
+ huart->RxXferCount = Size;\r
+\r
+ /* Check the remain data to be received */\r
+ while (huart->RxXferCount > 0U)\r
+ {\r
+ huart->RxXferCount--;\r
+ if (huart->Init.WordLength == UART_WORDLENGTH_9B)\r
+ {\r
+ if (UART_WaitOnFlagUntilTimeout(huart, UART_FLAG_RXNE, RESET, tickstart, Timeout) != HAL_OK)\r
+ {\r
+ return HAL_TIMEOUT;\r
+ }\r
+ tmp = (uint16_t *) pData;\r
+ if (huart->Init.Parity == UART_PARITY_NONE)\r
+ {\r
+ *tmp = (uint16_t)(huart->Instance->DR & (uint16_t)0x01FF);\r
+ pData += 2U;\r
+ }\r
+ else\r
+ {\r
+ *tmp = (uint16_t)(huart->Instance->DR & (uint16_t)0x00FF);\r
+ pData += 1U;\r
+ }\r
+\r
+ }\r
+ else\r
+ {\r
+ if (UART_WaitOnFlagUntilTimeout(huart, UART_FLAG_RXNE, RESET, tickstart, Timeout) != HAL_OK)\r
+ {\r
+ return HAL_TIMEOUT;\r
+ }\r
+ if (huart->Init.Parity == UART_PARITY_NONE)\r
+ {\r
+ *pData++ = (uint8_t)(huart->Instance->DR & (uint8_t)0x00FF);\r
+ }\r
+ else\r
+ {\r
+ *pData++ = (uint8_t)(huart->Instance->DR & (uint8_t)0x007F);\r
+ }\r
+\r
+ }\r
+ }\r
+\r
+ /* At end of Rx process, restore huart->RxState to Ready */\r
+ huart->RxState = HAL_UART_STATE_READY;\r
+\r
+ /* Process Unlocked */\r
+ __HAL_UNLOCK(huart);\r
+\r
+ return HAL_OK;\r
+ }\r
+ else\r
+ {\r
+ return HAL_BUSY;\r
+ }\r
+}\r
+\r
+/**\r
+ * @brief Sends an amount of data in non blocking mode.\r
+ * @param huart Pointer to a UART_HandleTypeDef structure that contains\r
+ * the configuration information for the specified UART module.\r
+ * @param pData Pointer to data buffer\r
+ * @param Size Amount of data to be sent\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_UART_Transmit_IT(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size)\r
+{\r
+ /* Check that a Tx process is not already ongoing */\r
+ if (huart->gState == HAL_UART_STATE_READY)\r
+ {\r
+ if ((pData == NULL) || (Size == 0U))\r
+ {\r
+ return HAL_ERROR;\r
+ }\r
+\r
+ /* Process Locked */\r
+ __HAL_LOCK(huart);\r
+\r
+ huart->pTxBuffPtr = pData;\r
+ huart->TxXferSize = Size;\r
+ huart->TxXferCount = Size;\r
+\r
+ huart->ErrorCode = HAL_UART_ERROR_NONE;\r
+ huart->gState = HAL_UART_STATE_BUSY_TX;\r
+\r
+ /* Process Unlocked */\r
+ __HAL_UNLOCK(huart);\r
+\r
+ /* Enable the UART Transmit data register empty Interrupt */\r
+ __HAL_UART_ENABLE_IT(huart, UART_IT_TXE);\r
+\r
+ return HAL_OK;\r
+ }\r
+ else\r
+ {\r
+ return HAL_BUSY;\r
+ }\r
+}\r
+\r
+/**\r
+ * @brief Receives an amount of data in non blocking mode.\r
+ * @param huart Pointer to a UART_HandleTypeDef structure that contains\r
+ * the configuration information for the specified UART module.\r
+ * @param pData Pointer to data buffer\r
+ * @param Size Amount of data to be received\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_UART_Receive_IT(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size)\r
+{\r
+ /* Check that a Rx process is not already ongoing */\r
+ if (huart->RxState == HAL_UART_STATE_READY)\r
+ {\r
+ if ((pData == NULL) || (Size == 0U))\r
+ {\r
+ return HAL_ERROR;\r
+ }\r
+\r
+ /* Process Locked */\r
+ __HAL_LOCK(huart);\r
+\r
+ huart->pRxBuffPtr = pData;\r
+ huart->RxXferSize = Size;\r
+ huart->RxXferCount = Size;\r
+\r
+ huart->ErrorCode = HAL_UART_ERROR_NONE;\r
+ huart->RxState = HAL_UART_STATE_BUSY_RX;\r
+\r
+ /* Process Unlocked */\r
+ __HAL_UNLOCK(huart);\r
+\r
+ /* Enable the UART Parity Error Interrupt */\r
+ __HAL_UART_ENABLE_IT(huart, UART_IT_PE);\r
+\r
+ /* Enable the UART Error Interrupt: (Frame error, noise error, overrun error) */\r
+ __HAL_UART_ENABLE_IT(huart, UART_IT_ERR);\r
+\r
+ /* Enable the UART Data Register not empty Interrupt */\r
+ __HAL_UART_ENABLE_IT(huart, UART_IT_RXNE);\r
+\r
+ return HAL_OK;\r
+ }\r
+ else\r
+ {\r
+ return HAL_BUSY;\r
+ }\r
+}\r
+\r
+/**\r
+ * @brief Sends an amount of data in non blocking mode.\r
+ * @param huart Pointer to a UART_HandleTypeDef structure that contains\r
+ * the configuration information for the specified UART module.\r
+ * @param pData Pointer to data buffer\r
+ * @param Size Amount of data to be sent\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_UART_Transmit_DMA(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size)\r
+{\r
+ uint32_t *tmp;\r
+\r
+ /* Check that a Tx process is not already ongoing */\r
+ if (huart->gState == HAL_UART_STATE_READY)\r
+ {\r
+ if ((pData == NULL) || (Size == 0U))\r
+ {\r
+ return HAL_ERROR;\r
+ }\r
+\r
+ /* Process Locked */\r
+ __HAL_LOCK(huart);\r
+\r
+ huart->pTxBuffPtr = pData;\r
+ huart->TxXferSize = Size;\r
+ huart->TxXferCount = Size;\r
+\r
+ huart->ErrorCode = HAL_UART_ERROR_NONE;\r
+ huart->gState = HAL_UART_STATE_BUSY_TX;\r
+\r
+ /* Set the UART DMA transfer complete callback */\r
+ huart->hdmatx->XferCpltCallback = UART_DMATransmitCplt;\r
+\r
+ /* Set the UART DMA Half transfer complete callback */\r
+ huart->hdmatx->XferHalfCpltCallback = UART_DMATxHalfCplt;\r
+\r
+ /* Set the DMA error callback */\r
+ huart->hdmatx->XferErrorCallback = UART_DMAError;\r
+\r
+ /* Set the DMA abort callback */\r
+ huart->hdmatx->XferAbortCallback = NULL;\r
+\r
+ /* Enable the UART transmit DMA channel */\r
+ tmp = (uint32_t *)&pData;\r
+ HAL_DMA_Start_IT(huart->hdmatx, *(uint32_t *)tmp, (uint32_t)&huart->Instance->DR, Size);\r
+\r
+ /* Clear the TC flag in the SR register by writing 0 to it */\r
+ __HAL_UART_CLEAR_FLAG(huart, UART_FLAG_TC);\r
+\r
+ /* Process Unlocked */\r
+ __HAL_UNLOCK(huart);\r
+\r
+ /* Enable the DMA transfer for transmit request by setting the DMAT bit\r
+ in the UART CR3 register */\r
+ SET_BIT(huart->Instance->CR3, USART_CR3_DMAT);\r
+\r
+ return HAL_OK;\r
+ }\r
+ else\r
+ {\r
+ return HAL_BUSY;\r
+ }\r
+}\r
+\r
+/**\r
+ * @brief Receives an amount of data in non blocking mode.\r
+ * @param huart Pointer to a UART_HandleTypeDef structure that contains\r
+ * the configuration information for the specified UART module.\r
+ * @param pData Pointer to data buffer\r
+ * @param Size Amount of data to be received\r
+ * @note When the UART parity is enabled (PCE = 1) the received data contains the parity bit.\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_UART_Receive_DMA(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size)\r
+{\r
+ uint32_t *tmp;\r
+\r
+ /* Check that a Rx process is not already ongoing */\r
+ if (huart->RxState == HAL_UART_STATE_READY)\r
+ {\r
+ if ((pData == NULL) || (Size == 0U))\r
+ {\r
+ return HAL_ERROR;\r
+ }\r
+\r
+ /* Process Locked */\r
+ __HAL_LOCK(huart);\r
+\r
+ huart->pRxBuffPtr = pData;\r
+ huart->RxXferSize = Size;\r
+\r
+ huart->ErrorCode = HAL_UART_ERROR_NONE;\r
+ huart->RxState = HAL_UART_STATE_BUSY_RX;\r
+\r
+ /* Set the UART DMA transfer complete callback */\r
+ huart->hdmarx->XferCpltCallback = UART_DMAReceiveCplt;\r
+\r
+ /* Set the UART DMA Half transfer complete callback */\r
+ huart->hdmarx->XferHalfCpltCallback = UART_DMARxHalfCplt;\r
+\r
+ /* Set the DMA error callback */\r
+ huart->hdmarx->XferErrorCallback = UART_DMAError;\r
+\r
+ /* Set the DMA abort callback */\r
+ huart->hdmarx->XferAbortCallback = NULL;\r
+\r
+ /* Enable the DMA channel */\r
+ tmp = (uint32_t *)&pData;\r
+ HAL_DMA_Start_IT(huart->hdmarx, (uint32_t)&huart->Instance->DR, *(uint32_t *)tmp, Size);\r
+\r
+ /* Clear the Overrun flag just before enabling the DMA Rx request: can be mandatory for the second transfer */\r
+ __HAL_UART_CLEAR_OREFLAG(huart);\r
+\r
+ /* Process Unlocked */\r
+ __HAL_UNLOCK(huart);\r
+\r
+ /* Enable the UART Parity Error Interrupt */\r
+ SET_BIT(huart->Instance->CR1, USART_CR1_PEIE);\r
+\r
+ /* Enable the UART Error Interrupt: (Frame error, noise error, overrun error) */\r
+ SET_BIT(huart->Instance->CR3, USART_CR3_EIE);\r
+\r
+ /* Enable the DMA transfer for the receiver request by setting the DMAR bit\r
+ in the UART CR3 register */\r
+ SET_BIT(huart->Instance->CR3, USART_CR3_DMAR);\r
+\r
+ return HAL_OK;\r
+ }\r
+ else\r
+ {\r
+ return HAL_BUSY;\r
+ }\r
+}\r
+\r
+/**\r
+ * @brief Pauses the DMA Transfer.\r
+ * @param huart Pointer to a UART_HandleTypeDef structure that contains\r
+ * the configuration information for the specified UART module.\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_UART_DMAPause(UART_HandleTypeDef *huart)\r
+{\r
+ uint32_t dmarequest = 0x00U;\r
+\r
+ /* Process Locked */\r
+ __HAL_LOCK(huart);\r
+\r
+ dmarequest = HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAT);\r
+ if ((huart->gState == HAL_UART_STATE_BUSY_TX) && dmarequest)\r
+ {\r
+ /* Disable the UART DMA Tx request */\r
+ CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAT);\r
+ }\r
+\r
+ dmarequest = HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR);\r
+ if ((huart->RxState == HAL_UART_STATE_BUSY_RX) && dmarequest)\r
+ {\r
+ /* Disable RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts */\r
+ CLEAR_BIT(huart->Instance->CR1, USART_CR1_PEIE);\r
+ CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE);\r
+\r
+ /* Disable the UART DMA Rx request */\r
+ CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAR);\r
+ }\r
+\r
+ /* Process Unlocked */\r
+ __HAL_UNLOCK(huart);\r
+\r
+ return HAL_OK;\r
+}\r
+\r
+/**\r
+ * @brief Resumes the DMA Transfer.\r
+ * @param huart Pointer to a UART_HandleTypeDef structure that contains\r
+ * the configuration information for the specified UART module.\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_UART_DMAResume(UART_HandleTypeDef *huart)\r
+{\r
+ /* Process Locked */\r
+ __HAL_LOCK(huart);\r
+\r
+ if (huart->gState == HAL_UART_STATE_BUSY_TX)\r
+ {\r
+ /* Enable the UART DMA Tx request */\r
+ SET_BIT(huart->Instance->CR3, USART_CR3_DMAT);\r
+ }\r
+\r
+ if (huart->RxState == HAL_UART_STATE_BUSY_RX)\r
+ {\r
+ /* Clear the Overrun flag before resuming the Rx transfer*/\r
+ __HAL_UART_CLEAR_OREFLAG(huart);\r
+\r
+ /* Reenable PE and ERR (Frame error, noise error, overrun error) interrupts */\r
+ SET_BIT(huart->Instance->CR1, USART_CR1_PEIE);\r
+ SET_BIT(huart->Instance->CR3, USART_CR3_EIE);\r
+\r
+ /* Enable the UART DMA Rx request */\r
+ SET_BIT(huart->Instance->CR3, USART_CR3_DMAR);\r
+ }\r
+\r
+ /* Process Unlocked */\r
+ __HAL_UNLOCK(huart);\r
+\r
+ return HAL_OK;\r
+}\r
+\r
+/**\r
+ * @brief Stops the DMA Transfer.\r
+ * @param huart Pointer to a UART_HandleTypeDef structure that contains\r
+ * the configuration information for the specified UART module.\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_UART_DMAStop(UART_HandleTypeDef *huart)\r
+{\r
+ uint32_t dmarequest = 0x00U;\r
+ /* The Lock is not implemented on this API to allow the user application\r
+ to call the HAL UART API under callbacks HAL_UART_TxCpltCallback() / HAL_UART_RxCpltCallback():\r
+ when calling HAL_DMA_Abort() API the DMA TX/RX Transfer complete interrupt is generated\r
+ and the correspond call back is executed HAL_UART_TxCpltCallback() / HAL_UART_RxCpltCallback()\r
+ */\r
+\r
+ /* Stop UART DMA Tx request if ongoing */\r
+ dmarequest = HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAT);\r
+ if ((huart->gState == HAL_UART_STATE_BUSY_TX) && dmarequest)\r
+ {\r
+ CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAT);\r
+\r
+ /* Abort the UART DMA Tx channel */\r
+ if (huart->hdmatx != NULL)\r
+ {\r
+ HAL_DMA_Abort(huart->hdmatx);\r
+ }\r
+ UART_EndTxTransfer(huart);\r
+ }\r
+\r
+ /* Stop UART DMA Rx request if ongoing */\r
+ dmarequest = HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR);\r
+ if ((huart->RxState == HAL_UART_STATE_BUSY_RX) && dmarequest)\r
+ {\r
+ CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAR);\r
+\r
+ /* Abort the UART DMA Rx channel */\r
+ if (huart->hdmarx != NULL)\r
+ {\r
+ HAL_DMA_Abort(huart->hdmarx);\r
+ }\r
+ UART_EndRxTransfer(huart);\r
+ }\r
+\r
+ return HAL_OK;\r
+}\r
+\r
+/**\r
+ * @brief Abort ongoing transfers (blocking mode).\r
+ * @param huart UART handle.\r
+ * @note This procedure could be used for aborting any ongoing transfer started in Interrupt or DMA mode.\r
+ * This procedure performs following operations :\r
+ * - Disable UART Interrupts (Tx and Rx)\r
+ * - Disable the DMA transfer in the peripheral register (if enabled)\r
+ * - Abort DMA transfer by calling HAL_DMA_Abort (in case of transfer in DMA mode)\r
+ * - Set handle State to READY\r
+ * @note This procedure is executed in blocking mode : when exiting function, Abort is considered as completed.\r
+ * @retval HAL status\r
+*/\r
+HAL_StatusTypeDef HAL_UART_Abort(UART_HandleTypeDef *huart)\r
+{\r
+ /* Disable TXEIE, TCIE, RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts */\r
+ CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE | USART_CR1_PEIE | USART_CR1_TXEIE | USART_CR1_TCIE));\r
+ CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE);\r
+\r
+ /* Disable the UART DMA Tx request if enabled */\r
+ if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAT))\r
+ {\r
+ CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAT);\r
+\r
+ /* Abort the UART DMA Tx channel: use blocking DMA Abort API (no callback) */\r
+ if (huart->hdmatx != NULL)\r
+ {\r
+ /* Set the UART DMA Abort callback to Null.\r
+ No call back execution at end of DMA abort procedure */\r
+ huart->hdmatx->XferAbortCallback = NULL;\r
+\r
+ if (HAL_DMA_Abort(huart->hdmatx) != HAL_OK)\r
+ {\r
+ if (HAL_DMA_GetError(huart->hdmatx) == HAL_DMA_ERROR_TIMEOUT)\r
+ {\r
+ /* Set error code to DMA */\r
+ huart->ErrorCode = HAL_UART_ERROR_DMA;\r
+\r
+ return HAL_TIMEOUT;\r
+ }\r
+ }\r
+ }\r
+ }\r
+\r
+ /* Disable the UART DMA Rx request if enabled */\r
+ if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR))\r
+ {\r
+ CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAR);\r
+\r
+ /* Abort the UART DMA Rx channel: use blocking DMA Abort API (no callback) */\r
+ if (huart->hdmarx != NULL)\r
+ {\r
+ /* Set the UART DMA Abort callback to Null.\r
+ No call back execution at end of DMA abort procedure */\r
+ huart->hdmarx->XferAbortCallback = NULL;\r
+\r
+ if (HAL_DMA_Abort(huart->hdmarx) != HAL_OK)\r
+ {\r
+ if (HAL_DMA_GetError(huart->hdmarx) == HAL_DMA_ERROR_TIMEOUT)\r
+ {\r
+ /* Set error code to DMA */\r
+ huart->ErrorCode = HAL_UART_ERROR_DMA;\r
+\r
+ return HAL_TIMEOUT;\r
+ }\r
+ }\r
+ }\r
+ }\r
+\r
+ /* Reset Tx and Rx transfer counters */\r
+ huart->TxXferCount = 0x00U;\r
+ huart->RxXferCount = 0x00U;\r
+\r
+ /* Reset ErrorCode */\r
+ huart->ErrorCode = HAL_UART_ERROR_NONE;\r
+\r
+ /* Restore huart->RxState and huart->gState to Ready */\r
+ huart->RxState = HAL_UART_STATE_READY;\r
+ huart->gState = HAL_UART_STATE_READY;\r
+\r
+ return HAL_OK;\r
+}\r
+\r
+/**\r
+ * @brief Abort ongoing Transmit transfer (blocking mode).\r
+ * @param huart UART handle.\r
+ * @note This procedure could be used for aborting any ongoing Tx transfer started in Interrupt or DMA mode.\r
+ * This procedure performs following operations :\r
+ * - Disable UART Interrupts (Tx)\r
+ * - Disable the DMA transfer in the peripheral register (if enabled)\r
+ * - Abort DMA transfer by calling HAL_DMA_Abort (in case of transfer in DMA mode)\r
+ * - Set handle State to READY\r
+ * @note This procedure is executed in blocking mode : when exiting function, Abort is considered as completed.\r
+ * @retval HAL status\r
+*/\r
+HAL_StatusTypeDef HAL_UART_AbortTransmit(UART_HandleTypeDef *huart)\r
+{\r
+ /* Disable TXEIE and TCIE interrupts */\r
+ CLEAR_BIT(huart->Instance->CR1, (USART_CR1_TXEIE | USART_CR1_TCIE));\r
+\r
+ /* Disable the UART DMA Tx request if enabled */\r
+ if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAT))\r
+ {\r
+ CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAT);\r
+\r
+ /* Abort the UART DMA Tx channel : use blocking DMA Abort API (no callback) */\r
+ if (huart->hdmatx != NULL)\r
+ {\r
+ /* Set the UART DMA Abort callback to Null.\r
+ No call back execution at end of DMA abort procedure */\r
+ huart->hdmatx->XferAbortCallback = NULL;\r
+\r
+ if (HAL_DMA_Abort(huart->hdmatx) != HAL_OK)\r
+ {\r
+ if (HAL_DMA_GetError(huart->hdmatx) == HAL_DMA_ERROR_TIMEOUT)\r
+ {\r
+ /* Set error code to DMA */\r
+ huart->ErrorCode = HAL_UART_ERROR_DMA;\r
+\r
+ return HAL_TIMEOUT;\r
+ }\r
+ }\r
+ }\r
+ }\r
+\r
+ /* Reset Tx transfer counter */\r
+ huart->TxXferCount = 0x00U;\r
+\r
+ /* Restore huart->gState to Ready */\r
+ huart->gState = HAL_UART_STATE_READY;\r
+\r
+ return HAL_OK;\r
+}\r
+\r
+/**\r
+ * @brief Abort ongoing Receive transfer (blocking mode).\r
+ * @param huart UART handle.\r
+ * @note This procedure could be used for aborting any ongoing Rx transfer started in Interrupt or DMA mode.\r
+ * This procedure performs following operations :\r
+ * - Disable UART Interrupts (Rx)\r
+ * - Disable the DMA transfer in the peripheral register (if enabled)\r
+ * - Abort DMA transfer by calling HAL_DMA_Abort (in case of transfer in DMA mode)\r
+ * - Set handle State to READY\r
+ * @note This procedure is executed in blocking mode : when exiting function, Abort is considered as completed.\r
+ * @retval HAL status\r
+*/\r
+HAL_StatusTypeDef HAL_UART_AbortReceive(UART_HandleTypeDef *huart)\r
+{\r
+ /* Disable RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts */\r
+ CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE | USART_CR1_PEIE));\r
+ CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE);\r
+\r
+ /* Disable the UART DMA Rx request if enabled */\r
+ if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR))\r
+ {\r
+ CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAR);\r
+\r
+ /* Abort the UART DMA Rx channel : use blocking DMA Abort API (no callback) */\r
+ if (huart->hdmarx != NULL)\r
+ {\r
+ /* Set the UART DMA Abort callback to Null.\r
+ No call back execution at end of DMA abort procedure */\r
+ huart->hdmarx->XferAbortCallback = NULL;\r
+\r
+ if (HAL_DMA_Abort(huart->hdmarx) != HAL_OK)\r
+ {\r
+ if (HAL_DMA_GetError(huart->hdmarx) == HAL_DMA_ERROR_TIMEOUT)\r
+ {\r
+ /* Set error code to DMA */\r
+ huart->ErrorCode = HAL_UART_ERROR_DMA;\r
+\r
+ return HAL_TIMEOUT;\r
+ }\r
+ }\r
+ }\r
+ }\r
+\r
+ /* Reset Rx transfer counter */\r
+ huart->RxXferCount = 0x00U;\r
+\r
+ /* Restore huart->RxState to Ready */\r
+ huart->RxState = HAL_UART_STATE_READY;\r
+\r
+ return HAL_OK;\r
+}\r
+\r
+/**\r
+ * @brief Abort ongoing transfers (Interrupt mode).\r
+ * @param huart UART handle.\r
+ * @note This procedure could be used for aborting any ongoing transfer started in Interrupt or DMA mode.\r
+ * This procedure performs following operations :\r
+ * - Disable UART Interrupts (Tx and Rx)\r
+ * - Disable the DMA transfer in the peripheral register (if enabled)\r
+ * - Abort DMA transfer by calling HAL_DMA_Abort_IT (in case of transfer in DMA mode)\r
+ * - Set handle State to READY\r
+ * - At abort completion, call user abort complete callback\r
+ * @note This procedure is executed in Interrupt mode, meaning that abort procedure could be\r
+ * considered as completed only when user abort complete callback is executed (not when exiting function).\r
+ * @retval HAL status\r
+*/\r
+HAL_StatusTypeDef HAL_UART_Abort_IT(UART_HandleTypeDef *huart)\r
+{\r
+ uint32_t AbortCplt = 0x01U;\r
+\r
+ /* Disable TXEIE, TCIE, RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts */\r
+ CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE | USART_CR1_PEIE | USART_CR1_TXEIE | USART_CR1_TCIE));\r
+ CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE);\r
+\r
+ /* If DMA Tx and/or DMA Rx Handles are associated to UART Handle, DMA Abort complete callbacks should be initialised\r
+ before any call to DMA Abort functions */\r
+ /* DMA Tx Handle is valid */\r
+ if (huart->hdmatx != NULL)\r
+ {\r
+ /* Set DMA Abort Complete callback if UART DMA Tx request if enabled.\r
+ Otherwise, set it to NULL */\r
+ if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAT))\r
+ {\r
+ huart->hdmatx->XferAbortCallback = UART_DMATxAbortCallback;\r
+ }\r
+ else\r
+ {\r
+ huart->hdmatx->XferAbortCallback = NULL;\r
+ }\r
+ }\r
+ /* DMA Rx Handle is valid */\r
+ if (huart->hdmarx != NULL)\r
+ {\r
+ /* Set DMA Abort Complete callback if UART DMA Rx request if enabled.\r
+ Otherwise, set it to NULL */\r
+ if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR))\r
+ {\r
+ huart->hdmarx->XferAbortCallback = UART_DMARxAbortCallback;\r
+ }\r
+ else\r
+ {\r
+ huart->hdmarx->XferAbortCallback = NULL;\r
+ }\r
+ }\r
+\r
+ /* Disable the UART DMA Tx request if enabled */\r
+ if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAT))\r
+ {\r
+ /* Disable DMA Tx at UART level */\r
+ CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAT);\r
+\r
+ /* Abort the UART DMA Tx channel : use non blocking DMA Abort API (callback) */\r
+ if (huart->hdmatx != NULL)\r
+ {\r
+ /* UART Tx DMA Abort callback has already been initialised :\r
+ will lead to call HAL_UART_AbortCpltCallback() at end of DMA abort procedure */\r
+\r
+ /* Abort DMA TX */\r
+ if (HAL_DMA_Abort_IT(huart->hdmatx) != HAL_OK)\r
+ {\r
+ huart->hdmatx->XferAbortCallback = NULL;\r
+ }\r
+ else\r
+ {\r
+ AbortCplt = 0x00U;\r
+ }\r
+ }\r
+ }\r
+\r
+ /* Disable the UART DMA Rx request if enabled */\r
+ if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR))\r
+ {\r
+ CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAR);\r
+\r
+ /* Abort the UART DMA Rx channel : use non blocking DMA Abort API (callback) */\r
+ if (huart->hdmarx != NULL)\r
+ {\r
+ /* UART Rx DMA Abort callback has already been initialised :\r
+ will lead to call HAL_UART_AbortCpltCallback() at end of DMA abort procedure */\r
+\r
+ /* Abort DMA RX */\r
+ if (HAL_DMA_Abort_IT(huart->hdmarx) != HAL_OK)\r
+ {\r
+ huart->hdmarx->XferAbortCallback = NULL;\r
+ AbortCplt = 0x01U;\r
+ }\r
+ else\r
+ {\r
+ AbortCplt = 0x00U;\r
+ }\r
+ }\r
+ }\r
+\r
+ /* if no DMA abort complete callback execution is required => call user Abort Complete callback */\r
+ if (AbortCplt == 0x01U)\r
+ {\r
+ /* Reset Tx and Rx transfer counters */\r
+ huart->TxXferCount = 0x00U;\r
+ huart->RxXferCount = 0x00U;\r
+\r
+ /* Reset ErrorCode */\r
+ huart->ErrorCode = HAL_UART_ERROR_NONE;\r
+\r
+ /* Restore huart->gState and huart->RxState to Ready */\r
+ huart->gState = HAL_UART_STATE_READY;\r
+ huart->RxState = HAL_UART_STATE_READY;\r
+\r
+ /* As no DMA to be aborted, call directly user Abort complete callback */\r
+#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)\r
+ /* Call registered Abort complete callback */\r
+ huart->AbortCpltCallback(huart);\r
+#else\r
+ /* Call legacy weak Abort complete callback */\r
+ HAL_UART_AbortCpltCallback(huart);\r
+#endif /* USE_HAL_UART_REGISTER_CALLBACKS */\r
+ }\r
+\r
+ return HAL_OK;\r
+}\r
+\r
+/**\r
+ * @brief Abort ongoing Transmit transfer (Interrupt mode).\r
+ * @param huart UART handle.\r
+ * @note This procedure could be used for aborting any ongoing Tx transfer started in Interrupt or DMA mode.\r
+ * This procedure performs following operations :\r
+ * - Disable UART Interrupts (Tx)\r
+ * - Disable the DMA transfer in the peripheral register (if enabled)\r
+ * - Abort DMA transfer by calling HAL_DMA_Abort_IT (in case of transfer in DMA mode)\r
+ * - Set handle State to READY\r
+ * - At abort completion, call user abort complete callback\r
+ * @note This procedure is executed in Interrupt mode, meaning that abort procedure could be\r
+ * considered as completed only when user abort complete callback is executed (not when exiting function).\r
+ * @retval HAL status\r
+*/\r
+HAL_StatusTypeDef HAL_UART_AbortTransmit_IT(UART_HandleTypeDef *huart)\r
+{\r
+ /* Disable TXEIE and TCIE interrupts */\r
+ CLEAR_BIT(huart->Instance->CR1, (USART_CR1_TXEIE | USART_CR1_TCIE));\r
+\r
+ /* Disable the UART DMA Tx request if enabled */\r
+ if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAT))\r
+ {\r
+ CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAT);\r
+\r
+ /* Abort the UART DMA Tx channel : use blocking DMA Abort API (no callback) */\r
+ if (huart->hdmatx != NULL)\r
+ {\r
+ /* Set the UART DMA Abort callback :\r
+ will lead to call HAL_UART_AbortCpltCallback() at end of DMA abort procedure */\r
+ huart->hdmatx->XferAbortCallback = UART_DMATxOnlyAbortCallback;\r
+\r
+ /* Abort DMA TX */\r
+ if (HAL_DMA_Abort_IT(huart->hdmatx) != HAL_OK)\r
+ {\r
+ /* Call Directly huart->hdmatx->XferAbortCallback function in case of error */\r
+ huart->hdmatx->XferAbortCallback(huart->hdmatx);\r
+ }\r
+ }\r
+ else\r
+ {\r
+ /* Reset Tx transfer counter */\r
+ huart->TxXferCount = 0x00U;\r
+\r
+ /* Restore huart->gState to Ready */\r
+ huart->gState = HAL_UART_STATE_READY;\r
+\r
+ /* As no DMA to be aborted, call directly user Abort complete callback */\r
+#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)\r
+ /* Call registered Abort Transmit Complete Callback */\r
+ huart->AbortTransmitCpltCallback(huart);\r
+#else\r
+ /* Call legacy weak Abort Transmit Complete Callback */\r
+ HAL_UART_AbortTransmitCpltCallback(huart);\r
+#endif /* USE_HAL_UART_REGISTER_CALLBACKS */\r
+ }\r
+ }\r
+ else\r
+ {\r
+ /* Reset Tx transfer counter */\r
+ huart->TxXferCount = 0x00U;\r
+\r
+ /* Restore huart->gState to Ready */\r
+ huart->gState = HAL_UART_STATE_READY;\r
+\r
+ /* As no DMA to be aborted, call directly user Abort complete callback */\r
+#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)\r
+ /* Call registered Abort Transmit Complete Callback */\r
+ huart->AbortTransmitCpltCallback(huart);\r
+#else\r
+ /* Call legacy weak Abort Transmit Complete Callback */\r
+ HAL_UART_AbortTransmitCpltCallback(huart);\r
+#endif /* USE_HAL_UART_REGISTER_CALLBACKS */\r
+ }\r
+\r
+ return HAL_OK;\r
+}\r
+\r
+/**\r
+ * @brief Abort ongoing Receive transfer (Interrupt mode).\r
+ * @param huart UART handle.\r
+ * @note This procedure could be used for aborting any ongoing Rx transfer started in Interrupt or DMA mode.\r
+ * This procedure performs following operations :\r
+ * - Disable UART Interrupts (Rx)\r
+ * - Disable the DMA transfer in the peripheral register (if enabled)\r
+ * - Abort DMA transfer by calling HAL_DMA_Abort_IT (in case of transfer in DMA mode)\r
+ * - Set handle State to READY\r
+ * - At abort completion, call user abort complete callback\r
+ * @note This procedure is executed in Interrupt mode, meaning that abort procedure could be\r
+ * considered as completed only when user abort complete callback is executed (not when exiting function).\r
+ * @retval HAL status\r
+*/\r
+HAL_StatusTypeDef HAL_UART_AbortReceive_IT(UART_HandleTypeDef *huart)\r
+{\r
+ /* Disable RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts */\r
+ CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE | USART_CR1_PEIE));\r
+ CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE);\r
+\r
+ /* Disable the UART DMA Rx request if enabled */\r
+ if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR))\r
+ {\r
+ CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAR);\r
+\r
+ /* Abort the UART DMA Rx channel : use blocking DMA Abort API (no callback) */\r
+ if (huart->hdmarx != NULL)\r
+ {\r
+ /* Set the UART DMA Abort callback :\r
+ will lead to call HAL_UART_AbortCpltCallback() at end of DMA abort procedure */\r
+ huart->hdmarx->XferAbortCallback = UART_DMARxOnlyAbortCallback;\r
+\r
+ /* Abort DMA RX */\r
+ if (HAL_DMA_Abort_IT(huart->hdmarx) != HAL_OK)\r
+ {\r
+ /* Call Directly huart->hdmarx->XferAbortCallback function in case of error */\r
+ huart->hdmarx->XferAbortCallback(huart->hdmarx);\r
+ }\r
+ }\r
+ else\r
+ {\r
+ /* Reset Rx transfer counter */\r
+ huart->RxXferCount = 0x00U;\r
+\r
+ /* Restore huart->RxState to Ready */\r
+ huart->RxState = HAL_UART_STATE_READY;\r
+\r
+ /* As no DMA to be aborted, call directly user Abort complete callback */\r
+#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)\r
+ /* Call registered Abort Receive Complete Callback */\r
+ huart->AbortReceiveCpltCallback(huart);\r
+#else\r
+ /* Call legacy weak Abort Receive Complete Callback */\r
+ HAL_UART_AbortReceiveCpltCallback(huart);\r
+#endif /* USE_HAL_UART_REGISTER_CALLBACKS */\r
+ }\r
+ }\r
+ else\r
+ {\r
+ /* Reset Rx transfer counter */\r
+ huart->RxXferCount = 0x00U;\r
+\r
+ /* Restore huart->RxState to Ready */\r
+ huart->RxState = HAL_UART_STATE_READY;\r
+\r
+ /* As no DMA to be aborted, call directly user Abort complete callback */\r
+#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)\r
+ /* Call registered Abort Receive Complete Callback */\r
+ huart->AbortReceiveCpltCallback(huart);\r
+#else\r
+ /* Call legacy weak Abort Receive Complete Callback */\r
+ HAL_UART_AbortReceiveCpltCallback(huart);\r
+#endif /* USE_HAL_UART_REGISTER_CALLBACKS */\r
+ }\r
+\r
+ return HAL_OK;\r
+}\r
+\r
+/**\r
+ * @brief This function handles UART interrupt request.\r
+ * @param huart Pointer to a UART_HandleTypeDef structure that contains\r
+ * the configuration information for the specified UART module.\r
+ * @retval None\r
+ */\r
+void HAL_UART_IRQHandler(UART_HandleTypeDef *huart)\r
+{\r
+ uint32_t isrflags = READ_REG(huart->Instance->SR);\r
+ uint32_t cr1its = READ_REG(huart->Instance->CR1);\r
+ uint32_t cr3its = READ_REG(huart->Instance->CR3);\r
+ uint32_t errorflags = 0x00U;\r
+ uint32_t dmarequest = 0x00U;\r
+\r
+ /* If no error occurs */\r
+ errorflags = (isrflags & (uint32_t)(USART_SR_PE | USART_SR_FE | USART_SR_ORE | USART_SR_NE));\r
+ if (errorflags == RESET)\r
+ {\r
+ /* UART in mode Receiver -------------------------------------------------*/\r
+ if (((isrflags & USART_SR_RXNE) != RESET) && ((cr1its & USART_CR1_RXNEIE) != RESET))\r
+ {\r
+ UART_Receive_IT(huart);\r
+ return;\r
+ }\r
+ }\r
+\r
+ /* If some errors occur */\r
+ if ((errorflags != RESET) && (((cr3its & USART_CR3_EIE) != RESET) || ((cr1its & (USART_CR1_RXNEIE | USART_CR1_PEIE)) != RESET)))\r
+ {\r
+ /* UART parity error interrupt occurred ----------------------------------*/\r
+ if (((isrflags & USART_SR_PE) != RESET) && ((cr1its & USART_CR1_PEIE) != RESET))\r
+ {\r
+ huart->ErrorCode |= HAL_UART_ERROR_PE;\r
+ }\r
+\r
+ /* UART noise error interrupt occurred -----------------------------------*/\r
+ if (((isrflags & USART_SR_NE) != RESET) && ((cr3its & USART_CR3_EIE) != RESET))\r
+ {\r
+ huart->ErrorCode |= HAL_UART_ERROR_NE;\r
+ }\r
+\r
+ /* UART frame error interrupt occurred -----------------------------------*/\r
+ if (((isrflags & USART_SR_FE) != RESET) && ((cr3its & USART_CR3_EIE) != RESET))\r
+ {\r
+ huart->ErrorCode |= HAL_UART_ERROR_FE;\r
+ }\r
+\r
+ /* UART Over-Run interrupt occurred --------------------------------------*/\r
+ if (((isrflags & USART_SR_ORE) != RESET) && ((cr3its & USART_CR3_EIE) != RESET))\r
+ {\r
+ huart->ErrorCode |= HAL_UART_ERROR_ORE;\r
+ }\r
+\r
+ /* Call UART Error Call back function if need be --------------------------*/\r
+ if (huart->ErrorCode != HAL_UART_ERROR_NONE)\r
+ {\r
+ /* UART in mode Receiver -----------------------------------------------*/\r
+ if (((isrflags & USART_SR_RXNE) != RESET) && ((cr1its & USART_CR1_RXNEIE) != RESET))\r
+ {\r
+ UART_Receive_IT(huart);\r
+ }\r
+\r
+ /* If Overrun error occurs, or if any error occurs in DMA mode reception,\r
+ consider error as blocking */\r
+ dmarequest = HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR);\r
+ if (((huart->ErrorCode & HAL_UART_ERROR_ORE) != RESET) || dmarequest)\r
+ {\r
+ /* Blocking error : transfer is aborted\r
+ Set the UART state ready to be able to start again the process,\r
+ Disable Rx Interrupts, and disable Rx DMA request, if ongoing */\r
+ UART_EndRxTransfer(huart);\r
+\r
+ /* Disable the UART DMA Rx request if enabled */\r
+ if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR))\r
+ {\r
+ CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAR);\r
+\r
+ /* Abort the UART DMA Rx channel */\r
+ if (huart->hdmarx != NULL)\r
+ {\r
+ /* Set the UART DMA Abort callback :\r
+ will lead to call HAL_UART_ErrorCallback() at end of DMA abort procedure */\r
+ huart->hdmarx->XferAbortCallback = UART_DMAAbortOnError;\r
+ if (HAL_DMA_Abort_IT(huart->hdmarx) != HAL_OK)\r
+ {\r
+ /* Call Directly XferAbortCallback function in case of error */\r
+ huart->hdmarx->XferAbortCallback(huart->hdmarx);\r
+ }\r
+ }\r
+ else\r
+ {\r
+ /* Call user error callback */\r
+#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)\r
+ /*Call registered error callback*/\r
+ huart->ErrorCallback(huart);\r
+#else\r
+ /*Call legacy weak error callback*/\r
+ HAL_UART_ErrorCallback(huart);\r
+#endif /* USE_HAL_UART_REGISTER_CALLBACKS */\r
+ }\r
+ }\r
+ else\r
+ {\r
+ /* Call user error callback */\r
+#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)\r
+ /*Call registered error callback*/\r
+ huart->ErrorCallback(huart);\r
+#else\r
+ /*Call legacy weak error callback*/\r
+ HAL_UART_ErrorCallback(huart);\r
+#endif /* USE_HAL_UART_REGISTER_CALLBACKS */\r
+ }\r
+ }\r
+ else\r
+ {\r
+ /* Non Blocking error : transfer could go on.\r
+ Error is notified to user through user error callback */\r
+#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)\r
+ /*Call registered error callback*/\r
+ huart->ErrorCallback(huart);\r
+#else\r
+ /*Call legacy weak error callback*/\r
+ HAL_UART_ErrorCallback(huart);\r
+#endif /* USE_HAL_UART_REGISTER_CALLBACKS */\r
+\r
+ huart->ErrorCode = HAL_UART_ERROR_NONE;\r
+ }\r
+ }\r
+ return;\r
+ } /* End if some error occurs */\r
+\r
+ /* UART in mode Transmitter ------------------------------------------------*/\r
+ if (((isrflags & USART_SR_TXE) != RESET) && ((cr1its & USART_CR1_TXEIE) != RESET))\r
+ {\r
+ UART_Transmit_IT(huart);\r
+ return;\r
+ }\r
+\r
+ /* UART in mode Transmitter end --------------------------------------------*/\r
+ if (((isrflags & USART_SR_TC) != RESET) && ((cr1its & USART_CR1_TCIE) != RESET))\r
+ {\r
+ UART_EndTransmit_IT(huart);\r
+ return;\r
+ }\r
+}\r
+\r
+/**\r
+ * @brief Tx Transfer completed callbacks.\r
+ * @param huart Pointer to a UART_HandleTypeDef structure that contains\r
+ * the configuration information for the specified UART module.\r
+ * @retval None\r
+ */\r
+__weak void HAL_UART_TxCpltCallback(UART_HandleTypeDef *huart)\r
+{\r
+ /* Prevent unused argument(s) compilation warning */\r
+ UNUSED(huart);\r
+ /* NOTE: This function should not be modified, when the callback is needed,\r
+ the HAL_UART_TxCpltCallback could be implemented in the user file\r
+ */\r
+}\r
+\r
+/**\r
+ * @brief Tx Half Transfer completed callbacks.\r
+ * @param huart Pointer to a UART_HandleTypeDef structure that contains\r
+ * the configuration information for the specified UART module.\r
+ * @retval None\r
+ */\r
+__weak void HAL_UART_TxHalfCpltCallback(UART_HandleTypeDef *huart)\r
+{\r
+ /* Prevent unused argument(s) compilation warning */\r
+ UNUSED(huart);\r
+ /* NOTE: This function should not be modified, when the callback is needed,\r
+ the HAL_UART_TxHalfCpltCallback could be implemented in the user file\r
+ */\r
+}\r
+\r
+/**\r
+ * @brief Rx Transfer completed callbacks.\r
+ * @param huart Pointer to a UART_HandleTypeDef structure that contains\r
+ * the configuration information for the specified UART module.\r
+ * @retval None\r
+ */\r
+__weak void HAL_UART_RxCpltCallback(UART_HandleTypeDef *huart)\r
+{\r
+ /* Prevent unused argument(s) compilation warning */\r
+ UNUSED(huart);\r
+ /* NOTE: This function should not be modified, when the callback is needed,\r
+ the HAL_UART_RxCpltCallback could be implemented in the user file\r
+ */\r
+}\r
+\r
+/**\r
+ * @brief Rx Half Transfer completed callbacks.\r
+ * @param huart Pointer to a UART_HandleTypeDef structure that contains\r
+ * the configuration information for the specified UART module.\r
+ * @retval None\r
+ */\r
+__weak void HAL_UART_RxHalfCpltCallback(UART_HandleTypeDef *huart)\r
+{\r
+ /* Prevent unused argument(s) compilation warning */\r
+ UNUSED(huart);\r
+ /* NOTE: This function should not be modified, when the callback is needed,\r
+ the HAL_UART_RxHalfCpltCallback could be implemented in the user file\r
+ */\r
+}\r
+\r
+/**\r
+ * @brief UART error callbacks.\r
+ * @param huart Pointer to a UART_HandleTypeDef structure that contains\r
+ * the configuration information for the specified UART module.\r
+ * @retval None\r
+ */\r
+__weak void HAL_UART_ErrorCallback(UART_HandleTypeDef *huart)\r
+{\r
+ /* Prevent unused argument(s) compilation warning */\r
+ UNUSED(huart);\r
+ /* NOTE: This function should not be modified, when the callback is needed,\r
+ the HAL_UART_ErrorCallback could be implemented in the user file\r
+ */\r
+}\r
+\r
+/**\r
+ * @brief UART Abort Complete callback.\r
+ * @param huart UART handle.\r
+ * @retval None\r
+ */\r
+__weak void HAL_UART_AbortCpltCallback(UART_HandleTypeDef *huart)\r
+{\r
+ /* Prevent unused argument(s) compilation warning */\r
+ UNUSED(huart);\r
+\r
+ /* NOTE : This function should not be modified, when the callback is needed,\r
+ the HAL_UART_AbortCpltCallback can be implemented in the user file.\r
+ */\r
+}\r
+\r
+/**\r
+ * @brief UART Abort Complete callback.\r
+ * @param huart UART handle.\r
+ * @retval None\r
+ */\r
+__weak void HAL_UART_AbortTransmitCpltCallback(UART_HandleTypeDef *huart)\r
+{\r
+ /* Prevent unused argument(s) compilation warning */\r
+ UNUSED(huart);\r
+\r
+ /* NOTE : This function should not be modified, when the callback is needed,\r
+ the HAL_UART_AbortTransmitCpltCallback can be implemented in the user file.\r
+ */\r
+}\r
+\r
+/**\r
+ * @brief UART Abort Receive Complete callback.\r
+ * @param huart UART handle.\r
+ * @retval None\r
+ */\r
+__weak void HAL_UART_AbortReceiveCpltCallback(UART_HandleTypeDef *huart)\r
+{\r
+ /* Prevent unused argument(s) compilation warning */\r
+ UNUSED(huart);\r
+\r
+ /* NOTE : This function should not be modified, when the callback is needed,\r
+ the HAL_UART_AbortReceiveCpltCallback can be implemented in the user file.\r
+ */\r
+}\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup UART_Exported_Functions_Group3 Peripheral Control functions\r
+ * @brief UART control functions\r
+ *\r
+@verbatim\r
+ ==============================================================================\r
+ ##### Peripheral Control functions #####\r
+ ==============================================================================\r
+ [..]\r
+ This subsection provides a set of functions allowing to control the UART:\r
+ (+) HAL_LIN_SendBreak() API can be helpful to transmit the break character.\r
+ (+) HAL_MultiProcessor_EnterMuteMode() API can be helpful to enter the UART in mute mode.\r
+ (+) HAL_MultiProcessor_ExitMuteMode() API can be helpful to exit the UART mute mode by software.\r
+ (+) HAL_HalfDuplex_EnableTransmitter() API to enable the UART transmitter and disables the UART receiver in Half Duplex mode\r
+ (+) HAL_HalfDuplex_EnableReceiver() API to enable the UART receiver and disables the UART transmitter in Half Duplex mode\r
+\r
+@endverbatim\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @brief Transmits break characters.\r
+ * @param huart Pointer to a UART_HandleTypeDef structure that contains\r
+ * the configuration information for the specified UART module.\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_LIN_SendBreak(UART_HandleTypeDef *huart)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_UART_INSTANCE(huart->Instance));\r
+\r
+ /* Process Locked */\r
+ __HAL_LOCK(huart);\r
+\r
+ huart->gState = HAL_UART_STATE_BUSY;\r
+\r
+ /* Send break characters */\r
+ SET_BIT(huart->Instance->CR1, USART_CR1_SBK);\r
+\r
+ huart->gState = HAL_UART_STATE_READY;\r
+\r
+ /* Process Unlocked */\r
+ __HAL_UNLOCK(huart);\r
+\r
+ return HAL_OK;\r
+}\r
+\r
+/**\r
+ * @brief Enters the UART in mute mode.\r
+ * @param huart Pointer to a UART_HandleTypeDef structure that contains\r
+ * the configuration information for the specified UART module.\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_MultiProcessor_EnterMuteMode(UART_HandleTypeDef *huart)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_UART_INSTANCE(huart->Instance));\r
+\r
+ /* Process Locked */\r
+ __HAL_LOCK(huart);\r
+\r
+ huart->gState = HAL_UART_STATE_BUSY;\r
+\r
+ /* Enable the USART mute mode by setting the RWU bit in the CR1 register */\r
+ SET_BIT(huart->Instance->CR1, USART_CR1_RWU);\r
+\r
+ huart->gState = HAL_UART_STATE_READY;\r
+\r
+ /* Process Unlocked */\r
+ __HAL_UNLOCK(huart);\r
+\r
+ return HAL_OK;\r
+}\r
+\r
+/**\r
+ * @brief Exits the UART mute mode: wake up software.\r
+ * @param huart Pointer to a UART_HandleTypeDef structure that contains\r
+ * the configuration information for the specified UART module.\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_MultiProcessor_ExitMuteMode(UART_HandleTypeDef *huart)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_UART_INSTANCE(huart->Instance));\r
+\r
+ /* Process Locked */\r
+ __HAL_LOCK(huart);\r
+\r
+ huart->gState = HAL_UART_STATE_BUSY;\r
+\r
+ /* Disable the USART mute mode by clearing the RWU bit in the CR1 register */\r
+ CLEAR_BIT(huart->Instance->CR1, USART_CR1_RWU);\r
+\r
+ huart->gState = HAL_UART_STATE_READY;\r
+\r
+ /* Process Unlocked */\r
+ __HAL_UNLOCK(huart);\r
+\r
+ return HAL_OK;\r
+}\r
+\r
+/**\r
+ * @brief Enables the UART transmitter and disables the UART receiver.\r
+ * @param huart Pointer to a UART_HandleTypeDef structure that contains\r
+ * the configuration information for the specified UART module.\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_HalfDuplex_EnableTransmitter(UART_HandleTypeDef *huart)\r
+{\r
+ uint32_t tmpreg = 0x00U;\r
+\r
+ /* Process Locked */\r
+ __HAL_LOCK(huart);\r
+\r
+ huart->gState = HAL_UART_STATE_BUSY;\r
+\r
+ /*-------------------------- USART CR1 Configuration -----------------------*/\r
+ tmpreg = huart->Instance->CR1;\r
+\r
+ /* Clear TE and RE bits */\r
+ tmpreg &= (uint32_t)~((uint32_t)(USART_CR1_TE | USART_CR1_RE));\r
+\r
+ /* Enable the USART's transmit interface by setting the TE bit in the USART CR1 register */\r
+ tmpreg |= (uint32_t)USART_CR1_TE;\r
+\r
+ /* Write to USART CR1 */\r
+ WRITE_REG(huart->Instance->CR1, (uint32_t)tmpreg);\r
+\r
+ huart->gState = HAL_UART_STATE_READY;\r
+\r
+ /* Process Unlocked */\r
+ __HAL_UNLOCK(huart);\r
+\r
+ return HAL_OK;\r
+}\r
+\r
+/**\r
+ * @brief Enables the UART receiver and disables the UART transmitter.\r
+ * @param huart Pointer to a UART_HandleTypeDef structure that contains\r
+ * the configuration information for the specified UART module.\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_HalfDuplex_EnableReceiver(UART_HandleTypeDef *huart)\r
+{\r
+ uint32_t tmpreg = 0x00U;\r
+\r
+ /* Process Locked */\r
+ __HAL_LOCK(huart);\r
+\r
+ huart->gState = HAL_UART_STATE_BUSY;\r
+\r
+ /*-------------------------- USART CR1 Configuration -----------------------*/\r
+ tmpreg = huart->Instance->CR1;\r
+\r
+ /* Clear TE and RE bits */\r
+ tmpreg &= (uint32_t)~((uint32_t)(USART_CR1_TE | USART_CR1_RE));\r
+\r
+ /* Enable the USART's receive interface by setting the RE bit in the USART CR1 register */\r
+ tmpreg |= (uint32_t)USART_CR1_RE;\r
+\r
+ /* Write to USART CR1 */\r
+ WRITE_REG(huart->Instance->CR1, (uint32_t)tmpreg);\r
+\r
+ huart->gState = HAL_UART_STATE_READY;\r
+\r
+ /* Process Unlocked */\r
+ __HAL_UNLOCK(huart);\r
+\r
+ return HAL_OK;\r
+}\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup UART_Exported_Functions_Group4 Peripheral State and Errors functions\r
+ * @brief UART State and Errors functions\r
+ *\r
+@verbatim\r
+ ==============================================================================\r
+ ##### Peripheral State and Errors functions #####\r
+ ==============================================================================\r
+ [..]\r
+ This subsection provides a set of functions allowing to return the State of\r
+ UART communication process, return Peripheral Errors occurred during communication\r
+ process\r
+ (+) HAL_UART_GetState() API can be helpful to check in run-time the state of the UART peripheral.\r
+ (+) HAL_UART_GetError() check in run-time errors that could be occurred during communication.\r
+\r
+@endverbatim\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @brief Returns the UART state.\r
+ * @param huart Pointer to a UART_HandleTypeDef structure that contains\r
+ * the configuration information for the specified UART module.\r
+ * @retval HAL state\r
+ */\r
+HAL_UART_StateTypeDef HAL_UART_GetState(UART_HandleTypeDef *huart)\r
+{\r
+ uint32_t temp1 = 0x00U, temp2 = 0x00U;\r
+ temp1 = huart->gState;\r
+ temp2 = huart->RxState;\r
+\r
+ return (HAL_UART_StateTypeDef)(temp1 | temp2);\r
+}\r
+\r
+/**\r
+ * @brief Return the UART error code\r
+ * @param huart Pointer to a UART_HandleTypeDef structure that contains\r
+ * the configuration information for the specified UART.\r
+ * @retval UART Error Code\r
+ */\r
+uint32_t HAL_UART_GetError(UART_HandleTypeDef *huart)\r
+{\r
+ return huart->ErrorCode;\r
+}\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup UART_Private_Functions UART Private Functions\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @brief Initialize the callbacks to their default values.\r
+ * @param huart UART handle.\r
+ * @retval none\r
+ */\r
+#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)\r
+void UART_InitCallbacksToDefault(UART_HandleTypeDef *huart)\r
+{\r
+ /* Init the UART Callback settings */\r
+ huart->TxHalfCpltCallback = HAL_UART_TxHalfCpltCallback; /* Legacy weak TxHalfCpltCallback */\r
+ huart->TxCpltCallback = HAL_UART_TxCpltCallback; /* Legacy weak TxCpltCallback */\r
+ huart->RxHalfCpltCallback = HAL_UART_RxHalfCpltCallback; /* Legacy weak RxHalfCpltCallback */\r
+ huart->RxCpltCallback = HAL_UART_RxCpltCallback; /* Legacy weak RxCpltCallback */\r
+ huart->ErrorCallback = HAL_UART_ErrorCallback; /* Legacy weak ErrorCallback */\r
+ huart->AbortCpltCallback = HAL_UART_AbortCpltCallback; /* Legacy weak AbortCpltCallback */\r
+ huart->AbortTransmitCpltCallback = HAL_UART_AbortTransmitCpltCallback; /* Legacy weak AbortTransmitCpltCallback */\r
+ huart->AbortReceiveCpltCallback = HAL_UART_AbortReceiveCpltCallback; /* Legacy weak AbortReceiveCpltCallback */\r
+\r
+}\r
+#endif /* USE_HAL_UART_REGISTER_CALLBACKS */\r
+\r
+/**\r
+ * @brief DMA UART transmit process complete callback.\r
+ * @param hdma Pointer to a DMA_HandleTypeDef structure that contains\r
+ * the configuration information for the specified DMA module.\r
+ * @retval None\r
+ */\r
+static void UART_DMATransmitCplt(DMA_HandleTypeDef *hdma)\r
+{\r
+ UART_HandleTypeDef *huart = (UART_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;\r
+ /* DMA Normal mode*/\r
+ if ((hdma->Instance->CCR & DMA_CCR_CIRC) == 0U)\r
+ {\r
+ huart->TxXferCount = 0x00U;\r
+\r
+ /* Disable the DMA transfer for transmit request by setting the DMAT bit\r
+ in the UART CR3 register */\r
+ CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAT);\r
+\r
+ /* Enable the UART Transmit Complete Interrupt */\r
+ SET_BIT(huart->Instance->CR1, USART_CR1_TCIE);\r
+\r
+ }\r
+ /* DMA Circular mode */\r
+ else\r
+ {\r
+#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)\r
+ /*Call registered Tx complete callback*/\r
+ huart->TxCpltCallback(huart);\r
+#else\r
+ /*Call legacy weak Tx complete callback*/\r
+ HAL_UART_TxCpltCallback(huart);\r
+#endif /* USE_HAL_UART_REGISTER_CALLBACKS */\r
+ }\r
+}\r
+\r
+/**\r
+ * @brief DMA UART transmit process half complete callback\r
+ * @param hdma Pointer to a DMA_HandleTypeDef structure that contains\r
+ * the configuration information for the specified DMA module.\r
+ * @retval None\r
+ */\r
+static void UART_DMATxHalfCplt(DMA_HandleTypeDef *hdma)\r
+{\r
+ UART_HandleTypeDef *huart = (UART_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;\r
+\r
+#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)\r
+ /*Call registered Tx complete callback*/\r
+ huart->TxHalfCpltCallback(huart);\r
+#else\r
+ /*Call legacy weak Tx complete callback*/\r
+ HAL_UART_TxHalfCpltCallback(huart);\r
+#endif /* USE_HAL_UART_REGISTER_CALLBACKS */\r
+}\r
+\r
+/**\r
+ * @brief DMA UART receive process complete callback.\r
+ * @param hdma Pointer to a DMA_HandleTypeDef structure that contains\r
+ * the configuration information for the specified DMA module.\r
+ * @retval None\r
+ */\r
+static void UART_DMAReceiveCplt(DMA_HandleTypeDef *hdma)\r
+{\r
+ UART_HandleTypeDef *huart = (UART_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;\r
+ /* DMA Normal mode*/\r
+ if ((hdma->Instance->CCR & DMA_CCR_CIRC) == 0U)\r
+ {\r
+ huart->RxXferCount = 0U;\r
+\r
+ /* Disable RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts */\r
+ CLEAR_BIT(huart->Instance->CR1, USART_CR1_PEIE);\r
+ CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE);\r
+\r
+ /* Disable the DMA transfer for the receiver request by setting the DMAR bit\r
+ in the UART CR3 register */\r
+ CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAR);\r
+\r
+ /* At end of Rx process, restore huart->RxState to Ready */\r
+ huart->RxState = HAL_UART_STATE_READY;\r
+ }\r
+#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)\r
+ /*Call registered Rx complete callback*/\r
+ huart->RxCpltCallback(huart);\r
+#else\r
+ /*Call legacy weak Rx complete callback*/\r
+ HAL_UART_RxCpltCallback(huart);\r
+#endif /* USE_HAL_UART_REGISTER_CALLBACKS */\r
+}\r
+\r
+/**\r
+ * @brief DMA UART receive process half complete callback\r
+ * @param hdma Pointer to a DMA_HandleTypeDef structure that contains\r
+ * the configuration information for the specified DMA module.\r
+ * @retval None\r
+ */\r
+static void UART_DMARxHalfCplt(DMA_HandleTypeDef *hdma)\r
+{\r
+ UART_HandleTypeDef *huart = (UART_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;\r
+\r
+#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)\r
+ /*Call registered Rx Half complete callback*/\r
+ huart->RxHalfCpltCallback(huart);\r
+#else\r
+ /*Call legacy weak Rx Half complete callback*/\r
+ HAL_UART_RxHalfCpltCallback(huart);\r
+#endif /* USE_HAL_UART_REGISTER_CALLBACKS */\r
+}\r
+\r
+/**\r
+ * @brief DMA UART communication error callback.\r
+ * @param hdma Pointer to a DMA_HandleTypeDef structure that contains\r
+ * the configuration information for the specified DMA module.\r
+ * @retval None\r
+ */\r
+static void UART_DMAError(DMA_HandleTypeDef *hdma)\r
+{\r
+ uint32_t dmarequest = 0x00U;\r
+ UART_HandleTypeDef *huart = (UART_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;\r
+\r
+ /* Stop UART DMA Tx request if ongoing */\r
+ dmarequest = HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAT);\r
+ if ((huart->gState == HAL_UART_STATE_BUSY_TX) && dmarequest)\r
+ {\r
+ huart->TxXferCount = 0x00U;\r
+ UART_EndTxTransfer(huart);\r
+ }\r
+\r
+ /* Stop UART DMA Rx request if ongoing */\r
+ dmarequest = HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR);\r
+ if ((huart->RxState == HAL_UART_STATE_BUSY_RX) && dmarequest)\r
+ {\r
+ huart->RxXferCount = 0x00U;\r
+ UART_EndRxTransfer(huart);\r
+ }\r
+\r
+ huart->ErrorCode |= HAL_UART_ERROR_DMA;\r
+#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)\r
+ /*Call registered error callback*/\r
+ huart->ErrorCallback(huart);\r
+#else\r
+ /*Call legacy weak error callback*/\r
+ HAL_UART_ErrorCallback(huart);\r
+#endif /* USE_HAL_UART_REGISTER_CALLBACKS */\r
+}\r
+\r
+/**\r
+ * @brief This function handles UART Communication Timeout.\r
+ * @param huart Pointer to a UART_HandleTypeDef structure that contains\r
+ * the configuration information for the specified UART module.\r
+ * @param Flag specifies the UART flag to check.\r
+ * @param Status The new Flag status (SET or RESET).\r
+ * @param Tickstart Tick start value\r
+ * @param Timeout Timeout duration\r
+ * @retval HAL status\r
+ */\r
+static HAL_StatusTypeDef UART_WaitOnFlagUntilTimeout(UART_HandleTypeDef *huart, uint32_t Flag, FlagStatus Status, uint32_t Tickstart, uint32_t Timeout)\r
+{\r
+ /* Wait until flag is set */\r
+ while ((__HAL_UART_GET_FLAG(huart, Flag) ? SET : RESET) == Status)\r
+ {\r
+ /* Check for the Timeout */\r
+ if (Timeout != HAL_MAX_DELAY)\r
+ {\r
+ if ((Timeout == 0U) || ((HAL_GetTick() - Tickstart) > Timeout))\r
+ {\r
+ /* Disable TXE, RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts for the interrupt process */\r
+ CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE | USART_CR1_PEIE | USART_CR1_TXEIE));\r
+ CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE);\r
+\r
+ huart->gState = HAL_UART_STATE_READY;\r
+ huart->RxState = HAL_UART_STATE_READY;\r
+\r
+ /* Process Unlocked */\r
+ __HAL_UNLOCK(huart);\r
+\r
+ return HAL_TIMEOUT;\r
+ }\r
+ }\r
+ }\r
+ return HAL_OK;\r
+}\r
+\r
+/**\r
+ * @brief End ongoing Tx transfer on UART peripheral (following error detection or Transmit completion).\r
+ * @param huart UART handle.\r
+ * @retval None\r
+ */\r
+static void UART_EndTxTransfer(UART_HandleTypeDef *huart)\r
+{\r
+ /* Disable TXEIE and TCIE interrupts */\r
+ CLEAR_BIT(huart->Instance->CR1, (USART_CR1_TXEIE | USART_CR1_TCIE));\r
+\r
+ /* At end of Tx process, restore huart->gState to Ready */\r
+ huart->gState = HAL_UART_STATE_READY;\r
+}\r
+\r
+/**\r
+ * @brief End ongoing Rx transfer on UART peripheral (following error detection or Reception completion).\r
+ * @param huart UART handle.\r
+ * @retval None\r
+ */\r
+static void UART_EndRxTransfer(UART_HandleTypeDef *huart)\r
+{\r
+ /* Disable RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts */\r
+ CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE | USART_CR1_PEIE));\r
+ CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE);\r
+\r
+ /* At end of Rx process, restore huart->RxState to Ready */\r
+ huart->RxState = HAL_UART_STATE_READY;\r
+}\r
+\r
+/**\r
+ * @brief DMA UART communication abort callback, when initiated by HAL services on Error\r
+ * (To be called at end of DMA Abort procedure following error occurrence).\r
+ * @param hdma Pointer to a DMA_HandleTypeDef structure that contains\r
+ * the configuration information for the specified DMA module.\r
+ * @retval None\r
+ */\r
+static void UART_DMAAbortOnError(DMA_HandleTypeDef *hdma)\r
+{\r
+ UART_HandleTypeDef *huart = (UART_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;\r
+ huart->RxXferCount = 0x00U;\r
+ huart->TxXferCount = 0x00U;\r
+\r
+#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)\r
+ /*Call registered error callback*/\r
+ huart->ErrorCallback(huart);\r
+#else\r
+ /*Call legacy weak error callback*/\r
+ HAL_UART_ErrorCallback(huart);\r
+#endif /* USE_HAL_UART_REGISTER_CALLBACKS */\r
+}\r
+\r
+/**\r
+ * @brief DMA UART Tx communication abort callback, when initiated by user\r
+ * (To be called at end of DMA Tx Abort procedure following user abort request).\r
+ * @note When this callback is executed, User Abort complete call back is called only if no\r
+ * Abort still ongoing for Rx DMA Handle.\r
+ * @param hdma Pointer to a DMA_HandleTypeDef structure that contains\r
+ * the configuration information for the specified DMA module.\r
+ * @retval None\r
+ */\r
+static void UART_DMATxAbortCallback(DMA_HandleTypeDef *hdma)\r
+{\r
+ UART_HandleTypeDef *huart = (UART_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;\r
+\r
+ huart->hdmatx->XferAbortCallback = NULL;\r
+\r
+ /* Check if an Abort process is still ongoing */\r
+ if (huart->hdmarx != NULL)\r
+ {\r
+ if (huart->hdmarx->XferAbortCallback != NULL)\r
+ {\r
+ return;\r
+ }\r
+ }\r
+\r
+ /* No Abort process still ongoing : All DMA channels are aborted, call user Abort Complete callback */\r
+ huart->TxXferCount = 0x00U;\r
+ huart->RxXferCount = 0x00U;\r
+\r
+ /* Reset ErrorCode */\r
+ huart->ErrorCode = HAL_UART_ERROR_NONE;\r
+\r
+ /* Restore huart->gState and huart->RxState to Ready */\r
+ huart->gState = HAL_UART_STATE_READY;\r
+ huart->RxState = HAL_UART_STATE_READY;\r
+\r
+ /* Call user Abort complete callback */\r
+#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)\r
+ /* Call registered Abort complete callback */\r
+ huart->AbortCpltCallback(huart);\r
+#else\r
+ /* Call legacy weak Abort complete callback */\r
+ HAL_UART_AbortCpltCallback(huart);\r
+#endif /* USE_HAL_UART_REGISTER_CALLBACKS */\r
+}\r
+\r
+/**\r
+ * @brief DMA UART Rx communication abort callback, when initiated by user\r
+ * (To be called at end of DMA Rx Abort procedure following user abort request).\r
+ * @note When this callback is executed, User Abort complete call back is called only if no\r
+ * Abort still ongoing for Tx DMA Handle.\r
+ * @param hdma Pointer to a DMA_HandleTypeDef structure that contains\r
+ * the configuration information for the specified DMA module.\r
+ * @retval None\r
+ */\r
+static void UART_DMARxAbortCallback(DMA_HandleTypeDef *hdma)\r
+{\r
+ UART_HandleTypeDef *huart = (UART_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;\r
+\r
+ huart->hdmarx->XferAbortCallback = NULL;\r
+\r
+ /* Check if an Abort process is still ongoing */\r
+ if (huart->hdmatx != NULL)\r
+ {\r
+ if (huart->hdmatx->XferAbortCallback != NULL)\r
+ {\r
+ return;\r
+ }\r
+ }\r
+\r
+ /* No Abort process still ongoing : All DMA channels are aborted, call user Abort Complete callback */\r
+ huart->TxXferCount = 0x00U;\r
+ huart->RxXferCount = 0x00U;\r
+\r
+ /* Reset ErrorCode */\r
+ huart->ErrorCode = HAL_UART_ERROR_NONE;\r
+\r
+ /* Restore huart->gState and huart->RxState to Ready */\r
+ huart->gState = HAL_UART_STATE_READY;\r
+ huart->RxState = HAL_UART_STATE_READY;\r
+\r
+ /* Call user Abort complete callback */\r
+#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)\r
+ /* Call registered Abort complete callback */\r
+ huart->AbortCpltCallback(huart);\r
+#else\r
+ /* Call legacy weak Abort complete callback */\r
+ HAL_UART_AbortCpltCallback(huart);\r
+#endif /* USE_HAL_UART_REGISTER_CALLBACKS */\r
+}\r
+\r
+/**\r
+ * @brief DMA UART Tx communication abort callback, when initiated by user by a call to\r
+ * HAL_UART_AbortTransmit_IT API (Abort only Tx transfer)\r
+ * (This callback is executed at end of DMA Tx Abort procedure following user abort request,\r
+ * and leads to user Tx Abort Complete callback execution).\r
+ * @param hdma Pointer to a DMA_HandleTypeDef structure that contains\r
+ * the configuration information for the specified DMA module.\r
+ * @retval None\r
+ */\r
+static void UART_DMATxOnlyAbortCallback(DMA_HandleTypeDef *hdma)\r
+{\r
+ UART_HandleTypeDef *huart = (UART_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;\r
+\r
+ huart->TxXferCount = 0x00U;\r
+\r
+ /* Restore huart->gState to Ready */\r
+ huart->gState = HAL_UART_STATE_READY;\r
+\r
+ /* Call user Abort complete callback */\r
+#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)\r
+ /* Call registered Abort Transmit Complete Callback */\r
+ huart->AbortTransmitCpltCallback(huart);\r
+#else\r
+ /* Call legacy weak Abort Transmit Complete Callback */\r
+ HAL_UART_AbortTransmitCpltCallback(huart);\r
+#endif /* USE_HAL_UART_REGISTER_CALLBACKS */\r
+}\r
+\r
+/**\r
+ * @brief DMA UART Rx communication abort callback, when initiated by user by a call to\r
+ * HAL_UART_AbortReceive_IT API (Abort only Rx transfer)\r
+ * (This callback is executed at end of DMA Rx Abort procedure following user abort request,\r
+ * and leads to user Rx Abort Complete callback execution).\r
+ * @param hdma Pointer to a DMA_HandleTypeDef structure that contains\r
+ * the configuration information for the specified DMA module.\r
+ * @retval None\r
+ */\r
+static void UART_DMARxOnlyAbortCallback(DMA_HandleTypeDef *hdma)\r
+{\r
+ UART_HandleTypeDef *huart = (UART_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;\r
+\r
+ huart->RxXferCount = 0x00U;\r
+\r
+ /* Restore huart->RxState to Ready */\r
+ huart->RxState = HAL_UART_STATE_READY;\r
+\r
+ /* Call user Abort complete callback */\r
+#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)\r
+ /* Call registered Abort Receive Complete Callback */\r
+ huart->AbortReceiveCpltCallback(huart);\r
+#else\r
+ /* Call legacy weak Abort Receive Complete Callback */\r
+ HAL_UART_AbortReceiveCpltCallback(huart);\r
+#endif /* USE_HAL_UART_REGISTER_CALLBACKS */\r
+}\r
+\r
+/**\r
+ * @brief Sends an amount of data in non blocking mode.\r
+ * @param huart Pointer to a UART_HandleTypeDef structure that contains\r
+ * the configuration information for the specified UART module.\r
+ * @retval HAL status\r
+ */\r
+static HAL_StatusTypeDef UART_Transmit_IT(UART_HandleTypeDef *huart)\r
+{\r
+ uint16_t *tmp;\r
+\r
+ /* Check that a Tx process is ongoing */\r
+ if (huart->gState == HAL_UART_STATE_BUSY_TX)\r
+ {\r
+ if (huart->Init.WordLength == UART_WORDLENGTH_9B)\r
+ {\r
+ tmp = (uint16_t *) huart->pTxBuffPtr;\r
+ huart->Instance->DR = (uint16_t)(*tmp & (uint16_t)0x01FF);\r
+ if (huart->Init.Parity == UART_PARITY_NONE)\r
+ {\r
+ huart->pTxBuffPtr += 2U;\r
+ }\r
+ else\r
+ {\r
+ huart->pTxBuffPtr += 1U;\r
+ }\r
+ }\r
+ else\r
+ {\r
+ huart->Instance->DR = (uint8_t)(*huart->pTxBuffPtr++ & (uint8_t)0x00FF);\r
+ }\r
+\r
+ if (--huart->TxXferCount == 0U)\r
+ {\r
+ /* Disable the UART Transmit Complete Interrupt */\r
+ __HAL_UART_DISABLE_IT(huart, UART_IT_TXE);\r
+\r
+ /* Enable the UART Transmit Complete Interrupt */\r
+ __HAL_UART_ENABLE_IT(huart, UART_IT_TC);\r
+ }\r
+ return HAL_OK;\r
+ }\r
+ else\r
+ {\r
+ return HAL_BUSY;\r
+ }\r
+}\r
+\r
+/**\r
+ * @brief Wraps up transmission in non blocking mode.\r
+ * @param huart Pointer to a UART_HandleTypeDef structure that contains\r
+ * the configuration information for the specified UART module.\r
+ * @retval HAL status\r
+ */\r
+static HAL_StatusTypeDef UART_EndTransmit_IT(UART_HandleTypeDef *huart)\r
+{\r
+ /* Disable the UART Transmit Complete Interrupt */\r
+ __HAL_UART_DISABLE_IT(huart, UART_IT_TC);\r
+\r
+ /* Tx process is ended, restore huart->gState to Ready */\r
+ huart->gState = HAL_UART_STATE_READY;\r
+\r
+#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)\r
+ /*Call registered Tx complete callback*/\r
+ huart->TxCpltCallback(huart);\r
+#else\r
+ /*Call legacy weak Tx complete callback*/\r
+ HAL_UART_TxCpltCallback(huart);\r
+#endif /* USE_HAL_UART_REGISTER_CALLBACKS */\r
+\r
+ return HAL_OK;\r
+}\r
+\r
+/**\r
+ * @brief Receives an amount of data in non blocking mode\r
+ * @param huart Pointer to a UART_HandleTypeDef structure that contains\r
+ * the configuration information for the specified UART module.\r
+ * @retval HAL status\r
+ */\r
+static HAL_StatusTypeDef UART_Receive_IT(UART_HandleTypeDef *huart)\r
+{\r
+ uint16_t *tmp;\r
+\r
+ /* Check that a Rx process is ongoing */\r
+ if (huart->RxState == HAL_UART_STATE_BUSY_RX)\r
+ {\r
+ if (huart->Init.WordLength == UART_WORDLENGTH_9B)\r
+ {\r
+ tmp = (uint16_t *) huart->pRxBuffPtr;\r
+ if (huart->Init.Parity == UART_PARITY_NONE)\r
+ {\r
+ *tmp = (uint16_t)(huart->Instance->DR & (uint16_t)0x01FF);\r
+ huart->pRxBuffPtr += 2U;\r
+ }\r
+ else\r
+ {\r
+ *tmp = (uint16_t)(huart->Instance->DR & (uint16_t)0x00FF);\r
+ huart->pRxBuffPtr += 1U;\r
+ }\r
+ }\r
+ else\r
+ {\r
+ if (huart->Init.Parity == UART_PARITY_NONE)\r
+ {\r
+ *huart->pRxBuffPtr++ = (uint8_t)(huart->Instance->DR & (uint8_t)0x00FF);\r
+ }\r
+ else\r
+ {\r
+ *huart->pRxBuffPtr++ = (uint8_t)(huart->Instance->DR & (uint8_t)0x007F);\r
+ }\r
+ }\r
+\r
+ if (--huart->RxXferCount == 0U)\r
+ {\r
+ /* Disable the UART Data Register not empty Interrupt */\r
+ __HAL_UART_DISABLE_IT(huart, UART_IT_RXNE);\r
+\r
+ /* Disable the UART Parity Error Interrupt */\r
+ __HAL_UART_DISABLE_IT(huart, UART_IT_PE);\r
+\r
+ /* Disable the UART Error Interrupt: (Frame error, noise error, overrun error) */\r
+ __HAL_UART_DISABLE_IT(huart, UART_IT_ERR);\r
+\r
+ /* Rx process is completed, restore huart->RxState to Ready */\r
+ huart->RxState = HAL_UART_STATE_READY;\r
+\r
+#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)\r
+ /*Call registered Rx complete callback*/\r
+ huart->RxCpltCallback(huart);\r
+#else\r
+ /*Call legacy weak Rx complete callback*/\r
+ HAL_UART_RxCpltCallback(huart);\r
+#endif /* USE_HAL_UART_REGISTER_CALLBACKS */\r
+\r
+ return HAL_OK;\r
+ }\r
+ return HAL_OK;\r
+ }\r
+ else\r
+ {\r
+ return HAL_BUSY;\r
+ }\r
+}\r
+\r
+/**\r
+ * @brief Configures the UART peripheral.\r
+ * @param huart Pointer to a UART_HandleTypeDef structure that contains\r
+ * the configuration information for the specified UART module.\r
+ * @retval None\r
+ */\r
+static void UART_SetConfig(UART_HandleTypeDef *huart)\r
+{\r
+ uint32_t tmpreg;\r
+ uint32_t pclk;\r
+\r
+ /* Check the parameters */\r
+ assert_param(IS_UART_BAUDRATE(huart->Init.BaudRate));\r
+ assert_param(IS_UART_STOPBITS(huart->Init.StopBits));\r
+ assert_param(IS_UART_PARITY(huart->Init.Parity));\r
+ assert_param(IS_UART_MODE(huart->Init.Mode));\r
+\r
+ /*-------------------------- USART CR2 Configuration -----------------------*/\r
+ /* Configure the UART Stop Bits: Set STOP[13:12] bits\r
+ according to huart->Init.StopBits value */\r
+ MODIFY_REG(huart->Instance->CR2, USART_CR2_STOP, huart->Init.StopBits);\r
+\r
+ /*-------------------------- USART CR1 Configuration -----------------------*/\r
+ /* Configure the UART Word Length, Parity and mode:\r
+ Set the M bits according to huart->Init.WordLength value\r
+ Set PCE and PS bits according to huart->Init.Parity value\r
+ Set TE and RE bits according to huart->Init.Mode value\r
+ Set OVER8 bit according to huart->Init.OverSampling value */\r
+\r
+ tmpreg = (uint32_t)huart->Init.WordLength | huart->Init.Parity | huart->Init.Mode | huart->Init.OverSampling;\r
+ MODIFY_REG(huart->Instance->CR1,\r
+ (uint32_t)(USART_CR1_M | USART_CR1_PCE | USART_CR1_PS | USART_CR1_TE | USART_CR1_RE | USART_CR1_OVER8),\r
+ tmpreg);\r
+\r
+ /*-------------------------- USART CR3 Configuration -----------------------*/\r
+ /* Configure the UART HFC: Set CTSE and RTSE bits according to huart->Init.HwFlowCtl value */\r
+ MODIFY_REG(huart->Instance->CR3, (USART_CR3_RTSE | USART_CR3_CTSE), huart->Init.HwFlowCtl);\r
+\r
+ /* Check the Over Sampling */\r
+ if(huart->Init.OverSampling == UART_OVERSAMPLING_8)\r
+ {\r
+ /*------- UART-associated USART registers setting : BRR Configuration ------*/\r
+ if((huart->Instance == USART1))\r
+ {\r
+ pclk = HAL_RCC_GetPCLK2Freq();\r
+ huart->Instance->BRR = UART_BRR_SAMPLING8(pclk, huart->Init.BaudRate);\r
+ }\r
+ else\r
+ {\r
+ pclk = HAL_RCC_GetPCLK1Freq();\r
+ huart->Instance->BRR = UART_BRR_SAMPLING8(pclk, huart->Init.BaudRate);\r
+ }\r
+ }\r
+ else\r
+ {\r
+ /*------- UART-associated USART registers setting : BRR Configuration ------*/\r
+ if((huart->Instance == USART1))\r
+ {\r
+ pclk = HAL_RCC_GetPCLK2Freq();\r
+ huart->Instance->BRR = UART_BRR_SAMPLING16(pclk, huart->Init.BaudRate);\r
+ }\r
+ else\r
+ {\r
+ pclk = HAL_RCC_GetPCLK1Freq();\r
+ huart->Instance->BRR = UART_BRR_SAMPLING16(pclk, huart->Init.BaudRate);\r
+ }\r
+ }\r
+}\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+#endif /* HAL_UART_MODULE_ENABLED */\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\r
projects / freertos / commitdiff