Update the RegTest.S file used by several GCC RISC-V demos to ensure correct alignmen...

git-svn-id: https://svn.code.sf.net/p/freertos/code/trunk@2739 1d2547de-c912-0410-9cb9-b8ca96c0e9e2

diff --git a/FreeRTOS/Demo/RISC-V-Qemu-sifive_e-FreedomStudio/full_demo/RegTest.S b/FreeRTOS/Demo/RISC-V-Qemu-sifive_e-FreedomStudio/full_demo/RegTest.S
index 0a5e544b6dd8f817028c7d98f07c72e6bd8c2d76..8eef086e6e266336582269fcaaec7a8c5b904c4a 100644 (file)
--- a/FreeRTOS/Demo/RISC-V-Qemu-sifive_e-FreedomStudio/full_demo/RegTest.S
+++ b/FreeRTOS/Demo/RISC-V-Qemu-sifive_e-FreedomStudio/full_demo/RegTest.S
@@ -38,6 +38,7 @@
  * main_full.c.\r
  */\r
 \r
+.align( 8 )\r
 vRegTest1Implementation:\r
 \r
        /* Fill the core registers with known values. */\r
@@ -144,13 +145,15 @@ reg1_loop:
 reg1_error_loop:\r
        /* Jump here if a register contains an uxpected value.  This stops the loop\r
        counter being incremented so the check task knows an error was found. */\r
-//     ebreak\r
+       ebreak\r
        jal reg1_error_loop\r
 \r
+.align( 16 )\r
 ulRegTest1LoopCounterConst: .word ulRegTest1LoopCounter\r
 \r
 /*-----------------------------------------------------------*/\r
 \r
+.align( 8 )\r
 vRegTest2Implementation:\r
 \r
        /* Fill the core registers with known values. */\r
@@ -254,9 +257,10 @@ Reg2_loop:
 reg2_error_loop:\r
        /* Jump here if a register contains an uxpected value.  This stops the loop\r
        counter being incremented so the check task knows an error was found. */\r
-//     ebreak\r
+       ebreak\r
        jal reg2_error_loop\r
 \r
+.align( 16 )\r
 ulRegTest2LoopCounterConst: .word ulRegTest2LoopCounter\r
 \r
 \r

diff --git a/FreeRTOS/Demo/RISC-V_RV32M1_Vega_GCC_Eclipse/projects/RTOSDemo_ri5cy/full_demo/RegTest.S b/FreeRTOS/Demo/RISC-V_RV32M1_Vega_GCC_Eclipse/projects/RTOSDemo_ri5cy/full_demo/RegTest.S
index b40c18dcf1a03bd196d294c9720e2ce74d296a5f..ca2c01b88f0b4242af588ce6c278d667057fb62d 100644 (file)
--- a/FreeRTOS/Demo/RISC-V_RV32M1_Vega_GCC_Eclipse/projects/RTOSDemo_ri5cy/full_demo/RegTest.S
+++ b/FreeRTOS/Demo/RISC-V_RV32M1_Vega_GCC_Eclipse/projects/RTOSDemo_ri5cy/full_demo/RegTest.S
@@ -47,6 +47,8 @@
  * The register check tasks are described in the comments at the top of\r
  * main_full.c.\r
  */\r
+\r
+.align( 8 )\r
 vRegTest1Implementation:\r
 \r
        /* Fill the additional registers with known values. */\r
@@ -191,10 +193,12 @@ reg1_error_loop:
        ebreak\r
        jal reg1_error_loop\r
 \r
+.align( 16 )\r
 ulRegTest1LoopCounterConst: .word ulRegTest1LoopCounter\r
 \r
 /*-----------------------------------------------------------*/\r
 \r
+.align( 8 )\r
 vRegTest2Implementation:\r
 \r
        /* Fill the additional registers with known values. */\r
@@ -336,6 +340,7 @@ reg2_error_loop:
        ebreak\r
        jal reg2_error_loop\r
 \r
+.align( 16 )\r
 ulRegTest2LoopCounterConst: .word ulRegTest2LoopCounter\r
 \r
 \r

diff --git a/FreeRTOS/Demo/RISC-V_RV32_SiFive_HiFive1_GCC/main.c b/FreeRTOS/Demo/RISC-V_RV32_SiFive_HiFive1_GCC/main.c
index 267ac2841128b847dee144352f113acb8faadca8..18671928332ea7b07153c421a201f40e271ebc67 100644 (file)
--- a/FreeRTOS/Demo/RISC-V_RV32_SiFive_HiFive1_GCC/main.c
+++ b/FreeRTOS/Demo/RISC-V_RV32_SiFive_HiFive1_GCC/main.c
@@ -58,7 +58,7 @@
 \r
 /* Set mainCREATE_SIMPLE_BLINKY_DEMO_ONLY to one to run the simple blinky demo,\r
 or 0 to run the more comprehensive test and demo application. */\r
-#define mainCREATE_SIMPLE_BLINKY_DEMO_ONLY     1\r
+#define mainCREATE_SIMPLE_BLINKY_DEMO_ONLY     0\r
 \r
 /* Index to first HART (there is only one). */\r
 #define mainHART_0             0\r