From: rtel Date: Sun, 30 Dec 2018 23:20:26 +0000 (+0000) Subject: Re-org of RISC-V file structure and naming step 1. X-Git-Tag: V10.2.0~23 X-Git-Url: https://git.sur5r.net/?p=freertos;a=commitdiff_plain;h=8ac2c5cb01b2c5eb89d49528dcc4aefbbcb71d03 Re-org of RISC-V file structure and naming step 1. git-svn-id: https://svn.code.sf.net/p/freertos/code/trunk@2619 1d2547de-c912-0410-9cb9-b8ca96c0e9e2 --- diff --git a/FreeRTOS/Source/portable/GCC/RISC-V-RV32/CLINT_no_extensions/freertos_risc_v_port_specific_extensions.h b/FreeRTOS/Source/portable/GCC/RISC-V-RV32/CLINT_no_extensions/freertos_risc_v_port_specific_extensions.h deleted file mode 100644 index a5544b061..000000000 --- a/FreeRTOS/Source/portable/GCC/RISC-V-RV32/CLINT_no_extensions/freertos_risc_v_port_specific_extensions.h +++ /dev/null @@ -1,76 +0,0 @@ -/* - * FreeRTOS Kernel V10.1.1 - * Copyright (C) 2018 Amazon.com, Inc. or its affiliates. All Rights Reserved. - * - * Permission is hereby granted, free of charge, to any person obtaining a copy of - * this software and associated documentation files (the "Software"), to deal in - * the Software without restriction, including without limitation the rights to - * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of - * the Software, and t - - o permit persons to whom the Software is furnished to do so, - * subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in all - * copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS - * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR - * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER - * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN - * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. - * - * http://www.FreeRTOS.org - * http://aws.amazon.com/freertos - * - * 1 tab == 4 spaces! - */ - -/* - * The FreeRTOS kernel's RISC-V port is split between the the code that is - * common across all currently supported RISC-V chips (implementations of the - * RISC-V ISA), and code which tailors the port to a specific RISC-V chip: - * - * + The code that is common to all RISC-V chips is implemented in - * FreeRTOS\Source\portable\GCC\RISC-V-RV32\portASM.S. There is only one - * portASM.S file because the same file is used no matter which RISC-V chip is - * in use. - * - * + The code that tailors the kernel's RISC-V port to a specific RISC-V - * chip is implemented in freertos_risc_v_port_specific_extensions.h. There - * is one freertos_risc_v_port_specific_extensions.h that can be used with any - * RISC-V chip that both includes a standard CLINT and does not add to the - * base set of RISC-V registers. There are additional - * freertos_risc_v_port_specific_extensions.h files for RISC-V implementations - * that do not include a standard CLINT or do add to the base set of RISC-V - * registers. - * - * CARE MUST BE TAKEN TO INCLDUE THE CORRECT - * freertos_risc_v_port_specific_extensions.h HEADER FILE FOR THE CHIP - * IN USE. To include the correct freertos_risc_v_port_specific_extensions.h - * header file ensure the path to the correct header file is in the assembler's - * include path. - * - * This freertos_risc_v_port_specific_extensions.h is for use on RISC-V chips - * that include a standard CLINT and do not add to the base set of RISC-V - * registers. - * - */ - -#ifndef __FREERTOS_RISC_V_EXTENSIONS_H__ -#define __FREERTOS_RISC_V_EXTENSIONS_H__ - -#define portasmHAS_CLINT 1 -#define portasmADDITIONAL_CONTEXT_SIZE 0 /* Must be even number on 32-bit cores. */ - -.macro portasmSAVE_ADDITIONAL_REGISTERS - /* No additional registers to save, so this macro does nothing. */ - .endm - -/* Restore the additional registers found on the Pulpino. */ -.macro portasmRESTORE_ADDITIONAL_REGISTERS - /* No additional registers to restore, so this macro does nothing. */ - .endm - -#endif /* __FREERTOS_RISC_V_EXTENSIONS_H__ */ diff --git a/FreeRTOS/Source/portable/GCC/RISC-V-RV32/Pulpino_Vega_RV32M1RM/freertos_risc_v_port_specific_extensions.h b/FreeRTOS/Source/portable/GCC/RISC-V-RV32/Pulpino_Vega_RV32M1RM/freertos_risc_v_port_specific_extensions.h deleted file mode 100644 index 5121abab1..000000000 --- a/FreeRTOS/Source/portable/GCC/RISC-V-RV32/Pulpino_Vega_RV32M1RM/freertos_risc_v_port_specific_extensions.h +++ /dev/null @@ -1,110 +0,0 @@ -/* - * FreeRTOS Kernel V10.1.1 - * Copyright (C) 2018 Amazon.com, Inc. or its affiliates. All Rights Reserved. - * - * Permission is hereby granted, free of charge, to any person obtaining a copy of - * this software and associated documentation files (the "Software"), to deal in - * the Software without restriction, including without limitation the rights to - * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of - * the Software, and t - - o permit persons to whom the Software is furnished to do so, - * subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in all - * copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS - * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR - * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER - * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN - * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. - * - * http://www.FreeRTOS.org - * http://aws.amazon.com/freertos - * - * 1 tab == 4 spaces! - */ - -/* - * The FreeRTOS kernel's RISC-V port is split between the the code that is - * common across all currently supported RISC-V chips (implementations of the - * RISC-V ISA), and code which tailors the port to a specific RISC-V chip: - * - * + The code that is common to all RISC-V chips is implemented in - * FreeRTOS\Source\portable\GCC\RISC-V-RV32\portASM.S. There is only one - * portASM.S file because the same file is used no matter which RISC-V chip is - * in use. - * - * + The code that tailors the kernel's RISC-V port to a specific RISC-V - * chip is implemented in freertos_risc_v_port_specific_extensions.h. There - * is one freertos_risc_v_port_specific_extensions.h that can be used with any - * RISC-V chip that both includes a standard CLINT and does not add to the - * base set of RISC-V registers. There are additional - * freertos_risc_v_port_specific_extensions.h files for RISC-V implementations - * that do not include a standard CLINT or do add to the base set of RISC-V - * registers. - * - * CARE MUST BE TAKEN TO INCLDUE THE CORRECT - * freertos_risc_v_port_specific_extensions.h HEADER FILE FOR THE CHIP - * IN USE. To include the correct freertos_risc_v_port_specific_extensions.h - * header file ensure the path to the correct header file is in the assembler's - * include path. - * - * This freertos_risc_v_port_specific_extensions.h is for use with Pulpino Ri5cy - * devices, developed and tested using the Vega board RV32M1RM. - * - */ - -#ifndef __FREERTOS_RISC_V_EXTENSIONS_H__ -#define __FREERTOS_RISC_V_EXTENSIONS_H__ - -#define portasmHAS_CLINT 0 - -/* Constants to define the additional registers found on the Pulpino RI5KY. */ -#define lpstart0 0x7b0 -#define lpend0 0x7b1 -#define lpcount0 0x7b2 -#define lpstart1 0x7b4 -#define lpend1 0x7b5 -#define lpcount1 0x7b6 - -/* Six additional registers to save and restore, as per the #defines above. */ -#define portasmADDITIONAL_CONTEXT_SIZE 6 /* Must be even number on 32-bit cores. */ - -/* Save additional registers found on the Pulpino. */ -.macro portasmSAVE_ADDITIONAL_REGISTERS - addi sp, sp, -(portasmADDITIONAL_CONTEXT_SIZE * portWORD_SIZE) /* Make room for the additional registers. */ - csrr t0, lpstart0 /* Load additional registers into accessable temporary registers. */ - csrr t1, lpend0 - csrr t2, lpcount0 - csrr t3, lpstart1 - csrr t4, lpend1 - csrr t5, lpcount1 - sw t0, 1 * portWORD_SIZE( sp ) - sw t1, 2 * portWORD_SIZE( sp ) - sw t2, 3 * portWORD_SIZE( sp ) - sw t3, 4 * portWORD_SIZE( sp ) - sw t4, 5 * portWORD_SIZE( sp ) - sw t5, 6 * portWORD_SIZE( sp ) - .endm - -/* Restore the additional registers found on the Pulpino. */ -.macro portasmRESTORE_ADDITIONAL_REGISTERS - lw t0, 1 * portWORD_SIZE( sp ) /* Load additional registers into accessable temporary registers. */ - lw t1, 2 * portWORD_SIZE( sp ) - lw t2, 3 * portWORD_SIZE( sp ) - lw t3, 4 * portWORD_SIZE( sp ) - lw t4, 5 * portWORD_SIZE( sp ) - lw t5, 6 * portWORD_SIZE( sp ) - csrw lpstart0, t0 - csrw lpend0, t1 - csrw lpcount0, t2 - csrw lpstart1, t3 - csrw lpend1, t4 - csrw lpcount1, t5 - addi sp, sp, (portasmADDITIONAL_CONTEXT_SIZE * portWORD_SIZE )/* Remove space added for additional registers. */ - .endm - -#endif /* __FREERTOS_RISC_V_EXTENSIONS_H__ */ diff --git a/FreeRTOS/Source/portable/GCC/RISC-V-RV32/chip_specific_extensions/Pulpino_Vega_RV32M1RM/freertos_risc_v_port_specific_extensions.h b/FreeRTOS/Source/portable/GCC/RISC-V-RV32/chip_specific_extensions/Pulpino_Vega_RV32M1RM/freertos_risc_v_port_specific_extensions.h new file mode 100644 index 000000000..5121abab1 --- /dev/null +++ b/FreeRTOS/Source/portable/GCC/RISC-V-RV32/chip_specific_extensions/Pulpino_Vega_RV32M1RM/freertos_risc_v_port_specific_extensions.h @@ -0,0 +1,110 @@ +/* + * FreeRTOS Kernel V10.1.1 + * Copyright (C) 2018 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and t + + o permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * http://www.FreeRTOS.org + * http://aws.amazon.com/freertos + * + * 1 tab == 4 spaces! + */ + +/* + * The FreeRTOS kernel's RISC-V port is split between the the code that is + * common across all currently supported RISC-V chips (implementations of the + * RISC-V ISA), and code which tailors the port to a specific RISC-V chip: + * + * + The code that is common to all RISC-V chips is implemented in + * FreeRTOS\Source\portable\GCC\RISC-V-RV32\portASM.S. There is only one + * portASM.S file because the same file is used no matter which RISC-V chip is + * in use. + * + * + The code that tailors the kernel's RISC-V port to a specific RISC-V + * chip is implemented in freertos_risc_v_port_specific_extensions.h. There + * is one freertos_risc_v_port_specific_extensions.h that can be used with any + * RISC-V chip that both includes a standard CLINT and does not add to the + * base set of RISC-V registers. There are additional + * freertos_risc_v_port_specific_extensions.h files for RISC-V implementations + * that do not include a standard CLINT or do add to the base set of RISC-V + * registers. + * + * CARE MUST BE TAKEN TO INCLDUE THE CORRECT + * freertos_risc_v_port_specific_extensions.h HEADER FILE FOR THE CHIP + * IN USE. To include the correct freertos_risc_v_port_specific_extensions.h + * header file ensure the path to the correct header file is in the assembler's + * include path. + * + * This freertos_risc_v_port_specific_extensions.h is for use with Pulpino Ri5cy + * devices, developed and tested using the Vega board RV32M1RM. + * + */ + +#ifndef __FREERTOS_RISC_V_EXTENSIONS_H__ +#define __FREERTOS_RISC_V_EXTENSIONS_H__ + +#define portasmHAS_CLINT 0 + +/* Constants to define the additional registers found on the Pulpino RI5KY. */ +#define lpstart0 0x7b0 +#define lpend0 0x7b1 +#define lpcount0 0x7b2 +#define lpstart1 0x7b4 +#define lpend1 0x7b5 +#define lpcount1 0x7b6 + +/* Six additional registers to save and restore, as per the #defines above. */ +#define portasmADDITIONAL_CONTEXT_SIZE 6 /* Must be even number on 32-bit cores. */ + +/* Save additional registers found on the Pulpino. */ +.macro portasmSAVE_ADDITIONAL_REGISTERS + addi sp, sp, -(portasmADDITIONAL_CONTEXT_SIZE * portWORD_SIZE) /* Make room for the additional registers. */ + csrr t0, lpstart0 /* Load additional registers into accessable temporary registers. */ + csrr t1, lpend0 + csrr t2, lpcount0 + csrr t3, lpstart1 + csrr t4, lpend1 + csrr t5, lpcount1 + sw t0, 1 * portWORD_SIZE( sp ) + sw t1, 2 * portWORD_SIZE( sp ) + sw t2, 3 * portWORD_SIZE( sp ) + sw t3, 4 * portWORD_SIZE( sp ) + sw t4, 5 * portWORD_SIZE( sp ) + sw t5, 6 * portWORD_SIZE( sp ) + .endm + +/* Restore the additional registers found on the Pulpino. */ +.macro portasmRESTORE_ADDITIONAL_REGISTERS + lw t0, 1 * portWORD_SIZE( sp ) /* Load additional registers into accessable temporary registers. */ + lw t1, 2 * portWORD_SIZE( sp ) + lw t2, 3 * portWORD_SIZE( sp ) + lw t3, 4 * portWORD_SIZE( sp ) + lw t4, 5 * portWORD_SIZE( sp ) + lw t5, 6 * portWORD_SIZE( sp ) + csrw lpstart0, t0 + csrw lpend0, t1 + csrw lpcount0, t2 + csrw lpstart1, t3 + csrw lpend1, t4 + csrw lpcount1, t5 + addi sp, sp, (portasmADDITIONAL_CONTEXT_SIZE * portWORD_SIZE )/* Remove space added for additional registers. */ + .endm + +#endif /* __FREERTOS_RISC_V_EXTENSIONS_H__ */ diff --git a/FreeRTOS/Source/portable/GCC/RISC-V-RV32/freertos_risc_v_port_specific_extensions.h b/FreeRTOS/Source/portable/GCC/RISC-V-RV32/freertos_risc_v_port_specific_extensions.h new file mode 100644 index 000000000..a5544b061 --- /dev/null +++ b/FreeRTOS/Source/portable/GCC/RISC-V-RV32/freertos_risc_v_port_specific_extensions.h @@ -0,0 +1,76 @@ +/* + * FreeRTOS Kernel V10.1.1 + * Copyright (C) 2018 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and t + + o permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * http://www.FreeRTOS.org + * http://aws.amazon.com/freertos + * + * 1 tab == 4 spaces! + */ + +/* + * The FreeRTOS kernel's RISC-V port is split between the the code that is + * common across all currently supported RISC-V chips (implementations of the + * RISC-V ISA), and code which tailors the port to a specific RISC-V chip: + * + * + The code that is common to all RISC-V chips is implemented in + * FreeRTOS\Source\portable\GCC\RISC-V-RV32\portASM.S. There is only one + * portASM.S file because the same file is used no matter which RISC-V chip is + * in use. + * + * + The code that tailors the kernel's RISC-V port to a specific RISC-V + * chip is implemented in freertos_risc_v_port_specific_extensions.h. There + * is one freertos_risc_v_port_specific_extensions.h that can be used with any + * RISC-V chip that both includes a standard CLINT and does not add to the + * base set of RISC-V registers. There are additional + * freertos_risc_v_port_specific_extensions.h files for RISC-V implementations + * that do not include a standard CLINT or do add to the base set of RISC-V + * registers. + * + * CARE MUST BE TAKEN TO INCLDUE THE CORRECT + * freertos_risc_v_port_specific_extensions.h HEADER FILE FOR THE CHIP + * IN USE. To include the correct freertos_risc_v_port_specific_extensions.h + * header file ensure the path to the correct header file is in the assembler's + * include path. + * + * This freertos_risc_v_port_specific_extensions.h is for use on RISC-V chips + * that include a standard CLINT and do not add to the base set of RISC-V + * registers. + * + */ + +#ifndef __FREERTOS_RISC_V_EXTENSIONS_H__ +#define __FREERTOS_RISC_V_EXTENSIONS_H__ + +#define portasmHAS_CLINT 1 +#define portasmADDITIONAL_CONTEXT_SIZE 0 /* Must be even number on 32-bit cores. */ + +.macro portasmSAVE_ADDITIONAL_REGISTERS + /* No additional registers to save, so this macro does nothing. */ + .endm + +/* Restore the additional registers found on the Pulpino. */ +.macro portasmRESTORE_ADDITIONAL_REGISTERS + /* No additional registers to restore, so this macro does nothing. */ + .endm + +#endif /* __FREERTOS_RISC_V_EXTENSIONS_H__ */ diff --git a/FreeRTOS/Source/portable/GCC/RISC-V-RV32/readme.txt b/FreeRTOS/Source/portable/GCC/RISC-V-RV32/readme.txt new file mode 100644 index 000000000..db628a412 --- /dev/null +++ b/FreeRTOS/Source/portable/GCC/RISC-V-RV32/readme.txt @@ -0,0 +1,27 @@ + * The FreeRTOS kernel's RISC-V port is split between the the code that is + * common across all currently supported RISC-V chips (implementations of the + * RISC-V ISA), and code which tailors the port to a specific RISC-V chip: + * + * + The code that is common to all RISC-V chips is implemented in + * FreeRTOS\Source\portable\GCC\RISC-V-RV32\portASM.S. There is only one + * portASM.S file because the same file is used no matter which RISC-V chip is + * in use. + * + * + The code that tailors the kernel's RISC-V port to a specific RISC-V + * chip is implemented in freertos_risc_v_port_specific_extensions.h. There + * is one freertos_risc_v_port_specific_extensions.h that can be used with any + * RISC-V chip that both includes a standard CLINT and does not add to the + * base set of RISC-V registers. There are additional + * freertos_risc_v_port_specific_extensions.h files for RISC-V implementations + * that do not include a standard CLINT or do add to the base set of RISC-V + * registers. + * + * CARE MUST BE TAKEN TO INCLDUE THE CORRECT + * freertos_risc_v_port_specific_extensions.h HEADER FILE FOR THE CHIP + * IN USE. To include the correct freertos_risc_v_port_specific_extensions.h + * header file ensure the path to the correct header file is in the assembler's + * include path. + * + * This freertos_risc_v_port_specific_extensions.h is for use on RISC-V chips + * that include a standard CLINT and do not add to the base set of RISC-V + * registers.